drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu.c

   1 /*
   2  * RTL8XXXU mac80211 USB driver
   3  *
   4  * Copyright (c) 2014 - 2015 Jes Sorensen <Jes.Sorensen@redhat.com>
   5  *
   6  * Portions, notably calibration code:
   7  * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
   8  *
   9  * This driver was written as a replacement for the vendor provided
  10  * rtl8723au driver. As the Realtek 8xxx chips are very similar in
  11  * their programming interface, I have started adding support for
  12  * additional 8xxx chips like the 8192cu, 8188cus, etc.
  13  *
  14  * This program is free software; you can redistribute it and/or modify it
  15  * under the terms of version 2 of the GNU General Public License as
  16  * published by the Free Software Foundation.
  17  *
  18  * This program is distributed in the hope that it will be useful, but WITHOUT
  19  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  20  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  21  * more details.
  22  */
  23
  24 #include <linux/init.h>
  25 #include <linux/kernel.h>
  26 #include <linux/sched.h>
  27 #include <linux/errno.h>
  28 #include <linux/slab.h>
  29 #include <linux/module.h>
  30 #include <linux/spinlock.h>
  31 #include <linux/list.h>
  32 #include <linux/usb.h>
  33 #include <linux/netdevice.h>
  34 #include <linux/etherdevice.h>
  35 #include <linux/ethtool.h>
  36 #include <linux/wireless.h>
  37 #include <linux/firmware.h>
  38 #include <linux/moduleparam.h>
  39 #include <net/mac80211.h>
  40 #include "rtl8xxxu.h"
  41 #include "rtl8xxxu_regs.h"
  42
  43 #define DRIVER_NAME "rtl8xxxu"
  44
  45 static int rtl8xxxu_debug;
  46 static bool rtl8xxxu_ht40_2g;
  47
  48 MODULE_AUTHOR("Jes Sorensen <Jes.Sorensen@redhat.com>");
  49 MODULE_DESCRIPTION("RTL8XXXu USB mac80211 Wireless LAN Driver");
  50 MODULE_LICENSE("GPL");
  51 MODULE_FIRMWARE("rtlwifi/rtl8723aufw_A.bin");
  52 MODULE_FIRMWARE("rtlwifi/rtl8723aufw_B.bin");
  53 MODULE_FIRMWARE("rtlwifi/rtl8723aufw_B_NoBT.bin");
  54 MODULE_FIRMWARE("rtlwifi/rtl8192cufw_A.bin");
  55 MODULE_FIRMWARE("rtlwifi/rtl8192cufw_B.bin");
  56 MODULE_FIRMWARE("rtlwifi/rtl8192cufw_TMSC.bin");
  57
  58 module_param_named(debug, rtl8xxxu_debug, int, 0600);
  59 MODULE_PARM_DESC(debug, "Set debug mask");
  60 module_param_named(ht40_2g, rtl8xxxu_ht40_2g, bool, 0600);
  61 MODULE_PARM_DESC(ht40_2g, "Enable HT40 support on the 2.4GHz band");
  62
  63 #define USB_VENDOR_ID_REALTEK           0x0bda
  64 /* Minimum IEEE80211_MAX_FRAME_LEN */
  65 #define RTL_RX_BUFFER_SIZE              IEEE80211_MAX_FRAME_LEN
  66 #define RTL8XXXU_RX_URBS                32
  67 #define RTL8XXXU_RX_URB_PENDING_WATER   8
  68 #define RTL8XXXU_TX_URBS                64
  69 #define RTL8XXXU_TX_URB_LOW_WATER       25
  70 #define RTL8XXXU_TX_URB_HIGH_WATER      32
  71
  72 static int rtl8xxxu_submit_rx_urb(struct rtl8xxxu_priv *priv,
  73                                   struct rtl8xxxu_rx_urb *rx_urb);
  74
  75 static struct ieee80211_rate rtl8xxxu_rates[] = {
  76         { .bitrate = 10, .hw_value = DESC_RATE_1M, .flags = 0 },
  77         { .bitrate = 20, .hw_value = DESC_RATE_2M, .flags = 0 },
  78         { .bitrate = 55, .hw_value = DESC_RATE_5_5M, .flags = 0 },
  79         { .bitrate = 110, .hw_value = DESC_RATE_11M, .flags = 0 },
  80         { .bitrate = 60, .hw_value = DESC_RATE_6M, .flags = 0 },
  81         { .bitrate = 90, .hw_value = DESC_RATE_9M, .flags = 0 },
  82         { .bitrate = 120, .hw_value = DESC_RATE_12M, .flags = 0 },
  83         { .bitrate = 180, .hw_value = DESC_RATE_18M, .flags = 0 },
  84         { .bitrate = 240, .hw_value = DESC_RATE_24M, .flags = 0 },
  85         { .bitrate = 360, .hw_value = DESC_RATE_36M, .flags = 0 },
  86         { .bitrate = 480, .hw_value = DESC_RATE_48M, .flags = 0 },
  87         { .bitrate = 540, .hw_value = DESC_RATE_54M, .flags = 0 },
  88 };
  89
  90 static struct ieee80211_channel rtl8xxxu_channels_2g[] = {
  91         { .band = IEEE80211_BAND_2GHZ, .center_freq = 2412,
  92           .hw_value = 1, .max_power = 30 },
  93         { .band = IEEE80211_BAND_2GHZ, .center_freq = 2417,
  94           .hw_value = 2, .max_power = 30 },
  95         { .band = IEEE80211_BAND_2GHZ, .center_freq = 2422,
  96           .hw_value = 3, .max_power = 30 },
  97         { .band = IEEE80211_BAND_2GHZ, .center_freq = 2427,
  98           .hw_value = 4, .max_power = 30 },
  99         { .band = IEEE80211_BAND_2GHZ, .center_freq = 2432,
 100           .hw_value = 5, .max_power = 30 },
 101         { .band = IEEE80211_BAND_2GHZ, .center_freq = 2437,
 102           .hw_value = 6, .max_power = 30 },
 103         { .band = IEEE80211_BAND_2GHZ, .center_freq = 2442,
 104           .hw_value = 7, .max_power = 30 },
 105         { .band = IEEE80211_BAND_2GHZ, .center_freq = 2447,
 106           .hw_value = 8, .max_power = 30 },
 107         { .band = IEEE80211_BAND_2GHZ, .center_freq = 2452,
 108           .hw_value = 9, .max_power = 30 },
 109         { .band = IEEE80211_BAND_2GHZ, .center_freq = 2457,
 110           .hw_value = 10, .max_power = 30 },
 111         { .band = IEEE80211_BAND_2GHZ, .center_freq = 2462,
 112           .hw_value = 11, .max_power = 30 },
 113         { .band = IEEE80211_BAND_2GHZ, .center_freq = 2467,
 114           .hw_value = 12, .max_power = 30 },
 115         { .band = IEEE80211_BAND_2GHZ, .center_freq = 2472,
 116           .hw_value = 13, .max_power = 30 },
 117         { .band = IEEE80211_BAND_2GHZ, .center_freq = 2484,
 118           .hw_value = 14, .max_power = 30 }
 119 };
 120
 121 static struct ieee80211_supported_band rtl8xxxu_supported_band = {
 122         .channels = rtl8xxxu_channels_2g,
 123         .n_channels = ARRAY_SIZE(rtl8xxxu_channels_2g),
 124         .bitrates = rtl8xxxu_rates,
 125         .n_bitrates = ARRAY_SIZE(rtl8xxxu_rates),
 126 };
 127
 128 static struct rtl8xxxu_reg8val rtl8723a_mac_init_table[] = {
 129         {0x420, 0x80}, {0x423, 0x00}, {0x430, 0x00}, {0x431, 0x00},
 130         {0x432, 0x00}, {0x433, 0x01}, {0x434, 0x04}, {0x435, 0x05},
 131         {0x436, 0x06}, {0x437, 0x07}, {0x438, 0x00}, {0x439, 0x00},
 132         {0x43a, 0x00}, {0x43b, 0x01}, {0x43c, 0x04}, {0x43d, 0x05},
 133         {0x43e, 0x06}, {0x43f, 0x07}, {0x440, 0x5d}, {0x441, 0x01},
 134         {0x442, 0x00}, {0x444, 0x15}, {0x445, 0xf0}, {0x446, 0x0f},
 135         {0x447, 0x00}, {0x458, 0x41}, {0x459, 0xa8}, {0x45a, 0x72},
 136         {0x45b, 0xb9}, {0x460, 0x66}, {0x461, 0x66}, {0x462, 0x08},
 137         {0x463, 0x03}, {0x4c8, 0xff}, {0x4c9, 0x08}, {0x4cc, 0xff},
 138         {0x4cd, 0xff}, {0x4ce, 0x01}, {0x500, 0x26}, {0x501, 0xa2},
 139         {0x502, 0x2f}, {0x503, 0x00}, {0x504, 0x28}, {0x505, 0xa3},
 140         {0x506, 0x5e}, {0x507, 0x00}, {0x508, 0x2b}, {0x509, 0xa4},
 141         {0x50a, 0x5e}, {0x50b, 0x00}, {0x50c, 0x4f}, {0x50d, 0xa4},
 142         {0x50e, 0x00}, {0x50f, 0x00}, {0x512, 0x1c}, {0x514, 0x0a},
 143         {0x515, 0x10}, {0x516, 0x0a}, {0x517, 0x10}, {0x51a, 0x16},
 144         {0x524, 0x0f}, {0x525, 0x4f}, {0x546, 0x40}, {0x547, 0x00},
 145         {0x550, 0x10}, {0x551, 0x10}, {0x559, 0x02}, {0x55a, 0x02},
 146         {0x55d, 0xff}, {0x605, 0x30}, {0x608, 0x0e}, {0x609, 0x2a},
 147         {0x652, 0x20}, {0x63c, 0x0a}, {0x63d, 0x0a}, {0x63e, 0x0e},
 148         {0x63f, 0x0e}, {0x66e, 0x05}, {0x700, 0x21}, {0x701, 0x43},
 149         {0x702, 0x65}, {0x703, 0x87}, {0x708, 0x21}, {0x709, 0x43},
 150         {0x70a, 0x65}, {0x70b, 0x87}, {0xffff, 0xff},
 151 };
 152
 153 static struct rtl8xxxu_reg32val rtl8723a_phy_1t_init_table[] = {
 154         {0x800, 0x80040000}, {0x804, 0x00000003},
 155         {0x808, 0x0000fc00}, {0x80c, 0x0000000a},
 156         {0x810, 0x10001331}, {0x814, 0x020c3d10},
 157         {0x818, 0x02200385}, {0x81c, 0x00000000},
 158         {0x820, 0x01000100}, {0x824, 0x00390004},
 159         {0x828, 0x00000000}, {0x82c, 0x00000000},
 160         {0x830, 0x00000000}, {0x834, 0x00000000},
 161         {0x838, 0x00000000}, {0x83c, 0x00000000},
 162         {0x840, 0x00010000}, {0x844, 0x00000000},
 163         {0x848, 0x00000000}, {0x84c, 0x00000000},
 164         {0x850, 0x00000000}, {0x854, 0x00000000},
 165         {0x858, 0x569a569a}, {0x85c, 0x001b25a4},
 166         {0x860, 0x66f60110}, {0x864, 0x061f0130},
 167         {0x868, 0x00000000}, {0x86c, 0x32323200},
 168         {0x870, 0x07000760}, {0x874, 0x22004000},
 169         {0x878, 0x00000808}, {0x87c, 0x00000000},
 170         {0x880, 0xc0083070}, {0x884, 0x000004d5},
 171         {0x888, 0x00000000}, {0x88c, 0xccc000c0},
 172         {0x890, 0x00000800}, {0x894, 0xfffffffe},
 173         {0x898, 0x40302010}, {0x89c, 0x00706050},
 174         {0x900, 0x00000000}, {0x904, 0x00000023},
 175         {0x908, 0x00000000}, {0x90c, 0x81121111},
 176         {0xa00, 0x00d047c8}, {0xa04, 0x80ff000c},
 177         {0xa08, 0x8c838300}, {0xa0c, 0x2e68120f},
 178         {0xa10, 0x9500bb78}, {0xa14, 0x11144028},
 179         {0xa18, 0x00881117}, {0xa1c, 0x89140f00},
 180         {0xa20, 0x1a1b0000}, {0xa24, 0x090e1317},
 181         {0xa28, 0x00000204}, {0xa2c, 0x00d30000},
 182         {0xa70, 0x101fbf00}, {0xa74, 0x00000007},
 183         {0xa78, 0x00000900},
 184         {0xc00, 0x48071d40}, {0xc04, 0x03a05611},
 185         {0xc08, 0x000000e4}, {0xc0c, 0x6c6c6c6c},
 186         {0xc10, 0x08800000}, {0xc14, 0x40000100},
 187         {0xc18, 0x08800000}, {0xc1c, 0x40000100},
 188         {0xc20, 0x00000000}, {0xc24, 0x00000000},
 189         {0xc28, 0x00000000}, {0xc2c, 0x00000000},
 190         {0xc30, 0x69e9ac44}, {0xc34, 0x469652af},
 191         {0xc38, 0x49795994}, {0xc3c, 0x0a97971c},
 192         {0xc40, 0x1f7c403f}, {0xc44, 0x000100b7},
 193         {0xc48, 0xec020107}, {0xc4c, 0x007f037f},
 194         {0xc50, 0x69543420}, {0xc54, 0x43bc0094},
 195         {0xc58, 0x69543420}, {0xc5c, 0x433c0094},
 196         {0xc60, 0x00000000}, {0xc64, 0x7112848b},
 197         {0xc68, 0x47c00bff}, {0xc6c, 0x00000036},
 198         {0xc70, 0x2c7f000d}, {0xc74, 0x018610db},
 199         {0xc78, 0x0000001f}, {0xc7c, 0x00b91612},
 200         {0xc80, 0x40000100}, {0xc84, 0x20f60000},
 201         {0xc88, 0x40000100}, {0xc8c, 0x20200000},
 202         {0xc90, 0x00121820}, {0xc94, 0x00000000},
 203         {0xc98, 0x00121820}, {0xc9c, 0x00007f7f},
 204         {0xca0, 0x00000000}, {0xca4, 0x00000080},
 205         {0xca8, 0x00000000}, {0xcac, 0x00000000},
 206         {0xcb0, 0x00000000}, {0xcb4, 0x00000000},
 207         {0xcb8, 0x00000000}, {0xcbc, 0x28000000},
 208         {0xcc0, 0x00000000}, {0xcc4, 0x00000000},
 209         {0xcc8, 0x00000000}, {0xccc, 0x00000000},
 210         {0xcd0, 0x00000000}, {0xcd4, 0x00000000},
 211         {0xcd8, 0x64b22427}, {0xcdc, 0x00766932},
 212         {0xce0, 0x00222222}, {0xce4, 0x00000000},
 213         {0xce8, 0x37644302}, {0xcec, 0x2f97d40c},
 214         {0xd00, 0x00080740}, {0xd04, 0x00020401},
 215         {0xd08, 0x0000907f}, {0xd0c, 0x20010201},
 216         {0xd10, 0xa0633333}, {0xd14, 0x3333bc43},
 217         {0xd18, 0x7a8f5b6b}, {0xd2c, 0xcc979975},
 218         {0xd30, 0x00000000}, {0xd34, 0x80608000},
 219         {0xd38, 0x00000000}, {0xd3c, 0x00027293},
 220         {0xd40, 0x00000000}, {0xd44, 0x00000000},
 221         {0xd48, 0x00000000}, {0xd4c, 0x00000000},
 222         {0xd50, 0x6437140a}, {0xd54, 0x00000000},
 223         {0xd58, 0x00000000}, {0xd5c, 0x30032064},
 224         {0xd60, 0x4653de68}, {0xd64, 0x04518a3c},
 225         {0xd68, 0x00002101}, {0xd6c, 0x2a201c16},
 226         {0xd70, 0x1812362e}, {0xd74, 0x322c2220},
 227         {0xd78, 0x000e3c24}, {0xe00, 0x2a2a2a2a},
 228         {0xe04, 0x2a2a2a2a}, {0xe08, 0x03902a2a},
 229         {0xe10, 0x2a2a2a2a}, {0xe14, 0x2a2a2a2a},
 230         {0xe18, 0x2a2a2a2a}, {0xe1c, 0x2a2a2a2a},
 231         {0xe28, 0x00000000}, {0xe30, 0x1000dc1f},
 232         {0xe34, 0x10008c1f}, {0xe38, 0x02140102},
 233         {0xe3c, 0x681604c2}, {0xe40, 0x01007c00},
 234         {0xe44, 0x01004800}, {0xe48, 0xfb000000},
 235         {0xe4c, 0x000028d1}, {0xe50, 0x1000dc1f},
 236         {0xe54, 0x10008c1f}, {0xe58, 0x02140102},
 237         {0xe5c, 0x28160d05}, {0xe60, 0x00000008},
 238         {0xe68, 0x001b25a4}, {0xe6c, 0x631b25a0},
 239         {0xe70, 0x631b25a0}, {0xe74, 0x081b25a0},
 240         {0xe78, 0x081b25a0}, {0xe7c, 0x081b25a0},
 241         {0xe80, 0x081b25a0}, {0xe84, 0x631b25a0},
 242         {0xe88, 0x081b25a0}, {0xe8c, 0x631b25a0},
 243         {0xed0, 0x631b25a0}, {0xed4, 0x631b25a0},
 244         {0xed8, 0x631b25a0}, {0xedc, 0x001b25a0},
 245         {0xee0, 0x001b25a0}, {0xeec, 0x6b1b25a0},
 246         {0xf14, 0x00000003}, {0xf4c, 0x00000000},
 247         {0xf00, 0x00000300},
 248         {0xffff, 0xffffffff},
 249 };
 250
 251 static struct rtl8xxxu_reg32val rtl8192cu_phy_2t_init_table[] = {
 252         {0x024, 0x0011800f}, {0x028, 0x00ffdb83},
 253         {0x800, 0x80040002}, {0x804, 0x00000003},
 254         {0x808, 0x0000fc00}, {0x80c, 0x0000000a},
 255         {0x810, 0x10000330}, {0x814, 0x020c3d10},
 256         {0x818, 0x02200385}, {0x81c, 0x00000000},
 257         {0x820, 0x01000100}, {0x824, 0x00390004},
 258         {0x828, 0x01000100}, {0x82c, 0x00390004},
 259         {0x830, 0x27272727}, {0x834, 0x27272727},
 260         {0x838, 0x27272727}, {0x83c, 0x27272727},
 261         {0x840, 0x00010000}, {0x844, 0x00010000},
 262         {0x848, 0x27272727}, {0x84c, 0x27272727},
 263         {0x850, 0x00000000}, {0x854, 0x00000000},
 264         {0x858, 0x569a569a}, {0x85c, 0x0c1b25a4},
 265         {0x860, 0x66e60230}, {0x864, 0x061f0130},
 266         {0x868, 0x27272727}, {0x86c, 0x2b2b2b27},
 267         {0x870, 0x07000700}, {0x874, 0x22184000},
 268         {0x878, 0x08080808}, {0x87c, 0x00000000},
 269         {0x880, 0xc0083070}, {0x884, 0x000004d5},
 270         {0x888, 0x00000000}, {0x88c, 0xcc0000c0},
 271         {0x890, 0x00000800}, {0x894, 0xfffffffe},
 272         {0x898, 0x40302010}, {0x89c, 0x00706050},
 273         {0x900, 0x00000000}, {0x904, 0x00000023},
 274         {0x908, 0x00000000}, {0x90c, 0x81121313},
 275         {0xa00, 0x00d047c8}, {0xa04, 0x80ff000c},
 276         {0xa08, 0x8c838300}, {0xa0c, 0x2e68120f},
 277         {0xa10, 0x9500bb78}, {0xa14, 0x11144028},
 278         {0xa18, 0x00881117}, {0xa1c, 0x89140f00},
 279         {0xa20, 0x1a1b0000}, {0xa24, 0x090e1317},
 280         {0xa28, 0x00000204}, {0xa2c, 0x00d30000},
 281         {0xa70, 0x101fbf00}, {0xa74, 0x00000007},
 282         {0xc00, 0x48071d40}, {0xc04, 0x03a05633},
 283         {0xc08, 0x000000e4}, {0xc0c, 0x6c6c6c6c},
 284         {0xc10, 0x08800000}, {0xc14, 0x40000100},
 285         {0xc18, 0x08800000}, {0xc1c, 0x40000100},
 286         {0xc20, 0x00000000}, {0xc24, 0x00000000},
 287         {0xc28, 0x00000000}, {0xc2c, 0x00000000},
 288         {0xc30, 0x69e9ac44}, {0xc34, 0x469652cf},
 289         {0xc38, 0x49795994}, {0xc3c, 0x0a97971c},
 290         {0xc40, 0x1f7c403f}, {0xc44, 0x000100b7},
 291         {0xc48, 0xec020107}, {0xc4c, 0x007f037f},
 292         {0xc50, 0x69543420}, {0xc54, 0x43bc0094},
 293         {0xc58, 0x69543420}, {0xc5c, 0x433c0094},
 294         {0xc60, 0x00000000}, {0xc64, 0x5116848b},
 295         {0xc68, 0x47c00bff}, {0xc6c, 0x00000036},
 296         {0xc70, 0x2c7f000d}, {0xc74, 0x2186115b},
 297         {0xc78, 0x0000001f}, {0xc7c, 0x00b99612},
 298         {0xc80, 0x40000100}, {0xc84, 0x20f60000},
 299         {0xc88, 0x40000100}, {0xc8c, 0xa0e40000},
 300         {0xc90, 0x00121820}, {0xc94, 0x00000000},
 301         {0xc98, 0x00121820}, {0xc9c, 0x00007f7f},
 302         {0xca0, 0x00000000}, {0xca4, 0x00000080},
 303         {0xca8, 0x00000000}, {0xcac, 0x00000000},
 304         {0xcb0, 0x00000000}, {0xcb4, 0x00000000},
 305         {0xcb8, 0x00000000}, {0xcbc, 0x28000000},
 306         {0xcc0, 0x00000000}, {0xcc4, 0x00000000},
 307         {0xcc8, 0x00000000}, {0xccc, 0x00000000},
 308         {0xcd0, 0x00000000}, {0xcd4, 0x00000000},
 309         {0xcd8, 0x64b22427}, {0xcdc, 0x00766932},
 310         {0xce0, 0x00222222}, {0xce4, 0x00000000},
 311         {0xce8, 0x37644302}, {0xcec, 0x2f97d40c},
 312         {0xd00, 0x00080740}, {0xd04, 0x00020403},
 313         {0xd08, 0x0000907f}, {0xd0c, 0x20010201},
 314         {0xd10, 0xa0633333}, {0xd14, 0x3333bc43},
 315         {0xd18, 0x7a8f5b6b}, {0xd2c, 0xcc979975},
 316         {0xd30, 0x00000000}, {0xd34, 0x80608000},
 317         {0xd38, 0x00000000}, {0xd3c, 0x00027293},
 318         {0xd40, 0x00000000}, {0xd44, 0x00000000},
 319         {0xd48, 0x00000000}, {0xd4c, 0x00000000},
 320         {0xd50, 0x6437140a}, {0xd54, 0x00000000},
 321         {0xd58, 0x00000000}, {0xd5c, 0x30032064},
 322         {0xd60, 0x4653de68}, {0xd64, 0x04518a3c},
 323         {0xd68, 0x00002101}, {0xd6c, 0x2a201c16},
 324         {0xd70, 0x1812362e}, {0xd74, 0x322c2220},
 325         {0xd78, 0x000e3c24}, {0xe00, 0x2a2a2a2a},
 326         {0xe04, 0x2a2a2a2a}, {0xe08, 0x03902a2a},
 327         {0xe10, 0x2a2a2a2a}, {0xe14, 0x2a2a2a2a},
 328         {0xe18, 0x2a2a2a2a}, {0xe1c, 0x2a2a2a2a},
 329         {0xe28, 0x00000000}, {0xe30, 0x1000dc1f},
 330         {0xe34, 0x10008c1f}, {0xe38, 0x02140102},
 331         {0xe3c, 0x681604c2}, {0xe40, 0x01007c00},
 332         {0xe44, 0x01004800}, {0xe48, 0xfb000000},
 333         {0xe4c, 0x000028d1}, {0xe50, 0x1000dc1f},
 334         {0xe54, 0x10008c1f}, {0xe58, 0x02140102},
 335         {0xe5c, 0x28160d05}, {0xe60, 0x00000010},
 336         {0xe68, 0x001b25a4}, {0xe6c, 0x63db25a4},
 337         {0xe70, 0x63db25a4}, {0xe74, 0x0c1b25a4},
 338         {0xe78, 0x0c1b25a4}, {0xe7c, 0x0c1b25a4},
 339         {0xe80, 0x0c1b25a4}, {0xe84, 0x63db25a4},
 340         {0xe88, 0x0c1b25a4}, {0xe8c, 0x63db25a4},
 341         {0xed0, 0x63db25a4}, {0xed4, 0x63db25a4},
 342         {0xed8, 0x63db25a4}, {0xedc, 0x001b25a4},
 343         {0xee0, 0x001b25a4}, {0xeec, 0x6fdb25a4},
 344         {0xf14, 0x00000003}, {0xf4c, 0x00000000},
 345         {0xf00, 0x00000300},
 346         {0xffff, 0xffffffff},
 347 };
 348
 349 static struct rtl8xxxu_reg32val rtl8188ru_phy_1t_highpa_table[] = {
 350         {0x024, 0x0011800f}, {0x028, 0x00ffdb83},
 351         {0x040, 0x000c0004}, {0x800, 0x80040000},
 352         {0x804, 0x00000001}, {0x808, 0x0000fc00},
 353         {0x80c, 0x0000000a}, {0x810, 0x10005388},
 354         {0x814, 0x020c3d10}, {0x818, 0x02200385},
 355         {0x81c, 0x00000000}, {0x820, 0x01000100},
 356         {0x824, 0x00390204}, {0x828, 0x00000000},
 357         {0x82c, 0x00000000}, {0x830, 0x00000000},
 358         {0x834, 0x00000000}, {0x838, 0x00000000},
 359         {0x83c, 0x00000000}, {0x840, 0x00010000},
 360         {0x844, 0x00000000}, {0x848, 0x00000000},
 361         {0x84c, 0x00000000}, {0x850, 0x00000000},
 362         {0x854, 0x00000000}, {0x858, 0x569a569a},
 363         {0x85c, 0x001b25a4}, {0x860, 0x66e60230},
 364         {0x864, 0x061f0130}, {0x868, 0x00000000},
 365         {0x86c, 0x20202000}, {0x870, 0x03000300},
 366         {0x874, 0x22004000}, {0x878, 0x00000808},
 367         {0x87c, 0x00ffc3f1}, {0x880, 0xc0083070},
 368         {0x884, 0x000004d5}, {0x888, 0x00000000},
 369         {0x88c, 0xccc000c0}, {0x890, 0x00000800},
 370         {0x894, 0xfffffffe}, {0x898, 0x40302010},
 371         {0x89c, 0x00706050}, {0x900, 0x00000000},
 372         {0x904, 0x00000023}, {0x908, 0x00000000},
 373         {0x90c, 0x81121111}, {0xa00, 0x00d047c8},
 374         {0xa04, 0x80ff000c}, {0xa08, 0x8c838300},
 375         {0xa0c, 0x2e68120f}, {0xa10, 0x9500bb78},
 376         {0xa14, 0x11144028}, {0xa18, 0x00881117},
 377         {0xa1c, 0x89140f00}, {0xa20, 0x15160000},
 378         {0xa24, 0x070b0f12}, {0xa28, 0x00000104},
 379         {0xa2c, 0x00d30000}, {0xa70, 0x101fbf00},
 380         {0xa74, 0x00000007}, {0xc00, 0x48071d40},
 381         {0xc04, 0x03a05611}, {0xc08, 0x000000e4},
 382         {0xc0c, 0x6c6c6c6c}, {0xc10, 0x08800000},
 383         {0xc14, 0x40000100}, {0xc18, 0x08800000},
 384         {0xc1c, 0x40000100}, {0xc20, 0x00000000},
 385         {0xc24, 0x00000000}, {0xc28, 0x00000000},
 386         {0xc2c, 0x00000000}, {0xc30, 0x69e9ac44},
 387         {0xc34, 0x469652cf}, {0xc38, 0x49795994},
 388         {0xc3c, 0x0a97971c}, {0xc40, 0x1f7c403f},
 389         {0xc44, 0x000100b7}, {0xc48, 0xec020107},
 390         {0xc4c, 0x007f037f}, {0xc50, 0x6954342e},
 391         {0xc54, 0x43bc0094}, {0xc58, 0x6954342f},
 392         {0xc5c, 0x433c0094}, {0xc60, 0x00000000},
 393         {0xc64, 0x5116848b}, {0xc68, 0x47c00bff},
 394         {0xc6c, 0x00000036}, {0xc70, 0x2c46000d},
 395         {0xc74, 0x018610db}, {0xc78, 0x0000001f},
 396         {0xc7c, 0x00b91612}, {0xc80, 0x24000090},
 397         {0xc84, 0x20f60000}, {0xc88, 0x24000090},
 398         {0xc8c, 0x20200000}, {0xc90, 0x00121820},
 399         {0xc94, 0x00000000}, {0xc98, 0x00121820},
 400         {0xc9c, 0x00007f7f}, {0xca0, 0x00000000},
 401         {0xca4, 0x00000080}, {0xca8, 0x00000000},
 402         {0xcac, 0x00000000}, {0xcb0, 0x00000000},
 403         {0xcb4, 0x00000000}, {0xcb8, 0x00000000},
 404         {0xcbc, 0x28000000}, {0xcc0, 0x00000000},
 405         {0xcc4, 0x00000000}, {0xcc8, 0x00000000},
 406         {0xccc, 0x00000000}, {0xcd0, 0x00000000},
 407         {0xcd4, 0x00000000}, {0xcd8, 0x64b22427},
 408         {0xcdc, 0x00766932}, {0xce0, 0x00222222},
 409         {0xce4, 0x00000000}, {0xce8, 0x37644302},
 410         {0xcec, 0x2f97d40c}, {0xd00, 0x00080740},
 411         {0xd04, 0x00020401}, {0xd08, 0x0000907f},
 412         {0xd0c, 0x20010201}, {0xd10, 0xa0633333},
 413         {0xd14, 0x3333bc43}, {0xd18, 0x7a8f5b6b},
 414         {0xd2c, 0xcc979975}, {0xd30, 0x00000000},
 415         {0xd34, 0x80608000}, {0xd38, 0x00000000},
 416         {0xd3c, 0x00027293}, {0xd40, 0x00000000},
 417         {0xd44, 0x00000000}, {0xd48, 0x00000000},
 418         {0xd4c, 0x00000000}, {0xd50, 0x6437140a},
 419         {0xd54, 0x00000000}, {0xd58, 0x00000000},
 420         {0xd5c, 0x30032064}, {0xd60, 0x4653de68},
 421         {0xd64, 0x04518a3c}, {0xd68, 0x00002101},
 422         {0xd6c, 0x2a201c16}, {0xd70, 0x1812362e},
 423         {0xd74, 0x322c2220}, {0xd78, 0x000e3c24},
 424         {0xe00, 0x24242424}, {0xe04, 0x24242424},
 425         {0xe08, 0x03902024}, {0xe10, 0x24242424},
 426         {0xe14, 0x24242424}, {0xe18, 0x24242424},
 427         {0xe1c, 0x24242424}, {0xe28, 0x00000000},
 428         {0xe30, 0x1000dc1f}, {0xe34, 0x10008c1f},
 429         {0xe38, 0x02140102}, {0xe3c, 0x681604c2},
 430         {0xe40, 0x01007c00}, {0xe44, 0x01004800},
 431         {0xe48, 0xfb000000}, {0xe4c, 0x000028d1},
 432         {0xe50, 0x1000dc1f}, {0xe54, 0x10008c1f},
 433         {0xe58, 0x02140102}, {0xe5c, 0x28160d05},
 434         {0xe60, 0x00000008}, {0xe68, 0x001b25a4},
 435         {0xe6c, 0x631b25a0}, {0xe70, 0x631b25a0},
 436         {0xe74, 0x081b25a0}, {0xe78, 0x081b25a0},
 437         {0xe7c, 0x081b25a0}, {0xe80, 0x081b25a0},
 438         {0xe84, 0x631b25a0}, {0xe88, 0x081b25a0},
 439         {0xe8c, 0x631b25a0}, {0xed0, 0x631b25a0},
 440         {0xed4, 0x631b25a0}, {0xed8, 0x631b25a0},
 441         {0xedc, 0x001b25a0}, {0xee0, 0x001b25a0},
 442         {0xeec, 0x6b1b25a0}, {0xee8, 0x31555448},
 443         {0xf14, 0x00000003}, {0xf4c, 0x00000000},
 444         {0xf00, 0x00000300},
 445         {0xffff, 0xffffffff},
 446 };
 447
 448 static struct rtl8xxxu_reg32val rtl8xxx_agc_standard_table[] = {
 449         {0xc78, 0x7b000001}, {0xc78, 0x7b010001},
 450         {0xc78, 0x7b020001}, {0xc78, 0x7b030001},
 451         {0xc78, 0x7b040001}, {0xc78, 0x7b050001},
 452         {0xc78, 0x7a060001}, {0xc78, 0x79070001},
 453         {0xc78, 0x78080001}, {0xc78, 0x77090001},
 454         {0xc78, 0x760a0001}, {0xc78, 0x750b0001},
 455         {0xc78, 0x740c0001}, {0xc78, 0x730d0001},
 456         {0xc78, 0x720e0001}, {0xc78, 0x710f0001},
 457         {0xc78, 0x70100001}, {0xc78, 0x6f110001},
 458         {0xc78, 0x6e120001}, {0xc78, 0x6d130001},
 459         {0xc78, 0x6c140001}, {0xc78, 0x6b150001},
 460         {0xc78, 0x6a160001}, {0xc78, 0x69170001},
 461         {0xc78, 0x68180001}, {0xc78, 0x67190001},
 462         {0xc78, 0x661a0001}, {0xc78, 0x651b0001},
 463         {0xc78, 0x641c0001}, {0xc78, 0x631d0001},
 464         {0xc78, 0x621e0001}, {0xc78, 0x611f0001},
 465         {0xc78, 0x60200001}, {0xc78, 0x49210001},
 466         {0xc78, 0x48220001}, {0xc78, 0x47230001},
 467         {0xc78, 0x46240001}, {0xc78, 0x45250001},
 468         {0xc78, 0x44260001}, {0xc78, 0x43270001},
 469         {0xc78, 0x42280001}, {0xc78, 0x41290001},
 470         {0xc78, 0x402a0001}, {0xc78, 0x262b0001},
 471         {0xc78, 0x252c0001}, {0xc78, 0x242d0001},
 472         {0xc78, 0x232e0001}, {0xc78, 0x222f0001},
 473         {0xc78, 0x21300001}, {0xc78, 0x20310001},
 474         {0xc78, 0x06320001}, {0xc78, 0x05330001},
 475         {0xc78, 0x04340001}, {0xc78, 0x03350001},
 476         {0xc78, 0x02360001}, {0xc78, 0x01370001},
 477         {0xc78, 0x00380001}, {0xc78, 0x00390001},
 478         {0xc78, 0x003a0001}, {0xc78, 0x003b0001},
 479         {0xc78, 0x003c0001}, {0xc78, 0x003d0001},
 480         {0xc78, 0x003e0001}, {0xc78, 0x003f0001},
 481         {0xc78, 0x7b400001}, {0xc78, 0x7b410001},
 482         {0xc78, 0x7b420001}, {0xc78, 0x7b430001},
 483         {0xc78, 0x7b440001}, {0xc78, 0x7b450001},
 484         {0xc78, 0x7a460001}, {0xc78, 0x79470001},
 485         {0xc78, 0x78480001}, {0xc78, 0x77490001},
 486         {0xc78, 0x764a0001}, {0xc78, 0x754b0001},
 487         {0xc78, 0x744c0001}, {0xc78, 0x734d0001},
 488         {0xc78, 0x724e0001}, {0xc78, 0x714f0001},
 489         {0xc78, 0x70500001}, {0xc78, 0x6f510001},
 490         {0xc78, 0x6e520001}, {0xc78, 0x6d530001},
 491         {0xc78, 0x6c540001}, {0xc78, 0x6b550001},
 492         {0xc78, 0x6a560001}, {0xc78, 0x69570001},
 493         {0xc78, 0x68580001}, {0xc78, 0x67590001},
 494         {0xc78, 0x665a0001}, {0xc78, 0x655b0001},
 495         {0xc78, 0x645c0001}, {0xc78, 0x635d0001},
 496         {0xc78, 0x625e0001}, {0xc78, 0x615f0001},
 497         {0xc78, 0x60600001}, {0xc78, 0x49610001},
 498         {0xc78, 0x48620001}, {0xc78, 0x47630001},
 499         {0xc78, 0x46640001}, {0xc78, 0x45650001},
 500         {0xc78, 0x44660001}, {0xc78, 0x43670001},
 501         {0xc78, 0x42680001}, {0xc78, 0x41690001},
 502         {0xc78, 0x406a0001}, {0xc78, 0x266b0001},
 503         {0xc78, 0x256c0001}, {0xc78, 0x246d0001},
 504         {0xc78, 0x236e0001}, {0xc78, 0x226f0001},
 505         {0xc78, 0x21700001}, {0xc78, 0x20710001},
 506         {0xc78, 0x06720001}, {0xc78, 0x05730001},
 507         {0xc78, 0x04740001}, {0xc78, 0x03750001},
 508         {0xc78, 0x02760001}, {0xc78, 0x01770001},
 509         {0xc78, 0x00780001}, {0xc78, 0x00790001},
 510         {0xc78, 0x007a0001}, {0xc78, 0x007b0001},
 511         {0xc78, 0x007c0001}, {0xc78, 0x007d0001},
 512         {0xc78, 0x007e0001}, {0xc78, 0x007f0001},
 513         {0xc78, 0x3800001e}, {0xc78, 0x3801001e},
 514         {0xc78, 0x3802001e}, {0xc78, 0x3803001e},
 515         {0xc78, 0x3804001e}, {0xc78, 0x3805001e},
 516         {0xc78, 0x3806001e}, {0xc78, 0x3807001e},
 517         {0xc78, 0x3808001e}, {0xc78, 0x3c09001e},
 518         {0xc78, 0x3e0a001e}, {0xc78, 0x400b001e},
 519         {0xc78, 0x440c001e}, {0xc78, 0x480d001e},
 520         {0xc78, 0x4c0e001e}, {0xc78, 0x500f001e},
 521         {0xc78, 0x5210001e}, {0xc78, 0x5611001e},
 522         {0xc78, 0x5a12001e}, {0xc78, 0x5e13001e},
 523         {0xc78, 0x6014001e}, {0xc78, 0x6015001e},
 524         {0xc78, 0x6016001e}, {0xc78, 0x6217001e},
 525         {0xc78, 0x6218001e}, {0xc78, 0x6219001e},
 526         {0xc78, 0x621a001e}, {0xc78, 0x621b001e},
 527         {0xc78, 0x621c001e}, {0xc78, 0x621d001e},
 528         {0xc78, 0x621e001e}, {0xc78, 0x621f001e},
 529         {0xffff, 0xffffffff}
 530 };
 531
 532 static struct rtl8xxxu_reg32val rtl8xxx_agc_highpa_table[] = {
 533         {0xc78, 0x7b000001}, {0xc78, 0x7b010001},
 534         {0xc78, 0x7b020001}, {0xc78, 0x7b030001},
 535         {0xc78, 0x7b040001}, {0xc78, 0x7b050001},
 536         {0xc78, 0x7b060001}, {0xc78, 0x7b070001},
 537         {0xc78, 0x7b080001}, {0xc78, 0x7a090001},
 538         {0xc78, 0x790a0001}, {0xc78, 0x780b0001},
 539         {0xc78, 0x770c0001}, {0xc78, 0x760d0001},
 540         {0xc78, 0x750e0001}, {0xc78, 0x740f0001},
 541         {0xc78, 0x73100001}, {0xc78, 0x72110001},
 542         {0xc78, 0x71120001}, {0xc78, 0x70130001},
 543         {0xc78, 0x6f140001}, {0xc78, 0x6e150001},
 544         {0xc78, 0x6d160001}, {0xc78, 0x6c170001},
 545         {0xc78, 0x6b180001}, {0xc78, 0x6a190001},
 546         {0xc78, 0x691a0001}, {0xc78, 0x681b0001},
 547         {0xc78, 0x671c0001}, {0xc78, 0x661d0001},
 548         {0xc78, 0x651e0001}, {0xc78, 0x641f0001},
 549         {0xc78, 0x63200001}, {0xc78, 0x62210001},
 550         {0xc78, 0x61220001}, {0xc78, 0x60230001},
 551         {0xc78, 0x46240001}, {0xc78, 0x45250001},
 552         {0xc78, 0x44260001}, {0xc78, 0x43270001},
 553         {0xc78, 0x42280001}, {0xc78, 0x41290001},
 554         {0xc78, 0x402a0001}, {0xc78, 0x262b0001},
 555         {0xc78, 0x252c0001}, {0xc78, 0x242d0001},
 556         {0xc78, 0x232e0001}, {0xc78, 0x222f0001},
 557         {0xc78, 0x21300001}, {0xc78, 0x20310001},
 558         {0xc78, 0x06320001}, {0xc78, 0x05330001},
 559         {0xc78, 0x04340001}, {0xc78, 0x03350001},
 560         {0xc78, 0x02360001}, {0xc78, 0x01370001},
 561         {0xc78, 0x00380001}, {0xc78, 0x00390001},
 562         {0xc78, 0x003a0001}, {0xc78, 0x003b0001},
 563         {0xc78, 0x003c0001}, {0xc78, 0x003d0001},
 564         {0xc78, 0x003e0001}, {0xc78, 0x003f0001},
 565         {0xc78, 0x7b400001}, {0xc78, 0x7b410001},
 566         {0xc78, 0x7b420001}, {0xc78, 0x7b430001},
 567         {0xc78, 0x7b440001}, {0xc78, 0x7b450001},
 568         {0xc78, 0x7b460001}, {0xc78, 0x7b470001},
 569         {0xc78, 0x7b480001}, {0xc78, 0x7a490001},
 570         {0xc78, 0x794a0001}, {0xc78, 0x784b0001},
 571         {0xc78, 0x774c0001}, {0xc78, 0x764d0001},
 572         {0xc78, 0x754e0001}, {0xc78, 0x744f0001},
 573         {0xc78, 0x73500001}, {0xc78, 0x72510001},
 574         {0xc78, 0x71520001}, {0xc78, 0x70530001},
 575         {0xc78, 0x6f540001}, {0xc78, 0x6e550001},
 576         {0xc78, 0x6d560001}, {0xc78, 0x6c570001},
 577         {0xc78, 0x6b580001}, {0xc78, 0x6a590001},
 578         {0xc78, 0x695a0001}, {0xc78, 0x685b0001},
 579         {0xc78, 0x675c0001}, {0xc78, 0x665d0001},
 580         {0xc78, 0x655e0001}, {0xc78, 0x645f0001},
 581         {0xc78, 0x63600001}, {0xc78, 0x62610001},
 582         {0xc78, 0x61620001}, {0xc78, 0x60630001},
 583         {0xc78, 0x46640001}, {0xc78, 0x45650001},
 584         {0xc78, 0x44660001}, {0xc78, 0x43670001},
 585         {0xc78, 0x42680001}, {0xc78, 0x41690001},
 586         {0xc78, 0x406a0001}, {0xc78, 0x266b0001},
 587         {0xc78, 0x256c0001}, {0xc78, 0x246d0001},
 588         {0xc78, 0x236e0001}, {0xc78, 0x226f0001},
 589         {0xc78, 0x21700001}, {0xc78, 0x20710001},
 590         {0xc78, 0x06720001}, {0xc78, 0x05730001},
 591         {0xc78, 0x04740001}, {0xc78, 0x03750001},
 592         {0xc78, 0x02760001}, {0xc78, 0x01770001},
 593         {0xc78, 0x00780001}, {0xc78, 0x00790001},
 594         {0xc78, 0x007a0001}, {0xc78, 0x007b0001},
 595         {0xc78, 0x007c0001}, {0xc78, 0x007d0001},
 596         {0xc78, 0x007e0001}, {0xc78, 0x007f0001},
 597         {0xc78, 0x3800001e}, {0xc78, 0x3801001e},
 598         {0xc78, 0x3802001e}, {0xc78, 0x3803001e},
 599         {0xc78, 0x3804001e}, {0xc78, 0x3805001e},
 600         {0xc78, 0x3806001e}, {0xc78, 0x3807001e},
 601         {0xc78, 0x3808001e}, {0xc78, 0x3c09001e},
 602         {0xc78, 0x3e0a001e}, {0xc78, 0x400b001e},
 603         {0xc78, 0x440c001e}, {0xc78, 0x480d001e},
 604         {0xc78, 0x4c0e001e}, {0xc78, 0x500f001e},
 605         {0xc78, 0x5210001e}, {0xc78, 0x5611001e},
 606         {0xc78, 0x5a12001e}, {0xc78, 0x5e13001e},
 607         {0xc78, 0x6014001e}, {0xc78, 0x6015001e},
 608         {0xc78, 0x6016001e}, {0xc78, 0x6217001e},
 609         {0xc78, 0x6218001e}, {0xc78, 0x6219001e},
 610         {0xc78, 0x621a001e}, {0xc78, 0x621b001e},
 611         {0xc78, 0x621c001e}, {0xc78, 0x621d001e},
 612         {0xc78, 0x621e001e}, {0xc78, 0x621f001e},
 613         {0xffff, 0xffffffff}
 614 };
 615
 616 static struct rtl8xxxu_rfregval rtl8723au_radioa_1t_init_table[] = {
 617         {0x00, 0x00030159}, {0x01, 0x00031284},
 618         {0x02, 0x00098000}, {0x03, 0x00039c63},
 619         {0x04, 0x000210e7}, {0x09, 0x0002044f},
 620         {0x0a, 0x0001a3f1}, {0x0b, 0x00014787},
 621         {0x0c, 0x000896fe}, {0x0d, 0x0000e02c},
 622         {0x0e, 0x00039ce7}, {0x0f, 0x00000451},
 623         {0x19, 0x00000000}, {0x1a, 0x00030355},
 624         {0x1b, 0x00060a00}, {0x1c, 0x000fc378},
 625         {0x1d, 0x000a1250}, {0x1e, 0x0000024f},
 626         {0x1f, 0x00000000}, {0x20, 0x0000b614},
 627         {0x21, 0x0006c000}, {0x22, 0x00000000},
 628         {0x23, 0x00001558}, {0x24, 0x00000060},
 629         {0x25, 0x00000483}, {0x26, 0x0004f000},
 630         {0x27, 0x000ec7d9}, {0x28, 0x00057730},
 631         {0x29, 0x00004783}, {0x2a, 0x00000001},
 632         {0x2b, 0x00021334}, {0x2a, 0x00000000},
 633         {0x2b, 0x00000054}, {0x2a, 0x00000001},
 634         {0x2b, 0x00000808}, {0x2b, 0x00053333},
 635         {0x2c, 0x0000000c}, {0x2a, 0x00000002},
 636         {0x2b, 0x00000808}, {0x2b, 0x0005b333},
 637         {0x2c, 0x0000000d}, {0x2a, 0x00000003},
 638         {0x2b, 0x00000808}, {0x2b, 0x00063333},
 639         {0x2c, 0x0000000d}, {0x2a, 0x00000004},
 640         {0x2b, 0x00000808}, {0x2b, 0x0006b333},
 641         {0x2c, 0x0000000d}, {0x2a, 0x00000005},
 642         {0x2b, 0x00000808}, {0x2b, 0x00073333},
 643         {0x2c, 0x0000000d}, {0x2a, 0x00000006},
 644         {0x2b, 0x00000709}, {0x2b, 0x0005b333},
 645         {0x2c, 0x0000000d}, {0x2a, 0x00000007},
 646         {0x2b, 0x00000709}, {0x2b, 0x00063333},
 647         {0x2c, 0x0000000d}, {0x2a, 0x00000008},
 648         {0x2b, 0x0000060a}, {0x2b, 0x0004b333},
 649         {0x2c, 0x0000000d}, {0x2a, 0x00000009},
 650         {0x2b, 0x0000060a}, {0x2b, 0x00053333},
 651         {0x2c, 0x0000000d}, {0x2a, 0x0000000a},
 652         {0x2b, 0x0000060a}, {0x2b, 0x0005b333},
 653         {0x2c, 0x0000000d}, {0x2a, 0x0000000b},
 654         {0x2b, 0x0000060a}, {0x2b, 0x00063333},
 655         {0x2c, 0x0000000d}, {0x2a, 0x0000000c},
 656         {0x2b, 0x0000060a}, {0x2b, 0x0006b333},
 657         {0x2c, 0x0000000d}, {0x2a, 0x0000000d},
 658         {0x2b, 0x0000060a}, {0x2b, 0x00073333},
 659         {0x2c, 0x0000000d}, {0x2a, 0x0000000e},
 660         {0x2b, 0x0000050b}, {0x2b, 0x00066666},
 661         {0x2c, 0x0000001a}, {0x2a, 0x000e0000},
 662         {0x10, 0x0004000f}, {0x11, 0x000e31fc},
 663         {0x10, 0x0006000f}, {0x11, 0x000ff9f8},
 664         {0x10, 0x0002000f}, {0x11, 0x000203f9},
 665         {0x10, 0x0003000f}, {0x11, 0x000ff500},
 666         {0x10, 0x00000000}, {0x11, 0x00000000},
 667         {0x10, 0x0008000f}, {0x11, 0x0003f100},
 668         {0x10, 0x0009000f}, {0x11, 0x00023100},
 669         {0x12, 0x00032000}, {0x12, 0x00071000},
 670         {0x12, 0x000b0000}, {0x12, 0x000fc000},
 671         {0x13, 0x000287b3}, {0x13, 0x000244b7},
 672         {0x13, 0x000204ab}, {0x13, 0x0001c49f},
 673         {0x13, 0x00018493}, {0x13, 0x0001429b},
 674         {0x13, 0x00010299}, {0x13, 0x0000c29c},
 675         {0x13, 0x000081a0}, {0x13, 0x000040ac},
 676         {0x13, 0x00000020}, {0x14, 0x0001944c},
 677         {0x14, 0x00059444}, {0x14, 0x0009944c},
 678         {0x14, 0x000d9444}, {0x15, 0x0000f474},
 679         {0x15, 0x0004f477}, {0x15, 0x0008f455},
 680         {0x15, 0x000cf455}, {0x16, 0x00000339},
 681         {0x16, 0x00040339}, {0x16, 0x00080339},
 682         {0x16, 0x000c0366}, {0x00, 0x00010159},
 683         {0x18, 0x0000f401}, {0xfe, 0x00000000},
 684         {0xfe, 0x00000000}, {0x1f, 0x00000003},
 685         {0xfe, 0x00000000}, {0xfe, 0x00000000},
 686         {0x1e, 0x00000247}, {0x1f, 0x00000000},
 687         {0x00, 0x00030159},
 688         {0xff, 0xffffffff}
 689 };
 690
 691 static struct rtl8xxxu_rfregval rtl8192cu_radioa_2t_init_table[] = {
 692         {0x00, 0x00030159}, {0x01, 0x00031284},
 693         {0x02, 0x00098000}, {0x03, 0x00018c63},
 694         {0x04, 0x000210e7}, {0x09, 0x0002044f},
 695         {0x0a, 0x0001adb1}, {0x0b, 0x00054867},
 696         {0x0c, 0x0008992e}, {0x0d, 0x0000e52c},
 697         {0x0e, 0x00039ce7}, {0x0f, 0x00000451},
 698         {0x19, 0x00000000}, {0x1a, 0x00010255},
 699         {0x1b, 0x00060a00}, {0x1c, 0x000fc378},
 700         {0x1d, 0x000a1250}, {0x1e, 0x0004445f},
 701         {0x1f, 0x00080001}, {0x20, 0x0000b614},
 702         {0x21, 0x0006c000}, {0x22, 0x00000000},
 703         {0x23, 0x00001558}, {0x24, 0x00000060},
 704         {0x25, 0x00000483}, {0x26, 0x0004f000},
 705         {0x27, 0x000ec7d9}, {0x28, 0x000577c0},
 706         {0x29, 0x00004783}, {0x2a, 0x00000001},
 707         {0x2b, 0x00021334}, {0x2a, 0x00000000},
 708         {0x2b, 0x00000054}, {0x2a, 0x00000001},
 709         {0x2b, 0x00000808}, {0x2b, 0x00053333},
 710         {0x2c, 0x0000000c}, {0x2a, 0x00000002},
 711         {0x2b, 0x00000808}, {0x2b, 0x0005b333},
 712         {0x2c, 0x0000000d}, {0x2a, 0x00000003},
 713         {0x2b, 0x00000808}, {0x2b, 0x00063333},
 714         {0x2c, 0x0000000d}, {0x2a, 0x00000004},
 715         {0x2b, 0x00000808}, {0x2b, 0x0006b333},
 716         {0x2c, 0x0000000d}, {0x2a, 0x00000005},
 717         {0x2b, 0x00000808}, {0x2b, 0x00073333},
 718         {0x2c, 0x0000000d}, {0x2a, 0x00000006},
 719         {0x2b, 0x00000709}, {0x2b, 0x0005b333},
 720         {0x2c, 0x0000000d}, {0x2a, 0x00000007},
 721         {0x2b, 0x00000709}, {0x2b, 0x00063333},
 722         {0x2c, 0x0000000d}, {0x2a, 0x00000008},
 723         {0x2b, 0x0000060a}, {0x2b, 0x0004b333},
 724         {0x2c, 0x0000000d}, {0x2a, 0x00000009},
 725         {0x2b, 0x0000060a}, {0x2b, 0x00053333},
 726         {0x2c, 0x0000000d}, {0x2a, 0x0000000a},
 727         {0x2b, 0x0000060a}, {0x2b, 0x0005b333},
 728         {0x2c, 0x0000000d}, {0x2a, 0x0000000b},
 729         {0x2b, 0x0000060a}, {0x2b, 0x00063333},
 730         {0x2c, 0x0000000d}, {0x2a, 0x0000000c},
 731         {0x2b, 0x0000060a}, {0x2b, 0x0006b333},
 732         {0x2c, 0x0000000d}, {0x2a, 0x0000000d},
 733         {0x2b, 0x0000060a}, {0x2b, 0x00073333},
 734         {0x2c, 0x0000000d}, {0x2a, 0x0000000e},
 735         {0x2b, 0x0000050b}, {0x2b, 0x00066666},
 736         {0x2c, 0x0000001a}, {0x2a, 0x000e0000},
 737         {0x10, 0x0004000f}, {0x11, 0x000e31fc},
 738         {0x10, 0x0006000f}, {0x11, 0x000ff9f8},
 739         {0x10, 0x0002000f}, {0x11, 0x000203f9},
 740         {0x10, 0x0003000f}, {0x11, 0x000ff500},
 741         {0x10, 0x00000000}, {0x11, 0x00000000},
 742         {0x10, 0x0008000f}, {0x11, 0x0003f100},
 743         {0x10, 0x0009000f}, {0x11, 0x00023100},
 744         {0x12, 0x00032000}, {0x12, 0x00071000},
 745         {0x12, 0x000b0000}, {0x12, 0x000fc000},
 746         {0x13, 0x000287b3}, {0x13, 0x000244b7},
 747         {0x13, 0x000204ab}, {0x13, 0x0001c49f},
 748         {0x13, 0x00018493}, {0x13, 0x0001429b},
 749         {0x13, 0x00010299}, {0x13, 0x0000c29c},
 750         {0x13, 0x000081a0}, {0x13, 0x000040ac},
 751         {0x13, 0x00000020}, {0x14, 0x0001944c},
 752         {0x14, 0x00059444}, {0x14, 0x0009944c},
 753         {0x14, 0x000d9444}, {0x15, 0x0000f424},
 754         {0x15, 0x0004f424}, {0x15, 0x0008f424},
 755         {0x15, 0x000cf424}, {0x16, 0x000e0330},
 756         {0x16, 0x000a0330}, {0x16, 0x00060330},
 757         {0x16, 0x00020330}, {0x00, 0x00010159},
 758         {0x18, 0x0000f401}, {0xfe, 0x00000000},
 759         {0xfe, 0x00000000}, {0x1f, 0x00080003},
 760         {0xfe, 0x00000000}, {0xfe, 0x00000000},
 761         {0x1e, 0x00044457}, {0x1f, 0x00080000},
 762         {0x00, 0x00030159},
 763         {0xff, 0xffffffff}
 764 };
 765
 766 static struct rtl8xxxu_rfregval rtl8192cu_radiob_2t_init_table[] = {
 767         {0x00, 0x00030159}, {0x01, 0x00031284},
 768         {0x02, 0x00098000}, {0x03, 0x00018c63},
 769         {0x04, 0x000210e7}, {0x09, 0x0002044f},
 770         {0x0a, 0x0001adb1}, {0x0b, 0x00054867},
 771         {0x0c, 0x0008992e}, {0x0d, 0x0000e52c},
 772         {0x0e, 0x00039ce7}, {0x0f, 0x00000451},
 773         {0x12, 0x00032000}, {0x12, 0x00071000},
 774         {0x12, 0x000b0000}, {0x12, 0x000fc000},
 775         {0x13, 0x000287af}, {0x13, 0x000244b7},
 776         {0x13, 0x000204ab}, {0x13, 0x0001c49f},
 777         {0x13, 0x00018493}, {0x13, 0x00014297},
 778         {0x13, 0x00010295}, {0x13, 0x0000c298},
 779         {0x13, 0x0000819c}, {0x13, 0x000040a8},
 780         {0x13, 0x0000001c}, {0x14, 0x0001944c},
 781         {0x14, 0x00059444}, {0x14, 0x0009944c},
 782         {0x14, 0x000d9444}, {0x15, 0x0000f424},
 783         {0x15, 0x0004f424}, {0x15, 0x0008f424},
 784         {0x15, 0x000cf424}, {0x16, 0x000e0330},
 785         {0x16, 0x000a0330}, {0x16, 0x00060330},
 786         {0x16, 0x00020330},
 787         {0xff, 0xffffffff}
 788 };
 789
 790 static struct rtl8xxxu_rfregval rtl8192cu_radioa_1t_init_table[] = {
 791         {0x00, 0x00030159}, {0x01, 0x00031284},
 792         {0x02, 0x00098000}, {0x03, 0x00018c63},
 793         {0x04, 0x000210e7}, {0x09, 0x0002044f},
 794         {0x0a, 0x0001adb1}, {0x0b, 0x00054867},
 795         {0x0c, 0x0008992e}, {0x0d, 0x0000e52c},
 796         {0x0e, 0x00039ce7}, {0x0f, 0x00000451},
 797         {0x19, 0x00000000}, {0x1a, 0x00010255},
 798         {0x1b, 0x00060a00}, {0x1c, 0x000fc378},
 799         {0x1d, 0x000a1250}, {0x1e, 0x0004445f},
 800         {0x1f, 0x00080001}, {0x20, 0x0000b614},
 801         {0x21, 0x0006c000}, {0x22, 0x00000000},
 802         {0x23, 0x00001558}, {0x24, 0x00000060},
 803         {0x25, 0x00000483}, {0x26, 0x0004f000},
 804         {0x27, 0x000ec7d9}, {0x28, 0x000577c0},
 805         {0x29, 0x00004783}, {0x2a, 0x00000001},
 806         {0x2b, 0x00021334}, {0x2a, 0x00000000},
 807         {0x2b, 0x00000054}, {0x2a, 0x00000001},
 808         {0x2b, 0x00000808}, {0x2b, 0x00053333},
 809         {0x2c, 0x0000000c}, {0x2a, 0x00000002},
 810         {0x2b, 0x00000808}, {0x2b, 0x0005b333},
 811         {0x2c, 0x0000000d}, {0x2a, 0x00000003},
 812         {0x2b, 0x00000808}, {0x2b, 0x00063333},
 813         {0x2c, 0x0000000d}, {0x2a, 0x00000004},
 814         {0x2b, 0x00000808}, {0x2b, 0x0006b333},
 815         {0x2c, 0x0000000d}, {0x2a, 0x00000005},
 816         {0x2b, 0x00000808}, {0x2b, 0x00073333},
 817         {0x2c, 0x0000000d}, {0x2a, 0x00000006},
 818         {0x2b, 0x00000709}, {0x2b, 0x0005b333},
 819         {0x2c, 0x0000000d}, {0x2a, 0x00000007},
 820         {0x2b, 0x00000709}, {0x2b, 0x00063333},
 821         {0x2c, 0x0000000d}, {0x2a, 0x00000008},
 822         {0x2b, 0x0000060a}, {0x2b, 0x0004b333},
 823         {0x2c, 0x0000000d}, {0x2a, 0x00000009},
 824         {0x2b, 0x0000060a}, {0x2b, 0x00053333},
 825         {0x2c, 0x0000000d}, {0x2a, 0x0000000a},
 826         {0x2b, 0x0000060a}, {0x2b, 0x0005b333},
 827         {0x2c, 0x0000000d}, {0x2a, 0x0000000b},
 828         {0x2b, 0x0000060a}, {0x2b, 0x00063333},
 829         {0x2c, 0x0000000d}, {0x2a, 0x0000000c},
 830         {0x2b, 0x0000060a}, {0x2b, 0x0006b333},
 831         {0x2c, 0x0000000d}, {0x2a, 0x0000000d},
 832         {0x2b, 0x0000060a}, {0x2b, 0x00073333},
 833         {0x2c, 0x0000000d}, {0x2a, 0x0000000e},
 834         {0x2b, 0x0000050b}, {0x2b, 0x00066666},
 835         {0x2c, 0x0000001a}, {0x2a, 0x000e0000},
 836         {0x10, 0x0004000f}, {0x11, 0x000e31fc},
 837         {0x10, 0x0006000f}, {0x11, 0x000ff9f8},
 838         {0x10, 0x0002000f}, {0x11, 0x000203f9},
 839         {0x10, 0x0003000f}, {0x11, 0x000ff500},
 840         {0x10, 0x00000000}, {0x11, 0x00000000},
 841         {0x10, 0x0008000f}, {0x11, 0x0003f100},
 842         {0x10, 0x0009000f}, {0x11, 0x00023100},
 843         {0x12, 0x00032000}, {0x12, 0x00071000},
 844         {0x12, 0x000b0000}, {0x12, 0x000fc000},
 845         {0x13, 0x000287b3}, {0x13, 0x000244b7},
 846         {0x13, 0x000204ab}, {0x13, 0x0001c49f},
 847         {0x13, 0x00018493}, {0x13, 0x0001429b},
 848         {0x13, 0x00010299}, {0x13, 0x0000c29c},
 849         {0x13, 0x000081a0}, {0x13, 0x000040ac},
 850         {0x13, 0x00000020}, {0x14, 0x0001944c},
 851         {0x14, 0x00059444}, {0x14, 0x0009944c},
 852         {0x14, 0x000d9444}, {0x15, 0x0000f405},
 853         {0x15, 0x0004f405}, {0x15, 0x0008f405},
 854         {0x15, 0x000cf405}, {0x16, 0x000e0330},
 855         {0x16, 0x000a0330}, {0x16, 0x00060330},
 856         {0x16, 0x00020330}, {0x00, 0x00010159},
 857         {0x18, 0x0000f401}, {0xfe, 0x00000000},
 858         {0xfe, 0x00000000}, {0x1f, 0x00080003},
 859         {0xfe, 0x00000000}, {0xfe, 0x00000000},
 860         {0x1e, 0x00044457}, {0x1f, 0x00080000},
 861         {0x00, 0x00030159},
 862         {0xff, 0xffffffff}
 863 };
 864
 865 static struct rtl8xxxu_rfregval rtl8188ru_radioa_1t_highpa_table[] = {
 866         {0x00, 0x00030159}, {0x01, 0x00031284},
 867         {0x02, 0x00098000}, {0x03, 0x00018c63},
 868         {0x04, 0x000210e7}, {0x09, 0x0002044f},
 869         {0x0a, 0x0001adb0}, {0x0b, 0x00054867},
 870         {0x0c, 0x0008992e}, {0x0d, 0x0000e529},
 871         {0x0e, 0x00039ce7}, {0x0f, 0x00000451},
 872         {0x19, 0x00000000}, {0x1a, 0x00000255},
 873         {0x1b, 0x00060a00}, {0x1c, 0x000fc378},
 874         {0x1d, 0x000a1250}, {0x1e, 0x0004445f},
 875         {0x1f, 0x00080001}, {0x20, 0x0000b614},
 876         {0x21, 0x0006c000}, {0x22, 0x0000083c},
 877         {0x23, 0x00001558}, {0x24, 0x00000060},
 878         {0x25, 0x00000483}, {0x26, 0x0004f000},
 879         {0x27, 0x000ec7d9}, {0x28, 0x000977c0},
 880         {0x29, 0x00004783}, {0x2a, 0x00000001},
 881         {0x2b, 0x00021334}, {0x2a, 0x00000000},
 882         {0x2b, 0x00000054}, {0x2a, 0x00000001},
 883         {0x2b, 0x00000808}, {0x2b, 0x00053333},
 884         {0x2c, 0x0000000c}, {0x2a, 0x00000002},
 885         {0x2b, 0x00000808}, {0x2b, 0x0005b333},
 886         {0x2c, 0x0000000d}, {0x2a, 0x00000003},
 887         {0x2b, 0x00000808}, {0x2b, 0x00063333},
 888         {0x2c, 0x0000000d}, {0x2a, 0x00000004},
 889         {0x2b, 0x00000808}, {0x2b, 0x0006b333},
 890         {0x2c, 0x0000000d}, {0x2a, 0x00000005},
 891         {0x2b, 0x00000808}, {0x2b, 0x00073333},
 892         {0x2c, 0x0000000d}, {0x2a, 0x00000006},
 893         {0x2b, 0x00000709}, {0x2b, 0x0005b333},
 894         {0x2c, 0x0000000d}, {0x2a, 0x00000007},
 895         {0x2b, 0x00000709}, {0x2b, 0x00063333},
 896         {0x2c, 0x0000000d}, {0x2a, 0x00000008},
 897         {0x2b, 0x0000060a}, {0x2b, 0x0004b333},
 898         {0x2c, 0x0000000d}, {0x2a, 0x00000009},
 899         {0x2b, 0x0000060a}, {0x2b, 0x00053333},
 900         {0x2c, 0x0000000d}, {0x2a, 0x0000000a},
 901         {0x2b, 0x0000060a}, {0x2b, 0x0005b333},
 902         {0x2c, 0x0000000d}, {0x2a, 0x0000000b},
 903         {0x2b, 0x0000060a}, {0x2b, 0x00063333},
 904         {0x2c, 0x0000000d}, {0x2a, 0x0000000c},
 905         {0x2b, 0x0000060a}, {0x2b, 0x0006b333},
 906         {0x2c, 0x0000000d}, {0x2a, 0x0000000d},
 907         {0x2b, 0x0000060a}, {0x2b, 0x00073333},
 908         {0x2c, 0x0000000d}, {0x2a, 0x0000000e},
 909         {0x2b, 0x0000050b}, {0x2b, 0x00066666},
 910         {0x2c, 0x0000001a}, {0x2a, 0x000e0000},
 911         {0x10, 0x0004000f}, {0x11, 0x000e31fc},
 912         {0x10, 0x0006000f}, {0x11, 0x000ff9f8},
 913         {0x10, 0x0002000f}, {0x11, 0x000203f9},
 914         {0x10, 0x0003000f}, {0x11, 0x000ff500},
 915         {0x10, 0x00000000}, {0x11, 0x00000000},
 916         {0x10, 0x0008000f}, {0x11, 0x0003f100},
 917         {0x10, 0x0009000f}, {0x11, 0x00023100},
 918         {0x12, 0x000d8000}, {0x12, 0x00090000},
 919         {0x12, 0x00051000}, {0x12, 0x00012000},
 920         {0x13, 0x00028fb4}, {0x13, 0x00024fa8},
 921         {0x13, 0x000207a4}, {0x13, 0x0001c3b0},
 922         {0x13, 0x000183a4}, {0x13, 0x00014398},
 923         {0x13, 0x000101a4}, {0x13, 0x0000c198},
 924         {0x13, 0x000080a4}, {0x13, 0x00004098},
 925         {0x13, 0x00000000}, {0x14, 0x0001944c},
 926         {0x14, 0x00059444}, {0x14, 0x0009944c},
 927         {0x14, 0x000d9444}, {0x15, 0x0000f405},
 928         {0x15, 0x0004f405}, {0x15, 0x0008f405},
 929         {0x15, 0x000cf405}, {0x16, 0x000e0330},
 930         {0x16, 0x000a0330}, {0x16, 0x00060330},
 931         {0x16, 0x00020330}, {0x00, 0x00010159},
 932         {0x18, 0x0000f401}, {0xfe, 0x00000000},
 933         {0xfe, 0x00000000}, {0x1f, 0x00080003},
 934         {0xfe, 0x00000000}, {0xfe, 0x00000000},
 935         {0x1e, 0x00044457}, {0x1f, 0x00080000},
 936         {0x00, 0x00030159},
 937         {0xff, 0xffffffff}
 938 };
 939
 940 static struct rtl8xxxu_rfregs rtl8xxxu_rfregs[] = {
 941         {       /* RF_A */
 942                 .hssiparm1 = REG_FPGA0_XA_HSSI_PARM1,
 943                 .hssiparm2 = REG_FPGA0_XA_HSSI_PARM2,
 944                 .lssiparm = REG_FPGA0_XA_LSSI_PARM,
 945                 .hspiread = REG_HSPI_XA_READBACK,
 946                 .lssiread = REG_FPGA0_XA_LSSI_READBACK,
 947                 .rf_sw_ctrl = REG_FPGA0_XA_RF_SW_CTRL,
 948         },
 949         {       /* RF_B */
 950                 .hssiparm1 = REG_FPGA0_XB_HSSI_PARM1,
 951                 .hssiparm2 = REG_FPGA0_XB_HSSI_PARM2,
 952                 .lssiparm = REG_FPGA0_XB_LSSI_PARM,
 953                 .hspiread = REG_HSPI_XB_READBACK,
 954                 .lssiread = REG_FPGA0_XB_LSSI_READBACK,
 955                 .rf_sw_ctrl = REG_FPGA0_XB_RF_SW_CTRL,
 956         },
 957 };
 958
 959 static const u32 rtl8723au_iqk_phy_iq_bb_reg[RTL8XXXU_BB_REGS] = {
 960         REG_OFDM0_XA_RX_IQ_IMBALANCE,
 961         REG_OFDM0_XB_RX_IQ_IMBALANCE,
 962         REG_OFDM0_ENERGY_CCA_THRES,
 963         REG_OFDM0_AGCR_SSI_TABLE,
 964         REG_OFDM0_XA_TX_IQ_IMBALANCE,
 965         REG_OFDM0_XB_TX_IQ_IMBALANCE,
 966         REG_OFDM0_XC_TX_AFE,
 967         REG_OFDM0_XD_TX_AFE,
 968         REG_OFDM0_RX_IQ_EXT_ANTA
 969 };
 970
 971 static u8 rtl8xxxu_read8(struct rtl8xxxu_priv *priv, u16 addr)
 972 {
 973         struct usb_device *udev = priv->udev;
 974         int len;
 975         u8 data;
 976
 977         mutex_lock(&priv->usb_buf_mutex);
 978         len = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0),
 979                               REALTEK_USB_CMD_REQ, REALTEK_USB_READ,
 980                               addr, 0, &priv->usb_buf.val8, sizeof(u8),
 981                               RTW_USB_CONTROL_MSG_TIMEOUT);
 982         data = priv->usb_buf.val8;
 983         mutex_unlock(&priv->usb_buf_mutex);
 984
 985         if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_READ)
 986                 dev_info(&udev->dev, "%s(%04x)   = 0x%02x, len %i\n",
 987                          __func__, addr, data, len);
 988         return data;
 989 }
 990
 991 static u16 rtl8xxxu_read16(struct rtl8xxxu_priv *priv, u16 addr)
 992 {
 993         struct usb_device *udev = priv->udev;
 994         int len;
 995         u16 data;
 996
 997         mutex_lock(&priv->usb_buf_mutex);
 998         len = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0),
 999                               REALTEK_USB_CMD_REQ, REALTEK_USB_READ,
1000                               addr, 0, &priv->usb_buf.val16, sizeof(u16),
1001                               RTW_USB_CONTROL_MSG_TIMEOUT);
1002         data = le16_to_cpu(priv->usb_buf.val16);
1003         mutex_unlock(&priv->usb_buf_mutex);
1004
1005         if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_READ)
1006                 dev_info(&udev->dev, "%s(%04x)  = 0x%04x, len %i\n",
1007                          __func__, addr, data, len);
1008         return data;
1009 }
1010
1011 static u32 rtl8xxxu_read32(struct rtl8xxxu_priv *priv, u16 addr)
1012 {
1013         struct usb_device *udev = priv->udev;
1014         int len;
1015         u32 data;
1016
1017         mutex_lock(&priv->usb_buf_mutex);
1018         len = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0),
1019                               REALTEK_USB_CMD_REQ, REALTEK_USB_READ,
1020                               addr, 0, &priv->usb_buf.val32, sizeof(u32),
1021                               RTW_USB_CONTROL_MSG_TIMEOUT);
1022         data = le32_to_cpu(priv->usb_buf.val32);
1023         mutex_unlock(&priv->usb_buf_mutex);
1024
1025         if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_READ)
1026                 dev_info(&udev->dev, "%s(%04x)  = 0x%08x, len %i\n",
1027                          __func__, addr, data, len);
1028         return data;
1029 }
1030
1031 static int rtl8xxxu_write8(struct rtl8xxxu_priv *priv, u16 addr, u8 val)
1032 {
1033         struct usb_device *udev = priv->udev;
1034         int ret;
1035
1036         mutex_lock(&priv->usb_buf_mutex);
1037         priv->usb_buf.val8 = val;
1038         ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
1039                               REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE,
1040                               addr, 0, &priv->usb_buf.val8, sizeof(u8),
1041                               RTW_USB_CONTROL_MSG_TIMEOUT);
1042
1043         mutex_unlock(&priv->usb_buf_mutex);
1044
1045         if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_WRITE)
1046                 dev_info(&udev->dev, "%s(%04x) = 0x%02x\n",
1047                          __func__, addr, val);
1048         return ret;
1049 }
1050
1051 static int rtl8xxxu_write16(struct rtl8xxxu_priv *priv, u16 addr, u16 val)
1052 {
1053         struct usb_device *udev = priv->udev;
1054         int ret;
1055
1056         mutex_lock(&priv->usb_buf_mutex);
1057         priv->usb_buf.val16 = cpu_to_le16(val);
1058         ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
1059                               REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE,
1060                               addr, 0, &priv->usb_buf.val16, sizeof(u16),
1061                               RTW_USB_CONTROL_MSG_TIMEOUT);
1062         mutex_unlock(&priv->usb_buf_mutex);
1063
1064         if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_WRITE)
1065                 dev_info(&udev->dev, "%s(%04x) = 0x%04x\n",
1066                          __func__, addr, val);
1067         return ret;
1068 }
1069
1070 static int rtl8xxxu_write32(struct rtl8xxxu_priv *priv, u16 addr, u32 val)
1071 {
1072         struct usb_device *udev = priv->udev;
1073         int ret;
1074
1075         mutex_lock(&priv->usb_buf_mutex);
1076         priv->usb_buf.val32 = cpu_to_le32(val);
1077         ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
1078                               REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE,
1079                               addr, 0, &priv->usb_buf.val32, sizeof(u32),
1080                               RTW_USB_CONTROL_MSG_TIMEOUT);
1081         mutex_unlock(&priv->usb_buf_mutex);
1082
1083         if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_WRITE)
1084                 dev_info(&udev->dev, "%s(%04x) = 0x%08x\n",
1085                          __func__, addr, val);
1086         return ret;
1087 }
1088
1089 static int
1090 rtl8xxxu_writeN(struct rtl8xxxu_priv *priv, u16 addr, u8 *buf, u16 len)
1091 {
1092         struct usb_device *udev = priv->udev;
1093         int blocksize = priv->fops->writeN_block_size;
1094         int ret, i, count, remainder;
1095
1096         count = len / blocksize;
1097         remainder = len % blocksize;
1098
1099         for (i = 0; i < count; i++) {
1100                 ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
1101                                       REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE,
1102                                       addr, 0, buf, blocksize,
1103                                       RTW_USB_CONTROL_MSG_TIMEOUT);
1104                 if (ret != blocksize)
1105                         goto write_error;
1106
1107                 addr += blocksize;
1108                 buf += blocksize;
1109         }
1110
1111         if (remainder) {
1112                 ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
1113                                       REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE,
1114                                       addr, 0, buf, remainder,
1115                                       RTW_USB_CONTROL_MSG_TIMEOUT);
1116                 if (ret != remainder)
1117                         goto write_error;
1118         }
1119
1120         return len;
1121
1122 write_error:
1123         dev_info(&udev->dev,
1124                  "%s: Failed to write block at addr: %04x size: %04x\n",
1125                  __func__, addr, blocksize);
1126         return -EAGAIN;
1127 }
1128
1129 static u32 rtl8xxxu_read_rfreg(struct rtl8xxxu_priv *priv,
1130                                enum rtl8xxxu_rfpath path, u8 reg)
1131 {
1132         u32 hssia, val32, retval;
1133
1134         hssia = rtl8xxxu_read32(priv, REG_FPGA0_XA_HSSI_PARM2);
1135         if (path != RF_A)
1136                 val32 = rtl8xxxu_read32(priv, rtl8xxxu_rfregs[path].hssiparm2);
1137         else
1138                 val32 = hssia;
1139
1140         val32 &= ~FPGA0_HSSI_PARM2_ADDR_MASK;
1141         val32 |= (reg << FPGA0_HSSI_PARM2_ADDR_SHIFT);
1142         val32 |= FPGA0_HSSI_PARM2_EDGE_READ;
1143         hssia &= ~FPGA0_HSSI_PARM2_EDGE_READ;
1144         rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM2, hssia);
1145
1146         udelay(10);
1147
1148         rtl8xxxu_write32(priv, rtl8xxxu_rfregs[path].hssiparm2, val32);
1149         udelay(100);
1150
1151         hssia |= FPGA0_HSSI_PARM2_EDGE_READ;
1152         rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM2, hssia);
1153         udelay(10);
1154
1155         val32 = rtl8xxxu_read32(priv, rtl8xxxu_rfregs[path].hssiparm1);
1156         if (val32 & FPGA0_HSSI_PARM1_PI)
1157                 retval = rtl8xxxu_read32(priv, rtl8xxxu_rfregs[path].hspiread);
1158         else
1159                 retval = rtl8xxxu_read32(priv, rtl8xxxu_rfregs[path].lssiread);
1160
1161         retval &= 0xfffff;
1162
1163         if (rtl8xxxu_debug & RTL8XXXU_DEBUG_RFREG_READ)
1164                 dev_info(&priv->udev->dev, "%s(%02x) = 0x%06x\n",
1165                          __func__, reg, retval);
1166         return retval;
1167 }
1168
1169 static int rtl8xxxu_write_rfreg(struct rtl8xxxu_priv *priv,
1170                                 enum rtl8xxxu_rfpath path, u8 reg, u32 data)
1171 {
1172         int ret, retval;
1173         u32 dataaddr;
1174
1175         if (rtl8xxxu_debug & RTL8XXXU_DEBUG_RFREG_WRITE)
1176                 dev_info(&priv->udev->dev, "%s(%02x) = 0x%06x\n",
1177                          __func__, reg, data);
1178
1179         data &= FPGA0_LSSI_PARM_DATA_MASK;
1180         dataaddr = (reg << FPGA0_LSSI_PARM_ADDR_SHIFT) | data;
1181
1182         /* Use XB for path B */
1183         ret = rtl8xxxu_write32(priv, rtl8xxxu_rfregs[path].lssiparm, dataaddr);
1184         if (ret != sizeof(dataaddr))
1185                 retval = -EIO;
1186         else
1187                 retval = 0;
1188
1189         udelay(1);
1190
1191         return retval;
1192 }
1193
1194 static int rtl8723a_h2c_cmd(struct rtl8xxxu_priv *priv, struct h2c_cmd *h2c)
1195 {
1196         struct device *dev = &priv->udev->dev;
1197         int mbox_nr, retry, retval = 0;
1198         int mbox_reg, mbox_ext_reg;
1199         u8 val8;
1200
1201         mutex_lock(&priv->h2c_mutex);
1202
1203         mbox_nr = priv->next_mbox;
1204         mbox_reg = REG_HMBOX_0 + (mbox_nr * 4);
1205         mbox_ext_reg = REG_HMBOX_EXT_0 + (mbox_nr * 2);
1206
1207         /*
1208          * MBOX ready?
1209          */
1210         retry = 100;
1211         do {
1212                 val8 = rtl8xxxu_read8(priv, REG_HMTFR);
1213                 if (!(val8 & BIT(mbox_nr)))
1214                         break;
1215         } while (retry--);
1216
1217         if (!retry) {
1218                 dev_dbg(dev, "%s: Mailbox busy\n", __func__);
1219                 retval = -EBUSY;
1220                 goto error;
1221         }
1222
1223         /*
1224          * Need to swap as it's being swapped again by rtl8xxxu_write16/32()
1225          */
1226         if (h2c->cmd.cmd & H2C_EXT) {
1227                 rtl8xxxu_write16(priv, mbox_ext_reg,
1228                                  le16_to_cpu(h2c->raw.ext));
1229                 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_H2C)
1230                         dev_info(dev, "H2C_EXT %04x\n",
1231                                  le16_to_cpu(h2c->raw.ext));
1232         }
1233         rtl8xxxu_write32(priv, mbox_reg, le32_to_cpu(h2c->raw.data));
1234         if (rtl8xxxu_debug & RTL8XXXU_DEBUG_H2C)
1235                 dev_info(dev, "H2C %08x\n", le32_to_cpu(h2c->raw.data));
1236
1237         priv->next_mbox = (mbox_nr + 1) % H2C_MAX_MBOX;
1238
1239 error:
1240         mutex_unlock(&priv->h2c_mutex);
1241         return retval;
1242 }
1243
1244 static void rtl8723a_enable_rf(struct rtl8xxxu_priv *priv)
1245 {
1246         u8 val8;
1247         u32 val32;
1248
1249         val8 = rtl8xxxu_read8(priv, REG_SPS0_CTRL);
1250         val8 |= BIT(0) | BIT(3);
1251         rtl8xxxu_write8(priv, REG_SPS0_CTRL, val8);
1252
1253         val32 = rtl8xxxu_read32(priv, REG_FPGA0_XAB_RF_PARM);
1254         val32 &= ~(BIT(4) | BIT(5));
1255         val32 |= BIT(3);
1256         if (priv->rf_paths == 2) {
1257                 val32 &= ~(BIT(20) | BIT(21));
1258                 val32 |= BIT(19);
1259         }
1260         rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_PARM, val32);
1261
1262         val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE);
1263         val32 &= ~OFDM_RF_PATH_TX_MASK;
1264         if (priv->tx_paths == 2)
1265                 val32 |= OFDM_RF_PATH_TX_A | OFDM_RF_PATH_TX_B;
1266         else if (priv->rtlchip == 0x8192c || priv->rtlchip == 0x8191c)
1267                 val32 |= OFDM_RF_PATH_TX_B;
1268         else
1269                 val32 |= OFDM_RF_PATH_TX_A;
1270         rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, val32);
1271
1272         val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
1273         val32 &= ~FPGA_RF_MODE_JAPAN;
1274         rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
1275
1276         if (priv->rf_paths == 2)
1277                 rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x63db25a0);
1278         else
1279                 rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x631b25a0);
1280
1281         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC, 0x32d95);
1282         if (priv->rf_paths == 2)
1283                 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_AC, 0x32d95);
1284
1285         rtl8xxxu_write8(priv, REG_TXPAUSE, 0x00);
1286 }
1287
1288 static void rtl8723a_disable_rf(struct rtl8xxxu_priv *priv)
1289 {
1290         u8 sps0;
1291         u32 val32;
1292
1293         rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff);
1294
1295         sps0 = rtl8xxxu_read8(priv, REG_SPS0_CTRL);
1296
1297         /* RF RX code for preamble power saving */
1298         val32 = rtl8xxxu_read32(priv, REG_FPGA0_XAB_RF_PARM);
1299         val32 &= ~(BIT(3) | BIT(4) | BIT(5));
1300         if (priv->rf_paths == 2)
1301                 val32 &= ~(BIT(19) | BIT(20) | BIT(21));
1302         rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_PARM, val32);
1303
1304         /* Disable TX for four paths */
1305         val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE);
1306         val32 &= ~OFDM_RF_PATH_TX_MASK;
1307         rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, val32);
1308
1309         /* Enable power saving */
1310         val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
1311         val32 |= FPGA_RF_MODE_JAPAN;
1312         rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
1313
1314         /* AFE control register to power down bits [30:22] */
1315         if (priv->rf_paths == 2)
1316                 rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x00db25a0);
1317         else
1318                 rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x001b25a0);
1319
1320         /* Power down RF module */
1321         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC, 0);
1322         if (priv->rf_paths == 2)
1323                 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_AC, 0);
1324
1325         sps0 &= ~(BIT(0) | BIT(3));
1326         rtl8xxxu_write8(priv, REG_SPS0_CTRL, sps0);
1327 }
1328
1329
1330 static void rtl8723a_stop_tx_beacon(struct rtl8xxxu_priv *priv)
1331 {
1332         u8 val8;
1333
1334         val8 = rtl8xxxu_read8(priv, REG_FWHW_TXQ_CTRL + 2);
1335         val8 &= ~BIT(6);
1336         rtl8xxxu_write8(priv, REG_FWHW_TXQ_CTRL + 2, val8);
1337
1338         rtl8xxxu_write8(priv, REG_TBTT_PROHIBIT + 1, 0x64);
1339         val8 = rtl8xxxu_read8(priv, REG_TBTT_PROHIBIT + 2);
1340         val8 &= ~BIT(0);
1341         rtl8xxxu_write8(priv, REG_TBTT_PROHIBIT + 2, val8);
1342 }
1343
1344
1345 /*
1346  * The rtl8723a has 3 channel groups for it's efuse settings. It only
1347  * supports the 2.4GHz band, so channels 1 - 14:
1348  *  group 0: channels 1 - 3
1349  *  group 1: channels 4 - 9
1350  *  group 2: channels 10 - 14
1351  *
1352  * Note: We index from 0 in the code
1353  */
1354 static int rtl8723a_channel_to_group(int channel)
1355 {
1356         int group;
1357
1358         if (channel < 4)
1359                 group = 0;
1360         else if (channel < 10)
1361                 group = 1;
1362         else
1363                 group = 2;
1364
1365         return group;
1366 }
1367
1368 static void rtl8723au_config_channel(struct ieee80211_hw *hw)
1369 {
1370         struct rtl8xxxu_priv *priv = hw->priv;
1371         u32 val32, rsr;
1372         u8 val8, opmode;
1373         bool ht = true;
1374         int sec_ch_above, channel;
1375         int i;
1376
1377         opmode = rtl8xxxu_read8(priv, REG_BW_OPMODE);
1378         rsr = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET);
1379         channel = hw->conf.chandef.chan->hw_value;
1380
1381         switch (hw->conf.chandef.width) {
1382         case NL80211_CHAN_WIDTH_20_NOHT:
1383                 ht = false;
1384         case NL80211_CHAN_WIDTH_20:
1385                 opmode |= BW_OPMODE_20MHZ;
1386                 rtl8xxxu_write8(priv, REG_BW_OPMODE, opmode);
1387
1388                 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
1389                 val32 &= ~FPGA_RF_MODE;
1390                 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
1391
1392                 val32 = rtl8xxxu_read32(priv, REG_FPGA1_RF_MODE);
1393                 val32 &= ~FPGA_RF_MODE;
1394                 rtl8xxxu_write32(priv, REG_FPGA1_RF_MODE, val32);
1395
1396                 val32 = rtl8xxxu_read32(priv, REG_FPGA0_ANALOG2);
1397                 val32 |= FPGA0_ANALOG2_20MHZ;
1398                 rtl8xxxu_write32(priv, REG_FPGA0_ANALOG2, val32);
1399                 break;
1400         case NL80211_CHAN_WIDTH_40:
1401                 if (hw->conf.chandef.center_freq1 >
1402                     hw->conf.chandef.chan->center_freq) {
1403                         sec_ch_above = 1;
1404                         channel += 2;
1405                 } else {
1406                         sec_ch_above = 0;
1407                         channel -= 2;
1408                 }
1409
1410                 opmode &= ~BW_OPMODE_20MHZ;
1411                 rtl8xxxu_write8(priv, REG_BW_OPMODE, opmode);
1412                 rsr &= ~RSR_RSC_BANDWIDTH_40M;
1413                 if (sec_ch_above)
1414                         rsr |= RSR_RSC_UPPER_SUB_CHANNEL;
1415                 else
1416                         rsr |= RSR_RSC_LOWER_SUB_CHANNEL;
1417                 rtl8xxxu_write32(priv, REG_RESPONSE_RATE_SET, rsr);
1418
1419                 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
1420                 val32 |= FPGA_RF_MODE;
1421                 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
1422
1423                 val32 = rtl8xxxu_read32(priv, REG_FPGA1_RF_MODE);
1424                 val32 |= FPGA_RF_MODE;
1425                 rtl8xxxu_write32(priv, REG_FPGA1_RF_MODE, val32);
1426
1427                 /*
1428                  * Set Control channel to upper or lower. These settings
1429                  * are required only for 40MHz
1430                  */
1431                 val32 = rtl8xxxu_read32(priv, REG_CCK0_SYSTEM);
1432                 val32 &= ~CCK0_SIDEBAND;
1433                 if (!sec_ch_above)
1434                         val32 |= CCK0_SIDEBAND;
1435                 rtl8xxxu_write32(priv, REG_CCK0_SYSTEM, val32);
1436
1437                 val32 = rtl8xxxu_read32(priv, REG_OFDM1_LSTF);
1438                 val32 &= ~OFDM_LSTF_PRIME_CH_MASK; /* 0xc00 */
1439                 if (sec_ch_above)
1440                         val32 |= OFDM_LSTF_PRIME_CH_LOW;
1441                 else
1442                         val32 |= OFDM_LSTF_PRIME_CH_HIGH;
1443                 rtl8xxxu_write32(priv, REG_OFDM1_LSTF, val32);
1444
1445                 val32 = rtl8xxxu_read32(priv, REG_FPGA0_ANALOG2);
1446                 val32 &= ~FPGA0_ANALOG2_20MHZ;
1447                 rtl8xxxu_write32(priv, REG_FPGA0_ANALOG2, val32);
1448
1449                 val32 = rtl8xxxu_read32(priv, REG_FPGA0_POWER_SAVE);
1450                 val32 &= ~(FPGA0_PS_LOWER_CHANNEL | FPGA0_PS_UPPER_CHANNEL);
1451                 if (sec_ch_above)
1452                         val32 |= FPGA0_PS_UPPER_CHANNEL;
1453                 else
1454                         val32 |= FPGA0_PS_LOWER_CHANNEL;
1455                 rtl8xxxu_write32(priv, REG_FPGA0_POWER_SAVE, val32);
1456                 break;
1457
1458         default:
1459                 break;
1460         }
1461
1462         for (i = RF_A; i < priv->rf_paths; i++) {
1463                 val32 = rtl8xxxu_read_rfreg(priv, i, RF6052_REG_MODE_AG);
1464                 val32 &= ~MODE_AG_CHANNEL_MASK;
1465                 val32 |= channel;
1466                 rtl8xxxu_write_rfreg(priv, i, RF6052_REG_MODE_AG, val32);
1467         }
1468
1469         if (ht)
1470                 val8 = 0x0e;
1471         else
1472                 val8 = 0x0a;
1473
1474         rtl8xxxu_write8(priv, REG_SIFS_CCK + 1, val8);
1475         rtl8xxxu_write8(priv, REG_SIFS_OFDM + 1, val8);
1476
1477         rtl8xxxu_write16(priv, REG_R2T_SIFS, 0x0808);
1478         rtl8xxxu_write16(priv, REG_T2T_SIFS, 0x0a0a);
1479
1480         for (i = RF_A; i < priv->rf_paths; i++) {
1481                 val32 = rtl8xxxu_read_rfreg(priv, i, RF6052_REG_MODE_AG);
1482                 if (hw->conf.chandef.width == NL80211_CHAN_WIDTH_40)
1483                         val32 &= ~MODE_AG_CHANNEL_20MHZ;
1484                 else
1485                         val32 |= MODE_AG_CHANNEL_20MHZ;
1486                 rtl8xxxu_write_rfreg(priv, i, RF6052_REG_MODE_AG, val32);
1487         }
1488 }
1489
1490 static void
1491 rtl8723a_set_tx_power(struct rtl8xxxu_priv *priv, int channel, bool ht40)
1492 {
1493         u8 cck[RTL8723A_MAX_RF_PATHS], ofdm[RTL8723A_MAX_RF_PATHS];
1494         u8 ofdmbase[RTL8723A_MAX_RF_PATHS], mcsbase[RTL8723A_MAX_RF_PATHS];
1495         u32 val32, ofdm_a, ofdm_b, mcs_a, mcs_b;
1496         u8 val8;
1497         int group, i;
1498
1499         group = rtl8723a_channel_to_group(channel);
1500
1501         cck[0] = priv->cck_tx_power_index_A[group];
1502         cck[1] = priv->cck_tx_power_index_B[group];
1503
1504         ofdm[0] = priv->ht40_1s_tx_power_index_A[group];
1505         ofdm[1] = priv->ht40_1s_tx_power_index_B[group];
1506
1507         ofdmbase[0] = ofdm[0] + priv->ofdm_tx_power_index_diff[group].a;
1508         ofdmbase[1] = ofdm[1] + priv->ofdm_tx_power_index_diff[group].b;
1509
1510         mcsbase[0] = ofdm[0];
1511         mcsbase[1] = ofdm[1];
1512         if (!ht40) {
1513                 mcsbase[0] += priv->ht20_tx_power_index_diff[group].a;
1514                 mcsbase[1] += priv->ht20_tx_power_index_diff[group].b;
1515         }
1516
1517         if (priv->tx_paths > 1) {
1518                 if (ofdm[0] > priv->ht40_2s_tx_power_index_diff[group].a)
1519                         ofdm[0] -=  priv->ht40_2s_tx_power_index_diff[group].a;
1520                 if (ofdm[1] > priv->ht40_2s_tx_power_index_diff[group].b)
1521                         ofdm[1] -=  priv->ht40_2s_tx_power_index_diff[group].b;
1522         }
1523
1524         if (rtl8xxxu_debug & RTL8XXXU_DEBUG_CHANNEL)
1525                 dev_info(&priv->udev->dev,
1526                          "%s: Setting TX power CCK A: %02x, "
1527                          "CCK B: %02x, OFDM A: %02x, OFDM B: %02x\n",
1528                          __func__, cck[0], cck[1], ofdm[0], ofdm[1]);
1529
1530         for (i = 0; i < RTL8723A_MAX_RF_PATHS; i++) {
1531                 if (cck[i] > RF6052_MAX_TX_PWR)
1532                         cck[i] = RF6052_MAX_TX_PWR;
1533                 if (ofdm[i] > RF6052_MAX_TX_PWR)
1534                         ofdm[i] = RF6052_MAX_TX_PWR;
1535         }
1536
1537         val32 = rtl8xxxu_read32(priv, REG_TX_AGC_A_CCK1_MCS32);
1538         val32 &= 0xffff00ff;
1539         val32 |= (cck[0] << 8);
1540         rtl8xxxu_write32(priv, REG_TX_AGC_A_CCK1_MCS32, val32);
1541
1542         val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11);
1543         val32 &= 0xff;
1544         val32 |= ((cck[0] << 8) | (cck[0] << 16) | (cck[0] << 24));
1545         rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11, val32);
1546
1547         val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11);
1548         val32 &= 0xffffff00;
1549         val32 |= cck[1];
1550         rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11, val32);
1551
1552         val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK1_55_MCS32);
1553         val32 &= 0xff;
1554         val32 |= ((cck[1] << 8) | (cck[1] << 16) | (cck[1] << 24));
1555         rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK1_55_MCS32, val32);
1556
1557         ofdm_a = ofdmbase[0] | ofdmbase[0] << 8 |
1558                 ofdmbase[0] << 16 | ofdmbase[0] << 24;
1559         ofdm_b = ofdmbase[1] | ofdmbase[1] << 8 |
1560                 ofdmbase[1] << 16 | ofdmbase[1] << 24;
1561         rtl8xxxu_write32(priv, REG_TX_AGC_A_RATE18_06, ofdm_a);
1562         rtl8xxxu_write32(priv, REG_TX_AGC_B_RATE18_06, ofdm_b);
1563
1564         rtl8xxxu_write32(priv, REG_TX_AGC_A_RATE54_24, ofdm_a);
1565         rtl8xxxu_write32(priv, REG_TX_AGC_B_RATE54_24, ofdm_b);
1566
1567         mcs_a = mcsbase[0] | mcsbase[0] << 8 |
1568                 mcsbase[0] << 16 | mcsbase[0] << 24;
1569         mcs_b = mcsbase[1] | mcsbase[1] << 8 |
1570                 mcsbase[1] << 16 | mcsbase[1] << 24;
1571
1572         rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS03_MCS00, mcs_a);
1573         rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS03_MCS00, mcs_b);
1574
1575         rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS07_MCS04, mcs_a);
1576         rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS07_MCS04, mcs_b);
1577
1578         rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS11_MCS08, mcs_a);
1579         rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS11_MCS08, mcs_b);
1580
1581         rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS15_MCS12, mcs_a);
1582         for (i = 0; i < 3; i++) {
1583                 if (i != 2)
1584                         val8 = (mcsbase[0] > 8) ? (mcsbase[0] - 8) : 0;
1585                 else
1586                         val8 = (mcsbase[0] > 6) ? (mcsbase[0] - 6) : 0;
1587                 rtl8xxxu_write8(priv, REG_OFDM0_XC_TX_IQ_IMBALANCE + i, val8);
1588         }
1589         rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS15_MCS12, mcs_b);
1590         for (i = 0; i < 3; i++) {
1591                 if (i != 2)
1592                         val8 = (mcsbase[1] > 8) ? (mcsbase[1] - 8) : 0;
1593                 else
1594                         val8 = (mcsbase[1] > 6) ? (mcsbase[1] - 6) : 0;
1595                 rtl8xxxu_write8(priv, REG_OFDM0_XD_TX_IQ_IMBALANCE + i, val8);
1596         }
1597 }
1598
1599 static void rtl8xxxu_set_linktype(struct rtl8xxxu_priv *priv,
1600                                   enum nl80211_iftype linktype)
1601 {
1602         u16 val8;
1603
1604         val8 = rtl8xxxu_read16(priv, REG_MSR);
1605         val8 &= ~MSR_LINKTYPE_MASK;
1606
1607         switch (linktype) {
1608         case NL80211_IFTYPE_UNSPECIFIED:
1609                 val8 |= MSR_LINKTYPE_NONE;
1610                 break;
1611         case NL80211_IFTYPE_ADHOC:
1612                 val8 |= MSR_LINKTYPE_ADHOC;
1613                 break;
1614         case NL80211_IFTYPE_STATION:
1615                 val8 |= MSR_LINKTYPE_STATION;
1616                 break;
1617         case NL80211_IFTYPE_AP:
1618                 val8 |= MSR_LINKTYPE_AP;
1619                 break;
1620         default:
1621                 goto out;
1622         }
1623
1624         rtl8xxxu_write8(priv, REG_MSR, val8);
1625 out:
1626         return;
1627 }
1628
1629 static void
1630 rtl8xxxu_set_retry(struct rtl8xxxu_priv *priv, u16 short_retry, u16 long_retry)
1631 {
1632         u16 val16;
1633
1634         val16 = ((short_retry << RETRY_LIMIT_SHORT_SHIFT) &
1635                  RETRY_LIMIT_SHORT_MASK) |
1636                 ((long_retry << RETRY_LIMIT_LONG_SHIFT) &
1637                  RETRY_LIMIT_LONG_MASK);
1638
1639         rtl8xxxu_write16(priv, REG_RETRY_LIMIT, val16);
1640 }
1641
1642 static void
1643 rtl8xxxu_set_spec_sifs(struct rtl8xxxu_priv *priv, u16 cck, u16 ofdm)
1644 {
1645         u16 val16;
1646
1647         val16 = ((cck << SPEC_SIFS_CCK_SHIFT) & SPEC_SIFS_CCK_MASK) |
1648                 ((ofdm << SPEC_SIFS_OFDM_SHIFT) & SPEC_SIFS_OFDM_MASK);
1649
1650         rtl8xxxu_write16(priv, REG_SPEC_SIFS, val16);
1651 }
1652
1653 static void rtl8xxxu_print_chipinfo(struct rtl8xxxu_priv *priv)
1654 {
1655         struct device *dev = &priv->udev->dev;
1656         char *cut;
1657
1658         switch (priv->chip_cut) {
1659         case 0:
1660                 cut = "A";
1661                 break;
1662         case 1:
1663                 cut = "B";
1664                 break;
1665         default:
1666                 cut = "unknown";
1667         }
1668
1669         dev_info(dev,
1670                  "RTL%s rev %s (%s) %iT%iR, TX queues %i, WiFi=%i, BT=%i, GPS=%i, HI PA=%i\n",
1671                  priv->chip_name, cut, priv->vendor_umc ? "UMC" : "TSMC",
1672                  priv->tx_paths, priv->rx_paths, priv->ep_tx_count,
1673                  priv->has_wifi, priv->has_bluetooth, priv->has_gps,
1674                  priv->hi_pa);
1675
1676         dev_info(dev, "RTL%s MAC: %pM\n", priv->chip_name, priv->mac_addr);
1677 }
1678
1679 static int rtl8xxxu_identify_chip(struct rtl8xxxu_priv *priv)
1680 {
1681         struct device *dev = &priv->udev->dev;
1682         u32 val32, bonding;
1683         u16 val16;
1684
1685         val32 = rtl8xxxu_read32(priv, REG_SYS_CFG);
1686         priv->chip_cut = (val32 & SYS_CFG_CHIP_VERSION_MASK) >>
1687                 SYS_CFG_CHIP_VERSION_SHIFT;
1688         if (val32 & SYS_CFG_TRP_VAUX_EN) {
1689                 dev_info(dev, "Unsupported test chip\n");
1690                 return -ENOTSUPP;
1691         }
1692
1693         if (val32 & SYS_CFG_BT_FUNC) {
1694                 sprintf(priv->chip_name, "8723AU");
1695                 priv->rf_paths = 1;
1696                 priv->rx_paths = 1;
1697                 priv->tx_paths = 1;
1698                 priv->rtlchip = 0x8723a;
1699
1700                 val32 = rtl8xxxu_read32(priv, REG_MULTI_FUNC_CTRL);
1701                 if (val32 & MULTI_WIFI_FUNC_EN)
1702                         priv->has_wifi = 1;
1703                 if (val32 & MULTI_BT_FUNC_EN)
1704                         priv->has_bluetooth = 1;
1705                 if (val32 & MULTI_GPS_FUNC_EN)
1706                         priv->has_gps = 1;
1707         } else if (val32 & SYS_CFG_TYPE_ID) {
1708                 bonding = rtl8xxxu_read32(priv, REG_HPON_FSM);
1709                 bonding &= HPON_FSM_BONDING_MASK;
1710                 if (bonding == HPON_FSM_BONDING_1T2R) {
1711                         sprintf(priv->chip_name, "8191CU");
1712                         priv->rf_paths = 2;
1713                         priv->rx_paths = 2;
1714                         priv->tx_paths = 1;
1715                         priv->rtlchip = 0x8191c;
1716                 } else {
1717                         sprintf(priv->chip_name, "8192CU");
1718                         priv->rf_paths = 2;
1719                         priv->rx_paths = 2;
1720                         priv->tx_paths = 2;
1721                         priv->rtlchip = 0x8192c;
1722                 }
1723                 priv->has_wifi = 1;
1724         } else {
1725                 sprintf(priv->chip_name, "8188CU");
1726                 priv->rf_paths = 1;
1727                 priv->rx_paths = 1;
1728                 priv->tx_paths = 1;
1729                 priv->rtlchip = 0x8188c;
1730                 priv->has_wifi = 1;
1731         }
1732
1733         if (val32 & SYS_CFG_VENDOR_ID)
1734                 priv->vendor_umc = 1;
1735
1736         val32 = rtl8xxxu_read32(priv, REG_GPIO_OUTSTS);
1737         priv->rom_rev = (val32 & GPIO_RF_RL_ID) >> 28;
1738
1739         val16 = rtl8xxxu_read16(priv, REG_NORMAL_SIE_EP_TX);
1740         if (val16 & NORMAL_SIE_EP_TX_HIGH_MASK) {
1741                 priv->ep_tx_high_queue = 1;
1742                 priv->ep_tx_count++;
1743         }
1744
1745         if (val16 & NORMAL_SIE_EP_TX_NORMAL_MASK) {
1746                 priv->ep_tx_normal_queue = 1;
1747                 priv->ep_tx_count++;
1748         }
1749
1750         if (val16 & NORMAL_SIE_EP_TX_LOW_MASK) {
1751                 priv->ep_tx_low_queue = 1;
1752                 priv->ep_tx_count++;
1753         }
1754
1755         /*
1756          * Fallback for devices that do not provide REG_NORMAL_SIE_EP_TX
1757          */
1758         if (!priv->ep_tx_count) {
1759                 switch (priv->nr_out_eps) {
1760                 case 3:
1761                         priv->ep_tx_low_queue = 1;
1762                         priv->ep_tx_count++;
1763                 case 2:
1764                         priv->ep_tx_normal_queue = 1;
1765                         priv->ep_tx_count++;
1766                 case 1:
1767                         priv->ep_tx_high_queue = 1;
1768                         priv->ep_tx_count++;
1769                         break;
1770                 default:
1771                         dev_info(dev, "Unsupported USB TX end-points\n");
1772                         return -ENOTSUPP;
1773                 }
1774         }
1775
1776         return 0;
1777 }
1778
1779 static int rtl8723au_parse_efuse(struct rtl8xxxu_priv *priv)
1780 {
1781         if (priv->efuse_wifi.efuse8723.rtl_id != cpu_to_le16(0x8129))
1782                 return -EINVAL;
1783
1784         ether_addr_copy(priv->mac_addr, priv->efuse_wifi.efuse8723.mac_addr);
1785
1786         memcpy(priv->cck_tx_power_index_A,
1787                priv->efuse_wifi.efuse8723.cck_tx_power_index_A,
1788                sizeof(priv->cck_tx_power_index_A));
1789         memcpy(priv->cck_tx_power_index_B,
1790                priv->efuse_wifi.efuse8723.cck_tx_power_index_B,
1791                sizeof(priv->cck_tx_power_index_B));
1792
1793         memcpy(priv->ht40_1s_tx_power_index_A,
1794                priv->efuse_wifi.efuse8723.ht40_1s_tx_power_index_A,
1795                sizeof(priv->ht40_1s_tx_power_index_A));
1796         memcpy(priv->ht40_1s_tx_power_index_B,
1797                priv->efuse_wifi.efuse8723.ht40_1s_tx_power_index_B,
1798                sizeof(priv->ht40_1s_tx_power_index_B));
1799
1800         memcpy(priv->ht20_tx_power_index_diff,
1801                priv->efuse_wifi.efuse8723.ht20_tx_power_index_diff,
1802                sizeof(priv->ht20_tx_power_index_diff));
1803         memcpy(priv->ofdm_tx_power_index_diff,
1804                priv->efuse_wifi.efuse8723.ofdm_tx_power_index_diff,
1805                sizeof(priv->ofdm_tx_power_index_diff));
1806
1807         memcpy(priv->ht40_max_power_offset,
1808                priv->efuse_wifi.efuse8723.ht40_max_power_offset,
1809                sizeof(priv->ht40_max_power_offset));
1810         memcpy(priv->ht20_max_power_offset,
1811                priv->efuse_wifi.efuse8723.ht20_max_power_offset,
1812                sizeof(priv->ht20_max_power_offset));
1813
1814         dev_info(&priv->udev->dev, "Vendor: %.7s\n",
1815                  priv->efuse_wifi.efuse8723.vendor_name);
1816         dev_info(&priv->udev->dev, "Product: %.41s\n",
1817                  priv->efuse_wifi.efuse8723.device_name);
1818         return 0;
1819 }
1820
1821 #ifdef CONFIG_RTL8XXXU_UNTESTED
1822
1823 static int rtl8192cu_parse_efuse(struct rtl8xxxu_priv *priv)
1824 {
1825         int i;
1826
1827         if (priv->efuse_wifi.efuse8192.rtl_id != cpu_to_le16(0x8129))
1828                 return -EINVAL;
1829
1830         ether_addr_copy(priv->mac_addr, priv->efuse_wifi.efuse8192.mac_addr);
1831
1832         memcpy(priv->cck_tx_power_index_A,
1833                priv->efuse_wifi.efuse8192.cck_tx_power_index_A,
1834                sizeof(priv->cck_tx_power_index_A));
1835         memcpy(priv->cck_tx_power_index_B,
1836                priv->efuse_wifi.efuse8192.cck_tx_power_index_B,
1837                sizeof(priv->cck_tx_power_index_B));
1838
1839         memcpy(priv->ht40_1s_tx_power_index_A,
1840                priv->efuse_wifi.efuse8192.ht40_1s_tx_power_index_A,
1841                sizeof(priv->ht40_1s_tx_power_index_A));
1842         memcpy(priv->ht40_1s_tx_power_index_B,
1843                priv->efuse_wifi.efuse8192.ht40_1s_tx_power_index_B,
1844                sizeof(priv->ht40_1s_tx_power_index_B));
1845         memcpy(priv->ht40_2s_tx_power_index_diff,
1846                priv->efuse_wifi.efuse8192.ht40_2s_tx_power_index_diff,
1847                sizeof(priv->ht40_2s_tx_power_index_diff));
1848
1849         memcpy(priv->ht20_tx_power_index_diff,
1850                priv->efuse_wifi.efuse8192.ht20_tx_power_index_diff,
1851                sizeof(priv->ht20_tx_power_index_diff));
1852         memcpy(priv->ofdm_tx_power_index_diff,
1853                priv->efuse_wifi.efuse8192.ofdm_tx_power_index_diff,
1854                sizeof(priv->ofdm_tx_power_index_diff));
1855
1856         memcpy(priv->ht40_max_power_offset,
1857                priv->efuse_wifi.efuse8192.ht40_max_power_offset,
1858                sizeof(priv->ht40_max_power_offset));
1859         memcpy(priv->ht20_max_power_offset,
1860                priv->efuse_wifi.efuse8192.ht20_max_power_offset,
1861                sizeof(priv->ht20_max_power_offset));
1862
1863         dev_info(&priv->udev->dev, "Vendor: %.7s\n",
1864                  priv->efuse_wifi.efuse8192.vendor_name);
1865         dev_info(&priv->udev->dev, "Product: %.20s\n",
1866                  priv->efuse_wifi.efuse8192.device_name);
1867
1868         if (priv->efuse_wifi.efuse8192.rf_regulatory & 0x20) {
1869                 sprintf(priv->chip_name, "8188RU");
1870                 priv->hi_pa = 1;
1871         }
1872
1873         if (rtl8xxxu_debug & RTL8XXXU_DEBUG_EFUSE) {
1874                 unsigned char *raw = priv->efuse_wifi.raw;
1875
1876                 dev_info(&priv->udev->dev,
1877                          "%s: dumping efuse (0x%02zx bytes):\n",
1878                          __func__, sizeof(struct rtl8192cu_efuse));
1879                 for (i = 0; i < sizeof(struct rtl8192cu_efuse); i += 8) {
1880                         dev_info(&priv->udev->dev, "%02x: "
1881                                  "%02x %02x %02x %02x %02x %02x %02x %02x\n", i,
1882                                  raw[i], raw[i + 1], raw[i + 2],
1883                                  raw[i + 3], raw[i + 4], raw[i + 5],
1884                                  raw[i + 6], raw[i + 7]);
1885                 }
1886         }
1887         return 0;
1888 }
1889
1890 #endif
1891
1892 static int
1893 rtl8xxxu_read_efuse8(struct rtl8xxxu_priv *priv, u16 offset, u8 *data)
1894 {
1895         int i;
1896         u8 val8;
1897         u32 val32;
1898
1899         /* Write Address */
1900         rtl8xxxu_write8(priv, REG_EFUSE_CTRL + 1, offset & 0xff);
1901         val8 = rtl8xxxu_read8(priv, REG_EFUSE_CTRL + 2);
1902         val8 &= 0xfc;
1903         val8 |= (offset >> 8) & 0x03;
1904         rtl8xxxu_write8(priv, REG_EFUSE_CTRL + 2, val8);
1905
1906         val8 = rtl8xxxu_read8(priv, REG_EFUSE_CTRL + 3);
1907         rtl8xxxu_write8(priv, REG_EFUSE_CTRL + 3, val8 & 0x7f);
1908
1909         /* Poll for data read */
1910         val32 = rtl8xxxu_read32(priv, REG_EFUSE_CTRL);
1911         for (i = 0; i < RTL8XXXU_MAX_REG_POLL; i++) {
1912                 val32 = rtl8xxxu_read32(priv, REG_EFUSE_CTRL);
1913                 if (val32 & BIT(31))
1914                         break;
1915         }
1916
1917         if (i == RTL8XXXU_MAX_REG_POLL)
1918                 return -EIO;
1919
1920         udelay(50);
1921         val32 = rtl8xxxu_read32(priv, REG_EFUSE_CTRL);
1922
1923         *data = val32 & 0xff;
1924         return 0;
1925 }
1926
1927 static int rtl8xxxu_read_efuse(struct rtl8xxxu_priv *priv)
1928 {
1929         struct device *dev = &priv->udev->dev;
1930         int i, ret = 0;
1931         u8 val8, word_mask, header, extheader;
1932         u16 val16, efuse_addr, offset;
1933         u32 val32;
1934
1935         val16 = rtl8xxxu_read16(priv, REG_9346CR);
1936         if (val16 & EEPROM_ENABLE)
1937                 priv->has_eeprom = 1;
1938         if (val16 & EEPROM_BOOT)
1939                 priv->boot_eeprom = 1;
1940
1941         val32 = rtl8xxxu_read32(priv, REG_EFUSE_TEST);
1942         val32 = (val32 & ~EFUSE_SELECT_MASK) | EFUSE_WIFI_SELECT;
1943         rtl8xxxu_write32(priv, REG_EFUSE_TEST, val32);
1944
1945         dev_dbg(dev, "Booting from %s\n",
1946                 priv->boot_eeprom ? "EEPROM" : "EFUSE");
1947
1948         rtl8xxxu_write8(priv, REG_EFUSE_ACCESS, EFUSE_ACCESS_ENABLE);
1949
1950         /*  1.2V Power: From VDDON with Power Cut(0x0000[15]), default valid */
1951         val16 = rtl8xxxu_read16(priv, REG_SYS_ISO_CTRL);
1952         if (!(val16 & SYS_ISO_PWC_EV12V)) {
1953                 val16 |= SYS_ISO_PWC_EV12V;
1954                 rtl8xxxu_write16(priv, REG_SYS_ISO_CTRL, val16);
1955         }
1956         /*  Reset: 0x0000[28], default valid */
1957         val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
1958         if (!(val16 & SYS_FUNC_ELDR)) {
1959                 val16 |= SYS_FUNC_ELDR;
1960                 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);
1961         }
1962
1963         /*
1964          * Clock: Gated(0x0008[5]) 8M(0x0008[1]) clock from ANA, default valid
1965          */
1966         val16 = rtl8xxxu_read16(priv, REG_SYS_CLKR);
1967         if (!(val16 & SYS_CLK_LOADER_ENABLE) || !(val16 & SYS_CLK_ANA8M)) {
1968                 val16 |= (SYS_CLK_LOADER_ENABLE | SYS_CLK_ANA8M);
1969                 rtl8xxxu_write16(priv, REG_SYS_CLKR, val16);
1970         }
1971
1972         /* Default value is 0xff */
1973         memset(priv->efuse_wifi.raw, 0xff, EFUSE_MAP_LEN_8723A);
1974
1975         efuse_addr = 0;
1976         while (efuse_addr < EFUSE_REAL_CONTENT_LEN_8723A) {
1977                 ret = rtl8xxxu_read_efuse8(priv, efuse_addr++, &header);
1978                 if (ret || header == 0xff)
1979                         goto exit;
1980
1981                 if ((header & 0x1f) == 0x0f) {  /* extended header */
1982                         offset = (header & 0xe0) >> 5;
1983
1984                         ret = rtl8xxxu_read_efuse8(priv, efuse_addr++,
1985                                                    &extheader);
1986                         if (ret)
1987                                 goto exit;
1988                         /* All words disabled */
1989                         if ((extheader & 0x0f) == 0x0f)
1990                                 continue;
1991
1992                         offset |= ((extheader & 0xf0) >> 1);
1993                         word_mask = extheader & 0x0f;
1994                 } else {
1995                         offset = (header >> 4) & 0x0f;
1996                         word_mask = header & 0x0f;
1997                 }
1998
1999                 if (offset < EFUSE_MAX_SECTION_8723A) {
2000                         u16 map_addr;
2001                         /* Get word enable value from PG header */
2002
2003                         /* We have 8 bits to indicate validity */
2004                         map_addr = offset * 8;
2005                         if (map_addr >= EFUSE_MAP_LEN_8723A) {
2006                                 dev_warn(dev, "%s: Illegal map_addr (%04x), "
2007                                          "efuse corrupt!\n",
2008                                          __func__, map_addr);
2009                                 ret = -EINVAL;
2010                                 goto exit;
2011                         }
2012                         for (i = 0; i < EFUSE_MAX_WORD_UNIT; i++) {
2013                                 /* Check word enable condition in the section */
2014                                 if (!(word_mask & BIT(i))) {
2015                                         ret = rtl8xxxu_read_efuse8(priv,
2016                                                                    efuse_addr++,
2017                                                                    &val8);
2018                                         if (ret)
2019                                                 goto exit;
2020                                         priv->efuse_wifi.raw[map_addr++] = val8;
2021
2022                                         ret = rtl8xxxu_read_efuse8(priv,
2023                                                                    efuse_addr++,
2024                                                                    &val8);
2025                                         if (ret)
2026                                                 goto exit;
2027                                         priv->efuse_wifi.raw[map_addr++] = val8;
2028                                 } else
2029                                         map_addr += 2;
2030                         }
2031                 } else {
2032                         dev_warn(dev,
2033                                  "%s: Illegal offset (%04x), efuse corrupt!\n",
2034                                  __func__, offset);
2035                         ret = -EINVAL;
2036                         goto exit;
2037                 }
2038         }
2039
2040 exit:
2041         rtl8xxxu_write8(priv, REG_EFUSE_ACCESS, EFUSE_ACCESS_DISABLE);
2042
2043         return ret;
2044 }
2045
2046 static int rtl8xxxu_start_firmware(struct rtl8xxxu_priv *priv)
2047 {
2048         struct device *dev = &priv->udev->dev;
2049         int ret = 0, i;
2050         u32 val32;
2051
2052         /* Poll checksum report */
2053         for (i = 0; i < RTL8XXXU_FIRMWARE_POLL_MAX; i++) {
2054                 val32 = rtl8xxxu_read32(priv, REG_MCU_FW_DL);
2055                 if (val32 & MCU_FW_DL_CSUM_REPORT)
2056                         break;
2057         }
2058
2059         if (i == RTL8XXXU_FIRMWARE_POLL_MAX) {
2060                 dev_warn(dev, "Firmware checksum poll timed out\n");
2061                 ret = -EAGAIN;
2062                 goto exit;
2063         }
2064
2065         val32 = rtl8xxxu_read32(priv, REG_MCU_FW_DL);
2066         val32 |= MCU_FW_DL_READY;
2067         val32 &= ~MCU_WINT_INIT_READY;
2068         rtl8xxxu_write32(priv, REG_MCU_FW_DL, val32);
2069
2070         /* Wait for firmware to become ready */
2071         for (i = 0; i < RTL8XXXU_FIRMWARE_POLL_MAX; i++) {
2072                 val32 = rtl8xxxu_read32(priv, REG_MCU_FW_DL);
2073                 if (val32 & MCU_WINT_INIT_READY)
2074                         break;
2075
2076                 udelay(100);
2077         }
2078
2079         if (i == RTL8XXXU_FIRMWARE_POLL_MAX) {
2080                 dev_warn(dev, "Firmware failed to start\n");
2081                 ret = -EAGAIN;
2082                 goto exit;
2083         }
2084
2085 exit:
2086         return ret;
2087 }
2088
2089 static int rtl8xxxu_download_firmware(struct rtl8xxxu_priv *priv)
2090 {
2091         int pages, remainder, i, ret;
2092         u8 val8;
2093         u16 val16;
2094         u32 val32;
2095         u8 *fwptr;
2096
2097         val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC + 1);
2098         val8 |= 4;
2099         rtl8xxxu_write8(priv, REG_SYS_FUNC + 1, val8);
2100
2101         /* 8051 enable */
2102         val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
2103         val16 |= SYS_FUNC_CPU_ENABLE;
2104         rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);
2105
2106         /* MCU firmware download enable */
2107         val8 = rtl8xxxu_read8(priv, REG_MCU_FW_DL);
2108         val8 |= MCU_FW_DL_ENABLE;
2109         rtl8xxxu_write8(priv, REG_MCU_FW_DL, val8);
2110
2111         /* 8051 reset */
2112         val32 = rtl8xxxu_read32(priv, REG_MCU_FW_DL);
2113         val32 &= ~BIT(19);
2114         rtl8xxxu_write32(priv, REG_MCU_FW_DL, val32);
2115
2116         /* Reset firmware download checksum */
2117         val8 = rtl8xxxu_read8(priv, REG_MCU_FW_DL);
2118         val8 |= MCU_FW_DL_CSUM_REPORT;
2119         rtl8xxxu_write8(priv, REG_MCU_FW_DL, val8);
2120
2121         pages = priv->fw_size / RTL_FW_PAGE_SIZE;
2122         remainder = priv->fw_size % RTL_FW_PAGE_SIZE;
2123
2124         fwptr = priv->fw_data->data;
2125
2126         for (i = 0; i < pages; i++) {
2127                 val8 = rtl8xxxu_read8(priv, REG_MCU_FW_DL + 2) & 0xF8;
2128                 val8 |= i;
2129                 rtl8xxxu_write8(priv, REG_MCU_FW_DL + 2, val8);
2130
2131                 ret = rtl8xxxu_writeN(priv, REG_FW_START_ADDRESS,
2132                                       fwptr, RTL_FW_PAGE_SIZE);
2133                 if (ret != RTL_FW_PAGE_SIZE) {
2134                         ret = -EAGAIN;
2135                         goto fw_abort;
2136                 }
2137
2138                 fwptr += RTL_FW_PAGE_SIZE;
2139         }
2140
2141         if (remainder) {
2142                 val8 = rtl8xxxu_read8(priv, REG_MCU_FW_DL + 2) & 0xF8;
2143                 val8 |= i;
2144                 rtl8xxxu_write8(priv, REG_MCU_FW_DL + 2, val8);
2145                 ret = rtl8xxxu_writeN(priv, REG_FW_START_ADDRESS,
2146                                       fwptr, remainder);
2147                 if (ret != remainder) {
2148                         ret = -EAGAIN;
2149                         goto fw_abort;
2150                 }
2151         }
2152
2153         ret = 0;
2154 fw_abort:
2155         /* MCU firmware download disable */
2156         val16 = rtl8xxxu_read16(priv, REG_MCU_FW_DL);
2157         val16 &= ~MCU_FW_DL_ENABLE;
2158         rtl8xxxu_write16(priv, REG_MCU_FW_DL, val16);
2159
2160         return ret;
2161 }
2162
2163 static int rtl8xxxu_load_firmware(struct rtl8xxxu_priv *priv, char *fw_name)
2164 {
2165         struct device *dev = &priv->udev->dev;
2166         const struct firmware *fw;
2167         int ret = 0;
2168         u16 signature;
2169
2170         dev_info(dev, "%s: Loading firmware %s\n", DRIVER_NAME, fw_name);
2171         if (request_firmware(&fw, fw_name, &priv->udev->dev)) {
2172                 dev_warn(dev, "request_firmware(%s) failed\n", fw_name);
2173                 ret = -EAGAIN;
2174                 goto exit;
2175         }
2176         if (!fw) {
2177                 dev_warn(dev, "Firmware data not available\n");
2178                 ret = -EINVAL;
2179                 goto exit;
2180         }
2181
2182         priv->fw_data = kmemdup(fw->data, fw->size, GFP_KERNEL);
2183         priv->fw_size = fw->size - sizeof(struct rtl8xxxu_firmware_header);
2184
2185         signature = le16_to_cpu(priv->fw_data->signature);
2186         switch (signature & 0xfff0) {
2187         case 0x92c0:
2188         case 0x88c0:
2189         case 0x2300:
2190                 break;
2191         default:
2192                 ret = -EINVAL;
2193                 dev_warn(dev, "%s: Invalid firmware signature: 0x%04x\n",
2194                          __func__, signature);
2195         }
2196
2197         dev_info(dev, "Firmware revision %i.%i (signature 0x%04x)\n",
2198                  le16_to_cpu(priv->fw_data->major_version),
2199                  priv->fw_data->minor_version, signature);
2200
2201 exit:
2202         release_firmware(fw);
2203         return ret;
2204 }
2205
2206 static int rtl8723au_load_firmware(struct rtl8xxxu_priv *priv)
2207 {
2208         char *fw_name;
2209         int ret;
2210
2211         switch (priv->chip_cut) {
2212         case 0:
2213                 fw_name = "rtlwifi/rtl8723aufw_A.bin";
2214                 break;
2215         case 1:
2216                 if (priv->enable_bluetooth)
2217                         fw_name = "rtlwifi/rtl8723aufw_B.bin";
2218                 else
2219                         fw_name = "rtlwifi/rtl8723aufw_B_NoBT.bin";
2220
2221                 break;
2222         default:
2223                 return -EINVAL;
2224         }
2225
2226         ret = rtl8xxxu_load_firmware(priv, fw_name);
2227         return ret;
2228 }
2229
2230 #ifdef CONFIG_RTL8XXXU_UNTESTED
2231
2232 static int rtl8192cu_load_firmware(struct rtl8xxxu_priv *priv)
2233 {
2234         char *fw_name;
2235         int ret;
2236
2237         if (!priv->vendor_umc)
2238                 fw_name = "rtlwifi/rtl8192cufw_TMSC.bin";
2239         else if (priv->chip_cut || priv->rtlchip == 0x8192c)
2240                 fw_name = "rtlwifi/rtl8192cufw_B.bin";
2241         else
2242                 fw_name = "rtlwifi/rtl8192cufw_A.bin";
2243
2244         ret = rtl8xxxu_load_firmware(priv, fw_name);
2245
2246         return ret;
2247 }
2248
2249 #endif
2250
2251 static void rtl8xxxu_firmware_self_reset(struct rtl8xxxu_priv *priv)
2252 {
2253         u16 val16;
2254         int i = 100;
2255
2256         /* Inform 8051 to perform reset */
2257         rtl8xxxu_write8(priv, REG_HMTFR + 3, 0x20);
2258
2259         for (i = 100; i > 0; i--) {
2260                 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
2261
2262                 if (!(val16 & SYS_FUNC_CPU_ENABLE)) {
2263                         dev_dbg(&priv->udev->dev,
2264                                 "%s: Firmware self reset success!\n", __func__);
2265                         break;
2266                 }
2267                 udelay(50);
2268         }
2269
2270         if (!i) {
2271                 /* Force firmware reset */
2272                 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
2273                 val16 &= ~SYS_FUNC_CPU_ENABLE;
2274                 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);
2275         }
2276 }
2277
2278 static int
2279 rtl8xxxu_init_mac(struct rtl8xxxu_priv *priv, struct rtl8xxxu_reg8val *array)
2280 {
2281         int i, ret;
2282         u16 reg;
2283         u8 val;
2284
2285         for (i = 0; ; i++) {
2286                 reg = array[i].reg;
2287                 val = array[i].val;
2288
2289                 if (reg == 0xffff && val == 0xff)
2290                         break;
2291
2292                 ret = rtl8xxxu_write8(priv, reg, val);
2293                 if (ret != 1) {
2294                         dev_warn(&priv->udev->dev,
2295                                  "Failed to initialize MAC\n");
2296                         return -EAGAIN;
2297                 }
2298         }
2299
2300         rtl8xxxu_write8(priv, REG_MAX_AGGR_NUM, 0x0a);
2301
2302         return 0;
2303 }
2304
2305 static int rtl8xxxu_init_phy_regs(struct rtl8xxxu_priv *priv,
2306                                   struct rtl8xxxu_reg32val *array)
2307 {
2308         int i, ret;
2309         u16 reg;
2310         u32 val;
2311
2312         for (i = 0; ; i++) {
2313                 reg = array[i].reg;
2314                 val = array[i].val;
2315
2316                 if (reg == 0xffff && val == 0xffffffff)
2317                         break;
2318
2319                 ret = rtl8xxxu_write32(priv, reg, val);
2320                 if (ret != sizeof(val)) {
2321                         dev_warn(&priv->udev->dev,
2322                                  "Failed to initialize PHY\n");
2323                         return -EAGAIN;
2324                 }
2325                 udelay(1);
2326         }
2327
2328         return 0;
2329 }
2330
2331 /*
2332  * Most of this is black magic retrieved from the old rtl8723au driver
2333  */
2334 static int rtl8xxxu_init_phy_bb(struct rtl8xxxu_priv *priv)
2335 {
2336         u8 val8, ldoa15, ldov12d, lpldo, ldohci12;
2337         u32 val32;
2338
2339         /*
2340          * Todo: The vendor driver maintains a table of PHY register
2341          *       addresses, which is initialized here. Do we need this?
2342          */
2343
2344         val8 = rtl8xxxu_read8(priv, REG_AFE_PLL_CTRL);
2345         udelay(2);
2346         val8 |= AFE_PLL_320_ENABLE;
2347         rtl8xxxu_write8(priv, REG_AFE_PLL_CTRL, val8);
2348         udelay(2);
2349
2350         rtl8xxxu_write8(priv, REG_AFE_PLL_CTRL + 1, 0xff);
2351         udelay(2);
2352
2353         val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC);
2354         val8 |= SYS_FUNC_BB_GLB_RSTN | SYS_FUNC_BBRSTB;
2355         rtl8xxxu_write8(priv, REG_SYS_FUNC, val8);
2356
2357         /* AFE_XTAL_RF_GATE (bit 14) if addressing as 32 bit register */
2358         val32 = rtl8xxxu_read32(priv, REG_AFE_XTAL_CTRL);
2359         val32 &= ~AFE_XTAL_RF_GATE;
2360         if (priv->has_bluetooth)
2361                 val32 &= ~AFE_XTAL_BT_GATE;
2362         rtl8xxxu_write32(priv, REG_AFE_XTAL_CTRL, val32);
2363
2364         /* 6. 0x1f[7:0] = 0x07 */
2365         val8 = RF_ENABLE | RF_RSTB | RF_SDMRSTB;
2366         rtl8xxxu_write8(priv, REG_RF_CTRL, val8);
2367
2368         if (priv->hi_pa)
2369                 rtl8xxxu_init_phy_regs(priv, rtl8188ru_phy_1t_highpa_table);
2370         else if (priv->tx_paths == 2)
2371                 rtl8xxxu_init_phy_regs(priv, rtl8192cu_phy_2t_init_table);
2372         else
2373                 rtl8xxxu_init_phy_regs(priv, rtl8723a_phy_1t_init_table);
2374
2375
2376         if (priv->rtlchip == 0x8188c && priv->hi_pa &&
2377             priv->vendor_umc && priv->chip_cut == 1)
2378                 rtl8xxxu_write8(priv, REG_OFDM0_AGC_PARM1 + 2, 0x50);
2379
2380         if (priv->tx_paths == 1 && priv->rx_paths == 2) {
2381                 /*
2382                  * For 1T2R boards, patch the registers.
2383                  *
2384                  * It looks like 8191/2 1T2R boards use path B for TX
2385                  */
2386                 val32 = rtl8xxxu_read32(priv, REG_FPGA0_TX_INFO);
2387                 val32 &= ~(BIT(0) | BIT(1));
2388                 val32 |= BIT(1);
2389                 rtl8xxxu_write32(priv, REG_FPGA0_TX_INFO, val32);
2390
2391                 val32 = rtl8xxxu_read32(priv, REG_FPGA1_TX_INFO);
2392                 val32 &= ~0x300033;
2393                 val32 |= 0x200022;
2394                 rtl8xxxu_write32(priv, REG_FPGA1_TX_INFO, val32);
2395
2396                 val32 = rtl8xxxu_read32(priv, REG_CCK0_AFE_SETTING);
2397                 val32 &= 0xff000000;
2398                 val32 |= 0x45000000;
2399                 rtl8xxxu_write32(priv, REG_CCK0_AFE_SETTING, val32);
2400
2401                 val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE);
2402                 val32 &= ~(OFDM_RF_PATH_RX_MASK | OFDM_RF_PATH_TX_MASK);
2403                 val32 |= (OFDM_RF_PATH_RX_A | OFDM_RF_PATH_RX_B |
2404                           OFDM_RF_PATH_TX_B);
2405                 rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, val32);
2406
2407                 val32 = rtl8xxxu_read32(priv, REG_OFDM0_AGC_PARM1);
2408                 val32 &= ~(BIT(4) | BIT(5));
2409                 val32 |= BIT(4);
2410                 rtl8xxxu_write32(priv, REG_OFDM0_AGC_PARM1, val32);
2411
2412                 val32 = rtl8xxxu_read32(priv, REG_TX_CCK_RFON);
2413                 val32 &= ~(BIT(27) | BIT(26));
2414                 val32 |= BIT(27);
2415                 rtl8xxxu_write32(priv, REG_TX_CCK_RFON, val32);
2416
2417                 val32 = rtl8xxxu_read32(priv, REG_TX_CCK_BBON);
2418                 val32 &= ~(BIT(27) | BIT(26));
2419                 val32 |= BIT(27);
2420                 rtl8xxxu_write32(priv, REG_TX_CCK_BBON, val32);
2421
2422                 val32 = rtl8xxxu_read32(priv, REG_TX_OFDM_RFON);
2423                 val32 &= ~(BIT(27) | BIT(26));
2424                 val32 |= BIT(27);
2425                 rtl8xxxu_write32(priv, REG_TX_OFDM_RFON, val32);
2426
2427                 val32 = rtl8xxxu_read32(priv, REG_TX_OFDM_BBON);
2428                 val32 &= ~(BIT(27) | BIT(26));
2429                 val32 |= BIT(27);
2430                 rtl8xxxu_write32(priv, REG_TX_OFDM_BBON, val32);
2431
2432                 val32 = rtl8xxxu_read32(priv, REG_TX_TO_TX);
2433                 val32 &= ~(BIT(27) | BIT(26));
2434                 val32 |= BIT(27);
2435                 rtl8xxxu_write32(priv, REG_TX_TO_TX, val32);
2436         }
2437
2438         if (priv->hi_pa)
2439                 rtl8xxxu_init_phy_regs(priv, rtl8xxx_agc_highpa_table);
2440         else
2441                 rtl8xxxu_init_phy_regs(priv, rtl8xxx_agc_standard_table);
2442
2443         if (priv->rtlchip == 0x8723a &&
2444             priv->efuse_wifi.efuse8723.version >= 0x01) {
2445                 val32 = rtl8xxxu_read32(priv, REG_MAC_PHY_CTRL);
2446
2447                 val8 = priv->efuse_wifi.efuse8723.xtal_k & 0x3f;
2448                 val32 &= 0xff000fff;
2449                 val32 |= ((val8 | (val8 << 6)) << 12);
2450
2451                 rtl8xxxu_write32(priv, REG_MAC_PHY_CTRL, val32);
2452         }
2453
2454         ldoa15 = LDOA15_ENABLE | LDOA15_OBUF;
2455         ldov12d = LDOV12D_ENABLE | BIT(2) | (2 << LDOV12D_VADJ_SHIFT);
2456         ldohci12 = 0x57;
2457         lpldo = 1;
2458         val32 = (lpldo << 24) | (ldohci12 << 16) | (ldov12d << 8) | ldoa15;
2459
2460         rtl8xxxu_write32(priv, REG_LDOA15_CTRL, val32);
2461
2462         return 0;
2463 }
2464
2465 static int rtl8xxxu_init_rf_regs(struct rtl8xxxu_priv *priv,
2466                                  struct rtl8xxxu_rfregval *array,
2467                                  enum rtl8xxxu_rfpath path)
2468 {
2469         int i, ret;
2470         u8 reg;
2471         u32 val;
2472
2473         for (i = 0; ; i++) {
2474                 reg = array[i].reg;
2475                 val = array[i].val;
2476
2477                 if (reg == 0xff && val == 0xffffffff)
2478                         break;
2479
2480                 switch (reg) {
2481                 case 0xfe:
2482                         msleep(50);
2483                         continue;
2484                 case 0xfd:
2485                         mdelay(5);
2486                         continue;
2487                 case 0xfc:
2488                         mdelay(1);
2489                         continue;
2490                 case 0xfb:
2491                         udelay(50);
2492                         continue;
2493                 case 0xfa:
2494                         udelay(5);
2495                         continue;
2496                 case 0xf9:
2497                         udelay(1);
2498                         continue;
2499                 }
2500
2501                 reg &= 0x3f;
2502
2503                 ret = rtl8xxxu_write_rfreg(priv, path, reg, val);
2504                 if (ret) {
2505                         dev_warn(&priv->udev->dev,
2506                                  "Failed to initialize RF\n");
2507                         return -EAGAIN;
2508                 }
2509                 udelay(1);
2510         }
2511
2512         return 0;
2513 }
2514
2515 static int rtl8xxxu_init_phy_rf(struct rtl8xxxu_priv *priv,
2516                                 struct rtl8xxxu_rfregval *table,
2517                                 enum rtl8xxxu_rfpath path)
2518 {
2519         u32 val32;
2520         u16 val16, rfsi_rfenv;
2521         u16 reg_sw_ctrl, reg_int_oe, reg_hssi_parm2;
2522
2523         switch (path) {
2524         case RF_A:
2525                 reg_sw_ctrl = REG_FPGA0_XA_RF_SW_CTRL;
2526                 reg_int_oe = REG_FPGA0_XA_RF_INT_OE;
2527                 reg_hssi_parm2 = REG_FPGA0_XA_HSSI_PARM2;
2528                 break;
2529         case RF_B:
2530                 reg_sw_ctrl = REG_FPGA0_XB_RF_SW_CTRL;
2531                 reg_int_oe = REG_FPGA0_XB_RF_INT_OE;
2532                 reg_hssi_parm2 = REG_FPGA0_XB_HSSI_PARM2;
2533                 break;
2534         default:
2535                 dev_err(&priv->udev->dev, "%s:Unsupported RF path %c\n",
2536                         __func__, path + 'A');
2537                 return -EINVAL;
2538         }
2539         /* For path B, use XB */
2540         rfsi_rfenv = rtl8xxxu_read16(priv, reg_sw_ctrl);
2541         rfsi_rfenv &= FPGA0_RF_RFENV;
2542
2543         /*
2544          * These two we might be able to optimize into one
2545          */
2546         val32 = rtl8xxxu_read32(priv, reg_int_oe);
2547         val32 |= BIT(20);       /* 0x10 << 16 */
2548         rtl8xxxu_write32(priv, reg_int_oe, val32);
2549         udelay(1);
2550
2551         val32 = rtl8xxxu_read32(priv, reg_int_oe);
2552         val32 |= BIT(4);
2553         rtl8xxxu_write32(priv, reg_int_oe, val32);
2554         udelay(1);
2555
2556         /*
2557          * These two we might be able to optimize into one
2558          */
2559         val32 = rtl8xxxu_read32(priv, reg_hssi_parm2);
2560         val32 &= ~FPGA0_HSSI_3WIRE_ADDR_LEN;
2561         rtl8xxxu_write32(priv, reg_hssi_parm2, val32);
2562         udelay(1);
2563
2564         val32 = rtl8xxxu_read32(priv, reg_hssi_parm2);
2565         val32 &= ~FPGA0_HSSI_3WIRE_DATA_LEN;
2566         rtl8xxxu_write32(priv, reg_hssi_parm2, val32);
2567         udelay(1);
2568
2569         rtl8xxxu_init_rf_regs(priv, table, path);
2570
2571         /* For path B, use XB */
2572         val16 = rtl8xxxu_read16(priv, reg_sw_ctrl);
2573         val16 &= ~FPGA0_RF_RFENV;
2574         val16 |= rfsi_rfenv;
2575         rtl8xxxu_write16(priv, reg_sw_ctrl, val16);
2576
2577         return 0;
2578 }
2579
2580 static int rtl8xxxu_llt_write(struct rtl8xxxu_priv *priv, u8 address, u8 data)
2581 {
2582         int ret = -EBUSY;
2583         int count = 0;
2584         u32 value;
2585
2586         value = LLT_OP_WRITE | address << 8 | data;
2587
2588         rtl8xxxu_write32(priv, REG_LLT_INIT, value);
2589
2590         do {
2591                 value = rtl8xxxu_read32(priv, REG_LLT_INIT);
2592                 if ((value & LLT_OP_MASK) == LLT_OP_INACTIVE) {
2593                         ret = 0;
2594                         break;
2595                 }
2596         } while (count++ < 20);
2597
2598         return ret;
2599 }
2600
2601 static int rtl8xxxu_init_llt_table(struct rtl8xxxu_priv *priv, u8 last_tx_page)
2602 {
2603         int ret;
2604         int i;
2605
2606         for (i = 0; i < last_tx_page; i++) {
2607                 ret = rtl8xxxu_llt_write(priv, i, i + 1);
2608                 if (ret)
2609                         goto exit;
2610         }
2611
2612         ret = rtl8xxxu_llt_write(priv, last_tx_page, 0xff);
2613         if (ret)
2614                 goto exit;
2615
2616         /* Mark remaining pages as a ring buffer */
2617         for (i = last_tx_page + 1; i < 0xff; i++) {
2618                 ret = rtl8xxxu_llt_write(priv, i, (i + 1));
2619                 if (ret)
2620                         goto exit;
2621         }
2622
2623         /*  Let last entry point to the start entry of ring buffer */
2624         ret = rtl8xxxu_llt_write(priv, 0xff, last_tx_page + 1);
2625         if (ret)
2626                 goto exit;
2627
2628 exit:
2629         return ret;
2630 }
2631
2632 static int rtl8xxxu_init_queue_priority(struct rtl8xxxu_priv *priv)
2633 {
2634         u16 val16, hi, lo;
2635         u16 hiq, mgq, bkq, beq, viq, voq;
2636         int hip, mgp, bkp, bep, vip, vop;
2637         int ret = 0;
2638
2639         switch (priv->ep_tx_count) {
2640         case 1:
2641                 if (priv->ep_tx_high_queue) {
2642                         hi = TRXDMA_QUEUE_HIGH;
2643                 } else if (priv->ep_tx_low_queue) {
2644                         hi = TRXDMA_QUEUE_LOW;
2645                 } else if (priv->ep_tx_normal_queue) {
2646                         hi = TRXDMA_QUEUE_NORMAL;
2647                 } else {
2648                         hi = 0;
2649                         ret = -EINVAL;
2650                 }
2651
2652                 hiq = hi;
2653                 mgq = hi;
2654                 bkq = hi;
2655                 beq = hi;
2656                 viq = hi;
2657                 voq = hi;
2658
2659                 hip = 0;
2660                 mgp = 0;
2661                 bkp = 0;
2662                 bep = 0;
2663                 vip = 0;
2664                 vop = 0;
2665                 break;
2666         case 2:
2667                 if (priv->ep_tx_high_queue && priv->ep_tx_low_queue) {
2668                         hi = TRXDMA_QUEUE_HIGH;
2669                         lo = TRXDMA_QUEUE_LOW;
2670                 } else if (priv->ep_tx_normal_queue && priv->ep_tx_low_queue) {
2671                         hi = TRXDMA_QUEUE_NORMAL;
2672                         lo = TRXDMA_QUEUE_LOW;
2673                 } else if (priv->ep_tx_high_queue && priv->ep_tx_normal_queue) {
2674                         hi = TRXDMA_QUEUE_HIGH;
2675                         lo = TRXDMA_QUEUE_NORMAL;
2676                 } else {
2677                         ret = -EINVAL;
2678                         hi = 0;
2679                         lo = 0;
2680                 }
2681
2682                 hiq = hi;
2683                 mgq = hi;
2684                 bkq = lo;
2685                 beq = lo;
2686                 viq = hi;
2687                 voq = hi;
2688
2689                 hip = 0;
2690                 mgp = 0;
2691                 bkp = 1;
2692                 bep = 1;
2693                 vip = 0;
2694                 vop = 0;
2695                 break;
2696         case 3:
2697                 beq = TRXDMA_QUEUE_LOW;
2698                 bkq = TRXDMA_QUEUE_LOW;
2699                 viq = TRXDMA_QUEUE_NORMAL;
2700                 voq = TRXDMA_QUEUE_HIGH;
2701                 mgq = TRXDMA_QUEUE_HIGH;
2702                 hiq = TRXDMA_QUEUE_HIGH;
2703
2704                 hip = hiq ^ 3;
2705                 mgp = mgq ^ 3;
2706                 bkp = bkq ^ 3;
2707                 bep = beq ^ 3;
2708                 vip = viq ^ 3;
2709                 vop = viq ^ 3;
2710                 break;
2711         default:
2712                 ret = -EINVAL;
2713         }
2714
2715         /*
2716          * None of the vendor drivers are configuring the beacon
2717          * queue here .... why?
2718          */
2719         if (!ret) {
2720                 val16 = rtl8xxxu_read16(priv, REG_TRXDMA_CTRL);
2721                 val16 &= 0x7;
2722                 val16 |= (voq << TRXDMA_CTRL_VOQ_SHIFT) |
2723                         (viq << TRXDMA_CTRL_VIQ_SHIFT) |
2724                         (beq << TRXDMA_CTRL_BEQ_SHIFT) |
2725                         (bkq << TRXDMA_CTRL_BKQ_SHIFT) |
2726                         (mgq << TRXDMA_CTRL_MGQ_SHIFT) |
2727                         (hiq << TRXDMA_CTRL_HIQ_SHIFT);
2728                 rtl8xxxu_write16(priv, REG_TRXDMA_CTRL, val16);
2729
2730                 priv->pipe_out[TXDESC_QUEUE_VO] =
2731                         usb_sndbulkpipe(priv->udev, priv->out_ep[vop]);
2732                 priv->pipe_out[TXDESC_QUEUE_VI] =
2733                         usb_sndbulkpipe(priv->udev, priv->out_ep[vip]);
2734                 priv->pipe_out[TXDESC_QUEUE_BE] =
2735                         usb_sndbulkpipe(priv->udev, priv->out_ep[bep]);
2736                 priv->pipe_out[TXDESC_QUEUE_BK] =
2737                         usb_sndbulkpipe(priv->udev, priv->out_ep[bkp]);
2738                 priv->pipe_out[TXDESC_QUEUE_BEACON] =
2739                         usb_sndbulkpipe(priv->udev, priv->out_ep[0]);
2740                 priv->pipe_out[TXDESC_QUEUE_MGNT] =
2741                         usb_sndbulkpipe(priv->udev, priv->out_ep[mgp]);
2742                 priv->pipe_out[TXDESC_QUEUE_HIGH] =
2743                         usb_sndbulkpipe(priv->udev, priv->out_ep[hip]);
2744                 priv->pipe_out[TXDESC_QUEUE_CMD] =
2745                         usb_sndbulkpipe(priv->udev, priv->out_ep[0]);
2746         }
2747
2748         return ret;
2749 }
2750
2751 static void rtl8xxxu_fill_iqk_matrix_a(struct rtl8xxxu_priv *priv,
2752                                        bool iqk_ok, int result[][8],
2753                                        int candidate, bool tx_only)
2754 {
2755         u32 oldval, x, tx0_a, reg;
2756         int y, tx0_c;
2757         u32 val32;
2758
2759         if (!iqk_ok)
2760                 return;
2761
2762         val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE);
2763         oldval = val32 >> 22;
2764
2765         x = result[candidate][0];
2766         if ((x & 0x00000200) != 0)
2767                 x = x | 0xfffffc00;
2768         tx0_a = (x * oldval) >> 8;
2769
2770         val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE);
2771         val32 &= ~0x3ff;
2772         val32 |= tx0_a;
2773         rtl8xxxu_write32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE, val32);
2774
2775         val32 = rtl8xxxu_read32(priv, REG_OFDM0_ENERGY_CCA_THRES);
2776         val32 &= ~BIT(31);
2777         if ((x * oldval >> 7) & 0x1)
2778                 val32 |= BIT(31);
2779         rtl8xxxu_write32(priv, REG_OFDM0_ENERGY_CCA_THRES, val32);
2780
2781         y = result[candidate][1];
2782         if ((y & 0x00000200) != 0)
2783                 y = y | 0xfffffc00;
2784         tx0_c = (y * oldval) >> 8;
2785
2786         val32 = rtl8xxxu_read32(priv, REG_OFDM0_XC_TX_AFE);
2787         val32 &= ~0xf0000000;
2788         val32 |= (((tx0_c & 0x3c0) >> 6) << 28);
2789         rtl8xxxu_write32(priv, REG_OFDM0_XC_TX_AFE, val32);
2790
2791         val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE);
2792         val32 &= ~0x003f0000;
2793         val32 |= ((tx0_c & 0x3f) << 16);
2794         rtl8xxxu_write32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE, val32);
2795
2796         val32 = rtl8xxxu_read32(priv, REG_OFDM0_ENERGY_CCA_THRES);
2797         val32 &= ~BIT(29);
2798         if ((y * oldval >> 7) & 0x1)
2799                 val32 |= BIT(29);
2800         rtl8xxxu_write32(priv, REG_OFDM0_ENERGY_CCA_THRES, val32);
2801
2802         if (tx_only) {
2803                 dev_dbg(&priv->udev->dev, "%s: only TX\n", __func__);
2804                 return;
2805         }
2806
2807         reg = result[candidate][2];
2808
2809         val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_RX_IQ_IMBALANCE);
2810         val32 &= ~0x3ff;
2811         val32 |= (reg & 0x3ff);
2812         rtl8xxxu_write32(priv, REG_OFDM0_XA_RX_IQ_IMBALANCE, val32);
2813
2814         reg = result[candidate][3] & 0x3F;
2815
2816         val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_RX_IQ_IMBALANCE);
2817         val32 &= ~0xfc00;
2818         val32 |= ((reg << 10) & 0xfc00);
2819         rtl8xxxu_write32(priv, REG_OFDM0_XA_RX_IQ_IMBALANCE, val32);
2820
2821         reg = (result[candidate][3] >> 6) & 0xF;
2822
2823         val32 = rtl8xxxu_read32(priv, REG_OFDM0_RX_IQ_EXT_ANTA);
2824         val32 &= ~0xf0000000;
2825         val32 |= (reg << 28);
2826         rtl8xxxu_write32(priv, REG_OFDM0_RX_IQ_EXT_ANTA, val32);
2827 }
2828
2829 static void rtl8xxxu_fill_iqk_matrix_b(struct rtl8xxxu_priv *priv,
2830                                        bool iqk_ok, int result[][8],
2831                                        int candidate, bool tx_only)
2832 {
2833         u32 oldval, x, tx1_a, reg;
2834         int y, tx1_c;
2835         u32 val32;
2836
2837         if (!iqk_ok)
2838                 return;
2839
2840         val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE);
2841         oldval = val32 >> 22;
2842
2843         x = result[candidate][4];
2844         if ((x & 0x00000200) != 0)
2845                 x = x | 0xfffffc00;
2846         tx1_a = (x * oldval) >> 8;
2847
2848         val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE);
2849         val32 &= ~0x3ff;
2850         val32 |= tx1_a;
2851         rtl8xxxu_write32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE, val32);
2852
2853         val32 = rtl8xxxu_read32(priv, REG_OFDM0_ENERGY_CCA_THRES);
2854         val32 &= ~BIT(27);
2855         if ((x * oldval >> 7) & 0x1)
2856                 val32 |= BIT(27);
2857         rtl8xxxu_write32(priv, REG_OFDM0_ENERGY_CCA_THRES, val32);
2858
2859         y = result[candidate][5];
2860         if ((y & 0x00000200) != 0)
2861                 y = y | 0xfffffc00;
2862         tx1_c = (y * oldval) >> 8;
2863
2864         val32 = rtl8xxxu_read32(priv, REG_OFDM0_XD_TX_AFE);
2865         val32 &= ~0xf0000000;
2866         val32 |= (((tx1_c & 0x3c0) >> 6) << 28);
2867         rtl8xxxu_write32(priv, REG_OFDM0_XD_TX_AFE, val32);
2868
2869         val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE);
2870         val32 &= ~0x003f0000;
2871         val32 |= ((tx1_c & 0x3f) << 16);
2872         rtl8xxxu_write32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE, val32);
2873
2874         val32 = rtl8xxxu_read32(priv, REG_OFDM0_ENERGY_CCA_THRES);
2875         val32 &= ~BIT(25);
2876         if ((y * oldval >> 7) & 0x1)
2877                 val32 |= BIT(25);
2878         rtl8xxxu_write32(priv, REG_OFDM0_ENERGY_CCA_THRES, val32);
2879
2880         if (tx_only) {
2881                 dev_dbg(&priv->udev->dev, "%s: only TX\n", __func__);
2882                 return;
2883         }
2884
2885         reg = result[candidate][6];
2886
2887         val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_RX_IQ_IMBALANCE);
2888         val32 &= ~0x3ff;
2889         val32 |= (reg & 0x3ff);
2890         rtl8xxxu_write32(priv, REG_OFDM0_XB_RX_IQ_IMBALANCE, val32);
2891
2892         reg = result[candidate][7] & 0x3f;
2893
2894         val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_RX_IQ_IMBALANCE);
2895         val32 &= ~0xfc00;
2896         val32 |= ((reg << 10) & 0xfc00);
2897         rtl8xxxu_write32(priv, REG_OFDM0_XB_RX_IQ_IMBALANCE, val32);
2898
2899         reg = (result[candidate][7] >> 6) & 0xf;
2900
2901         val32 = rtl8xxxu_read32(priv, REG_OFDM0_AGCR_SSI_TABLE);
2902         val32 &= ~0x0000f000;
2903         val32 |= (reg << 12);
2904         rtl8xxxu_write32(priv, REG_OFDM0_AGCR_SSI_TABLE, val32);
2905 }
2906
2907 #define MAX_TOLERANCE           5
2908
2909 static bool rtl8xxxu_simularity_compare(struct rtl8xxxu_priv *priv,
2910                                         int result[][8], int c1, int c2)
2911 {
2912         u32 i, j, diff, simubitmap, bound = 0;
2913         int candidate[2] = {-1, -1};    /* for path A and path B */
2914         bool retval = true;
2915
2916         if (priv->tx_paths > 1)
2917                 bound = 8;
2918         else
2919                 bound = 4;
2920
2921         simubitmap = 0;
2922
2923         for (i = 0; i < bound; i++) {
2924                 diff = (result[c1][i] > result[c2][i]) ?
2925                         (result[c1][i] - result[c2][i]) :
2926                         (result[c2][i] - result[c1][i]);
2927                 if (diff > MAX_TOLERANCE) {
2928                         if ((i == 2 || i == 6) && !simubitmap) {
2929                                 if (result[c1][i] + result[c1][i + 1] == 0)
2930                                         candidate[(i / 4)] = c2;
2931                                 else if (result[c2][i] + result[c2][i + 1] == 0)
2932                                         candidate[(i / 4)] = c1;
2933                                 else
2934                                         simubitmap = simubitmap | (1 << i);
2935                         } else {
2936                                 simubitmap = simubitmap | (1 << i);
2937                         }
2938                 }
2939         }
2940
2941         if (simubitmap == 0) {
2942                 for (i = 0; i < (bound / 4); i++) {
2943                         if (candidate[i] >= 0) {
2944                                 for (j = i * 4; j < (i + 1) * 4 - 2; j++)
2945                                         result[3][j] = result[candidate[i]][j];
2946                                 retval = false;
2947                         }
2948                 }
2949                 return retval;
2950         } else if (!(simubitmap & 0x0f)) {
2951                 /* path A OK */
2952                 for (i = 0; i < 4; i++)
2953                         result[3][i] = result[c1][i];
2954         } else if (!(simubitmap & 0xf0) && priv->tx_paths > 1) {
2955                 /* path B OK */
2956                 for (i = 4; i < 8; i++)
2957                         result[3][i] = result[c1][i];
2958         }
2959
2960         return false;
2961 }
2962
2963 static void
2964 rtl8xxxu_save_mac_regs(struct rtl8xxxu_priv *priv, const u32 *reg, u32 *backup)
2965 {
2966         int i;
2967
2968         for (i = 0; i < (RTL8XXXU_MAC_REGS - 1); i++)
2969                 backup[i] = rtl8xxxu_read8(priv, reg[i]);
2970
2971         backup[i] = rtl8xxxu_read32(priv, reg[i]);
2972 }
2973
2974 static void rtl8xxxu_restore_mac_regs(struct rtl8xxxu_priv *priv,
2975                                       const u32 *reg, u32 *backup)
2976 {
2977         int i;
2978
2979         for (i = 0; i < (RTL8XXXU_MAC_REGS - 1); i++)
2980                 rtl8xxxu_write8(priv, reg[i], backup[i]);
2981
2982         rtl8xxxu_write32(priv, reg[i], backup[i]);
2983 }
2984
2985 static void rtl8xxxu_save_regs(struct rtl8xxxu_priv *priv, const u32 *regs,
2986                                u32 *backup, int count)
2987 {
2988         int i;
2989
2990         for (i = 0; i < count; i++)
2991                 backup[i] = rtl8xxxu_read32(priv, regs[i]);
2992 }
2993
2994 static void rtl8xxxu_restore_regs(struct rtl8xxxu_priv *priv, const u32 *regs,
2995                                   u32 *backup, int count)
2996 {
2997         int i;
2998
2999         for (i = 0; i < count; i++)
3000                 rtl8xxxu_write32(priv, regs[i], backup[i]);
3001 }
3002
3003
3004 static void rtl8xxxu_path_adda_on(struct rtl8xxxu_priv *priv, const u32 *regs,
3005                                   bool path_a_on)
3006 {
3007         u32 path_on;
3008         int i;
3009
3010         path_on = path_a_on ? 0x04db25a4 : 0x0b1b25a4;
3011         if (priv->tx_paths == 1) {
3012                 path_on = 0x0bdb25a0;
3013                 rtl8xxxu_write32(priv, regs[0], 0x0b1b25a0);
3014         } else {
3015                 rtl8xxxu_write32(priv, regs[0], path_on);
3016         }
3017
3018         for (i = 1 ; i < RTL8XXXU_ADDA_REGS ; i++)
3019                 rtl8xxxu_write32(priv, regs[i], path_on);
3020 }
3021
3022 static void rtl8xxxu_mac_calibration(struct rtl8xxxu_priv *priv,
3023                                      const u32 *regs, u32 *backup)
3024 {
3025         int i = 0;
3026
3027         rtl8xxxu_write8(priv, regs[i], 0x3f);
3028
3029         for (i = 1 ; i < (RTL8XXXU_MAC_REGS - 1); i++)
3030                 rtl8xxxu_write8(priv, regs[i], (u8)(backup[i] & ~BIT(3)));
3031
3032         rtl8xxxu_write8(priv, regs[i], (u8)(backup[i] & ~BIT(5)));
3033 }
3034
3035 static int rtl8xxxu_iqk_path_a(struct rtl8xxxu_priv *priv)
3036 {
3037         u32 reg_eac, reg_e94, reg_e9c, reg_ea4, val32;
3038         int result = 0;
3039
3040         /* path-A IQK setting */
3041         rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x10008c1f);
3042         rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x10008c1f);
3043         rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x82140102);
3044
3045         val32 = (priv->rf_paths > 1) ? 0x28160202 :
3046                 /*IS_81xxC_VENDOR_UMC_B_CUT(pHalData->VersionID)?0x28160202: */
3047                 0x28160502;
3048         rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, val32);
3049
3050         /* path-B IQK setting */
3051         if (priv->rf_paths > 1) {
3052                 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x10008c22);
3053                 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x10008c22);
3054                 rtl8xxxu_write32(priv, REG_TX_IQK_PI_B, 0x82140102);
3055                 rtl8xxxu_write32(priv, REG_RX_IQK_PI_B, 0x28160202);
3056         }
3057
3058         /* LO calibration setting */
3059         rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x001028d1);
3060
3061         /* One shot, path A LOK & IQK */
3062         rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf9000000);
3063         rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000);
3064
3065         mdelay(1);
3066
3067         /* Check failed */
3068         reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2);
3069         reg_e94 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_A);
3070         reg_e9c = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_A);
3071         reg_ea4 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_A_2);
3072
3073         if (!(reg_eac & BIT(28)) &&
3074             ((reg_e94 & 0x03ff0000) != 0x01420000) &&
3075             ((reg_e9c & 0x03ff0000) != 0x00420000))
3076                 result |= 0x01;
3077         else    /* If TX not OK, ignore RX */
3078                 goto out;
3079
3080         /* If TX is OK, check whether RX is OK */
3081         if (!(reg_eac & BIT(27)) &&
3082             ((reg_ea4 & 0x03ff0000) != 0x01320000) &&
3083             ((reg_eac & 0x03ff0000) != 0x00360000))
3084                 result |= 0x02;
3085         else
3086                 dev_warn(&priv->udev->dev, "%s: Path A RX IQK failed!\n",
3087                          __func__);
3088 out:
3089         return result;
3090 }
3091
3092 static int rtl8xxxu_iqk_path_b(struct rtl8xxxu_priv *priv)
3093 {
3094         u32 reg_eac, reg_eb4, reg_ebc, reg_ec4, reg_ecc;
3095         int result = 0;
3096
3097         /* One shot, path B LOK & IQK */
3098         rtl8xxxu_write32(priv, REG_IQK_AGC_CONT, 0x00000002);
3099         rtl8xxxu_write32(priv, REG_IQK_AGC_CONT, 0x00000000);
3100
3101         mdelay(1);
3102
3103         /* Check failed */
3104         reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2);
3105         reg_eb4 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B);
3106         reg_ebc = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B);
3107         reg_ec4 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_B_2);
3108         reg_ecc = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_B_2);
3109
3110         if (!(reg_eac & BIT(31)) &&
3111             ((reg_eb4 & 0x03ff0000) != 0x01420000) &&
3112             ((reg_ebc & 0x03ff0000) != 0x00420000))
3113                 result |= 0x01;
3114         else
3115                 goto out;
3116
3117         if (!(reg_eac & BIT(30)) &&
3118             (((reg_ec4 & 0x03ff0000) >> 16) != 0x132) &&
3119             (((reg_ecc & 0x03ff0000) >> 16) != 0x36))
3120                 result |= 0x02;
3121         else
3122                 dev_warn(&priv->udev->dev, "%s: Path B RX IQK failed!\n",
3123                          __func__);
3124 out:
3125         return result;
3126 }
3127
3128 static void rtl8xxxu_phy_iqcalibrate(struct rtl8xxxu_priv *priv,
3129                                      int result[][8], int t)
3130 {
3131         struct device *dev = &priv->udev->dev;
3132         u32 i, val32;
3133         int path_a_ok, path_b_ok;
3134         int retry = 2;
3135         const u32 adda_regs[RTL8XXXU_ADDA_REGS] = {
3136                 REG_FPGA0_XCD_SWITCH_CTRL, REG_BLUETOOTH,
3137                 REG_RX_WAIT_CCA, REG_TX_CCK_RFON,
3138                 REG_TX_CCK_BBON, REG_TX_OFDM_RFON,
3139                 REG_TX_OFDM_BBON, REG_TX_TO_RX,
3140                 REG_TX_TO_TX, REG_RX_CCK,
3141                 REG_RX_OFDM, REG_RX_WAIT_RIFS,
3142                 REG_RX_TO_RX, REG_STANDBY,
3143                 REG_SLEEP, REG_PMPD_ANAEN
3144         };
3145         const u32 iqk_mac_regs[RTL8XXXU_MAC_REGS] = {
3146                 REG_TXPAUSE, REG_BEACON_CTRL,
3147                 REG_BEACON_CTRL_1, REG_GPIO_MUXCFG
3148         };
3149         const u32 iqk_bb_regs[RTL8XXXU_BB_REGS] = {
3150                 REG_OFDM0_TRX_PATH_ENABLE, REG_OFDM0_TR_MUX_PAR,
3151                 REG_FPGA0_XCD_RF_SW_CTRL, REG_CONFIG_ANT_A, REG_CONFIG_ANT_B,
3152                 REG_FPGA0_XAB_RF_SW_CTRL, REG_FPGA0_XA_RF_INT_OE,
3153                 REG_FPGA0_XB_RF_INT_OE, REG_FPGA0_RF_MODE
3154         };
3155
3156         /*
3157          * Note: IQ calibration must be performed after loading
3158          *       PHY_REG.txt , and radio_a, radio_b.txt
3159          */
3160
3161         if (t == 0) {
3162                 /* Save ADDA parameters, turn Path A ADDA on */
3163                 rtl8xxxu_save_regs(priv, adda_regs, priv->adda_backup,
3164                                    RTL8XXXU_ADDA_REGS);
3165                 rtl8xxxu_save_mac_regs(priv, iqk_mac_regs, priv->mac_backup);
3166                 rtl8xxxu_save_regs(priv, iqk_bb_regs,
3167                                    priv->bb_backup, RTL8XXXU_BB_REGS);
3168         }
3169
3170         rtl8xxxu_path_adda_on(priv, adda_regs, true);
3171
3172         if (t == 0) {
3173                 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XA_HSSI_PARM1);
3174                 if (val32 & FPGA0_HSSI_PARM1_PI)
3175                         priv->pi_enabled = 1;
3176         }
3177
3178         if (!priv->pi_enabled) {
3179                 /* Switch BB to PI mode to do IQ Calibration. */
3180                 rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM1, 0x01000100);
3181                 rtl8xxxu_write32(priv, REG_FPGA0_XB_HSSI_PARM1, 0x01000100);
3182         }
3183
3184         val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
3185         val32 &= ~FPGA_RF_MODE_CCK;
3186         rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
3187
3188         rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, 0x03a05600);
3189         rtl8xxxu_write32(priv, REG_OFDM0_TR_MUX_PAR, 0x000800e4);
3190         rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_SW_CTRL, 0x22204000);
3191
3192         val32 = rtl8xxxu_read32(priv, REG_FPGA0_XAB_RF_SW_CTRL);
3193         val32 |= (FPGA0_RF_PAPE | (FPGA0_RF_PAPE << FPGA0_RF_BD_CTRL_SHIFT));
3194         rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_SW_CTRL, val32);
3195
3196         val32 = rtl8xxxu_read32(priv, REG_FPGA0_XA_RF_INT_OE);
3197         val32 &= ~BIT(10);
3198         rtl8xxxu_write32(priv, REG_FPGA0_XA_RF_INT_OE, val32);
3199         val32 = rtl8xxxu_read32(priv, REG_FPGA0_XB_RF_INT_OE);
3200         val32 &= ~BIT(10);
3201         rtl8xxxu_write32(priv, REG_FPGA0_XB_RF_INT_OE, val32);
3202
3203         if (priv->tx_paths > 1) {
3204                 rtl8xxxu_write32(priv, REG_FPGA0_XA_LSSI_PARM, 0x00010000);
3205                 rtl8xxxu_write32(priv, REG_FPGA0_XB_LSSI_PARM, 0x00010000);
3206         }
3207
3208         /* MAC settings */
3209         rtl8xxxu_mac_calibration(priv, iqk_mac_regs, priv->mac_backup);
3210
3211         /* Page B init */
3212         rtl8xxxu_write32(priv, REG_CONFIG_ANT_A, 0x00080000);
3213
3214         if (priv->tx_paths > 1)
3215                 rtl8xxxu_write32(priv, REG_CONFIG_ANT_B, 0x00080000);
3216
3217         /* IQ calibration setting */
3218         rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000);
3219         rtl8xxxu_write32(priv, REG_TX_IQK, 0x01007c00);
3220         rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800);
3221
3222         for (i = 0; i < retry; i++) {
3223                 path_a_ok = rtl8xxxu_iqk_path_a(priv);
3224                 if (path_a_ok == 0x03) {
3225                         val32 = rtl8xxxu_read32(priv,
3226                                                 REG_TX_POWER_BEFORE_IQK_A);
3227                         result[t][0] = (val32 >> 16) & 0x3ff;
3228                         val32 = rtl8xxxu_read32(priv,
3229                                                 REG_TX_POWER_AFTER_IQK_A);
3230                         result[t][1] = (val32 >> 16) & 0x3ff;
3231                         val32 = rtl8xxxu_read32(priv,
3232                                                 REG_RX_POWER_BEFORE_IQK_A_2);
3233                         result[t][2] = (val32 >> 16) & 0x3ff;
3234                         val32 = rtl8xxxu_read32(priv,
3235                                                 REG_RX_POWER_AFTER_IQK_A_2);
3236                         result[t][3] = (val32 >> 16) & 0x3ff;
3237                         break;
3238                 } else if (i == (retry - 1) && path_a_ok == 0x01) {
3239                         /* TX IQK OK */
3240                         dev_dbg(dev, "%s: Path A IQK Only Tx Success!!\n",
3241                                 __func__);
3242
3243                         val32 = rtl8xxxu_read32(priv,
3244                                                 REG_TX_POWER_BEFORE_IQK_A);
3245                         result[t][0] = (val32 >> 16) & 0x3ff;
3246                         val32 = rtl8xxxu_read32(priv,
3247                                                 REG_TX_POWER_AFTER_IQK_A);
3248                         result[t][1] = (val32 >> 16) & 0x3ff;
3249                 }
3250         }
3251
3252         if (!path_a_ok)
3253                 dev_dbg(dev, "%s: Path A IQK failed!\n", __func__);
3254
3255         if (priv->tx_paths > 1) {
3256                 /*
3257                  * Path A into standby
3258                  */
3259                 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x0);
3260                 rtl8xxxu_write32(priv, REG_FPGA0_XA_LSSI_PARM, 0x00010000);
3261                 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000);
3262
3263                 /* Turn Path B ADDA on */
3264                 rtl8xxxu_path_adda_on(priv, adda_regs, false);
3265
3266                 for (i = 0; i < retry; i++) {
3267                         path_b_ok = rtl8xxxu_iqk_path_b(priv);
3268                         if (path_b_ok == 0x03) {
3269                                 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B);
3270                                 result[t][4] = (val32 >> 16) & 0x3ff;
3271                                 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B);
3272                                 result[t][5] = (val32 >> 16) & 0x3ff;
3273                                 val32 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_B_2);
3274                                 result[t][6] = (val32 >> 16) & 0x3ff;
3275                                 val32 = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_B_2);
3276                                 result[t][7] = (val32 >> 16) & 0x3ff;
3277                                 break;
3278                         } else if (i == (retry - 1) && path_b_ok == 0x01) {
3279                                 /* TX IQK OK */
3280                                 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B);
3281                                 result[t][4] = (val32 >> 16) & 0x3ff;
3282                                 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B);
3283                                 result[t][5] = (val32 >> 16) & 0x3ff;
3284                         }
3285                 }
3286
3287                 if (!path_b_ok)
3288                         dev_dbg(dev, "%s: Path B IQK failed!\n", __func__);
3289         }
3290
3291         /* Back to BB mode, load original value */
3292         rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0);
3293
3294         if (t) {
3295                 if (!priv->pi_enabled) {
3296                         /*
3297                          * Switch back BB to SI mode after finishing
3298                          * IQ Calibration
3299                          */
3300                         val32 = 0x01000000;
3301                         rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM1, val32);
3302                         rtl8xxxu_write32(priv, REG_FPGA0_XB_HSSI_PARM1, val32);
3303                 }
3304
3305                 /* Reload ADDA power saving parameters */
3306                 rtl8xxxu_restore_regs(priv, adda_regs, priv->adda_backup,
3307                                       RTL8XXXU_ADDA_REGS);
3308
3309                 /* Reload MAC parameters */
3310                 rtl8xxxu_restore_mac_regs(priv, iqk_mac_regs, priv->mac_backup);
3311
3312                 /* Reload BB parameters */
3313                 rtl8xxxu_restore_regs(priv, iqk_bb_regs,
3314                                       priv->bb_backup, RTL8XXXU_BB_REGS);
3315
3316                 /* Restore RX initial gain */
3317                 rtl8xxxu_write32(priv, REG_FPGA0_XA_LSSI_PARM, 0x00032ed3);
3318
3319                 if (priv->tx_paths > 1) {
3320                         rtl8xxxu_write32(priv, REG_FPGA0_XB_LSSI_PARM,
3321                                          0x00032ed3);
3322                 }
3323
3324                 /* Load 0xe30 IQC default value */
3325                 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x01008c00);
3326                 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x01008c00);
3327         }
3328 }
3329
3330 static void rtl8723a_phy_iq_calibrate(struct rtl8xxxu_priv *priv)
3331 {
3332         struct device *dev = &priv->udev->dev;
3333         int result[4][8];       /* last is final result */
3334         int i, candidate;
3335         bool path_a_ok, path_b_ok;
3336         u32 reg_e94, reg_e9c, reg_ea4, reg_eac;
3337         u32 reg_eb4, reg_ebc, reg_ec4, reg_ecc;
3338         s32 reg_tmp = 0;
3339         bool simu;
3340
3341         memset(result, 0, sizeof(result));
3342         candidate = -1;
3343
3344         path_a_ok = false;
3345         path_b_ok = false;
3346
3347         rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
3348
3349         for (i = 0; i < 3; i++) {
3350                 rtl8xxxu_phy_iqcalibrate(priv, result, i);
3351
3352                 if (i == 1) {
3353                         simu = rtl8xxxu_simularity_compare(priv, result, 0, 1);
3354                         if (simu) {
3355                                 candidate = 0;
3356                                 break;
3357                         }
3358                 }
3359
3360                 if (i == 2) {
3361                         simu = rtl8xxxu_simularity_compare(priv, result, 0, 2);
3362                         if (simu) {
3363                                 candidate = 0;
3364                                 break;
3365                         }
3366
3367                         simu = rtl8xxxu_simularity_compare(priv, result, 1, 2);
3368                         if (simu) {
3369                                 candidate = 1;
3370                         } else {
3371                                 for (i = 0; i < 8; i++)
3372                                         reg_tmp += result[3][i];
3373
3374                                 if (reg_tmp)
3375                                         candidate = 3;
3376                                 else
3377                                         candidate = -1;
3378                         }
3379                 }
3380         }
3381
3382         for (i = 0; i < 4; i++) {
3383                 reg_e94 = result[i][0];
3384                 reg_e9c = result[i][1];
3385                 reg_ea4 = result[i][2];
3386                 reg_eac = result[i][3];
3387                 reg_eb4 = result[i][4];
3388                 reg_ebc = result[i][5];
3389                 reg_ec4 = result[i][6];
3390                 reg_ecc = result[i][7];
3391         }
3392
3393         if (candidate >= 0) {
3394                 reg_e94 = result[candidate][0];
3395                 priv->rege94 =  reg_e94;
3396                 reg_e9c = result[candidate][1];
3397                 priv->rege9c = reg_e9c;
3398                 reg_ea4 = result[candidate][2];
3399                 reg_eac = result[candidate][3];
3400                 reg_eb4 = result[candidate][4];
3401                 priv->regeb4 = reg_eb4;
3402                 reg_ebc = result[candidate][5];
3403                 priv->regebc = reg_ebc;
3404                 reg_ec4 = result[candidate][6];
3405                 reg_ecc = result[candidate][7];
3406                 dev_dbg(dev, "%s: candidate is %x\n", __func__, candidate);
3407                 dev_dbg(dev,
3408                         "%s: e94 =%x e9c=%x ea4=%x eac=%x eb4=%x ebc=%x ec4=%x "
3409                         "ecc=%x\n ", __func__, reg_e94, reg_e9c,
3410                         reg_ea4, reg_eac, reg_eb4, reg_ebc, reg_ec4, reg_ecc);
3411                 path_a_ok = true;
3412                 path_b_ok = true;
3413         } else {
3414                 reg_e94 = reg_eb4 = priv->rege94 = priv->regeb4 = 0x100;
3415                 reg_e9c = reg_ebc = priv->rege9c = priv->regebc = 0x0;
3416         }
3417
3418         if (reg_e94 && candidate >= 0)
3419                 rtl8xxxu_fill_iqk_matrix_a(priv, path_a_ok, result,
3420                                            candidate, (reg_ea4 == 0));
3421
3422         if (priv->tx_paths > 1 && reg_eb4)
3423                 rtl8xxxu_fill_iqk_matrix_b(priv, path_b_ok, result,
3424                                            candidate, (reg_ec4 == 0));
3425
3426         rtl8xxxu_save_regs(priv, rtl8723au_iqk_phy_iq_bb_reg,
3427                            priv->bb_recovery_backup, RTL8XXXU_BB_REGS);
3428 }
3429
3430 static void rtl8723a_phy_lc_calibrate(struct rtl8xxxu_priv *priv)
3431 {
3432         u32 val32;
3433         u32 rf_amode, rf_bmode = 0, lstf;
3434
3435         /* Check continuous TX and Packet TX */
3436         lstf = rtl8xxxu_read32(priv, REG_OFDM1_LSTF);
3437
3438         if (lstf & OFDM_LSTF_MASK) {
3439                 /* Disable all continuous TX */
3440                 val32 = lstf & ~OFDM_LSTF_MASK;
3441                 rtl8xxxu_write32(priv, REG_OFDM1_LSTF, val32);
3442
3443                 /* Read original RF mode Path A */
3444                 rf_amode = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_AC);
3445
3446                 /* Set RF mode to standby Path A */
3447                 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC,
3448                                      (rf_amode & 0x8ffff) | 0x10000);
3449
3450                 /* Path-B */
3451                 if (priv->tx_paths > 1) {
3452                         rf_bmode = rtl8xxxu_read_rfreg(priv, RF_B,
3453                                                        RF6052_REG_AC);
3454
3455                         rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_AC,
3456                                              (rf_bmode & 0x8ffff) | 0x10000);
3457                 }
3458         } else {
3459                 /*  Deal with Packet TX case */
3460                 /*  block all queues */
3461                 rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff);
3462         }
3463
3464         /* Start LC calibration */
3465         val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_MODE_AG);
3466         val32 |= 0x08000;
3467         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_MODE_AG, val32);
3468
3469         msleep(100);
3470
3471         /* Restore original parameters */
3472         if (lstf & OFDM_LSTF_MASK) {
3473                 /* Path-A */
3474                 rtl8xxxu_write32(priv, REG_OFDM1_LSTF, lstf);
3475                 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC, rf_amode);
3476
3477                 /* Path-B */
3478                 if (priv->tx_paths > 1)
3479                         rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_AC,
3480                                              rf_bmode);
3481         } else /*  Deal with Packet TX case */
3482                 rtl8xxxu_write8(priv, REG_TXPAUSE, 0x00);
3483 }
3484
3485 static int rtl8xxxu_set_mac(struct rtl8xxxu_priv *priv)
3486 {
3487         int i;
3488         u16 reg;
3489
3490         reg = REG_MACID;
3491
3492         for (i = 0; i < ETH_ALEN; i++)
3493                 rtl8xxxu_write8(priv, reg + i, priv->mac_addr[i]);
3494
3495         return 0;
3496 }
3497
3498 static int rtl8xxxu_set_bssid(struct rtl8xxxu_priv *priv, const u8 *bssid)
3499 {
3500         int i;
3501         u16 reg;
3502
3503         dev_dbg(&priv->udev->dev, "%s: (%pM)\n", __func__, bssid);
3504
3505         reg = REG_BSSID;
3506
3507         for (i = 0; i < ETH_ALEN; i++)
3508                 rtl8xxxu_write8(priv, reg + i, bssid[i]);
3509
3510         return 0;
3511 }
3512
3513 static void
3514 rtl8xxxu_set_ampdu_factor(struct rtl8xxxu_priv *priv, u8 ampdu_factor)
3515 {
3516         u8 vals[4] = { 0x41, 0xa8, 0x72, 0xb9 };
3517         u8 max_agg = 0xf;
3518         int i;
3519
3520         ampdu_factor = 1 << (ampdu_factor + 2);
3521         if (ampdu_factor > max_agg)
3522                 ampdu_factor = max_agg;
3523
3524         for (i = 0; i < 4; i++) {
3525                 if ((vals[i] & 0xf0) > (ampdu_factor << 4))
3526                         vals[i] = (vals[i] & 0x0f) | (ampdu_factor << 4);
3527
3528                 if ((vals[i] & 0x0f) > ampdu_factor)
3529                         vals[i] = (vals[i] & 0xf0) | ampdu_factor;
3530
3531                 rtl8xxxu_write8(priv, REG_AGGLEN_LMT + i, vals[i]);
3532         }
3533 }
3534
3535 static void rtl8xxxu_set_ampdu_min_space(struct rtl8xxxu_priv *priv, u8 density)
3536 {
3537         u8 val8;
3538
3539         val8 = rtl8xxxu_read8(priv, REG_AMPDU_MIN_SPACE);
3540         val8 &= 0xf8;
3541         val8 |= density;
3542         rtl8xxxu_write8(priv, REG_AMPDU_MIN_SPACE, val8);
3543 }
3544
3545 static int rtl8xxxu_active_to_emu(struct rtl8xxxu_priv *priv)
3546 {
3547         u8 val8;
3548         int count, ret;
3549
3550         /* Start of rtl8723AU_card_enable_flow */
3551         /* Act to Cardemu sequence*/
3552         /* Turn off RF */
3553         rtl8xxxu_write8(priv, REG_RF_CTRL, 0);
3554
3555         /* 0x004E[7] = 0, switch DPDT_SEL_P output from register 0x0065[2] */
3556         val8 = rtl8xxxu_read8(priv, REG_LEDCFG2);
3557         val8 &= ~LEDCFG2_DPDT_SELECT;
3558         rtl8xxxu_write8(priv, REG_LEDCFG2, val8);
3559
3560         /* 0x0005[1] = 1 turn off MAC by HW state machine*/
3561         val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
3562         val8 |= BIT(1);
3563         rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
3564
3565         for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
3566                 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
3567                 if ((val8 & BIT(1)) == 0)
3568                         break;
3569                 udelay(10);
3570         }
3571
3572         if (!count) {
3573                 dev_warn(&priv->udev->dev, "%s: Disabling MAC timed out\n",
3574                          __func__);
3575                 ret = -EBUSY;
3576                 goto exit;
3577         }
3578
3579         /* 0x0000[5] = 1 analog Ips to digital, 1:isolation */
3580         val8 = rtl8xxxu_read8(priv, REG_SYS_ISO_CTRL);
3581         val8 |= SYS_ISO_ANALOG_IPS;
3582         rtl8xxxu_write8(priv, REG_SYS_ISO_CTRL, val8);
3583
3584         /* 0x0020[0] = 0 disable LDOA12 MACRO block*/
3585         val8 = rtl8xxxu_read8(priv, REG_LDOA15_CTRL);
3586         val8 &= ~LDOA15_ENABLE;
3587         rtl8xxxu_write8(priv, REG_LDOA15_CTRL, val8);
3588
3589 exit:
3590         return ret;
3591 }
3592
3593 static int rtl8xxxu_active_to_lps(struct rtl8xxxu_priv *priv)
3594 {
3595         u8 val8;
3596         u8 val32;
3597         int count, ret;
3598
3599         rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff);
3600
3601         /*
3602          * Poll - wait for RX packet to complete
3603          */
3604         for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
3605                 val32 = rtl8xxxu_read32(priv, 0x5f8);
3606                 if (!val32)
3607                         break;
3608                 udelay(10);
3609         }
3610
3611         if (!count) {
3612                 dev_warn(&priv->udev->dev,
3613                          "%s: RX poll timed out (0x05f8)\n", __func__);
3614                 ret = -EBUSY;
3615                 goto exit;
3616         }
3617
3618         /* Disable CCK and OFDM, clock gated */
3619         val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC);
3620         val8 &= ~SYS_FUNC_BBRSTB;
3621         rtl8xxxu_write8(priv, REG_SYS_FUNC, val8);
3622
3623         udelay(2);
3624
3625         /* Reset baseband */
3626         val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC);
3627         val8 &= ~SYS_FUNC_BB_GLB_RSTN;
3628         rtl8xxxu_write8(priv, REG_SYS_FUNC, val8);
3629
3630         /* Reset MAC TRX */
3631         val8 = rtl8xxxu_read8(priv, REG_CR);
3632         val8 = CR_HCI_TXDMA_ENABLE | CR_HCI_RXDMA_ENABLE;
3633         rtl8xxxu_write8(priv, REG_CR, val8);
3634
3635         /* Reset MAC TRX */
3636         val8 = rtl8xxxu_read8(priv, REG_CR + 1);
3637         val8 &= ~BIT(1); /* CR_SECURITY_ENABLE */
3638         rtl8xxxu_write8(priv, REG_CR + 1, val8);
3639
3640         /* Respond TX OK to scheduler */
3641         val8 = rtl8xxxu_read8(priv, REG_DUAL_TSF_RST);
3642         val8 |= DUAL_TSF_TX_OK;
3643         rtl8xxxu_write8(priv, REG_DUAL_TSF_RST, val8);
3644
3645 exit:
3646         return ret;
3647 }
3648
3649 static void rtl8xxxu_disabled_to_emu(struct rtl8xxxu_priv *priv)
3650 {
3651         u8 val8;
3652
3653         /* Clear suspend enable and power down enable*/
3654         val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
3655         val8 &= ~(BIT(3) | BIT(7));
3656         rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
3657
3658         /* 0x48[16] = 0 to disable GPIO9 as EXT WAKEUP*/
3659         val8 = rtl8xxxu_read8(priv, REG_GPIO_INTM + 2);
3660         val8 &= ~BIT(0);
3661         rtl8xxxu_write8(priv, REG_GPIO_INTM + 2, val8);
3662
3663         /* 0x04[12:11] = 11 enable WL suspend*/
3664         val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
3665         val8 &= ~(BIT(3) | BIT(4));
3666         rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
3667 }
3668
3669 static int rtl8xxxu_emu_to_active(struct rtl8xxxu_priv *priv)
3670 {
3671         u8 val8;
3672         u32 val32;
3673         int count, ret = 0;
3674
3675         /* 0x20[0] = 1 enable LDOA12 MACRO block for all interface*/
3676         val8 = rtl8xxxu_read8(priv, REG_LDOA15_CTRL);
3677         val8 |= LDOA15_ENABLE;
3678         rtl8xxxu_write8(priv, REG_LDOA15_CTRL, val8);
3679
3680         /* 0x67[0] = 0 to disable BT_GPS_SEL pins*/
3681         val8 = rtl8xxxu_read8(priv, 0x0067);
3682         val8 &= ~BIT(4);
3683         rtl8xxxu_write8(priv, 0x0067, val8);
3684
3685         mdelay(1);
3686
3687         /* 0x00[5] = 0 release analog Ips to digital, 1:isolation */
3688         val8 = rtl8xxxu_read8(priv, REG_SYS_ISO_CTRL);
3689         val8 &= ~SYS_ISO_ANALOG_IPS;
3690         rtl8xxxu_write8(priv, REG_SYS_ISO_CTRL, val8);
3691
3692         /* disable SW LPS 0x04[10]= 0 */
3693         val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
3694         val8 &= ~BIT(2);
3695         rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
3696
3697         /* wait till 0x04[17] = 1 power ready*/
3698         for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
3699                 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
3700                 if (val32 & BIT(17))
3701                         break;
3702
3703                 udelay(10);
3704         }
3705
3706         if (!count) {
3707                 ret = -EBUSY;
3708                 goto exit;
3709         }
3710
3711         /* We should be able to optimize the following three entries into one */
3712
3713         /* release WLON reset 0x04[16]= 1*/
3714         val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 2);
3715         val8 |= BIT(0);
3716         rtl8xxxu_write8(priv, REG_APS_FSMCO + 2, val8);
3717
3718         /* disable HWPDN 0x04[15]= 0*/
3719         val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
3720         val8 &= ~BIT(7);
3721         rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
3722
3723         /* disable WL suspend*/
3724         val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
3725         val8 &= ~(BIT(3) | BIT(4));
3726         rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
3727
3728         /* set, then poll until 0 */
3729         val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
3730         val32 |= APS_FSMCO_MAC_ENABLE;
3731         rtl8xxxu_write32(priv, REG_APS_FSMCO, val32);
3732
3733         for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
3734                 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
3735                 if ((val32 & APS_FSMCO_MAC_ENABLE) == 0) {
3736                         ret = 0;
3737                         break;
3738                 }
3739                 udelay(10);
3740         }
3741
3742         if (!count) {
3743                 ret = -EBUSY;
3744                 goto exit;
3745         }
3746
3747         /* 0x4C[23] = 0x4E[7] = 1, switch DPDT_SEL_P output from WL BB */
3748         /*
3749          * Note: Vendor driver actually clears this bit, despite the
3750          * documentation claims it's being set!
3751          */
3752         val8 = rtl8xxxu_read8(priv, REG_LEDCFG2);
3753         val8 |= LEDCFG2_DPDT_SELECT;
3754         val8 &= ~LEDCFG2_DPDT_SELECT;
3755         rtl8xxxu_write8(priv, REG_LEDCFG2, val8);
3756
3757 exit:
3758         return ret;
3759 }
3760
3761 static int rtl8xxxu_emu_to_disabled(struct rtl8xxxu_priv *priv)
3762 {
3763         u8 val8;
3764
3765         /* 0x0007[7:0] = 0x20 SOP option to disable BG/MB */
3766         rtl8xxxu_write8(priv, REG_APS_FSMCO + 3, 0x20);
3767
3768         /* 0x04[12:11] = 01 enable WL suspend */
3769         val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
3770         val8 &= ~BIT(4);
3771         val8 |= BIT(3);
3772         rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
3773
3774         val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
3775         val8 |= BIT(7);
3776         rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
3777
3778         /* 0x48[16] = 1 to enable GPIO9 as EXT wakeup */
3779         val8 = rtl8xxxu_read8(priv, REG_GPIO_INTM + 2);
3780         val8 |= BIT(0);
3781         rtl8xxxu_write8(priv, REG_GPIO_INTM + 2, val8);
3782
3783         return 0;
3784 }
3785
3786 static int rtl8723au_power_on(struct rtl8xxxu_priv *priv)
3787 {
3788         u8 val8;
3789         u16 val16;
3790         u32 val32;
3791         int ret;
3792
3793         /*
3794          * RSV_CTRL 0x001C[7:0] = 0x00, unlock ISO/CLK/Power control register
3795          */
3796         rtl8xxxu_write8(priv, REG_RSV_CTRL, 0x0);
3797
3798         rtl8xxxu_disabled_to_emu(priv);
3799
3800         ret = rtl8xxxu_emu_to_active(priv);
3801         if (ret)
3802                 goto exit;
3803
3804         /*
3805          * 0x0004[19] = 1, reset 8051
3806          */
3807         val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 2);
3808         val8 |= BIT(3);
3809         rtl8xxxu_write8(priv, REG_APS_FSMCO + 2, val8);
3810
3811         /*
3812          * Enable MAC DMA/WMAC/SCHEDULE/SEC block
3813          * Set CR bit10 to enable 32k calibration.
3814          */
3815         val16 = rtl8xxxu_read16(priv, REG_CR);
3816         val16 |= (CR_HCI_TXDMA_ENABLE | CR_HCI_RXDMA_ENABLE |
3817                   CR_TXDMA_ENABLE | CR_RXDMA_ENABLE |
3818                   CR_PROTOCOL_ENABLE | CR_SCHEDULE_ENABLE |
3819                   CR_MAC_TX_ENABLE | CR_MAC_RX_ENABLE |
3820                   CR_SECURITY_ENABLE | CR_CALTIMER_ENABLE);
3821         rtl8xxxu_write16(priv, REG_CR, val16);
3822
3823         /* For EFuse PG */
3824         val32 = rtl8xxxu_read32(priv, REG_EFUSE_CTRL);
3825         val32 &= ~(BIT(28) | BIT(29) | BIT(30));
3826         val32 |= (0x06 << 28);
3827         rtl8xxxu_write32(priv, REG_EFUSE_CTRL, val32);
3828 exit:
3829         return ret;
3830 }
3831
3832 #ifdef CONFIG_RTL8XXXU_UNTESTED
3833
3834 static int rtl8192cu_power_on(struct rtl8xxxu_priv *priv)
3835 {
3836         u8 val8;
3837         u16 val16;
3838         u32 val32;
3839         int i;
3840
3841         for (i = 100; i; i--) {
3842                 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO);
3843                 if (val8 & APS_FSMCO_PFM_ALDN)
3844                         break;
3845         }
3846
3847         if (!i) {
3848                 pr_info("%s: Poll failed\n", __func__);
3849                 return -ENODEV;
3850         }
3851
3852         /*
3853          * RSV_CTRL 0x001C[7:0] = 0x00, unlock ISO/CLK/Power control register
3854          */
3855         rtl8xxxu_write8(priv, REG_RSV_CTRL, 0x0);
3856         rtl8xxxu_write8(priv, REG_SPS0_CTRL, 0x2b);
3857         udelay(100);
3858
3859         val8 = rtl8xxxu_read8(priv, REG_LDOV12D_CTRL);
3860         if (!(val8 & LDOV12D_ENABLE)) {
3861                 pr_info("%s: Enabling LDOV12D (%02x)\n", __func__, val8);
3862                 val8 |= LDOV12D_ENABLE;
3863                 rtl8xxxu_write8(priv, REG_LDOV12D_CTRL, val8);
3864
3865                 udelay(100);
3866
3867                 val8 = rtl8xxxu_read8(priv, REG_SYS_ISO_CTRL);
3868                 val8 &= ~SYS_ISO_MD2PP;
3869                 rtl8xxxu_write8(priv, REG_SYS_ISO_CTRL, val8);
3870         }
3871
3872         /*
3873          * Auto enable WLAN
3874          */
3875         val16 = rtl8xxxu_read16(priv, REG_APS_FSMCO);
3876         val16 |= APS_FSMCO_MAC_ENABLE;
3877         rtl8xxxu_write16(priv, REG_APS_FSMCO, val16);
3878
3879         for (i = 1000; i; i--) {
3880                 val16 = rtl8xxxu_read16(priv, REG_APS_FSMCO);
3881                 if (!(val16 & APS_FSMCO_MAC_ENABLE))
3882                         break;
3883         }
3884         if (!i) {
3885                 pr_info("%s: FSMCO_MAC_ENABLE poll failed\n", __func__);
3886                 return -EBUSY;
3887         }
3888
3889         /*
3890          * Enable radio, GPIO, LED
3891          */
3892         val16 = APS_FSMCO_HW_SUSPEND | APS_FSMCO_ENABLE_POWERDOWN |
3893                 APS_FSMCO_PFM_ALDN;
3894         rtl8xxxu_write16(priv, REG_APS_FSMCO, val16);
3895
3896         /*
3897          * Release RF digital isolation
3898          */
3899         val16 = rtl8xxxu_read16(priv, REG_SYS_ISO_CTRL);
3900         val16 &= ~SYS_ISO_DIOR;
3901         rtl8xxxu_write16(priv, REG_SYS_ISO_CTRL, val16);
3902
3903         val8 = rtl8xxxu_read8(priv, REG_APSD_CTRL);
3904         val8 &= ~APSD_CTRL_OFF;
3905         rtl8xxxu_write8(priv, REG_APSD_CTRL, val8);
3906         for (i = 200; i; i--) {
3907                 val8 = rtl8xxxu_read8(priv, REG_APSD_CTRL);
3908                 if (!(val8 & APSD_CTRL_OFF_STATUS))
3909                         break;
3910         }
3911
3912         if (!i) {
3913                 pr_info("%s: APSD_CTRL poll failed\n", __func__);
3914                 return -EBUSY;
3915         }
3916
3917         /*
3918          * Enable MAC DMA/WMAC/SCHEDULE/SEC block
3919          */
3920         val16 = rtl8xxxu_read16(priv, REG_CR);
3921         val16 |= CR_HCI_TXDMA_ENABLE | CR_HCI_RXDMA_ENABLE |
3922                 CR_TXDMA_ENABLE | CR_RXDMA_ENABLE | CR_PROTOCOL_ENABLE |
3923                 CR_SCHEDULE_ENABLE | CR_MAC_TX_ENABLE | CR_MAC_RX_ENABLE;
3924         rtl8xxxu_write16(priv, REG_CR, val16);
3925
3926         /*
3927          * Workaround for 8188RU LNA power leakage problem.
3928          */
3929         if (priv->rtlchip == 0x8188c && priv->hi_pa) {
3930                 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XCD_RF_PARM);
3931                 val32 &= ~BIT(1);
3932                 rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_PARM, val32);
3933         }
3934         return 0;
3935 }
3936
3937 #endif
3938
3939 static void rtl8xxxu_power_off(struct rtl8xxxu_priv *priv)
3940 {
3941         u8 val8;
3942         u16 val16;
3943         u32 val32;
3944
3945         /*
3946          * Workaround for 8188RU LNA power leakage problem.
3947          */
3948         if (priv->rtlchip == 0x8188c && priv->hi_pa) {
3949                 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XCD_RF_PARM);
3950                 val32 |= BIT(1);
3951                 rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_PARM, val32);
3952         }
3953
3954         rtl8xxxu_active_to_lps(priv);
3955
3956         /* Turn off RF */
3957         rtl8xxxu_write8(priv, REG_RF_CTRL, 0x00);
3958
3959         /* Reset Firmware if running in RAM */
3960         if (rtl8xxxu_read8(priv, REG_MCU_FW_DL) & MCU_FW_RAM_SEL)
3961                 rtl8xxxu_firmware_self_reset(priv);
3962
3963         /* Reset MCU */
3964         val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
3965         val16 &= ~SYS_FUNC_CPU_ENABLE;
3966         rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);
3967
3968         /* Reset MCU ready status */
3969         rtl8xxxu_write8(priv, REG_MCU_FW_DL, 0x00);
3970
3971         rtl8xxxu_active_to_emu(priv);
3972         rtl8xxxu_emu_to_disabled(priv);
3973
3974         /* Reset MCU IO Wrapper */
3975         val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1);
3976         val8 &= ~BIT(0);
3977         rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8);
3978
3979         val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1);
3980         val8 |= BIT(0);
3981         rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8);
3982
3983         /* RSV_CTRL 0x1C[7:0] = 0x0e  lock ISO/CLK/Power control register */
3984         rtl8xxxu_write8(priv, REG_RSV_CTRL, 0x0e);
3985 }
3986
3987 static void rtl8xxxu_init_bt(struct rtl8xxxu_priv *priv)
3988 {
3989         if (!priv->has_bluetooth)
3990                 return;
3991 }
3992
3993 static int rtl8xxxu_init_device(struct ieee80211_hw *hw)
3994 {
3995         struct rtl8xxxu_priv *priv = hw->priv;
3996         struct device *dev = &priv->udev->dev;
3997         struct rtl8xxxu_rfregval *rftable;
3998         bool macpower;
3999         int ret;
4000         u8 val8;
4001         u16 val16;
4002         u32 val32;
4003
4004         /* Check if MAC is already powered on */
4005         val8 = rtl8xxxu_read8(priv, REG_CR);
4006
4007         /*
4008          * Fix 92DU-VC S3 hang with the reason is that secondary mac is not
4009          * initialized. First MAC returns 0xea, second MAC returns 0x00
4010          */
4011         if (val8 == 0xea)
4012                 macpower = false;
4013         else
4014                 macpower = true;
4015
4016         ret = priv->fops->power_on(priv);
4017         if (ret < 0) {
4018                 dev_warn(dev, "%s: Failed power on\n", __func__);
4019                 goto exit;
4020         }
4021
4022         dev_dbg(dev, "%s: macpower %i\n", __func__, macpower);
4023         if (!macpower) {
4024                 ret = rtl8xxxu_init_llt_table(priv, TX_TOTAL_PAGE_NUM);
4025                 if (ret) {
4026                         dev_warn(dev, "%s: LLT table init failed\n", __func__);
4027                         goto exit;
4028                 }
4029         }
4030
4031         ret = rtl8xxxu_download_firmware(priv);
4032         dev_dbg(dev, "%s: download_fiwmare %i\n", __func__, ret);
4033         if (ret)
4034                 goto exit;
4035         ret = rtl8xxxu_start_firmware(priv);
4036         dev_dbg(dev, "%s: start_fiwmare %i\n", __func__, ret);
4037         if (ret)
4038                 goto exit;
4039
4040         ret = rtl8xxxu_init_mac(priv, rtl8723a_mac_init_table);
4041         dev_dbg(dev, "%s: init_mac %i\n", __func__, ret);
4042         if (ret)
4043                 goto exit;
4044
4045         ret = rtl8xxxu_init_phy_bb(priv);
4046         dev_dbg(dev, "%s: init_phy_bb %i\n", __func__, ret);
4047         if (ret)
4048                 goto exit;
4049
4050         switch(priv->rtlchip) {
4051         case 0x8723a:
4052                 rftable = rtl8723au_radioa_1t_init_table;
4053                 ret = rtl8xxxu_init_phy_rf(priv, rftable, RF_A);
4054                 break;
4055         case 0x8188c:
4056                 if (priv->hi_pa)
4057                         rftable = rtl8188ru_radioa_1t_highpa_table;
4058                 else
4059                         rftable = rtl8192cu_radioa_1t_init_table;
4060                 ret = rtl8xxxu_init_phy_rf(priv, rftable, RF_A);
4061                 break;
4062         case 0x8191c:
4063                 rftable = rtl8192cu_radioa_1t_init_table;
4064                 ret = rtl8xxxu_init_phy_rf(priv, rftable, RF_A);
4065                 break;
4066         case 0x8192c:
4067                 rftable = rtl8192cu_radioa_2t_init_table;
4068                 ret = rtl8xxxu_init_phy_rf(priv, rftable, RF_A);
4069                 if (ret)
4070                         break;
4071                 rftable = rtl8192cu_radiob_2t_init_table;
4072                 ret = rtl8xxxu_init_phy_rf(priv, rftable, RF_B);
4073                 break;
4074         default:
4075                 ret = -EINVAL;
4076         }
4077
4078         if (ret)
4079                 goto exit;
4080
4081         /* Reduce 80M spur */
4082         rtl8xxxu_write32(priv, REG_AFE_XTAL_CTRL, 0x0381808d);
4083         rtl8xxxu_write32(priv, REG_AFE_PLL_CTRL, 0xf0ffff83);
4084         rtl8xxxu_write32(priv, REG_AFE_PLL_CTRL, 0xf0ffff82);
4085         rtl8xxxu_write32(priv, REG_AFE_PLL_CTRL, 0xf0ffff83);
4086
4087         /* RFSW Control - clear bit 14 ?? */
4088         rtl8xxxu_write32(priv, REG_FPGA0_TX_INFO, 0x00000003);
4089         /* 0x07000760 */
4090         val32 = FPGA0_RF_TRSW | FPGA0_RF_TRSWB | FPGA0_RF_ANTSW |
4091                 FPGA0_RF_ANTSWB | FPGA0_RF_PAPE |
4092                 ((FPGA0_RF_ANTSW | FPGA0_RF_ANTSWB | FPGA0_RF_PAPE) <<
4093                  FPGA0_RF_BD_CTRL_SHIFT);
4094         rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_SW_CTRL, val32);
4095         /* 0x860[6:5]= 00 - why? - this sets antenna B */
4096         rtl8xxxu_write32(priv, REG_FPGA0_XA_RF_INT_OE, 0x66F60210);
4097
4098         priv->rf_mode_ag[0] = rtl8xxxu_read_rfreg(priv, RF_A,
4099                                                   RF6052_REG_MODE_AG);
4100
4101         dev_dbg(dev, "%s: macpower %i\n", __func__, macpower);
4102         if (!macpower) {
4103                 if (priv->ep_tx_normal_queue)
4104                         val8 = TX_PAGE_NUM_NORM_PQ;
4105                 else
4106                         val8 = 0;
4107
4108                 rtl8xxxu_write8(priv, REG_RQPN_NPQ, val8);
4109
4110                 val32 = (TX_PAGE_NUM_PUBQ << RQPN_NORM_PQ_SHIFT) | RQPN_LOAD;
4111
4112                 if (priv->ep_tx_high_queue)
4113                         val32 |= (TX_PAGE_NUM_HI_PQ << RQPN_HI_PQ_SHIFT);
4114                 if (priv->ep_tx_low_queue)
4115                         val32 |= (TX_PAGE_NUM_LO_PQ << RQPN_LO_PQ_SHIFT);
4116
4117                 rtl8xxxu_write32(priv, REG_RQPN, val32);
4118
4119                 /*
4120                  * Set TX buffer boundary
4121                  */
4122                 val8 = TX_TOTAL_PAGE_NUM + 1;
4123                 rtl8xxxu_write8(priv, REG_TXPKTBUF_BCNQ_BDNY, val8);
4124                 rtl8xxxu_write8(priv, REG_TXPKTBUF_MGQ_BDNY, val8);
4125                 rtl8xxxu_write8(priv, REG_TXPKTBUF_WMAC_LBK_BF_HD, val8);
4126                 rtl8xxxu_write8(priv, REG_TRXFF_BNDY, val8);
4127                 rtl8xxxu_write8(priv, REG_TDECTRL + 1, val8);
4128         }
4129
4130         ret = rtl8xxxu_init_queue_priority(priv);
4131         dev_dbg(dev, "%s: init_queue_priority %i\n", __func__, ret);
4132         if (ret)
4133                 goto exit;
4134
4135         /*
4136          * Set RX page boundary
4137          */
4138         rtl8xxxu_write16(priv, REG_TRXFF_BNDY + 2, 0x27ff);
4139         /*
4140          * Transfer page size is always 128
4141          */
4142         val8 = (PBP_PAGE_SIZE_128 << PBP_PAGE_SIZE_RX_SHIFT) |
4143                 (PBP_PAGE_SIZE_128 << PBP_PAGE_SIZE_TX_SHIFT);
4144         rtl8xxxu_write8(priv, REG_PBP, val8);
4145
4146         /*
4147          * Unit in 8 bytes, not obvious what it is used for
4148          */
4149         rtl8xxxu_write8(priv, REG_RX_DRVINFO_SZ, 4);
4150
4151         /*
4152          * Enable all interrupts - not obvious USB needs to do this
4153          */
4154         rtl8xxxu_write32(priv, REG_HISR, 0xffffffff);
4155         rtl8xxxu_write32(priv, REG_HIMR, 0xffffffff);
4156
4157         rtl8xxxu_set_mac(priv);
4158         rtl8xxxu_set_linktype(priv, NL80211_IFTYPE_STATION);
4159
4160         /*
4161          * Configure initial WMAC settings
4162          */
4163         val32 = RCR_ACCEPT_PHYS_MATCH | RCR_ACCEPT_MCAST | RCR_ACCEPT_BCAST |
4164                 /* RCR_CHECK_BSSID_MATCH | RCR_CHECK_BSSID_BEACON | */
4165                 RCR_ACCEPT_MGMT_FRAME | RCR_HTC_LOC_CTRL |
4166                 RCR_APPEND_PHYSTAT | RCR_APPEND_ICV | RCR_APPEND_MIC;
4167         rtl8xxxu_write32(priv, REG_RCR, val32);
4168
4169         /*
4170          * Accept all multicast
4171          */
4172         rtl8xxxu_write32(priv, REG_MAR, 0xffffffff);
4173         rtl8xxxu_write32(priv, REG_MAR + 4, 0xffffffff);
4174
4175         /*
4176          * Init adaptive controls
4177          */
4178         val32 = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET);
4179         val32 &= ~RESPONSE_RATE_BITMAP_ALL;
4180         val32 |= RESPONSE_RATE_RRSR_CCK_ONLY_1M;
4181         rtl8xxxu_write32(priv, REG_RESPONSE_RATE_SET, val32);
4182
4183         /* CCK = 0x0a, OFDM = 0x10 */
4184         rtl8xxxu_set_spec_sifs(priv, 0x10, 0x10);
4185         rtl8xxxu_set_retry(priv, 0x30, 0x30);
4186         rtl8xxxu_set_spec_sifs(priv, 0x0a, 0x10);
4187
4188         /*
4189          * Init EDCA
4190          */
4191         rtl8xxxu_write16(priv, REG_MAC_SPEC_SIFS, 0x100a);
4192
4193         /* Set CCK SIFS */
4194         rtl8xxxu_write16(priv, REG_SIFS_CCK, 0x100a);
4195
4196         /* Set OFDM SIFS */
4197         rtl8xxxu_write16(priv, REG_SIFS_OFDM, 0x100a);
4198
4199         /* TXOP */
4200         rtl8xxxu_write32(priv, REG_EDCA_BE_PARAM, 0x005ea42b);
4201         rtl8xxxu_write32(priv, REG_EDCA_BK_PARAM, 0x0000a44f);
4202         rtl8xxxu_write32(priv, REG_EDCA_VI_PARAM, 0x005ea324);
4203         rtl8xxxu_write32(priv, REG_EDCA_VO_PARAM, 0x002fa226);
4204
4205         /* Set data auto rate fallback retry count */
4206         rtl8xxxu_write32(priv, REG_DARFRC, 0x00000000);
4207         rtl8xxxu_write32(priv, REG_DARFRC + 4, 0x10080404);
4208         rtl8xxxu_write32(priv, REG_RARFRC, 0x04030201);
4209         rtl8xxxu_write32(priv, REG_RARFRC + 4, 0x08070605);
4210
4211         val8 = rtl8xxxu_read8(priv, REG_FWHW_TXQ_CTRL);
4212         val8 |= FWHW_TXQ_CTRL_AMPDU_RETRY;
4213         rtl8xxxu_write8(priv, REG_FWHW_TXQ_CTRL, val8);
4214
4215         /*  Set ACK timeout */
4216         rtl8xxxu_write8(priv, REG_ACKTO, 0x40);
4217
4218         /*
4219          * Initialize beacon parameters
4220          */
4221         val16 = BEACON_DISABLE_TSF_UPDATE | (BEACON_DISABLE_TSF_UPDATE << 8);
4222         rtl8xxxu_write16(priv, REG_BEACON_CTRL, val16);
4223         rtl8xxxu_write16(priv, REG_TBTT_PROHIBIT, 0x6404);
4224         rtl8xxxu_write8(priv, REG_DRIVER_EARLY_INT, DRIVER_EARLY_INT_TIME);
4225         rtl8xxxu_write8(priv, REG_BEACON_DMA_TIME, BEACON_DMA_ATIME_INT_TIME);
4226         rtl8xxxu_write16(priv, REG_BEACON_TCFG, 0x660F);
4227
4228         /*
4229          * Enable CCK and OFDM block
4230          */
4231         val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
4232         val32 |= (FPGA_RF_MODE_CCK | FPGA_RF_MODE_OFDM);
4233         rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
4234
4235         /*
4236          * Invalidate all CAM entries - bit 30 is undocumented
4237          */
4238         rtl8xxxu_write32(priv, REG_CAM_CMD, CAM_CMD_POLLING | BIT(30));
4239
4240         /*
4241          * Start out with default power levels for channel 6, 20MHz
4242          */
4243         rtl8723a_set_tx_power(priv, 1, false);
4244
4245         /* Let the 8051 take control of antenna setting */
4246         val8 = rtl8xxxu_read8(priv, REG_LEDCFG2);
4247         val8 |= LEDCFG2_DPDT_SELECT;
4248         rtl8xxxu_write8(priv, REG_LEDCFG2, val8);
4249
4250         rtl8xxxu_write8(priv, REG_HWSEQ_CTRL, 0xff);
4251
4252         /* Disable BAR - not sure if this has any effect on USB */
4253         rtl8xxxu_write32(priv, REG_BAR_MODE_CTRL, 0x0201ffff);
4254
4255         rtl8xxxu_write16(priv, REG_FAST_EDCA_CTRL, 0);
4256
4257         /*
4258          * Not sure if we should get into this at all
4259          */
4260         if (priv->iqk_initialized) {
4261                 rtl8xxxu_restore_regs(priv, rtl8723au_iqk_phy_iq_bb_reg,
4262                                       priv->bb_recovery_backup,
4263                                       RTL8XXXU_BB_REGS);
4264         } else {
4265                 rtl8723a_phy_iq_calibrate(priv);
4266                 priv->iqk_initialized = true;
4267         }
4268
4269         /*
4270          * This should enable thermal meter
4271          */
4272         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_T_METER, 0x60);
4273
4274         rtl8723a_phy_lc_calibrate(priv);
4275
4276         /* fix USB interface interference issue */
4277         rtl8xxxu_write8(priv, 0xfe40, 0xe0);
4278         rtl8xxxu_write8(priv, 0xfe41, 0x8d);
4279         rtl8xxxu_write8(priv, 0xfe42, 0x80);
4280         rtl8xxxu_write32(priv, REG_TXDMA_OFFSET_CHK, 0xfd0320);
4281
4282         /* Solve too many protocol error on USB bus */
4283         /* Can't do this for 8188/8192 UMC A cut parts */
4284         rtl8xxxu_write8(priv, 0xfe40, 0xe6);
4285         rtl8xxxu_write8(priv, 0xfe41, 0x94);
4286         rtl8xxxu_write8(priv, 0xfe42, 0x80);
4287
4288         rtl8xxxu_write8(priv, 0xfe40, 0xe0);
4289         rtl8xxxu_write8(priv, 0xfe41, 0x19);
4290         rtl8xxxu_write8(priv, 0xfe42, 0x80);
4291
4292         rtl8xxxu_write8(priv, 0xfe40, 0xe5);
4293         rtl8xxxu_write8(priv, 0xfe41, 0x91);
4294         rtl8xxxu_write8(priv, 0xfe42, 0x80);
4295
4296         rtl8xxxu_write8(priv, 0xfe40, 0xe2);
4297         rtl8xxxu_write8(priv, 0xfe41, 0x81);
4298         rtl8xxxu_write8(priv, 0xfe42, 0x80);
4299
4300         /* Init BT hw config. */
4301         rtl8xxxu_init_bt(priv);
4302
4303         /*
4304          * Not sure if we really need to save these parameters, but the
4305          * vendor driver does
4306          */
4307         val32 = rtl8xxxu_read32(priv, REG_FPGA0_XA_HSSI_PARM2);
4308         if (val32 & FPGA0_HSSI_PARM2_CCK_HIGH_PWR)
4309                 priv->path_a_hi_power = 1;
4310
4311         val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE);
4312         priv->path_a_rf_paths = val32 & OFDM_RF_PATH_RX_MASK;
4313
4314         val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_AGC_CORE1);
4315         priv->path_a_ig_value = val32 & OFDM0_X_AGC_CORE1_IGI_MASK;
4316
4317         /* Set NAV_UPPER to 30000us */
4318         val8 = ((30000 + NAV_UPPER_UNIT - 1) / NAV_UPPER_UNIT);
4319         rtl8xxxu_write8(priv, REG_NAV_UPPER, val8);
4320
4321         /*
4322          * 2011/03/09 MH debug only, UMC-B cut pass 2500 S5 test,
4323          * but we need to fin root cause.
4324          */
4325         val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
4326         if ((val32 & 0xff000000) != 0x83000000) {
4327                 val32 |= FPGA_RF_MODE_CCK;
4328                 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
4329         }
4330
4331         val32 = rtl8xxxu_read32(priv, REG_FWHW_TXQ_CTRL);
4332         val32 |= FWHW_TXQ_CTRL_XMIT_MGMT_ACK;
4333         /* ack for xmit mgmt frames. */
4334         rtl8xxxu_write32(priv, REG_FWHW_TXQ_CTRL, val32);
4335
4336 exit:
4337         return ret;
4338 }
4339
4340 static void rtl8xxxu_disable_device(struct ieee80211_hw *hw)
4341 {
4342         struct rtl8xxxu_priv *priv = hw->priv;
4343
4344         rtl8xxxu_power_off(priv);
4345 }
4346
4347 static void rtl8xxxu_cam_write(struct rtl8xxxu_priv *priv,
4348                                struct ieee80211_key_conf *key, const u8 *mac)
4349 {
4350         u32 cmd, val32, addr, ctrl;
4351         int j, i, tmp_debug;
4352
4353         tmp_debug = rtl8xxxu_debug;
4354         if (rtl8xxxu_debug & RTL8XXXU_DEBUG_KEY)
4355                 rtl8xxxu_debug |= RTL8XXXU_DEBUG_REG_WRITE;
4356
4357         /*
4358          * This is a bit of a hack - the lower bits of the cipher
4359          * suite selector happens to match the cipher index in the CAM
4360          */
4361         addr = key->keyidx << CAM_CMD_KEY_SHIFT;
4362         ctrl = (key->cipher & 0x0f) << 2 | key->keyidx | CAM_WRITE_VALID;
4363
4364         for (j = 5; j >= 0; j--) {
4365                 switch (j) {
4366                 case 0:
4367                         val32 = ctrl | (mac[0] << 16) | (mac[1] << 24);
4368                         break;
4369                 case 1:
4370                         val32 = mac[2] | (mac[3] << 8) |
4371                                 (mac[4] << 16) | (mac[5] << 24);
4372                         break;
4373                 default:
4374                         i = (j - 2) << 2;
4375                         val32 = key->key[i] | (key->key[i + 1] << 8) |
4376                                 key->key[i + 2] << 16 | key->key[i + 3] << 24;
4377                         break;
4378                 }
4379
4380                 rtl8xxxu_write32(priv, REG_CAM_WRITE, val32);
4381                 cmd = CAM_CMD_POLLING | CAM_CMD_WRITE | (addr + j);
4382                 rtl8xxxu_write32(priv, REG_CAM_CMD, cmd);
4383                 udelay(100);
4384         }
4385
4386         rtl8xxxu_debug = tmp_debug;
4387 }
4388
4389 static void rtl8xxxu_sw_scan_start(struct ieee80211_hw *hw,
4390                                    struct ieee80211_vif *vif, const u8* mac)
4391 {
4392         struct rtl8xxxu_priv *priv = hw->priv;
4393         u8 val8;
4394
4395         val8 = rtl8xxxu_read8(priv, REG_BEACON_CTRL);
4396         val8 |= BEACON_DISABLE_TSF_UPDATE;
4397         rtl8xxxu_write8(priv, REG_BEACON_CTRL, val8);
4398 }
4399
4400 static void rtl8xxxu_sw_scan_complete(struct ieee80211_hw *hw,
4401                                       struct ieee80211_vif *vif)
4402 {
4403         struct rtl8xxxu_priv *priv = hw->priv;
4404         u8 val8;
4405
4406         val8 = rtl8xxxu_read8(priv, REG_BEACON_CTRL);
4407         val8 &= ~BEACON_DISABLE_TSF_UPDATE;
4408         rtl8xxxu_write8(priv, REG_BEACON_CTRL, val8);
4409 }
4410
4411 static void rtl8xxxu_update_rate_mask(struct rtl8xxxu_priv *priv,
4412                                       u32 ramask, int sgi)
4413 {
4414         struct h2c_cmd h2c;
4415
4416         h2c.ramask.cmd = H2C_SET_RATE_MASK;
4417         h2c.ramask.mask_lo = cpu_to_le16(ramask & 0xffff);
4418         h2c.ramask.mask_hi = cpu_to_le16(ramask >> 16);
4419
4420         h2c.ramask.arg = 0x80;
4421         if (sgi)
4422                 h2c.ramask.arg |= 0x20;
4423
4424         dev_dbg(&priv->udev->dev, "%s: rate mask %08x, arg %02x\n", __func__,
4425                 ramask, h2c.ramask.arg);
4426         rtl8723a_h2c_cmd(priv, &h2c);
4427 }
4428
4429 static void rtl8xxxu_set_basic_rates(struct rtl8xxxu_priv *priv, u32 rate_cfg)
4430 {
4431         u32 val32;
4432         u8 rate_idx = 0;
4433
4434         rate_cfg &= RESPONSE_RATE_BITMAP_ALL;
4435
4436         val32 = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET);
4437         val32 &= ~RESPONSE_RATE_BITMAP_ALL;
4438         val32 |= rate_cfg;
4439         rtl8xxxu_write32(priv, REG_RESPONSE_RATE_SET, val32);
4440
4441         dev_dbg(&priv->udev->dev, "%s: rates %08x\n", __func__, rate_cfg);
4442
4443         while (rate_cfg) {
4444                 rate_cfg = (rate_cfg >> 1);
4445                 rate_idx++;
4446         }
4447         rtl8xxxu_write8(priv, REG_INIRTS_RATE_SEL, rate_idx);
4448 }
4449
4450 static void
4451 rtl8xxxu_bss_info_changed(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
4452                           struct ieee80211_bss_conf *bss_conf, u32 changed)
4453 {
4454         struct rtl8xxxu_priv *priv = hw->priv;
4455         struct device *dev = &priv->udev->dev;
4456         struct ieee80211_sta *sta;
4457         u32 val32;
4458         u8 val8;
4459
4460         if (changed & BSS_CHANGED_ASSOC) {
4461                 struct h2c_cmd h2c;
4462
4463                 dev_dbg(dev, "Changed ASSOC: %i!\n", bss_conf->assoc);
4464
4465                 memset(&h2c, 0, sizeof(struct h2c_cmd));
4466                 rtl8xxxu_set_linktype(priv, vif->type);
4467
4468                 if (bss_conf->assoc) {
4469                         u32 ramask;
4470                         int sgi = 0;
4471
4472                         rcu_read_lock();
4473                         sta = ieee80211_find_sta(vif, bss_conf->bssid);
4474                         if (!sta) {
4475                                 dev_info(dev, "%s: ASSOC no sta found\n",
4476                                          __func__);
4477                                 rcu_read_unlock();
4478                                 goto error;
4479                         }
4480
4481                         if (sta->ht_cap.ht_supported)
4482                                 dev_info(dev, "%s: HT supported\n", __func__);
4483                         if (sta->vht_cap.vht_supported)
4484                                 dev_info(dev, "%s: VHT supported\n", __func__);
4485
4486                         /* TODO: Set bits 28-31 for rate adaptive id */
4487                         ramask = (sta->supp_rates[0] & 0xfff) |
4488                                 sta->ht_cap.mcs.rx_mask[0] << 12 |
4489                                 sta->ht_cap.mcs.rx_mask[1] << 20;
4490                         if (sta->ht_cap.cap &
4491                             (IEEE80211_HT_CAP_SGI_40 | IEEE80211_HT_CAP_SGI_20))
4492                                 sgi = 1;
4493                         rcu_read_unlock();
4494
4495                         rtl8xxxu_update_rate_mask(priv, ramask, sgi);
4496
4497                         val32 = rtl8xxxu_read32(priv, REG_RCR);
4498                         val32 |= RCR_CHECK_BSSID_MATCH | RCR_CHECK_BSSID_BEACON;
4499                         rtl8xxxu_write32(priv, REG_RCR, val32);
4500
4501                         /* Enable RX of data frames */
4502                         rtl8xxxu_write16(priv, REG_RXFLTMAP2, 0xffff);
4503
4504                         rtl8xxxu_write8(priv, REG_BCN_MAX_ERR, 0xff);
4505
4506                         rtl8723a_stop_tx_beacon(priv);
4507
4508                         /* joinbss sequence */
4509                         rtl8xxxu_write16(priv, REG_BCN_PSR_RPT,
4510                                          0xc000 | bss_conf->aid);
4511
4512                         h2c.joinbss.data = H2C_JOIN_BSS_CONNECT;
4513                 } else {
4514                         val32 = rtl8xxxu_read32(priv, REG_RCR);
4515                         val32 &= ~(RCR_CHECK_BSSID_MATCH |
4516                                    RCR_CHECK_BSSID_BEACON);
4517                         rtl8xxxu_write32(priv, REG_RCR, val32);
4518
4519                         val8 = rtl8xxxu_read8(priv, REG_BEACON_CTRL);
4520                         val8 |= BEACON_DISABLE_TSF_UPDATE;
4521                         rtl8xxxu_write8(priv, REG_BEACON_CTRL, val8);
4522
4523                         /* Disable RX of data frames */
4524                         rtl8xxxu_write16(priv, REG_RXFLTMAP2, 0x0000);
4525                         h2c.joinbss.data = H2C_JOIN_BSS_DISCONNECT;
4526                 }
4527                 h2c.joinbss.cmd = H2C_JOIN_BSS_REPORT;
4528                 rtl8723a_h2c_cmd(priv, &h2c);
4529         }
4530
4531         if (changed & BSS_CHANGED_ERP_PREAMBLE) {
4532                 dev_dbg(dev, "Changed ERP_PREAMBLE: Use short preamble %i\n",
4533                         bss_conf->use_short_preamble);
4534                 val32 = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET);
4535                 if (bss_conf->use_short_preamble)
4536                         val32 |= RSR_ACK_SHORT_PREAMBLE;
4537                 else
4538                         val32 &= ~RSR_ACK_SHORT_PREAMBLE;
4539                 rtl8xxxu_write32(priv, REG_RESPONSE_RATE_SET, val32);
4540         }
4541
4542         if (changed & BSS_CHANGED_ERP_SLOT) {
4543                 dev_dbg(dev, "Changed ERP_SLOT: short_slot_time %i\n",
4544                         bss_conf->use_short_slot);
4545
4546                 if (bss_conf->use_short_slot)
4547                         val8 = 9;
4548                 else
4549                         val8 = 20;
4550                 rtl8xxxu_write8(priv, REG_SLOT, val8);
4551         }
4552
4553         if (changed & BSS_CHANGED_BSSID) {
4554                 dev_dbg(dev, "Changed BSSID!\n");
4555                 rtl8xxxu_set_bssid(priv, bss_conf->bssid);
4556         }
4557
4558         if (changed & BSS_CHANGED_BASIC_RATES) {
4559                 dev_dbg(dev, "Changed BASIC_RATES!\n");
4560                 rtl8xxxu_set_basic_rates(priv, bss_conf->basic_rates);
4561         }
4562 error:
4563         return;
4564 }
4565
4566 static u32 rtl8xxxu_80211_to_rtl_queue(u32 queue)
4567 {
4568         u32 rtlqueue;
4569
4570         switch (queue) {
4571         case IEEE80211_AC_VO:
4572                 rtlqueue = TXDESC_QUEUE_VO;
4573                 break;
4574         case IEEE80211_AC_VI:
4575                 rtlqueue = TXDESC_QUEUE_VI;
4576                 break;
4577         case IEEE80211_AC_BE:
4578                 rtlqueue = TXDESC_QUEUE_BE;
4579                 break;
4580         case IEEE80211_AC_BK:
4581                 rtlqueue = TXDESC_QUEUE_BK;
4582                 break;
4583         default:
4584                 rtlqueue = TXDESC_QUEUE_BE;
4585         }
4586
4587         return rtlqueue;
4588 }
4589
4590 static u32 rtl8xxxu_queue_select(struct ieee80211_hw *hw, struct sk_buff *skb)
4591 {
4592         struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
4593         u32 queue;
4594
4595         if (ieee80211_is_mgmt(hdr->frame_control))
4596                 queue = TXDESC_QUEUE_MGNT;
4597         else
4598                 queue = rtl8xxxu_80211_to_rtl_queue(skb_get_queue_mapping(skb));
4599
4600         return queue;
4601 }
4602
4603 static void rtl8xxxu_calc_tx_desc_csum(struct rtl8xxxu_tx_desc *tx_desc)
4604 {
4605         __le16 *ptr = (__le16 *)tx_desc;
4606         u16 csum = 0;
4607         int i;
4608
4609         /*
4610          * Clear csum field before calculation, as the csum field is
4611          * in the middle of the struct.
4612          */
4613         tx_desc->csum = cpu_to_le16(0);
4614
4615         for (i = 0; i < (sizeof(struct rtl8xxxu_tx_desc) / sizeof(u16)); i++)
4616                 csum = csum ^ le16_to_cpu(ptr[i]);
4617
4618         tx_desc->csum |= cpu_to_le16(csum);
4619 }
4620
4621 static void rtl8xxxu_free_tx_resources(struct rtl8xxxu_priv *priv)
4622 {
4623         struct rtl8xxxu_tx_urb *tx_urb, *tmp;
4624         unsigned long flags;
4625
4626         spin_lock_irqsave(&priv->tx_urb_lock, flags);
4627         list_for_each_entry_safe(tx_urb, tmp, &priv->tx_urb_free_list, list) {
4628                 list_del(&tx_urb->list);
4629                 priv->tx_urb_free_count--;
4630                 usb_free_urb(&tx_urb->urb);
4631         }
4632         spin_unlock_irqrestore(&priv->tx_urb_lock, flags);
4633 }
4634
4635 static struct rtl8xxxu_tx_urb *
4636 rtl8xxxu_alloc_tx_urb(struct rtl8xxxu_priv *priv)
4637 {
4638         struct rtl8xxxu_tx_urb *tx_urb;
4639         unsigned long flags;
4640
4641         spin_lock_irqsave(&priv->tx_urb_lock, flags);
4642         tx_urb = list_first_entry_or_null(&priv->tx_urb_free_list,
4643                                           struct rtl8xxxu_tx_urb, list);
4644         if (tx_urb) {
4645                 list_del(&tx_urb->list);
4646                 priv->tx_urb_free_count--;
4647                 if (priv->tx_urb_free_count < RTL8XXXU_TX_URB_LOW_WATER &&
4648                     !priv->tx_stopped) {
4649                         priv->tx_stopped = true;
4650                         ieee80211_stop_queues(priv->hw);
4651                 }
4652         }
4653
4654         spin_unlock_irqrestore(&priv->tx_urb_lock, flags);
4655
4656         return tx_urb;
4657 }
4658
4659 static void rtl8xxxu_free_tx_urb(struct rtl8xxxu_priv *priv,
4660                                  struct rtl8xxxu_tx_urb *tx_urb)
4661 {
4662         unsigned long flags;
4663
4664         INIT_LIST_HEAD(&tx_urb->list);
4665
4666         spin_lock_irqsave(&priv->tx_urb_lock, flags);
4667
4668         list_add(&tx_urb->list, &priv->tx_urb_free_list);
4669         priv->tx_urb_free_count++;
4670         if (priv->tx_urb_free_count > RTL8XXXU_TX_URB_HIGH_WATER &&
4671             priv->tx_stopped) {
4672                 priv->tx_stopped = false;
4673                 ieee80211_wake_queues(priv->hw);
4674         }
4675
4676         spin_unlock_irqrestore(&priv->tx_urb_lock, flags);
4677 }
4678
4679 static void rtl8xxxu_tx_complete(struct urb *urb)
4680 {
4681         struct sk_buff *skb = (struct sk_buff *)urb->context;
4682         struct ieee80211_tx_info *tx_info;
4683         struct ieee80211_hw *hw;
4684         struct rtl8xxxu_tx_urb *tx_urb =
4685                 container_of(urb, struct rtl8xxxu_tx_urb, urb);
4686
4687         tx_info = IEEE80211_SKB_CB(skb);
4688         hw = tx_info->rate_driver_data[0];
4689
4690         skb_pull(skb, sizeof(struct rtl8xxxu_tx_desc));
4691
4692         ieee80211_tx_info_clear_status(tx_info);
4693         tx_info->status.rates[0].idx = -1;
4694         tx_info->status.rates[0].count = 0;
4695
4696         if (!urb->status)
4697                 tx_info->flags |= IEEE80211_TX_STAT_ACK;
4698
4699         ieee80211_tx_status_irqsafe(hw, skb);
4700
4701         rtl8xxxu_free_tx_urb(hw->priv, tx_urb);
4702 }
4703
4704 static void rtl8xxxu_dump_action(struct device *dev,
4705                                  struct ieee80211_hdr *hdr)
4706 {
4707         struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)hdr;
4708         u16 cap, timeout;
4709
4710         if (!(rtl8xxxu_debug & RTL8XXXU_DEBUG_ACTION))
4711                 return;
4712
4713         switch (mgmt->u.action.u.addba_resp.action_code) {
4714         case WLAN_ACTION_ADDBA_RESP:
4715                 cap = le16_to_cpu(mgmt->u.action.u.addba_resp.capab);
4716                 timeout = le16_to_cpu(mgmt->u.action.u.addba_resp.timeout);
4717                 dev_info(dev, "WLAN_ACTION_ADDBA_RESP: "
4718                          "timeout %i, tid %02x, buf_size %02x, policy %02x, "
4719                          "status %02x\n",
4720                          timeout,
4721                          (cap & IEEE80211_ADDBA_PARAM_TID_MASK) >> 2,
4722                          (cap & IEEE80211_ADDBA_PARAM_BUF_SIZE_MASK) >> 6,
4723                          (cap >> 1) & 0x1,
4724                          le16_to_cpu(mgmt->u.action.u.addba_resp.status));
4725                 break;
4726         case WLAN_ACTION_ADDBA_REQ:
4727                 cap = le16_to_cpu(mgmt->u.action.u.addba_req.capab);
4728                 timeout = le16_to_cpu(mgmt->u.action.u.addba_req.timeout);
4729                 dev_info(dev, "WLAN_ACTION_ADDBA_REQ: "
4730                          "timeout %i, tid %02x, buf_size %02x, policy %02x\n",
4731                          timeout,
4732                          (cap & IEEE80211_ADDBA_PARAM_TID_MASK) >> 2,
4733                          (cap & IEEE80211_ADDBA_PARAM_BUF_SIZE_MASK) >> 6,
4734                          (cap >> 1) & 0x1);
4735                 break;
4736         default:
4737                 dev_info(dev, "action frame %02x\n",
4738                          mgmt->u.action.u.addba_resp.action_code);
4739                 break;
4740         }
4741 }
4742
4743 static void rtl8xxxu_tx(struct ieee80211_hw *hw,
4744                         struct ieee80211_tx_control *control,
4745                         struct sk_buff *skb)
4746 {
4747         struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
4748         struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
4749         struct ieee80211_rate *tx_rate = ieee80211_get_tx_rate(hw, tx_info);
4750         struct rtl8xxxu_priv *priv = hw->priv;
4751         struct rtl8xxxu_tx_desc *tx_desc;
4752         struct rtl8xxxu_tx_urb *tx_urb;
4753         struct ieee80211_sta *sta = NULL;
4754         struct ieee80211_vif *vif = tx_info->control.vif;
4755         struct device *dev = &priv->udev->dev;
4756         u32 queue, rate;
4757         u16 pktlen = skb->len;
4758         u16 seq_number;
4759         u16 rate_flag = tx_info->control.rates[0].flags;
4760         int ret;
4761
4762         if (skb_headroom(skb) < sizeof(struct rtl8xxxu_tx_desc)) {
4763                 dev_warn(dev,
4764                          "%s: Not enough headroom (%i) for tx descriptor\n",
4765                          __func__, skb_headroom(skb));
4766                 goto error;
4767         }
4768
4769         if (unlikely(skb->len > (65535 - sizeof(struct rtl8xxxu_tx_desc)))) {
4770                 dev_warn(dev, "%s: Trying to send over-sized skb (%i)\n",
4771                          __func__, skb->len);
4772                 goto error;
4773         }
4774
4775         tx_urb = rtl8xxxu_alloc_tx_urb(priv);
4776         if (!tx_urb) {
4777                 dev_warn(dev, "%s: Unable to allocate tx urb\n", __func__);
4778                 goto error;
4779         }
4780
4781         if (rtl8xxxu_debug & RTL8XXXU_DEBUG_TX)
4782                 dev_info(dev, "%s: TX rate: %d (%d), pkt size %d\n",
4783                          __func__, tx_rate->bitrate, tx_rate->hw_value, pktlen);
4784
4785         if (ieee80211_is_action(hdr->frame_control))
4786                 rtl8xxxu_dump_action(dev, hdr);
4787
4788         tx_info->rate_driver_data[0] = hw;
4789
4790         if (control && control->sta)
4791                 sta = control->sta;
4792
4793         tx_desc = (struct rtl8xxxu_tx_desc *)
4794                 skb_push(skb, sizeof(struct rtl8xxxu_tx_desc));
4795
4796         memset(tx_desc, 0, sizeof(struct rtl8xxxu_tx_desc));
4797         tx_desc->pkt_size = cpu_to_le16(pktlen);
4798         tx_desc->pkt_offset = sizeof(struct rtl8xxxu_tx_desc);
4799
4800         tx_desc->txdw0 =
4801                 TXDESC_OWN | TXDESC_FIRST_SEGMENT | TXDESC_LAST_SEGMENT;
4802         if (is_multicast_ether_addr(ieee80211_get_DA(hdr)) ||
4803             is_broadcast_ether_addr(ieee80211_get_DA(hdr)))
4804                 tx_desc->txdw0 |= TXDESC_BROADMULTICAST;
4805
4806         queue = rtl8xxxu_queue_select(hw, skb);
4807         tx_desc->txdw1 = cpu_to_le32(queue << TXDESC_QUEUE_SHIFT);
4808
4809         if (tx_info->control.hw_key) {
4810                 switch (tx_info->control.hw_key->cipher) {
4811                 case WLAN_CIPHER_SUITE_WEP40:
4812                 case WLAN_CIPHER_SUITE_WEP104:
4813                 case WLAN_CIPHER_SUITE_TKIP:
4814                         tx_desc->txdw1 |= cpu_to_le32(TXDESC_SEC_RC4);
4815                         break;
4816                 case WLAN_CIPHER_SUITE_CCMP:
4817                         tx_desc->txdw1 |= cpu_to_le32(TXDESC_SEC_AES);
4818                         break;
4819                 default:
4820                         break;
4821                 }
4822         }
4823
4824         seq_number = IEEE80211_SEQ_TO_SN(le16_to_cpu(hdr->seq_ctrl));
4825         tx_desc->txdw3 = cpu_to_le32((u32)seq_number << TXDESC_SEQ_SHIFT);
4826
4827         if (rate_flag & IEEE80211_TX_RC_MCS)
4828                 rate = tx_info->control.rates[0].idx + DESC_RATE_MCS0;
4829         else
4830                 rate = tx_rate->hw_value;
4831         tx_desc->txdw5 = cpu_to_le32(rate);
4832
4833         if (ieee80211_is_data(hdr->frame_control))
4834                 tx_desc->txdw5 |= cpu_to_le32(0x0001ff00);
4835
4836         /* (tx_info->flags & IEEE80211_TX_CTL_AMPDU) && */
4837         if (ieee80211_is_data_qos(hdr->frame_control) && sta) {
4838                 if (sta->ht_cap.ht_supported) {
4839                         u32 ampdu, val32;
4840
4841                         ampdu = (u32)sta->ht_cap.ampdu_density;
4842                         val32 = ampdu << TXDESC_AMPDU_DENSITY_SHIFT;
4843                         tx_desc->txdw2 |= cpu_to_le32(val32);
4844                         tx_desc->txdw1 |= cpu_to_le32(TXDESC_AGG_ENABLE);
4845                 } else
4846                         tx_desc->txdw1 |= cpu_to_le32(TXDESC_BK);
4847         } else
4848                 tx_desc->txdw1 |= cpu_to_le32(TXDESC_BK);
4849
4850         if (ieee80211_is_data_qos(hdr->frame_control))
4851                 tx_desc->txdw4 |= cpu_to_le32(TXDESC_QOS);
4852         if (rate_flag & IEEE80211_TX_RC_USE_SHORT_PREAMBLE ||
4853             (sta && vif && vif->bss_conf.use_short_preamble))
4854                 tx_desc->txdw4 |= cpu_to_le32(TXDESC_SHORT_PREAMBLE);
4855         if (rate_flag & IEEE80211_TX_RC_SHORT_GI ||
4856             (ieee80211_is_data_qos(hdr->frame_control) &&
4857              sta && sta->ht_cap.cap &
4858              (IEEE80211_HT_CAP_SGI_40 | IEEE80211_HT_CAP_SGI_20))) {
4859                 tx_desc->txdw5 |= cpu_to_le32(TXDESC_SHORT_GI);
4860         }
4861         if (ieee80211_is_mgmt(hdr->frame_control)) {
4862                 tx_desc->txdw5 = cpu_to_le32(tx_rate->hw_value);
4863                 tx_desc->txdw4 |= cpu_to_le32(TXDESC_USE_DRIVER_RATE);
4864                 tx_desc->txdw5 |= cpu_to_le32(6 << TXDESC_RETRY_LIMIT_SHIFT);
4865                 tx_desc->txdw5 |= cpu_to_le32(TXDESC_RETRY_LIMIT_ENABLE);
4866         }
4867
4868         if (rate_flag & IEEE80211_TX_RC_USE_RTS_CTS) {
4869                 /* Use RTS rate 24M - does the mac80211 tell us which to use? */
4870                 tx_desc->txdw4 |= cpu_to_le32(DESC_RATE_24M);
4871                 tx_desc->txdw4 |= cpu_to_le32(TXDESC_RTS_CTS_ENABLE);
4872                 tx_desc->txdw4 |= cpu_to_le32(TXDESC_HW_RTS_ENABLE);
4873         }
4874
4875         rtl8xxxu_calc_tx_desc_csum(tx_desc);
4876
4877         usb_fill_bulk_urb(&tx_urb->urb, priv->udev, priv->pipe_out[queue],
4878                           skb->data, skb->len, rtl8xxxu_tx_complete, skb);
4879
4880         usb_anchor_urb(&tx_urb->urb, &priv->tx_anchor);
4881         ret = usb_submit_urb(&tx_urb->urb, GFP_ATOMIC);
4882         if (ret) {
4883                 usb_unanchor_urb(&tx_urb->urb);
4884                 rtl8xxxu_free_tx_urb(priv, tx_urb);
4885                 goto error;
4886         }
4887         return;
4888 error:
4889         dev_kfree_skb(skb);
4890 }
4891
4892 static void rtl8xxxu_rx_parse_phystats(struct rtl8xxxu_priv *priv,
4893                                        struct ieee80211_rx_status *rx_status,
4894                                        struct rtl8xxxu_rx_desc *rx_desc,
4895                                        struct rtl8723au_phy_stats *phy_stats)
4896 {
4897         if (phy_stats->sgi_en)
4898                 rx_status->flag |= RX_FLAG_SHORT_GI;
4899
4900         if (rx_desc->rxmcs < DESC_RATE_6M) {
4901                 /*
4902                  * Handle PHY stats for CCK rates
4903                  */
4904                 u8 cck_agc_rpt = phy_stats->cck_agc_rpt_ofdm_cfosho_a;
4905
4906                 switch (cck_agc_rpt & 0xc0) {
4907                 case 0xc0:
4908                         rx_status->signal = -46 - (cck_agc_rpt & 0x3e);
4909                         break;
4910                 case 0x80:
4911                         rx_status->signal = -26 - (cck_agc_rpt & 0x3e);
4912                         break;
4913                 case 0x40:
4914                         rx_status->signal = -12 - (cck_agc_rpt & 0x3e);
4915                         break;
4916                 case 0x00:
4917                         rx_status->signal = 16 - (cck_agc_rpt & 0x3e);
4918                         break;
4919                 }
4920         } else {
4921                 rx_status->signal =
4922                         (phy_stats->cck_sig_qual_ofdm_pwdb_all >> 1) - 110;
4923         }
4924 }
4925
4926 static void rtl8xxxu_free_rx_resources(struct rtl8xxxu_priv *priv)
4927 {
4928         struct rtl8xxxu_rx_urb *rx_urb, *tmp;
4929         unsigned long flags;
4930
4931         spin_lock_irqsave(&priv->rx_urb_lock, flags);
4932
4933         list_for_each_entry_safe(rx_urb, tmp,
4934                                  &priv->rx_urb_pending_list, list) {
4935                 list_del(&rx_urb->list);
4936                 priv->rx_urb_pending_count--;
4937                 usb_free_urb(&rx_urb->urb);
4938         }
4939
4940         spin_unlock_irqrestore(&priv->rx_urb_lock, flags);
4941 }
4942
4943 static void rtl8xxxu_queue_rx_urb(struct rtl8xxxu_priv *priv,
4944                                   struct rtl8xxxu_rx_urb *rx_urb)
4945 {
4946         struct sk_buff *skb;
4947         unsigned long flags;
4948         int pending = 0;
4949
4950         spin_lock_irqsave(&priv->rx_urb_lock, flags);
4951
4952         if (!priv->shutdown) {
4953                 list_add_tail(&rx_urb->list, &priv->rx_urb_pending_list);
4954                 priv->rx_urb_pending_count++;
4955                 pending = priv->rx_urb_pending_count;
4956         } else {
4957                 skb = (struct sk_buff *)rx_urb->urb.context;
4958                 dev_kfree_skb(skb);
4959                 usb_free_urb(&rx_urb->urb);
4960         }
4961
4962         spin_unlock_irqrestore(&priv->rx_urb_lock, flags);
4963
4964         if (pending > RTL8XXXU_RX_URB_PENDING_WATER)
4965                 schedule_work(&priv->rx_urb_wq);
4966 }
4967
4968 static void rtl8xxxu_rx_urb_work(struct work_struct *work)
4969 {
4970         struct rtl8xxxu_priv *priv;
4971         struct rtl8xxxu_rx_urb *rx_urb, *tmp;
4972         struct list_head local;
4973         struct sk_buff *skb;
4974         unsigned long flags;
4975         int ret;
4976
4977         priv = container_of(work, struct rtl8xxxu_priv, rx_urb_wq);
4978         INIT_LIST_HEAD(&local);
4979
4980         spin_lock_irqsave(&priv->rx_urb_lock, flags);
4981
4982         list_splice_init(&priv->rx_urb_pending_list, &local);
4983         priv->rx_urb_pending_count = 0;
4984
4985         spin_unlock_irqrestore(&priv->rx_urb_lock, flags);
4986
4987         list_for_each_entry_safe(rx_urb, tmp, &local, list) {
4988                 list_del_init(&rx_urb->list);
4989                 ret = rtl8xxxu_submit_rx_urb(priv, rx_urb);
4990                 /*
4991                  * If out of memory or temporary error, put it back on the
4992                  * queue and try again. Otherwise the device is dead/gone
4993                  * and we should drop it.
4994                  */
4995                 switch (ret) {
4996                 case 0:
4997                         break;
4998                 case -ENOMEM:
4999                 case -EAGAIN:
5000                         rtl8xxxu_queue_rx_urb(priv, rx_urb);
5001                         break;
5002                 default:
5003                         pr_info("failed to requeue urb %i\n", ret);
5004                         skb = (struct sk_buff *)rx_urb->urb.context;
5005                         dev_kfree_skb(skb);
5006                         usb_free_urb(&rx_urb->urb);
5007                 }
5008         }
5009 }
5010
5011 static void rtl8xxxu_rx_complete(struct urb *urb)
5012 {
5013         struct rtl8xxxu_rx_urb *rx_urb =
5014                 container_of(urb, struct rtl8xxxu_rx_urb, urb);
5015         struct ieee80211_hw *hw = rx_urb->hw;
5016         struct rtl8xxxu_priv *priv = hw->priv;
5017         struct sk_buff *skb = (struct sk_buff *)urb->context;
5018         struct rtl8xxxu_rx_desc *rx_desc = (struct rtl8xxxu_rx_desc *)skb->data;
5019         struct rtl8723au_phy_stats *phy_stats;
5020         struct ieee80211_rx_status *rx_status = IEEE80211_SKB_RXCB(skb);
5021         struct ieee80211_mgmt *mgmt;
5022         struct device *dev = &priv->udev->dev;
5023         __le32 *_rx_desc_le = (__le32 *)skb->data;
5024         u32 *_rx_desc = (u32 *)skb->data;
5025         int cnt, len, drvinfo_sz, desc_shift, i;
5026
5027         for (i = 0; i < (sizeof(struct rtl8xxxu_rx_desc) / sizeof(u32)); i++)
5028                 _rx_desc[i] = le32_to_cpu(_rx_desc_le[i]);
5029
5030         cnt = rx_desc->frag;
5031         len = rx_desc->pktlen;
5032         drvinfo_sz = rx_desc->drvinfo_sz * 8;
5033         desc_shift = rx_desc->shift;
5034         skb_put(skb, urb->actual_length);
5035
5036         if (urb->status == 0) {
5037                 skb_pull(skb, sizeof(struct rtl8xxxu_rx_desc));
5038                 phy_stats = (struct rtl8723au_phy_stats *)skb->data;
5039
5040                 skb_pull(skb, drvinfo_sz + desc_shift);
5041
5042                 mgmt = (struct ieee80211_mgmt *)skb->data;
5043
5044                 memset(rx_status, 0, sizeof(struct ieee80211_rx_status));
5045
5046                 if (rx_desc->phy_stats)
5047                         rtl8xxxu_rx_parse_phystats(priv, rx_status,
5048                                                    rx_desc, phy_stats);
5049
5050                 rx_status->freq = hw->conf.chandef.chan->center_freq;
5051                 rx_status->band = hw->conf.chandef.chan->band;
5052
5053                 rx_status->mactime = le32_to_cpu(rx_desc->tsfl);
5054                 rx_status->flag |= RX_FLAG_MACTIME_START;
5055
5056                 if (!rx_desc->swdec)
5057                         rx_status->flag |= RX_FLAG_DECRYPTED;
5058                 if (rx_desc->crc32)
5059                         rx_status->flag |= RX_FLAG_FAILED_FCS_CRC;
5060                 if (rx_desc->bw)
5061                         rx_status->flag |= RX_FLAG_40MHZ;
5062
5063                 if (rx_desc->rxht) {
5064                         rx_status->flag |= RX_FLAG_HT;
5065                         rx_status->rate_idx = rx_desc->rxmcs - DESC_RATE_MCS0;
5066                 } else {
5067                         rx_status->rate_idx = rx_desc->rxmcs;
5068                 }
5069
5070                 ieee80211_rx_irqsafe(hw, skb);
5071                 skb = NULL;
5072                 rx_urb->urb.context = NULL;
5073                 rtl8xxxu_queue_rx_urb(priv, rx_urb);
5074         } else {
5075                 dev_dbg(dev, "%s: status %i\n", __func__, urb->status);
5076                 goto cleanup;
5077         }
5078         return;
5079
5080 cleanup:
5081         usb_free_urb(urb);
5082         dev_kfree_skb(skb);
5083         return;
5084 }
5085
5086 static int rtl8xxxu_submit_rx_urb(struct rtl8xxxu_priv *priv,
5087                                   struct rtl8xxxu_rx_urb *rx_urb)
5088 {
5089         struct sk_buff *skb;
5090         int skb_size;
5091         int ret;
5092
5093         skb_size = sizeof(struct rtl8xxxu_rx_desc) + RTL_RX_BUFFER_SIZE;
5094         skb = __netdev_alloc_skb(NULL, skb_size, GFP_KERNEL);
5095         if (!skb)
5096                 return -ENOMEM;
5097
5098         memset(skb->data, 0, sizeof(struct rtl8xxxu_rx_desc));
5099         usb_fill_bulk_urb(&rx_urb->urb, priv->udev, priv->pipe_in, skb->data,
5100                           skb_size, rtl8xxxu_rx_complete, skb);
5101         usb_anchor_urb(&rx_urb->urb, &priv->rx_anchor);
5102         ret = usb_submit_urb(&rx_urb->urb, GFP_ATOMIC);
5103         if (ret)
5104                 usb_unanchor_urb(&rx_urb->urb);
5105         return ret;
5106 }
5107
5108 static void rtl8xxxu_int_complete(struct urb *urb)
5109 {
5110         struct rtl8xxxu_priv *priv = (struct rtl8xxxu_priv *)urb->context;
5111         struct device *dev = &priv->udev->dev;
5112         int ret;
5113
5114         dev_dbg(dev, "%s: status %i\n", __func__, urb->status);
5115         if (urb->status == 0) {
5116                 usb_anchor_urb(urb, &priv->int_anchor);
5117                 ret = usb_submit_urb(urb, GFP_ATOMIC);
5118                 if (ret)
5119                         usb_unanchor_urb(urb);
5120         } else {
5121                 dev_info(dev, "%s: Error %i\n", __func__, urb->status);
5122         }
5123 }
5124
5125
5126 static int rtl8xxxu_submit_int_urb(struct ieee80211_hw *hw)
5127 {
5128         struct rtl8xxxu_priv *priv = hw->priv;
5129         struct urb *urb;
5130         u32 val32;
5131         int ret;
5132
5133         urb = usb_alloc_urb(0, GFP_KERNEL);
5134         if (!urb)
5135                 return -ENOMEM;
5136
5137         usb_fill_int_urb(urb, priv->udev, priv->pipe_interrupt,
5138                          priv->int_buf, USB_INTR_CONTENT_LENGTH,
5139                          rtl8xxxu_int_complete, priv, 1);
5140         usb_anchor_urb(urb, &priv->int_anchor);
5141         ret = usb_submit_urb(urb, GFP_KERNEL);
5142         if (ret) {
5143                 usb_unanchor_urb(urb);
5144                 goto error;
5145         }
5146
5147         val32 = rtl8xxxu_read32(priv, REG_USB_HIMR);
5148         val32 |= USB_HIMR_CPWM;
5149         rtl8xxxu_write32(priv, REG_USB_HIMR, val32);
5150
5151 error:
5152         return ret;
5153 }
5154
5155 static int rtl8xxxu_add_interface(struct ieee80211_hw *hw,
5156                                   struct ieee80211_vif *vif)
5157 {
5158         struct rtl8xxxu_priv *priv = hw->priv;
5159         int ret;
5160         u8 val8;
5161
5162         switch (vif->type) {
5163         case NL80211_IFTYPE_STATION:
5164                 rtl8723a_stop_tx_beacon(priv);
5165
5166                 val8 = rtl8xxxu_read8(priv, REG_BEACON_CTRL);
5167                 val8 |= BEACON_ATIM | BEACON_FUNCTION_ENABLE |
5168                         BEACON_DISABLE_TSF_UPDATE;
5169                 rtl8xxxu_write8(priv, REG_BEACON_CTRL, val8);
5170                 ret = 0;
5171                 break;
5172         default:
5173                 ret = -EOPNOTSUPP;
5174         }
5175
5176         rtl8xxxu_set_linktype(priv, vif->type);
5177
5178         return ret;
5179 }
5180
5181 static void rtl8xxxu_remove_interface(struct ieee80211_hw *hw,
5182                                       struct ieee80211_vif *vif)
5183 {
5184         struct rtl8xxxu_priv *priv = hw->priv;
5185
5186         dev_dbg(&priv->udev->dev, "%s\n", __func__);
5187 }
5188
5189 static int rtl8xxxu_config(struct ieee80211_hw *hw, u32 changed)
5190 {
5191         struct rtl8xxxu_priv *priv = hw->priv;
5192         struct device *dev = &priv->udev->dev;
5193         u16 val16;
5194         int ret = 0, channel;
5195         bool ht40;
5196
5197         if (rtl8xxxu_debug & RTL8XXXU_DEBUG_CHANNEL)
5198                 dev_info(dev,
5199                          "%s: channel: %i (changed %08x chandef.width %02x)\n",
5200                          __func__, hw->conf.chandef.chan->hw_value,
5201                          changed, hw->conf.chandef.width);
5202
5203         if (changed & IEEE80211_CONF_CHANGE_RETRY_LIMITS) {
5204                 val16 = ((hw->conf.long_frame_max_tx_count <<
5205                           RETRY_LIMIT_LONG_SHIFT) & RETRY_LIMIT_LONG_MASK) |
5206                         ((hw->conf.short_frame_max_tx_count <<
5207                           RETRY_LIMIT_SHORT_SHIFT) & RETRY_LIMIT_SHORT_MASK);
5208                 rtl8xxxu_write16(priv, REG_RETRY_LIMIT, val16);
5209         }
5210
5211         if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
5212                 switch (hw->conf.chandef.width) {
5213                 case NL80211_CHAN_WIDTH_20_NOHT:
5214                 case NL80211_CHAN_WIDTH_20:
5215                         ht40 = false;
5216                         break;
5217                 case NL80211_CHAN_WIDTH_40:
5218                         ht40 = true;
5219                         break;
5220                 default:
5221                         ret = -ENOTSUPP;
5222                         goto exit;
5223                 }
5224
5225                 channel = hw->conf.chandef.chan->hw_value;
5226
5227                 rtl8723a_set_tx_power(priv, channel, ht40);
5228
5229                 rtl8723au_config_channel(hw);
5230         }
5231
5232 exit:
5233         return ret;
5234 }
5235
5236 static int rtl8xxxu_conf_tx(struct ieee80211_hw *hw,
5237                             struct ieee80211_vif *vif, u16 queue,
5238                             const struct ieee80211_tx_queue_params *param)
5239 {
5240         struct rtl8xxxu_priv *priv = hw->priv;
5241         struct device *dev = &priv->udev->dev;
5242         u32 val32;
5243         u8 aifs, acm_ctrl, acm_bit;
5244
5245         aifs = param->aifs;
5246
5247         val32 = aifs |
5248                 fls(param->cw_min) << EDCA_PARAM_ECW_MIN_SHIFT |
5249                 fls(param->cw_max) << EDCA_PARAM_ECW_MAX_SHIFT |
5250                 (u32)param->txop << EDCA_PARAM_TXOP_SHIFT;
5251
5252         acm_ctrl = rtl8xxxu_read8(priv, REG_ACM_HW_CTRL);
5253         dev_dbg(dev,
5254                 "%s: IEEE80211 queue %02x val %08x, acm %i, acm_ctrl %02x\n",
5255                 __func__, queue, val32, param->acm, acm_ctrl);
5256
5257         switch (queue) {
5258         case IEEE80211_AC_VO:
5259                 acm_bit = ACM_HW_CTRL_VO;
5260                 rtl8xxxu_write32(priv, REG_EDCA_VO_PARAM, val32);
5261                 break;
5262         case IEEE80211_AC_VI:
5263                 acm_bit = ACM_HW_CTRL_VI;
5264                 rtl8xxxu_write32(priv, REG_EDCA_VI_PARAM, val32);
5265                 break;
5266         case IEEE80211_AC_BE:
5267                 acm_bit = ACM_HW_CTRL_BE;
5268                 rtl8xxxu_write32(priv, REG_EDCA_BE_PARAM, val32);
5269                 break;
5270         case IEEE80211_AC_BK:
5271                 acm_bit = ACM_HW_CTRL_BK;
5272                 rtl8xxxu_write32(priv, REG_EDCA_BK_PARAM, val32);
5273                 break;
5274         default:
5275                 acm_bit = 0;
5276                 break;
5277         }
5278
5279         if (param->acm)
5280                 acm_ctrl |= acm_bit;
5281         else
5282                 acm_ctrl &= ~acm_bit;
5283         rtl8xxxu_write8(priv, REG_ACM_HW_CTRL, acm_ctrl);
5284
5285         return 0;
5286 }
5287
5288 static void rtl8xxxu_configure_filter(struct ieee80211_hw *hw,
5289                                       unsigned int changed_flags,
5290                                       unsigned int *total_flags, u64 multicast)
5291 {
5292         struct rtl8xxxu_priv *priv = hw->priv;
5293
5294         dev_dbg(&priv->udev->dev, "%s: changed_flags %08x, total_flags %08x\n",
5295                 __func__, changed_flags, *total_flags);
5296
5297         *total_flags &= (FIF_ALLMULTI | FIF_CONTROL | FIF_BCN_PRBRESP_PROMISC);
5298 }
5299
5300 static int rtl8xxxu_set_rts_threshold(struct ieee80211_hw *hw, u32 rts)
5301 {
5302         if (rts > 2347)
5303                 return -EINVAL;
5304
5305         return 0;
5306 }
5307
5308 static int rtl8xxxu_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
5309                             struct ieee80211_vif *vif,
5310                             struct ieee80211_sta *sta,
5311                             struct ieee80211_key_conf *key)
5312 {
5313         struct rtl8xxxu_priv *priv = hw->priv;
5314         struct device *dev = &priv->udev->dev;
5315         u8 mac_addr[ETH_ALEN];
5316         u8 val8;
5317         u16 val16;
5318         u32 val32;
5319         int retval = -EOPNOTSUPP;
5320
5321         dev_dbg(dev, "%s: cmd %02x, cipher %08x, index %i\n",
5322                 __func__, cmd, key->cipher, key->keyidx);
5323
5324         if (vif->type != NL80211_IFTYPE_STATION)
5325                 return -EOPNOTSUPP;
5326
5327         if (key->keyidx > 3)
5328                 return -EOPNOTSUPP;
5329
5330         switch (key->cipher) {
5331         case WLAN_CIPHER_SUITE_WEP40:
5332         case WLAN_CIPHER_SUITE_WEP104:
5333
5334                 break;
5335         case WLAN_CIPHER_SUITE_CCMP:
5336                 key->flags |= IEEE80211_KEY_FLAG_SW_MGMT_TX;
5337                 break;
5338         case WLAN_CIPHER_SUITE_TKIP:
5339                 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
5340         default:
5341                 return -EOPNOTSUPP;
5342         }
5343
5344         if (key->flags & IEEE80211_KEY_FLAG_PAIRWISE) {
5345                 dev_dbg(dev, "%s: pairwise key\n", __func__);
5346                 ether_addr_copy(mac_addr, sta->addr);
5347         } else {
5348                 dev_dbg(dev, "%s: group key\n", __func__);
5349                 eth_broadcast_addr(mac_addr);
5350         }
5351
5352         val16 = rtl8xxxu_read16(priv, REG_CR);
5353         val16 |= CR_SECURITY_ENABLE;
5354         rtl8xxxu_write16(priv, REG_CR, val16);
5355
5356         val8 = SEC_CFG_TX_SEC_ENABLE | SEC_CFG_TXBC_USE_DEFKEY |
5357                 SEC_CFG_RX_SEC_ENABLE | SEC_CFG_RXBC_USE_DEFKEY;
5358         val8 |= SEC_CFG_TX_USE_DEFKEY | SEC_CFG_RX_USE_DEFKEY;
5359         rtl8xxxu_write8(priv, REG_SECURITY_CFG, val8);
5360
5361         switch (cmd) {
5362         case SET_KEY:
5363                 key->hw_key_idx = key->keyidx;
5364                 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
5365                 rtl8xxxu_cam_write(priv, key, mac_addr);
5366                 retval = 0;
5367                 break;
5368         case DISABLE_KEY:
5369                 rtl8xxxu_write32(priv, REG_CAM_WRITE, 0x00000000);
5370                 val32 = CAM_CMD_POLLING | CAM_CMD_WRITE |
5371                         key->keyidx << CAM_CMD_KEY_SHIFT;
5372                 rtl8xxxu_write32(priv, REG_CAM_CMD, val32);
5373                 retval = 0;
5374                 break;
5375         default:
5376                 dev_warn(dev, "%s: Unsupported command %02x\n", __func__, cmd);
5377         }
5378
5379         return retval;
5380 }
5381
5382 static int
5383 rtl8xxxu_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
5384                       enum ieee80211_ampdu_mlme_action action,
5385                       struct ieee80211_sta *sta, u16 tid, u16 *ssn, u8 buf_size,
5386                       bool amsdu)
5387 {
5388         struct rtl8xxxu_priv *priv = hw->priv;
5389         struct device *dev = &priv->udev->dev;
5390         u8 ampdu_factor, ampdu_density;
5391
5392         switch (action) {
5393         case IEEE80211_AMPDU_TX_START:
5394                 dev_info(dev, "%s: IEEE80211_AMPDU_TX_START\n", __func__);
5395                 ampdu_factor = sta->ht_cap.ampdu_factor;
5396                 ampdu_density = sta->ht_cap.ampdu_density;
5397                 rtl8xxxu_set_ampdu_factor(priv, ampdu_factor);
5398                 rtl8xxxu_set_ampdu_min_space(priv, ampdu_density);
5399                 dev_dbg(dev,
5400                         "Changed HT: ampdu_factor %02x, ampdu_density %02x\n",
5401                         ampdu_factor, ampdu_density);
5402                 break;
5403         case IEEE80211_AMPDU_TX_STOP_FLUSH:
5404                 dev_info(dev, "%s: IEEE80211_AMPDU_TX_STOP_FLUSH\n", __func__);
5405                 rtl8xxxu_set_ampdu_factor(priv, 0);
5406                 rtl8xxxu_set_ampdu_min_space(priv, 0);
5407                 break;
5408         case IEEE80211_AMPDU_TX_STOP_FLUSH_CONT:
5409                 dev_info(dev, "%s: IEEE80211_AMPDU_TX_STOP_FLUSH_CONT\n",
5410                          __func__);
5411                 rtl8xxxu_set_ampdu_factor(priv, 0);
5412                 rtl8xxxu_set_ampdu_min_space(priv, 0);
5413                 break;
5414         case IEEE80211_AMPDU_RX_START:
5415                 dev_info(dev, "%s: IEEE80211_AMPDU_RX_START\n", __func__);
5416                 break;
5417         case IEEE80211_AMPDU_RX_STOP:
5418                 dev_info(dev, "%s: IEEE80211_AMPDU_RX_STOP\n", __func__);
5419                 break;
5420         default:
5421                 break;
5422         }
5423         return 0;
5424 }
5425
5426 static int rtl8xxxu_start(struct ieee80211_hw *hw)
5427 {
5428         struct rtl8xxxu_priv *priv = hw->priv;
5429         struct rtl8xxxu_rx_urb *rx_urb;
5430         struct rtl8xxxu_tx_urb *tx_urb;
5431         unsigned long flags;
5432         int ret, i;
5433
5434         ret = 0;
5435
5436         init_usb_anchor(&priv->rx_anchor);
5437         init_usb_anchor(&priv->tx_anchor);
5438         init_usb_anchor(&priv->int_anchor);
5439
5440         rtl8723a_enable_rf(priv);
5441         ret = rtl8xxxu_submit_int_urb(hw);
5442         if (ret)
5443                 goto exit;
5444
5445         for (i = 0; i < RTL8XXXU_TX_URBS; i++) {
5446                 tx_urb = kmalloc(sizeof(struct rtl8xxxu_tx_urb), GFP_KERNEL);
5447                 if (!tx_urb) {
5448                         if (!i)
5449                                 ret = -ENOMEM;
5450
5451                         goto error_out;
5452                 }
5453                 usb_init_urb(&tx_urb->urb);
5454                 INIT_LIST_HEAD(&tx_urb->list);
5455                 tx_urb->hw = hw;
5456                 list_add(&tx_urb->list, &priv->tx_urb_free_list);
5457                 priv->tx_urb_free_count++;
5458         }
5459
5460         priv->tx_stopped = false;
5461
5462         spin_lock_irqsave(&priv->rx_urb_lock, flags);
5463         priv->shutdown = false;
5464         spin_unlock_irqrestore(&priv->rx_urb_lock, flags);
5465
5466         for (i = 0; i < RTL8XXXU_RX_URBS; i++) {
5467                 rx_urb = kmalloc(sizeof(struct rtl8xxxu_rx_urb), GFP_KERNEL);
5468                 if (!rx_urb) {
5469                         if (!i)
5470                                 ret = -ENOMEM;
5471
5472                         goto error_out;
5473                 }
5474                 usb_init_urb(&rx_urb->urb);
5475                 INIT_LIST_HEAD(&rx_urb->list);
5476                 rx_urb->hw = hw;
5477
5478                 ret = rtl8xxxu_submit_rx_urb(priv, rx_urb);
5479         }
5480 exit:
5481         /*
5482          * Disable all data frames
5483          */
5484         rtl8xxxu_write16(priv, REG_RXFLTMAP2, 0x0000);
5485         /*
5486          * Accept all mgmt frames
5487          */
5488         rtl8xxxu_write16(priv, REG_RXFLTMAP0, 0xffff);
5489
5490         rtl8xxxu_write32(priv, REG_OFDM0_XA_AGC_CORE1, 0x6954341e);
5491
5492         return ret;
5493
5494 error_out:
5495         rtl8xxxu_free_tx_resources(priv);
5496         /*
5497          * Disable all data and mgmt frames
5498          */
5499         rtl8xxxu_write16(priv, REG_RXFLTMAP2, 0x0000);
5500         rtl8xxxu_write16(priv, REG_RXFLTMAP0, 0x0000);
5501
5502         return ret;
5503 }
5504
5505 static void rtl8xxxu_stop(struct ieee80211_hw *hw)
5506 {
5507         struct rtl8xxxu_priv *priv = hw->priv;
5508         unsigned long flags;
5509
5510         rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff);
5511
5512         rtl8xxxu_write16(priv, REG_RXFLTMAP0, 0x0000);
5513         rtl8xxxu_write16(priv, REG_RXFLTMAP2, 0x0000);
5514
5515         spin_lock_irqsave(&priv->rx_urb_lock, flags);
5516         priv->shutdown = true;
5517         spin_unlock_irqrestore(&priv->rx_urb_lock, flags);
5518
5519         usb_kill_anchored_urbs(&priv->rx_anchor);
5520         usb_kill_anchored_urbs(&priv->tx_anchor);
5521         usb_kill_anchored_urbs(&priv->int_anchor);
5522
5523         rtl8723a_disable_rf(priv);
5524
5525         /*
5526          * Disable interrupts
5527          */
5528         rtl8xxxu_write32(priv, REG_USB_HIMR, 0);
5529
5530         rtl8xxxu_free_rx_resources(priv);
5531         rtl8xxxu_free_tx_resources(priv);
5532 }
5533
5534 static const struct ieee80211_ops rtl8xxxu_ops = {
5535         .tx = rtl8xxxu_tx,
5536         .add_interface = rtl8xxxu_add_interface,
5537         .remove_interface = rtl8xxxu_remove_interface,
5538         .config = rtl8xxxu_config,
5539         .conf_tx = rtl8xxxu_conf_tx,
5540         .bss_info_changed = rtl8xxxu_bss_info_changed,
5541         .configure_filter = rtl8xxxu_configure_filter,
5542         .set_rts_threshold = rtl8xxxu_set_rts_threshold,
5543         .start = rtl8xxxu_start,
5544         .stop = rtl8xxxu_stop,
5545         .sw_scan_start = rtl8xxxu_sw_scan_start,
5546         .sw_scan_complete = rtl8xxxu_sw_scan_complete,
5547         .set_key = rtl8xxxu_set_key,
5548         .ampdu_action = rtl8xxxu_ampdu_action,
5549 };
5550
5551 static int rtl8xxxu_parse_usb(struct rtl8xxxu_priv *priv,
5552                               struct usb_interface *interface)
5553 {
5554         struct usb_interface_descriptor *interface_desc;
5555         struct usb_host_interface *host_interface;
5556         struct usb_endpoint_descriptor *endpoint;
5557         struct device *dev = &priv->udev->dev;
5558         int i, j = 0, endpoints;
5559         u8 dir, xtype, num;
5560         int ret = 0;
5561
5562         host_interface = &interface->altsetting[0];
5563         interface_desc = &host_interface->desc;
5564         endpoints = interface_desc->bNumEndpoints;
5565
5566         for (i = 0; i < endpoints; i++) {
5567                 endpoint = &host_interface->endpoint[i].desc;
5568
5569                 dir = endpoint->bEndpointAddress & USB_ENDPOINT_DIR_MASK;
5570                 num = usb_endpoint_num(endpoint);
5571                 xtype = usb_endpoint_type(endpoint);
5572                 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_USB)
5573                         dev_dbg(dev,
5574                                 "%s: endpoint: dir %02x, # %02x, type %02x\n",
5575                                 __func__, dir, num, xtype);
5576                 if (usb_endpoint_dir_in(endpoint) &&
5577                     usb_endpoint_xfer_bulk(endpoint)) {
5578                         if (rtl8xxxu_debug & RTL8XXXU_DEBUG_USB)
5579                                 dev_dbg(dev, "%s: in endpoint num %i\n",
5580                                         __func__, num);
5581
5582                         if (priv->pipe_in) {
5583                                 dev_warn(dev,
5584                                          "%s: Too many IN pipes\n", __func__);
5585                                 ret = -EINVAL;
5586                                 goto exit;
5587                         }
5588
5589                         priv->pipe_in = usb_rcvbulkpipe(priv->udev, num);
5590                 }
5591
5592                 if (usb_endpoint_dir_in(endpoint) &&
5593                     usb_endpoint_xfer_int(endpoint)) {
5594                         if (rtl8xxxu_debug & RTL8XXXU_DEBUG_USB)
5595                                 dev_dbg(dev, "%s: interrupt endpoint num %i\n",
5596                                         __func__, num);
5597
5598                         if (priv->pipe_interrupt) {
5599                                 dev_warn(dev, "%s: Too many INTERRUPT pipes\n",
5600                                          __func__);
5601                                 ret = -EINVAL;
5602                                 goto exit;
5603                         }
5604
5605                         priv->pipe_interrupt = usb_rcvintpipe(priv->udev, num);
5606                 }
5607
5608                 if (usb_endpoint_dir_out(endpoint) &&
5609                     usb_endpoint_xfer_bulk(endpoint)) {
5610                         if (rtl8xxxu_debug & RTL8XXXU_DEBUG_USB)
5611                                 dev_dbg(dev, "%s: out endpoint num %i\n",
5612                                         __func__, num);
5613                         if (j >= RTL8XXXU_OUT_ENDPOINTS) {
5614                                 dev_warn(dev,
5615                                          "%s: Too many OUT pipes\n", __func__);
5616                                 ret = -EINVAL;
5617                                 goto exit;
5618                         }
5619                         priv->out_ep[j++] = num;
5620                 }
5621         }
5622 exit:
5623         priv->nr_out_eps = j;
5624         return ret;
5625 }
5626
5627 static int rtl8xxxu_probe(struct usb_interface *interface,
5628                           const struct usb_device_id *id)
5629 {
5630         struct rtl8xxxu_priv *priv;
5631         struct ieee80211_hw *hw;
5632         struct usb_device *udev;
5633         struct ieee80211_supported_band *sband;
5634         int ret = 0;
5635         int untested = 1;
5636
5637         udev = usb_get_dev(interface_to_usbdev(interface));
5638
5639         switch (id->idVendor) {
5640         case USB_VENDOR_ID_REALTEK:
5641                 switch(id->idProduct) {
5642                 case 0x1724:
5643                 case 0x8176:
5644                 case 0x8178:
5645                 case 0x817f:
5646                         untested = 0;
5647                         break;
5648                 }
5649                 break;
5650         case 0x7392:
5651                 if (id->idProduct == 0x7811)
5652                         untested = 0;
5653                 break;
5654         default:
5655                 break;
5656         }
5657
5658         if (untested) {
5659                 rtl8xxxu_debug = RTL8XXXU_DEBUG_EFUSE;
5660                 dev_info(&udev->dev,
5661                          "This Realtek USB WiFi dongle (0x%04x:0x%04x) is untested!\n",
5662                          id->idVendor, id->idProduct);
5663                 dev_info(&udev->dev,
5664                          "Please report results to Jes.Sorensen@gmail.com\n");
5665         }
5666
5667         hw = ieee80211_alloc_hw(sizeof(struct rtl8xxxu_priv), &rtl8xxxu_ops);
5668         if (!hw) {
5669                 ret = -ENOMEM;
5670                 goto exit;
5671         }
5672
5673         priv = hw->priv;
5674         priv->hw = hw;
5675         priv->udev = udev;
5676         priv->fops = (struct rtl8xxxu_fileops *)id->driver_info;
5677         mutex_init(&priv->usb_buf_mutex);
5678         mutex_init(&priv->h2c_mutex);
5679         INIT_LIST_HEAD(&priv->tx_urb_free_list);
5680         spin_lock_init(&priv->tx_urb_lock);
5681         INIT_LIST_HEAD(&priv->rx_urb_pending_list);
5682         spin_lock_init(&priv->rx_urb_lock);
5683         INIT_WORK(&priv->rx_urb_wq, rtl8xxxu_rx_urb_work);
5684
5685         usb_set_intfdata(interface, hw);
5686
5687         ret = rtl8xxxu_parse_usb(priv, interface);
5688         if (ret)
5689                 goto exit;
5690
5691         ret = rtl8xxxu_identify_chip(priv);
5692         if (ret) {
5693                 dev_err(&udev->dev, "Fatal - failed to identify chip\n");
5694                 goto exit;
5695         }
5696
5697         ret = rtl8xxxu_read_efuse(priv);
5698         if (ret) {
5699                 dev_err(&udev->dev, "Fatal - failed to read EFuse\n");
5700                 goto exit;
5701         }
5702
5703         ret = priv->fops->parse_efuse(priv);
5704         if (ret) {
5705                 dev_err(&udev->dev, "Fatal - failed to parse EFuse\n");
5706                 goto exit;
5707         }
5708
5709         rtl8xxxu_print_chipinfo(priv);
5710
5711         ret = priv->fops->load_firmware(priv);
5712         if (ret) {
5713                 dev_err(&udev->dev, "Fatal - failed to load firmware\n");
5714                 goto exit;
5715         }
5716
5717         ret = rtl8xxxu_init_device(hw);
5718
5719         hw->wiphy->max_scan_ssids = 1;
5720         hw->wiphy->max_scan_ie_len = IEEE80211_MAX_DATA_LEN;
5721         hw->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION);
5722         hw->queues = 4;
5723
5724         sband = &rtl8xxxu_supported_band;
5725         sband->ht_cap.ht_supported = true;
5726         sband->ht_cap.ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K;
5727         sband->ht_cap.ampdu_density = IEEE80211_HT_MPDU_DENSITY_16;
5728         sband->ht_cap.cap = IEEE80211_HT_CAP_SGI_20 | IEEE80211_HT_CAP_SGI_40;
5729         memset(&sband->ht_cap.mcs, 0, sizeof(sband->ht_cap.mcs));
5730         sband->ht_cap.mcs.rx_mask[0] = 0xff;
5731         sband->ht_cap.mcs.rx_mask[4] = 0x01;
5732         if (priv->rf_paths > 1) {
5733                 sband->ht_cap.mcs.rx_mask[1] = 0xff;
5734                 sband->ht_cap.cap |= IEEE80211_HT_CAP_SGI_40;
5735         }
5736         sband->ht_cap.mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
5737         /*
5738          * Some APs will negotiate HT20_40 in a noisy environment leading
5739          * to miserable performance. Rather than defaulting to this, only
5740          * enable it if explicitly requested at module load time.
5741          */
5742         if (rtl8xxxu_ht40_2g) {
5743                 dev_info(&udev->dev, "Enabling HT_20_40 on the 2.4GHz band\n");
5744                 sband->ht_cap.cap |= IEEE80211_HT_CAP_SUP_WIDTH_20_40;
5745         }
5746         hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
5747
5748         hw->wiphy->rts_threshold = 2347;
5749
5750         SET_IEEE80211_DEV(priv->hw, &interface->dev);
5751         SET_IEEE80211_PERM_ADDR(hw, priv->mac_addr);
5752
5753         hw->extra_tx_headroom = sizeof(struct rtl8xxxu_tx_desc);
5754         ieee80211_hw_set(hw, SIGNAL_DBM);
5755         /*
5756          * The firmware handles rate control
5757          */
5758         ieee80211_hw_set(hw, HAS_RATE_CONTROL);
5759         ieee80211_hw_set(hw, AMPDU_AGGREGATION);
5760
5761         ret = ieee80211_register_hw(priv->hw);
5762         if (ret) {
5763                 dev_err(&udev->dev, "%s: Failed to register: %i\n",
5764                         __func__, ret);
5765                 goto exit;
5766         }
5767
5768 exit:
5769         if (ret < 0)
5770                 usb_put_dev(udev);
5771         return ret;
5772 }
5773
5774 static void rtl8xxxu_disconnect(struct usb_interface *interface)
5775 {
5776         struct rtl8xxxu_priv *priv;
5777         struct ieee80211_hw *hw;
5778
5779         hw = usb_get_intfdata(interface);
5780         priv = hw->priv;
5781
5782         rtl8xxxu_disable_device(hw);
5783         usb_set_intfdata(interface, NULL);
5784
5785         dev_info(&priv->udev->dev, "disconnecting\n");
5786
5787         ieee80211_unregister_hw(hw);
5788
5789         kfree(priv->fw_data);
5790         mutex_destroy(&priv->usb_buf_mutex);
5791         mutex_destroy(&priv->h2c_mutex);
5792
5793         usb_put_dev(priv->udev);
5794         ieee80211_free_hw(hw);
5795 }
5796
5797 static struct rtl8xxxu_fileops rtl8723au_fops = {
5798         .parse_efuse = rtl8723au_parse_efuse,
5799         .load_firmware = rtl8723au_load_firmware,
5800         .power_on = rtl8723au_power_on,
5801         .writeN_block_size = 1024,
5802 };
5803
5804 #ifdef CONFIG_RTL8XXXU_UNTESTED
5805
5806 static struct rtl8xxxu_fileops rtl8192cu_fops = {
5807         .parse_efuse = rtl8192cu_parse_efuse,
5808         .load_firmware = rtl8192cu_load_firmware,
5809         .power_on = rtl8192cu_power_on,
5810         .writeN_block_size = 128,
5811 };
5812
5813 #endif
5814
5815 static struct usb_device_id dev_table[] = {
5816 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8724, 0xff, 0xff, 0xff),
5817         .driver_info = (unsigned long)&rtl8723au_fops},
5818 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x1724, 0xff, 0xff, 0xff),
5819         .driver_info = (unsigned long)&rtl8723au_fops},
5820 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x0724, 0xff, 0xff, 0xff),
5821         .driver_info = (unsigned long)&rtl8723au_fops},
5822 #ifdef CONFIG_RTL8XXXU_UNTESTED
5823 /* Still supported by rtlwifi */
5824 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8176, 0xff, 0xff, 0xff),
5825         .driver_info = (unsigned long)&rtl8192cu_fops},
5826 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8178, 0xff, 0xff, 0xff),
5827         .driver_info = (unsigned long)&rtl8192cu_fops},
5828 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817f, 0xff, 0xff, 0xff),
5829         .driver_info = (unsigned long)&rtl8192cu_fops},
5830 /* Tested by Larry Finger */
5831 {USB_DEVICE_AND_INTERFACE_INFO(0x7392, 0x7811, 0xff, 0xff, 0xff),
5832         .driver_info = (unsigned long)&rtl8192cu_fops},
5833 /* Currently untested 8188 series devices */
5834 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8191, 0xff, 0xff, 0xff),
5835         .driver_info = (unsigned long)&rtl8192cu_fops},
5836 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8170, 0xff, 0xff, 0xff),
5837         .driver_info = (unsigned long)&rtl8192cu_fops},
5838 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8177, 0xff, 0xff, 0xff),
5839         .driver_info = (unsigned long)&rtl8192cu_fops},
5840 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817a, 0xff, 0xff, 0xff),
5841         .driver_info = (unsigned long)&rtl8192cu_fops},
5842 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817b, 0xff, 0xff, 0xff),
5843         .driver_info = (unsigned long)&rtl8192cu_fops},
5844 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817d, 0xff, 0xff, 0xff),
5845         .driver_info = (unsigned long)&rtl8192cu_fops},
5846 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817e, 0xff, 0xff, 0xff),
5847         .driver_info = (unsigned long)&rtl8192cu_fops},
5848 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x818a, 0xff, 0xff, 0xff),
5849         .driver_info = (unsigned long)&rtl8192cu_fops},
5850 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x317f, 0xff, 0xff, 0xff),
5851         .driver_info = (unsigned long)&rtl8192cu_fops},
5852 {USB_DEVICE_AND_INTERFACE_INFO(0x1058, 0x0631, 0xff, 0xff, 0xff),
5853         .driver_info = (unsigned long)&rtl8192cu_fops},
5854 {USB_DEVICE_AND_INTERFACE_INFO(0x04bb, 0x094c, 0xff, 0xff, 0xff),
5855         .driver_info = (unsigned long)&rtl8192cu_fops},
5856 {USB_DEVICE_AND_INTERFACE_INFO(0x050d, 0x1102, 0xff, 0xff, 0xff),
5857         .driver_info = (unsigned long)&rtl8192cu_fops},
5858 {USB_DEVICE_AND_INTERFACE_INFO(0x06f8, 0xe033, 0xff, 0xff, 0xff),
5859         .driver_info = (unsigned long)&rtl8192cu_fops},
5860 {USB_DEVICE_AND_INTERFACE_INFO(0x07b8, 0x8189, 0xff, 0xff, 0xff),
5861         .driver_info = (unsigned long)&rtl8192cu_fops},
5862 {USB_DEVICE_AND_INTERFACE_INFO(0x0846, 0x9041, 0xff, 0xff, 0xff),
5863         .driver_info = (unsigned long)&rtl8192cu_fops},
5864 {USB_DEVICE_AND_INTERFACE_INFO(0x0b05, 0x17ba, 0xff, 0xff, 0xff),
5865         .driver_info = (unsigned long)&rtl8192cu_fops},
5866 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x1e1e, 0xff, 0xff, 0xff),
5867         .driver_info = (unsigned long)&rtl8192cu_fops},
5868 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x5088, 0xff, 0xff, 0xff),
5869         .driver_info = (unsigned long)&rtl8192cu_fops},
5870 {USB_DEVICE_AND_INTERFACE_INFO(0x0df6, 0x0052, 0xff, 0xff, 0xff),
5871         .driver_info = (unsigned long)&rtl8192cu_fops},
5872 {USB_DEVICE_AND_INTERFACE_INFO(0x0df6, 0x005c, 0xff, 0xff, 0xff),
5873         .driver_info = (unsigned long)&rtl8192cu_fops},
5874 {USB_DEVICE_AND_INTERFACE_INFO(0x0eb0, 0x9071, 0xff, 0xff, 0xff),
5875         .driver_info = (unsigned long)&rtl8192cu_fops},
5876 {USB_DEVICE_AND_INTERFACE_INFO(0x103c, 0x1629, 0xff, 0xff, 0xff),
5877         .driver_info = (unsigned long)&rtl8192cu_fops},
5878 {USB_DEVICE_AND_INTERFACE_INFO(0x13d3, 0x3357, 0xff, 0xff, 0xff),
5879         .driver_info = (unsigned long)&rtl8192cu_fops},
5880 {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x3308, 0xff, 0xff, 0xff),
5881         .driver_info = (unsigned long)&rtl8192cu_fops},
5882 {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x330b, 0xff, 0xff, 0xff),
5883         .driver_info = (unsigned long)&rtl8192cu_fops},
5884 {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0x4902, 0xff, 0xff, 0xff),
5885         .driver_info = (unsigned long)&rtl8192cu_fops},
5886 {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xab2a, 0xff, 0xff, 0xff),
5887         .driver_info = (unsigned long)&rtl8192cu_fops},
5888 {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xab2e, 0xff, 0xff, 0xff),
5889         .driver_info = (unsigned long)&rtl8192cu_fops},
5890 {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xed17, 0xff, 0xff, 0xff),
5891         .driver_info = (unsigned long)&rtl8192cu_fops},
5892 {USB_DEVICE_AND_INTERFACE_INFO(0x20f4, 0x648b, 0xff, 0xff, 0xff),
5893         .driver_info = (unsigned long)&rtl8192cu_fops},
5894 {USB_DEVICE_AND_INTERFACE_INFO(0x4855, 0x0090, 0xff, 0xff, 0xff),
5895         .driver_info = (unsigned long)&rtl8192cu_fops},
5896 {USB_DEVICE_AND_INTERFACE_INFO(0x4856, 0x0091, 0xff, 0xff, 0xff),
5897         .driver_info = (unsigned long)&rtl8192cu_fops},
5898 {USB_DEVICE_AND_INTERFACE_INFO(0xcdab, 0x8010, 0xff, 0xff, 0xff),
5899         .driver_info = (unsigned long)&rtl8192cu_fops},
5900 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x317f, 0xff, 0xff, 0xff),
5901         .driver_info = (unsigned long)&rtl8192cu_fops}, /* Netcore 8188RU */
5902 {USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaff7, 0xff, 0xff, 0xff),
5903         .driver_info = (unsigned long)&rtl8192cu_fops},
5904 {USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaff9, 0xff, 0xff, 0xff),
5905         .driver_info = (unsigned long)&rtl8192cu_fops},
5906 {USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaffa, 0xff, 0xff, 0xff),
5907         .driver_info = (unsigned long)&rtl8192cu_fops},
5908 {USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaff8, 0xff, 0xff, 0xff),
5909         .driver_info = (unsigned long)&rtl8192cu_fops},
5910 {USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaffb, 0xff, 0xff, 0xff),
5911         .driver_info = (unsigned long)&rtl8192cu_fops},
5912 {USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaffc, 0xff, 0xff, 0xff),
5913         .driver_info = (unsigned long)&rtl8192cu_fops},
5914 {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0x1201, 0xff, 0xff, 0xff),
5915         .driver_info = (unsigned long)&rtl8192cu_fops},
5916 /* Currently untested 8192 series devices */
5917 {USB_DEVICE_AND_INTERFACE_INFO(0x04bb, 0x0950, 0xff, 0xff, 0xff),
5918         .driver_info = (unsigned long)&rtl8192cu_fops},
5919 {USB_DEVICE_AND_INTERFACE_INFO(0x050d, 0x1004, 0xff, 0xff, 0xff),
5920         .driver_info = (unsigned long)&rtl8192cu_fops},
5921 {USB_DEVICE_AND_INTERFACE_INFO(0x050d, 0x2102, 0xff, 0xff, 0xff),
5922         .driver_info = (unsigned long)&rtl8192cu_fops},
5923 {USB_DEVICE_AND_INTERFACE_INFO(0x050d, 0x2103, 0xff, 0xff, 0xff),
5924         .driver_info = (unsigned long)&rtl8192cu_fops},
5925 {USB_DEVICE_AND_INTERFACE_INFO(0x0586, 0x341f, 0xff, 0xff, 0xff),
5926         .driver_info = (unsigned long)&rtl8192cu_fops},
5927 {USB_DEVICE_AND_INTERFACE_INFO(0x06f8, 0xe035, 0xff, 0xff, 0xff),
5928         .driver_info = (unsigned long)&rtl8192cu_fops},
5929 {USB_DEVICE_AND_INTERFACE_INFO(0x0b05, 0x17ab, 0xff, 0xff, 0xff),
5930         .driver_info = (unsigned long)&rtl8192cu_fops},
5931 {USB_DEVICE_AND_INTERFACE_INFO(0x0df6, 0x0061, 0xff, 0xff, 0xff),
5932         .driver_info = (unsigned long)&rtl8192cu_fops},
5933 {USB_DEVICE_AND_INTERFACE_INFO(0x0df6, 0x0070, 0xff, 0xff, 0xff),
5934         .driver_info = (unsigned long)&rtl8192cu_fops},
5935 {USB_DEVICE_AND_INTERFACE_INFO(0x0789, 0x016d, 0xff, 0xff, 0xff),
5936         .driver_info = (unsigned long)&rtl8192cu_fops},
5937 {USB_DEVICE_AND_INTERFACE_INFO(0x07aa, 0x0056, 0xff, 0xff, 0xff),
5938         .driver_info = (unsigned long)&rtl8192cu_fops},
5939 {USB_DEVICE_AND_INTERFACE_INFO(0x07b8, 0x8178, 0xff, 0xff, 0xff),
5940         .driver_info = (unsigned long)&rtl8192cu_fops},
5941 {USB_DEVICE_AND_INTERFACE_INFO(0x0846, 0x9021, 0xff, 0xff, 0xff),
5942         .driver_info = (unsigned long)&rtl8192cu_fops},
5943 {USB_DEVICE_AND_INTERFACE_INFO(0x0846, 0xf001, 0xff, 0xff, 0xff),
5944         .driver_info = (unsigned long)&rtl8192cu_fops},
5945 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x2e2e, 0xff, 0xff, 0xff),
5946         .driver_info = (unsigned long)&rtl8192cu_fops},
5947 {USB_DEVICE_AND_INTERFACE_INFO(0x0e66, 0x0019, 0xff, 0xff, 0xff),
5948         .driver_info = (unsigned long)&rtl8192cu_fops},
5949 {USB_DEVICE_AND_INTERFACE_INFO(0x0e66, 0x0020, 0xff, 0xff, 0xff),
5950         .driver_info = (unsigned long)&rtl8192cu_fops},
5951 {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x3307, 0xff, 0xff, 0xff),
5952         .driver_info = (unsigned long)&rtl8192cu_fops},
5953 {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x3309, 0xff, 0xff, 0xff),
5954         .driver_info = (unsigned long)&rtl8192cu_fops},
5955 {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x330a, 0xff, 0xff, 0xff),
5956         .driver_info = (unsigned long)&rtl8192cu_fops},
5957 {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xab2b, 0xff, 0xff, 0xff),
5958         .driver_info = (unsigned long)&rtl8192cu_fops},
5959 {USB_DEVICE_AND_INTERFACE_INFO(0x20f4, 0x624d, 0xff, 0xff, 0xff),
5960         .driver_info = (unsigned long)&rtl8192cu_fops},
5961 {USB_DEVICE_AND_INTERFACE_INFO(0x2357, 0x0100, 0xff, 0xff, 0xff),
5962         .driver_info = (unsigned long)&rtl8192cu_fops},
5963 {USB_DEVICE_AND_INTERFACE_INFO(0x4855, 0x0091, 0xff, 0xff, 0xff),
5964         .driver_info = (unsigned long)&rtl8192cu_fops},
5965 {USB_DEVICE_AND_INTERFACE_INFO(0x7392, 0x7822, 0xff, 0xff, 0xff),
5966         .driver_info = (unsigned long)&rtl8192cu_fops},
5967 #endif
5968 { }
5969 };
5970
5971 static struct usb_driver rtl8xxxu_driver = {
5972         .name = DRIVER_NAME,
5973         .probe = rtl8xxxu_probe,
5974         .disconnect = rtl8xxxu_disconnect,
5975         .id_table = dev_table,
5976         .disable_hub_initiated_lpm = 1,
5977 };
5978
5979 static int __init rtl8xxxu_module_init(void)
5980 {
5981         int res;
5982
5983         res = usb_register(&rtl8xxxu_driver);
5984         if (res < 0)
5985                 pr_err(DRIVER_NAME ": usb_register() failed (%i)\n", res);
5986
5987         return res;
5988 }
5989
5990 static void __exit rtl8xxxu_module_exit(void)
5991 {
5992         usb_deregister(&rtl8xxxu_driver);
5993 }
5994
5995
5996 MODULE_DEVICE_TABLE(usb, dev_table);
5997
5998 module_init(rtl8xxxu_module_init);
5999 module_exit(rtl8xxxu_module_exit);