drivers/net/wireless/rt2x00/rt2800lib.c

   1 /*
   2         Copyright (C) 2010 Willow Garage <http://www.willowgarage.com>
   3         Copyright (C) 2010 Ivo van Doorn <IvDoorn@gmail.com>
   4         Copyright (C) 2009 Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
   5         Copyright (C) 2009 Gertjan van Wingerde <gwingerde@gmail.com>
   6
   7         Based on the original rt2800pci.c and rt2800usb.c.
   8           Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com>
   9           Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
  10           Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com>
  11           Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de>
  12           Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com>
  13           Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com>
  14           <http://rt2x00.serialmonkey.com>
  15
  16         This program is free software; you can redistribute it and/or modify
  17         it under the terms of the GNU General Public License as published by
  18         the Free Software Foundation; either version 2 of the License, or
  19         (at your option) any later version.
  20
  21         This program is distributed in the hope that it will be useful,
  22         but WITHOUT ANY WARRANTY; without even the implied warranty of
  23         MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  24         GNU General Public License for more details.
  25
  26         You should have received a copy of the GNU General Public License
  27         along with this program; if not, write to the
  28         Free Software Foundation, Inc.,
  29         59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  30  */
  31
  32 /*
  33         Module: rt2800lib
  34         Abstract: rt2800 generic device routines.
  35  */
  36
  37 #include <linux/crc-ccitt.h>
  38 #include <linux/kernel.h>
  39 #include <linux/module.h>
  40 #include <linux/slab.h>
  41
  42 #include "rt2x00.h"
  43 #include "rt2800lib.h"
  44 #include "rt2800.h"
  45
  46 /*
  47  * Register access.
  48  * All access to the CSR registers will go through the methods
  49  * rt2800_register_read and rt2800_register_write.
  50  * BBP and RF register require indirect register access,
  51  * and use the CSR registers BBPCSR and RFCSR to achieve this.
  52  * These indirect registers work with busy bits,
  53  * and we will try maximal REGISTER_BUSY_COUNT times to access
  54  * the register while taking a REGISTER_BUSY_DELAY us delay
  55  * between each attampt. When the busy bit is still set at that time,
  56  * the access attempt is considered to have failed,
  57  * and we will print an error.
  58  * The _lock versions must be used if you already hold the csr_mutex
  59  */
  60 #define WAIT_FOR_BBP(__dev, __reg) \
  61         rt2800_regbusy_read((__dev), BBP_CSR_CFG, BBP_CSR_CFG_BUSY, (__reg))
  62 #define WAIT_FOR_RFCSR(__dev, __reg) \
  63         rt2800_regbusy_read((__dev), RF_CSR_CFG, RF_CSR_CFG_BUSY, (__reg))
  64 #define WAIT_FOR_RF(__dev, __reg) \
  65         rt2800_regbusy_read((__dev), RF_CSR_CFG0, RF_CSR_CFG0_BUSY, (__reg))
  66 #define WAIT_FOR_MCU(__dev, __reg) \
  67         rt2800_regbusy_read((__dev), H2M_MAILBOX_CSR, \
  68                             H2M_MAILBOX_CSR_OWNER, (__reg))
  69
  70 static inline bool rt2800_is_305x_soc(struct rt2x00_dev *rt2x00dev)
  71 {
  72         /* check for rt2872 on SoC */
  73         if (!rt2x00_is_soc(rt2x00dev) ||
  74             !rt2x00_rt(rt2x00dev, RT2872))
  75                 return false;
  76
  77         /* we know for sure that these rf chipsets are used on rt305x boards */
  78         if (rt2x00_rf(rt2x00dev, RF3020) ||
  79             rt2x00_rf(rt2x00dev, RF3021) ||
  80             rt2x00_rf(rt2x00dev, RF3022))
  81                 return true;
  82
  83         rt2x00_warn(rt2x00dev, "Unknown RF chipset on rt305x\n");
  84         return false;
  85 }
  86
  87 static void rt2800_bbp_write(struct rt2x00_dev *rt2x00dev,
  88                              const unsigned int word, const u8 value)
  89 {
  90         u32 reg;
  91
  92         mutex_lock(&rt2x00dev->csr_mutex);
  93
  94         /*
  95          * Wait until the BBP becomes available, afterwards we
  96          * can safely write the new data into the register.
  97          */
  98         if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
  99                 reg = 0;
 100                 rt2x00_set_field32(&reg, BBP_CSR_CFG_VALUE, value);
 101                 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
 102                 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
 103                 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 0);
 104                 rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
 105
 106                 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
 107         }
 108
 109         mutex_unlock(&rt2x00dev->csr_mutex);
 110 }
 111
 112 static void rt2800_bbp_read(struct rt2x00_dev *rt2x00dev,
 113                             const unsigned int word, u8 *value)
 114 {
 115         u32 reg;
 116
 117         mutex_lock(&rt2x00dev->csr_mutex);
 118
 119         /*
 120          * Wait until the BBP becomes available, afterwards we
 121          * can safely write the read request into the register.
 122          * After the data has been written, we wait until hardware
 123          * returns the correct value, if at any time the register
 124          * doesn't become available in time, reg will be 0xffffffff
 125          * which means we return 0xff to the caller.
 126          */
 127         if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
 128                 reg = 0;
 129                 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
 130                 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
 131                 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 1);
 132                 rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
 133
 134                 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
 135
 136                 WAIT_FOR_BBP(rt2x00dev, &reg);
 137         }
 138
 139         *value = rt2x00_get_field32(reg, BBP_CSR_CFG_VALUE);
 140
 141         mutex_unlock(&rt2x00dev->csr_mutex);
 142 }
 143
 144 static void rt2800_rfcsr_write(struct rt2x00_dev *rt2x00dev,
 145                                const unsigned int word, const u8 value)
 146 {
 147         u32 reg;
 148
 149         mutex_lock(&rt2x00dev->csr_mutex);
 150
 151         /*
 152          * Wait until the RFCSR becomes available, afterwards we
 153          * can safely write the new data into the register.
 154          */
 155         if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
 156                 reg = 0;
 157                 rt2x00_set_field32(&reg, RF_CSR_CFG_DATA, value);
 158                 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
 159                 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 1);
 160                 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
 161
 162                 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
 163         }
 164
 165         mutex_unlock(&rt2x00dev->csr_mutex);
 166 }
 167
 168 static void rt2800_rfcsr_read(struct rt2x00_dev *rt2x00dev,
 169                               const unsigned int word, u8 *value)
 170 {
 171         u32 reg;
 172
 173         mutex_lock(&rt2x00dev->csr_mutex);
 174
 175         /*
 176          * Wait until the RFCSR becomes available, afterwards we
 177          * can safely write the read request into the register.
 178          * After the data has been written, we wait until hardware
 179          * returns the correct value, if at any time the register
 180          * doesn't become available in time, reg will be 0xffffffff
 181          * which means we return 0xff to the caller.
 182          */
 183         if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
 184                 reg = 0;
 185                 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
 186                 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 0);
 187                 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
 188
 189                 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
 190
 191                 WAIT_FOR_RFCSR(rt2x00dev, &reg);
 192         }
 193
 194         *value = rt2x00_get_field32(reg, RF_CSR_CFG_DATA);
 195
 196         mutex_unlock(&rt2x00dev->csr_mutex);
 197 }
 198
 199 static void rt2800_rf_write(struct rt2x00_dev *rt2x00dev,
 200                             const unsigned int word, const u32 value)
 201 {
 202         u32 reg;
 203
 204         mutex_lock(&rt2x00dev->csr_mutex);
 205
 206         /*
 207          * Wait until the RF becomes available, afterwards we
 208          * can safely write the new data into the register.
 209          */
 210         if (WAIT_FOR_RF(rt2x00dev, &reg)) {
 211                 reg = 0;
 212                 rt2x00_set_field32(&reg, RF_CSR_CFG0_REG_VALUE_BW, value);
 213                 rt2x00_set_field32(&reg, RF_CSR_CFG0_STANDBYMODE, 0);
 214                 rt2x00_set_field32(&reg, RF_CSR_CFG0_SEL, 0);
 215                 rt2x00_set_field32(&reg, RF_CSR_CFG0_BUSY, 1);
 216
 217                 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG0, reg);
 218                 rt2x00_rf_write(rt2x00dev, word, value);
 219         }
 220
 221         mutex_unlock(&rt2x00dev->csr_mutex);
 222 }
 223
 224 static const unsigned int rt2800_eeprom_map[EEPROM_WORD_COUNT] = {
 225         [EEPROM_CHIP_ID]                = 0x0000,
 226         [EEPROM_VERSION]                = 0x0001,
 227         [EEPROM_MAC_ADDR_0]             = 0x0002,
 228         [EEPROM_MAC_ADDR_1]             = 0x0003,
 229         [EEPROM_MAC_ADDR_2]             = 0x0004,
 230         [EEPROM_NIC_CONF0]              = 0x001a,
 231         [EEPROM_NIC_CONF1]              = 0x001b,
 232         [EEPROM_FREQ]                   = 0x001d,
 233         [EEPROM_LED_AG_CONF]            = 0x001e,
 234         [EEPROM_LED_ACT_CONF]           = 0x001f,
 235         [EEPROM_LED_POLARITY]           = 0x0020,
 236         [EEPROM_NIC_CONF2]              = 0x0021,
 237         [EEPROM_LNA]                    = 0x0022,
 238         [EEPROM_RSSI_BG]                = 0x0023,
 239         [EEPROM_RSSI_BG2]               = 0x0024,
 240         [EEPROM_TXMIXER_GAIN_BG]        = 0x0024, /* overlaps with RSSI_BG2 */
 241         [EEPROM_RSSI_A]                 = 0x0025,
 242         [EEPROM_RSSI_A2]                = 0x0026,
 243         [EEPROM_TXMIXER_GAIN_A]         = 0x0026, /* overlaps with RSSI_A2 */
 244         [EEPROM_EIRP_MAX_TX_POWER]      = 0x0027,
 245         [EEPROM_TXPOWER_DELTA]          = 0x0028,
 246         [EEPROM_TXPOWER_BG1]            = 0x0029,
 247         [EEPROM_TXPOWER_BG2]            = 0x0030,
 248         [EEPROM_TSSI_BOUND_BG1]         = 0x0037,
 249         [EEPROM_TSSI_BOUND_BG2]         = 0x0038,
 250         [EEPROM_TSSI_BOUND_BG3]         = 0x0039,
 251         [EEPROM_TSSI_BOUND_BG4]         = 0x003a,
 252         [EEPROM_TSSI_BOUND_BG5]         = 0x003b,
 253         [EEPROM_TXPOWER_A1]             = 0x003c,
 254         [EEPROM_TXPOWER_A2]             = 0x0053,
 255         [EEPROM_TSSI_BOUND_A1]          = 0x006a,
 256         [EEPROM_TSSI_BOUND_A2]          = 0x006b,
 257         [EEPROM_TSSI_BOUND_A3]          = 0x006c,
 258         [EEPROM_TSSI_BOUND_A4]          = 0x006d,
 259         [EEPROM_TSSI_BOUND_A5]          = 0x006e,
 260         [EEPROM_TXPOWER_BYRATE]         = 0x006f,
 261         [EEPROM_BBP_START]              = 0x0078,
 262 };
 263
 264 static const unsigned int rt2800_eeprom_map_ext[EEPROM_WORD_COUNT] = {
 265         [EEPROM_CHIP_ID]                = 0x0000,
 266         [EEPROM_VERSION]                = 0x0001,
 267         [EEPROM_MAC_ADDR_0]             = 0x0002,
 268         [EEPROM_MAC_ADDR_1]             = 0x0003,
 269         [EEPROM_MAC_ADDR_2]             = 0x0004,
 270         [EEPROM_NIC_CONF0]              = 0x001a,
 271         [EEPROM_NIC_CONF1]              = 0x001b,
 272         [EEPROM_NIC_CONF2]              = 0x001c,
 273         [EEPROM_EIRP_MAX_TX_POWER]      = 0x0020,
 274         [EEPROM_FREQ]                   = 0x0022,
 275         [EEPROM_LED_AG_CONF]            = 0x0023,
 276         [EEPROM_LED_ACT_CONF]           = 0x0024,
 277         [EEPROM_LED_POLARITY]           = 0x0025,
 278         [EEPROM_LNA]                    = 0x0026,
 279         [EEPROM_EXT_LNA2]               = 0x0027,
 280         [EEPROM_RSSI_BG]                = 0x0028,
 281         [EEPROM_TXPOWER_DELTA]          = 0x0028, /* Overlaps with RSSI_BG */
 282         [EEPROM_RSSI_BG2]               = 0x0029,
 283         [EEPROM_TXMIXER_GAIN_BG]        = 0x0029, /* Overlaps with RSSI_BG2 */
 284         [EEPROM_RSSI_A]                 = 0x002a,
 285         [EEPROM_RSSI_A2]                = 0x002b,
 286         [EEPROM_TXMIXER_GAIN_A]         = 0x002b, /* Overlaps with RSSI_A2 */
 287         [EEPROM_TXPOWER_BG1]            = 0x0030,
 288         [EEPROM_TXPOWER_BG2]            = 0x0037,
 289         [EEPROM_EXT_TXPOWER_BG3]        = 0x003e,
 290         [EEPROM_TSSI_BOUND_BG1]         = 0x0045,
 291         [EEPROM_TSSI_BOUND_BG2]         = 0x0046,
 292         [EEPROM_TSSI_BOUND_BG3]         = 0x0047,
 293         [EEPROM_TSSI_BOUND_BG4]         = 0x0048,
 294         [EEPROM_TSSI_BOUND_BG5]         = 0x0049,
 295         [EEPROM_TXPOWER_A1]             = 0x004b,
 296         [EEPROM_TXPOWER_A2]             = 0x0065,
 297         [EEPROM_EXT_TXPOWER_A3]         = 0x007f,
 298         [EEPROM_TSSI_BOUND_A1]          = 0x009a,
 299         [EEPROM_TSSI_BOUND_A2]          = 0x009b,
 300         [EEPROM_TSSI_BOUND_A3]          = 0x009c,
 301         [EEPROM_TSSI_BOUND_A4]          = 0x009d,
 302         [EEPROM_TSSI_BOUND_A5]          = 0x009e,
 303         [EEPROM_TXPOWER_BYRATE]         = 0x00a0,
 304 };
 305
 306 static unsigned int rt2800_eeprom_word_index(struct rt2x00_dev *rt2x00dev,
 307                                              const enum rt2800_eeprom_word word)
 308 {
 309         const unsigned int *map;
 310         unsigned int index;
 311
 312         if (WARN_ONCE(word >= EEPROM_WORD_COUNT,
 313                       "%s: invalid EEPROM word %d\n",
 314                       wiphy_name(rt2x00dev->hw->wiphy), word))
 315                 return 0;
 316
 317         if (rt2x00_rt(rt2x00dev, RT3593))
 318                 map = rt2800_eeprom_map_ext;
 319         else
 320                 map = rt2800_eeprom_map;
 321
 322         index = map[word];
 323
 324         /* Index 0 is valid only for EEPROM_CHIP_ID.
 325          * Otherwise it means that the offset of the
 326          * given word is not initialized in the map,
 327          * or that the field is not usable on the
 328          * actual chipset.
 329          */
 330         WARN_ONCE(word != EEPROM_CHIP_ID && index == 0,
 331                   "%s: invalid access of EEPROM word %d\n",
 332                   wiphy_name(rt2x00dev->hw->wiphy), word);
 333
 334         return index;
 335 }
 336
 337 static void *rt2800_eeprom_addr(struct rt2x00_dev *rt2x00dev,
 338                                 const enum rt2800_eeprom_word word)
 339 {
 340         unsigned int index;
 341
 342         index = rt2800_eeprom_word_index(rt2x00dev, word);
 343         return rt2x00_eeprom_addr(rt2x00dev, index);
 344 }
 345
 346 static void rt2800_eeprom_read(struct rt2x00_dev *rt2x00dev,
 347                                const enum rt2800_eeprom_word word, u16 *data)
 348 {
 349         unsigned int index;
 350
 351         index = rt2800_eeprom_word_index(rt2x00dev, word);
 352         rt2x00_eeprom_read(rt2x00dev, index, data);
 353 }
 354
 355 static void rt2800_eeprom_write(struct rt2x00_dev *rt2x00dev,
 356                                 const enum rt2800_eeprom_word word, u16 data)
 357 {
 358         unsigned int index;
 359
 360         index = rt2800_eeprom_word_index(rt2x00dev, word);
 361         rt2x00_eeprom_write(rt2x00dev, index, data);
 362 }
 363
 364 static void rt2800_eeprom_read_from_array(struct rt2x00_dev *rt2x00dev,
 365                                           const enum rt2800_eeprom_word array,
 366                                           unsigned int offset,
 367                                           u16 *data)
 368 {
 369         unsigned int index;
 370
 371         index = rt2800_eeprom_word_index(rt2x00dev, array);
 372         rt2x00_eeprom_read(rt2x00dev, index + offset, data);
 373 }
 374
 375 static int rt2800_enable_wlan_rt3290(struct rt2x00_dev *rt2x00dev)
 376 {
 377         u32 reg;
 378         int i, count;
 379
 380         rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL, &reg);
 381         if (rt2x00_get_field32(reg, WLAN_EN))
 382                 return 0;
 383
 384         rt2x00_set_field32(&reg, WLAN_GPIO_OUT_OE_BIT_ALL, 0xff);
 385         rt2x00_set_field32(&reg, FRC_WL_ANT_SET, 1);
 386         rt2x00_set_field32(&reg, WLAN_CLK_EN, 0);
 387         rt2x00_set_field32(&reg, WLAN_EN, 1);
 388         rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg);
 389
 390         udelay(REGISTER_BUSY_DELAY);
 391
 392         count = 0;
 393         do {
 394                 /*
 395                  * Check PLL_LD & XTAL_RDY.
 396                  */
 397                 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
 398                         rt2800_register_read(rt2x00dev, CMB_CTRL, &reg);
 399                         if (rt2x00_get_field32(reg, PLL_LD) &&
 400                             rt2x00_get_field32(reg, XTAL_RDY))
 401                                 break;
 402                         udelay(REGISTER_BUSY_DELAY);
 403                 }
 404
 405                 if (i >= REGISTER_BUSY_COUNT) {
 406
 407                         if (count >= 10)
 408                                 return -EIO;
 409
 410                         rt2800_register_write(rt2x00dev, 0x58, 0x018);
 411                         udelay(REGISTER_BUSY_DELAY);
 412                         rt2800_register_write(rt2x00dev, 0x58, 0x418);
 413                         udelay(REGISTER_BUSY_DELAY);
 414                         rt2800_register_write(rt2x00dev, 0x58, 0x618);
 415                         udelay(REGISTER_BUSY_DELAY);
 416                         count++;
 417                 } else {
 418                         count = 0;
 419                 }
 420
 421                 rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL, &reg);
 422                 rt2x00_set_field32(&reg, PCIE_APP0_CLK_REQ, 0);
 423                 rt2x00_set_field32(&reg, WLAN_CLK_EN, 1);
 424                 rt2x00_set_field32(&reg, WLAN_RESET, 1);
 425                 rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg);
 426                 udelay(10);
 427                 rt2x00_set_field32(&reg, WLAN_RESET, 0);
 428                 rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg);
 429                 udelay(10);
 430                 rt2800_register_write(rt2x00dev, INT_SOURCE_CSR, 0x7fffffff);
 431         } while (count != 0);
 432
 433         return 0;
 434 }
 435
 436 void rt2800_mcu_request(struct rt2x00_dev *rt2x00dev,
 437                         const u8 command, const u8 token,
 438                         const u8 arg0, const u8 arg1)
 439 {
 440         u32 reg;
 441
 442         /*
 443          * SOC devices don't support MCU requests.
 444          */
 445         if (rt2x00_is_soc(rt2x00dev))
 446                 return;
 447
 448         mutex_lock(&rt2x00dev->csr_mutex);
 449
 450         /*
 451          * Wait until the MCU becomes available, afterwards we
 452          * can safely write the new data into the register.
 453          */
 454         if (WAIT_FOR_MCU(rt2x00dev, &reg)) {
 455                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_OWNER, 1);
 456                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_CMD_TOKEN, token);
 457                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG0, arg0);
 458                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG1, arg1);
 459                 rt2800_register_write_lock(rt2x00dev, H2M_MAILBOX_CSR, reg);
 460
 461                 reg = 0;
 462                 rt2x00_set_field32(&reg, HOST_CMD_CSR_HOST_COMMAND, command);
 463                 rt2800_register_write_lock(rt2x00dev, HOST_CMD_CSR, reg);
 464         }
 465
 466         mutex_unlock(&rt2x00dev->csr_mutex);
 467 }
 468 EXPORT_SYMBOL_GPL(rt2800_mcu_request);
 469
 470 int rt2800_wait_csr_ready(struct rt2x00_dev *rt2x00dev)
 471 {
 472         unsigned int i = 0;
 473         u32 reg;
 474
 475         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
 476                 rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
 477                 if (reg && reg != ~0)
 478                         return 0;
 479                 msleep(1);
 480         }
 481
 482         rt2x00_err(rt2x00dev, "Unstable hardware\n");
 483         return -EBUSY;
 484 }
 485 EXPORT_SYMBOL_GPL(rt2800_wait_csr_ready);
 486
 487 int rt2800_wait_wpdma_ready(struct rt2x00_dev *rt2x00dev)
 488 {
 489         unsigned int i;
 490         u32 reg;
 491
 492         /*
 493          * Some devices are really slow to respond here. Wait a whole second
 494          * before timing out.
 495          */
 496         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
 497                 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
 498                 if (!rt2x00_get_field32(reg, WPDMA_GLO_CFG_TX_DMA_BUSY) &&
 499                     !rt2x00_get_field32(reg, WPDMA_GLO_CFG_RX_DMA_BUSY))
 500                         return 0;
 501
 502                 msleep(10);
 503         }
 504
 505         rt2x00_err(rt2x00dev, "WPDMA TX/RX busy [0x%08x]\n", reg);
 506         return -EACCES;
 507 }
 508 EXPORT_SYMBOL_GPL(rt2800_wait_wpdma_ready);
 509
 510 void rt2800_disable_wpdma(struct rt2x00_dev *rt2x00dev)
 511 {
 512         u32 reg;
 513
 514         rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
 515         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
 516         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
 517         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
 518         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
 519         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
 520         rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
 521 }
 522 EXPORT_SYMBOL_GPL(rt2800_disable_wpdma);
 523
 524 static bool rt2800_check_firmware_crc(const u8 *data, const size_t len)
 525 {
 526         u16 fw_crc;
 527         u16 crc;
 528
 529         /*
 530          * The last 2 bytes in the firmware array are the crc checksum itself,
 531          * this means that we should never pass those 2 bytes to the crc
 532          * algorithm.
 533          */
 534         fw_crc = (data[len - 2] << 8 | data[len - 1]);
 535
 536         /*
 537          * Use the crc ccitt algorithm.
 538          * This will return the same value as the legacy driver which
 539          * used bit ordering reversion on the both the firmware bytes
 540          * before input input as well as on the final output.
 541          * Obviously using crc ccitt directly is much more efficient.
 542          */
 543         crc = crc_ccitt(~0, data, len - 2);
 544
 545         /*
 546          * There is a small difference between the crc-itu-t + bitrev and
 547          * the crc-ccitt crc calculation. In the latter method the 2 bytes
 548          * will be swapped, use swab16 to convert the crc to the correct
 549          * value.
 550          */
 551         crc = swab16(crc);
 552
 553         return fw_crc == crc;
 554 }
 555
 556 int rt2800_check_firmware(struct rt2x00_dev *rt2x00dev,
 557                           const u8 *data, const size_t len)
 558 {
 559         size_t offset = 0;
 560         size_t fw_len;
 561         bool multiple;
 562
 563         /*
 564          * PCI(e) & SOC devices require firmware with a length
 565          * of 8kb. USB devices require firmware files with a length
 566          * of 4kb. Certain USB chipsets however require different firmware,
 567          * which Ralink only provides attached to the original firmware
 568          * file. Thus for USB devices, firmware files have a length
 569          * which is a multiple of 4kb. The firmware for rt3290 chip also
 570          * have a length which is a multiple of 4kb.
 571          */
 572         if (rt2x00_is_usb(rt2x00dev) || rt2x00_rt(rt2x00dev, RT3290))
 573                 fw_len = 4096;
 574         else
 575                 fw_len = 8192;
 576
 577         multiple = true;
 578         /*
 579          * Validate the firmware length
 580          */
 581         if (len != fw_len && (!multiple || (len % fw_len) != 0))
 582                 return FW_BAD_LENGTH;
 583
 584         /*
 585          * Check if the chipset requires one of the upper parts
 586          * of the firmware.
 587          */
 588         if (rt2x00_is_usb(rt2x00dev) &&
 589             !rt2x00_rt(rt2x00dev, RT2860) &&
 590             !rt2x00_rt(rt2x00dev, RT2872) &&
 591             !rt2x00_rt(rt2x00dev, RT3070) &&
 592             ((len / fw_len) == 1))
 593                 return FW_BAD_VERSION;
 594
 595         /*
 596          * 8kb firmware files must be checked as if it were
 597          * 2 separate firmware files.
 598          */
 599         while (offset < len) {
 600                 if (!rt2800_check_firmware_crc(data + offset, fw_len))
 601                         return FW_BAD_CRC;
 602
 603                 offset += fw_len;
 604         }
 605
 606         return FW_OK;
 607 }
 608 EXPORT_SYMBOL_GPL(rt2800_check_firmware);
 609
 610 int rt2800_load_firmware(struct rt2x00_dev *rt2x00dev,
 611                          const u8 *data, const size_t len)
 612 {
 613         unsigned int i;
 614         u32 reg;
 615         int retval;
 616
 617         if (rt2x00_rt(rt2x00dev, RT3290)) {
 618                 retval = rt2800_enable_wlan_rt3290(rt2x00dev);
 619                 if (retval)
 620                         return -EBUSY;
 621         }
 622
 623         /*
 624          * If driver doesn't wake up firmware here,
 625          * rt2800_load_firmware will hang forever when interface is up again.
 626          */
 627         rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0x00000000);
 628
 629         /*
 630          * Wait for stable hardware.
 631          */
 632         if (rt2800_wait_csr_ready(rt2x00dev))
 633                 return -EBUSY;
 634
 635         if (rt2x00_is_pci(rt2x00dev)) {
 636                 if (rt2x00_rt(rt2x00dev, RT3290) ||
 637                     rt2x00_rt(rt2x00dev, RT3572) ||
 638                     rt2x00_rt(rt2x00dev, RT5390) ||
 639                     rt2x00_rt(rt2x00dev, RT5392)) {
 640                         rt2800_register_read(rt2x00dev, AUX_CTRL, &reg);
 641                         rt2x00_set_field32(&reg, AUX_CTRL_FORCE_PCIE_CLK, 1);
 642                         rt2x00_set_field32(&reg, AUX_CTRL_WAKE_PCIE_EN, 1);
 643                         rt2800_register_write(rt2x00dev, AUX_CTRL, reg);
 644                 }
 645                 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000002);
 646         }
 647
 648         rt2800_disable_wpdma(rt2x00dev);
 649
 650         /*
 651          * Write firmware to the device.
 652          */
 653         rt2800_drv_write_firmware(rt2x00dev, data, len);
 654
 655         /*
 656          * Wait for device to stabilize.
 657          */
 658         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
 659                 rt2800_register_read(rt2x00dev, PBF_SYS_CTRL, &reg);
 660                 if (rt2x00_get_field32(reg, PBF_SYS_CTRL_READY))
 661                         break;
 662                 msleep(1);
 663         }
 664
 665         if (i == REGISTER_BUSY_COUNT) {
 666                 rt2x00_err(rt2x00dev, "PBF system register not ready\n");
 667                 return -EBUSY;
 668         }
 669
 670         /*
 671          * Disable DMA, will be reenabled later when enabling
 672          * the radio.
 673          */
 674         rt2800_disable_wpdma(rt2x00dev);
 675
 676         /*
 677          * Initialize firmware.
 678          */
 679         rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
 680         rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
 681         if (rt2x00_is_usb(rt2x00dev)) {
 682                 rt2800_register_write(rt2x00dev, H2M_INT_SRC, 0);
 683                 rt2800_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0, 0, 0);
 684         }
 685         msleep(1);
 686
 687         return 0;
 688 }
 689 EXPORT_SYMBOL_GPL(rt2800_load_firmware);
 690
 691 void rt2800_write_tx_data(struct queue_entry *entry,
 692                           struct txentry_desc *txdesc)
 693 {
 694         __le32 *txwi = rt2800_drv_get_txwi(entry);
 695         u32 word;
 696         int i;
 697
 698         /*
 699          * Initialize TX Info descriptor
 700          */
 701         rt2x00_desc_read(txwi, 0, &word);
 702         rt2x00_set_field32(&word, TXWI_W0_FRAG,
 703                            test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
 704         rt2x00_set_field32(&word, TXWI_W0_MIMO_PS,
 705                            test_bit(ENTRY_TXD_HT_MIMO_PS, &txdesc->flags));
 706         rt2x00_set_field32(&word, TXWI_W0_CF_ACK, 0);
 707         rt2x00_set_field32(&word, TXWI_W0_TS,
 708                            test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
 709         rt2x00_set_field32(&word, TXWI_W0_AMPDU,
 710                            test_bit(ENTRY_TXD_HT_AMPDU, &txdesc->flags));
 711         rt2x00_set_field32(&word, TXWI_W0_MPDU_DENSITY,
 712                            txdesc->u.ht.mpdu_density);
 713         rt2x00_set_field32(&word, TXWI_W0_TX_OP, txdesc->u.ht.txop);
 714         rt2x00_set_field32(&word, TXWI_W0_MCS, txdesc->u.ht.mcs);
 715         rt2x00_set_field32(&word, TXWI_W0_BW,
 716                            test_bit(ENTRY_TXD_HT_BW_40, &txdesc->flags));
 717         rt2x00_set_field32(&word, TXWI_W0_SHORT_GI,
 718                            test_bit(ENTRY_TXD_HT_SHORT_GI, &txdesc->flags));
 719         rt2x00_set_field32(&word, TXWI_W0_STBC, txdesc->u.ht.stbc);
 720         rt2x00_set_field32(&word, TXWI_W0_PHYMODE, txdesc->rate_mode);
 721         rt2x00_desc_write(txwi, 0, word);
 722
 723         rt2x00_desc_read(txwi, 1, &word);
 724         rt2x00_set_field32(&word, TXWI_W1_ACK,
 725                            test_bit(ENTRY_TXD_ACK, &txdesc->flags));
 726         rt2x00_set_field32(&word, TXWI_W1_NSEQ,
 727                            test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags));
 728         rt2x00_set_field32(&word, TXWI_W1_BW_WIN_SIZE, txdesc->u.ht.ba_size);
 729         rt2x00_set_field32(&word, TXWI_W1_WIRELESS_CLI_ID,
 730                            test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags) ?
 731                            txdesc->key_idx : txdesc->u.ht.wcid);
 732         rt2x00_set_field32(&word, TXWI_W1_MPDU_TOTAL_BYTE_COUNT,
 733                            txdesc->length);
 734         rt2x00_set_field32(&word, TXWI_W1_PACKETID_QUEUE, entry->queue->qid);
 735         rt2x00_set_field32(&word, TXWI_W1_PACKETID_ENTRY, (entry->entry_idx % 3) + 1);
 736         rt2x00_desc_write(txwi, 1, word);
 737
 738         /*
 739          * Always write 0 to IV/EIV fields (word 2 and 3), hardware will insert
 740          * the IV from the IVEIV register when TXD_W3_WIV is set to 0.
 741          * When TXD_W3_WIV is set to 1 it will use the IV data
 742          * from the descriptor. The TXWI_W1_WIRELESS_CLI_ID indicates which
 743          * crypto entry in the registers should be used to encrypt the frame.
 744          *
 745          * Nulify all remaining words as well, we don't know how to program them.
 746          */
 747         for (i = 2; i < entry->queue->winfo_size / sizeof(__le32); i++)
 748                 _rt2x00_desc_write(txwi, i, 0);
 749 }
 750 EXPORT_SYMBOL_GPL(rt2800_write_tx_data);
 751
 752 static int rt2800_agc_to_rssi(struct rt2x00_dev *rt2x00dev, u32 rxwi_w2)
 753 {
 754         s8 rssi0 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI0);
 755         s8 rssi1 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI1);
 756         s8 rssi2 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI2);
 757         u16 eeprom;
 758         u8 offset0;
 759         u8 offset1;
 760         u8 offset2;
 761
 762         if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
 763                 rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &eeprom);
 764                 offset0 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG_OFFSET0);
 765                 offset1 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG_OFFSET1);
 766                 rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom);
 767                 offset2 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_OFFSET2);
 768         } else {
 769                 rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &eeprom);
 770                 offset0 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A_OFFSET0);
 771                 offset1 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A_OFFSET1);
 772                 rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom);
 773                 offset2 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_OFFSET2);
 774         }
 775
 776         /*
 777          * Convert the value from the descriptor into the RSSI value
 778          * If the value in the descriptor is 0, it is considered invalid
 779          * and the default (extremely low) rssi value is assumed
 780          */
 781         rssi0 = (rssi0) ? (-12 - offset0 - rt2x00dev->lna_gain - rssi0) : -128;
 782         rssi1 = (rssi1) ? (-12 - offset1 - rt2x00dev->lna_gain - rssi1) : -128;
 783         rssi2 = (rssi2) ? (-12 - offset2 - rt2x00dev->lna_gain - rssi2) : -128;
 784
 785         /*
 786          * mac80211 only accepts a single RSSI value. Calculating the
 787          * average doesn't deliver a fair answer either since -60:-60 would
 788          * be considered equally good as -50:-70 while the second is the one
 789          * which gives less energy...
 790          */
 791         rssi0 = max(rssi0, rssi1);
 792         return (int)max(rssi0, rssi2);
 793 }
 794
 795 void rt2800_process_rxwi(struct queue_entry *entry,
 796                          struct rxdone_entry_desc *rxdesc)
 797 {
 798         __le32 *rxwi = (__le32 *) entry->skb->data;
 799         u32 word;
 800
 801         rt2x00_desc_read(rxwi, 0, &word);
 802
 803         rxdesc->cipher = rt2x00_get_field32(word, RXWI_W0_UDF);
 804         rxdesc->size = rt2x00_get_field32(word, RXWI_W0_MPDU_TOTAL_BYTE_COUNT);
 805
 806         rt2x00_desc_read(rxwi, 1, &word);
 807
 808         if (rt2x00_get_field32(word, RXWI_W1_SHORT_GI))
 809                 rxdesc->flags |= RX_FLAG_SHORT_GI;
 810
 811         if (rt2x00_get_field32(word, RXWI_W1_BW))
 812                 rxdesc->flags |= RX_FLAG_40MHZ;
 813
 814         /*
 815          * Detect RX rate, always use MCS as signal type.
 816          */
 817         rxdesc->dev_flags |= RXDONE_SIGNAL_MCS;
 818         rxdesc->signal = rt2x00_get_field32(word, RXWI_W1_MCS);
 819         rxdesc->rate_mode = rt2x00_get_field32(word, RXWI_W1_PHYMODE);
 820
 821         /*
 822          * Mask of 0x8 bit to remove the short preamble flag.
 823          */
 824         if (rxdesc->rate_mode == RATE_MODE_CCK)
 825                 rxdesc->signal &= ~0x8;
 826
 827         rt2x00_desc_read(rxwi, 2, &word);
 828
 829         /*
 830          * Convert descriptor AGC value to RSSI value.
 831          */
 832         rxdesc->rssi = rt2800_agc_to_rssi(entry->queue->rt2x00dev, word);
 833         /*
 834          * Remove RXWI descriptor from start of the buffer.
 835          */
 836         skb_pull(entry->skb, entry->queue->winfo_size);
 837 }
 838 EXPORT_SYMBOL_GPL(rt2800_process_rxwi);
 839
 840 void rt2800_txdone_entry(struct queue_entry *entry, u32 status, __le32 *txwi)
 841 {
 842         struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
 843         struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
 844         struct txdone_entry_desc txdesc;
 845         u32 word;
 846         u16 mcs, real_mcs;
 847         int aggr, ampdu;
 848
 849         /*
 850          * Obtain the status about this packet.
 851          */
 852         txdesc.flags = 0;
 853         rt2x00_desc_read(txwi, 0, &word);
 854
 855         mcs = rt2x00_get_field32(word, TXWI_W0_MCS);
 856         ampdu = rt2x00_get_field32(word, TXWI_W0_AMPDU);
 857
 858         real_mcs = rt2x00_get_field32(status, TX_STA_FIFO_MCS);
 859         aggr = rt2x00_get_field32(status, TX_STA_FIFO_TX_AGGRE);
 860
 861         /*
 862          * If a frame was meant to be sent as a single non-aggregated MPDU
 863          * but ended up in an aggregate the used tx rate doesn't correlate
 864          * with the one specified in the TXWI as the whole aggregate is sent
 865          * with the same rate.
 866          *
 867          * For example: two frames are sent to rt2x00, the first one sets
 868          * AMPDU=1 and requests MCS7 whereas the second frame sets AMDPU=0
 869          * and requests MCS15. If the hw aggregates both frames into one
 870          * AMDPU the tx status for both frames will contain MCS7 although
 871          * the frame was sent successfully.
 872          *
 873          * Hence, replace the requested rate with the real tx rate to not
 874          * confuse the rate control algortihm by providing clearly wrong
 875          * data.
 876          */
 877         if (unlikely(aggr == 1 && ampdu == 0 && real_mcs != mcs)) {
 878                 skbdesc->tx_rate_idx = real_mcs;
 879                 mcs = real_mcs;
 880         }
 881
 882         if (aggr == 1 || ampdu == 1)
 883                 __set_bit(TXDONE_AMPDU, &txdesc.flags);
 884
 885         /*
 886          * Ralink has a retry mechanism using a global fallback
 887          * table. We setup this fallback table to try the immediate
 888          * lower rate for all rates. In the TX_STA_FIFO, the MCS field
 889          * always contains the MCS used for the last transmission, be
 890          * it successful or not.
 891          */
 892         if (rt2x00_get_field32(status, TX_STA_FIFO_TX_SUCCESS)) {
 893                 /*
 894                  * Transmission succeeded. The number of retries is
 895                  * mcs - real_mcs
 896                  */
 897                 __set_bit(TXDONE_SUCCESS, &txdesc.flags);
 898                 txdesc.retry = ((mcs > real_mcs) ? mcs - real_mcs : 0);
 899         } else {
 900                 /*
 901                  * Transmission failed. The number of retries is
 902                  * always 7 in this case (for a total number of 8
 903                  * frames sent).
 904                  */
 905                 __set_bit(TXDONE_FAILURE, &txdesc.flags);
 906                 txdesc.retry = rt2x00dev->long_retry;
 907         }
 908
 909         /*
 910          * the frame was retried at least once
 911          * -> hw used fallback rates
 912          */
 913         if (txdesc.retry)
 914                 __set_bit(TXDONE_FALLBACK, &txdesc.flags);
 915
 916         rt2x00lib_txdone(entry, &txdesc);
 917 }
 918 EXPORT_SYMBOL_GPL(rt2800_txdone_entry);
 919
 920 void rt2800_write_beacon(struct queue_entry *entry, struct txentry_desc *txdesc)
 921 {
 922         struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
 923         struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
 924         unsigned int beacon_base;
 925         unsigned int padding_len;
 926         u32 orig_reg, reg;
 927         const int txwi_desc_size = entry->queue->winfo_size;
 928
 929         /*
 930          * Disable beaconing while we are reloading the beacon data,
 931          * otherwise we might be sending out invalid data.
 932          */
 933         rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
 934         orig_reg = reg;
 935         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
 936         rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
 937
 938         /*
 939          * Add space for the TXWI in front of the skb.
 940          */
 941         memset(skb_push(entry->skb, txwi_desc_size), 0, txwi_desc_size);
 942
 943         /*
 944          * Register descriptor details in skb frame descriptor.
 945          */
 946         skbdesc->flags |= SKBDESC_DESC_IN_SKB;
 947         skbdesc->desc = entry->skb->data;
 948         skbdesc->desc_len = txwi_desc_size;
 949
 950         /*
 951          * Add the TXWI for the beacon to the skb.
 952          */
 953         rt2800_write_tx_data(entry, txdesc);
 954
 955         /*
 956          * Dump beacon to userspace through debugfs.
 957          */
 958         rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_BEACON, entry->skb);
 959
 960         /*
 961          * Write entire beacon with TXWI and padding to register.
 962          */
 963         padding_len = roundup(entry->skb->len, 4) - entry->skb->len;
 964         if (padding_len && skb_pad(entry->skb, padding_len)) {
 965                 rt2x00_err(rt2x00dev, "Failure padding beacon, aborting\n");
 966                 /* skb freed by skb_pad() on failure */
 967                 entry->skb = NULL;
 968                 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, orig_reg);
 969                 return;
 970         }
 971
 972         beacon_base = HW_BEACON_OFFSET(entry->entry_idx);
 973         rt2800_register_multiwrite(rt2x00dev, beacon_base, entry->skb->data,
 974                                    entry->skb->len + padding_len);
 975
 976         /*
 977          * Enable beaconing again.
 978          */
 979         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 1);
 980         rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
 981
 982         /*
 983          * Clean up beacon skb.
 984          */
 985         dev_kfree_skb_any(entry->skb);
 986         entry->skb = NULL;
 987 }
 988 EXPORT_SYMBOL_GPL(rt2800_write_beacon);
 989
 990 static inline void rt2800_clear_beacon_register(struct rt2x00_dev *rt2x00dev,
 991                                                 unsigned int beacon_base)
 992 {
 993         int i;
 994         const int txwi_desc_size = rt2x00dev->bcn->winfo_size;
 995
 996         /*
 997          * For the Beacon base registers we only need to clear
 998          * the whole TXWI which (when set to 0) will invalidate
 999          * the entire beacon.
1000          */
1001         for (i = 0; i < txwi_desc_size; i += sizeof(__le32))
1002                 rt2800_register_write(rt2x00dev, beacon_base + i, 0);
1003 }
1004
1005 void rt2800_clear_beacon(struct queue_entry *entry)
1006 {
1007         struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1008         u32 reg;
1009
1010         /*
1011          * Disable beaconing while we are reloading the beacon data,
1012          * otherwise we might be sending out invalid data.
1013          */
1014         rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
1015         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
1016         rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1017
1018         /*
1019          * Clear beacon.
1020          */
1021         rt2800_clear_beacon_register(rt2x00dev,
1022                                      HW_BEACON_OFFSET(entry->entry_idx));
1023
1024         /*
1025          * Enabled beaconing again.
1026          */
1027         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 1);
1028         rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1029 }
1030 EXPORT_SYMBOL_GPL(rt2800_clear_beacon);
1031
1032 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
1033 const struct rt2x00debug rt2800_rt2x00debug = {
1034         .owner  = THIS_MODULE,
1035         .csr    = {
1036                 .read           = rt2800_register_read,
1037                 .write          = rt2800_register_write,
1038                 .flags          = RT2X00DEBUGFS_OFFSET,
1039                 .word_base      = CSR_REG_BASE,
1040                 .word_size      = sizeof(u32),
1041                 .word_count     = CSR_REG_SIZE / sizeof(u32),
1042         },
1043         .eeprom = {
1044                 /* NOTE: The local EEPROM access functions can't
1045                  * be used here, use the generic versions instead.
1046                  */
1047                 .read           = rt2x00_eeprom_read,
1048                 .write          = rt2x00_eeprom_write,
1049                 .word_base      = EEPROM_BASE,
1050                 .word_size      = sizeof(u16),
1051                 .word_count     = EEPROM_SIZE / sizeof(u16),
1052         },
1053         .bbp    = {
1054                 .read           = rt2800_bbp_read,
1055                 .write          = rt2800_bbp_write,
1056                 .word_base      = BBP_BASE,
1057                 .word_size      = sizeof(u8),
1058                 .word_count     = BBP_SIZE / sizeof(u8),
1059         },
1060         .rf     = {
1061                 .read           = rt2x00_rf_read,
1062                 .write          = rt2800_rf_write,
1063                 .word_base      = RF_BASE,
1064                 .word_size      = sizeof(u32),
1065                 .word_count     = RF_SIZE / sizeof(u32),
1066         },
1067         .rfcsr  = {
1068                 .read           = rt2800_rfcsr_read,
1069                 .write          = rt2800_rfcsr_write,
1070                 .word_base      = RFCSR_BASE,
1071                 .word_size      = sizeof(u8),
1072                 .word_count     = RFCSR_SIZE / sizeof(u8),
1073         },
1074 };
1075 EXPORT_SYMBOL_GPL(rt2800_rt2x00debug);
1076 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
1077
1078 int rt2800_rfkill_poll(struct rt2x00_dev *rt2x00dev)
1079 {
1080         u32 reg;
1081
1082         if (rt2x00_rt(rt2x00dev, RT3290)) {
1083                 rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL, &reg);
1084                 return rt2x00_get_field32(reg, WLAN_GPIO_IN_BIT0);
1085         } else {
1086                 rt2800_register_read(rt2x00dev, GPIO_CTRL, &reg);
1087                 return rt2x00_get_field32(reg, GPIO_CTRL_VAL2);
1088         }
1089 }
1090 EXPORT_SYMBOL_GPL(rt2800_rfkill_poll);
1091
1092 #ifdef CONFIG_RT2X00_LIB_LEDS
1093 static void rt2800_brightness_set(struct led_classdev *led_cdev,
1094                                   enum led_brightness brightness)
1095 {
1096         struct rt2x00_led *led =
1097             container_of(led_cdev, struct rt2x00_led, led_dev);
1098         unsigned int enabled = brightness != LED_OFF;
1099         unsigned int bg_mode =
1100             (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
1101         unsigned int polarity =
1102                 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
1103                                    EEPROM_FREQ_LED_POLARITY);
1104         unsigned int ledmode =
1105                 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
1106                                    EEPROM_FREQ_LED_MODE);
1107         u32 reg;
1108
1109         /* Check for SoC (SOC devices don't support MCU requests) */
1110         if (rt2x00_is_soc(led->rt2x00dev)) {
1111                 rt2800_register_read(led->rt2x00dev, LED_CFG, &reg);
1112
1113                 /* Set LED Polarity */
1114                 rt2x00_set_field32(&reg, LED_CFG_LED_POLAR, polarity);
1115
1116                 /* Set LED Mode */
1117                 if (led->type == LED_TYPE_RADIO) {
1118                         rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE,
1119                                            enabled ? 3 : 0);
1120                 } else if (led->type == LED_TYPE_ASSOC) {
1121                         rt2x00_set_field32(&reg, LED_CFG_Y_LED_MODE,
1122                                            enabled ? 3 : 0);
1123                 } else if (led->type == LED_TYPE_QUALITY) {
1124                         rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE,
1125                                            enabled ? 3 : 0);
1126                 }
1127
1128                 rt2800_register_write(led->rt2x00dev, LED_CFG, reg);
1129
1130         } else {
1131                 if (led->type == LED_TYPE_RADIO) {
1132                         rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
1133                                               enabled ? 0x20 : 0);
1134                 } else if (led->type == LED_TYPE_ASSOC) {
1135                         rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
1136                                               enabled ? (bg_mode ? 0x60 : 0xa0) : 0x20);
1137                 } else if (led->type == LED_TYPE_QUALITY) {
1138                         /*
1139                          * The brightness is divided into 6 levels (0 - 5),
1140                          * The specs tell us the following levels:
1141                          *      0, 1 ,3, 7, 15, 31
1142                          * to determine the level in a simple way we can simply
1143                          * work with bitshifting:
1144                          *      (1 << level) - 1
1145                          */
1146                         rt2800_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff,
1147                                               (1 << brightness / (LED_FULL / 6)) - 1,
1148                                               polarity);
1149                 }
1150         }
1151 }
1152
1153 static void rt2800_init_led(struct rt2x00_dev *rt2x00dev,
1154                      struct rt2x00_led *led, enum led_type type)
1155 {
1156         led->rt2x00dev = rt2x00dev;
1157         led->type = type;
1158         led->led_dev.brightness_set = rt2800_brightness_set;
1159         led->flags = LED_INITIALIZED;
1160 }
1161 #endif /* CONFIG_RT2X00_LIB_LEDS */
1162
1163 /*
1164  * Configuration handlers.
1165  */
1166 static void rt2800_config_wcid(struct rt2x00_dev *rt2x00dev,
1167                                const u8 *address,
1168                                int wcid)
1169 {
1170         struct mac_wcid_entry wcid_entry;
1171         u32 offset;
1172
1173         offset = MAC_WCID_ENTRY(wcid);
1174
1175         memset(&wcid_entry, 0xff, sizeof(wcid_entry));
1176         if (address)
1177                 memcpy(wcid_entry.mac, address, ETH_ALEN);
1178
1179         rt2800_register_multiwrite(rt2x00dev, offset,
1180                                       &wcid_entry, sizeof(wcid_entry));
1181 }
1182
1183 static void rt2800_delete_wcid_attr(struct rt2x00_dev *rt2x00dev, int wcid)
1184 {
1185         u32 offset;
1186         offset = MAC_WCID_ATTR_ENTRY(wcid);
1187         rt2800_register_write(rt2x00dev, offset, 0);
1188 }
1189
1190 static void rt2800_config_wcid_attr_bssidx(struct rt2x00_dev *rt2x00dev,
1191                                            int wcid, u32 bssidx)
1192 {
1193         u32 offset = MAC_WCID_ATTR_ENTRY(wcid);
1194         u32 reg;
1195
1196         /*
1197          * The BSS Idx numbers is split in a main value of 3 bits,
1198          * and a extended field for adding one additional bit to the value.
1199          */
1200         rt2800_register_read(rt2x00dev, offset, &reg);
1201         rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX, (bssidx & 0x7));
1202         rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX_EXT,
1203                            (bssidx & 0x8) >> 3);
1204         rt2800_register_write(rt2x00dev, offset, reg);
1205 }
1206
1207 static void rt2800_config_wcid_attr_cipher(struct rt2x00_dev *rt2x00dev,
1208                                            struct rt2x00lib_crypto *crypto,
1209                                            struct ieee80211_key_conf *key)
1210 {
1211         struct mac_iveiv_entry iveiv_entry;
1212         u32 offset;
1213         u32 reg;
1214
1215         offset = MAC_WCID_ATTR_ENTRY(key->hw_key_idx);
1216
1217         if (crypto->cmd == SET_KEY) {
1218                 rt2800_register_read(rt2x00dev, offset, &reg);
1219                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_KEYTAB,
1220                                    !!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE));
1221                 /*
1222                  * Both the cipher as the BSS Idx numbers are split in a main
1223                  * value of 3 bits, and a extended field for adding one additional
1224                  * bit to the value.
1225                  */
1226                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER,
1227                                    (crypto->cipher & 0x7));
1228                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER_EXT,
1229                                    (crypto->cipher & 0x8) >> 3);
1230                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_RX_WIUDF, crypto->cipher);
1231                 rt2800_register_write(rt2x00dev, offset, reg);
1232         } else {
1233                 /* Delete the cipher without touching the bssidx */
1234                 rt2800_register_read(rt2x00dev, offset, &reg);
1235                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_KEYTAB, 0);
1236                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER, 0);
1237                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER_EXT, 0);
1238                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_RX_WIUDF, 0);
1239                 rt2800_register_write(rt2x00dev, offset, reg);
1240         }
1241
1242         offset = MAC_IVEIV_ENTRY(key->hw_key_idx);
1243
1244         memset(&iveiv_entry, 0, sizeof(iveiv_entry));
1245         if ((crypto->cipher == CIPHER_TKIP) ||
1246             (crypto->cipher == CIPHER_TKIP_NO_MIC) ||
1247             (crypto->cipher == CIPHER_AES))
1248                 iveiv_entry.iv[3] |= 0x20;
1249         iveiv_entry.iv[3] |= key->keyidx << 6;
1250         rt2800_register_multiwrite(rt2x00dev, offset,
1251                                       &iveiv_entry, sizeof(iveiv_entry));
1252 }
1253
1254 int rt2800_config_shared_key(struct rt2x00_dev *rt2x00dev,
1255                              struct rt2x00lib_crypto *crypto,
1256                              struct ieee80211_key_conf *key)
1257 {
1258         struct hw_key_entry key_entry;
1259         struct rt2x00_field32 field;
1260         u32 offset;
1261         u32 reg;
1262
1263         if (crypto->cmd == SET_KEY) {
1264                 key->hw_key_idx = (4 * crypto->bssidx) + key->keyidx;
1265
1266                 memcpy(key_entry.key, crypto->key,
1267                        sizeof(key_entry.key));
1268                 memcpy(key_entry.tx_mic, crypto->tx_mic,
1269                        sizeof(key_entry.tx_mic));
1270                 memcpy(key_entry.rx_mic, crypto->rx_mic,
1271                        sizeof(key_entry.rx_mic));
1272
1273                 offset = SHARED_KEY_ENTRY(key->hw_key_idx);
1274                 rt2800_register_multiwrite(rt2x00dev, offset,
1275                                               &key_entry, sizeof(key_entry));
1276         }
1277
1278         /*
1279          * The cipher types are stored over multiple registers
1280          * starting with SHARED_KEY_MODE_BASE each word will have
1281          * 32 bits and contains the cipher types for 2 bssidx each.
1282          * Using the correct defines correctly will cause overhead,
1283          * so just calculate the correct offset.
1284          */
1285         field.bit_offset = 4 * (key->hw_key_idx % 8);
1286         field.bit_mask = 0x7 << field.bit_offset;
1287
1288         offset = SHARED_KEY_MODE_ENTRY(key->hw_key_idx / 8);
1289
1290         rt2800_register_read(rt2x00dev, offset, &reg);
1291         rt2x00_set_field32(&reg, field,
1292                            (crypto->cmd == SET_KEY) * crypto->cipher);
1293         rt2800_register_write(rt2x00dev, offset, reg);
1294
1295         /*
1296          * Update WCID information
1297          */
1298         rt2800_config_wcid(rt2x00dev, crypto->address, key->hw_key_idx);
1299         rt2800_config_wcid_attr_bssidx(rt2x00dev, key->hw_key_idx,
1300                                        crypto->bssidx);
1301         rt2800_config_wcid_attr_cipher(rt2x00dev, crypto, key);
1302
1303         return 0;
1304 }
1305 EXPORT_SYMBOL_GPL(rt2800_config_shared_key);
1306
1307 static inline int rt2800_find_wcid(struct rt2x00_dev *rt2x00dev)
1308 {
1309         struct mac_wcid_entry wcid_entry;
1310         int idx;
1311         u32 offset;
1312
1313         /*
1314          * Search for the first free WCID entry and return the corresponding
1315          * index.
1316          *
1317          * Make sure the WCID starts _after_ the last possible shared key
1318          * entry (>32).
1319          *
1320          * Since parts of the pairwise key table might be shared with
1321          * the beacon frame buffers 6 & 7 we should only write into the
1322          * first 222 entries.
1323          */
1324         for (idx = 33; idx <= 222; idx++) {
1325                 offset = MAC_WCID_ENTRY(idx);
1326                 rt2800_register_multiread(rt2x00dev, offset, &wcid_entry,
1327                                           sizeof(wcid_entry));
1328                 if (is_broadcast_ether_addr(wcid_entry.mac))
1329                         return idx;
1330         }
1331
1332         /*
1333          * Use -1 to indicate that we don't have any more space in the WCID
1334          * table.
1335          */
1336         return -1;
1337 }
1338
1339 int rt2800_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
1340                                struct rt2x00lib_crypto *crypto,
1341                                struct ieee80211_key_conf *key)
1342 {
1343         struct hw_key_entry key_entry;
1344         u32 offset;
1345
1346         if (crypto->cmd == SET_KEY) {
1347                 /*
1348                  * Allow key configuration only for STAs that are
1349                  * known by the hw.
1350                  */
1351                 if (crypto->wcid < 0)
1352                         return -ENOSPC;
1353                 key->hw_key_idx = crypto->wcid;
1354
1355                 memcpy(key_entry.key, crypto->key,
1356                        sizeof(key_entry.key));
1357                 memcpy(key_entry.tx_mic, crypto->tx_mic,
1358                        sizeof(key_entry.tx_mic));
1359                 memcpy(key_entry.rx_mic, crypto->rx_mic,
1360                        sizeof(key_entry.rx_mic));
1361
1362                 offset = PAIRWISE_KEY_ENTRY(key->hw_key_idx);
1363                 rt2800_register_multiwrite(rt2x00dev, offset,
1364                                               &key_entry, sizeof(key_entry));
1365         }
1366
1367         /*
1368          * Update WCID information
1369          */
1370         rt2800_config_wcid_attr_cipher(rt2x00dev, crypto, key);
1371
1372         return 0;
1373 }
1374 EXPORT_SYMBOL_GPL(rt2800_config_pairwise_key);
1375
1376 int rt2800_sta_add(struct rt2x00_dev *rt2x00dev, struct ieee80211_vif *vif,
1377                    struct ieee80211_sta *sta)
1378 {
1379         int wcid;
1380         struct rt2x00_sta *sta_priv = sta_to_rt2x00_sta(sta);
1381
1382         /*
1383          * Find next free WCID.
1384          */
1385         wcid = rt2800_find_wcid(rt2x00dev);
1386
1387         /*
1388          * Store selected wcid even if it is invalid so that we can
1389          * later decide if the STA is uploaded into the hw.
1390          */
1391         sta_priv->wcid = wcid;
1392
1393         /*
1394          * No space left in the device, however, we can still communicate
1395          * with the STA -> No error.
1396          */
1397         if (wcid < 0)
1398                 return 0;
1399
1400         /*
1401          * Clean up WCID attributes and write STA address to the device.
1402          */
1403         rt2800_delete_wcid_attr(rt2x00dev, wcid);
1404         rt2800_config_wcid(rt2x00dev, sta->addr, wcid);
1405         rt2800_config_wcid_attr_bssidx(rt2x00dev, wcid,
1406                                        rt2x00lib_get_bssidx(rt2x00dev, vif));
1407         return 0;
1408 }
1409 EXPORT_SYMBOL_GPL(rt2800_sta_add);
1410
1411 int rt2800_sta_remove(struct rt2x00_dev *rt2x00dev, int wcid)
1412 {
1413         /*
1414          * Remove WCID entry, no need to clean the attributes as they will
1415          * get renewed when the WCID is reused.
1416          */
1417         rt2800_config_wcid(rt2x00dev, NULL, wcid);
1418
1419         return 0;
1420 }
1421 EXPORT_SYMBOL_GPL(rt2800_sta_remove);
1422
1423 void rt2800_config_filter(struct rt2x00_dev *rt2x00dev,
1424                           const unsigned int filter_flags)
1425 {
1426         u32 reg;
1427
1428         /*
1429          * Start configuration steps.
1430          * Note that the version error will always be dropped
1431          * and broadcast frames will always be accepted since
1432          * there is no filter for it at this time.
1433          */
1434         rt2800_register_read(rt2x00dev, RX_FILTER_CFG, &reg);
1435         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CRC_ERROR,
1436                            !(filter_flags & FIF_FCSFAIL));
1437         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PHY_ERROR,
1438                            !(filter_flags & FIF_PLCPFAIL));
1439         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_TO_ME,
1440                            !(filter_flags & FIF_PROMISC_IN_BSS));
1441         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_MY_BSSD, 0);
1442         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_VER_ERROR, 1);
1443         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_MULTICAST,
1444                            !(filter_flags & FIF_ALLMULTI));
1445         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BROADCAST, 0);
1446         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_DUPLICATE, 1);
1447         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END_ACK,
1448                            !(filter_flags & FIF_CONTROL));
1449         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END,
1450                            !(filter_flags & FIF_CONTROL));
1451         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_ACK,
1452                            !(filter_flags & FIF_CONTROL));
1453         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CTS,
1454                            !(filter_flags & FIF_CONTROL));
1455         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_RTS,
1456                            !(filter_flags & FIF_CONTROL));
1457         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PSPOLL,
1458                            !(filter_flags & FIF_PSPOLL));
1459         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BA, 0);
1460         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BAR,
1461                            !(filter_flags & FIF_CONTROL));
1462         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CNTL,
1463                            !(filter_flags & FIF_CONTROL));
1464         rt2800_register_write(rt2x00dev, RX_FILTER_CFG, reg);
1465 }
1466 EXPORT_SYMBOL_GPL(rt2800_config_filter);
1467
1468 void rt2800_config_intf(struct rt2x00_dev *rt2x00dev, struct rt2x00_intf *intf,
1469                         struct rt2x00intf_conf *conf, const unsigned int flags)
1470 {
1471         u32 reg;
1472         bool update_bssid = false;
1473
1474         if (flags & CONFIG_UPDATE_TYPE) {
1475                 /*
1476                  * Enable synchronisation.
1477                  */
1478                 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
1479                 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, conf->sync);
1480                 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1481
1482                 if (conf->sync == TSF_SYNC_AP_NONE) {
1483                         /*
1484                          * Tune beacon queue transmit parameters for AP mode
1485                          */
1486                         rt2800_register_read(rt2x00dev, TBTT_SYNC_CFG, &reg);
1487                         rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_CWMIN, 0);
1488                         rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_AIFSN, 1);
1489                         rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_EXP_WIN, 32);
1490                         rt2x00_set_field32(&reg, TBTT_SYNC_CFG_TBTT_ADJUST, 0);
1491                         rt2800_register_write(rt2x00dev, TBTT_SYNC_CFG, reg);
1492                 } else {
1493                         rt2800_register_read(rt2x00dev, TBTT_SYNC_CFG, &reg);
1494                         rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_CWMIN, 4);
1495                         rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_AIFSN, 2);
1496                         rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_EXP_WIN, 32);
1497                         rt2x00_set_field32(&reg, TBTT_SYNC_CFG_TBTT_ADJUST, 16);
1498                         rt2800_register_write(rt2x00dev, TBTT_SYNC_CFG, reg);
1499                 }
1500         }
1501
1502         if (flags & CONFIG_UPDATE_MAC) {
1503                 if (flags & CONFIG_UPDATE_TYPE &&
1504                     conf->sync == TSF_SYNC_AP_NONE) {
1505                         /*
1506                          * The BSSID register has to be set to our own mac
1507                          * address in AP mode.
1508                          */
1509                         memcpy(conf->bssid, conf->mac, sizeof(conf->mac));
1510                         update_bssid = true;
1511                 }
1512
1513                 if (!is_zero_ether_addr((const u8 *)conf->mac)) {
1514                         reg = le32_to_cpu(conf->mac[1]);
1515                         rt2x00_set_field32(&reg, MAC_ADDR_DW1_UNICAST_TO_ME_MASK, 0xff);
1516                         conf->mac[1] = cpu_to_le32(reg);
1517                 }
1518
1519                 rt2800_register_multiwrite(rt2x00dev, MAC_ADDR_DW0,
1520                                               conf->mac, sizeof(conf->mac));
1521         }
1522
1523         if ((flags & CONFIG_UPDATE_BSSID) || update_bssid) {
1524                 if (!is_zero_ether_addr((const u8 *)conf->bssid)) {
1525                         reg = le32_to_cpu(conf->bssid[1]);
1526                         rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_ID_MASK, 3);
1527                         rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_BCN_NUM, 7);
1528                         conf->bssid[1] = cpu_to_le32(reg);
1529                 }
1530
1531                 rt2800_register_multiwrite(rt2x00dev, MAC_BSSID_DW0,
1532                                               conf->bssid, sizeof(conf->bssid));
1533         }
1534 }
1535 EXPORT_SYMBOL_GPL(rt2800_config_intf);
1536
1537 static void rt2800_config_ht_opmode(struct rt2x00_dev *rt2x00dev,
1538                                     struct rt2x00lib_erp *erp)
1539 {
1540         bool any_sta_nongf = !!(erp->ht_opmode &
1541                                 IEEE80211_HT_OP_MODE_NON_GF_STA_PRSNT);
1542         u8 protection = erp->ht_opmode & IEEE80211_HT_OP_MODE_PROTECTION;
1543         u8 mm20_mode, mm40_mode, gf20_mode, gf40_mode;
1544         u16 mm20_rate, mm40_rate, gf20_rate, gf40_rate;
1545         u32 reg;
1546
1547         /* default protection rate for HT20: OFDM 24M */
1548         mm20_rate = gf20_rate = 0x4004;
1549
1550         /* default protection rate for HT40: duplicate OFDM 24M */
1551         mm40_rate = gf40_rate = 0x4084;
1552
1553         switch (protection) {
1554         case IEEE80211_HT_OP_MODE_PROTECTION_NONE:
1555                 /*
1556                  * All STAs in this BSS are HT20/40 but there might be
1557                  * STAs not supporting greenfield mode.
1558                  * => Disable protection for HT transmissions.
1559                  */
1560                 mm20_mode = mm40_mode = gf20_mode = gf40_mode = 0;
1561
1562                 break;
1563         case IEEE80211_HT_OP_MODE_PROTECTION_20MHZ:
1564                 /*
1565                  * All STAs in this BSS are HT20 or HT20/40 but there
1566                  * might be STAs not supporting greenfield mode.
1567                  * => Protect all HT40 transmissions.
1568                  */
1569                 mm20_mode = gf20_mode = 0;
1570                 mm40_mode = gf40_mode = 2;
1571
1572                 break;
1573         case IEEE80211_HT_OP_MODE_PROTECTION_NONMEMBER:
1574                 /*
1575                  * Nonmember protection:
1576                  * According to 802.11n we _should_ protect all
1577                  * HT transmissions (but we don't have to).
1578                  *
1579                  * But if cts_protection is enabled we _shall_ protect
1580                  * all HT transmissions using a CCK rate.
1581                  *
1582                  * And if any station is non GF we _shall_ protect
1583                  * GF transmissions.
1584                  *
1585                  * We decide to protect everything
1586                  * -> fall through to mixed mode.
1587                  */
1588         case IEEE80211_HT_OP_MODE_PROTECTION_NONHT_MIXED:
1589                 /*
1590                  * Legacy STAs are present
1591                  * => Protect all HT transmissions.
1592                  */
1593                 mm20_mode = mm40_mode = gf20_mode = gf40_mode = 2;
1594
1595                 /*
1596                  * If erp protection is needed we have to protect HT
1597                  * transmissions with CCK 11M long preamble.
1598                  */
1599                 if (erp->cts_protection) {
1600                         /* don't duplicate RTS/CTS in CCK mode */
1601                         mm20_rate = mm40_rate = 0x0003;
1602                         gf20_rate = gf40_rate = 0x0003;
1603                 }
1604                 break;
1605         }
1606
1607         /* check for STAs not supporting greenfield mode */
1608         if (any_sta_nongf)
1609                 gf20_mode = gf40_mode = 2;
1610
1611         /* Update HT protection config */
1612         rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
1613         rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, mm20_rate);
1614         rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, mm20_mode);
1615         rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
1616
1617         rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
1618         rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, mm40_rate);
1619         rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL, mm40_mode);
1620         rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
1621
1622         rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
1623         rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, gf20_rate);
1624         rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, gf20_mode);
1625         rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
1626
1627         rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
1628         rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, gf40_rate);
1629         rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, gf40_mode);
1630         rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
1631 }
1632
1633 void rt2800_config_erp(struct rt2x00_dev *rt2x00dev, struct rt2x00lib_erp *erp,
1634                        u32 changed)
1635 {
1636         u32 reg;
1637
1638         if (changed & BSS_CHANGED_ERP_PREAMBLE) {
1639                 rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
1640                 rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY,
1641                                    !!erp->short_preamble);
1642                 rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE,
1643                                    !!erp->short_preamble);
1644                 rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
1645         }
1646
1647         if (changed & BSS_CHANGED_ERP_CTS_PROT) {
1648                 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
1649                 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL,
1650                                    erp->cts_protection ? 2 : 0);
1651                 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
1652         }
1653
1654         if (changed & BSS_CHANGED_BASIC_RATES) {
1655                 rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE,
1656                                          erp->basic_rates);
1657                 rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
1658         }
1659
1660         if (changed & BSS_CHANGED_ERP_SLOT) {
1661                 rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
1662                 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME,
1663                                    erp->slot_time);
1664                 rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
1665
1666                 rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
1667                 rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, erp->eifs);
1668                 rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
1669         }
1670
1671         if (changed & BSS_CHANGED_BEACON_INT) {
1672                 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
1673                 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL,
1674                                    erp->beacon_int * 16);
1675                 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1676         }
1677
1678         if (changed & BSS_CHANGED_HT)
1679                 rt2800_config_ht_opmode(rt2x00dev, erp);
1680 }
1681 EXPORT_SYMBOL_GPL(rt2800_config_erp);
1682
1683 static void rt2800_config_3572bt_ant(struct rt2x00_dev *rt2x00dev)
1684 {
1685         u32 reg;
1686         u16 eeprom;
1687         u8 led_ctrl, led_g_mode, led_r_mode;
1688
1689         rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg);
1690         if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ) {
1691                 rt2x00_set_field32(&reg, GPIO_SWITCH_0, 1);
1692                 rt2x00_set_field32(&reg, GPIO_SWITCH_1, 1);
1693         } else {
1694                 rt2x00_set_field32(&reg, GPIO_SWITCH_0, 0);
1695                 rt2x00_set_field32(&reg, GPIO_SWITCH_1, 0);
1696         }
1697         rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
1698
1699         rt2800_register_read(rt2x00dev, LED_CFG, &reg);
1700         led_g_mode = rt2x00_get_field32(reg, LED_CFG_LED_POLAR) ? 3 : 0;
1701         led_r_mode = rt2x00_get_field32(reg, LED_CFG_LED_POLAR) ? 0 : 3;
1702         if (led_g_mode != rt2x00_get_field32(reg, LED_CFG_G_LED_MODE) ||
1703             led_r_mode != rt2x00_get_field32(reg, LED_CFG_R_LED_MODE)) {
1704                 rt2800_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
1705                 led_ctrl = rt2x00_get_field16(eeprom, EEPROM_FREQ_LED_MODE);
1706                 if (led_ctrl == 0 || led_ctrl > 0x40) {
1707                         rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE, led_g_mode);
1708                         rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE, led_r_mode);
1709                         rt2800_register_write(rt2x00dev, LED_CFG, reg);
1710                 } else {
1711                         rt2800_mcu_request(rt2x00dev, MCU_BAND_SELECT, 0xff,
1712                                            (led_g_mode << 2) | led_r_mode, 1);
1713                 }
1714         }
1715 }
1716
1717 static void rt2800_set_ant_diversity(struct rt2x00_dev *rt2x00dev,
1718                                      enum antenna ant)
1719 {
1720         u32 reg;
1721         u8 eesk_pin = (ant == ANTENNA_A) ? 1 : 0;
1722         u8 gpio_bit3 = (ant == ANTENNA_A) ? 0 : 1;
1723
1724         if (rt2x00_is_pci(rt2x00dev)) {
1725                 rt2800_register_read(rt2x00dev, E2PROM_CSR, &reg);
1726                 rt2x00_set_field32(&reg, E2PROM_CSR_DATA_CLOCK, eesk_pin);
1727                 rt2800_register_write(rt2x00dev, E2PROM_CSR, reg);
1728         } else if (rt2x00_is_usb(rt2x00dev))
1729                 rt2800_mcu_request(rt2x00dev, MCU_ANT_SELECT, 0xff,
1730                                    eesk_pin, 0);
1731
1732         rt2800_register_read(rt2x00dev, GPIO_CTRL, &reg);
1733         rt2x00_set_field32(&reg, GPIO_CTRL_DIR3, 0);
1734         rt2x00_set_field32(&reg, GPIO_CTRL_VAL3, gpio_bit3);
1735         rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
1736 }
1737
1738 void rt2800_config_ant(struct rt2x00_dev *rt2x00dev, struct antenna_setup *ant)
1739 {
1740         u8 r1;
1741         u8 r3;
1742         u16 eeprom;
1743
1744         rt2800_bbp_read(rt2x00dev, 1, &r1);
1745         rt2800_bbp_read(rt2x00dev, 3, &r3);
1746
1747         if (rt2x00_rt(rt2x00dev, RT3572) &&
1748             test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags))
1749                 rt2800_config_3572bt_ant(rt2x00dev);
1750
1751         /*
1752          * Configure the TX antenna.
1753          */
1754         switch (ant->tx_chain_num) {
1755         case 1:
1756                 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0);
1757                 break;
1758         case 2:
1759                 if (rt2x00_rt(rt2x00dev, RT3572) &&
1760                     test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags))
1761                         rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 1);
1762                 else
1763                         rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 2);
1764                 break;
1765         case 3:
1766                 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 2);
1767                 break;
1768         }
1769
1770         /*
1771          * Configure the RX antenna.
1772          */
1773         switch (ant->rx_chain_num) {
1774         case 1:
1775                 if (rt2x00_rt(rt2x00dev, RT3070) ||
1776                     rt2x00_rt(rt2x00dev, RT3090) ||
1777                     rt2x00_rt(rt2x00dev, RT3352) ||
1778                     rt2x00_rt(rt2x00dev, RT3390)) {
1779                         rt2800_eeprom_read(rt2x00dev,
1780                                            EEPROM_NIC_CONF1, &eeprom);
1781                         if (rt2x00_get_field16(eeprom,
1782                                                 EEPROM_NIC_CONF1_ANT_DIVERSITY))
1783                                 rt2800_set_ant_diversity(rt2x00dev,
1784                                                 rt2x00dev->default_ant.rx);
1785                 }
1786                 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0);
1787                 break;
1788         case 2:
1789                 if (rt2x00_rt(rt2x00dev, RT3572) &&
1790                     test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags)) {
1791                         rt2x00_set_field8(&r3, BBP3_RX_ADC, 1);
1792                         rt2x00_set_field8(&r3, BBP3_RX_ANTENNA,
1793                                 rt2x00dev->curr_band == IEEE80211_BAND_5GHZ);
1794                         rt2800_set_ant_diversity(rt2x00dev, ANTENNA_B);
1795                 } else {
1796                         rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 1);
1797                 }
1798                 break;
1799         case 3:
1800                 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 2);
1801                 break;
1802         }
1803
1804         rt2800_bbp_write(rt2x00dev, 3, r3);
1805         rt2800_bbp_write(rt2x00dev, 1, r1);
1806
1807         if (rt2x00_rt(rt2x00dev, RT3593)) {
1808                 if (ant->rx_chain_num == 1)
1809                         rt2800_bbp_write(rt2x00dev, 86, 0x00);
1810                 else
1811                         rt2800_bbp_write(rt2x00dev, 86, 0x46);
1812         }
1813 }
1814 EXPORT_SYMBOL_GPL(rt2800_config_ant);
1815
1816 static void rt2800_config_lna_gain(struct rt2x00_dev *rt2x00dev,
1817                                    struct rt2x00lib_conf *libconf)
1818 {
1819         u16 eeprom;
1820         short lna_gain;
1821
1822         if (libconf->rf.channel <= 14) {
1823                 rt2800_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
1824                 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_BG);
1825         } else if (libconf->rf.channel <= 64) {
1826                 rt2800_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
1827                 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_A0);
1828         } else if (libconf->rf.channel <= 128) {
1829                 if (rt2x00_rt(rt2x00dev, RT3593)) {
1830                         rt2800_eeprom_read(rt2x00dev, EEPROM_EXT_LNA2, &eeprom);
1831                         lna_gain = rt2x00_get_field16(eeprom,
1832                                                       EEPROM_EXT_LNA2_A1);
1833                 } else {
1834                         rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom);
1835                         lna_gain = rt2x00_get_field16(eeprom,
1836                                                       EEPROM_RSSI_BG2_LNA_A1);
1837                 }
1838         } else {
1839                 if (rt2x00_rt(rt2x00dev, RT3593)) {
1840                         rt2800_eeprom_read(rt2x00dev, EEPROM_EXT_LNA2, &eeprom);
1841                         lna_gain = rt2x00_get_field16(eeprom,
1842                                                       EEPROM_EXT_LNA2_A2);
1843                 } else {
1844                         rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom);
1845                         lna_gain = rt2x00_get_field16(eeprom,
1846                                                       EEPROM_RSSI_A2_LNA_A2);
1847                 }
1848         }
1849
1850         rt2x00dev->lna_gain = lna_gain;
1851 }
1852
1853 static void rt2800_config_channel_rf2xxx(struct rt2x00_dev *rt2x00dev,
1854                                          struct ieee80211_conf *conf,
1855                                          struct rf_channel *rf,
1856                                          struct channel_info *info)
1857 {
1858         rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
1859
1860         if (rt2x00dev->default_ant.tx_chain_num == 1)
1861                 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_TX1, 1);
1862
1863         if (rt2x00dev->default_ant.rx_chain_num == 1) {
1864                 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX1, 1);
1865                 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
1866         } else if (rt2x00dev->default_ant.rx_chain_num == 2)
1867                 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
1868
1869         if (rf->channel > 14) {
1870                 /*
1871                  * When TX power is below 0, we should increase it by 7 to
1872                  * make it a positive value (Minimum value is -7).
1873                  * However this means that values between 0 and 7 have
1874                  * double meaning, and we should set a 7DBm boost flag.
1875                  */
1876                 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A_7DBM_BOOST,
1877                                    (info->default_power1 >= 0));
1878
1879                 if (info->default_power1 < 0)
1880                         info->default_power1 += 7;
1881
1882                 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A, info->default_power1);
1883
1884                 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A_7DBM_BOOST,
1885                                    (info->default_power2 >= 0));
1886
1887                 if (info->default_power2 < 0)
1888                         info->default_power2 += 7;
1889
1890                 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A, info->default_power2);
1891         } else {
1892                 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_G, info->default_power1);
1893                 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_G, info->default_power2);
1894         }
1895
1896         rt2x00_set_field32(&rf->rf4, RF4_HT40, conf_is_ht40(conf));
1897
1898         rt2800_rf_write(rt2x00dev, 1, rf->rf1);
1899         rt2800_rf_write(rt2x00dev, 2, rf->rf2);
1900         rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
1901         rt2800_rf_write(rt2x00dev, 4, rf->rf4);
1902
1903         udelay(200);
1904
1905         rt2800_rf_write(rt2x00dev, 1, rf->rf1);
1906         rt2800_rf_write(rt2x00dev, 2, rf->rf2);
1907         rt2800_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
1908         rt2800_rf_write(rt2x00dev, 4, rf->rf4);
1909
1910         udelay(200);
1911
1912         rt2800_rf_write(rt2x00dev, 1, rf->rf1);
1913         rt2800_rf_write(rt2x00dev, 2, rf->rf2);
1914         rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
1915         rt2800_rf_write(rt2x00dev, 4, rf->rf4);
1916 }
1917
1918 static void rt2800_config_channel_rf3xxx(struct rt2x00_dev *rt2x00dev,
1919                                          struct ieee80211_conf *conf,
1920                                          struct rf_channel *rf,
1921                                          struct channel_info *info)
1922 {
1923         struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
1924         u8 rfcsr, calib_tx, calib_rx;
1925
1926         rt2800_rfcsr_write(rt2x00dev, 2, rf->rf1);
1927
1928         rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr);
1929         rt2x00_set_field8(&rfcsr, RFCSR3_K, rf->rf3);
1930         rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
1931
1932         rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
1933         rt2x00_set_field8(&rfcsr, RFCSR6_R1, rf->rf2);
1934         rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
1935
1936         rt2800_rfcsr_read(rt2x00dev, 12, &rfcsr);
1937         rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER, info->default_power1);
1938         rt2800_rfcsr_write(rt2x00dev, 12, rfcsr);
1939
1940         rt2800_rfcsr_read(rt2x00dev, 13, &rfcsr);
1941         rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER, info->default_power2);
1942         rt2800_rfcsr_write(rt2x00dev, 13, rfcsr);
1943
1944         rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
1945         rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
1946         rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD,
1947                           rt2x00dev->default_ant.rx_chain_num <= 1);
1948         rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD,
1949                           rt2x00dev->default_ant.rx_chain_num <= 2);
1950         rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
1951         rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD,
1952                           rt2x00dev->default_ant.tx_chain_num <= 1);
1953         rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD,
1954                           rt2x00dev->default_ant.tx_chain_num <= 2);
1955         rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
1956
1957         rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
1958         rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
1959         rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
1960         msleep(1);
1961         rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0);
1962         rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
1963
1964         rt2800_rfcsr_read(rt2x00dev, 23, &rfcsr);
1965         rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset);
1966         rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
1967
1968         if (rt2x00_rt(rt2x00dev, RT3390)) {
1969                 calib_tx = conf_is_ht40(conf) ? 0x68 : 0x4f;
1970                 calib_rx = conf_is_ht40(conf) ? 0x6f : 0x4f;
1971         } else {
1972                 if (conf_is_ht40(conf)) {
1973                         calib_tx = drv_data->calibration_bw40;
1974                         calib_rx = drv_data->calibration_bw40;
1975                 } else {
1976                         calib_tx = drv_data->calibration_bw20;
1977                         calib_rx = drv_data->calibration_bw20;
1978                 }
1979         }
1980
1981         rt2800_rfcsr_read(rt2x00dev, 24, &rfcsr);
1982         rt2x00_set_field8(&rfcsr, RFCSR24_TX_CALIB, calib_tx);
1983         rt2800_rfcsr_write(rt2x00dev, 24, rfcsr);
1984
1985         rt2800_rfcsr_read(rt2x00dev, 31, &rfcsr);
1986         rt2x00_set_field8(&rfcsr, RFCSR31_RX_CALIB, calib_rx);
1987         rt2800_rfcsr_write(rt2x00dev, 31, rfcsr);
1988
1989         rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
1990         rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
1991         rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
1992
1993         rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
1994         rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
1995         rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
1996         msleep(1);
1997         rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0);
1998         rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
1999 }
2000
2001 static void rt2800_config_channel_rf3052(struct rt2x00_dev *rt2x00dev,
2002                                          struct ieee80211_conf *conf,
2003                                          struct rf_channel *rf,
2004                                          struct channel_info *info)
2005 {
2006         struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
2007         u8 rfcsr;
2008         u32 reg;
2009
2010         if (rf->channel <= 14) {
2011                 rt2800_bbp_write(rt2x00dev, 25, drv_data->bbp25);
2012                 rt2800_bbp_write(rt2x00dev, 26, drv_data->bbp26);
2013         } else {
2014                 rt2800_bbp_write(rt2x00dev, 25, 0x09);
2015                 rt2800_bbp_write(rt2x00dev, 26, 0xff);
2016         }
2017
2018         rt2800_rfcsr_write(rt2x00dev, 2, rf->rf1);
2019         rt2800_rfcsr_write(rt2x00dev, 3, rf->rf3);
2020
2021         rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
2022         rt2x00_set_field8(&rfcsr, RFCSR6_R1, rf->rf2);
2023         if (rf->channel <= 14)
2024                 rt2x00_set_field8(&rfcsr, RFCSR6_TXDIV, 2);
2025         else
2026                 rt2x00_set_field8(&rfcsr, RFCSR6_TXDIV, 1);
2027         rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
2028
2029         rt2800_rfcsr_read(rt2x00dev, 5, &rfcsr);
2030         if (rf->channel <= 14)
2031                 rt2x00_set_field8(&rfcsr, RFCSR5_R1, 1);
2032         else
2033                 rt2x00_set_field8(&rfcsr, RFCSR5_R1, 2);
2034         rt2800_rfcsr_write(rt2x00dev, 5, rfcsr);
2035
2036         rt2800_rfcsr_read(rt2x00dev, 12, &rfcsr);
2037         if (rf->channel <= 14) {
2038                 rt2x00_set_field8(&rfcsr, RFCSR12_DR0, 3);
2039                 rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER,
2040                                   info->default_power1);
2041         } else {
2042                 rt2x00_set_field8(&rfcsr, RFCSR12_DR0, 7);
2043                 rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER,
2044                                 (info->default_power1 & 0x3) |
2045                                 ((info->default_power1 & 0xC) << 1));
2046         }
2047         rt2800_rfcsr_write(rt2x00dev, 12, rfcsr);
2048
2049         rt2800_rfcsr_read(rt2x00dev, 13, &rfcsr);
2050         if (rf->channel <= 14) {
2051                 rt2x00_set_field8(&rfcsr, RFCSR13_DR0, 3);
2052                 rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER,
2053                                   info->default_power2);
2054         } else {
2055                 rt2x00_set_field8(&rfcsr, RFCSR13_DR0, 7);
2056                 rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER,
2057                                 (info->default_power2 & 0x3) |
2058                                 ((info->default_power2 & 0xC) << 1));
2059         }
2060         rt2800_rfcsr_write(rt2x00dev, 13, rfcsr);
2061
2062         rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
2063         rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
2064         rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
2065         rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 0);
2066         rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 0);
2067         rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0);
2068         rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0);
2069         if (test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags)) {
2070                 if (rf->channel <= 14) {
2071                         rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
2072                         rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
2073                 }
2074                 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1);
2075                 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1);
2076         } else {
2077                 switch (rt2x00dev->default_ant.tx_chain_num) {
2078                 case 1:
2079                         rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
2080                 case 2:
2081                         rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1);
2082                         break;
2083                 }
2084
2085                 switch (rt2x00dev->default_ant.rx_chain_num) {
2086                 case 1:
2087                         rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
2088                 case 2:
2089                         rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1);
2090                         break;
2091                 }
2092         }
2093         rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
2094
2095         rt2800_rfcsr_read(rt2x00dev, 23, &rfcsr);
2096         rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset);
2097         rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
2098
2099         if (conf_is_ht40(conf)) {
2100                 rt2800_rfcsr_write(rt2x00dev, 24, drv_data->calibration_bw40);
2101                 rt2800_rfcsr_write(rt2x00dev, 31, drv_data->calibration_bw40);
2102         } else {
2103                 rt2800_rfcsr_write(rt2x00dev, 24, drv_data->calibration_bw20);
2104                 rt2800_rfcsr_write(rt2x00dev, 31, drv_data->calibration_bw20);
2105         }
2106
2107         if (rf->channel <= 14) {
2108                 rt2800_rfcsr_write(rt2x00dev, 7, 0xd8);
2109                 rt2800_rfcsr_write(rt2x00dev, 9, 0xc3);
2110                 rt2800_rfcsr_write(rt2x00dev, 10, 0xf1);
2111                 rt2800_rfcsr_write(rt2x00dev, 11, 0xb9);
2112                 rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
2113                 rfcsr = 0x4c;
2114                 rt2x00_set_field8(&rfcsr, RFCSR16_TXMIXER_GAIN,
2115                                   drv_data->txmixer_gain_24g);
2116                 rt2800_rfcsr_write(rt2x00dev, 16, rfcsr);
2117                 rt2800_rfcsr_write(rt2x00dev, 17, 0x23);
2118                 rt2800_rfcsr_write(rt2x00dev, 19, 0x93);
2119                 rt2800_rfcsr_write(rt2x00dev, 20, 0xb3);
2120                 rt2800_rfcsr_write(rt2x00dev, 25, 0x15);
2121                 rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
2122                 rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
2123                 rt2800_rfcsr_write(rt2x00dev, 29, 0x9b);
2124         } else {
2125                 rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
2126                 rt2x00_set_field8(&rfcsr, RFCSR7_BIT2, 1);
2127                 rt2x00_set_field8(&rfcsr, RFCSR7_BIT3, 0);
2128                 rt2x00_set_field8(&rfcsr, RFCSR7_BIT4, 1);
2129                 rt2x00_set_field8(&rfcsr, RFCSR7_BITS67, 0);
2130                 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
2131                 rt2800_rfcsr_write(rt2x00dev, 9, 0xc0);
2132                 rt2800_rfcsr_write(rt2x00dev, 10, 0xf1);
2133                 rt2800_rfcsr_write(rt2x00dev, 11, 0x00);
2134                 rt2800_rfcsr_write(rt2x00dev, 15, 0x43);
2135                 rfcsr = 0x7a;
2136                 rt2x00_set_field8(&rfcsr, RFCSR16_TXMIXER_GAIN,
2137                                   drv_data->txmixer_gain_5g);
2138                 rt2800_rfcsr_write(rt2x00dev, 16, rfcsr);
2139                 rt2800_rfcsr_write(rt2x00dev, 17, 0x23);
2140                 if (rf->channel <= 64) {
2141                         rt2800_rfcsr_write(rt2x00dev, 19, 0xb7);
2142                         rt2800_rfcsr_write(rt2x00dev, 20, 0xf6);
2143                         rt2800_rfcsr_write(rt2x00dev, 25, 0x3d);
2144                 } else if (rf->channel <= 128) {
2145                         rt2800_rfcsr_write(rt2x00dev, 19, 0x74);
2146                         rt2800_rfcsr_write(rt2x00dev, 20, 0xf4);
2147                         rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
2148                 } else {
2149                         rt2800_rfcsr_write(rt2x00dev, 19, 0x72);
2150                         rt2800_rfcsr_write(rt2x00dev, 20, 0xf3);
2151                         rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
2152                 }
2153                 rt2800_rfcsr_write(rt2x00dev, 26, 0x87);
2154                 rt2800_rfcsr_write(rt2x00dev, 27, 0x01);
2155                 rt2800_rfcsr_write(rt2x00dev, 29, 0x9f);
2156         }
2157
2158         rt2800_register_read(rt2x00dev, GPIO_CTRL, &reg);
2159         rt2x00_set_field32(&reg, GPIO_CTRL_DIR7, 0);
2160         if (rf->channel <= 14)
2161                 rt2x00_set_field32(&reg, GPIO_CTRL_VAL7, 1);
2162         else
2163                 rt2x00_set_field32(&reg, GPIO_CTRL_VAL7, 0);
2164         rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
2165
2166         rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
2167         rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
2168         rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
2169 }
2170
2171 #define POWER_BOUND             0x27
2172 #define POWER_BOUND_5G          0x2b
2173 #define FREQ_OFFSET_BOUND       0x5f
2174
2175 static void rt2800_adjust_freq_offset(struct rt2x00_dev *rt2x00dev)
2176 {
2177         u8 rfcsr;
2178
2179         rt2800_rfcsr_read(rt2x00dev, 17, &rfcsr);
2180         if (rt2x00dev->freq_offset > FREQ_OFFSET_BOUND)
2181                 rt2x00_set_field8(&rfcsr, RFCSR17_CODE, FREQ_OFFSET_BOUND);
2182         else
2183                 rt2x00_set_field8(&rfcsr, RFCSR17_CODE, rt2x00dev->freq_offset);
2184         rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
2185 }
2186
2187 static void rt2800_config_channel_rf3290(struct rt2x00_dev *rt2x00dev,
2188                                          struct ieee80211_conf *conf,
2189                                          struct rf_channel *rf,
2190                                          struct channel_info *info)
2191 {
2192         u8 rfcsr;
2193
2194         rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
2195         rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3);
2196         rt2800_rfcsr_read(rt2x00dev, 11, &rfcsr);
2197         rt2x00_set_field8(&rfcsr, RFCSR11_R, rf->rf2);
2198         rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
2199
2200         rt2800_rfcsr_read(rt2x00dev, 49, &rfcsr);
2201         if (info->default_power1 > POWER_BOUND)
2202                 rt2x00_set_field8(&rfcsr, RFCSR49_TX, POWER_BOUND);
2203         else
2204                 rt2x00_set_field8(&rfcsr, RFCSR49_TX, info->default_power1);
2205         rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);
2206
2207         rt2800_adjust_freq_offset(rt2x00dev);
2208
2209         if (rf->channel <= 14) {
2210                 if (rf->channel == 6)
2211                         rt2800_bbp_write(rt2x00dev, 68, 0x0c);
2212                 else
2213                         rt2800_bbp_write(rt2x00dev, 68, 0x0b);
2214
2215                 if (rf->channel >= 1 && rf->channel <= 6)
2216                         rt2800_bbp_write(rt2x00dev, 59, 0x0f);
2217                 else if (rf->channel >= 7 && rf->channel <= 11)
2218                         rt2800_bbp_write(rt2x00dev, 59, 0x0e);
2219                 else if (rf->channel >= 12 && rf->channel <= 14)
2220                         rt2800_bbp_write(rt2x00dev, 59, 0x0d);
2221         }
2222 }
2223
2224 static void rt2800_config_channel_rf3322(struct rt2x00_dev *rt2x00dev,
2225                                          struct ieee80211_conf *conf,
2226                                          struct rf_channel *rf,
2227                                          struct channel_info *info)
2228 {
2229         u8 rfcsr;
2230
2231         rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
2232         rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3);
2233
2234         rt2800_rfcsr_write(rt2x00dev, 11, 0x42);
2235         rt2800_rfcsr_write(rt2x00dev, 12, 0x1c);
2236         rt2800_rfcsr_write(rt2x00dev, 13, 0x00);
2237
2238         if (info->default_power1 > POWER_BOUND)
2239                 rt2800_rfcsr_write(rt2x00dev, 47, POWER_BOUND);
2240         else
2241                 rt2800_rfcsr_write(rt2x00dev, 47, info->default_power1);
2242
2243         if (info->default_power2 > POWER_BOUND)
2244                 rt2800_rfcsr_write(rt2x00dev, 48, POWER_BOUND);
2245         else
2246                 rt2800_rfcsr_write(rt2x00dev, 48, info->default_power2);
2247
2248         rt2800_adjust_freq_offset(rt2x00dev);
2249
2250         rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
2251         rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
2252         rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
2253
2254         if ( rt2x00dev->default_ant.tx_chain_num == 2 )
2255                 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
2256         else
2257                 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 0);
2258
2259         if ( rt2x00dev->default_ant.rx_chain_num == 2 )
2260                 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
2261         else
2262                 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 0);
2263
2264         rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0);
2265         rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0);
2266
2267         rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
2268
2269         rt2800_rfcsr_write(rt2x00dev, 31, 80);
2270 }
2271
2272 static void rt2800_config_channel_rf53xx(struct rt2x00_dev *rt2x00dev,
2273                                          struct ieee80211_conf *conf,
2274                                          struct rf_channel *rf,
2275                                          struct channel_info *info)
2276 {
2277         u8 rfcsr;
2278
2279         rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
2280         rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3);
2281         rt2800_rfcsr_read(rt2x00dev, 11, &rfcsr);
2282         rt2x00_set_field8(&rfcsr, RFCSR11_R, rf->rf2);
2283         rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
2284
2285         rt2800_rfcsr_read(rt2x00dev, 49, &rfcsr);
2286         if (info->default_power1 > POWER_BOUND)
2287                 rt2x00_set_field8(&rfcsr, RFCSR49_TX, POWER_BOUND);
2288         else
2289                 rt2x00_set_field8(&rfcsr, RFCSR49_TX, info->default_power1);
2290         rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);
2291
2292         if (rt2x00_rt(rt2x00dev, RT5392)) {
2293                 rt2800_rfcsr_read(rt2x00dev, 50, &rfcsr);
2294                 if (info->default_power1 > POWER_BOUND)
2295                         rt2x00_set_field8(&rfcsr, RFCSR50_TX, POWER_BOUND);
2296                 else
2297                         rt2x00_set_field8(&rfcsr, RFCSR50_TX,
2298                                           info->default_power2);
2299                 rt2800_rfcsr_write(rt2x00dev, 50, rfcsr);
2300         }
2301
2302         rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
2303         if (rt2x00_rt(rt2x00dev, RT5392)) {
2304                 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
2305                 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
2306         }
2307         rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
2308         rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1);
2309         rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
2310         rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
2311         rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
2312
2313         rt2800_adjust_freq_offset(rt2x00dev);
2314
2315         if (rf->channel <= 14) {
2316                 int idx = rf->channel-1;
2317
2318                 if (test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags)) {
2319                         if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) {
2320                                 /* r55/r59 value array of channel 1~14 */
2321                                 static const char r55_bt_rev[] = {0x83, 0x83,
2322                                         0x83, 0x73, 0x73, 0x63, 0x53, 0x53,
2323                                         0x53, 0x43, 0x43, 0x43, 0x43, 0x43};
2324                                 static const char r59_bt_rev[] = {0x0e, 0x0e,
2325                                         0x0e, 0x0e, 0x0e, 0x0b, 0x0a, 0x09,
2326                                         0x07, 0x07, 0x07, 0x07, 0x07, 0x07};
2327
2328                                 rt2800_rfcsr_write(rt2x00dev, 55,
2329                                                    r55_bt_rev[idx]);
2330                                 rt2800_rfcsr_write(rt2x00dev, 59,
2331                                                    r59_bt_rev[idx]);
2332                         } else {
2333                                 static const char r59_bt[] = {0x8b, 0x8b, 0x8b,
2334                                         0x8b, 0x8b, 0x8b, 0x8b, 0x8a, 0x89,
2335                                         0x88, 0x88, 0x86, 0x85, 0x84};
2336
2337                                 rt2800_rfcsr_write(rt2x00dev, 59, r59_bt[idx]);
2338                         }
2339                 } else {
2340                         if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) {
2341                                 static const char r55_nonbt_rev[] = {0x23, 0x23,
2342                                         0x23, 0x23, 0x13, 0x13, 0x03, 0x03,
2343                                         0x03, 0x03, 0x03, 0x03, 0x03, 0x03};
2344                                 static const char r59_nonbt_rev[] = {0x07, 0x07,
2345                                         0x07, 0x07, 0x07, 0x07, 0x07, 0x07,
2346                                         0x07, 0x07, 0x06, 0x05, 0x04, 0x04};
2347
2348                                 rt2800_rfcsr_write(rt2x00dev, 55,
2349                                                    r55_nonbt_rev[idx]);
2350                                 rt2800_rfcsr_write(rt2x00dev, 59,
2351                                                    r59_nonbt_rev[idx]);
2352                         } else if (rt2x00_rt(rt2x00dev, RT5390) ||
2353                                    rt2x00_rt(rt2x00dev, RT5392)) {
2354                                 static const char r59_non_bt[] = {0x8f, 0x8f,
2355                                         0x8f, 0x8f, 0x8f, 0x8f, 0x8f, 0x8d,
2356                                         0x8a, 0x88, 0x88, 0x87, 0x87, 0x86};
2357
2358                                 rt2800_rfcsr_write(rt2x00dev, 59,
2359                                                    r59_non_bt[idx]);
2360                         }
2361                 }
2362         }
2363 }
2364
2365 static void rt2800_config_channel_rf55xx(struct rt2x00_dev *rt2x00dev,
2366                                          struct ieee80211_conf *conf,
2367                                          struct rf_channel *rf,
2368                                          struct channel_info *info)
2369 {
2370         u8 rfcsr, ep_reg;
2371         u32 reg;
2372         int power_bound;
2373
2374         /* TODO */
2375         const bool is_11b = false;
2376         const bool is_type_ep = false;
2377
2378         rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
2379         rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL,
2380                            (rf->channel > 14 || conf_is_ht40(conf)) ? 5 : 0);
2381         rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
2382
2383         /* Order of values on rf_channel entry: N, K, mod, R */
2384         rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1 & 0xff);
2385
2386         rt2800_rfcsr_read(rt2x00dev,  9, &rfcsr);
2387         rt2x00_set_field8(&rfcsr, RFCSR9_K, rf->rf2 & 0xf);
2388         rt2x00_set_field8(&rfcsr, RFCSR9_N, (rf->rf1 & 0x100) >> 8);
2389         rt2x00_set_field8(&rfcsr, RFCSR9_MOD, ((rf->rf3 - 8) & 0x4) >> 2);
2390         rt2800_rfcsr_write(rt2x00dev, 9, rfcsr);
2391
2392         rt2800_rfcsr_read(rt2x00dev, 11, &rfcsr);
2393         rt2x00_set_field8(&rfcsr, RFCSR11_R, rf->rf4 - 1);
2394         rt2x00_set_field8(&rfcsr, RFCSR11_MOD, (rf->rf3 - 8) & 0x3);
2395         rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
2396
2397         if (rf->channel <= 14) {
2398                 rt2800_rfcsr_write(rt2x00dev, 10, 0x90);
2399                 /* FIXME: RF11 owerwrite ? */
2400                 rt2800_rfcsr_write(rt2x00dev, 11, 0x4A);
2401                 rt2800_rfcsr_write(rt2x00dev, 12, 0x52);
2402                 rt2800_rfcsr_write(rt2x00dev, 13, 0x42);
2403                 rt2800_rfcsr_write(rt2x00dev, 22, 0x40);
2404                 rt2800_rfcsr_write(rt2x00dev, 24, 0x4A);
2405                 rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
2406                 rt2800_rfcsr_write(rt2x00dev, 27, 0x42);
2407                 rt2800_rfcsr_write(rt2x00dev, 36, 0x80);
2408                 rt2800_rfcsr_write(rt2x00dev, 37, 0x08);
2409                 rt2800_rfcsr_write(rt2x00dev, 38, 0x89);
2410                 rt2800_rfcsr_write(rt2x00dev, 39, 0x1B);
2411                 rt2800_rfcsr_write(rt2x00dev, 40, 0x0D);
2412                 rt2800_rfcsr_write(rt2x00dev, 41, 0x9B);
2413                 rt2800_rfcsr_write(rt2x00dev, 42, 0xD5);
2414                 rt2800_rfcsr_write(rt2x00dev, 43, 0x72);
2415                 rt2800_rfcsr_write(rt2x00dev, 44, 0x0E);
2416                 rt2800_rfcsr_write(rt2x00dev, 45, 0xA2);
2417                 rt2800_rfcsr_write(rt2x00dev, 46, 0x6B);
2418                 rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
2419                 rt2800_rfcsr_write(rt2x00dev, 51, 0x3E);
2420                 rt2800_rfcsr_write(rt2x00dev, 52, 0x48);
2421                 rt2800_rfcsr_write(rt2x00dev, 54, 0x38);
2422                 rt2800_rfcsr_write(rt2x00dev, 56, 0xA1);
2423                 rt2800_rfcsr_write(rt2x00dev, 57, 0x00);
2424                 rt2800_rfcsr_write(rt2x00dev, 58, 0x39);
2425                 rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
2426                 rt2800_rfcsr_write(rt2x00dev, 61, 0x91);
2427                 rt2800_rfcsr_write(rt2x00dev, 62, 0x39);
2428
2429                 /* TODO RF27 <- tssi */
2430
2431                 rfcsr = rf->channel <= 10 ? 0x07 : 0x06;
2432                 rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
2433                 rt2800_rfcsr_write(rt2x00dev, 59, rfcsr);
2434
2435                 if (is_11b) {
2436                         /* CCK */
2437                         rt2800_rfcsr_write(rt2x00dev, 31, 0xF8);
2438                         rt2800_rfcsr_write(rt2x00dev, 32, 0xC0);
2439                         if (is_type_ep)
2440                                 rt2800_rfcsr_write(rt2x00dev, 55, 0x06);
2441                         else
2442                                 rt2800_rfcsr_write(rt2x00dev, 55, 0x47);
2443                 } else {
2444                         /* OFDM */
2445                         if (is_type_ep)
2446                                 rt2800_rfcsr_write(rt2x00dev, 55, 0x03);
2447                         else
2448                                 rt2800_rfcsr_write(rt2x00dev, 55, 0x43);
2449                 }
2450
2451                 power_bound = POWER_BOUND;
2452                 ep_reg = 0x2;
2453         } else {
2454                 rt2800_rfcsr_write(rt2x00dev, 10, 0x97);
2455                 /* FIMXE: RF11 overwrite */
2456                 rt2800_rfcsr_write(rt2x00dev, 11, 0x40);
2457                 rt2800_rfcsr_write(rt2x00dev, 25, 0xBF);
2458                 rt2800_rfcsr_write(rt2x00dev, 27, 0x42);
2459                 rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
2460                 rt2800_rfcsr_write(rt2x00dev, 37, 0x04);
2461                 rt2800_rfcsr_write(rt2x00dev, 38, 0x85);
2462                 rt2800_rfcsr_write(rt2x00dev, 40, 0x42);
2463                 rt2800_rfcsr_write(rt2x00dev, 41, 0xBB);
2464                 rt2800_rfcsr_write(rt2x00dev, 42, 0xD7);
2465                 rt2800_rfcsr_write(rt2x00dev, 45, 0x41);
2466                 rt2800_rfcsr_write(rt2x00dev, 48, 0x00);
2467                 rt2800_rfcsr_write(rt2x00dev, 57, 0x77);
2468                 rt2800_rfcsr_write(rt2x00dev, 60, 0x05);
2469                 rt2800_rfcsr_write(rt2x00dev, 61, 0x01);
2470
2471                 /* TODO RF27 <- tssi */
2472
2473                 if (rf->channel >= 36 && rf->channel <= 64) {
2474
2475                         rt2800_rfcsr_write(rt2x00dev, 12, 0x2E);
2476                         rt2800_rfcsr_write(rt2x00dev, 13, 0x22);
2477                         rt2800_rfcsr_write(rt2x00dev, 22, 0x60);
2478                         rt2800_rfcsr_write(rt2x00dev, 23, 0x7F);
2479                         if (rf->channel <= 50)
2480                                 rt2800_rfcsr_write(rt2x00dev, 24, 0x09);
2481                         else if (rf->channel >= 52)
2482                                 rt2800_rfcsr_write(rt2x00dev, 24, 0x07);
2483                         rt2800_rfcsr_write(rt2x00dev, 39, 0x1C);
2484                         rt2800_rfcsr_write(rt2x00dev, 43, 0x5B);
2485                         rt2800_rfcsr_write(rt2x00dev, 44, 0X40);
2486                         rt2800_rfcsr_write(rt2x00dev, 46, 0X00);
2487                         rt2800_rfcsr_write(rt2x00dev, 51, 0xFE);
2488                         rt2800_rfcsr_write(rt2x00dev, 52, 0x0C);
2489                         rt2800_rfcsr_write(rt2x00dev, 54, 0xF8);
2490                         if (rf->channel <= 50) {
2491                                 rt2800_rfcsr_write(rt2x00dev, 55, 0x06),
2492                                 rt2800_rfcsr_write(rt2x00dev, 56, 0xD3);
2493                         } else if (rf->channel >= 52) {
2494                                 rt2800_rfcsr_write(rt2x00dev, 55, 0x04);
2495                                 rt2800_rfcsr_write(rt2x00dev, 56, 0xBB);
2496                         }
2497
2498                         rt2800_rfcsr_write(rt2x00dev, 58, 0x15);
2499                         rt2800_rfcsr_write(rt2x00dev, 59, 0x7F);
2500                         rt2800_rfcsr_write(rt2x00dev, 62, 0x15);
2501
2502                 } else if (rf->channel >= 100 && rf->channel <= 165) {
2503
2504                         rt2800_rfcsr_write(rt2x00dev, 12, 0x0E);
2505                         rt2800_rfcsr_write(rt2x00dev, 13, 0x42);
2506                         rt2800_rfcsr_write(rt2x00dev, 22, 0x40);
2507                         if (rf->channel <= 153) {
2508                                 rt2800_rfcsr_write(rt2x00dev, 23, 0x3C);
2509                                 rt2800_rfcsr_write(rt2x00dev, 24, 0x06);
2510                         } else if (rf->channel >= 155) {
2511                                 rt2800_rfcsr_write(rt2x00dev, 23, 0x38);
2512                                 rt2800_rfcsr_write(rt2x00dev, 24, 0x05);
2513                         }
2514                         if (rf->channel <= 138) {
2515                                 rt2800_rfcsr_write(rt2x00dev, 39, 0x1A);
2516                                 rt2800_rfcsr_write(rt2x00dev, 43, 0x3B);
2517                                 rt2800_rfcsr_write(rt2x00dev, 44, 0x20);
2518                                 rt2800_rfcsr_write(rt2x00dev, 46, 0x18);
2519                         } else if (rf->channel >= 140) {
2520                                 rt2800_rfcsr_write(rt2x00dev, 39, 0x18);
2521                                 rt2800_rfcsr_write(rt2x00dev, 43, 0x1B);
2522                                 rt2800_rfcsr_write(rt2x00dev, 44, 0x10);
2523                                 rt2800_rfcsr_write(rt2x00dev, 46, 0X08);
2524                         }
2525                         if (rf->channel <= 124)
2526                                 rt2800_rfcsr_write(rt2x00dev, 51, 0xFC);
2527                         else if (rf->channel >= 126)
2528                                 rt2800_rfcsr_write(rt2x00dev, 51, 0xEC);
2529                         if (rf->channel <= 138)
2530                                 rt2800_rfcsr_write(rt2x00dev, 52, 0x06);
2531                         else if (rf->channel >= 140)
2532                                 rt2800_rfcsr_write(rt2x00dev, 52, 0x06);
2533                         rt2800_rfcsr_write(rt2x00dev, 54, 0xEB);
2534                         if (rf->channel <= 138)
2535                                 rt2800_rfcsr_write(rt2x00dev, 55, 0x01);
2536                         else if (rf->channel >= 140)
2537                                 rt2800_rfcsr_write(rt2x00dev, 55, 0x00);
2538                         if (rf->channel <= 128)
2539                                 rt2800_rfcsr_write(rt2x00dev, 56, 0xBB);
2540                         else if (rf->channel >= 130)
2541                                 rt2800_rfcsr_write(rt2x00dev, 56, 0xAB);
2542                         if (rf->channel <= 116)
2543                                 rt2800_rfcsr_write(rt2x00dev, 58, 0x1D);
2544                         else if (rf->channel >= 118)
2545                                 rt2800_rfcsr_write(rt2x00dev, 58, 0x15);
2546                         if (rf->channel <= 138)
2547                                 rt2800_rfcsr_write(rt2x00dev, 59, 0x3F);
2548                         else if (rf->channel >= 140)
2549                                 rt2800_rfcsr_write(rt2x00dev, 59, 0x7C);
2550                         if (rf->channel <= 116)
2551                                 rt2800_rfcsr_write(rt2x00dev, 62, 0x1D);
2552                         else if (rf->channel >= 118)
2553                                 rt2800_rfcsr_write(rt2x00dev, 62, 0x15);
2554                 }
2555
2556                 power_bound = POWER_BOUND_5G;
2557                 ep_reg = 0x3;
2558         }
2559
2560         rt2800_rfcsr_read(rt2x00dev, 49, &rfcsr);
2561         if (info->default_power1 > power_bound)
2562                 rt2x00_set_field8(&rfcsr, RFCSR49_TX, power_bound);
2563         else
2564                 rt2x00_set_field8(&rfcsr, RFCSR49_TX, info->default_power1);
2565         if (is_type_ep)
2566                 rt2x00_set_field8(&rfcsr, RFCSR49_EP, ep_reg);
2567         rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);
2568
2569         rt2800_rfcsr_read(rt2x00dev, 50, &rfcsr);
2570         if (info->default_power2 > power_bound)
2571                 rt2x00_set_field8(&rfcsr, RFCSR50_TX, power_bound);
2572         else
2573                 rt2x00_set_field8(&rfcsr, RFCSR50_TX, info->default_power2);
2574         if (is_type_ep)
2575                 rt2x00_set_field8(&rfcsr, RFCSR50_EP, ep_reg);
2576         rt2800_rfcsr_write(rt2x00dev, 50, rfcsr);
2577
2578         rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
2579         rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
2580         rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1);
2581
2582         rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD,
2583                           rt2x00dev->default_ant.tx_chain_num >= 1);
2584         rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD,
2585                           rt2x00dev->default_ant.tx_chain_num == 2);
2586         rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0);
2587
2588         rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD,
2589                           rt2x00dev->default_ant.rx_chain_num >= 1);
2590         rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD,
2591                           rt2x00dev->default_ant.rx_chain_num == 2);
2592         rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0);
2593
2594         rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
2595         rt2800_rfcsr_write(rt2x00dev, 6, 0xe4);
2596
2597         if (conf_is_ht40(conf))
2598                 rt2800_rfcsr_write(rt2x00dev, 30, 0x16);
2599         else
2600                 rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
2601
2602         if (!is_11b) {
2603                 rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
2604                 rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
2605         }
2606
2607         /* TODO proper frequency adjustment */
2608         rt2800_adjust_freq_offset(rt2x00dev);
2609
2610         /* TODO merge with others */
2611         rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr);
2612         rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1);
2613         rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
2614
2615         /* BBP settings */
2616         rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
2617         rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
2618         rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
2619
2620         rt2800_bbp_write(rt2x00dev, 79, (rf->channel <= 14) ? 0x1C : 0x18);
2621         rt2800_bbp_write(rt2x00dev, 80, (rf->channel <= 14) ? 0x0E : 0x08);
2622         rt2800_bbp_write(rt2x00dev, 81, (rf->channel <= 14) ? 0x3A : 0x38);
2623         rt2800_bbp_write(rt2x00dev, 82, (rf->channel <= 14) ? 0x62 : 0x92);
2624
2625         /* GLRT band configuration */
2626         rt2800_bbp_write(rt2x00dev, 195, 128);
2627         rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0xE0 : 0xF0);
2628         rt2800_bbp_write(rt2x00dev, 195, 129);
2629         rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x1F : 0x1E);
2630         rt2800_bbp_write(rt2x00dev, 195, 130);
2631         rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x38 : 0x28);
2632         rt2800_bbp_write(rt2x00dev, 195, 131);
2633         rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x32 : 0x20);
2634         rt2800_bbp_write(rt2x00dev, 195, 133);
2635         rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x28 : 0x7F);
2636         rt2800_bbp_write(rt2x00dev, 195, 124);
2637         rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x19 : 0x7F);
2638 }
2639
2640 static void rt2800_bbp_write_with_rx_chain(struct rt2x00_dev *rt2x00dev,
2641                                            const unsigned int word,
2642                                            const u8 value)
2643 {
2644         u8 chain, reg;
2645
2646         for (chain = 0; chain < rt2x00dev->default_ant.rx_chain_num; chain++) {
2647                 rt2800_bbp_read(rt2x00dev, 27, &reg);
2648                 rt2x00_set_field8(&reg,  BBP27_RX_CHAIN_SEL, chain);
2649                 rt2800_bbp_write(rt2x00dev, 27, reg);
2650
2651                 rt2800_bbp_write(rt2x00dev, word, value);
2652         }
2653 }
2654
2655 static void rt2800_iq_calibrate(struct rt2x00_dev *rt2x00dev, int channel)
2656 {
2657         u8 cal;
2658
2659         /* TX0 IQ Gain */
2660         rt2800_bbp_write(rt2x00dev, 158, 0x2c);
2661         if (channel <= 14)
2662                 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_IQ_GAIN_CAL_TX0_2G);
2663         else if (channel >= 36 && channel <= 64)
2664                 cal = rt2x00_eeprom_byte(rt2x00dev,
2665                                          EEPROM_IQ_GAIN_CAL_TX0_CH36_TO_CH64_5G);
2666         else if (channel >= 100 && channel <= 138)
2667                 cal = rt2x00_eeprom_byte(rt2x00dev,
2668                                          EEPROM_IQ_GAIN_CAL_TX0_CH100_TO_CH138_5G);
2669         else if (channel >= 140 && channel <= 165)
2670                 cal = rt2x00_eeprom_byte(rt2x00dev,
2671                                          EEPROM_IQ_GAIN_CAL_TX0_CH140_TO_CH165_5G);
2672         else
2673                 cal = 0;
2674         rt2800_bbp_write(rt2x00dev, 159, cal);
2675
2676         /* TX0 IQ Phase */
2677         rt2800_bbp_write(rt2x00dev, 158, 0x2d);
2678         if (channel <= 14)
2679                 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_IQ_PHASE_CAL_TX0_2G);
2680         else if (channel >= 36 && channel <= 64)
2681                 cal = rt2x00_eeprom_byte(rt2x00dev,
2682                                          EEPROM_IQ_PHASE_CAL_TX0_CH36_TO_CH64_5G);
2683         else if (channel >= 100 && channel <= 138)
2684                 cal = rt2x00_eeprom_byte(rt2x00dev,
2685                                          EEPROM_IQ_PHASE_CAL_TX0_CH100_TO_CH138_5G);
2686         else if (channel >= 140 && channel <= 165)
2687                 cal = rt2x00_eeprom_byte(rt2x00dev,
2688                                          EEPROM_IQ_PHASE_CAL_TX0_CH140_TO_CH165_5G);
2689         else
2690                 cal = 0;
2691         rt2800_bbp_write(rt2x00dev, 159, cal);
2692
2693         /* TX1 IQ Gain */
2694         rt2800_bbp_write(rt2x00dev, 158, 0x4a);
2695         if (channel <= 14)
2696                 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_IQ_GAIN_CAL_TX1_2G);
2697         else if (channel >= 36 && channel <= 64)
2698                 cal = rt2x00_eeprom_byte(rt2x00dev,
2699                                          EEPROM_IQ_GAIN_CAL_TX1_CH36_TO_CH64_5G);
2700         else if (channel >= 100 && channel <= 138)
2701                 cal = rt2x00_eeprom_byte(rt2x00dev,
2702                                          EEPROM_IQ_GAIN_CAL_TX1_CH100_TO_CH138_5G);
2703         else if (channel >= 140 && channel <= 165)
2704                 cal = rt2x00_eeprom_byte(rt2x00dev,
2705                                          EEPROM_IQ_GAIN_CAL_TX1_CH140_TO_CH165_5G);
2706         else
2707                 cal = 0;
2708         rt2800_bbp_write(rt2x00dev, 159, cal);
2709
2710         /* TX1 IQ Phase */
2711         rt2800_bbp_write(rt2x00dev, 158, 0x4b);
2712         if (channel <= 14)
2713                 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_IQ_PHASE_CAL_TX1_2G);
2714         else if (channel >= 36 && channel <= 64)
2715                 cal = rt2x00_eeprom_byte(rt2x00dev,
2716                                          EEPROM_IQ_PHASE_CAL_TX1_CH36_TO_CH64_5G);
2717         else if (channel >= 100 && channel <= 138)
2718                 cal = rt2x00_eeprom_byte(rt2x00dev,
2719                                          EEPROM_IQ_PHASE_CAL_TX1_CH100_TO_CH138_5G);
2720         else if (channel >= 140 && channel <= 165)
2721                 cal = rt2x00_eeprom_byte(rt2x00dev,
2722                                          EEPROM_IQ_PHASE_CAL_TX1_CH140_TO_CH165_5G);
2723         else
2724                 cal = 0;
2725         rt2800_bbp_write(rt2x00dev, 159, cal);
2726
2727         /* FIXME: possible RX0, RX1 callibration ? */
2728
2729         /* RF IQ compensation control */
2730         rt2800_bbp_write(rt2x00dev, 158, 0x04);
2731         cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_RF_IQ_COMPENSATION_CONTROL);
2732         rt2800_bbp_write(rt2x00dev, 159, cal != 0xff ? cal : 0);
2733
2734         /* RF IQ imbalance compensation control */
2735         rt2800_bbp_write(rt2x00dev, 158, 0x03);
2736         cal = rt2x00_eeprom_byte(rt2x00dev,
2737                                  EEPROM_RF_IQ_IMBALANCE_COMPENSATION_CONTROL);
2738         rt2800_bbp_write(rt2x00dev, 159, cal != 0xff ? cal : 0);
2739 }
2740
2741 static char rt2800_txpower_to_dev(struct rt2x00_dev *rt2x00dev,
2742                                   unsigned int channel,
2743                                   char txpower)
2744 {
2745         if (rt2x00_rt(rt2x00dev, RT3593))
2746                 txpower = rt2x00_get_field8(txpower, EEPROM_TXPOWER_ALC);
2747
2748         if (channel <= 14)
2749                 return clamp_t(char, txpower, MIN_G_TXPOWER, MAX_G_TXPOWER);
2750
2751         if (rt2x00_rt(rt2x00dev, RT3593))
2752                 return clamp_t(char, txpower, MIN_A_TXPOWER_3593,
2753                                MAX_A_TXPOWER_3593);
2754         else
2755                 return clamp_t(char, txpower, MIN_A_TXPOWER, MAX_A_TXPOWER);
2756 }
2757
2758 static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev,
2759                                   struct ieee80211_conf *conf,
2760                                   struct rf_channel *rf,
2761                                   struct channel_info *info)
2762 {
2763         u32 reg;
2764         unsigned int tx_pin;
2765         u8 bbp, rfcsr;
2766
2767         info->default_power1 = rt2800_txpower_to_dev(rt2x00dev, rf->channel,
2768                                                      info->default_power1);
2769         info->default_power2 = rt2800_txpower_to_dev(rt2x00dev, rf->channel,
2770                                                      info->default_power2);
2771
2772         switch (rt2x00dev->chip.rf) {
2773         case RF2020:
2774         case RF3020:
2775         case RF3021:
2776         case RF3022:
2777         case RF3320:
2778                 rt2800_config_channel_rf3xxx(rt2x00dev, conf, rf, info);
2779                 break;
2780         case RF3052:
2781                 rt2800_config_channel_rf3052(rt2x00dev, conf, rf, info);
2782                 break;
2783         case RF3290:
2784                 rt2800_config_channel_rf3290(rt2x00dev, conf, rf, info);
2785                 break;
2786         case RF3322:
2787                 rt2800_config_channel_rf3322(rt2x00dev, conf, rf, info);
2788                 break;
2789         case RF5360:
2790         case RF5370:
2791         case RF5372:
2792         case RF5390:
2793         case RF5392:
2794                 rt2800_config_channel_rf53xx(rt2x00dev, conf, rf, info);
2795                 break;
2796         case RF5592:
2797                 rt2800_config_channel_rf55xx(rt2x00dev, conf, rf, info);
2798                 break;
2799         default:
2800                 rt2800_config_channel_rf2xxx(rt2x00dev, conf, rf, info);
2801         }
2802
2803         if (rt2x00_rf(rt2x00dev, RF3290) ||
2804             rt2x00_rf(rt2x00dev, RF3322) ||
2805             rt2x00_rf(rt2x00dev, RF5360) ||
2806             rt2x00_rf(rt2x00dev, RF5370) ||
2807             rt2x00_rf(rt2x00dev, RF5372) ||
2808             rt2x00_rf(rt2x00dev, RF5390) ||
2809             rt2x00_rf(rt2x00dev, RF5392)) {
2810                 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
2811                 rt2x00_set_field8(&rfcsr, RFCSR30_TX_H20M, 0);
2812                 rt2x00_set_field8(&rfcsr, RFCSR30_RX_H20M, 0);
2813                 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
2814
2815                 rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr);
2816                 rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1);
2817                 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
2818         }
2819
2820         /*
2821          * Change BBP settings
2822          */
2823         if (rt2x00_rt(rt2x00dev, RT3352)) {
2824                 rt2800_bbp_write(rt2x00dev, 27, 0x0);
2825                 rt2800_bbp_write(rt2x00dev, 66, 0x26 + rt2x00dev->lna_gain);
2826                 rt2800_bbp_write(rt2x00dev, 27, 0x20);
2827                 rt2800_bbp_write(rt2x00dev, 66, 0x26 + rt2x00dev->lna_gain);
2828         } else {
2829                 rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
2830                 rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
2831                 rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
2832                 rt2800_bbp_write(rt2x00dev, 86, 0);
2833         }
2834
2835         if (rf->channel <= 14) {
2836                 if (!rt2x00_rt(rt2x00dev, RT5390) &&
2837                     !rt2x00_rt(rt2x00dev, RT5392)) {
2838                         if (test_bit(CAPABILITY_EXTERNAL_LNA_BG,
2839                                      &rt2x00dev->cap_flags)) {
2840                                 rt2800_bbp_write(rt2x00dev, 82, 0x62);
2841                                 rt2800_bbp_write(rt2x00dev, 75, 0x46);
2842                         } else {
2843                                 rt2800_bbp_write(rt2x00dev, 82, 0x84);
2844                                 rt2800_bbp_write(rt2x00dev, 75, 0x50);
2845                         }
2846                 }
2847         } else {
2848                 if (rt2x00_rt(rt2x00dev, RT3572))
2849                         rt2800_bbp_write(rt2x00dev, 82, 0x94);
2850                 else
2851                         rt2800_bbp_write(rt2x00dev, 82, 0xf2);
2852
2853                 if (test_bit(CAPABILITY_EXTERNAL_LNA_A, &rt2x00dev->cap_flags))
2854                         rt2800_bbp_write(rt2x00dev, 75, 0x46);
2855                 else
2856                         rt2800_bbp_write(rt2x00dev, 75, 0x50);
2857         }
2858
2859         rt2800_register_read(rt2x00dev, TX_BAND_CFG, &reg);
2860         rt2x00_set_field32(&reg, TX_BAND_CFG_HT40_MINUS, conf_is_ht40_minus(conf));
2861         rt2x00_set_field32(&reg, TX_BAND_CFG_A, rf->channel > 14);
2862         rt2x00_set_field32(&reg, TX_BAND_CFG_BG, rf->channel <= 14);
2863         rt2800_register_write(rt2x00dev, TX_BAND_CFG, reg);
2864
2865         if (rt2x00_rt(rt2x00dev, RT3572))
2866                 rt2800_rfcsr_write(rt2x00dev, 8, 0);
2867
2868         tx_pin = 0;
2869
2870         switch (rt2x00dev->default_ant.tx_chain_num) {
2871         case 3:
2872                 /* Turn on tertiary PAs */
2873                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A2_EN,
2874                                    rf->channel > 14);
2875                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G2_EN,
2876                                    rf->channel <= 14);
2877                 /* fall-through */
2878         case 2:
2879                 /* Turn on secondary PAs */
2880                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN,
2881                                    rf->channel > 14);
2882                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN,
2883                                    rf->channel <= 14);
2884                 /* fall-through */
2885         case 1:
2886                 /* Turn on primary PAs */
2887                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN,
2888                                    rf->channel > 14);
2889                 if (test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags))
2890                         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, 1);
2891                 else
2892                         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN,
2893                                            rf->channel <= 14);
2894                 break;
2895         }
2896
2897         switch (rt2x00dev->default_ant.rx_chain_num) {
2898         case 3:
2899                 /* Turn on tertiary LNAs */
2900                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A2_EN, 1);
2901                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G2_EN, 1);
2902                 /* fall-through */
2903         case 2:
2904                 /* Turn on secondary LNAs */
2905                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A1_EN, 1);
2906                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G1_EN, 1);
2907                 /* fall-through */
2908         case 1:
2909                 /* Turn on primary LNAs */
2910                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A0_EN, 1);
2911                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G0_EN, 1);
2912                 break;
2913         }
2914
2915         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFTR_EN, 1);
2916         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_TRSW_EN, 1);
2917
2918         rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
2919
2920         if (rt2x00_rt(rt2x00dev, RT3572))
2921                 rt2800_rfcsr_write(rt2x00dev, 8, 0x80);
2922
2923         if (rt2x00_rt(rt2x00dev, RT5592)) {
2924                 rt2800_bbp_write(rt2x00dev, 195, 141);
2925                 rt2800_bbp_write(rt2x00dev, 196, conf_is_ht40(conf) ? 0x10 : 0x1a);
2926
2927                 /* AGC init */
2928                 reg = (rf->channel <= 14 ? 0x1c : 0x24) + 2 * rt2x00dev->lna_gain;
2929                 rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, reg);
2930
2931                 rt2800_iq_calibrate(rt2x00dev, rf->channel);
2932         }
2933
2934         rt2800_bbp_read(rt2x00dev, 4, &bbp);
2935         rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * conf_is_ht40(conf));
2936         rt2800_bbp_write(rt2x00dev, 4, bbp);
2937
2938         rt2800_bbp_read(rt2x00dev, 3, &bbp);
2939         rt2x00_set_field8(&bbp, BBP3_HT40_MINUS, conf_is_ht40_minus(conf));
2940         rt2800_bbp_write(rt2x00dev, 3, bbp);
2941
2942         if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) {
2943                 if (conf_is_ht40(conf)) {
2944                         rt2800_bbp_write(rt2x00dev, 69, 0x1a);
2945                         rt2800_bbp_write(rt2x00dev, 70, 0x0a);
2946                         rt2800_bbp_write(rt2x00dev, 73, 0x16);
2947                 } else {
2948                         rt2800_bbp_write(rt2x00dev, 69, 0x16);
2949                         rt2800_bbp_write(rt2x00dev, 70, 0x08);
2950                         rt2800_bbp_write(rt2x00dev, 73, 0x11);
2951                 }
2952         }
2953
2954         msleep(1);
2955
2956         /*
2957          * Clear channel statistic counters
2958          */
2959         rt2800_register_read(rt2x00dev, CH_IDLE_STA, &reg);
2960         rt2800_register_read(rt2x00dev, CH_BUSY_STA, &reg);
2961         rt2800_register_read(rt2x00dev, CH_BUSY_STA_SEC, &reg);
2962
2963         /*
2964          * Clear update flag
2965          */
2966         if (rt2x00_rt(rt2x00dev, RT3352)) {
2967                 rt2800_bbp_read(rt2x00dev, 49, &bbp);
2968                 rt2x00_set_field8(&bbp, BBP49_UPDATE_FLAG, 0);
2969                 rt2800_bbp_write(rt2x00dev, 49, bbp);
2970         }
2971 }
2972
2973 static int rt2800_get_gain_calibration_delta(struct rt2x00_dev *rt2x00dev)
2974 {
2975         u8 tssi_bounds[9];
2976         u8 current_tssi;
2977         u16 eeprom;
2978         u8 step;
2979         int i;
2980
2981         /*
2982          * Read TSSI boundaries for temperature compensation from
2983          * the EEPROM.
2984          *
2985          * Array idx               0    1    2    3    4    5    6    7    8
2986          * Matching Delta value   -4   -3   -2   -1    0   +1   +2   +3   +4
2987          * Example TSSI bounds  0xF0 0xD0 0xB5 0xA0 0x88 0x45 0x25 0x15 0x00
2988          */
2989         if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
2990                 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG1, &eeprom);
2991                 tssi_bounds[0] = rt2x00_get_field16(eeprom,
2992                                         EEPROM_TSSI_BOUND_BG1_MINUS4);
2993                 tssi_bounds[1] = rt2x00_get_field16(eeprom,
2994                                         EEPROM_TSSI_BOUND_BG1_MINUS3);
2995
2996                 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG2, &eeprom);
2997                 tssi_bounds[2] = rt2x00_get_field16(eeprom,
2998                                         EEPROM_TSSI_BOUND_BG2_MINUS2);
2999                 tssi_bounds[3] = rt2x00_get_field16(eeprom,
3000                                         EEPROM_TSSI_BOUND_BG2_MINUS1);
3001
3002                 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG3, &eeprom);
3003                 tssi_bounds[4] = rt2x00_get_field16(eeprom,
3004                                         EEPROM_TSSI_BOUND_BG3_REF);
3005                 tssi_bounds[5] = rt2x00_get_field16(eeprom,
3006                                         EEPROM_TSSI_BOUND_BG3_PLUS1);
3007
3008                 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG4, &eeprom);
3009                 tssi_bounds[6] = rt2x00_get_field16(eeprom,
3010                                         EEPROM_TSSI_BOUND_BG4_PLUS2);
3011                 tssi_bounds[7] = rt2x00_get_field16(eeprom,
3012                                         EEPROM_TSSI_BOUND_BG4_PLUS3);
3013
3014                 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG5, &eeprom);
3015                 tssi_bounds[8] = rt2x00_get_field16(eeprom,
3016                                         EEPROM_TSSI_BOUND_BG5_PLUS4);
3017
3018                 step = rt2x00_get_field16(eeprom,
3019                                           EEPROM_TSSI_BOUND_BG5_AGC_STEP);
3020         } else {
3021                 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A1, &eeprom);
3022                 tssi_bounds[0] = rt2x00_get_field16(eeprom,
3023                                         EEPROM_TSSI_BOUND_A1_MINUS4);
3024                 tssi_bounds[1] = rt2x00_get_field16(eeprom,
3025                                         EEPROM_TSSI_BOUND_A1_MINUS3);
3026
3027                 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A2, &eeprom);
3028                 tssi_bounds[2] = rt2x00_get_field16(eeprom,
3029                                         EEPROM_TSSI_BOUND_A2_MINUS2);
3030                 tssi_bounds[3] = rt2x00_get_field16(eeprom,
3031                                         EEPROM_TSSI_BOUND_A2_MINUS1);
3032
3033                 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A3, &eeprom);
3034                 tssi_bounds[4] = rt2x00_get_field16(eeprom,
3035                                         EEPROM_TSSI_BOUND_A3_REF);
3036                 tssi_bounds[5] = rt2x00_get_field16(eeprom,
3037                                         EEPROM_TSSI_BOUND_A3_PLUS1);
3038
3039                 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A4, &eeprom);
3040                 tssi_bounds[6] = rt2x00_get_field16(eeprom,
3041                                         EEPROM_TSSI_BOUND_A4_PLUS2);
3042                 tssi_bounds[7] = rt2x00_get_field16(eeprom,
3043                                         EEPROM_TSSI_BOUND_A4_PLUS3);
3044
3045                 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A5, &eeprom);
3046                 tssi_bounds[8] = rt2x00_get_field16(eeprom,
3047                                         EEPROM_TSSI_BOUND_A5_PLUS4);
3048
3049                 step = rt2x00_get_field16(eeprom,
3050                                           EEPROM_TSSI_BOUND_A5_AGC_STEP);
3051         }
3052
3053         /*
3054          * Check if temperature compensation is supported.
3055          */
3056         if (tssi_bounds[4] == 0xff || step == 0xff)
3057                 return 0;
3058
3059         /*
3060          * Read current TSSI (BBP 49).
3061          */
3062         rt2800_bbp_read(rt2x00dev, 49, &current_tssi);
3063
3064         /*
3065          * Compare TSSI value (BBP49) with the compensation boundaries
3066          * from the EEPROM and increase or decrease tx power.
3067          */
3068         for (i = 0; i <= 3; i++) {
3069                 if (current_tssi > tssi_bounds[i])
3070                         break;
3071         }
3072
3073         if (i == 4) {
3074                 for (i = 8; i >= 5; i--) {
3075                         if (current_tssi < tssi_bounds[i])
3076                                 break;
3077                 }
3078         }
3079
3080         return (i - 4) * step;
3081 }
3082
3083 static int rt2800_get_txpower_bw_comp(struct rt2x00_dev *rt2x00dev,
3084                                       enum ieee80211_band band)
3085 {
3086         u16 eeprom;
3087         u8 comp_en;
3088         u8 comp_type;
3089         int comp_value = 0;
3090
3091         rt2800_eeprom_read(rt2x00dev, EEPROM_TXPOWER_DELTA, &eeprom);
3092
3093         /*
3094          * HT40 compensation not required.
3095          */
3096         if (eeprom == 0xffff ||
3097             !test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
3098                 return 0;
3099
3100         if (band == IEEE80211_BAND_2GHZ) {
3101                 comp_en = rt2x00_get_field16(eeprom,
3102                                  EEPROM_TXPOWER_DELTA_ENABLE_2G);
3103                 if (comp_en) {
3104                         comp_type = rt2x00_get_field16(eeprom,
3105                                            EEPROM_TXPOWER_DELTA_TYPE_2G);
3106                         comp_value = rt2x00_get_field16(eeprom,
3107                                             EEPROM_TXPOWER_DELTA_VALUE_2G);
3108                         if (!comp_type)
3109                                 comp_value = -comp_value;
3110                 }
3111         } else {
3112                 comp_en = rt2x00_get_field16(eeprom,
3113                                  EEPROM_TXPOWER_DELTA_ENABLE_5G);
3114                 if (comp_en) {
3115                         comp_type = rt2x00_get_field16(eeprom,
3116                                            EEPROM_TXPOWER_DELTA_TYPE_5G);
3117                         comp_value = rt2x00_get_field16(eeprom,
3118                                             EEPROM_TXPOWER_DELTA_VALUE_5G);
3119                         if (!comp_type)
3120                                 comp_value = -comp_value;
3121                 }
3122         }
3123
3124         return comp_value;
3125 }
3126
3127 static int rt2800_get_txpower_reg_delta(struct rt2x00_dev *rt2x00dev,
3128                                         int power_level, int max_power)
3129 {
3130         int delta;
3131
3132         if (test_bit(CAPABILITY_POWER_LIMIT, &rt2x00dev->cap_flags))
3133                 return 0;
3134
3135         /*
3136          * XXX: We don't know the maximum transmit power of our hardware since
3137          * the EEPROM doesn't expose it. We only know that we are calibrated
3138          * to 100% tx power.
3139          *
3140          * Hence, we assume the regulatory limit that cfg80211 calulated for
3141          * the current channel is our maximum and if we are requested to lower
3142          * the value we just reduce our tx power accordingly.
3143          */
3144         delta = power_level - max_power;
3145         return min(delta, 0);
3146 }
3147
3148 static u8 rt2800_compensate_txpower(struct rt2x00_dev *rt2x00dev, int is_rate_b,
3149                                    enum ieee80211_band band, int power_level,
3150                                    u8 txpower, int delta)
3151 {
3152         u16 eeprom;
3153         u8 criterion;
3154         u8 eirp_txpower;
3155         u8 eirp_txpower_criterion;
3156         u8 reg_limit;
3157
3158         if (rt2x00_rt(rt2x00dev, RT3593))
3159                 return min_t(u8, txpower, 0xc);
3160
3161         if (test_bit(CAPABILITY_POWER_LIMIT, &rt2x00dev->cap_flags)) {
3162                 /*
3163                  * Check if eirp txpower exceed txpower_limit.
3164                  * We use OFDM 6M as criterion and its eirp txpower
3165                  * is stored at EEPROM_EIRP_MAX_TX_POWER.
3166                  * .11b data rate need add additional 4dbm
3167                  * when calculating eirp txpower.
3168                  */
3169                 rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
3170                                               1, &eeprom);
3171                 criterion = rt2x00_get_field16(eeprom,
3172                                                EEPROM_TXPOWER_BYRATE_RATE0);
3173
3174                 rt2800_eeprom_read(rt2x00dev, EEPROM_EIRP_MAX_TX_POWER,
3175                                    &eeprom);
3176
3177                 if (band == IEEE80211_BAND_2GHZ)
3178                         eirp_txpower_criterion = rt2x00_get_field16(eeprom,
3179                                                  EEPROM_EIRP_MAX_TX_POWER_2GHZ);
3180                 else
3181                         eirp_txpower_criterion = rt2x00_get_field16(eeprom,
3182                                                  EEPROM_EIRP_MAX_TX_POWER_5GHZ);
3183
3184                 eirp_txpower = eirp_txpower_criterion + (txpower - criterion) +
3185                                (is_rate_b ? 4 : 0) + delta;
3186
3187                 reg_limit = (eirp_txpower > power_level) ?
3188                                         (eirp_txpower - power_level) : 0;
3189         } else
3190                 reg_limit = 0;
3191
3192         txpower = max(0, txpower + delta - reg_limit);
3193         return min_t(u8, txpower, 0xc);
3194 }
3195
3196
3197 enum {
3198         TX_PWR_CFG_0_IDX,
3199         TX_PWR_CFG_1_IDX,
3200         TX_PWR_CFG_2_IDX,
3201         TX_PWR_CFG_3_IDX,
3202         TX_PWR_CFG_4_IDX,
3203         TX_PWR_CFG_5_IDX,
3204         TX_PWR_CFG_6_IDX,
3205         TX_PWR_CFG_7_IDX,
3206         TX_PWR_CFG_8_IDX,
3207         TX_PWR_CFG_9_IDX,
3208         TX_PWR_CFG_0_EXT_IDX,
3209         TX_PWR_CFG_1_EXT_IDX,
3210         TX_PWR_CFG_2_EXT_IDX,
3211         TX_PWR_CFG_3_EXT_IDX,
3212         TX_PWR_CFG_4_EXT_IDX,
3213         TX_PWR_CFG_IDX_COUNT,
3214 };
3215
3216 static void rt2800_config_txpower_rt3593(struct rt2x00_dev *rt2x00dev,
3217                                          struct ieee80211_channel *chan,
3218                                          int power_level)
3219 {
3220         u8 txpower;
3221         u16 eeprom;
3222         u32 regs[TX_PWR_CFG_IDX_COUNT];
3223         unsigned int offset;
3224         enum ieee80211_band band = chan->band;
3225         int delta;
3226         int i;
3227
3228         memset(regs, '\0', sizeof(regs));
3229
3230         /* TODO: adapt TX power reduction from the rt28xx code */
3231
3232         /* calculate temperature compensation delta */
3233         delta = rt2800_get_gain_calibration_delta(rt2x00dev);
3234
3235         if (band == IEEE80211_BAND_5GHZ)
3236                 offset = 16;
3237         else
3238                 offset = 0;
3239
3240         if (test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
3241                 offset += 8;
3242
3243         /* read the next four txpower values */
3244         rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
3245                                       offset, &eeprom);
3246
3247         /* CCK 1MBS,2MBS */
3248         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
3249         txpower = rt2800_compensate_txpower(rt2x00dev, 1, band, power_level,
3250                                             txpower, delta);
3251         rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
3252                            TX_PWR_CFG_0_CCK1_CH0, txpower);
3253         rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
3254                            TX_PWR_CFG_0_CCK1_CH1, txpower);
3255         rt2x00_set_field32(&regs[TX_PWR_CFG_0_EXT_IDX],
3256                            TX_PWR_CFG_0_EXT_CCK1_CH2, txpower);
3257
3258         /* CCK 5.5MBS,11MBS */
3259         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1);
3260         txpower = rt2800_compensate_txpower(rt2x00dev, 1, band, power_level,
3261                                             txpower, delta);
3262         rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
3263                            TX_PWR_CFG_0_CCK5_CH0, txpower);
3264         rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
3265                            TX_PWR_CFG_0_CCK5_CH1, txpower);
3266         rt2x00_set_field32(&regs[TX_PWR_CFG_0_EXT_IDX],
3267                            TX_PWR_CFG_0_EXT_CCK5_CH2, txpower);
3268
3269         /* OFDM 6MBS,9MBS */
3270         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2);
3271         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3272                                             txpower, delta);
3273         rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
3274                            TX_PWR_CFG_0_OFDM6_CH0, txpower);
3275         rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
3276                            TX_PWR_CFG_0_OFDM6_CH1, txpower);
3277         rt2x00_set_field32(&regs[TX_PWR_CFG_0_EXT_IDX],
3278                            TX_PWR_CFG_0_EXT_OFDM6_CH2, txpower);
3279
3280         /* OFDM 12MBS,18MBS */
3281         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3);
3282         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3283                                             txpower, delta);
3284         rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
3285                            TX_PWR_CFG_0_OFDM12_CH0, txpower);
3286         rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
3287                            TX_PWR_CFG_0_OFDM12_CH1, txpower);
3288         rt2x00_set_field32(&regs[TX_PWR_CFG_0_EXT_IDX],
3289                            TX_PWR_CFG_0_EXT_OFDM12_CH2, txpower);
3290
3291         /* read the next four txpower values */
3292         rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
3293                                       offset + 1, &eeprom);
3294
3295         /* OFDM 24MBS,36MBS */
3296         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
3297         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3298                                             txpower, delta);
3299         rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
3300                            TX_PWR_CFG_1_OFDM24_CH0, txpower);
3301         rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
3302                            TX_PWR_CFG_1_OFDM24_CH1, txpower);
3303         rt2x00_set_field32(&regs[TX_PWR_CFG_1_EXT_IDX],
3304                            TX_PWR_CFG_1_EXT_OFDM24_CH2, txpower);
3305
3306         /* OFDM 48MBS */
3307         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1);
3308         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3309                                             txpower, delta);
3310         rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
3311                            TX_PWR_CFG_1_OFDM48_CH0, txpower);
3312         rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
3313                            TX_PWR_CFG_1_OFDM48_CH1, txpower);
3314         rt2x00_set_field32(&regs[TX_PWR_CFG_1_EXT_IDX],
3315                            TX_PWR_CFG_1_EXT_OFDM48_CH2, txpower);
3316
3317         /* OFDM 54MBS */
3318         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2);
3319         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3320                                             txpower, delta);
3321         rt2x00_set_field32(&regs[TX_PWR_CFG_7_IDX],
3322                            TX_PWR_CFG_7_OFDM54_CH0, txpower);
3323         rt2x00_set_field32(&regs[TX_PWR_CFG_7_IDX],
3324                            TX_PWR_CFG_7_OFDM54_CH1, txpower);
3325         rt2x00_set_field32(&regs[TX_PWR_CFG_7_IDX],
3326                            TX_PWR_CFG_7_OFDM54_CH2, txpower);
3327
3328         /* read the next four txpower values */
3329         rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
3330                                       offset + 2, &eeprom);
3331
3332         /* MCS 0,1 */
3333         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
3334         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3335                                             txpower, delta);
3336         rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
3337                            TX_PWR_CFG_1_MCS0_CH0, txpower);
3338         rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
3339                            TX_PWR_CFG_1_MCS0_CH1, txpower);
3340         rt2x00_set_field32(&regs[TX_PWR_CFG_1_EXT_IDX],
3341                            TX_PWR_CFG_1_EXT_MCS0_CH2, txpower);
3342
3343         /* MCS 2,3 */
3344         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1);
3345         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3346                                             txpower, delta);
3347         rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
3348                            TX_PWR_CFG_1_MCS2_CH0, txpower);
3349         rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
3350                            TX_PWR_CFG_1_MCS2_CH1, txpower);
3351         rt2x00_set_field32(&regs[TX_PWR_CFG_1_EXT_IDX],
3352                            TX_PWR_CFG_1_EXT_MCS2_CH2, txpower);
3353
3354         /* MCS 4,5 */
3355         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2);
3356         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3357                                             txpower, delta);
3358         rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
3359                            TX_PWR_CFG_2_MCS4_CH0, txpower);
3360         rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
3361                            TX_PWR_CFG_2_MCS4_CH1, txpower);
3362         rt2x00_set_field32(&regs[TX_PWR_CFG_2_EXT_IDX],
3363                            TX_PWR_CFG_2_EXT_MCS4_CH2, txpower);
3364
3365         /* MCS 6 */
3366         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3);
3367         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3368                                             txpower, delta);
3369         rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
3370                            TX_PWR_CFG_2_MCS6_CH0, txpower);
3371         rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
3372                            TX_PWR_CFG_2_MCS6_CH1, txpower);
3373         rt2x00_set_field32(&regs[TX_PWR_CFG_2_EXT_IDX],
3374                            TX_PWR_CFG_2_EXT_MCS6_CH2, txpower);
3375
3376         /* read the next four txpower values */
3377         rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
3378                                       offset + 3, &eeprom);
3379
3380         /* MCS 7 */
3381         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
3382         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3383                                             txpower, delta);
3384         rt2x00_set_field32(&regs[TX_PWR_CFG_7_IDX],
3385                            TX_PWR_CFG_7_MCS7_CH0, txpower);
3386         rt2x00_set_field32(&regs[TX_PWR_CFG_7_IDX],
3387                            TX_PWR_CFG_7_MCS7_CH1, txpower);
3388         rt2x00_set_field32(&regs[TX_PWR_CFG_7_IDX],
3389                            TX_PWR_CFG_7_MCS7_CH2, txpower);
3390
3391         /* MCS 8,9 */
3392         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1);
3393         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3394                                             txpower, delta);
3395         rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
3396                            TX_PWR_CFG_2_MCS8_CH0, txpower);
3397         rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
3398                            TX_PWR_CFG_2_MCS8_CH1, txpower);
3399         rt2x00_set_field32(&regs[TX_PWR_CFG_2_EXT_IDX],
3400                            TX_PWR_CFG_2_EXT_MCS8_CH2, txpower);
3401
3402         /* MCS 10,11 */
3403         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2);
3404         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3405                                             txpower, delta);
3406         rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
3407                            TX_PWR_CFG_2_MCS10_CH0, txpower);
3408         rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
3409                            TX_PWR_CFG_2_MCS10_CH1, txpower);
3410         rt2x00_set_field32(&regs[TX_PWR_CFG_2_EXT_IDX],
3411                            TX_PWR_CFG_2_EXT_MCS10_CH2, txpower);
3412
3413         /* MCS 12,13 */
3414         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3);
3415         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3416                                             txpower, delta);
3417         rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
3418                            TX_PWR_CFG_3_MCS12_CH0, txpower);
3419         rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
3420                            TX_PWR_CFG_3_MCS12_CH1, txpower);
3421         rt2x00_set_field32(&regs[TX_PWR_CFG_3_EXT_IDX],
3422                            TX_PWR_CFG_3_EXT_MCS12_CH2, txpower);
3423
3424         /* read the next four txpower values */
3425         rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
3426                                       offset + 4, &eeprom);
3427
3428         /* MCS 14 */
3429         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
3430         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3431                                             txpower, delta);
3432         rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
3433                            TX_PWR_CFG_3_MCS14_CH0, txpower);
3434         rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
3435                            TX_PWR_CFG_3_MCS14_CH1, txpower);
3436         rt2x00_set_field32(&regs[TX_PWR_CFG_3_EXT_IDX],
3437                            TX_PWR_CFG_3_EXT_MCS14_CH2, txpower);
3438
3439         /* MCS 15 */
3440         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1);
3441         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3442                                             txpower, delta);
3443         rt2x00_set_field32(&regs[TX_PWR_CFG_8_IDX],
3444                            TX_PWR_CFG_8_MCS15_CH0, txpower);
3445         rt2x00_set_field32(&regs[TX_PWR_CFG_8_IDX],
3446                            TX_PWR_CFG_8_MCS15_CH1, txpower);
3447         rt2x00_set_field32(&regs[TX_PWR_CFG_8_IDX],
3448                            TX_PWR_CFG_8_MCS15_CH2, txpower);
3449
3450         /* MCS 16,17 */
3451         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2);
3452         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3453                                             txpower, delta);
3454         rt2x00_set_field32(&regs[TX_PWR_CFG_5_IDX],
3455                            TX_PWR_CFG_5_MCS16_CH0, txpower);
3456         rt2x00_set_field32(&regs[TX_PWR_CFG_5_IDX],
3457                            TX_PWR_CFG_5_MCS16_CH1, txpower);
3458         rt2x00_set_field32(&regs[TX_PWR_CFG_5_IDX],
3459                            TX_PWR_CFG_5_MCS16_CH2, txpower);
3460
3461         /* MCS 18,19 */
3462         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3);
3463         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3464                                             txpower, delta);
3465         rt2x00_set_field32(&regs[TX_PWR_CFG_5_IDX],
3466                            TX_PWR_CFG_5_MCS18_CH0, txpower);
3467         rt2x00_set_field32(&regs[TX_PWR_CFG_5_IDX],
3468                            TX_PWR_CFG_5_MCS18_CH1, txpower);
3469         rt2x00_set_field32(&regs[TX_PWR_CFG_5_IDX],
3470                            TX_PWR_CFG_5_MCS18_CH2, txpower);
3471
3472         /* read the next four txpower values */
3473         rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
3474                                       offset + 5, &eeprom);
3475
3476         /* MCS 20,21 */
3477         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
3478         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3479                                             txpower, delta);
3480         rt2x00_set_field32(&regs[TX_PWR_CFG_6_IDX],
3481                            TX_PWR_CFG_6_MCS20_CH0, txpower);
3482         rt2x00_set_field32(&regs[TX_PWR_CFG_6_IDX],
3483                            TX_PWR_CFG_6_MCS20_CH1, txpower);
3484         rt2x00_set_field32(&regs[TX_PWR_CFG_6_IDX],
3485                            TX_PWR_CFG_6_MCS20_CH2, txpower);
3486
3487         /* MCS 22 */
3488         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1);
3489         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3490                                             txpower, delta);
3491         rt2x00_set_field32(&regs[TX_PWR_CFG_6_IDX],
3492                            TX_PWR_CFG_6_MCS22_CH0, txpower);
3493         rt2x00_set_field32(&regs[TX_PWR_CFG_6_IDX],
3494                            TX_PWR_CFG_6_MCS22_CH1, txpower);
3495         rt2x00_set_field32(&regs[TX_PWR_CFG_6_IDX],
3496                            TX_PWR_CFG_6_MCS22_CH2, txpower);
3497
3498         /* MCS 23 */
3499         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2);
3500         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3501                                             txpower, delta);
3502         rt2x00_set_field32(&regs[TX_PWR_CFG_8_IDX],
3503                            TX_PWR_CFG_8_MCS23_CH0, txpower);
3504         rt2x00_set_field32(&regs[TX_PWR_CFG_8_IDX],
3505                            TX_PWR_CFG_8_MCS23_CH1, txpower);
3506         rt2x00_set_field32(&regs[TX_PWR_CFG_8_IDX],
3507                            TX_PWR_CFG_8_MCS23_CH2, txpower);
3508
3509         /* read the next four txpower values */
3510         rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
3511                                       offset + 6, &eeprom);
3512
3513         /* STBC, MCS 0,1 */
3514         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
3515         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3516                                             txpower, delta);
3517         rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
3518                            TX_PWR_CFG_3_STBC0_CH0, txpower);
3519         rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
3520                            TX_PWR_CFG_3_STBC0_CH1, txpower);
3521         rt2x00_set_field32(&regs[TX_PWR_CFG_3_EXT_IDX],
3522                            TX_PWR_CFG_3_EXT_STBC0_CH2, txpower);
3523
3524         /* STBC, MCS 2,3 */
3525         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1);
3526         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3527                                             txpower, delta);
3528         rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
3529                            TX_PWR_CFG_3_STBC2_CH0, txpower);
3530         rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
3531                            TX_PWR_CFG_3_STBC2_CH1, txpower);
3532         rt2x00_set_field32(&regs[TX_PWR_CFG_3_EXT_IDX],
3533                            TX_PWR_CFG_3_EXT_STBC2_CH2, txpower);
3534
3535         /* STBC, MCS 4,5 */
3536         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2);
3537         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3538                                             txpower, delta);
3539         rt2x00_set_field32(&regs[TX_PWR_CFG_4_IDX], TX_PWR_CFG_RATE0, txpower);
3540         rt2x00_set_field32(&regs[TX_PWR_CFG_4_IDX], TX_PWR_CFG_RATE1, txpower);
3541         rt2x00_set_field32(&regs[TX_PWR_CFG_4_EXT_IDX], TX_PWR_CFG_RATE0,
3542                            txpower);
3543
3544         /* STBC, MCS 6 */
3545         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3);
3546         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3547                                             txpower, delta);
3548         rt2x00_set_field32(&regs[TX_PWR_CFG_4_IDX], TX_PWR_CFG_RATE2, txpower);
3549         rt2x00_set_field32(&regs[TX_PWR_CFG_4_IDX], TX_PWR_CFG_RATE3, txpower);
3550         rt2x00_set_field32(&regs[TX_PWR_CFG_4_EXT_IDX], TX_PWR_CFG_RATE2,
3551                            txpower);
3552
3553         /* read the next four txpower values */
3554         rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
3555                                       offset + 7, &eeprom);
3556
3557         /* STBC, MCS 7 */
3558         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
3559         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3560                                             txpower, delta);
3561         rt2x00_set_field32(&regs[TX_PWR_CFG_9_IDX],
3562                            TX_PWR_CFG_9_STBC7_CH0, txpower);
3563         rt2x00_set_field32(&regs[TX_PWR_CFG_9_IDX],
3564                            TX_PWR_CFG_9_STBC7_CH1, txpower);
3565         rt2x00_set_field32(&regs[TX_PWR_CFG_9_IDX],
3566                            TX_PWR_CFG_9_STBC7_CH2, txpower);
3567
3568         rt2800_register_write(rt2x00dev, TX_PWR_CFG_0, regs[TX_PWR_CFG_0_IDX]);
3569         rt2800_register_write(rt2x00dev, TX_PWR_CFG_1, regs[TX_PWR_CFG_1_IDX]);
3570         rt2800_register_write(rt2x00dev, TX_PWR_CFG_2, regs[TX_PWR_CFG_2_IDX]);
3571         rt2800_register_write(rt2x00dev, TX_PWR_CFG_3, regs[TX_PWR_CFG_3_IDX]);
3572         rt2800_register_write(rt2x00dev, TX_PWR_CFG_4, regs[TX_PWR_CFG_4_IDX]);
3573         rt2800_register_write(rt2x00dev, TX_PWR_CFG_5, regs[TX_PWR_CFG_5_IDX]);
3574         rt2800_register_write(rt2x00dev, TX_PWR_CFG_6, regs[TX_PWR_CFG_6_IDX]);
3575         rt2800_register_write(rt2x00dev, TX_PWR_CFG_7, regs[TX_PWR_CFG_7_IDX]);
3576         rt2800_register_write(rt2x00dev, TX_PWR_CFG_8, regs[TX_PWR_CFG_8_IDX]);
3577         rt2800_register_write(rt2x00dev, TX_PWR_CFG_9, regs[TX_PWR_CFG_9_IDX]);
3578
3579         rt2800_register_write(rt2x00dev, TX_PWR_CFG_0_EXT,
3580                               regs[TX_PWR_CFG_0_EXT_IDX]);
3581         rt2800_register_write(rt2x00dev, TX_PWR_CFG_1_EXT,
3582                               regs[TX_PWR_CFG_1_EXT_IDX]);
3583         rt2800_register_write(rt2x00dev, TX_PWR_CFG_2_EXT,
3584                               regs[TX_PWR_CFG_2_EXT_IDX]);
3585         rt2800_register_write(rt2x00dev, TX_PWR_CFG_3_EXT,
3586                               regs[TX_PWR_CFG_3_EXT_IDX]);
3587         rt2800_register_write(rt2x00dev, TX_PWR_CFG_4_EXT,
3588                               regs[TX_PWR_CFG_4_EXT_IDX]);
3589
3590         for (i = 0; i < TX_PWR_CFG_IDX_COUNT; i++)
3591                 rt2x00_dbg(rt2x00dev,
3592                            "band:%cGHz, BW:%c0MHz, TX_PWR_CFG_%d%s = %08lx\n",
3593                            (band == IEEE80211_BAND_5GHZ) ? '5' : '2',
3594                            (test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags)) ?
3595                                                                 '4' : '2',
3596                            (i > TX_PWR_CFG_9_IDX) ?
3597                                         (i - TX_PWR_CFG_9_IDX - 1) : i,
3598                            (i > TX_PWR_CFG_9_IDX) ? "_EXT" : "",
3599                            (unsigned long) regs[i]);
3600 }
3601
3602 /*
3603  * We configure transmit power using MAC TX_PWR_CFG_{0,...,N} registers and
3604  * BBP R1 register. TX_PWR_CFG_X allow to configure per rate TX power values,
3605  * 4 bits for each rate (tune from 0 to 15 dBm). BBP_R1 controls transmit power
3606  * for all rates, but allow to set only 4 discrete values: -12, -6, 0 and 6 dBm.
3607  * Reference per rate transmit power values are located in the EEPROM at
3608  * EEPROM_TXPOWER_BYRATE offset. We adjust them and BBP R1 settings according to
3609  * current conditions (i.e. band, bandwidth, temperature, user settings).
3610  */
3611 static void rt2800_config_txpower_rt28xx(struct rt2x00_dev *rt2x00dev,
3612                                          struct ieee80211_channel *chan,
3613                                          int power_level)
3614 {
3615         u8 txpower, r1;
3616         u16 eeprom;
3617         u32 reg, offset;
3618         int i, is_rate_b, delta, power_ctrl;
3619         enum ieee80211_band band = chan->band;
3620
3621         /*
3622          * Calculate HT40 compensation. For 40MHz we need to add or subtract
3623          * value read from EEPROM (different for 2GHz and for 5GHz).
3624          */
3625         delta = rt2800_get_txpower_bw_comp(rt2x00dev, band);
3626
3627         /*
3628          * Calculate temperature compensation. Depends on measurement of current
3629          * TSSI (Transmitter Signal Strength Indication) we know TX power (due
3630          * to temperature or maybe other factors) is smaller or bigger than
3631          * expected. We adjust it, based on TSSI reference and boundaries values
3632          * provided in EEPROM.
3633          */
3634         delta += rt2800_get_gain_calibration_delta(rt2x00dev);
3635
3636         /*
3637          * Decrease power according to user settings, on devices with unknown
3638          * maximum tx power. For other devices we take user power_level into
3639          * consideration on rt2800_compensate_txpower().
3640          */
3641         delta += rt2800_get_txpower_reg_delta(rt2x00dev, power_level,
3642                                               chan->max_power);
3643
3644         /*
3645          * BBP_R1 controls TX power for all rates, it allow to set the following
3646          * gains -12, -6, 0, +6 dBm by setting values 2, 1, 0, 3 respectively.
3647          *
3648          * TODO: we do not use +6 dBm option to do not increase power beyond
3649          * regulatory limit, however this could be utilized for devices with
3650          * CAPABILITY_POWER_LIMIT.
3651          *
3652          * TODO: add different temperature compensation code for RT3290 & RT5390
3653          * to allow to use BBP_R1 for those chips.
3654          */
3655         if (!rt2x00_rt(rt2x00dev, RT3290) &&
3656             !rt2x00_rt(rt2x00dev, RT5390)) {
3657                 rt2800_bbp_read(rt2x00dev, 1, &r1);
3658                 if (delta <= -12) {
3659                         power_ctrl = 2;
3660                         delta += 12;
3661                 } else if (delta <= -6) {
3662                         power_ctrl = 1;
3663                         delta += 6;
3664                 } else {
3665                         power_ctrl = 0;
3666                 }
3667                 rt2x00_set_field8(&r1, BBP1_TX_POWER_CTRL, power_ctrl);
3668                 rt2800_bbp_write(rt2x00dev, 1, r1);
3669         }
3670
3671         offset = TX_PWR_CFG_0;
3672
3673         for (i = 0; i < EEPROM_TXPOWER_BYRATE_SIZE; i += 2) {
3674                 /* just to be safe */
3675                 if (offset > TX_PWR_CFG_4)
3676                         break;
3677
3678                 rt2800_register_read(rt2x00dev, offset, &reg);
3679
3680                 /* read the next four txpower values */
3681                 rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
3682                                               i, &eeprom);
3683
3684                 is_rate_b = i ? 0 : 1;
3685                 /*
3686                  * TX_PWR_CFG_0: 1MBS, TX_PWR_CFG_1: 24MBS,
3687                  * TX_PWR_CFG_2: MCS4, TX_PWR_CFG_3: MCS12,
3688                  * TX_PWR_CFG_4: unknown
3689                  */
3690                 txpower = rt2x00_get_field16(eeprom,
3691                                              EEPROM_TXPOWER_BYRATE_RATE0);
3692                 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
3693                                              power_level, txpower, delta);
3694                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE0, txpower);
3695
3696                 /*
3697                  * TX_PWR_CFG_0: 2MBS, TX_PWR_CFG_1: 36MBS,
3698                  * TX_PWR_CFG_2: MCS5, TX_PWR_CFG_3: MCS13,
3699                  * TX_PWR_CFG_4: unknown
3700                  */
3701                 txpower = rt2x00_get_field16(eeprom,
3702                                              EEPROM_TXPOWER_BYRATE_RATE1);
3703                 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
3704                                              power_level, txpower, delta);
3705                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE1, txpower);
3706
3707                 /*
3708                  * TX_PWR_CFG_0: 5.5MBS, TX_PWR_CFG_1: 48MBS,
3709                  * TX_PWR_CFG_2: MCS6,  TX_PWR_CFG_3: MCS14,
3710                  * TX_PWR_CFG_4: unknown
3711                  */
3712                 txpower = rt2x00_get_field16(eeprom,
3713                                              EEPROM_TXPOWER_BYRATE_RATE2);
3714                 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
3715                                              power_level, txpower, delta);
3716                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE2, txpower);
3717
3718                 /*
3719                  * TX_PWR_CFG_0: 11MBS, TX_PWR_CFG_1: 54MBS,
3720                  * TX_PWR_CFG_2: MCS7,  TX_PWR_CFG_3: MCS15,
3721                  * TX_PWR_CFG_4: unknown
3722                  */
3723                 txpower = rt2x00_get_field16(eeprom,
3724                                              EEPROM_TXPOWER_BYRATE_RATE3);
3725                 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
3726                                              power_level, txpower, delta);
3727                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE3, txpower);
3728
3729                 /* read the next four txpower values */
3730                 rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
3731                                               i + 1, &eeprom);
3732
3733                 is_rate_b = 0;
3734                 /*
3735                  * TX_PWR_CFG_0: 6MBS, TX_PWR_CFG_1: MCS0,
3736                  * TX_PWR_CFG_2: MCS8, TX_PWR_CFG_3: unknown,
3737                  * TX_PWR_CFG_4: unknown
3738                  */
3739                 txpower = rt2x00_get_field16(eeprom,
3740                                              EEPROM_TXPOWER_BYRATE_RATE0);
3741                 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
3742                                              power_level, txpower, delta);
3743                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE4, txpower);
3744
3745                 /*
3746                  * TX_PWR_CFG_0: 9MBS, TX_PWR_CFG_1: MCS1,
3747                  * TX_PWR_CFG_2: MCS9, TX_PWR_CFG_3: unknown,
3748                  * TX_PWR_CFG_4: unknown
3749                  */
3750                 txpower = rt2x00_get_field16(eeprom,
3751                                              EEPROM_TXPOWER_BYRATE_RATE1);
3752                 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
3753                                              power_level, txpower, delta);
3754                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE5, txpower);
3755
3756                 /*
3757                  * TX_PWR_CFG_0: 12MBS, TX_PWR_CFG_1: MCS2,
3758                  * TX_PWR_CFG_2: MCS10, TX_PWR_CFG_3: unknown,
3759                  * TX_PWR_CFG_4: unknown
3760                  */
3761                 txpower = rt2x00_get_field16(eeprom,
3762                                              EEPROM_TXPOWER_BYRATE_RATE2);
3763                 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
3764                                              power_level, txpower, delta);
3765                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE6, txpower);
3766
3767                 /*
3768                  * TX_PWR_CFG_0: 18MBS, TX_PWR_CFG_1: MCS3,
3769                  * TX_PWR_CFG_2: MCS11, TX_PWR_CFG_3: unknown,
3770                  * TX_PWR_CFG_4: unknown
3771                  */
3772                 txpower = rt2x00_get_field16(eeprom,
3773                                              EEPROM_TXPOWER_BYRATE_RATE3);
3774                 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
3775                                              power_level, txpower, delta);
3776                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE7, txpower);
3777
3778                 rt2800_register_write(rt2x00dev, offset, reg);
3779
3780                 /* next TX_PWR_CFG register */
3781                 offset += 4;
3782         }
3783 }
3784
3785 static void rt2800_config_txpower(struct rt2x00_dev *rt2x00dev,
3786                                   struct ieee80211_channel *chan,
3787                                   int power_level)
3788 {
3789         if (rt2x00_rt(rt2x00dev, RT3593))
3790                 rt2800_config_txpower_rt3593(rt2x00dev, chan, power_level);
3791         else
3792                 rt2800_config_txpower_rt28xx(rt2x00dev, chan, power_level);
3793 }
3794
3795 void rt2800_gain_calibration(struct rt2x00_dev *rt2x00dev)
3796 {
3797         rt2800_config_txpower(rt2x00dev, rt2x00dev->hw->conf.chandef.chan,
3798                               rt2x00dev->tx_power);
3799 }
3800 EXPORT_SYMBOL_GPL(rt2800_gain_calibration);
3801
3802 void rt2800_vco_calibration(struct rt2x00_dev *rt2x00dev)
3803 {
3804         u32     tx_pin;
3805         u8      rfcsr;
3806
3807         /*
3808          * A voltage-controlled oscillator(VCO) is an electronic oscillator
3809          * designed to be controlled in oscillation frequency by a voltage
3810          * input. Maybe the temperature will affect the frequency of
3811          * oscillation to be shifted. The VCO calibration will be called
3812          * periodically to adjust the frequency to be precision.
3813         */
3814
3815         rt2800_register_read(rt2x00dev, TX_PIN_CFG, &tx_pin);
3816         tx_pin &= TX_PIN_CFG_PA_PE_DISABLE;
3817         rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
3818
3819         switch (rt2x00dev->chip.rf) {
3820         case RF2020:
3821         case RF3020:
3822         case RF3021:
3823         case RF3022:
3824         case RF3320:
3825         case RF3052:
3826                 rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
3827                 rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
3828                 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
3829                 break;
3830         case RF3290:
3831         case RF5360:
3832         case RF5370:
3833         case RF5372:
3834         case RF5390:
3835         case RF5392:
3836                 rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr);
3837                 rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1);
3838                 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
3839                 break;
3840         default:
3841                 return;
3842         }
3843
3844         mdelay(1);
3845
3846         rt2800_register_read(rt2x00dev, TX_PIN_CFG, &tx_pin);
3847         if (rt2x00dev->rf_channel <= 14) {
3848                 switch (rt2x00dev->default_ant.tx_chain_num) {
3849                 case 3:
3850                         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G2_EN, 1);
3851                         /* fall through */
3852                 case 2:
3853                         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN, 1);
3854                         /* fall through */
3855                 case 1:
3856                 default:
3857                         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, 1);
3858                         break;
3859                 }
3860         } else {
3861                 switch (rt2x00dev->default_ant.tx_chain_num) {
3862                 case 3:
3863                         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A2_EN, 1);
3864                         /* fall through */
3865                 case 2:
3866                         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN, 1);
3867                         /* fall through */
3868                 case 1:
3869                 default:
3870                         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN, 1);
3871                         break;
3872                 }
3873         }
3874         rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
3875
3876 }
3877 EXPORT_SYMBOL_GPL(rt2800_vco_calibration);
3878
3879 static void rt2800_config_retry_limit(struct rt2x00_dev *rt2x00dev,
3880                                       struct rt2x00lib_conf *libconf)
3881 {
3882         u32 reg;
3883
3884         rt2800_register_read(rt2x00dev, TX_RTY_CFG, &reg);
3885         rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT,
3886                            libconf->conf->short_frame_max_tx_count);
3887         rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT,
3888                            libconf->conf->long_frame_max_tx_count);
3889         rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
3890 }
3891
3892 static void rt2800_config_ps(struct rt2x00_dev *rt2x00dev,
3893                              struct rt2x00lib_conf *libconf)
3894 {
3895         enum dev_state state =
3896             (libconf->conf->flags & IEEE80211_CONF_PS) ?
3897                 STATE_SLEEP : STATE_AWAKE;
3898         u32 reg;
3899
3900         if (state == STATE_SLEEP) {
3901                 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0);
3902
3903                 rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
3904                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 5);
3905                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE,
3906                                    libconf->conf->listen_interval - 1);
3907                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 1);
3908                 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
3909
3910                 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
3911         } else {
3912                 rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
3913                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 0);
3914                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE, 0);
3915                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 0);
3916                 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
3917
3918                 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
3919         }
3920 }
3921
3922 void rt2800_config(struct rt2x00_dev *rt2x00dev,
3923                    struct rt2x00lib_conf *libconf,
3924                    const unsigned int flags)
3925 {
3926         /* Always recalculate LNA gain before changing configuration */
3927         rt2800_config_lna_gain(rt2x00dev, libconf);
3928
3929         if (flags & IEEE80211_CONF_CHANGE_CHANNEL) {
3930                 rt2800_config_channel(rt2x00dev, libconf->conf,
3931                                       &libconf->rf, &libconf->channel);
3932                 rt2800_config_txpower(rt2x00dev, libconf->conf->chandef.chan,
3933                                       libconf->conf->power_level);
3934         }
3935         if (flags & IEEE80211_CONF_CHANGE_POWER)
3936                 rt2800_config_txpower(rt2x00dev, libconf->conf->chandef.chan,
3937                                       libconf->conf->power_level);
3938         if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
3939                 rt2800_config_retry_limit(rt2x00dev, libconf);
3940         if (flags & IEEE80211_CONF_CHANGE_PS)
3941                 rt2800_config_ps(rt2x00dev, libconf);
3942 }
3943 EXPORT_SYMBOL_GPL(rt2800_config);
3944
3945 /*
3946  * Link tuning
3947  */
3948 void rt2800_link_stats(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
3949 {
3950         u32 reg;
3951
3952         /*
3953          * Update FCS error count from register.
3954          */
3955         rt2800_register_read(rt2x00dev, RX_STA_CNT0, &reg);
3956         qual->rx_failed = rt2x00_get_field32(reg, RX_STA_CNT0_CRC_ERR);
3957 }
3958 EXPORT_SYMBOL_GPL(rt2800_link_stats);
3959
3960 static u8 rt2800_get_default_vgc(struct rt2x00_dev *rt2x00dev)
3961 {
3962         u8 vgc;
3963
3964         if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
3965                 if (rt2x00_rt(rt2x00dev, RT3070) ||
3966                     rt2x00_rt(rt2x00dev, RT3071) ||
3967                     rt2x00_rt(rt2x00dev, RT3090) ||
3968                     rt2x00_rt(rt2x00dev, RT3290) ||
3969                     rt2x00_rt(rt2x00dev, RT3390) ||
3970                     rt2x00_rt(rt2x00dev, RT3572) ||
3971                     rt2x00_rt(rt2x00dev, RT5390) ||
3972                     rt2x00_rt(rt2x00dev, RT5392) ||
3973                     rt2x00_rt(rt2x00dev, RT5592))
3974                         vgc = 0x1c + (2 * rt2x00dev->lna_gain);
3975                 else
3976                         vgc = 0x2e + rt2x00dev->lna_gain;
3977         } else { /* 5GHZ band */
3978                 if (rt2x00_rt(rt2x00dev, RT3572))
3979                         vgc = 0x22 + (rt2x00dev->lna_gain * 5) / 3;
3980                 else if (rt2x00_rt(rt2x00dev, RT5592))
3981                         vgc = 0x24 + (2 * rt2x00dev->lna_gain);
3982                 else {
3983                         if (!test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
3984                                 vgc = 0x32 + (rt2x00dev->lna_gain * 5) / 3;
3985                         else
3986                                 vgc = 0x3a + (rt2x00dev->lna_gain * 5) / 3;
3987                 }
3988         }
3989
3990         return vgc;
3991 }
3992
3993 static inline void rt2800_set_vgc(struct rt2x00_dev *rt2x00dev,
3994                                   struct link_qual *qual, u8 vgc_level)
3995 {
3996         if (qual->vgc_level != vgc_level) {
3997                 if (rt2x00_rt(rt2x00dev, RT5592)) {
3998                         rt2800_bbp_write(rt2x00dev, 83, qual->rssi > -65 ? 0x4a : 0x7a);
3999                         rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, vgc_level);
4000                 } else
4001                         rt2800_bbp_write(rt2x00dev, 66, vgc_level);
4002                 qual->vgc_level = vgc_level;
4003                 qual->vgc_level_reg = vgc_level;
4004         }
4005 }
4006
4007 void rt2800_reset_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
4008 {
4009         rt2800_set_vgc(rt2x00dev, qual, rt2800_get_default_vgc(rt2x00dev));
4010 }
4011 EXPORT_SYMBOL_GPL(rt2800_reset_tuner);
4012
4013 void rt2800_link_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual,
4014                        const u32 count)
4015 {
4016         u8 vgc;
4017
4018         if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C))
4019                 return;
4020         /*
4021          * When RSSI is better then -80 increase VGC level with 0x10, except
4022          * for rt5592 chip.
4023          */
4024
4025         vgc = rt2800_get_default_vgc(rt2x00dev);
4026
4027         if (rt2x00_rt(rt2x00dev, RT5592) && qual->rssi > -65)
4028                 vgc += 0x20;
4029         else if (qual->rssi > -80)
4030                 vgc += 0x10;
4031
4032         rt2800_set_vgc(rt2x00dev, qual, vgc);
4033 }
4034 EXPORT_SYMBOL_GPL(rt2800_link_tuner);
4035
4036 /*
4037  * Initialization functions.
4038  */
4039 static int rt2800_init_registers(struct rt2x00_dev *rt2x00dev)
4040 {
4041         u32 reg;
4042         u16 eeprom;
4043         unsigned int i;
4044         int ret;
4045
4046         rt2800_disable_wpdma(rt2x00dev);
4047
4048         ret = rt2800_drv_init_registers(rt2x00dev);
4049         if (ret)
4050                 return ret;
4051
4052         rt2800_register_read(rt2x00dev, BCN_OFFSET0, &reg);
4053         rt2x00_set_field32(&reg, BCN_OFFSET0_BCN0, 0xe0); /* 0x3800 */
4054         rt2x00_set_field32(&reg, BCN_OFFSET0_BCN1, 0xe8); /* 0x3a00 */
4055         rt2x00_set_field32(&reg, BCN_OFFSET0_BCN2, 0xf0); /* 0x3c00 */
4056         rt2x00_set_field32(&reg, BCN_OFFSET0_BCN3, 0xf8); /* 0x3e00 */
4057         rt2800_register_write(rt2x00dev, BCN_OFFSET0, reg);
4058
4059         rt2800_register_read(rt2x00dev, BCN_OFFSET1, &reg);
4060         rt2x00_set_field32(&reg, BCN_OFFSET1_BCN4, 0xc8); /* 0x3200 */
4061         rt2x00_set_field32(&reg, BCN_OFFSET1_BCN5, 0xd0); /* 0x3400 */
4062         rt2x00_set_field32(&reg, BCN_OFFSET1_BCN6, 0x77); /* 0x1dc0 */
4063         rt2x00_set_field32(&reg, BCN_OFFSET1_BCN7, 0x6f); /* 0x1bc0 */
4064         rt2800_register_write(rt2x00dev, BCN_OFFSET1, reg);
4065
4066         rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE, 0x0000013f);
4067         rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
4068
4069         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
4070
4071         rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
4072         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL, 1600);
4073         rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 0);
4074         rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, 0);
4075         rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 0);
4076         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
4077         rt2x00_set_field32(&reg, BCN_TIME_CFG_TX_TIME_COMPENSATE, 0);
4078         rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
4079
4080         rt2800_config_filter(rt2x00dev, FIF_ALLMULTI);
4081
4082         rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
4083         rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME, 9);
4084         rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_CC_DELAY_TIME, 2);
4085         rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
4086
4087         if (rt2x00_rt(rt2x00dev, RT3290)) {
4088                 rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL, &reg);
4089                 if (rt2x00_get_field32(reg, WLAN_EN) == 1) {
4090                         rt2x00_set_field32(&reg, PCIE_APP0_CLK_REQ, 1);
4091                         rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg);
4092                 }
4093
4094                 rt2800_register_read(rt2x00dev, CMB_CTRL, &reg);
4095                 if (!(rt2x00_get_field32(reg, LDO0_EN) == 1)) {
4096                         rt2x00_set_field32(&reg, LDO0_EN, 1);
4097                         rt2x00_set_field32(&reg, LDO_BGSEL, 3);
4098                         rt2800_register_write(rt2x00dev, CMB_CTRL, reg);
4099                 }
4100
4101                 rt2800_register_read(rt2x00dev, OSC_CTRL, &reg);
4102                 rt2x00_set_field32(&reg, OSC_ROSC_EN, 1);
4103                 rt2x00_set_field32(&reg, OSC_CAL_REQ, 1);
4104                 rt2x00_set_field32(&reg, OSC_REF_CYCLE, 0x27);
4105                 rt2800_register_write(rt2x00dev, OSC_CTRL, reg);
4106
4107                 rt2800_register_read(rt2x00dev, COEX_CFG0, &reg);
4108                 rt2x00_set_field32(&reg, COEX_CFG_ANT, 0x5e);
4109                 rt2800_register_write(rt2x00dev, COEX_CFG0, reg);
4110
4111                 rt2800_register_read(rt2x00dev, COEX_CFG2, &reg);
4112                 rt2x00_set_field32(&reg, BT_COEX_CFG1, 0x00);
4113                 rt2x00_set_field32(&reg, BT_COEX_CFG0, 0x17);
4114                 rt2x00_set_field32(&reg, WL_COEX_CFG1, 0x93);
4115                 rt2x00_set_field32(&reg, WL_COEX_CFG0, 0x7f);
4116                 rt2800_register_write(rt2x00dev, COEX_CFG2, reg);
4117
4118                 rt2800_register_read(rt2x00dev, PLL_CTRL, &reg);
4119                 rt2x00_set_field32(&reg, PLL_CONTROL, 1);
4120                 rt2800_register_write(rt2x00dev, PLL_CTRL, reg);
4121         }
4122
4123         if (rt2x00_rt(rt2x00dev, RT3071) ||
4124             rt2x00_rt(rt2x00dev, RT3090) ||
4125             rt2x00_rt(rt2x00dev, RT3290) ||
4126             rt2x00_rt(rt2x00dev, RT3390)) {
4127
4128                 if (rt2x00_rt(rt2x00dev, RT3290))
4129                         rt2800_register_write(rt2x00dev, TX_SW_CFG0,
4130                                               0x00000404);
4131                 else
4132                         rt2800_register_write(rt2x00dev, TX_SW_CFG0,
4133                                               0x00000400);
4134
4135                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
4136                 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
4137                     rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
4138                     rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) {
4139                         rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1,
4140                                            &eeprom);
4141                         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_DAC_TEST))
4142                                 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
4143                                                       0x0000002c);
4144                         else
4145                                 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
4146                                                       0x0000000f);
4147                 } else {
4148                         rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
4149                 }
4150         } else if (rt2x00_rt(rt2x00dev, RT3070)) {
4151                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
4152
4153                 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) {
4154                         rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
4155                         rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x0000002c);
4156                 } else {
4157                         rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
4158                         rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
4159                 }
4160         } else if (rt2800_is_305x_soc(rt2x00dev)) {
4161                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
4162                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
4163                 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000030);
4164         } else if (rt2x00_rt(rt2x00dev, RT3352)) {
4165                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000402);
4166                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
4167                 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
4168         } else if (rt2x00_rt(rt2x00dev, RT3572)) {
4169                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
4170                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
4171         } else if (rt2x00_rt(rt2x00dev, RT3593)) {
4172                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000402);
4173                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
4174                 if (rt2x00_rt_rev_lt(rt2x00dev, RT3593, REV_RT3593E)) {
4175                         rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1,
4176                                            &eeprom);
4177                         if (rt2x00_get_field16(eeprom,
4178                                                EEPROM_NIC_CONF1_DAC_TEST))
4179                                 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
4180                                                       0x0000001f);
4181                         else
4182                                 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
4183                                                       0x0000000f);
4184                 } else {
4185                         rt2800_register_write(rt2x00dev, TX_SW_CFG2,
4186                                               0x00000000);
4187                 }
4188         } else if (rt2x00_rt(rt2x00dev, RT5390) ||
4189                    rt2x00_rt(rt2x00dev, RT5392) ||
4190                    rt2x00_rt(rt2x00dev, RT5592)) {
4191                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000404);
4192                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
4193                 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
4194         } else {
4195                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000000);
4196                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
4197         }
4198
4199         rt2800_register_read(rt2x00dev, TX_LINK_CFG, &reg);
4200         rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB_LIFETIME, 32);
4201         rt2x00_set_field32(&reg, TX_LINK_CFG_MFB_ENABLE, 0);
4202         rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_UMFS_ENABLE, 0);
4203         rt2x00_set_field32(&reg, TX_LINK_CFG_TX_MRQ_EN, 0);
4204         rt2x00_set_field32(&reg, TX_LINK_CFG_TX_RDG_EN, 0);
4205         rt2x00_set_field32(&reg, TX_LINK_CFG_TX_CF_ACK_EN, 1);
4206         rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB, 0);
4207         rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFS, 0);
4208         rt2800_register_write(rt2x00dev, TX_LINK_CFG, reg);
4209
4210         rt2800_register_read(rt2x00dev, TX_TIMEOUT_CFG, &reg);
4211         rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_MPDU_LIFETIME, 9);
4212         rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_RX_ACK_TIMEOUT, 32);
4213         rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_TX_OP_TIMEOUT, 10);
4214         rt2800_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg);
4215
4216         rt2800_register_read(rt2x00dev, MAX_LEN_CFG, &reg);
4217         rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_MPDU, AGGREGATION_SIZE);
4218         if (rt2x00_rt_rev_gte(rt2x00dev, RT2872, REV_RT2872E) ||
4219             rt2x00_rt(rt2x00dev, RT2883) ||
4220             rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070E))
4221                 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 2);
4222         else
4223                 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 1);
4224         rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_PSDU, 0);
4225         rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_MPDU, 0);
4226         rt2800_register_write(rt2x00dev, MAX_LEN_CFG, reg);
4227
4228         rt2800_register_read(rt2x00dev, LED_CFG, &reg);
4229         rt2x00_set_field32(&reg, LED_CFG_ON_PERIOD, 70);
4230         rt2x00_set_field32(&reg, LED_CFG_OFF_PERIOD, 30);
4231         rt2x00_set_field32(&reg, LED_CFG_SLOW_BLINK_PERIOD, 3);
4232         rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE, 3);
4233         rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE, 3);
4234         rt2x00_set_field32(&reg, LED_CFG_Y_LED_MODE, 3);
4235         rt2x00_set_field32(&reg, LED_CFG_LED_POLAR, 1);
4236         rt2800_register_write(rt2x00dev, LED_CFG, reg);
4237
4238         rt2800_register_write(rt2x00dev, PBF_MAX_PCNT, 0x1f3fbf9f);
4239
4240         rt2800_register_read(rt2x00dev, TX_RTY_CFG, &reg);
4241         rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT, 15);
4242         rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT, 31);
4243         rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_THRE, 2000);
4244         rt2x00_set_field32(&reg, TX_RTY_CFG_NON_AGG_RTY_MODE, 0);
4245         rt2x00_set_field32(&reg, TX_RTY_CFG_AGG_RTY_MODE, 0);
4246         rt2x00_set_field32(&reg, TX_RTY_CFG_TX_AUTO_FB_ENABLE, 1);
4247         rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
4248
4249         rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
4250         rt2x00_set_field32(&reg, AUTO_RSP_CFG_AUTORESPONDER, 1);
4251         rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY, 1);
4252         rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MMODE, 0);
4253         rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MREF, 0);
4254         rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE, 1);
4255         rt2x00_set_field32(&reg, AUTO_RSP_CFG_DUAL_CTS_EN, 0);
4256         rt2x00_set_field32(&reg, AUTO_RSP_CFG_ACK_CTS_PSM_BIT, 0);
4257         rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
4258
4259         rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
4260         rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_RATE, 3);
4261         rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_CTRL, 0);
4262         rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_NAV_SHORT, 1);
4263         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_CCK, 1);
4264         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
4265         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM20, 1);
4266         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM40, 0);
4267         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF20, 1);
4268         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF40, 0);
4269         rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, 1);
4270         rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
4271
4272         rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
4273         rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_RATE, 3);
4274         rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL, 0);
4275         rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_NAV_SHORT, 1);
4276         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_CCK, 1);
4277         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
4278         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM20, 1);
4279         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM40, 0);
4280         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF20, 1);
4281         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF40, 0);
4282         rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, 1);
4283         rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
4284
4285         rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
4286         rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, 0x4004);
4287         rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, 0);
4288         rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_NAV_SHORT, 1);
4289         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
4290         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
4291         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
4292         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
4293         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
4294         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
4295         rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, 0);
4296         rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
4297
4298         rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
4299         rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, 0x4084);
4300         rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL, 0);
4301         rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_NAV_SHORT, 1);
4302         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
4303         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
4304         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
4305         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
4306         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
4307         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
4308         rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, 0);
4309         rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
4310
4311         rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
4312         rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, 0x4004);
4313         rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, 0);
4314         rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_NAV_SHORT, 1);
4315         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
4316         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
4317         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
4318         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
4319         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
4320         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
4321         rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, 0);
4322         rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
4323
4324         rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
4325         rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, 0x4084);
4326         rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, 0);
4327         rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_NAV_SHORT, 1);
4328         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
4329         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
4330         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
4331         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
4332         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
4333         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
4334         rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, 0);
4335         rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
4336
4337         if (rt2x00_is_usb(rt2x00dev)) {
4338                 rt2800_register_write(rt2x00dev, PBF_CFG, 0xf40006);
4339
4340                 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
4341                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
4342                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
4343                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
4344                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
4345                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 3);
4346                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 0);
4347                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_BIG_ENDIAN, 0);
4348                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_HDR_SCATTER, 0);
4349                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_HDR_SEG_LEN, 0);
4350                 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
4351         }
4352
4353         /*
4354          * The legacy driver also sets TXOP_CTRL_CFG_RESERVED_TRUN_EN to 1
4355          * although it is reserved.
4356          */
4357         rt2800_register_read(rt2x00dev, TXOP_CTRL_CFG, &reg);
4358         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_TIMEOUT_TRUN_EN, 1);
4359         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_AC_TRUN_EN, 1);
4360         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_TXRATEGRP_TRUN_EN, 1);
4361         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_USER_MODE_TRUN_EN, 1);
4362         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_MIMO_PS_TRUN_EN, 1);
4363         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_RESERVED_TRUN_EN, 1);
4364         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_LSIG_TXOP_EN, 0);
4365         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_EXT_CCA_EN, 0);
4366         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_EXT_CCA_DLY, 88);
4367         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_EXT_CWMIN, 0);
4368         rt2800_register_write(rt2x00dev, TXOP_CTRL_CFG, reg);
4369
4370         reg = rt2x00_rt(rt2x00dev, RT5592) ? 0x00000082 : 0x00000002;
4371         rt2800_register_write(rt2x00dev, TXOP_HLDR_ET, reg);
4372
4373         rt2800_register_read(rt2x00dev, TX_RTS_CFG, &reg);
4374         rt2x00_set_field32(&reg, TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT, 32);
4375         rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES,
4376                            IEEE80211_MAX_RTS_THRESHOLD);
4377         rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_FBK_EN, 0);
4378         rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
4379
4380         rt2800_register_write(rt2x00dev, EXP_ACK_TIME, 0x002400ca);
4381
4382         /*
4383          * Usually the CCK SIFS time should be set to 10 and the OFDM SIFS
4384          * time should be set to 16. However, the original Ralink driver uses
4385          * 16 for both and indeed using a value of 10 for CCK SIFS results in
4386          * connection problems with 11g + CTS protection. Hence, use the same
4387          * defaults as the Ralink driver: 16 for both, CCK and OFDM SIFS.
4388          */
4389         rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
4390         rt2x00_set_field32(&reg, XIFS_TIME_CFG_CCKM_SIFS_TIME, 16);
4391         rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_SIFS_TIME, 16);
4392         rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_XIFS_TIME, 4);
4393         rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, 314);
4394         rt2x00_set_field32(&reg, XIFS_TIME_CFG_BB_RXEND_ENABLE, 1);
4395         rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
4396
4397         rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
4398
4399         /*
4400          * ASIC will keep garbage value after boot, clear encryption keys.
4401          */
4402         for (i = 0; i < 4; i++)
4403                 rt2800_register_write(rt2x00dev,
4404                                          SHARED_KEY_MODE_ENTRY(i), 0);
4405
4406         for (i = 0; i < 256; i++) {
4407                 rt2800_config_wcid(rt2x00dev, NULL, i);
4408                 rt2800_delete_wcid_attr(rt2x00dev, i);
4409                 rt2800_register_write(rt2x00dev, MAC_IVEIV_ENTRY(i), 0);
4410         }
4411
4412         /*
4413          * Clear all beacons
4414          */
4415         rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE0);
4416         rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE1);
4417         rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE2);
4418         rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE3);
4419         rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE4);
4420         rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE5);
4421         rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE6);
4422         rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE7);
4423
4424         if (rt2x00_is_usb(rt2x00dev)) {
4425                 rt2800_register_read(rt2x00dev, US_CYC_CNT, &reg);
4426                 rt2x00_set_field32(&reg, US_CYC_CNT_CLOCK_CYCLE, 30);
4427                 rt2800_register_write(rt2x00dev, US_CYC_CNT, reg);
4428         } else if (rt2x00_is_pcie(rt2x00dev)) {
4429                 rt2800_register_read(rt2x00dev, US_CYC_CNT, &reg);
4430                 rt2x00_set_field32(&reg, US_CYC_CNT_CLOCK_CYCLE, 125);
4431                 rt2800_register_write(rt2x00dev, US_CYC_CNT, reg);
4432         }
4433
4434         rt2800_register_read(rt2x00dev, HT_FBK_CFG0, &reg);
4435         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS0FBK, 0);
4436         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS1FBK, 0);
4437         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS2FBK, 1);
4438         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS3FBK, 2);
4439         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS4FBK, 3);
4440         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS5FBK, 4);
4441         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS6FBK, 5);
4442         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS7FBK, 6);
4443         rt2800_register_write(rt2x00dev, HT_FBK_CFG0, reg);
4444
4445         rt2800_register_read(rt2x00dev, HT_FBK_CFG1, &reg);
4446         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS8FBK, 8);
4447         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS9FBK, 8);
4448         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS10FBK, 9);
4449         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS11FBK, 10);
4450         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS12FBK, 11);
4451         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS13FBK, 12);
4452         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS14FBK, 13);
4453         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS15FBK, 14);
4454         rt2800_register_write(rt2x00dev, HT_FBK_CFG1, reg);
4455
4456         rt2800_register_read(rt2x00dev, LG_FBK_CFG0, &reg);
4457         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS0FBK, 8);
4458         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS1FBK, 8);
4459         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS2FBK, 9);
4460         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS3FBK, 10);
4461         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS4FBK, 11);
4462         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS5FBK, 12);
4463         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS6FBK, 13);
4464         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS7FBK, 14);
4465         rt2800_register_write(rt2x00dev, LG_FBK_CFG0, reg);
4466
4467         rt2800_register_read(rt2x00dev, LG_FBK_CFG1, &reg);
4468         rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS0FBK, 0);
4469         rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS1FBK, 0);
4470         rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS2FBK, 1);
4471         rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS3FBK, 2);
4472         rt2800_register_write(rt2x00dev, LG_FBK_CFG1, reg);
4473
4474         /*
4475          * Do not force the BA window size, we use the TXWI to set it
4476          */
4477         rt2800_register_read(rt2x00dev, AMPDU_BA_WINSIZE, &reg);
4478         rt2x00_set_field32(&reg, AMPDU_BA_WINSIZE_FORCE_WINSIZE_ENABLE, 0);
4479         rt2x00_set_field32(&reg, AMPDU_BA_WINSIZE_FORCE_WINSIZE, 0);
4480         rt2800_register_write(rt2x00dev, AMPDU_BA_WINSIZE, reg);
4481
4482         /*
4483          * We must clear the error counters.
4484          * These registers are cleared on read,
4485          * so we may pass a useless variable to store the value.
4486          */
4487         rt2800_register_read(rt2x00dev, RX_STA_CNT0, &reg);
4488         rt2800_register_read(rt2x00dev, RX_STA_CNT1, &reg);
4489         rt2800_register_read(rt2x00dev, RX_STA_CNT2, &reg);
4490         rt2800_register_read(rt2x00dev, TX_STA_CNT0, &reg);
4491         rt2800_register_read(rt2x00dev, TX_STA_CNT1, &reg);
4492         rt2800_register_read(rt2x00dev, TX_STA_CNT2, &reg);
4493
4494         /*
4495          * Setup leadtime for pre tbtt interrupt to 6ms
4496          */
4497         rt2800_register_read(rt2x00dev, INT_TIMER_CFG, &reg);
4498         rt2x00_set_field32(&reg, INT_TIMER_CFG_PRE_TBTT_TIMER, 6 << 4);
4499         rt2800_register_write(rt2x00dev, INT_TIMER_CFG, reg);
4500
4501         /*
4502          * Set up channel statistics timer
4503          */
4504         rt2800_register_read(rt2x00dev, CH_TIME_CFG, &reg);
4505         rt2x00_set_field32(&reg, CH_TIME_CFG_EIFS_BUSY, 1);
4506         rt2x00_set_field32(&reg, CH_TIME_CFG_NAV_BUSY, 1);
4507         rt2x00_set_field32(&reg, CH_TIME_CFG_RX_BUSY, 1);
4508         rt2x00_set_field32(&reg, CH_TIME_CFG_TX_BUSY, 1);
4509         rt2x00_set_field32(&reg, CH_TIME_CFG_TMR_EN, 1);
4510         rt2800_register_write(rt2x00dev, CH_TIME_CFG, reg);
4511
4512         return 0;
4513 }
4514
4515 static int rt2800_wait_bbp_rf_ready(struct rt2x00_dev *rt2x00dev)
4516 {
4517         unsigned int i;
4518         u32 reg;
4519
4520         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
4521                 rt2800_register_read(rt2x00dev, MAC_STATUS_CFG, &reg);
4522                 if (!rt2x00_get_field32(reg, MAC_STATUS_CFG_BBP_RF_BUSY))
4523                         return 0;
4524
4525                 udelay(REGISTER_BUSY_DELAY);
4526         }
4527
4528         rt2x00_err(rt2x00dev, "BBP/RF register access failed, aborting\n");
4529         return -EACCES;
4530 }
4531
4532 static int rt2800_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
4533 {
4534         unsigned int i;
4535         u8 value;
4536
4537         /*
4538          * BBP was enabled after firmware was loaded,
4539          * but we need to reactivate it now.
4540          */
4541         rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
4542         rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
4543         msleep(1);
4544
4545         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
4546                 rt2800_bbp_read(rt2x00dev, 0, &value);
4547                 if ((value != 0xff) && (value != 0x00))
4548                         return 0;
4549                 udelay(REGISTER_BUSY_DELAY);
4550         }
4551
4552         rt2x00_err(rt2x00dev, "BBP register access failed, aborting\n");
4553         return -EACCES;
4554 }
4555
4556 static void rt2800_bbp4_mac_if_ctrl(struct rt2x00_dev *rt2x00dev)
4557 {
4558         u8 value;
4559
4560         rt2800_bbp_read(rt2x00dev, 4, &value);
4561         rt2x00_set_field8(&value, BBP4_MAC_IF_CTRL, 1);
4562         rt2800_bbp_write(rt2x00dev, 4, value);
4563 }
4564
4565 static void rt2800_init_freq_calibration(struct rt2x00_dev *rt2x00dev)
4566 {
4567         rt2800_bbp_write(rt2x00dev, 142, 1);
4568         rt2800_bbp_write(rt2x00dev, 143, 57);
4569 }
4570
4571 static void rt2800_init_bbp_5592_glrt(struct rt2x00_dev *rt2x00dev)
4572 {
4573         const u8 glrt_table[] = {
4574                 0xE0, 0x1F, 0X38, 0x32, 0x08, 0x28, 0x19, 0x0A, 0xFF, 0x00, /* 128 ~ 137 */
4575                 0x16, 0x10, 0x10, 0x0B, 0x36, 0x2C, 0x26, 0x24, 0x42, 0x36, /* 138 ~ 147 */
4576                 0x30, 0x2D, 0x4C, 0x46, 0x3D, 0x40, 0x3E, 0x42, 0x3D, 0x40, /* 148 ~ 157 */
4577                 0X3C, 0x34, 0x2C, 0x2F, 0x3C, 0x35, 0x2E, 0x2A, 0x49, 0x41, /* 158 ~ 167 */
4578                 0x36, 0x31, 0x30, 0x30, 0x0E, 0x0D, 0x28, 0x21, 0x1C, 0x16, /* 168 ~ 177 */
4579                 0x50, 0x4A, 0x43, 0x40, 0x10, 0x10, 0x10, 0x10, 0x00, 0x00, /* 178 ~ 187 */
4580                 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 188 ~ 197 */
4581                 0x00, 0x00, 0x7D, 0x14, 0x32, 0x2C, 0x36, 0x4C, 0x43, 0x2C, /* 198 ~ 207 */
4582                 0x2E, 0x36, 0x30, 0x6E,                                     /* 208 ~ 211 */
4583         };
4584         int i;
4585
4586         for (i = 0; i < ARRAY_SIZE(glrt_table); i++) {
4587                 rt2800_bbp_write(rt2x00dev, 195, 128 + i);
4588                 rt2800_bbp_write(rt2x00dev, 196, glrt_table[i]);
4589         }
4590 };
4591
4592 static void rt2800_init_bbp_early(struct rt2x00_dev *rt2x00dev)
4593 {
4594         rt2800_bbp_write(rt2x00dev, 65, 0x2C);
4595         rt2800_bbp_write(rt2x00dev, 66, 0x38);
4596         rt2800_bbp_write(rt2x00dev, 68, 0x0B);
4597         rt2800_bbp_write(rt2x00dev, 69, 0x12);
4598         rt2800_bbp_write(rt2x00dev, 70, 0x0a);
4599         rt2800_bbp_write(rt2x00dev, 73, 0x10);
4600         rt2800_bbp_write(rt2x00dev, 81, 0x37);
4601         rt2800_bbp_write(rt2x00dev, 82, 0x62);
4602         rt2800_bbp_write(rt2x00dev, 83, 0x6A);
4603         rt2800_bbp_write(rt2x00dev, 84, 0x99);
4604         rt2800_bbp_write(rt2x00dev, 86, 0x00);
4605         rt2800_bbp_write(rt2x00dev, 91, 0x04);
4606         rt2800_bbp_write(rt2x00dev, 92, 0x00);
4607         rt2800_bbp_write(rt2x00dev, 103, 0x00);
4608         rt2800_bbp_write(rt2x00dev, 105, 0x05);
4609         rt2800_bbp_write(rt2x00dev, 106, 0x35);
4610 }
4611
4612 static void rt2800_disable_unused_dac_adc(struct rt2x00_dev *rt2x00dev)
4613 {
4614         u16 eeprom;
4615         u8 value;
4616
4617         rt2800_bbp_read(rt2x00dev, 138, &value);
4618         rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
4619         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1)
4620                 value |= 0x20;
4621         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1)
4622                 value &= ~0x02;
4623         rt2800_bbp_write(rt2x00dev, 138, value);
4624 }
4625
4626 static void rt2800_init_bbp_305x_soc(struct rt2x00_dev *rt2x00dev)
4627 {
4628         rt2800_bbp_write(rt2x00dev, 31, 0x08);
4629
4630         rt2800_bbp_write(rt2x00dev, 65, 0x2c);
4631         rt2800_bbp_write(rt2x00dev, 66, 0x38);
4632
4633         rt2800_bbp_write(rt2x00dev, 69, 0x12);
4634         rt2800_bbp_write(rt2x00dev, 73, 0x10);
4635
4636         rt2800_bbp_write(rt2x00dev, 70, 0x0a);
4637
4638         rt2800_bbp_write(rt2x00dev, 78, 0x0e);
4639         rt2800_bbp_write(rt2x00dev, 80, 0x08);
4640
4641         rt2800_bbp_write(rt2x00dev, 82, 0x62);
4642
4643         rt2800_bbp_write(rt2x00dev, 83, 0x6a);
4644
4645         rt2800_bbp_write(rt2x00dev, 84, 0x99);
4646
4647         rt2800_bbp_write(rt2x00dev, 86, 0x00);
4648
4649         rt2800_bbp_write(rt2x00dev, 91, 0x04);
4650
4651         rt2800_bbp_write(rt2x00dev, 92, 0x00);
4652
4653         rt2800_bbp_write(rt2x00dev, 103, 0xc0);
4654
4655         rt2800_bbp_write(rt2x00dev, 105, 0x01);
4656
4657         rt2800_bbp_write(rt2x00dev, 106, 0x35);
4658 }
4659
4660 static void rt2800_init_bbp_28xx(struct rt2x00_dev *rt2x00dev)
4661 {
4662         rt2800_bbp_write(rt2x00dev, 65, 0x2c);
4663         rt2800_bbp_write(rt2x00dev, 66, 0x38);
4664
4665         if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) {
4666                 rt2800_bbp_write(rt2x00dev, 69, 0x16);
4667                 rt2800_bbp_write(rt2x00dev, 73, 0x12);
4668         } else {
4669                 rt2800_bbp_write(rt2x00dev, 69, 0x12);
4670                 rt2800_bbp_write(rt2x00dev, 73, 0x10);
4671         }
4672
4673         rt2800_bbp_write(rt2x00dev, 70, 0x0a);
4674
4675         rt2800_bbp_write(rt2x00dev, 81, 0x37);
4676
4677         rt2800_bbp_write(rt2x00dev, 82, 0x62);
4678
4679         rt2800_bbp_write(rt2x00dev, 83, 0x6a);
4680
4681         if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860D))
4682                 rt2800_bbp_write(rt2x00dev, 84, 0x19);
4683         else
4684                 rt2800_bbp_write(rt2x00dev, 84, 0x99);
4685
4686         rt2800_bbp_write(rt2x00dev, 86, 0x00);
4687
4688         rt2800_bbp_write(rt2x00dev, 91, 0x04);
4689
4690         rt2800_bbp_write(rt2x00dev, 92, 0x00);
4691
4692         rt2800_bbp_write(rt2x00dev, 103, 0x00);
4693
4694         rt2800_bbp_write(rt2x00dev, 105, 0x05);
4695
4696         rt2800_bbp_write(rt2x00dev, 106, 0x35);
4697 }
4698
4699 static void rt2800_init_bbp_30xx(struct rt2x00_dev *rt2x00dev)
4700 {
4701         rt2800_bbp_write(rt2x00dev, 65, 0x2c);
4702         rt2800_bbp_write(rt2x00dev, 66, 0x38);
4703
4704         rt2800_bbp_write(rt2x00dev, 69, 0x12);
4705         rt2800_bbp_write(rt2x00dev, 73, 0x10);
4706
4707         rt2800_bbp_write(rt2x00dev, 70, 0x0a);
4708
4709         rt2800_bbp_write(rt2x00dev, 79, 0x13);
4710         rt2800_bbp_write(rt2x00dev, 80, 0x05);
4711         rt2800_bbp_write(rt2x00dev, 81, 0x33);
4712
4713         rt2800_bbp_write(rt2x00dev, 82, 0x62);
4714
4715         rt2800_bbp_write(rt2x00dev, 83, 0x6a);
4716
4717         rt2800_bbp_write(rt2x00dev, 84, 0x99);
4718
4719         rt2800_bbp_write(rt2x00dev, 86, 0x00);
4720
4721         rt2800_bbp_write(rt2x00dev, 91, 0x04);
4722
4723         rt2800_bbp_write(rt2x00dev, 92, 0x00);
4724
4725         if (rt2x00_rt_rev_gte(rt2x00dev, RT3070, REV_RT3070F) ||
4726             rt2x00_rt_rev_gte(rt2x00dev, RT3071, REV_RT3071E) ||
4727             rt2x00_rt_rev_gte(rt2x00dev, RT3090, REV_RT3090E))
4728                 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
4729         else
4730                 rt2800_bbp_write(rt2x00dev, 103, 0x00);
4731
4732         rt2800_bbp_write(rt2x00dev, 105, 0x05);
4733
4734         rt2800_bbp_write(rt2x00dev, 106, 0x35);
4735
4736         if (rt2x00_rt(rt2x00dev, RT3071) ||
4737             rt2x00_rt(rt2x00dev, RT3090))
4738                 rt2800_disable_unused_dac_adc(rt2x00dev);
4739 }
4740
4741 static void rt2800_init_bbp_3290(struct rt2x00_dev *rt2x00dev)
4742 {
4743         u8 value;
4744
4745         rt2800_bbp4_mac_if_ctrl(rt2x00dev);
4746
4747         rt2800_bbp_write(rt2x00dev, 31, 0x08);
4748
4749         rt2800_bbp_write(rt2x00dev, 65, 0x2c);
4750         rt2800_bbp_write(rt2x00dev, 66, 0x38);
4751
4752         rt2800_bbp_write(rt2x00dev, 68, 0x0b);
4753
4754         rt2800_bbp_write(rt2x00dev, 69, 0x12);
4755         rt2800_bbp_write(rt2x00dev, 73, 0x13);
4756         rt2800_bbp_write(rt2x00dev, 75, 0x46);
4757         rt2800_bbp_write(rt2x00dev, 76, 0x28);
4758
4759         rt2800_bbp_write(rt2x00dev, 77, 0x58);
4760
4761         rt2800_bbp_write(rt2x00dev, 70, 0x0a);
4762
4763         rt2800_bbp_write(rt2x00dev, 74, 0x0b);
4764         rt2800_bbp_write(rt2x00dev, 79, 0x18);
4765         rt2800_bbp_write(rt2x00dev, 80, 0x09);
4766         rt2800_bbp_write(rt2x00dev, 81, 0x33);
4767
4768         rt2800_bbp_write(rt2x00dev, 82, 0x62);
4769
4770         rt2800_bbp_write(rt2x00dev, 83, 0x7a);
4771
4772         rt2800_bbp_write(rt2x00dev, 84, 0x9a);
4773
4774         rt2800_bbp_write(rt2x00dev, 86, 0x38);
4775
4776         rt2800_bbp_write(rt2x00dev, 91, 0x04);
4777
4778         rt2800_bbp_write(rt2x00dev, 92, 0x02);
4779
4780         rt2800_bbp_write(rt2x00dev, 103, 0xc0);
4781
4782         rt2800_bbp_write(rt2x00dev, 104, 0x92);
4783
4784         rt2800_bbp_write(rt2x00dev, 105, 0x1c);
4785
4786         rt2800_bbp_write(rt2x00dev, 106, 0x03);
4787
4788         rt2800_bbp_write(rt2x00dev, 128, 0x12);
4789
4790         rt2800_bbp_write(rt2x00dev, 67, 0x24);
4791         rt2800_bbp_write(rt2x00dev, 143, 0x04);
4792         rt2800_bbp_write(rt2x00dev, 142, 0x99);
4793         rt2800_bbp_write(rt2x00dev, 150, 0x30);
4794         rt2800_bbp_write(rt2x00dev, 151, 0x2e);
4795         rt2800_bbp_write(rt2x00dev, 152, 0x20);
4796         rt2800_bbp_write(rt2x00dev, 153, 0x34);
4797         rt2800_bbp_write(rt2x00dev, 154, 0x40);
4798         rt2800_bbp_write(rt2x00dev, 155, 0x3b);
4799         rt2800_bbp_write(rt2x00dev, 253, 0x04);
4800
4801         rt2800_bbp_read(rt2x00dev, 47, &value);
4802         rt2x00_set_field8(&value, BBP47_TSSI_ADC6, 1);
4803         rt2800_bbp_write(rt2x00dev, 47, value);
4804
4805         /* Use 5-bit ADC for Acquisition and 8-bit ADC for data */
4806         rt2800_bbp_read(rt2x00dev, 3, &value);
4807         rt2x00_set_field8(&value, BBP3_ADC_MODE_SWITCH, 1);
4808         rt2x00_set_field8(&value, BBP3_ADC_INIT_MODE, 1);
4809         rt2800_bbp_write(rt2x00dev, 3, value);
4810 }
4811
4812 static void rt2800_init_bbp_3352(struct rt2x00_dev *rt2x00dev)
4813 {
4814         rt2800_bbp_write(rt2x00dev, 3, 0x00);
4815         rt2800_bbp_write(rt2x00dev, 4, 0x50);
4816
4817         rt2800_bbp_write(rt2x00dev, 31, 0x08);
4818
4819         rt2800_bbp_write(rt2x00dev, 47, 0x48);
4820
4821         rt2800_bbp_write(rt2x00dev, 65, 0x2c);
4822         rt2800_bbp_write(rt2x00dev, 66, 0x38);
4823
4824         rt2800_bbp_write(rt2x00dev, 68, 0x0b);
4825
4826         rt2800_bbp_write(rt2x00dev, 69, 0x12);
4827         rt2800_bbp_write(rt2x00dev, 73, 0x13);
4828         rt2800_bbp_write(rt2x00dev, 75, 0x46);
4829         rt2800_bbp_write(rt2x00dev, 76, 0x28);
4830
4831         rt2800_bbp_write(rt2x00dev, 77, 0x59);
4832
4833         rt2800_bbp_write(rt2x00dev, 70, 0x0a);
4834
4835         rt2800_bbp_write(rt2x00dev, 78, 0x0e);
4836         rt2800_bbp_write(rt2x00dev, 80, 0x08);
4837         rt2800_bbp_write(rt2x00dev, 81, 0x37);
4838
4839         rt2800_bbp_write(rt2x00dev, 82, 0x62);
4840
4841         rt2800_bbp_write(rt2x00dev, 83, 0x6a);
4842
4843         rt2800_bbp_write(rt2x00dev, 84, 0x99);
4844
4845         rt2800_bbp_write(rt2x00dev, 86, 0x38);
4846
4847         rt2800_bbp_write(rt2x00dev, 88, 0x90);
4848
4849         rt2800_bbp_write(rt2x00dev, 91, 0x04);
4850
4851         rt2800_bbp_write(rt2x00dev, 92, 0x02);
4852
4853         rt2800_bbp_write(rt2x00dev, 103, 0xc0);
4854
4855         rt2800_bbp_write(rt2x00dev, 104, 0x92);
4856
4857         rt2800_bbp_write(rt2x00dev, 105, 0x34);
4858
4859         rt2800_bbp_write(rt2x00dev, 106, 0x05);
4860
4861         rt2800_bbp_write(rt2x00dev, 120, 0x50);
4862
4863         rt2800_bbp_write(rt2x00dev, 137, 0x0f);
4864
4865         rt2800_bbp_write(rt2x00dev, 163, 0xbd);
4866         /* Set ITxBF timeout to 0x9c40=1000msec */
4867         rt2800_bbp_write(rt2x00dev, 179, 0x02);
4868         rt2800_bbp_write(rt2x00dev, 180, 0x00);
4869         rt2800_bbp_write(rt2x00dev, 182, 0x40);
4870         rt2800_bbp_write(rt2x00dev, 180, 0x01);
4871         rt2800_bbp_write(rt2x00dev, 182, 0x9c);
4872         rt2800_bbp_write(rt2x00dev, 179, 0x00);
4873         /* Reprogram the inband interface to put right values in RXWI */
4874         rt2800_bbp_write(rt2x00dev, 142, 0x04);
4875         rt2800_bbp_write(rt2x00dev, 143, 0x3b);
4876         rt2800_bbp_write(rt2x00dev, 142, 0x06);
4877         rt2800_bbp_write(rt2x00dev, 143, 0xa0);
4878         rt2800_bbp_write(rt2x00dev, 142, 0x07);
4879         rt2800_bbp_write(rt2x00dev, 143, 0xa1);
4880         rt2800_bbp_write(rt2x00dev, 142, 0x08);
4881         rt2800_bbp_write(rt2x00dev, 143, 0xa2);
4882
4883         rt2800_bbp_write(rt2x00dev, 148, 0xc8);
4884 }
4885
4886 static void rt2800_init_bbp_3390(struct rt2x00_dev *rt2x00dev)
4887 {
4888         rt2800_bbp_write(rt2x00dev, 65, 0x2c);
4889         rt2800_bbp_write(rt2x00dev, 66, 0x38);
4890
4891         rt2800_bbp_write(rt2x00dev, 69, 0x12);
4892         rt2800_bbp_write(rt2x00dev, 73, 0x10);
4893
4894         rt2800_bbp_write(rt2x00dev, 70, 0x0a);
4895
4896         rt2800_bbp_write(rt2x00dev, 79, 0x13);
4897         rt2800_bbp_write(rt2x00dev, 80, 0x05);
4898         rt2800_bbp_write(rt2x00dev, 81, 0x33);
4899
4900         rt2800_bbp_write(rt2x00dev, 82, 0x62);
4901
4902         rt2800_bbp_write(rt2x00dev, 83, 0x6a);
4903
4904         rt2800_bbp_write(rt2x00dev, 84, 0x99);
4905
4906         rt2800_bbp_write(rt2x00dev, 86, 0x00);
4907
4908         rt2800_bbp_write(rt2x00dev, 91, 0x04);
4909
4910         rt2800_bbp_write(rt2x00dev, 92, 0x00);
4911
4912         if (rt2x00_rt_rev_gte(rt2x00dev, RT3390, REV_RT3390E))
4913                 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
4914         else
4915                 rt2800_bbp_write(rt2x00dev, 103, 0x00);
4916
4917         rt2800_bbp_write(rt2x00dev, 105, 0x05);
4918
4919         rt2800_bbp_write(rt2x00dev, 106, 0x35);
4920
4921         rt2800_disable_unused_dac_adc(rt2x00dev);
4922 }
4923
4924 static void rt2800_init_bbp_3572(struct rt2x00_dev *rt2x00dev)
4925 {
4926         rt2800_bbp_write(rt2x00dev, 31, 0x08);
4927
4928         rt2800_bbp_write(rt2x00dev, 65, 0x2c);
4929         rt2800_bbp_write(rt2x00dev, 66, 0x38);
4930
4931         rt2800_bbp_write(rt2x00dev, 69, 0x12);
4932         rt2800_bbp_write(rt2x00dev, 73, 0x10);
4933
4934         rt2800_bbp_write(rt2x00dev, 70, 0x0a);
4935
4936         rt2800_bbp_write(rt2x00dev, 79, 0x13);
4937         rt2800_bbp_write(rt2x00dev, 80, 0x05);
4938         rt2800_bbp_write(rt2x00dev, 81, 0x33);
4939
4940         rt2800_bbp_write(rt2x00dev, 82, 0x62);
4941
4942         rt2800_bbp_write(rt2x00dev, 83, 0x6a);
4943
4944         rt2800_bbp_write(rt2x00dev, 84, 0x99);
4945
4946         rt2800_bbp_write(rt2x00dev, 86, 0x00);
4947
4948         rt2800_bbp_write(rt2x00dev, 91, 0x04);
4949
4950         rt2800_bbp_write(rt2x00dev, 92, 0x00);
4951
4952         rt2800_bbp_write(rt2x00dev, 103, 0xc0);
4953
4954         rt2800_bbp_write(rt2x00dev, 105, 0x05);
4955
4956         rt2800_bbp_write(rt2x00dev, 106, 0x35);
4957
4958         rt2800_disable_unused_dac_adc(rt2x00dev);
4959 }
4960
4961 static void rt2800_init_bbp_3593(struct rt2x00_dev *rt2x00dev)
4962 {
4963         rt2800_init_bbp_early(rt2x00dev);
4964
4965         rt2800_bbp_write(rt2x00dev, 79, 0x13);
4966         rt2800_bbp_write(rt2x00dev, 80, 0x05);
4967         rt2800_bbp_write(rt2x00dev, 81, 0x33);
4968         rt2800_bbp_write(rt2x00dev, 137, 0x0f);
4969
4970         rt2800_bbp_write(rt2x00dev, 84, 0x19);
4971
4972         /* Enable DC filter */
4973         if (rt2x00_rt_rev_gte(rt2x00dev, RT3593, REV_RT3593E))
4974                 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
4975 }
4976
4977 static void rt2800_init_bbp_53xx(struct rt2x00_dev *rt2x00dev)
4978 {
4979         int ant, div_mode;
4980         u16 eeprom;
4981         u8 value;
4982
4983         rt2800_bbp4_mac_if_ctrl(rt2x00dev);
4984
4985         rt2800_bbp_write(rt2x00dev, 31, 0x08);
4986
4987         rt2800_bbp_write(rt2x00dev, 65, 0x2c);
4988         rt2800_bbp_write(rt2x00dev, 66, 0x38);
4989
4990         rt2800_bbp_write(rt2x00dev, 68, 0x0b);
4991
4992         rt2800_bbp_write(rt2x00dev, 69, 0x12);
4993         rt2800_bbp_write(rt2x00dev, 73, 0x13);
4994         rt2800_bbp_write(rt2x00dev, 75, 0x46);
4995         rt2800_bbp_write(rt2x00dev, 76, 0x28);
4996
4997         rt2800_bbp_write(rt2x00dev, 77, 0x59);
4998
4999         rt2800_bbp_write(rt2x00dev, 70, 0x0a);
5000
5001         rt2800_bbp_write(rt2x00dev, 79, 0x13);
5002         rt2800_bbp_write(rt2x00dev, 80, 0x05);
5003         rt2800_bbp_write(rt2x00dev, 81, 0x33);
5004
5005         rt2800_bbp_write(rt2x00dev, 82, 0x62);
5006
5007         rt2800_bbp_write(rt2x00dev, 83, 0x7a);
5008
5009         rt2800_bbp_write(rt2x00dev, 84, 0x9a);
5010
5011         rt2800_bbp_write(rt2x00dev, 86, 0x38);
5012
5013         if (rt2x00_rt(rt2x00dev, RT5392))
5014                 rt2800_bbp_write(rt2x00dev, 88, 0x90);
5015
5016         rt2800_bbp_write(rt2x00dev, 91, 0x04);
5017
5018         rt2800_bbp_write(rt2x00dev, 92, 0x02);
5019
5020         if (rt2x00_rt(rt2x00dev, RT5392)) {
5021                 rt2800_bbp_write(rt2x00dev, 95, 0x9a);
5022                 rt2800_bbp_write(rt2x00dev, 98, 0x12);
5023         }
5024
5025         rt2800_bbp_write(rt2x00dev, 103, 0xc0);
5026
5027         rt2800_bbp_write(rt2x00dev, 104, 0x92);
5028
5029         rt2800_bbp_write(rt2x00dev, 105, 0x3c);
5030
5031         if (rt2x00_rt(rt2x00dev, RT5390))
5032                 rt2800_bbp_write(rt2x00dev, 106, 0x03);
5033         else if (rt2x00_rt(rt2x00dev, RT5392))
5034                 rt2800_bbp_write(rt2x00dev, 106, 0x12);
5035         else
5036                 WARN_ON(1);
5037
5038         rt2800_bbp_write(rt2x00dev, 128, 0x12);
5039
5040         if (rt2x00_rt(rt2x00dev, RT5392)) {
5041                 rt2800_bbp_write(rt2x00dev, 134, 0xd0);
5042                 rt2800_bbp_write(rt2x00dev, 135, 0xf6);
5043         }
5044
5045         rt2800_disable_unused_dac_adc(rt2x00dev);
5046
5047         rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
5048         div_mode = rt2x00_get_field16(eeprom,
5049                                       EEPROM_NIC_CONF1_ANT_DIVERSITY);
5050         ant = (div_mode == 3) ? 1 : 0;
5051
5052         /* check if this is a Bluetooth combo card */
5053         if (test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags)) {
5054                 u32 reg;
5055
5056                 rt2800_register_read(rt2x00dev, GPIO_CTRL, &reg);
5057                 rt2x00_set_field32(&reg, GPIO_CTRL_DIR3, 0);
5058                 rt2x00_set_field32(&reg, GPIO_CTRL_DIR6, 0);
5059                 rt2x00_set_field32(&reg, GPIO_CTRL_VAL3, 0);
5060                 rt2x00_set_field32(&reg, GPIO_CTRL_VAL6, 0);
5061                 if (ant == 0)
5062                         rt2x00_set_field32(&reg, GPIO_CTRL_VAL3, 1);
5063                 else if (ant == 1)
5064                         rt2x00_set_field32(&reg, GPIO_CTRL_VAL6, 1);
5065                 rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
5066         }
5067
5068         /* This chip has hardware antenna diversity*/
5069         if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390R)) {
5070                 rt2800_bbp_write(rt2x00dev, 150, 0); /* Disable Antenna Software OFDM */
5071                 rt2800_bbp_write(rt2x00dev, 151, 0); /* Disable Antenna Software CCK */
5072                 rt2800_bbp_write(rt2x00dev, 154, 0); /* Clear previously selected antenna */
5073         }
5074
5075         rt2800_bbp_read(rt2x00dev, 152, &value);
5076         if (ant == 0)
5077                 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 1);
5078         else
5079                 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 0);
5080         rt2800_bbp_write(rt2x00dev, 152, value);
5081
5082         rt2800_init_freq_calibration(rt2x00dev);
5083 }
5084
5085 static void rt2800_init_bbp_5592(struct rt2x00_dev *rt2x00dev)
5086 {
5087         int ant, div_mode;
5088         u16 eeprom;
5089         u8 value;
5090
5091         rt2800_init_bbp_early(rt2x00dev);
5092
5093         rt2800_bbp_read(rt2x00dev, 105, &value);
5094         rt2x00_set_field8(&value, BBP105_MLD,
5095                           rt2x00dev->default_ant.rx_chain_num == 2);
5096         rt2800_bbp_write(rt2x00dev, 105, value);
5097
5098         rt2800_bbp4_mac_if_ctrl(rt2x00dev);
5099
5100         rt2800_bbp_write(rt2x00dev, 20, 0x06);
5101         rt2800_bbp_write(rt2x00dev, 31, 0x08);
5102         rt2800_bbp_write(rt2x00dev, 65, 0x2C);
5103         rt2800_bbp_write(rt2x00dev, 68, 0xDD);
5104         rt2800_bbp_write(rt2x00dev, 69, 0x1A);
5105         rt2800_bbp_write(rt2x00dev, 70, 0x05);
5106         rt2800_bbp_write(rt2x00dev, 73, 0x13);
5107         rt2800_bbp_write(rt2x00dev, 74, 0x0F);
5108         rt2800_bbp_write(rt2x00dev, 75, 0x4F);
5109         rt2800_bbp_write(rt2x00dev, 76, 0x28);
5110         rt2800_bbp_write(rt2x00dev, 77, 0x59);
5111         rt2800_bbp_write(rt2x00dev, 84, 0x9A);
5112         rt2800_bbp_write(rt2x00dev, 86, 0x38);
5113         rt2800_bbp_write(rt2x00dev, 88, 0x90);
5114         rt2800_bbp_write(rt2x00dev, 91, 0x04);
5115         rt2800_bbp_write(rt2x00dev, 92, 0x02);
5116         rt2800_bbp_write(rt2x00dev, 95, 0x9a);
5117         rt2800_bbp_write(rt2x00dev, 98, 0x12);
5118         rt2800_bbp_write(rt2x00dev, 103, 0xC0);
5119         rt2800_bbp_write(rt2x00dev, 104, 0x92);
5120         /* FIXME BBP105 owerwrite */
5121         rt2800_bbp_write(rt2x00dev, 105, 0x3C);
5122         rt2800_bbp_write(rt2x00dev, 106, 0x35);
5123         rt2800_bbp_write(rt2x00dev, 128, 0x12);
5124         rt2800_bbp_write(rt2x00dev, 134, 0xD0);
5125         rt2800_bbp_write(rt2x00dev, 135, 0xF6);
5126         rt2800_bbp_write(rt2x00dev, 137, 0x0F);
5127
5128         /* Initialize GLRT (Generalized Likehood Radio Test) */
5129         rt2800_init_bbp_5592_glrt(rt2x00dev);
5130
5131         rt2800_bbp4_mac_if_ctrl(rt2x00dev);
5132
5133         rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
5134         div_mode = rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_ANT_DIVERSITY);
5135         ant = (div_mode == 3) ? 1 : 0;
5136         rt2800_bbp_read(rt2x00dev, 152, &value);
5137         if (ant == 0) {
5138                 /* Main antenna */
5139                 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 1);
5140         } else {
5141                 /* Auxiliary antenna */
5142                 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 0);
5143         }
5144         rt2800_bbp_write(rt2x00dev, 152, value);
5145
5146         if (rt2x00_rt_rev_gte(rt2x00dev, RT5592, REV_RT5592C)) {
5147                 rt2800_bbp_read(rt2x00dev, 254, &value);
5148                 rt2x00_set_field8(&value, BBP254_BIT7, 1);
5149                 rt2800_bbp_write(rt2x00dev, 254, value);
5150         }
5151
5152         rt2800_init_freq_calibration(rt2x00dev);
5153
5154         rt2800_bbp_write(rt2x00dev, 84, 0x19);
5155         if (rt2x00_rt_rev_gte(rt2x00dev, RT5592, REV_RT5592C))
5156                 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
5157 }
5158
5159 static void rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
5160 {
5161         unsigned int i;
5162         u16 eeprom;
5163         u8 reg_id;
5164         u8 value;
5165
5166         if (rt2800_is_305x_soc(rt2x00dev))
5167                 rt2800_init_bbp_305x_soc(rt2x00dev);
5168
5169         switch (rt2x00dev->chip.rt) {
5170         case RT2860:
5171         case RT2872:
5172         case RT2883:
5173                 rt2800_init_bbp_28xx(rt2x00dev);
5174                 break;
5175         case RT3070:
5176         case RT3071:
5177         case RT3090:
5178                 rt2800_init_bbp_30xx(rt2x00dev);
5179                 break;
5180         case RT3290:
5181                 rt2800_init_bbp_3290(rt2x00dev);
5182                 break;
5183         case RT3352:
5184                 rt2800_init_bbp_3352(rt2x00dev);
5185                 break;
5186         case RT3390:
5187                 rt2800_init_bbp_3390(rt2x00dev);
5188                 break;
5189         case RT3572:
5190                 rt2800_init_bbp_3572(rt2x00dev);
5191                 break;
5192         case RT3593:
5193                 rt2800_init_bbp_3593(rt2x00dev);
5194                 return;
5195         case RT5390:
5196         case RT5392:
5197                 rt2800_init_bbp_53xx(rt2x00dev);
5198                 break;
5199         case RT5592:
5200                 rt2800_init_bbp_5592(rt2x00dev);
5201                 return;
5202         }
5203
5204         for (i = 0; i < EEPROM_BBP_SIZE; i++) {
5205                 rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_BBP_START, i,
5206                                               &eeprom);
5207
5208                 if (eeprom != 0xffff && eeprom != 0x0000) {
5209                         reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
5210                         value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
5211                         rt2800_bbp_write(rt2x00dev, reg_id, value);
5212                 }
5213         }
5214 }
5215
5216 static void rt2800_led_open_drain_enable(struct rt2x00_dev *rt2x00dev)
5217 {
5218         u32 reg;
5219
5220         rt2800_register_read(rt2x00dev, OPT_14_CSR, &reg);
5221         rt2x00_set_field32(&reg, OPT_14_CSR_BIT0, 1);
5222         rt2800_register_write(rt2x00dev, OPT_14_CSR, reg);
5223 }
5224
5225 static u8 rt2800_init_rx_filter(struct rt2x00_dev *rt2x00dev, bool bw40,
5226                                 u8 filter_target)
5227 {
5228         unsigned int i;
5229         u8 bbp;
5230         u8 rfcsr;
5231         u8 passband;
5232         u8 stopband;
5233         u8 overtuned = 0;
5234         u8 rfcsr24 = (bw40) ? 0x27 : 0x07;
5235
5236         rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
5237
5238         rt2800_bbp_read(rt2x00dev, 4, &bbp);
5239         rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * bw40);
5240         rt2800_bbp_write(rt2x00dev, 4, bbp);
5241
5242         rt2800_rfcsr_read(rt2x00dev, 31, &rfcsr);
5243         rt2x00_set_field8(&rfcsr, RFCSR31_RX_H20M, bw40);
5244         rt2800_rfcsr_write(rt2x00dev, 31, rfcsr);
5245
5246         rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
5247         rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 1);
5248         rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
5249
5250         /*
5251          * Set power & frequency of passband test tone
5252          */
5253         rt2800_bbp_write(rt2x00dev, 24, 0);
5254
5255         for (i = 0; i < 100; i++) {
5256                 rt2800_bbp_write(rt2x00dev, 25, 0x90);
5257                 msleep(1);
5258
5259                 rt2800_bbp_read(rt2x00dev, 55, &passband);
5260                 if (passband)
5261                         break;
5262         }
5263
5264         /*
5265          * Set power & frequency of stopband test tone
5266          */
5267         rt2800_bbp_write(rt2x00dev, 24, 0x06);
5268
5269         for (i = 0; i < 100; i++) {
5270                 rt2800_bbp_write(rt2x00dev, 25, 0x90);
5271                 msleep(1);
5272
5273                 rt2800_bbp_read(rt2x00dev, 55, &stopband);
5274
5275                 if ((passband - stopband) <= filter_target) {
5276                         rfcsr24++;
5277                         overtuned += ((passband - stopband) == filter_target);
5278                 } else
5279                         break;
5280
5281                 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
5282         }
5283
5284         rfcsr24 -= !!overtuned;
5285
5286         rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
5287         return rfcsr24;
5288 }
5289
5290 static void rt2800_rf_init_calibration(struct rt2x00_dev *rt2x00dev,
5291                                        const unsigned int rf_reg)
5292 {
5293         u8 rfcsr;
5294
5295         rt2800_rfcsr_read(rt2x00dev, rf_reg, &rfcsr);
5296         rt2x00_set_field8(&rfcsr, FIELD8(0x80), 1);
5297         rt2800_rfcsr_write(rt2x00dev, rf_reg, rfcsr);
5298         msleep(1);
5299         rt2x00_set_field8(&rfcsr, FIELD8(0x80), 0);
5300         rt2800_rfcsr_write(rt2x00dev, rf_reg, rfcsr);
5301 }
5302
5303 static void rt2800_rx_filter_calibration(struct rt2x00_dev *rt2x00dev)
5304 {
5305         struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
5306         u8 filter_tgt_bw20;
5307         u8 filter_tgt_bw40;
5308         u8 rfcsr, bbp;
5309
5310         /*
5311          * TODO: sync filter_tgt values with vendor driver
5312          */
5313         if (rt2x00_rt(rt2x00dev, RT3070)) {
5314                 filter_tgt_bw20 = 0x16;
5315                 filter_tgt_bw40 = 0x19;
5316         } else {
5317                 filter_tgt_bw20 = 0x13;
5318                 filter_tgt_bw40 = 0x15;
5319         }
5320
5321         drv_data->calibration_bw20 =
5322                 rt2800_init_rx_filter(rt2x00dev, false, filter_tgt_bw20);
5323         drv_data->calibration_bw40 =
5324                 rt2800_init_rx_filter(rt2x00dev, true, filter_tgt_bw40);
5325
5326         /*
5327          * Save BBP 25 & 26 values for later use in channel switching (for 3052)
5328          */
5329         rt2800_bbp_read(rt2x00dev, 25, &drv_data->bbp25);
5330         rt2800_bbp_read(rt2x00dev, 26, &drv_data->bbp26);
5331
5332         /*
5333          * Set back to initial state
5334          */
5335         rt2800_bbp_write(rt2x00dev, 24, 0);
5336
5337         rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
5338         rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 0);
5339         rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
5340
5341         /*
5342          * Set BBP back to BW20
5343          */
5344         rt2800_bbp_read(rt2x00dev, 4, &bbp);
5345         rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 0);
5346         rt2800_bbp_write(rt2x00dev, 4, bbp);
5347 }
5348
5349 static void rt2800_normal_mode_setup_3xxx(struct rt2x00_dev *rt2x00dev)
5350 {
5351         struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
5352         u8 min_gain, rfcsr, bbp;
5353         u16 eeprom;
5354
5355         rt2800_rfcsr_read(rt2x00dev, 17, &rfcsr);
5356
5357         rt2x00_set_field8(&rfcsr, RFCSR17_TX_LO1_EN, 0);
5358         if (rt2x00_rt(rt2x00dev, RT3070) ||
5359             rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
5360             rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
5361             rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) {
5362                 if (!test_bit(CAPABILITY_EXTERNAL_LNA_BG, &rt2x00dev->cap_flags))
5363                         rt2x00_set_field8(&rfcsr, RFCSR17_R, 1);
5364         }
5365
5366         min_gain = rt2x00_rt(rt2x00dev, RT3070) ? 1 : 2;
5367         if (drv_data->txmixer_gain_24g >= min_gain) {
5368                 rt2x00_set_field8(&rfcsr, RFCSR17_TXMIXER_GAIN,
5369                                   drv_data->txmixer_gain_24g);
5370         }
5371
5372         rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
5373
5374         if (rt2x00_rt(rt2x00dev, RT3090)) {
5375                 /*  Turn off unused DAC1 and ADC1 to reduce power consumption */
5376                 rt2800_bbp_read(rt2x00dev, 138, &bbp);
5377                 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
5378                 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1)
5379                         rt2x00_set_field8(&bbp, BBP138_RX_ADC1, 0);
5380                 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1)
5381                         rt2x00_set_field8(&bbp, BBP138_TX_DAC1, 1);
5382                 rt2800_bbp_write(rt2x00dev, 138, bbp);
5383         }
5384
5385         if (rt2x00_rt(rt2x00dev, RT3070)) {
5386                 rt2800_rfcsr_read(rt2x00dev, 27, &rfcsr);
5387                 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F))
5388                         rt2x00_set_field8(&rfcsr, RFCSR27_R1, 3);
5389                 else
5390                         rt2x00_set_field8(&rfcsr, RFCSR27_R1, 0);
5391                 rt2x00_set_field8(&rfcsr, RFCSR27_R2, 0);
5392                 rt2x00_set_field8(&rfcsr, RFCSR27_R3, 0);
5393                 rt2x00_set_field8(&rfcsr, RFCSR27_R4, 0);
5394                 rt2800_rfcsr_write(rt2x00dev, 27, rfcsr);
5395         } else if (rt2x00_rt(rt2x00dev, RT3071) ||
5396                    rt2x00_rt(rt2x00dev, RT3090) ||
5397                    rt2x00_rt(rt2x00dev, RT3390)) {
5398                 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
5399                 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
5400                 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
5401                 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
5402                 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
5403                 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
5404                 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
5405
5406                 rt2800_rfcsr_read(rt2x00dev, 15, &rfcsr);
5407                 rt2x00_set_field8(&rfcsr, RFCSR15_TX_LO2_EN, 0);
5408                 rt2800_rfcsr_write(rt2x00dev, 15, rfcsr);
5409
5410                 rt2800_rfcsr_read(rt2x00dev, 20, &rfcsr);
5411                 rt2x00_set_field8(&rfcsr, RFCSR20_RX_LO1_EN, 0);
5412                 rt2800_rfcsr_write(rt2x00dev, 20, rfcsr);
5413
5414                 rt2800_rfcsr_read(rt2x00dev, 21, &rfcsr);
5415                 rt2x00_set_field8(&rfcsr, RFCSR21_RX_LO2_EN, 0);
5416                 rt2800_rfcsr_write(rt2x00dev, 21, rfcsr);
5417         }
5418 }
5419
5420 static void rt2800_normal_mode_setup_3593(struct rt2x00_dev *rt2x00dev)
5421 {
5422         struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
5423         u8 rfcsr;
5424         u8 tx_gain;
5425
5426         rt2800_rfcsr_read(rt2x00dev, 50, &rfcsr);
5427         rt2x00_set_field8(&rfcsr, RFCSR50_TX_LO2_EN, 0);
5428         rt2800_rfcsr_write(rt2x00dev, 50, rfcsr);
5429
5430         rt2800_rfcsr_read(rt2x00dev, 51, &rfcsr);
5431         tx_gain = rt2x00_get_field8(drv_data->txmixer_gain_24g,
5432                                     RFCSR17_TXMIXER_GAIN);
5433         rt2x00_set_field8(&rfcsr, RFCSR51_BITS24, tx_gain);
5434         rt2800_rfcsr_write(rt2x00dev, 51, rfcsr);
5435
5436         rt2800_rfcsr_read(rt2x00dev, 38, &rfcsr);
5437         rt2x00_set_field8(&rfcsr, RFCSR38_RX_LO1_EN, 0);
5438         rt2800_rfcsr_write(rt2x00dev, 38, rfcsr);
5439
5440         rt2800_rfcsr_read(rt2x00dev, 39, &rfcsr);
5441         rt2x00_set_field8(&rfcsr, RFCSR39_RX_LO2_EN, 0);
5442         rt2800_rfcsr_write(rt2x00dev, 39, rfcsr);
5443
5444         rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
5445         rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
5446         rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1);
5447         rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
5448
5449         rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
5450         rt2x00_set_field8(&rfcsr, RFCSR30_RX_VCM, 2);
5451         rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
5452
5453         /* TODO: enable stream mode */
5454 }
5455
5456 static void rt2800_normal_mode_setup_5xxx(struct rt2x00_dev *rt2x00dev)
5457 {
5458         u8 reg;
5459         u16 eeprom;
5460
5461         /*  Turn off unused DAC1 and ADC1 to reduce power consumption */
5462         rt2800_bbp_read(rt2x00dev, 138, &reg);
5463         rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
5464         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1)
5465                 rt2x00_set_field8(&reg, BBP138_RX_ADC1, 0);
5466         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1)
5467                 rt2x00_set_field8(&reg, BBP138_TX_DAC1, 1);
5468         rt2800_bbp_write(rt2x00dev, 138, reg);
5469
5470         rt2800_rfcsr_read(rt2x00dev, 38, &reg);
5471         rt2x00_set_field8(&reg, RFCSR38_RX_LO1_EN, 0);
5472         rt2800_rfcsr_write(rt2x00dev, 38, reg);
5473
5474         rt2800_rfcsr_read(rt2x00dev, 39, &reg);
5475         rt2x00_set_field8(&reg, RFCSR39_RX_LO2_EN, 0);
5476         rt2800_rfcsr_write(rt2x00dev, 39, reg);
5477
5478         rt2800_bbp4_mac_if_ctrl(rt2x00dev);
5479
5480         rt2800_rfcsr_read(rt2x00dev, 30, &reg);
5481         rt2x00_set_field8(&reg, RFCSR30_RX_VCM, 2);
5482         rt2800_rfcsr_write(rt2x00dev, 30, reg);
5483 }
5484
5485 static void rt2800_init_rfcsr_305x_soc(struct rt2x00_dev *rt2x00dev)
5486 {
5487         rt2800_rf_init_calibration(rt2x00dev, 30);
5488
5489         rt2800_rfcsr_write(rt2x00dev, 0, 0x50);
5490         rt2800_rfcsr_write(rt2x00dev, 1, 0x01);
5491         rt2800_rfcsr_write(rt2x00dev, 2, 0xf7);
5492         rt2800_rfcsr_write(rt2x00dev, 3, 0x75);
5493         rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
5494         rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
5495         rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
5496         rt2800_rfcsr_write(rt2x00dev, 7, 0x50);
5497         rt2800_rfcsr_write(rt2x00dev, 8, 0x39);
5498         rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
5499         rt2800_rfcsr_write(rt2x00dev, 10, 0x60);
5500         rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
5501         rt2800_rfcsr_write(rt2x00dev, 12, 0x75);
5502         rt2800_rfcsr_write(rt2x00dev, 13, 0x75);
5503         rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
5504         rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
5505         rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
5506         rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
5507         rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
5508         rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
5509         rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
5510         rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
5511         rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
5512         rt2800_rfcsr_write(rt2x00dev, 23, 0x31);
5513         rt2800_rfcsr_write(rt2x00dev, 24, 0x08);
5514         rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
5515         rt2800_rfcsr_write(rt2x00dev, 26, 0x25);
5516         rt2800_rfcsr_write(rt2x00dev, 27, 0x23);
5517         rt2800_rfcsr_write(rt2x00dev, 28, 0x13);
5518         rt2800_rfcsr_write(rt2x00dev, 29, 0x83);
5519         rt2800_rfcsr_write(rt2x00dev, 30, 0x00);
5520         rt2800_rfcsr_write(rt2x00dev, 31, 0x00);
5521 }
5522
5523 static void rt2800_init_rfcsr_30xx(struct rt2x00_dev *rt2x00dev)
5524 {
5525         u8 rfcsr;
5526         u16 eeprom;
5527         u32 reg;
5528
5529         /* XXX vendor driver do this only for 3070 */
5530         rt2800_rf_init_calibration(rt2x00dev, 30);
5531
5532         rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
5533         rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
5534         rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
5535         rt2800_rfcsr_write(rt2x00dev, 7, 0x60);
5536         rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
5537         rt2800_rfcsr_write(rt2x00dev, 10, 0x41);
5538         rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
5539         rt2800_rfcsr_write(rt2x00dev, 12, 0x7b);
5540         rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
5541         rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
5542         rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
5543         rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
5544         rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
5545         rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
5546         rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
5547         rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
5548         rt2800_rfcsr_write(rt2x00dev, 24, 0x16);
5549         rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
5550         rt2800_rfcsr_write(rt2x00dev, 29, 0x1f);
5551
5552         if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) {
5553                 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
5554                 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
5555                 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
5556                 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
5557         } else if (rt2x00_rt(rt2x00dev, RT3071) ||
5558                    rt2x00_rt(rt2x00dev, RT3090)) {
5559                 rt2800_rfcsr_write(rt2x00dev, 31, 0x14);
5560
5561                 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
5562                 rt2x00_set_field8(&rfcsr, RFCSR6_R2, 1);
5563                 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
5564
5565                 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
5566                 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
5567                 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
5568                     rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E)) {
5569                         rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1,
5570                                            &eeprom);
5571                         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_DAC_TEST))
5572                                 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
5573                         else
5574                                 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 0);
5575                 }
5576                 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
5577
5578                 rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg);
5579                 rt2x00_set_field32(&reg, GPIO_SWITCH_5, 0);
5580                 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
5581         }
5582
5583         rt2800_rx_filter_calibration(rt2x00dev);
5584
5585         if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F) ||
5586             rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
5587             rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E))
5588                 rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
5589
5590         rt2800_led_open_drain_enable(rt2x00dev);
5591         rt2800_normal_mode_setup_3xxx(rt2x00dev);
5592 }
5593
5594 static void rt2800_init_rfcsr_3290(struct rt2x00_dev *rt2x00dev)
5595 {
5596         u8 rfcsr;
5597
5598         rt2800_rf_init_calibration(rt2x00dev, 2);
5599
5600         rt2800_rfcsr_write(rt2x00dev, 1, 0x0f);
5601         rt2800_rfcsr_write(rt2x00dev, 2, 0x80);
5602         rt2800_rfcsr_write(rt2x00dev, 3, 0x08);
5603         rt2800_rfcsr_write(rt2x00dev, 4, 0x00);
5604         rt2800_rfcsr_write(rt2x00dev, 6, 0xa0);
5605         rt2800_rfcsr_write(rt2x00dev, 8, 0xf3);
5606         rt2800_rfcsr_write(rt2x00dev, 9, 0x02);
5607         rt2800_rfcsr_write(rt2x00dev, 10, 0x53);
5608         rt2800_rfcsr_write(rt2x00dev, 11, 0x4a);
5609         rt2800_rfcsr_write(rt2x00dev, 12, 0x46);
5610         rt2800_rfcsr_write(rt2x00dev, 13, 0x9f);
5611         rt2800_rfcsr_write(rt2x00dev, 18, 0x02);
5612         rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
5613         rt2800_rfcsr_write(rt2x00dev, 25, 0x83);
5614         rt2800_rfcsr_write(rt2x00dev, 26, 0x82);
5615         rt2800_rfcsr_write(rt2x00dev, 27, 0x09);
5616         rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
5617         rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
5618         rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
5619         rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
5620         rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
5621         rt2800_rfcsr_write(rt2x00dev, 34, 0x05);
5622         rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
5623         rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
5624         rt2800_rfcsr_write(rt2x00dev, 38, 0x85);
5625         rt2800_rfcsr_write(rt2x00dev, 39, 0x1b);
5626         rt2800_rfcsr_write(rt2x00dev, 40, 0x0b);
5627         rt2800_rfcsr_write(rt2x00dev, 41, 0xbb);
5628         rt2800_rfcsr_write(rt2x00dev, 42, 0xd5);
5629         rt2800_rfcsr_write(rt2x00dev, 43, 0x7b);
5630         rt2800_rfcsr_write(rt2x00dev, 44, 0x0e);
5631         rt2800_rfcsr_write(rt2x00dev, 45, 0xa2);
5632         rt2800_rfcsr_write(rt2x00dev, 46, 0x73);
5633         rt2800_rfcsr_write(rt2x00dev, 47, 0x00);
5634         rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
5635         rt2800_rfcsr_write(rt2x00dev, 49, 0x98);
5636         rt2800_rfcsr_write(rt2x00dev, 52, 0x38);
5637         rt2800_rfcsr_write(rt2x00dev, 53, 0x00);
5638         rt2800_rfcsr_write(rt2x00dev, 54, 0x78);
5639         rt2800_rfcsr_write(rt2x00dev, 55, 0x43);
5640         rt2800_rfcsr_write(rt2x00dev, 56, 0x02);
5641         rt2800_rfcsr_write(rt2x00dev, 57, 0x80);
5642         rt2800_rfcsr_write(rt2x00dev, 58, 0x7f);
5643         rt2800_rfcsr_write(rt2x00dev, 59, 0x09);
5644         rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
5645         rt2800_rfcsr_write(rt2x00dev, 61, 0xc1);
5646
5647         rt2800_rfcsr_read(rt2x00dev, 29, &rfcsr);
5648         rt2x00_set_field8(&rfcsr, RFCSR29_RSSI_GAIN, 3);
5649         rt2800_rfcsr_write(rt2x00dev, 29, rfcsr);
5650
5651         rt2800_led_open_drain_enable(rt2x00dev);
5652         rt2800_normal_mode_setup_3xxx(rt2x00dev);
5653 }
5654
5655 static void rt2800_init_rfcsr_3352(struct rt2x00_dev *rt2x00dev)
5656 {
5657         rt2800_rf_init_calibration(rt2x00dev, 30);
5658
5659         rt2800_rfcsr_write(rt2x00dev, 0, 0xf0);
5660         rt2800_rfcsr_write(rt2x00dev, 1, 0x23);
5661         rt2800_rfcsr_write(rt2x00dev, 2, 0x50);
5662         rt2800_rfcsr_write(rt2x00dev, 3, 0x18);
5663         rt2800_rfcsr_write(rt2x00dev, 4, 0x00);
5664         rt2800_rfcsr_write(rt2x00dev, 5, 0x00);
5665         rt2800_rfcsr_write(rt2x00dev, 6, 0x33);
5666         rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
5667         rt2800_rfcsr_write(rt2x00dev, 8, 0xf1);
5668         rt2800_rfcsr_write(rt2x00dev, 9, 0x02);
5669         rt2800_rfcsr_write(rt2x00dev, 10, 0xd2);
5670         rt2800_rfcsr_write(rt2x00dev, 11, 0x42);
5671         rt2800_rfcsr_write(rt2x00dev, 12, 0x1c);
5672         rt2800_rfcsr_write(rt2x00dev, 13, 0x00);
5673         rt2800_rfcsr_write(rt2x00dev, 14, 0x5a);
5674         rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
5675         rt2800_rfcsr_write(rt2x00dev, 16, 0x01);
5676         rt2800_rfcsr_write(rt2x00dev, 18, 0x45);
5677         rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
5678         rt2800_rfcsr_write(rt2x00dev, 20, 0x00);
5679         rt2800_rfcsr_write(rt2x00dev, 21, 0x00);
5680         rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
5681         rt2800_rfcsr_write(rt2x00dev, 23, 0x00);
5682         rt2800_rfcsr_write(rt2x00dev, 24, 0x00);
5683         rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
5684         rt2800_rfcsr_write(rt2x00dev, 26, 0x00);
5685         rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
5686         rt2800_rfcsr_write(rt2x00dev, 28, 0x03);
5687         rt2800_rfcsr_write(rt2x00dev, 29, 0x00);
5688         rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
5689         rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
5690         rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
5691         rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
5692         rt2800_rfcsr_write(rt2x00dev, 34, 0x01);
5693         rt2800_rfcsr_write(rt2x00dev, 35, 0x03);
5694         rt2800_rfcsr_write(rt2x00dev, 36, 0xbd);
5695         rt2800_rfcsr_write(rt2x00dev, 37, 0x3c);
5696         rt2800_rfcsr_write(rt2x00dev, 38, 0x5f);
5697         rt2800_rfcsr_write(rt2x00dev, 39, 0xc5);
5698         rt2800_rfcsr_write(rt2x00dev, 40, 0x33);
5699         rt2800_rfcsr_write(rt2x00dev, 41, 0x5b);
5700         rt2800_rfcsr_write(rt2x00dev, 42, 0x5b);
5701         rt2800_rfcsr_write(rt2x00dev, 43, 0xdb);
5702         rt2800_rfcsr_write(rt2x00dev, 44, 0xdb);
5703         rt2800_rfcsr_write(rt2x00dev, 45, 0xdb);
5704         rt2800_rfcsr_write(rt2x00dev, 46, 0xdd);
5705         rt2800_rfcsr_write(rt2x00dev, 47, 0x0d);
5706         rt2800_rfcsr_write(rt2x00dev, 48, 0x14);
5707         rt2800_rfcsr_write(rt2x00dev, 49, 0x00);
5708         rt2800_rfcsr_write(rt2x00dev, 50, 0x2d);
5709         rt2800_rfcsr_write(rt2x00dev, 51, 0x7f);
5710         rt2800_rfcsr_write(rt2x00dev, 52, 0x00);
5711         rt2800_rfcsr_write(rt2x00dev, 53, 0x52);
5712         rt2800_rfcsr_write(rt2x00dev, 54, 0x1b);
5713         rt2800_rfcsr_write(rt2x00dev, 55, 0x7f);
5714         rt2800_rfcsr_write(rt2x00dev, 56, 0x00);
5715         rt2800_rfcsr_write(rt2x00dev, 57, 0x52);
5716         rt2800_rfcsr_write(rt2x00dev, 58, 0x1b);
5717         rt2800_rfcsr_write(rt2x00dev, 59, 0x00);
5718         rt2800_rfcsr_write(rt2x00dev, 60, 0x00);
5719         rt2800_rfcsr_write(rt2x00dev, 61, 0x00);
5720         rt2800_rfcsr_write(rt2x00dev, 62, 0x00);
5721         rt2800_rfcsr_write(rt2x00dev, 63, 0x00);
5722
5723         rt2800_rx_filter_calibration(rt2x00dev);
5724         rt2800_led_open_drain_enable(rt2x00dev);
5725         rt2800_normal_mode_setup_3xxx(rt2x00dev);
5726 }
5727
5728 static void rt2800_init_rfcsr_3390(struct rt2x00_dev *rt2x00dev)
5729 {
5730         u32 reg;
5731
5732         rt2800_rf_init_calibration(rt2x00dev, 30);
5733
5734         rt2800_rfcsr_write(rt2x00dev, 0, 0xa0);
5735         rt2800_rfcsr_write(rt2x00dev, 1, 0xe1);
5736         rt2800_rfcsr_write(rt2x00dev, 2, 0xf1);
5737         rt2800_rfcsr_write(rt2x00dev, 3, 0x62);
5738         rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
5739         rt2800_rfcsr_write(rt2x00dev, 5, 0x8b);
5740         rt2800_rfcsr_write(rt2x00dev, 6, 0x42);
5741         rt2800_rfcsr_write(rt2x00dev, 7, 0x34);
5742         rt2800_rfcsr_write(rt2x00dev, 8, 0x00);
5743         rt2800_rfcsr_write(rt2x00dev, 9, 0xc0);
5744         rt2800_rfcsr_write(rt2x00dev, 10, 0x61);
5745         rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
5746         rt2800_rfcsr_write(rt2x00dev, 12, 0x3b);
5747         rt2800_rfcsr_write(rt2x00dev, 13, 0xe0);
5748         rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
5749         rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
5750         rt2800_rfcsr_write(rt2x00dev, 16, 0xe0);
5751         rt2800_rfcsr_write(rt2x00dev, 17, 0x94);
5752         rt2800_rfcsr_write(rt2x00dev, 18, 0x5c);
5753         rt2800_rfcsr_write(rt2x00dev, 19, 0x4a);
5754         rt2800_rfcsr_write(rt2x00dev, 20, 0xb2);
5755         rt2800_rfcsr_write(rt2x00dev, 21, 0xf6);
5756         rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
5757         rt2800_rfcsr_write(rt2x00dev, 23, 0x14);
5758         rt2800_rfcsr_write(rt2x00dev, 24, 0x08);
5759         rt2800_rfcsr_write(rt2x00dev, 25, 0x3d);
5760         rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
5761         rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
5762         rt2800_rfcsr_write(rt2x00dev, 28, 0x41);
5763         rt2800_rfcsr_write(rt2x00dev, 29, 0x8f);
5764         rt2800_rfcsr_write(rt2x00dev, 30, 0x20);
5765         rt2800_rfcsr_write(rt2x00dev, 31, 0x0f);
5766
5767         rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg);
5768         rt2x00_set_field32(&reg, GPIO_SWITCH_5, 0);
5769         rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
5770
5771         rt2800_rx_filter_calibration(rt2x00dev);
5772
5773         if (rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E))
5774                 rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
5775
5776         rt2800_led_open_drain_enable(rt2x00dev);
5777         rt2800_normal_mode_setup_3xxx(rt2x00dev);
5778 }
5779
5780 static void rt2800_init_rfcsr_3572(struct rt2x00_dev *rt2x00dev)
5781 {
5782         u8 rfcsr;
5783         u32 reg;
5784
5785         rt2800_rf_init_calibration(rt2x00dev, 30);
5786
5787         rt2800_rfcsr_write(rt2x00dev, 0, 0x70);
5788         rt2800_rfcsr_write(rt2x00dev, 1, 0x81);
5789         rt2800_rfcsr_write(rt2x00dev, 2, 0xf1);
5790         rt2800_rfcsr_write(rt2x00dev, 3, 0x02);
5791         rt2800_rfcsr_write(rt2x00dev, 4, 0x4c);
5792         rt2800_rfcsr_write(rt2x00dev, 5, 0x05);
5793         rt2800_rfcsr_write(rt2x00dev, 6, 0x4a);
5794         rt2800_rfcsr_write(rt2x00dev, 7, 0xd8);
5795         rt2800_rfcsr_write(rt2x00dev, 9, 0xc3);
5796         rt2800_rfcsr_write(rt2x00dev, 10, 0xf1);
5797         rt2800_rfcsr_write(rt2x00dev, 11, 0xb9);
5798         rt2800_rfcsr_write(rt2x00dev, 12, 0x70);
5799         rt2800_rfcsr_write(rt2x00dev, 13, 0x65);
5800         rt2800_rfcsr_write(rt2x00dev, 14, 0xa0);
5801         rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
5802         rt2800_rfcsr_write(rt2x00dev, 16, 0x4c);
5803         rt2800_rfcsr_write(rt2x00dev, 17, 0x23);
5804         rt2800_rfcsr_write(rt2x00dev, 18, 0xac);
5805         rt2800_rfcsr_write(rt2x00dev, 19, 0x93);
5806         rt2800_rfcsr_write(rt2x00dev, 20, 0xb3);
5807         rt2800_rfcsr_write(rt2x00dev, 21, 0xd0);
5808         rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
5809         rt2800_rfcsr_write(rt2x00dev, 23, 0x3c);
5810         rt2800_rfcsr_write(rt2x00dev, 24, 0x16);
5811         rt2800_rfcsr_write(rt2x00dev, 25, 0x15);
5812         rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
5813         rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
5814         rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
5815         rt2800_rfcsr_write(rt2x00dev, 29, 0x9b);
5816         rt2800_rfcsr_write(rt2x00dev, 30, 0x09);
5817         rt2800_rfcsr_write(rt2x00dev, 31, 0x10);
5818
5819         rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
5820         rt2x00_set_field8(&rfcsr, RFCSR6_R2, 1);
5821         rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
5822
5823         rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
5824         rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
5825         rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
5826         rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
5827         msleep(1);
5828         rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
5829         rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 0);
5830         rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
5831         rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
5832
5833         rt2800_rx_filter_calibration(rt2x00dev);
5834         rt2800_led_open_drain_enable(rt2x00dev);
5835         rt2800_normal_mode_setup_3xxx(rt2x00dev);
5836 }
5837
5838 static void rt3593_post_bbp_init(struct rt2x00_dev *rt2x00dev)
5839 {
5840         u8 bbp;
5841         bool txbf_enabled = false; /* FIXME */
5842
5843         rt2800_bbp_read(rt2x00dev, 105, &bbp);
5844         if (rt2x00dev->default_ant.rx_chain_num == 1)
5845                 rt2x00_set_field8(&bbp, BBP105_MLD, 0);
5846         else
5847                 rt2x00_set_field8(&bbp, BBP105_MLD, 1);
5848         rt2800_bbp_write(rt2x00dev, 105, bbp);
5849
5850         rt2800_bbp4_mac_if_ctrl(rt2x00dev);
5851
5852         rt2800_bbp_write(rt2x00dev, 92, 0x02);
5853         rt2800_bbp_write(rt2x00dev, 82, 0x82);
5854         rt2800_bbp_write(rt2x00dev, 106, 0x05);
5855         rt2800_bbp_write(rt2x00dev, 104, 0x92);
5856         rt2800_bbp_write(rt2x00dev, 88, 0x90);
5857         rt2800_bbp_write(rt2x00dev, 148, 0xc8);
5858         rt2800_bbp_write(rt2x00dev, 47, 0x48);
5859         rt2800_bbp_write(rt2x00dev, 120, 0x50);
5860
5861         if (txbf_enabled)
5862                 rt2800_bbp_write(rt2x00dev, 163, 0xbd);
5863         else
5864                 rt2800_bbp_write(rt2x00dev, 163, 0x9d);
5865
5866         /* SNR mapping */
5867         rt2800_bbp_write(rt2x00dev, 142, 6);
5868         rt2800_bbp_write(rt2x00dev, 143, 160);
5869         rt2800_bbp_write(rt2x00dev, 142, 7);
5870         rt2800_bbp_write(rt2x00dev, 143, 161);
5871         rt2800_bbp_write(rt2x00dev, 142, 8);
5872         rt2800_bbp_write(rt2x00dev, 143, 162);
5873
5874         /* ADC/DAC control */
5875         rt2800_bbp_write(rt2x00dev, 31, 0x08);
5876
5877         /* RX AGC energy lower bound in log2 */
5878         rt2800_bbp_write(rt2x00dev, 68, 0x0b);
5879
5880         /* FIXME: BBP 105 owerwrite? */
5881         rt2800_bbp_write(rt2x00dev, 105, 0x04);
5882 }
5883
5884 static void rt2800_init_rfcsr_3593(struct rt2x00_dev *rt2x00dev)
5885 {
5886         struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
5887         u32 reg;
5888         u8 rfcsr;
5889
5890         /* Disable GPIO #4 and #7 function for LAN PE control */
5891         rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg);
5892         rt2x00_set_field32(&reg, GPIO_SWITCH_4, 0);
5893         rt2x00_set_field32(&reg, GPIO_SWITCH_7, 0);
5894         rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
5895
5896         /* Initialize default register values */
5897         rt2800_rfcsr_write(rt2x00dev, 1, 0x03);
5898         rt2800_rfcsr_write(rt2x00dev, 3, 0x80);
5899         rt2800_rfcsr_write(rt2x00dev, 5, 0x00);
5900         rt2800_rfcsr_write(rt2x00dev, 6, 0x40);
5901         rt2800_rfcsr_write(rt2x00dev, 8, 0xf1);
5902         rt2800_rfcsr_write(rt2x00dev, 9, 0x02);
5903         rt2800_rfcsr_write(rt2x00dev, 10, 0xd3);
5904         rt2800_rfcsr_write(rt2x00dev, 11, 0x40);
5905         rt2800_rfcsr_write(rt2x00dev, 12, 0x4e);
5906         rt2800_rfcsr_write(rt2x00dev, 13, 0x12);
5907         rt2800_rfcsr_write(rt2x00dev, 18, 0x40);
5908         rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
5909         rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
5910         rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
5911         rt2800_rfcsr_write(rt2x00dev, 32, 0x78);
5912         rt2800_rfcsr_write(rt2x00dev, 33, 0x3b);
5913         rt2800_rfcsr_write(rt2x00dev, 34, 0x3c);
5914         rt2800_rfcsr_write(rt2x00dev, 35, 0xe0);
5915         rt2800_rfcsr_write(rt2x00dev, 38, 0x86);
5916         rt2800_rfcsr_write(rt2x00dev, 39, 0x23);
5917         rt2800_rfcsr_write(rt2x00dev, 44, 0xd3);
5918         rt2800_rfcsr_write(rt2x00dev, 45, 0xbb);
5919         rt2800_rfcsr_write(rt2x00dev, 46, 0x60);
5920         rt2800_rfcsr_write(rt2x00dev, 49, 0x8e);
5921         rt2800_rfcsr_write(rt2x00dev, 50, 0x86);
5922         rt2800_rfcsr_write(rt2x00dev, 51, 0x75);
5923         rt2800_rfcsr_write(rt2x00dev, 52, 0x45);
5924         rt2800_rfcsr_write(rt2x00dev, 53, 0x18);
5925         rt2800_rfcsr_write(rt2x00dev, 54, 0x18);
5926         rt2800_rfcsr_write(rt2x00dev, 55, 0x18);
5927         rt2800_rfcsr_write(rt2x00dev, 56, 0xdb);
5928         rt2800_rfcsr_write(rt2x00dev, 57, 0x6e);
5929
5930         /* Initiate calibration */
5931         /* TODO: use rt2800_rf_init_calibration ? */
5932         rt2800_rfcsr_read(rt2x00dev, 2, &rfcsr);
5933         rt2x00_set_field8(&rfcsr, RFCSR2_RESCAL_EN, 1);
5934         rt2800_rfcsr_write(rt2x00dev, 2, rfcsr);
5935
5936         rt2800_adjust_freq_offset(rt2x00dev);
5937
5938         rt2800_rfcsr_read(rt2x00dev, 18, &rfcsr);
5939         rt2x00_set_field8(&rfcsr, RFCSR18_XO_TUNE_BYPASS, 1);
5940         rt2800_rfcsr_write(rt2x00dev, 18, rfcsr);
5941
5942         rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
5943         rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
5944         rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
5945         rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
5946         usleep_range(1000, 1500);
5947         rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
5948         rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 0);
5949         rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
5950
5951         /* Set initial values for RX filter calibration */
5952         drv_data->calibration_bw20 = 0x1f;
5953         drv_data->calibration_bw40 = 0x2f;
5954
5955         /* Save BBP 25 & 26 values for later use in channel switching */
5956         rt2800_bbp_read(rt2x00dev, 25, &drv_data->bbp25);
5957         rt2800_bbp_read(rt2x00dev, 26, &drv_data->bbp26);
5958
5959         rt2800_led_open_drain_enable(rt2x00dev);
5960         rt2800_normal_mode_setup_3593(rt2x00dev);
5961
5962         rt3593_post_bbp_init(rt2x00dev);
5963
5964         /* TODO: enable stream mode support */
5965 }
5966
5967 static void rt2800_init_rfcsr_5390(struct rt2x00_dev *rt2x00dev)
5968 {
5969         rt2800_rf_init_calibration(rt2x00dev, 2);
5970
5971         rt2800_rfcsr_write(rt2x00dev, 1, 0x0f);
5972         rt2800_rfcsr_write(rt2x00dev, 2, 0x80);
5973         rt2800_rfcsr_write(rt2x00dev, 3, 0x88);
5974         rt2800_rfcsr_write(rt2x00dev, 5, 0x10);
5975         if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
5976                 rt2800_rfcsr_write(rt2x00dev, 6, 0xe0);
5977         else
5978                 rt2800_rfcsr_write(rt2x00dev, 6, 0xa0);
5979         rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
5980         rt2800_rfcsr_write(rt2x00dev, 10, 0x53);
5981         rt2800_rfcsr_write(rt2x00dev, 11, 0x4a);
5982         rt2800_rfcsr_write(rt2x00dev, 12, 0xc6);
5983         rt2800_rfcsr_write(rt2x00dev, 13, 0x9f);
5984         rt2800_rfcsr_write(rt2x00dev, 14, 0x00);
5985         rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
5986         rt2800_rfcsr_write(rt2x00dev, 16, 0x00);
5987         rt2800_rfcsr_write(rt2x00dev, 18, 0x03);
5988         rt2800_rfcsr_write(rt2x00dev, 19, 0x00);
5989
5990         rt2800_rfcsr_write(rt2x00dev, 20, 0x00);
5991         rt2800_rfcsr_write(rt2x00dev, 21, 0x00);
5992         rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
5993         rt2800_rfcsr_write(rt2x00dev, 23, 0x00);
5994         rt2800_rfcsr_write(rt2x00dev, 24, 0x00);
5995         if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
5996                 rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
5997         else
5998                 rt2800_rfcsr_write(rt2x00dev, 25, 0xc0);
5999         rt2800_rfcsr_write(rt2x00dev, 26, 0x00);
6000         rt2800_rfcsr_write(rt2x00dev, 27, 0x09);
6001         rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
6002         rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
6003
6004         rt2800_rfcsr_write(rt2x00dev, 30, 0x00);
6005         rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
6006         rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
6007         rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
6008         rt2800_rfcsr_write(rt2x00dev, 34, 0x07);
6009         rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
6010         rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
6011         rt2800_rfcsr_write(rt2x00dev, 37, 0x08);
6012         rt2800_rfcsr_write(rt2x00dev, 38, 0x85);
6013         rt2800_rfcsr_write(rt2x00dev, 39, 0x1b);
6014
6015         if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
6016                 rt2800_rfcsr_write(rt2x00dev, 40, 0x0b);
6017         else
6018                 rt2800_rfcsr_write(rt2x00dev, 40, 0x4b);
6019         rt2800_rfcsr_write(rt2x00dev, 41, 0xbb);
6020         rt2800_rfcsr_write(rt2x00dev, 42, 0xd2);
6021         rt2800_rfcsr_write(rt2x00dev, 43, 0x9a);
6022         rt2800_rfcsr_write(rt2x00dev, 44, 0x0e);
6023         rt2800_rfcsr_write(rt2x00dev, 45, 0xa2);
6024         if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
6025                 rt2800_rfcsr_write(rt2x00dev, 46, 0x73);
6026         else
6027                 rt2800_rfcsr_write(rt2x00dev, 46, 0x7b);
6028         rt2800_rfcsr_write(rt2x00dev, 47, 0x00);
6029         rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
6030         rt2800_rfcsr_write(rt2x00dev, 49, 0x94);
6031
6032         rt2800_rfcsr_write(rt2x00dev, 52, 0x38);
6033         if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
6034                 rt2800_rfcsr_write(rt2x00dev, 53, 0x00);
6035         else
6036                 rt2800_rfcsr_write(rt2x00dev, 53, 0x84);
6037         rt2800_rfcsr_write(rt2x00dev, 54, 0x78);
6038         rt2800_rfcsr_write(rt2x00dev, 55, 0x44);
6039         rt2800_rfcsr_write(rt2x00dev, 56, 0x22);
6040         rt2800_rfcsr_write(rt2x00dev, 57, 0x80);
6041         rt2800_rfcsr_write(rt2x00dev, 58, 0x7f);
6042         rt2800_rfcsr_write(rt2x00dev, 59, 0x63);
6043
6044         rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
6045         if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
6046                 rt2800_rfcsr_write(rt2x00dev, 61, 0xd1);
6047         else
6048                 rt2800_rfcsr_write(rt2x00dev, 61, 0xdd);
6049         rt2800_rfcsr_write(rt2x00dev, 62, 0x00);
6050         rt2800_rfcsr_write(rt2x00dev, 63, 0x00);
6051
6052         rt2800_normal_mode_setup_5xxx(rt2x00dev);
6053
6054         rt2800_led_open_drain_enable(rt2x00dev);
6055 }
6056
6057 static void rt2800_init_rfcsr_5392(struct rt2x00_dev *rt2x00dev)
6058 {
6059         rt2800_rf_init_calibration(rt2x00dev, 2);
6060
6061         rt2800_rfcsr_write(rt2x00dev, 1, 0x17);
6062         rt2800_rfcsr_write(rt2x00dev, 2, 0x80);
6063         rt2800_rfcsr_write(rt2x00dev, 3, 0x88);
6064         rt2800_rfcsr_write(rt2x00dev, 5, 0x10);
6065         rt2800_rfcsr_write(rt2x00dev, 6, 0xe0);
6066         rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
6067         rt2800_rfcsr_write(rt2x00dev, 10, 0x53);
6068         rt2800_rfcsr_write(rt2x00dev, 11, 0x4a);
6069         rt2800_rfcsr_write(rt2x00dev, 12, 0x46);
6070         rt2800_rfcsr_write(rt2x00dev, 13, 0x9f);
6071         rt2800_rfcsr_write(rt2x00dev, 14, 0x00);
6072         rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
6073         rt2800_rfcsr_write(rt2x00dev, 16, 0x00);
6074         rt2800_rfcsr_write(rt2x00dev, 18, 0x03);
6075         rt2800_rfcsr_write(rt2x00dev, 19, 0x4d);
6076         rt2800_rfcsr_write(rt2x00dev, 20, 0x00);
6077         rt2800_rfcsr_write(rt2x00dev, 21, 0x8d);
6078         rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
6079         rt2800_rfcsr_write(rt2x00dev, 23, 0x0b);
6080         rt2800_rfcsr_write(rt2x00dev, 24, 0x44);
6081         rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
6082         rt2800_rfcsr_write(rt2x00dev, 26, 0x82);
6083         rt2800_rfcsr_write(rt2x00dev, 27, 0x09);
6084         rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
6085         rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
6086         rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
6087         rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
6088         rt2800_rfcsr_write(rt2x00dev, 32, 0x20);
6089         rt2800_rfcsr_write(rt2x00dev, 33, 0xC0);
6090         rt2800_rfcsr_write(rt2x00dev, 34, 0x07);
6091         rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
6092         rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
6093         rt2800_rfcsr_write(rt2x00dev, 37, 0x08);
6094         rt2800_rfcsr_write(rt2x00dev, 38, 0x89);
6095         rt2800_rfcsr_write(rt2x00dev, 39, 0x1b);
6096         rt2800_rfcsr_write(rt2x00dev, 40, 0x0f);
6097         rt2800_rfcsr_write(rt2x00dev, 41, 0xbb);
6098         rt2800_rfcsr_write(rt2x00dev, 42, 0xd5);
6099         rt2800_rfcsr_write(rt2x00dev, 43, 0x9b);
6100         rt2800_rfcsr_write(rt2x00dev, 44, 0x0e);
6101         rt2800_rfcsr_write(rt2x00dev, 45, 0xa2);
6102         rt2800_rfcsr_write(rt2x00dev, 46, 0x73);
6103         rt2800_rfcsr_write(rt2x00dev, 47, 0x0c);
6104         rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
6105         rt2800_rfcsr_write(rt2x00dev, 49, 0x94);
6106         rt2800_rfcsr_write(rt2x00dev, 50, 0x94);
6107         rt2800_rfcsr_write(rt2x00dev, 51, 0x3a);
6108         rt2800_rfcsr_write(rt2x00dev, 52, 0x48);
6109         rt2800_rfcsr_write(rt2x00dev, 53, 0x44);
6110         rt2800_rfcsr_write(rt2x00dev, 54, 0x38);
6111         rt2800_rfcsr_write(rt2x00dev, 55, 0x43);
6112         rt2800_rfcsr_write(rt2x00dev, 56, 0xa1);
6113         rt2800_rfcsr_write(rt2x00dev, 57, 0x00);
6114         rt2800_rfcsr_write(rt2x00dev, 58, 0x39);
6115         rt2800_rfcsr_write(rt2x00dev, 59, 0x07);
6116         rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
6117         rt2800_rfcsr_write(rt2x00dev, 61, 0x91);
6118         rt2800_rfcsr_write(rt2x00dev, 62, 0x39);
6119         rt2800_rfcsr_write(rt2x00dev, 63, 0x07);
6120
6121         rt2800_normal_mode_setup_5xxx(rt2x00dev);
6122
6123         rt2800_led_open_drain_enable(rt2x00dev);
6124 }
6125
6126 static void rt2800_init_rfcsr_5592(struct rt2x00_dev *rt2x00dev)
6127 {
6128         rt2800_rf_init_calibration(rt2x00dev, 30);
6129
6130         rt2800_rfcsr_write(rt2x00dev, 1, 0x3F);
6131         rt2800_rfcsr_write(rt2x00dev, 3, 0x08);
6132         rt2800_rfcsr_write(rt2x00dev, 3, 0x08);
6133         rt2800_rfcsr_write(rt2x00dev, 5, 0x10);
6134         rt2800_rfcsr_write(rt2x00dev, 6, 0xE4);
6135         rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
6136         rt2800_rfcsr_write(rt2x00dev, 14, 0x00);
6137         rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
6138         rt2800_rfcsr_write(rt2x00dev, 16, 0x00);
6139         rt2800_rfcsr_write(rt2x00dev, 18, 0x03);
6140         rt2800_rfcsr_write(rt2x00dev, 19, 0x4D);
6141         rt2800_rfcsr_write(rt2x00dev, 20, 0x10);
6142         rt2800_rfcsr_write(rt2x00dev, 21, 0x8D);
6143         rt2800_rfcsr_write(rt2x00dev, 26, 0x82);
6144         rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
6145         rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
6146         rt2800_rfcsr_write(rt2x00dev, 33, 0xC0);
6147         rt2800_rfcsr_write(rt2x00dev, 34, 0x07);
6148         rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
6149         rt2800_rfcsr_write(rt2x00dev, 47, 0x0C);
6150         rt2800_rfcsr_write(rt2x00dev, 53, 0x22);
6151         rt2800_rfcsr_write(rt2x00dev, 63, 0x07);
6152
6153         rt2800_rfcsr_write(rt2x00dev, 2, 0x80);
6154         msleep(1);
6155
6156         rt2800_adjust_freq_offset(rt2x00dev);
6157
6158         /* Enable DC filter */
6159         if (rt2x00_rt_rev_gte(rt2x00dev, RT5592, REV_RT5592C))
6160                 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
6161
6162         rt2800_normal_mode_setup_5xxx(rt2x00dev);
6163
6164         if (rt2x00_rt_rev_lt(rt2x00dev, RT5592, REV_RT5592C))
6165                 rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
6166
6167         rt2800_led_open_drain_enable(rt2x00dev);
6168 }
6169
6170 static void rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)
6171 {
6172         if (rt2800_is_305x_soc(rt2x00dev)) {
6173                 rt2800_init_rfcsr_305x_soc(rt2x00dev);
6174                 return;
6175         }
6176
6177         switch (rt2x00dev->chip.rt) {
6178         case RT3070:
6179         case RT3071:
6180         case RT3090:
6181                 rt2800_init_rfcsr_30xx(rt2x00dev);
6182                 break;
6183         case RT3290:
6184                 rt2800_init_rfcsr_3290(rt2x00dev);
6185                 break;
6186         case RT3352:
6187                 rt2800_init_rfcsr_3352(rt2x00dev);
6188                 break;
6189         case RT3390:
6190                 rt2800_init_rfcsr_3390(rt2x00dev);
6191                 break;
6192         case RT3572:
6193                 rt2800_init_rfcsr_3572(rt2x00dev);
6194                 break;
6195         case RT3593:
6196                 rt2800_init_rfcsr_3593(rt2x00dev);
6197                 break;
6198         case RT5390:
6199                 rt2800_init_rfcsr_5390(rt2x00dev);
6200                 break;
6201         case RT5392:
6202                 rt2800_init_rfcsr_5392(rt2x00dev);
6203                 break;
6204         case RT5592:
6205                 rt2800_init_rfcsr_5592(rt2x00dev);
6206                 break;
6207         }
6208 }
6209
6210 int rt2800_enable_radio(struct rt2x00_dev *rt2x00dev)
6211 {
6212         u32 reg;
6213         u16 word;
6214
6215         /*
6216          * Initialize all registers.
6217          */
6218         if (unlikely(rt2800_wait_wpdma_ready(rt2x00dev) ||
6219                      rt2800_init_registers(rt2x00dev)))
6220                 return -EIO;
6221
6222         /*
6223          * Send signal to firmware during boot time.
6224          */
6225         rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
6226         rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
6227         if (rt2x00_is_usb(rt2x00dev)) {
6228                 rt2800_register_write(rt2x00dev, H2M_INT_SRC, 0);
6229                 rt2800_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0, 0, 0);
6230         }
6231         msleep(1);
6232
6233         if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev) ||
6234                      rt2800_wait_bbp_ready(rt2x00dev)))
6235                 return -EIO;
6236
6237         rt2800_init_bbp(rt2x00dev);
6238         rt2800_init_rfcsr(rt2x00dev);
6239
6240         if (rt2x00_is_usb(rt2x00dev) &&
6241             (rt2x00_rt(rt2x00dev, RT3070) ||
6242              rt2x00_rt(rt2x00dev, RT3071) ||
6243              rt2x00_rt(rt2x00dev, RT3572))) {
6244                 udelay(200);
6245                 rt2800_mcu_request(rt2x00dev, MCU_CURRENT, 0, 0, 0);
6246                 udelay(10);
6247         }
6248
6249         /*
6250          * Enable RX.
6251          */
6252         rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
6253         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
6254         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0);
6255         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
6256
6257         udelay(50);
6258
6259         rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
6260         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 1);
6261         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 1);
6262         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 2);
6263         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
6264         rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
6265
6266         rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
6267         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
6268         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 1);
6269         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
6270
6271         /*
6272          * Initialize LED control
6273          */
6274         rt2800_eeprom_read(rt2x00dev, EEPROM_LED_AG_CONF, &word);
6275         rt2800_mcu_request(rt2x00dev, MCU_LED_AG_CONF, 0xff,
6276                            word & 0xff, (word >> 8) & 0xff);
6277
6278         rt2800_eeprom_read(rt2x00dev, EEPROM_LED_ACT_CONF, &word);
6279         rt2800_mcu_request(rt2x00dev, MCU_LED_ACT_CONF, 0xff,
6280                            word & 0xff, (word >> 8) & 0xff);
6281
6282         rt2800_eeprom_read(rt2x00dev, EEPROM_LED_POLARITY, &word);
6283         rt2800_mcu_request(rt2x00dev, MCU_LED_LED_POLARITY, 0xff,
6284                            word & 0xff, (word >> 8) & 0xff);
6285
6286         return 0;
6287 }
6288 EXPORT_SYMBOL_GPL(rt2800_enable_radio);
6289
6290 void rt2800_disable_radio(struct rt2x00_dev *rt2x00dev)
6291 {
6292         u32 reg;
6293
6294         rt2800_disable_wpdma(rt2x00dev);
6295
6296         /* Wait for DMA, ignore error */
6297         rt2800_wait_wpdma_ready(rt2x00dev);
6298
6299         rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
6300         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 0);
6301         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0);
6302         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
6303 }
6304 EXPORT_SYMBOL_GPL(rt2800_disable_radio);
6305
6306 int rt2800_efuse_detect(struct rt2x00_dev *rt2x00dev)
6307 {
6308         u32 reg;
6309         u16 efuse_ctrl_reg;
6310
6311         if (rt2x00_rt(rt2x00dev, RT3290))
6312                 efuse_ctrl_reg = EFUSE_CTRL_3290;
6313         else
6314                 efuse_ctrl_reg = EFUSE_CTRL;
6315
6316         rt2800_register_read(rt2x00dev, efuse_ctrl_reg, &reg);
6317         return rt2x00_get_field32(reg, EFUSE_CTRL_PRESENT);
6318 }
6319 EXPORT_SYMBOL_GPL(rt2800_efuse_detect);
6320
6321 static void rt2800_efuse_read(struct rt2x00_dev *rt2x00dev, unsigned int i)
6322 {
6323         u32 reg;
6324         u16 efuse_ctrl_reg;
6325         u16 efuse_data0_reg;
6326         u16 efuse_data1_reg;
6327         u16 efuse_data2_reg;
6328         u16 efuse_data3_reg;
6329
6330         if (rt2x00_rt(rt2x00dev, RT3290)) {
6331                 efuse_ctrl_reg = EFUSE_CTRL_3290;
6332                 efuse_data0_reg = EFUSE_DATA0_3290;
6333                 efuse_data1_reg = EFUSE_DATA1_3290;
6334                 efuse_data2_reg = EFUSE_DATA2_3290;
6335                 efuse_data3_reg = EFUSE_DATA3_3290;
6336         } else {
6337                 efuse_ctrl_reg = EFUSE_CTRL;
6338                 efuse_data0_reg = EFUSE_DATA0;
6339                 efuse_data1_reg = EFUSE_DATA1;
6340                 efuse_data2_reg = EFUSE_DATA2;
6341                 efuse_data3_reg = EFUSE_DATA3;
6342         }
6343         mutex_lock(&rt2x00dev->csr_mutex);
6344
6345         rt2800_register_read_lock(rt2x00dev, efuse_ctrl_reg, &reg);
6346         rt2x00_set_field32(&reg, EFUSE_CTRL_ADDRESS_IN, i);
6347         rt2x00_set_field32(&reg, EFUSE_CTRL_MODE, 0);
6348         rt2x00_set_field32(&reg, EFUSE_CTRL_KICK, 1);
6349         rt2800_register_write_lock(rt2x00dev, efuse_ctrl_reg, reg);
6350
6351         /* Wait until the EEPROM has been loaded */
6352         rt2800_regbusy_read(rt2x00dev, efuse_ctrl_reg, EFUSE_CTRL_KICK, &reg);
6353         /* Apparently the data is read from end to start */
6354         rt2800_register_read_lock(rt2x00dev, efuse_data3_reg, &reg);
6355         /* The returned value is in CPU order, but eeprom is le */
6356         *(u32 *)&rt2x00dev->eeprom[i] = cpu_to_le32(reg);
6357         rt2800_register_read_lock(rt2x00dev, efuse_data2_reg, &reg);
6358         *(u32 *)&rt2x00dev->eeprom[i + 2] = cpu_to_le32(reg);
6359         rt2800_register_read_lock(rt2x00dev, efuse_data1_reg, &reg);
6360         *(u32 *)&rt2x00dev->eeprom[i + 4] = cpu_to_le32(reg);
6361         rt2800_register_read_lock(rt2x00dev, efuse_data0_reg, &reg);
6362         *(u32 *)&rt2x00dev->eeprom[i + 6] = cpu_to_le32(reg);
6363
6364         mutex_unlock(&rt2x00dev->csr_mutex);
6365 }
6366
6367 int rt2800_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
6368 {
6369         unsigned int i;
6370
6371         for (i = 0; i < EEPROM_SIZE / sizeof(u16); i += 8)
6372                 rt2800_efuse_read(rt2x00dev, i);
6373
6374         return 0;
6375 }
6376 EXPORT_SYMBOL_GPL(rt2800_read_eeprom_efuse);
6377
6378 static u8 rt2800_get_txmixer_gain_24g(struct rt2x00_dev *rt2x00dev)
6379 {
6380         u16 word;
6381
6382         if (rt2x00_rt(rt2x00dev, RT3593))
6383                 return 0;
6384
6385         rt2800_eeprom_read(rt2x00dev, EEPROM_TXMIXER_GAIN_BG, &word);
6386         if ((word & 0x00ff) != 0x00ff)
6387                 return rt2x00_get_field16(word, EEPROM_TXMIXER_GAIN_BG_VAL);
6388
6389         return 0;
6390 }
6391
6392 static u8 rt2800_get_txmixer_gain_5g(struct rt2x00_dev *rt2x00dev)
6393 {
6394         u16 word;
6395
6396         if (rt2x00_rt(rt2x00dev, RT3593))
6397                 return 0;
6398
6399         rt2800_eeprom_read(rt2x00dev, EEPROM_TXMIXER_GAIN_A, &word);
6400         if ((word & 0x00ff) != 0x00ff)
6401                 return rt2x00_get_field16(word, EEPROM_TXMIXER_GAIN_A_VAL);
6402
6403         return 0;
6404 }
6405
6406 static int rt2800_validate_eeprom(struct rt2x00_dev *rt2x00dev)
6407 {
6408         struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
6409         u16 word;
6410         u8 *mac;
6411         u8 default_lna_gain;
6412         int retval;
6413
6414         /*
6415          * Read the EEPROM.
6416          */
6417         retval = rt2800_read_eeprom(rt2x00dev);
6418         if (retval)
6419                 return retval;
6420
6421         /*
6422          * Start validation of the data that has been read.
6423          */
6424         mac = rt2800_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
6425         if (!is_valid_ether_addr(mac)) {
6426                 eth_random_addr(mac);
6427                 rt2x00_eeprom_dbg(rt2x00dev, "MAC: %pM\n", mac);
6428         }
6429
6430         rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &word);
6431         if (word == 0xffff) {
6432                 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RXPATH, 2);
6433                 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_TXPATH, 1);
6434                 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RF_TYPE, RF2820);
6435                 rt2800_eeprom_write(rt2x00dev, EEPROM_NIC_CONF0, word);
6436                 rt2x00_eeprom_dbg(rt2x00dev, "Antenna: 0x%04x\n", word);
6437         } else if (rt2x00_rt(rt2x00dev, RT2860) ||
6438                    rt2x00_rt(rt2x00dev, RT2872)) {
6439                 /*
6440                  * There is a max of 2 RX streams for RT28x0 series
6441                  */
6442                 if (rt2x00_get_field16(word, EEPROM_NIC_CONF0_RXPATH) > 2)
6443                         rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RXPATH, 2);
6444                 rt2800_eeprom_write(rt2x00dev, EEPROM_NIC_CONF0, word);
6445         }
6446
6447         rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &word);
6448         if (word == 0xffff) {
6449                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_HW_RADIO, 0);
6450                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_TX_ALC, 0);
6451                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_LNA_2G, 0);
6452                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_LNA_5G, 0);
6453                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_CARDBUS_ACCEL, 0);
6454                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_SB_2G, 0);
6455                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_SB_5G, 0);
6456                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_WPS_PBC, 0);
6457                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_2G, 0);
6458                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_5G, 0);
6459                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BROADBAND_EXT_LNA, 0);
6460                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_ANT_DIVERSITY, 0);
6461                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_INTERNAL_TX_ALC, 0);
6462                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BT_COEXIST, 0);
6463                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_DAC_TEST, 0);
6464                 rt2800_eeprom_write(rt2x00dev, EEPROM_NIC_CONF1, word);
6465                 rt2x00_eeprom_dbg(rt2x00dev, "NIC: 0x%04x\n", word);
6466         }
6467
6468         rt2800_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
6469         if ((word & 0x00ff) == 0x00ff) {
6470                 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
6471                 rt2800_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
6472                 rt2x00_eeprom_dbg(rt2x00dev, "Freq: 0x%04x\n", word);
6473         }
6474         if ((word & 0xff00) == 0xff00) {
6475                 rt2x00_set_field16(&word, EEPROM_FREQ_LED_MODE,
6476                                    LED_MODE_TXRX_ACTIVITY);
6477                 rt2x00_set_field16(&word, EEPROM_FREQ_LED_POLARITY, 0);
6478                 rt2800_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
6479                 rt2800_eeprom_write(rt2x00dev, EEPROM_LED_AG_CONF, 0x5555);
6480                 rt2800_eeprom_write(rt2x00dev, EEPROM_LED_ACT_CONF, 0x2221);
6481                 rt2800_eeprom_write(rt2x00dev, EEPROM_LED_POLARITY, 0xa9f8);
6482                 rt2x00_eeprom_dbg(rt2x00dev, "Led Mode: 0x%04x\n", word);
6483         }
6484
6485         /*
6486          * During the LNA validation we are going to use
6487          * lna0 as correct value. Note that EEPROM_LNA
6488          * is never validated.
6489          */
6490         rt2800_eeprom_read(rt2x00dev, EEPROM_LNA, &word);
6491         default_lna_gain = rt2x00_get_field16(word, EEPROM_LNA_A0);
6492
6493         rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &word);
6494         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET0)) > 10)
6495                 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET0, 0);
6496         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET1)) > 10)
6497                 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET1, 0);
6498         rt2800_eeprom_write(rt2x00dev, EEPROM_RSSI_BG, word);
6499
6500         drv_data->txmixer_gain_24g = rt2800_get_txmixer_gain_24g(rt2x00dev);
6501
6502         rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &word);
6503         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG2_OFFSET2)) > 10)
6504                 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_OFFSET2, 0);
6505         if (!rt2x00_rt(rt2x00dev, RT3593)) {
6506                 if (rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0x00 ||
6507                     rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0xff)
6508                         rt2x00_set_field16(&word, EEPROM_RSSI_BG2_LNA_A1,
6509                                            default_lna_gain);
6510         }
6511         rt2800_eeprom_write(rt2x00dev, EEPROM_RSSI_BG2, word);
6512
6513         drv_data->txmixer_gain_5g = rt2800_get_txmixer_gain_5g(rt2x00dev);
6514
6515         rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &word);
6516         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET0)) > 10)
6517                 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET0, 0);
6518         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET1)) > 10)
6519                 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET1, 0);
6520         rt2800_eeprom_write(rt2x00dev, EEPROM_RSSI_A, word);
6521
6522         rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &word);
6523         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A2_OFFSET2)) > 10)
6524                 rt2x00_set_field16(&word, EEPROM_RSSI_A2_OFFSET2, 0);
6525         if (!rt2x00_rt(rt2x00dev, RT3593)) {
6526                 if (rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0x00 ||
6527                     rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0xff)
6528                         rt2x00_set_field16(&word, EEPROM_RSSI_A2_LNA_A2,
6529                                            default_lna_gain);
6530         }
6531         rt2800_eeprom_write(rt2x00dev, EEPROM_RSSI_A2, word);
6532
6533         if (rt2x00_rt(rt2x00dev, RT3593)) {
6534                 rt2800_eeprom_read(rt2x00dev, EEPROM_EXT_LNA2, &word);
6535                 if (rt2x00_get_field16(word, EEPROM_EXT_LNA2_A1) == 0x00 ||
6536                     rt2x00_get_field16(word, EEPROM_EXT_LNA2_A1) == 0xff)
6537                         rt2x00_set_field16(&word, EEPROM_EXT_LNA2_A1,
6538                                            default_lna_gain);
6539                 if (rt2x00_get_field16(word, EEPROM_EXT_LNA2_A2) == 0x00 ||
6540                     rt2x00_get_field16(word, EEPROM_EXT_LNA2_A2) == 0xff)
6541                         rt2x00_set_field16(&word, EEPROM_EXT_LNA2_A1,
6542                                            default_lna_gain);
6543                 rt2800_eeprom_write(rt2x00dev, EEPROM_EXT_LNA2, word);
6544         }
6545
6546         return 0;
6547 }
6548
6549 static int rt2800_init_eeprom(struct rt2x00_dev *rt2x00dev)
6550 {
6551         u16 value;
6552         u16 eeprom;
6553         u16 rf;
6554
6555         /*
6556          * Read EEPROM word for configuration.
6557          */
6558         rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
6559
6560         /*
6561          * Identify RF chipset by EEPROM value
6562          * RT28xx/RT30xx: defined in "EEPROM_NIC_CONF0_RF_TYPE" field
6563          * RT53xx: defined in "EEPROM_CHIP_ID" field
6564          */
6565         if (rt2x00_rt(rt2x00dev, RT3290) ||
6566             rt2x00_rt(rt2x00dev, RT5390) ||
6567             rt2x00_rt(rt2x00dev, RT5392))
6568                 rt2800_eeprom_read(rt2x00dev, EEPROM_CHIP_ID, &rf);
6569         else
6570                 rf = rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RF_TYPE);
6571
6572         switch (rf) {
6573         case RF2820:
6574         case RF2850:
6575         case RF2720:
6576         case RF2750:
6577         case RF3020:
6578         case RF2020:
6579         case RF3021:
6580         case RF3022:
6581         case RF3052:
6582         case RF3290:
6583         case RF3320:
6584         case RF3322:
6585         case RF5360:
6586         case RF5370:
6587         case RF5372:
6588         case RF5390:
6589         case RF5392:
6590         case RF5592:
6591                 break;
6592         default:
6593                 rt2x00_err(rt2x00dev, "Invalid RF chipset 0x%04x detected\n",
6594                            rf);
6595                 return -ENODEV;
6596         }
6597
6598         rt2x00_set_rf(rt2x00dev, rf);
6599
6600         /*
6601          * Identify default antenna configuration.
6602          */
6603         rt2x00dev->default_ant.tx_chain_num =
6604             rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH);
6605         rt2x00dev->default_ant.rx_chain_num =
6606             rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH);
6607
6608         rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
6609
6610         if (rt2x00_rt(rt2x00dev, RT3070) ||
6611             rt2x00_rt(rt2x00dev, RT3090) ||
6612             rt2x00_rt(rt2x00dev, RT3352) ||
6613             rt2x00_rt(rt2x00dev, RT3390)) {
6614                 value = rt2x00_get_field16(eeprom,
6615                                 EEPROM_NIC_CONF1_ANT_DIVERSITY);
6616                 switch (value) {
6617                 case 0:
6618                 case 1:
6619                 case 2:
6620                         rt2x00dev->default_ant.tx = ANTENNA_A;
6621                         rt2x00dev->default_ant.rx = ANTENNA_A;
6622                         break;
6623                 case 3:
6624                         rt2x00dev->default_ant.tx = ANTENNA_A;
6625                         rt2x00dev->default_ant.rx = ANTENNA_B;
6626                         break;
6627                 }
6628         } else {
6629                 rt2x00dev->default_ant.tx = ANTENNA_A;
6630                 rt2x00dev->default_ant.rx = ANTENNA_A;
6631         }
6632
6633         if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390R)) {
6634                 rt2x00dev->default_ant.tx = ANTENNA_HW_DIVERSITY; /* Unused */
6635                 rt2x00dev->default_ant.rx = ANTENNA_HW_DIVERSITY; /* Unused */
6636         }
6637
6638         /*
6639          * Determine external LNA informations.
6640          */
6641         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_LNA_5G))
6642                 __set_bit(CAPABILITY_EXTERNAL_LNA_A, &rt2x00dev->cap_flags);
6643         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_LNA_2G))
6644                 __set_bit(CAPABILITY_EXTERNAL_LNA_BG, &rt2x00dev->cap_flags);
6645
6646         /*
6647          * Detect if this device has an hardware controlled radio.
6648          */
6649         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_HW_RADIO))
6650                 __set_bit(CAPABILITY_HW_BUTTON, &rt2x00dev->cap_flags);
6651
6652         /*
6653          * Detect if this device has Bluetooth co-existence.
6654          */
6655         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_BT_COEXIST))
6656                 __set_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags);
6657
6658         /*
6659          * Read frequency offset and RF programming sequence.
6660          */
6661         rt2800_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
6662         rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
6663
6664         /*
6665          * Store led settings, for correct led behaviour.
6666          */
6667 #ifdef CONFIG_RT2X00_LIB_LEDS
6668         rt2800_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
6669         rt2800_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC);
6670         rt2800_init_led(rt2x00dev, &rt2x00dev->led_qual, LED_TYPE_QUALITY);
6671
6672         rt2x00dev->led_mcu_reg = eeprom;
6673 #endif /* CONFIG_RT2X00_LIB_LEDS */
6674
6675         /*
6676          * Check if support EIRP tx power limit feature.
6677          */
6678         rt2800_eeprom_read(rt2x00dev, EEPROM_EIRP_MAX_TX_POWER, &eeprom);
6679
6680         if (rt2x00_get_field16(eeprom, EEPROM_EIRP_MAX_TX_POWER_2GHZ) <
6681                                         EIRP_MAX_TX_POWER_LIMIT)
6682                 __set_bit(CAPABILITY_POWER_LIMIT, &rt2x00dev->cap_flags);
6683
6684         return 0;
6685 }
6686
6687 /*
6688  * RF value list for rt28xx
6689  * Supports: 2.4 GHz (all) & 5.2 GHz (RF2850 & RF2750)
6690  */
6691 static const struct rf_channel rf_vals[] = {
6692         { 1,  0x18402ecc, 0x184c0786, 0x1816b455, 0x1800510b },
6693         { 2,  0x18402ecc, 0x184c0786, 0x18168a55, 0x1800519f },
6694         { 3,  0x18402ecc, 0x184c078a, 0x18168a55, 0x1800518b },
6695         { 4,  0x18402ecc, 0x184c078a, 0x18168a55, 0x1800519f },
6696         { 5,  0x18402ecc, 0x184c078e, 0x18168a55, 0x1800518b },
6697         { 6,  0x18402ecc, 0x184c078e, 0x18168a55, 0x1800519f },
6698         { 7,  0x18402ecc, 0x184c0792, 0x18168a55, 0x1800518b },
6699         { 8,  0x18402ecc, 0x184c0792, 0x18168a55, 0x1800519f },
6700         { 9,  0x18402ecc, 0x184c0796, 0x18168a55, 0x1800518b },
6701         { 10, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800519f },
6702         { 11, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800518b },
6703         { 12, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800519f },
6704         { 13, 0x18402ecc, 0x184c079e, 0x18168a55, 0x1800518b },
6705         { 14, 0x18402ecc, 0x184c07a2, 0x18168a55, 0x18005193 },
6706
6707         /* 802.11 UNI / HyperLan 2 */
6708         { 36, 0x18402ecc, 0x184c099a, 0x18158a55, 0x180ed1a3 },
6709         { 38, 0x18402ecc, 0x184c099e, 0x18158a55, 0x180ed193 },
6710         { 40, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed183 },
6711         { 44, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed1a3 },
6712         { 46, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed18b },
6713         { 48, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed19b },
6714         { 52, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed193 },
6715         { 54, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed1a3 },
6716         { 56, 0x18402ec8, 0x184c068e, 0x18158a55, 0x180ed18b },
6717         { 60, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed183 },
6718         { 62, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed193 },
6719         { 64, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed1a3 },
6720
6721         /* 802.11 HyperLan 2 */
6722         { 100, 0x18402ec8, 0x184c06b2, 0x18178a55, 0x180ed783 },
6723         { 102, 0x18402ec8, 0x184c06b2, 0x18578a55, 0x180ed793 },
6724         { 104, 0x18402ec8, 0x185c06b2, 0x18578a55, 0x180ed1a3 },
6725         { 108, 0x18402ecc, 0x185c0a32, 0x18578a55, 0x180ed193 },
6726         { 110, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed183 },
6727         { 112, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed19b },
6728         { 116, 0x18402ecc, 0x184c0a3a, 0x18178a55, 0x180ed1a3 },
6729         { 118, 0x18402ecc, 0x184c0a3e, 0x18178a55, 0x180ed193 },
6730         { 120, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed183 },
6731         { 124, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed193 },
6732         { 126, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed15b },
6733         { 128, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed1a3 },
6734         { 132, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed18b },
6735         { 134, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed193 },
6736         { 136, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed19b },
6737         { 140, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed183 },
6738
6739         /* 802.11 UNII */
6740         { 149, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed1a7 },
6741         { 151, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed187 },
6742         { 153, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed18f },
6743         { 157, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed19f },
6744         { 159, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed1a7 },
6745         { 161, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed187 },
6746         { 165, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed197 },
6747         { 167, 0x18402ec4, 0x184c03d2, 0x18179855, 0x1815531f },
6748         { 169, 0x18402ec4, 0x184c03d2, 0x18179855, 0x18155327 },
6749         { 171, 0x18402ec4, 0x184c03d6, 0x18179855, 0x18155307 },
6750         { 173, 0x18402ec4, 0x184c03d6, 0x18179855, 0x1815530f },
6751
6752         /* 802.11 Japan */
6753         { 184, 0x15002ccc, 0x1500491e, 0x1509be55, 0x150c0a0b },
6754         { 188, 0x15002ccc, 0x15004922, 0x1509be55, 0x150c0a13 },
6755         { 192, 0x15002ccc, 0x15004926, 0x1509be55, 0x150c0a1b },
6756         { 196, 0x15002ccc, 0x1500492a, 0x1509be55, 0x150c0a23 },
6757         { 208, 0x15002ccc, 0x1500493a, 0x1509be55, 0x150c0a13 },
6758         { 212, 0x15002ccc, 0x1500493e, 0x1509be55, 0x150c0a1b },
6759         { 216, 0x15002ccc, 0x15004982, 0x1509be55, 0x150c0a23 },
6760 };
6761
6762 /*
6763  * RF value list for rt3xxx
6764  * Supports: 2.4 GHz (all) & 5.2 GHz (RF3052)
6765  */
6766 static const struct rf_channel rf_vals_3x[] = {
6767         {1,  241, 2, 2 },
6768         {2,  241, 2, 7 },
6769         {3,  242, 2, 2 },
6770         {4,  242, 2, 7 },
6771         {5,  243, 2, 2 },
6772         {6,  243, 2, 7 },
6773         {7,  244, 2, 2 },
6774         {8,  244, 2, 7 },
6775         {9,  245, 2, 2 },
6776         {10, 245, 2, 7 },
6777         {11, 246, 2, 2 },
6778         {12, 246, 2, 7 },
6779         {13, 247, 2, 2 },
6780         {14, 248, 2, 4 },
6781
6782         /* 802.11 UNI / HyperLan 2 */
6783         {36, 0x56, 0, 4},
6784         {38, 0x56, 0, 6},
6785         {40, 0x56, 0, 8},
6786         {44, 0x57, 0, 0},
6787         {46, 0x57, 0, 2},
6788         {48, 0x57, 0, 4},
6789         {52, 0x57, 0, 8},
6790         {54, 0x57, 0, 10},
6791         {56, 0x58, 0, 0},
6792         {60, 0x58, 0, 4},
6793         {62, 0x58, 0, 6},
6794         {64, 0x58, 0, 8},
6795
6796         /* 802.11 HyperLan 2 */
6797         {100, 0x5b, 0, 8},
6798         {102, 0x5b, 0, 10},
6799         {104, 0x5c, 0, 0},
6800         {108, 0x5c, 0, 4},
6801         {110, 0x5c, 0, 6},
6802         {112, 0x5c, 0, 8},
6803         {116, 0x5d, 0, 0},
6804         {118, 0x5d, 0, 2},
6805         {120, 0x5d, 0, 4},
6806         {124, 0x5d, 0, 8},
6807         {126, 0x5d, 0, 10},
6808         {128, 0x5e, 0, 0},
6809         {132, 0x5e, 0, 4},
6810         {134, 0x5e, 0, 6},
6811         {136, 0x5e, 0, 8},
6812         {140, 0x5f, 0, 0},
6813
6814         /* 802.11 UNII */
6815         {149, 0x5f, 0, 9},
6816         {151, 0x5f, 0, 11},
6817         {153, 0x60, 0, 1},
6818         {157, 0x60, 0, 5},
6819         {159, 0x60, 0, 7},
6820         {161, 0x60, 0, 9},
6821         {165, 0x61, 0, 1},
6822         {167, 0x61, 0, 3},
6823         {169, 0x61, 0, 5},
6824         {171, 0x61, 0, 7},
6825         {173, 0x61, 0, 9},
6826 };
6827
6828 static const struct rf_channel rf_vals_5592_xtal20[] = {
6829         /* Channel, N, K, mod, R */
6830         {1, 482, 4, 10, 3},
6831         {2, 483, 4, 10, 3},
6832         {3, 484, 4, 10, 3},
6833         {4, 485, 4, 10, 3},
6834         {5, 486, 4, 10, 3},
6835         {6, 487, 4, 10, 3},
6836         {7, 488, 4, 10, 3},
6837         {8, 489, 4, 10, 3},
6838         {9, 490, 4, 10, 3},
6839         {10, 491, 4, 10, 3},
6840         {11, 492, 4, 10, 3},
6841         {12, 493, 4, 10, 3},
6842         {13, 494, 4, 10, 3},
6843         {14, 496, 8, 10, 3},
6844         {36, 172, 8, 12, 1},
6845         {38, 173, 0, 12, 1},
6846         {40, 173, 4, 12, 1},
6847         {42, 173, 8, 12, 1},
6848         {44, 174, 0, 12, 1},
6849         {46, 174, 4, 12, 1},
6850         {48, 174, 8, 12, 1},
6851         {50, 175, 0, 12, 1},
6852         {52, 175, 4, 12, 1},
6853         {54, 175, 8, 12, 1},
6854         {56, 176, 0, 12, 1},
6855         {58, 176, 4, 12, 1},
6856         {60, 176, 8, 12, 1},
6857         {62, 177, 0, 12, 1},
6858         {64, 177, 4, 12, 1},
6859         {100, 183, 4, 12, 1},
6860         {102, 183, 8, 12, 1},
6861         {104, 184, 0, 12, 1},
6862         {106, 184, 4, 12, 1},
6863         {108, 184, 8, 12, 1},
6864         {110, 185, 0, 12, 1},
6865         {112, 185, 4, 12, 1},
6866         {114, 185, 8, 12, 1},
6867         {116, 186, 0, 12, 1},
6868         {118, 186, 4, 12, 1},
6869         {120, 186, 8, 12, 1},
6870         {122, 187, 0, 12, 1},
6871         {124, 187, 4, 12, 1},
6872         {126, 187, 8, 12, 1},
6873         {128, 188, 0, 12, 1},
6874         {130, 188, 4, 12, 1},
6875         {132, 188, 8, 12, 1},
6876         {134, 189, 0, 12, 1},
6877         {136, 189, 4, 12, 1},
6878         {138, 189, 8, 12, 1},
6879         {140, 190, 0, 12, 1},
6880         {149, 191, 6, 12, 1},
6881         {151, 191, 10, 12, 1},
6882         {153, 192, 2, 12, 1},
6883         {155, 192, 6, 12, 1},
6884         {157, 192, 10, 12, 1},
6885         {159, 193, 2, 12, 1},
6886         {161, 193, 6, 12, 1},
6887         {165, 194, 2, 12, 1},
6888         {184, 164, 0, 12, 1},
6889         {188, 164, 4, 12, 1},
6890         {192, 165, 8, 12, 1},
6891         {196, 166, 0, 12, 1},
6892 };
6893
6894 static const struct rf_channel rf_vals_5592_xtal40[] = {
6895         /* Channel, N, K, mod, R */
6896         {1, 241, 2, 10, 3},
6897         {2, 241, 7, 10, 3},
6898         {3, 242, 2, 10, 3},
6899         {4, 242, 7, 10, 3},
6900         {5, 243, 2, 10, 3},
6901         {6, 243, 7, 10, 3},
6902         {7, 244, 2, 10, 3},
6903         {8, 244, 7, 10, 3},
6904         {9, 245, 2, 10, 3},
6905         {10, 245, 7, 10, 3},
6906         {11, 246, 2, 10, 3},
6907         {12, 246, 7, 10, 3},
6908         {13, 247, 2, 10, 3},
6909         {14, 248, 4, 10, 3},
6910         {36, 86, 4, 12, 1},
6911         {38, 86, 6, 12, 1},
6912         {40, 86, 8, 12, 1},
6913         {42, 86, 10, 12, 1},
6914         {44, 87, 0, 12, 1},
6915         {46, 87, 2, 12, 1},
6916         {48, 87, 4, 12, 1},
6917         {50, 87, 6, 12, 1},
6918         {52, 87, 8, 12, 1},
6919         {54, 87, 10, 12, 1},
6920         {56, 88, 0, 12, 1},
6921         {58, 88, 2, 12, 1},
6922         {60, 88, 4, 12, 1},
6923         {62, 88, 6, 12, 1},
6924         {64, 88, 8, 12, 1},
6925         {100, 91, 8, 12, 1},
6926         {102, 91, 10, 12, 1},
6927         {104, 92, 0, 12, 1},
6928         {106, 92, 2, 12, 1},
6929         {108, 92, 4, 12, 1},
6930         {110, 92, 6, 12, 1},
6931         {112, 92, 8, 12, 1},
6932         {114, 92, 10, 12, 1},
6933         {116, 93, 0, 12, 1},
6934         {118, 93, 2, 12, 1},
6935         {120, 93, 4, 12, 1},
6936         {122, 93, 6, 12, 1},
6937         {124, 93, 8, 12, 1},
6938         {126, 93, 10, 12, 1},
6939         {128, 94, 0, 12, 1},
6940         {130, 94, 2, 12, 1},
6941         {132, 94, 4, 12, 1},
6942         {134, 94, 6, 12, 1},
6943         {136, 94, 8, 12, 1},
6944         {138, 94, 10, 12, 1},
6945         {140, 95, 0, 12, 1},
6946         {149, 95, 9, 12, 1},
6947         {151, 95, 11, 12, 1},
6948         {153, 96, 1, 12, 1},
6949         {155, 96, 3, 12, 1},
6950         {157, 96, 5, 12, 1},
6951         {159, 96, 7, 12, 1},
6952         {161, 96, 9, 12, 1},
6953         {165, 97, 1, 12, 1},
6954         {184, 82, 0, 12, 1},
6955         {188, 82, 4, 12, 1},
6956         {192, 82, 8, 12, 1},
6957         {196, 83, 0, 12, 1},
6958 };
6959
6960 static int rt2800_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
6961 {
6962         struct hw_mode_spec *spec = &rt2x00dev->spec;
6963         struct channel_info *info;
6964         char *default_power1;
6965         char *default_power2;
6966         unsigned int i;
6967         u16 eeprom;
6968         u32 reg;
6969
6970         /*
6971          * Disable powersaving as default on PCI devices.
6972          */
6973         if (rt2x00_is_pci(rt2x00dev) || rt2x00_is_soc(rt2x00dev))
6974                 rt2x00dev->hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
6975
6976         /*
6977          * Initialize all hw fields.
6978          */
6979         rt2x00dev->hw->flags =
6980             IEEE80211_HW_SIGNAL_DBM |
6981             IEEE80211_HW_SUPPORTS_PS |
6982             IEEE80211_HW_PS_NULLFUNC_STACK |
6983             IEEE80211_HW_AMPDU_AGGREGATION |
6984             IEEE80211_HW_REPORTS_TX_ACK_STATUS;
6985
6986         /*
6987          * Don't set IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING for USB devices
6988          * unless we are capable of sending the buffered frames out after the
6989          * DTIM transmission using rt2x00lib_beacondone. This will send out
6990          * multicast and broadcast traffic immediately instead of buffering it
6991          * infinitly and thus dropping it after some time.
6992          */
6993         if (!rt2x00_is_usb(rt2x00dev))
6994                 rt2x00dev->hw->flags |=
6995                         IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING;
6996
6997         SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
6998         SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
6999                                 rt2800_eeprom_addr(rt2x00dev,
7000                                                    EEPROM_MAC_ADDR_0));
7001
7002         /*
7003          * As rt2800 has a global fallback table we cannot specify
7004          * more then one tx rate per frame but since the hw will
7005          * try several rates (based on the fallback table) we should
7006          * initialize max_report_rates to the maximum number of rates
7007          * we are going to try. Otherwise mac80211 will truncate our
7008          * reported tx rates and the rc algortihm will end up with
7009          * incorrect data.
7010          */
7011         rt2x00dev->hw->max_rates = 1;
7012         rt2x00dev->hw->max_report_rates = 7;
7013         rt2x00dev->hw->max_rate_tries = 1;
7014
7015         rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
7016
7017         /*
7018          * Initialize hw_mode information.
7019          */
7020         spec->supported_bands = SUPPORT_BAND_2GHZ;
7021         spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
7022
7023         if (rt2x00_rf(rt2x00dev, RF2820) ||
7024             rt2x00_rf(rt2x00dev, RF2720)) {
7025                 spec->num_channels = 14;
7026                 spec->channels = rf_vals;
7027         } else if (rt2x00_rf(rt2x00dev, RF2850) ||
7028                    rt2x00_rf(rt2x00dev, RF2750)) {
7029                 spec->supported_bands |= SUPPORT_BAND_5GHZ;
7030                 spec->num_channels = ARRAY_SIZE(rf_vals);
7031                 spec->channels = rf_vals;
7032         } else if (rt2x00_rf(rt2x00dev, RF3020) ||
7033                    rt2x00_rf(rt2x00dev, RF2020) ||
7034                    rt2x00_rf(rt2x00dev, RF3021) ||
7035                    rt2x00_rf(rt2x00dev, RF3022) ||
7036                    rt2x00_rf(rt2x00dev, RF3290) ||
7037                    rt2x00_rf(rt2x00dev, RF3320) ||
7038                    rt2x00_rf(rt2x00dev, RF3322) ||
7039                    rt2x00_rf(rt2x00dev, RF5360) ||
7040                    rt2x00_rf(rt2x00dev, RF5370) ||
7041                    rt2x00_rf(rt2x00dev, RF5372) ||
7042                    rt2x00_rf(rt2x00dev, RF5390) ||
7043                    rt2x00_rf(rt2x00dev, RF5392)) {
7044                 spec->num_channels = 14;
7045                 spec->channels = rf_vals_3x;
7046         } else if (rt2x00_rf(rt2x00dev, RF3052)) {
7047                 spec->supported_bands |= SUPPORT_BAND_5GHZ;
7048                 spec->num_channels = ARRAY_SIZE(rf_vals_3x);
7049                 spec->channels = rf_vals_3x;
7050         } else if (rt2x00_rf(rt2x00dev, RF5592)) {
7051                 spec->supported_bands |= SUPPORT_BAND_5GHZ;
7052
7053                 rt2800_register_read(rt2x00dev, MAC_DEBUG_INDEX, &reg);
7054                 if (rt2x00_get_field32(reg, MAC_DEBUG_INDEX_XTAL)) {
7055                         spec->num_channels = ARRAY_SIZE(rf_vals_5592_xtal40);
7056                         spec->channels = rf_vals_5592_xtal40;
7057                 } else {
7058                         spec->num_channels = ARRAY_SIZE(rf_vals_5592_xtal20);
7059                         spec->channels = rf_vals_5592_xtal20;
7060                 }
7061         }
7062
7063         if (WARN_ON_ONCE(!spec->channels))
7064                 return -ENODEV;
7065
7066         /*
7067          * Initialize HT information.
7068          */
7069         if (!rt2x00_rf(rt2x00dev, RF2020))
7070                 spec->ht.ht_supported = true;
7071         else
7072                 spec->ht.ht_supported = false;
7073
7074         spec->ht.cap =
7075             IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
7076             IEEE80211_HT_CAP_GRN_FLD |
7077             IEEE80211_HT_CAP_SGI_20 |
7078             IEEE80211_HT_CAP_SGI_40;
7079
7080         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) >= 2)
7081                 spec->ht.cap |= IEEE80211_HT_CAP_TX_STBC;
7082
7083         spec->ht.cap |=
7084             rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) <<
7085                 IEEE80211_HT_CAP_RX_STBC_SHIFT;
7086
7087         spec->ht.ampdu_factor = 3;
7088         spec->ht.ampdu_density = 4;
7089         spec->ht.mcs.tx_params =
7090             IEEE80211_HT_MCS_TX_DEFINED |
7091             IEEE80211_HT_MCS_TX_RX_DIFF |
7092             ((rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) - 1) <<
7093                 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
7094
7095         switch (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH)) {
7096         case 3:
7097                 spec->ht.mcs.rx_mask[2] = 0xff;
7098         case 2:
7099                 spec->ht.mcs.rx_mask[1] = 0xff;
7100         case 1:
7101                 spec->ht.mcs.rx_mask[0] = 0xff;
7102                 spec->ht.mcs.rx_mask[4] = 0x1; /* MCS32 */
7103                 break;
7104         }
7105
7106         /*
7107          * Create channel information array
7108          */
7109         info = kcalloc(spec->num_channels, sizeof(*info), GFP_KERNEL);
7110         if (!info)
7111                 return -ENOMEM;
7112
7113         spec->channels_info = info;
7114
7115         default_power1 = rt2800_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG1);
7116         default_power2 = rt2800_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG2);
7117
7118         for (i = 0; i < 14; i++) {
7119                 info[i].default_power1 = default_power1[i];
7120                 info[i].default_power2 = default_power2[i];
7121         }
7122
7123         if (spec->num_channels > 14) {
7124                 default_power1 = rt2800_eeprom_addr(rt2x00dev,
7125                                                     EEPROM_TXPOWER_A1);
7126                 default_power2 = rt2800_eeprom_addr(rt2x00dev,
7127                                                     EEPROM_TXPOWER_A2);
7128
7129                 for (i = 14; i < spec->num_channels; i++) {
7130                         info[i].default_power1 = default_power1[i - 14];
7131                         info[i].default_power2 = default_power2[i - 14];
7132                 }
7133         }
7134
7135         switch (rt2x00dev->chip.rf) {
7136         case RF2020:
7137         case RF3020:
7138         case RF3021:
7139         case RF3022:
7140         case RF3320:
7141         case RF3052:
7142         case RF3290:
7143         case RF5360:
7144         case RF5370:
7145         case RF5372:
7146         case RF5390:
7147         case RF5392:
7148                 __set_bit(CAPABILITY_VCO_RECALIBRATION, &rt2x00dev->cap_flags);
7149                 break;
7150         }
7151
7152         return 0;
7153 }
7154
7155 static int rt2800_probe_rt(struct rt2x00_dev *rt2x00dev)
7156 {
7157         u32 reg;
7158         u32 rt;
7159         u32 rev;
7160
7161         if (rt2x00_rt(rt2x00dev, RT3290))
7162                 rt2800_register_read(rt2x00dev, MAC_CSR0_3290, &reg);
7163         else
7164                 rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
7165
7166         rt = rt2x00_get_field32(reg, MAC_CSR0_CHIPSET);
7167         rev = rt2x00_get_field32(reg, MAC_CSR0_REVISION);
7168
7169         switch (rt) {
7170         case RT2860:
7171         case RT2872:
7172         case RT2883:
7173         case RT3070:
7174         case RT3071:
7175         case RT3090:
7176         case RT3290:
7177         case RT3352:
7178         case RT3390:
7179         case RT3572:
7180         case RT5390:
7181         case RT5392:
7182         case RT5592:
7183                 break;
7184         default:
7185                 rt2x00_err(rt2x00dev, "Invalid RT chipset 0x%04x, rev %04x detected\n",
7186                            rt, rev);
7187                 return -ENODEV;
7188         }
7189
7190         rt2x00_set_rt(rt2x00dev, rt, rev);
7191
7192         return 0;
7193 }
7194
7195 int rt2800_probe_hw(struct rt2x00_dev *rt2x00dev)
7196 {
7197         int retval;
7198         u32 reg;
7199
7200         retval = rt2800_probe_rt(rt2x00dev);
7201         if (retval)
7202                 return retval;
7203
7204         /*
7205          * Allocate eeprom data.
7206          */
7207         retval = rt2800_validate_eeprom(rt2x00dev);
7208         if (retval)
7209                 return retval;
7210
7211         retval = rt2800_init_eeprom(rt2x00dev);
7212         if (retval)
7213                 return retval;
7214
7215         /*
7216          * Enable rfkill polling by setting GPIO direction of the
7217          * rfkill switch GPIO pin correctly.
7218          */
7219         rt2800_register_read(rt2x00dev, GPIO_CTRL, &reg);
7220         rt2x00_set_field32(&reg, GPIO_CTRL_DIR2, 1);
7221         rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
7222
7223         /*
7224          * Initialize hw specifications.
7225          */
7226         retval = rt2800_probe_hw_mode(rt2x00dev);
7227         if (retval)
7228                 return retval;
7229
7230         /*
7231          * Set device capabilities.
7232          */
7233         __set_bit(CAPABILITY_CONTROL_FILTERS, &rt2x00dev->cap_flags);
7234         __set_bit(CAPABILITY_CONTROL_FILTER_PSPOLL, &rt2x00dev->cap_flags);
7235         if (!rt2x00_is_usb(rt2x00dev))
7236                 __set_bit(CAPABILITY_PRE_TBTT_INTERRUPT, &rt2x00dev->cap_flags);
7237
7238         /*
7239          * Set device requirements.
7240          */
7241         if (!rt2x00_is_soc(rt2x00dev))
7242                 __set_bit(REQUIRE_FIRMWARE, &rt2x00dev->cap_flags);
7243         __set_bit(REQUIRE_L2PAD, &rt2x00dev->cap_flags);
7244         __set_bit(REQUIRE_TXSTATUS_FIFO, &rt2x00dev->cap_flags);
7245         if (!rt2800_hwcrypt_disabled(rt2x00dev))
7246                 __set_bit(CAPABILITY_HW_CRYPTO, &rt2x00dev->cap_flags);
7247         __set_bit(CAPABILITY_LINK_TUNING, &rt2x00dev->cap_flags);
7248         __set_bit(REQUIRE_HT_TX_DESC, &rt2x00dev->cap_flags);
7249         if (rt2x00_is_usb(rt2x00dev))
7250                 __set_bit(REQUIRE_PS_AUTOWAKE, &rt2x00dev->cap_flags);
7251         else {
7252                 __set_bit(REQUIRE_DMA, &rt2x00dev->cap_flags);
7253                 __set_bit(REQUIRE_TASKLET_CONTEXT, &rt2x00dev->cap_flags);
7254         }
7255
7256         /*
7257          * Set the rssi offset.
7258          */
7259         rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
7260
7261         return 0;
7262 }
7263 EXPORT_SYMBOL_GPL(rt2800_probe_hw);
7264
7265 /*
7266  * IEEE80211 stack callback functions.
7267  */
7268 void rt2800_get_tkip_seq(struct ieee80211_hw *hw, u8 hw_key_idx, u32 *iv32,
7269                          u16 *iv16)
7270 {
7271         struct rt2x00_dev *rt2x00dev = hw->priv;
7272         struct mac_iveiv_entry iveiv_entry;
7273         u32 offset;
7274
7275         offset = MAC_IVEIV_ENTRY(hw_key_idx);
7276         rt2800_register_multiread(rt2x00dev, offset,
7277                                       &iveiv_entry, sizeof(iveiv_entry));
7278
7279         memcpy(iv16, &iveiv_entry.iv[0], sizeof(*iv16));
7280         memcpy(iv32, &iveiv_entry.iv[4], sizeof(*iv32));
7281 }
7282 EXPORT_SYMBOL_GPL(rt2800_get_tkip_seq);
7283
7284 int rt2800_set_rts_threshold(struct ieee80211_hw *hw, u32 value)
7285 {
7286         struct rt2x00_dev *rt2x00dev = hw->priv;
7287         u32 reg;
7288         bool enabled = (value < IEEE80211_MAX_RTS_THRESHOLD);
7289
7290         rt2800_register_read(rt2x00dev, TX_RTS_CFG, &reg);
7291         rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES, value);
7292         rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
7293
7294         rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
7295         rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, enabled);
7296         rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
7297
7298         rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
7299         rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, enabled);
7300         rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
7301
7302         rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
7303         rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, enabled);
7304         rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
7305
7306         rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
7307         rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, enabled);
7308         rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
7309
7310         rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
7311         rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, enabled);
7312         rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
7313
7314         rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
7315         rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, enabled);
7316         rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
7317
7318         return 0;
7319 }
7320 EXPORT_SYMBOL_GPL(rt2800_set_rts_threshold);
7321
7322 int rt2800_conf_tx(struct ieee80211_hw *hw,
7323                    struct ieee80211_vif *vif, u16 queue_idx,
7324                    const struct ieee80211_tx_queue_params *params)
7325 {
7326         struct rt2x00_dev *rt2x00dev = hw->priv;
7327         struct data_queue *queue;
7328         struct rt2x00_field32 field;
7329         int retval;
7330         u32 reg;
7331         u32 offset;
7332
7333         /*
7334          * First pass the configuration through rt2x00lib, that will
7335          * update the queue settings and validate the input. After that
7336          * we are free to update the registers based on the value
7337          * in the queue parameter.
7338          */
7339         retval = rt2x00mac_conf_tx(hw, vif, queue_idx, params);
7340         if (retval)
7341                 return retval;
7342
7343         /*
7344          * We only need to perform additional register initialization
7345          * for WMM queues/
7346          */
7347         if (queue_idx >= 4)
7348                 return 0;
7349
7350         queue = rt2x00queue_get_tx_queue(rt2x00dev, queue_idx);
7351
7352         /* Update WMM TXOP register */
7353         offset = WMM_TXOP0_CFG + (sizeof(u32) * (!!(queue_idx & 2)));
7354         field.bit_offset = (queue_idx & 1) * 16;
7355         field.bit_mask = 0xffff << field.bit_offset;
7356
7357         rt2800_register_read(rt2x00dev, offset, &reg);
7358         rt2x00_set_field32(&reg, field, queue->txop);
7359         rt2800_register_write(rt2x00dev, offset, reg);
7360
7361         /* Update WMM registers */
7362         field.bit_offset = queue_idx * 4;
7363         field.bit_mask = 0xf << field.bit_offset;
7364
7365         rt2800_register_read(rt2x00dev, WMM_AIFSN_CFG, &reg);
7366         rt2x00_set_field32(&reg, field, queue->aifs);
7367         rt2800_register_write(rt2x00dev, WMM_AIFSN_CFG, reg);
7368
7369         rt2800_register_read(rt2x00dev, WMM_CWMIN_CFG, &reg);
7370         rt2x00_set_field32(&reg, field, queue->cw_min);
7371         rt2800_register_write(rt2x00dev, WMM_CWMIN_CFG, reg);
7372
7373         rt2800_register_read(rt2x00dev, WMM_CWMAX_CFG, &reg);
7374         rt2x00_set_field32(&reg, field, queue->cw_max);
7375         rt2800_register_write(rt2x00dev, WMM_CWMAX_CFG, reg);
7376
7377         /* Update EDCA registers */
7378         offset = EDCA_AC0_CFG + (sizeof(u32) * queue_idx);
7379
7380         rt2800_register_read(rt2x00dev, offset, &reg);
7381         rt2x00_set_field32(&reg, EDCA_AC0_CFG_TX_OP, queue->txop);
7382         rt2x00_set_field32(&reg, EDCA_AC0_CFG_AIFSN, queue->aifs);
7383         rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMIN, queue->cw_min);
7384         rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMAX, queue->cw_max);
7385         rt2800_register_write(rt2x00dev, offset, reg);
7386
7387         return 0;
7388 }
7389 EXPORT_SYMBOL_GPL(rt2800_conf_tx);
7390
7391 u64 rt2800_get_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
7392 {
7393         struct rt2x00_dev *rt2x00dev = hw->priv;
7394         u64 tsf;
7395         u32 reg;
7396
7397         rt2800_register_read(rt2x00dev, TSF_TIMER_DW1, &reg);
7398         tsf = (u64) rt2x00_get_field32(reg, TSF_TIMER_DW1_HIGH_WORD) << 32;
7399         rt2800_register_read(rt2x00dev, TSF_TIMER_DW0, &reg);
7400         tsf |= rt2x00_get_field32(reg, TSF_TIMER_DW0_LOW_WORD);
7401
7402         return tsf;
7403 }
7404 EXPORT_SYMBOL_GPL(rt2800_get_tsf);
7405
7406 int rt2800_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
7407                         enum ieee80211_ampdu_mlme_action action,
7408                         struct ieee80211_sta *sta, u16 tid, u16 *ssn,
7409                         u8 buf_size)
7410 {
7411         struct rt2x00_sta *sta_priv = (struct rt2x00_sta *)sta->drv_priv;
7412         int ret = 0;
7413
7414         /*
7415          * Don't allow aggregation for stations the hardware isn't aware
7416          * of because tx status reports for frames to an unknown station
7417          * always contain wcid=255 and thus we can't distinguish between
7418          * multiple stations which leads to unwanted situations when the
7419          * hw reorders frames due to aggregation.
7420          */
7421         if (sta_priv->wcid < 0)
7422                 return 1;
7423
7424         switch (action) {
7425         case IEEE80211_AMPDU_RX_START:
7426         case IEEE80211_AMPDU_RX_STOP:
7427                 /*
7428                  * The hw itself takes care of setting up BlockAck mechanisms.
7429                  * So, we only have to allow mac80211 to nagotiate a BlockAck
7430                  * agreement. Once that is done, the hw will BlockAck incoming
7431                  * AMPDUs without further setup.
7432                  */
7433                 break;
7434         case IEEE80211_AMPDU_TX_START:
7435                 ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid);
7436                 break;
7437         case IEEE80211_AMPDU_TX_STOP_CONT:
7438         case IEEE80211_AMPDU_TX_STOP_FLUSH:
7439         case IEEE80211_AMPDU_TX_STOP_FLUSH_CONT:
7440                 ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
7441                 break;
7442         case IEEE80211_AMPDU_TX_OPERATIONAL:
7443                 break;
7444         default:
7445                 rt2x00_warn((struct rt2x00_dev *)hw->priv,
7446                             "Unknown AMPDU action\n");
7447         }
7448
7449         return ret;
7450 }
7451 EXPORT_SYMBOL_GPL(rt2800_ampdu_action);
7452
7453 int rt2800_get_survey(struct ieee80211_hw *hw, int idx,
7454                       struct survey_info *survey)
7455 {
7456         struct rt2x00_dev *rt2x00dev = hw->priv;
7457         struct ieee80211_conf *conf = &hw->conf;
7458         u32 idle, busy, busy_ext;
7459
7460         if (idx != 0)
7461                 return -ENOENT;
7462
7463         survey->channel = conf->chandef.chan;
7464
7465         rt2800_register_read(rt2x00dev, CH_IDLE_STA, &idle);
7466         rt2800_register_read(rt2x00dev, CH_BUSY_STA, &busy);
7467         rt2800_register_read(rt2x00dev, CH_BUSY_STA_SEC, &busy_ext);
7468
7469         if (idle || busy) {
7470                 survey->filled = SURVEY_INFO_CHANNEL_TIME |
7471                                  SURVEY_INFO_CHANNEL_TIME_BUSY |
7472                                  SURVEY_INFO_CHANNEL_TIME_EXT_BUSY;
7473
7474                 survey->channel_time = (idle + busy) / 1000;
7475                 survey->channel_time_busy = busy / 1000;
7476                 survey->channel_time_ext_busy = busy_ext / 1000;
7477         }
7478
7479         if (!(hw->conf.flags & IEEE80211_CONF_OFFCHANNEL))
7480                 survey->filled |= SURVEY_INFO_IN_USE;
7481
7482         return 0;
7483
7484 }
7485 EXPORT_SYMBOL_GPL(rt2800_get_survey);
7486
7487 MODULE_AUTHOR(DRV_PROJECT ", Bartlomiej Zolnierkiewicz");
7488 MODULE_VERSION(DRV_VERSION);
7489 MODULE_DESCRIPTION("Ralink RT2800 library");
7490 MODULE_LICENSE("GPL");