drivers/net/wireless/rt2x00/rt73usb.c

   1 /*
   2         Copyright (C) 2004 - 2009 Ivo van Doorn <IvDoorn@gmail.com>
   3         <http://rt2x00.serialmonkey.com>
   4
   5         This program is free software; you can redistribute it and/or modify
   6         it under the terms of the GNU General Public License as published by
   7         the Free Software Foundation; either version 2 of the License, or
   8         (at your option) any later version.
   9
  10         This program is distributed in the hope that it will be useful,
  11         but WITHOUT ANY WARRANTY; without even the implied warranty of
  12         MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13         GNU General Public License for more details.
  14
  15         You should have received a copy of the GNU General Public License
  16         along with this program; if not, see <http://www.gnu.org/licenses/>.
  17  */
  18
  19 /*
  20         Module: rt73usb
  21         Abstract: rt73usb device specific routines.
  22         Supported chipsets: rt2571W & rt2671.
  23  */
  24
  25 #include <linux/crc-itu-t.h>
  26 #include <linux/delay.h>
  27 #include <linux/etherdevice.h>
  28 #include <linux/init.h>
  29 #include <linux/kernel.h>
  30 #include <linux/module.h>
  31 #include <linux/slab.h>
  32 #include <linux/usb.h>
  33
  34 #include "rt2x00.h"
  35 #include "rt2x00usb.h"
  36 #include "rt73usb.h"
  37
  38 /*
  39  * Allow hardware encryption to be disabled.
  40  */
  41 static bool modparam_nohwcrypt;
  42 module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO);
  43 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
  44
  45 /*
  46  * Register access.
  47  * All access to the CSR registers will go through the methods
  48  * rt2x00usb_register_read and rt2x00usb_register_write.
  49  * BBP and RF register require indirect register access,
  50  * and use the CSR registers BBPCSR and RFCSR to achieve this.
  51  * These indirect registers work with busy bits,
  52  * and we will try maximal REGISTER_BUSY_COUNT times to access
  53  * the register while taking a REGISTER_BUSY_DELAY us delay
  54  * between each attampt. When the busy bit is still set at that time,
  55  * the access attempt is considered to have failed,
  56  * and we will print an error.
  57  * The _lock versions must be used if you already hold the csr_mutex
  58  */
  59 #define WAIT_FOR_BBP(__dev, __reg) \
  60         rt2x00usb_regbusy_read((__dev), PHY_CSR3, PHY_CSR3_BUSY, (__reg))
  61 #define WAIT_FOR_RF(__dev, __reg) \
  62         rt2x00usb_regbusy_read((__dev), PHY_CSR4, PHY_CSR4_BUSY, (__reg))
  63
  64 static void rt73usb_bbp_write(struct rt2x00_dev *rt2x00dev,
  65                               const unsigned int word, const u8 value)
  66 {
  67         u32 reg;
  68
  69         mutex_lock(&rt2x00dev->csr_mutex);
  70
  71         /*
  72          * Wait until the BBP becomes available, afterwards we
  73          * can safely write the new data into the register.
  74          */
  75         if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
  76                 reg = 0;
  77                 rt2x00_set_field32(&reg, PHY_CSR3_VALUE, value);
  78                 rt2x00_set_field32(&reg, PHY_CSR3_REGNUM, word);
  79                 rt2x00_set_field32(&reg, PHY_CSR3_BUSY, 1);
  80                 rt2x00_set_field32(&reg, PHY_CSR3_READ_CONTROL, 0);
  81
  82                 rt2x00usb_register_write_lock(rt2x00dev, PHY_CSR3, reg);
  83         }
  84
  85         mutex_unlock(&rt2x00dev->csr_mutex);
  86 }
  87
  88 static void rt73usb_bbp_read(struct rt2x00_dev *rt2x00dev,
  89                              const unsigned int word, u8 *value)
  90 {
  91         u32 reg;
  92
  93         mutex_lock(&rt2x00dev->csr_mutex);
  94
  95         /*
  96          * Wait until the BBP becomes available, afterwards we
  97          * can safely write the read request into the register.
  98          * After the data has been written, we wait until hardware
  99          * returns the correct value, if at any time the register
 100          * doesn't become available in time, reg will be 0xffffffff
 101          * which means we return 0xff to the caller.
 102          */
 103         if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
 104                 reg = 0;
 105                 rt2x00_set_field32(&reg, PHY_CSR3_REGNUM, word);
 106                 rt2x00_set_field32(&reg, PHY_CSR3_BUSY, 1);
 107                 rt2x00_set_field32(&reg, PHY_CSR3_READ_CONTROL, 1);
 108
 109                 rt2x00usb_register_write_lock(rt2x00dev, PHY_CSR3, reg);
 110
 111                 WAIT_FOR_BBP(rt2x00dev, &reg);
 112         }
 113
 114         *value = rt2x00_get_field32(reg, PHY_CSR3_VALUE);
 115
 116         mutex_unlock(&rt2x00dev->csr_mutex);
 117 }
 118
 119 static void rt73usb_rf_write(struct rt2x00_dev *rt2x00dev,
 120                              const unsigned int word, const u32 value)
 121 {
 122         u32 reg;
 123
 124         mutex_lock(&rt2x00dev->csr_mutex);
 125
 126         /*
 127          * Wait until the RF becomes available, afterwards we
 128          * can safely write the new data into the register.
 129          */
 130         if (WAIT_FOR_RF(rt2x00dev, &reg)) {
 131                 reg = 0;
 132                 rt2x00_set_field32(&reg, PHY_CSR4_VALUE, value);
 133                 /*
 134                  * RF5225 and RF2527 contain 21 bits per RF register value,
 135                  * all others contain 20 bits.
 136                  */
 137                 rt2x00_set_field32(&reg, PHY_CSR4_NUMBER_OF_BITS,
 138                                    20 + (rt2x00_rf(rt2x00dev, RF5225) ||
 139                                          rt2x00_rf(rt2x00dev, RF2527)));
 140                 rt2x00_set_field32(&reg, PHY_CSR4_IF_SELECT, 0);
 141                 rt2x00_set_field32(&reg, PHY_CSR4_BUSY, 1);
 142
 143                 rt2x00usb_register_write_lock(rt2x00dev, PHY_CSR4, reg);
 144                 rt2x00_rf_write(rt2x00dev, word, value);
 145         }
 146
 147         mutex_unlock(&rt2x00dev->csr_mutex);
 148 }
 149
 150 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
 151 static const struct rt2x00debug rt73usb_rt2x00debug = {
 152         .owner  = THIS_MODULE,
 153         .csr    = {
 154                 .read           = rt2x00usb_register_read,
 155                 .write          = rt2x00usb_register_write,
 156                 .flags          = RT2X00DEBUGFS_OFFSET,
 157                 .word_base      = CSR_REG_BASE,
 158                 .word_size      = sizeof(u32),
 159                 .word_count     = CSR_REG_SIZE / sizeof(u32),
 160         },
 161         .eeprom = {
 162                 .read           = rt2x00_eeprom_read,
 163                 .write          = rt2x00_eeprom_write,
 164                 .word_base      = EEPROM_BASE,
 165                 .word_size      = sizeof(u16),
 166                 .word_count     = EEPROM_SIZE / sizeof(u16),
 167         },
 168         .bbp    = {
 169                 .read           = rt73usb_bbp_read,
 170                 .write          = rt73usb_bbp_write,
 171                 .word_base      = BBP_BASE,
 172                 .word_size      = sizeof(u8),
 173                 .word_count     = BBP_SIZE / sizeof(u8),
 174         },
 175         .rf     = {
 176                 .read           = rt2x00_rf_read,
 177                 .write          = rt73usb_rf_write,
 178                 .word_base      = RF_BASE,
 179                 .word_size      = sizeof(u32),
 180                 .word_count     = RF_SIZE / sizeof(u32),
 181         },
 182 };
 183 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
 184
 185 static int rt73usb_rfkill_poll(struct rt2x00_dev *rt2x00dev)
 186 {
 187         u32 reg;
 188
 189         rt2x00usb_register_read(rt2x00dev, MAC_CSR13, &reg);
 190         return rt2x00_get_field32(reg, MAC_CSR13_VAL7);
 191 }
 192
 193 #ifdef CONFIG_RT2X00_LIB_LEDS
 194 static void rt73usb_brightness_set(struct led_classdev *led_cdev,
 195                                    enum led_brightness brightness)
 196 {
 197         struct rt2x00_led *led =
 198            container_of(led_cdev, struct rt2x00_led, led_dev);
 199         unsigned int enabled = brightness != LED_OFF;
 200         unsigned int a_mode =
 201             (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_5GHZ);
 202         unsigned int bg_mode =
 203             (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
 204
 205         if (led->type == LED_TYPE_RADIO) {
 206                 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
 207                                    MCU_LEDCS_RADIO_STATUS, enabled);
 208
 209                 rt2x00usb_vendor_request_sw(led->rt2x00dev, USB_LED_CONTROL,
 210                                             0, led->rt2x00dev->led_mcu_reg,
 211                                             REGISTER_TIMEOUT);
 212         } else if (led->type == LED_TYPE_ASSOC) {
 213                 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
 214                                    MCU_LEDCS_LINK_BG_STATUS, bg_mode);
 215                 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
 216                                    MCU_LEDCS_LINK_A_STATUS, a_mode);
 217
 218                 rt2x00usb_vendor_request_sw(led->rt2x00dev, USB_LED_CONTROL,
 219                                             0, led->rt2x00dev->led_mcu_reg,
 220                                             REGISTER_TIMEOUT);
 221         } else if (led->type == LED_TYPE_QUALITY) {
 222                 /*
 223                  * The brightness is divided into 6 levels (0 - 5),
 224                  * this means we need to convert the brightness
 225                  * argument into the matching level within that range.
 226                  */
 227                 rt2x00usb_vendor_request_sw(led->rt2x00dev, USB_LED_CONTROL,
 228                                             brightness / (LED_FULL / 6),
 229                                             led->rt2x00dev->led_mcu_reg,
 230                                             REGISTER_TIMEOUT);
 231         }
 232 }
 233
 234 static int rt73usb_blink_set(struct led_classdev *led_cdev,
 235                              unsigned long *delay_on,
 236                              unsigned long *delay_off)
 237 {
 238         struct rt2x00_led *led =
 239             container_of(led_cdev, struct rt2x00_led, led_dev);
 240         u32 reg;
 241
 242         rt2x00usb_register_read(led->rt2x00dev, MAC_CSR14, &reg);
 243         rt2x00_set_field32(&reg, MAC_CSR14_ON_PERIOD, *delay_on);
 244         rt2x00_set_field32(&reg, MAC_CSR14_OFF_PERIOD, *delay_off);
 245         rt2x00usb_register_write(led->rt2x00dev, MAC_CSR14, reg);
 246
 247         return 0;
 248 }
 249
 250 static void rt73usb_init_led(struct rt2x00_dev *rt2x00dev,
 251                              struct rt2x00_led *led,
 252                              enum led_type type)
 253 {
 254         led->rt2x00dev = rt2x00dev;
 255         led->type = type;
 256         led->led_dev.brightness_set = rt73usb_brightness_set;
 257         led->led_dev.blink_set = rt73usb_blink_set;
 258         led->flags = LED_INITIALIZED;
 259 }
 260 #endif /* CONFIG_RT2X00_LIB_LEDS */
 261
 262 /*
 263  * Configuration handlers.
 264  */
 265 static int rt73usb_config_shared_key(struct rt2x00_dev *rt2x00dev,
 266                                      struct rt2x00lib_crypto *crypto,
 267                                      struct ieee80211_key_conf *key)
 268 {
 269         struct hw_key_entry key_entry;
 270         struct rt2x00_field32 field;
 271         u32 mask;
 272         u32 reg;
 273
 274         if (crypto->cmd == SET_KEY) {
 275                 /*
 276                  * rt2x00lib can't determine the correct free
 277                  * key_idx for shared keys. We have 1 register
 278                  * with key valid bits. The goal is simple, read
 279                  * the register, if that is full we have no slots
 280                  * left.
 281                  * Note that each BSS is allowed to have up to 4
 282                  * shared keys, so put a mask over the allowed
 283                  * entries.
 284                  */
 285                 mask = (0xf << crypto->bssidx);
 286
 287                 rt2x00usb_register_read(rt2x00dev, SEC_CSR0, &reg);
 288                 reg &= mask;
 289
 290                 if (reg && reg == mask)
 291                         return -ENOSPC;
 292
 293                 key->hw_key_idx += reg ? ffz(reg) : 0;
 294
 295                 /*
 296                  * Upload key to hardware
 297                  */
 298                 memcpy(key_entry.key, crypto->key,
 299                        sizeof(key_entry.key));
 300                 memcpy(key_entry.tx_mic, crypto->tx_mic,
 301                        sizeof(key_entry.tx_mic));
 302                 memcpy(key_entry.rx_mic, crypto->rx_mic,
 303                        sizeof(key_entry.rx_mic));
 304
 305                 reg = SHARED_KEY_ENTRY(key->hw_key_idx);
 306                 rt2x00usb_register_multiwrite(rt2x00dev, reg,
 307                                               &key_entry, sizeof(key_entry));
 308
 309                 /*
 310                  * The cipher types are stored over 2 registers.
 311                  * bssidx 0 and 1 keys are stored in SEC_CSR1 and
 312                  * bssidx 1 and 2 keys are stored in SEC_CSR5.
 313                  * Using the correct defines correctly will cause overhead,
 314                  * so just calculate the correct offset.
 315                  */
 316                 if (key->hw_key_idx < 8) {
 317                         field.bit_offset = (3 * key->hw_key_idx);
 318                         field.bit_mask = 0x7 << field.bit_offset;
 319
 320                         rt2x00usb_register_read(rt2x00dev, SEC_CSR1, &reg);
 321                         rt2x00_set_field32(&reg, field, crypto->cipher);
 322                         rt2x00usb_register_write(rt2x00dev, SEC_CSR1, reg);
 323                 } else {
 324                         field.bit_offset = (3 * (key->hw_key_idx - 8));
 325                         field.bit_mask = 0x7 << field.bit_offset;
 326
 327                         rt2x00usb_register_read(rt2x00dev, SEC_CSR5, &reg);
 328                         rt2x00_set_field32(&reg, field, crypto->cipher);
 329                         rt2x00usb_register_write(rt2x00dev, SEC_CSR5, reg);
 330                 }
 331
 332                 /*
 333                  * The driver does not support the IV/EIV generation
 334                  * in hardware. However it doesn't support the IV/EIV
 335                  * inside the ieee80211 frame either, but requires it
 336                  * to be provided separately for the descriptor.
 337                  * rt2x00lib will cut the IV/EIV data out of all frames
 338                  * given to us by mac80211, but we must tell mac80211
 339                  * to generate the IV/EIV data.
 340                  */
 341                 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
 342         }
 343
 344         /*
 345          * SEC_CSR0 contains only single-bit fields to indicate
 346          * a particular key is valid. Because using the FIELD32()
 347          * defines directly will cause a lot of overhead we use
 348          * a calculation to determine the correct bit directly.
 349          */
 350         mask = 1 << key->hw_key_idx;
 351
 352         rt2x00usb_register_read(rt2x00dev, SEC_CSR0, &reg);
 353         if (crypto->cmd == SET_KEY)
 354                 reg |= mask;
 355         else if (crypto->cmd == DISABLE_KEY)
 356                 reg &= ~mask;
 357         rt2x00usb_register_write(rt2x00dev, SEC_CSR0, reg);
 358
 359         return 0;
 360 }
 361
 362 static int rt73usb_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
 363                                        struct rt2x00lib_crypto *crypto,
 364                                        struct ieee80211_key_conf *key)
 365 {
 366         struct hw_pairwise_ta_entry addr_entry;
 367         struct hw_key_entry key_entry;
 368         u32 mask;
 369         u32 reg;
 370
 371         if (crypto->cmd == SET_KEY) {
 372                 /*
 373                  * rt2x00lib can't determine the correct free
 374                  * key_idx for pairwise keys. We have 2 registers
 375                  * with key valid bits. The goal is simple, read
 376                  * the first register, if that is full move to
 377                  * the next register.
 378                  * When both registers are full, we drop the key,
 379                  * otherwise we use the first invalid entry.
 380                  */
 381                 rt2x00usb_register_read(rt2x00dev, SEC_CSR2, &reg);
 382                 if (reg && reg == ~0) {
 383                         key->hw_key_idx = 32;
 384                         rt2x00usb_register_read(rt2x00dev, SEC_CSR3, &reg);
 385                         if (reg && reg == ~0)
 386                                 return -ENOSPC;
 387                 }
 388
 389                 key->hw_key_idx += reg ? ffz(reg) : 0;
 390
 391                 /*
 392                  * Upload key to hardware
 393                  */
 394                 memcpy(key_entry.key, crypto->key,
 395                        sizeof(key_entry.key));
 396                 memcpy(key_entry.tx_mic, crypto->tx_mic,
 397                        sizeof(key_entry.tx_mic));
 398                 memcpy(key_entry.rx_mic, crypto->rx_mic,
 399                        sizeof(key_entry.rx_mic));
 400
 401                 reg = PAIRWISE_KEY_ENTRY(key->hw_key_idx);
 402                 rt2x00usb_register_multiwrite(rt2x00dev, reg,
 403                                               &key_entry, sizeof(key_entry));
 404
 405                 /*
 406                  * Send the address and cipher type to the hardware register.
 407                  */
 408                 memset(&addr_entry, 0, sizeof(addr_entry));
 409                 memcpy(&addr_entry, crypto->address, ETH_ALEN);
 410                 addr_entry.cipher = crypto->cipher;
 411
 412                 reg = PAIRWISE_TA_ENTRY(key->hw_key_idx);
 413                 rt2x00usb_register_multiwrite(rt2x00dev, reg,
 414                                             &addr_entry, sizeof(addr_entry));
 415
 416                 /*
 417                  * Enable pairwise lookup table for given BSS idx,
 418                  * without this received frames will not be decrypted
 419                  * by the hardware.
 420                  */
 421                 rt2x00usb_register_read(rt2x00dev, SEC_CSR4, &reg);
 422                 reg |= (1 << crypto->bssidx);
 423                 rt2x00usb_register_write(rt2x00dev, SEC_CSR4, reg);
 424
 425                 /*
 426                  * The driver does not support the IV/EIV generation
 427                  * in hardware. However it doesn't support the IV/EIV
 428                  * inside the ieee80211 frame either, but requires it
 429                  * to be provided separately for the descriptor.
 430                  * rt2x00lib will cut the IV/EIV data out of all frames
 431                  * given to us by mac80211, but we must tell mac80211
 432                  * to generate the IV/EIV data.
 433                  */
 434                 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
 435         }
 436
 437         /*
 438          * SEC_CSR2 and SEC_CSR3 contain only single-bit fields to indicate
 439          * a particular key is valid. Because using the FIELD32()
 440          * defines directly will cause a lot of overhead we use
 441          * a calculation to determine the correct bit directly.
 442          */
 443         if (key->hw_key_idx < 32) {
 444                 mask = 1 << key->hw_key_idx;
 445
 446                 rt2x00usb_register_read(rt2x00dev, SEC_CSR2, &reg);
 447                 if (crypto->cmd == SET_KEY)
 448                         reg |= mask;
 449                 else if (crypto->cmd == DISABLE_KEY)
 450                         reg &= ~mask;
 451                 rt2x00usb_register_write(rt2x00dev, SEC_CSR2, reg);
 452         } else {
 453                 mask = 1 << (key->hw_key_idx - 32);
 454
 455                 rt2x00usb_register_read(rt2x00dev, SEC_CSR3, &reg);
 456                 if (crypto->cmd == SET_KEY)
 457                         reg |= mask;
 458                 else if (crypto->cmd == DISABLE_KEY)
 459                         reg &= ~mask;
 460                 rt2x00usb_register_write(rt2x00dev, SEC_CSR3, reg);
 461         }
 462
 463         return 0;
 464 }
 465
 466 static void rt73usb_config_filter(struct rt2x00_dev *rt2x00dev,
 467                                   const unsigned int filter_flags)
 468 {
 469         u32 reg;
 470
 471         /*
 472          * Start configuration steps.
 473          * Note that the version error will always be dropped
 474          * and broadcast frames will always be accepted since
 475          * there is no filter for it at this time.
 476          */
 477         rt2x00usb_register_read(rt2x00dev, TXRX_CSR0, &reg);
 478         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_CRC,
 479                            !(filter_flags & FIF_FCSFAIL));
 480         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_PHYSICAL,
 481                            !(filter_flags & FIF_PLCPFAIL));
 482         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_CONTROL,
 483                            !(filter_flags & (FIF_CONTROL | FIF_PSPOLL)));
 484         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_NOT_TO_ME,
 485                            !(filter_flags & FIF_PROMISC_IN_BSS));
 486         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_TO_DS,
 487                            !(filter_flags & FIF_PROMISC_IN_BSS) &&
 488                            !rt2x00dev->intf_ap_count);
 489         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_VERSION_ERROR, 1);
 490         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_MULTICAST,
 491                            !(filter_flags & FIF_ALLMULTI));
 492         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_BROADCAST, 0);
 493         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_ACK_CTS,
 494                            !(filter_flags & FIF_CONTROL));
 495         rt2x00usb_register_write(rt2x00dev, TXRX_CSR0, reg);
 496 }
 497
 498 static void rt73usb_config_intf(struct rt2x00_dev *rt2x00dev,
 499                                 struct rt2x00_intf *intf,
 500                                 struct rt2x00intf_conf *conf,
 501                                 const unsigned int flags)
 502 {
 503         u32 reg;
 504
 505         if (flags & CONFIG_UPDATE_TYPE) {
 506                 /*
 507                  * Enable synchronisation.
 508                  */
 509                 rt2x00usb_register_read(rt2x00dev, TXRX_CSR9, &reg);
 510                 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_SYNC, conf->sync);
 511                 rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, reg);
 512         }
 513
 514         if (flags & CONFIG_UPDATE_MAC) {
 515                 reg = le32_to_cpu(conf->mac[1]);
 516                 rt2x00_set_field32(&reg, MAC_CSR3_UNICAST_TO_ME_MASK, 0xff);
 517                 conf->mac[1] = cpu_to_le32(reg);
 518
 519                 rt2x00usb_register_multiwrite(rt2x00dev, MAC_CSR2,
 520                                             conf->mac, sizeof(conf->mac));
 521         }
 522
 523         if (flags & CONFIG_UPDATE_BSSID) {
 524                 reg = le32_to_cpu(conf->bssid[1]);
 525                 rt2x00_set_field32(&reg, MAC_CSR5_BSS_ID_MASK, 3);
 526                 conf->bssid[1] = cpu_to_le32(reg);
 527
 528                 rt2x00usb_register_multiwrite(rt2x00dev, MAC_CSR4,
 529                                             conf->bssid, sizeof(conf->bssid));
 530         }
 531 }
 532
 533 static void rt73usb_config_erp(struct rt2x00_dev *rt2x00dev,
 534                                struct rt2x00lib_erp *erp,
 535                                u32 changed)
 536 {
 537         u32 reg;
 538
 539         rt2x00usb_register_read(rt2x00dev, TXRX_CSR0, &reg);
 540         rt2x00_set_field32(&reg, TXRX_CSR0_RX_ACK_TIMEOUT, 0x32);
 541         rt2x00_set_field32(&reg, TXRX_CSR0_TSF_OFFSET, IEEE80211_HEADER);
 542         rt2x00usb_register_write(rt2x00dev, TXRX_CSR0, reg);
 543
 544         if (changed & BSS_CHANGED_ERP_PREAMBLE) {
 545                 rt2x00usb_register_read(rt2x00dev, TXRX_CSR4, &reg);
 546                 rt2x00_set_field32(&reg, TXRX_CSR4_AUTORESPOND_ENABLE, 1);
 547                 rt2x00_set_field32(&reg, TXRX_CSR4_AUTORESPOND_PREAMBLE,
 548                                    !!erp->short_preamble);
 549                 rt2x00usb_register_write(rt2x00dev, TXRX_CSR4, reg);
 550         }
 551
 552         if (changed & BSS_CHANGED_BASIC_RATES)
 553                 rt2x00usb_register_write(rt2x00dev, TXRX_CSR5,
 554                                          erp->basic_rates);
 555
 556         if (changed & BSS_CHANGED_BEACON_INT) {
 557                 rt2x00usb_register_read(rt2x00dev, TXRX_CSR9, &reg);
 558                 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_INTERVAL,
 559                                    erp->beacon_int * 16);
 560                 rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, reg);
 561         }
 562
 563         if (changed & BSS_CHANGED_ERP_SLOT) {
 564                 rt2x00usb_register_read(rt2x00dev, MAC_CSR9, &reg);
 565                 rt2x00_set_field32(&reg, MAC_CSR9_SLOT_TIME, erp->slot_time);
 566                 rt2x00usb_register_write(rt2x00dev, MAC_CSR9, reg);
 567
 568                 rt2x00usb_register_read(rt2x00dev, MAC_CSR8, &reg);
 569                 rt2x00_set_field32(&reg, MAC_CSR8_SIFS, erp->sifs);
 570                 rt2x00_set_field32(&reg, MAC_CSR8_SIFS_AFTER_RX_OFDM, 3);
 571                 rt2x00_set_field32(&reg, MAC_CSR8_EIFS, erp->eifs);
 572                 rt2x00usb_register_write(rt2x00dev, MAC_CSR8, reg);
 573         }
 574 }
 575
 576 static void rt73usb_config_antenna_5x(struct rt2x00_dev *rt2x00dev,
 577                                       struct antenna_setup *ant)
 578 {
 579         u8 r3;
 580         u8 r4;
 581         u8 r77;
 582         u8 temp;
 583
 584         rt73usb_bbp_read(rt2x00dev, 3, &r3);
 585         rt73usb_bbp_read(rt2x00dev, 4, &r4);
 586         rt73usb_bbp_read(rt2x00dev, 77, &r77);
 587
 588         rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, 0);
 589
 590         /*
 591          * Configure the RX antenna.
 592          */
 593         switch (ant->rx) {
 594         case ANTENNA_HW_DIVERSITY:
 595                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 2);
 596                 temp = !rt2x00_has_cap_frame_type(rt2x00dev) &&
 597                        (rt2x00dev->curr_band != IEEE80211_BAND_5GHZ);
 598                 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, temp);
 599                 break;
 600         case ANTENNA_A:
 601                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
 602                 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0);
 603                 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ)
 604                         rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
 605                 else
 606                         rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
 607                 break;
 608         case ANTENNA_B:
 609         default:
 610                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
 611                 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0);
 612                 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ)
 613                         rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
 614                 else
 615                         rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
 616                 break;
 617         }
 618
 619         rt73usb_bbp_write(rt2x00dev, 77, r77);
 620         rt73usb_bbp_write(rt2x00dev, 3, r3);
 621         rt73usb_bbp_write(rt2x00dev, 4, r4);
 622 }
 623
 624 static void rt73usb_config_antenna_2x(struct rt2x00_dev *rt2x00dev,
 625                                       struct antenna_setup *ant)
 626 {
 627         u8 r3;
 628         u8 r4;
 629         u8 r77;
 630
 631         rt73usb_bbp_read(rt2x00dev, 3, &r3);
 632         rt73usb_bbp_read(rt2x00dev, 4, &r4);
 633         rt73usb_bbp_read(rt2x00dev, 77, &r77);
 634
 635         rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, 0);
 636         rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END,
 637                           !rt2x00_has_cap_frame_type(rt2x00dev));
 638
 639         /*
 640          * Configure the RX antenna.
 641          */
 642         switch (ant->rx) {
 643         case ANTENNA_HW_DIVERSITY:
 644                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 2);
 645                 break;
 646         case ANTENNA_A:
 647                 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
 648                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
 649                 break;
 650         case ANTENNA_B:
 651         default:
 652                 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
 653                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
 654                 break;
 655         }
 656
 657         rt73usb_bbp_write(rt2x00dev, 77, r77);
 658         rt73usb_bbp_write(rt2x00dev, 3, r3);
 659         rt73usb_bbp_write(rt2x00dev, 4, r4);
 660 }
 661
 662 struct antenna_sel {
 663         u8 word;
 664         /*
 665          * value[0] -> non-LNA
 666          * value[1] -> LNA
 667          */
 668         u8 value[2];
 669 };
 670
 671 static const struct antenna_sel antenna_sel_a[] = {
 672         { 96,  { 0x58, 0x78 } },
 673         { 104, { 0x38, 0x48 } },
 674         { 75,  { 0xfe, 0x80 } },
 675         { 86,  { 0xfe, 0x80 } },
 676         { 88,  { 0xfe, 0x80 } },
 677         { 35,  { 0x60, 0x60 } },
 678         { 97,  { 0x58, 0x58 } },
 679         { 98,  { 0x58, 0x58 } },
 680 };
 681
 682 static const struct antenna_sel antenna_sel_bg[] = {
 683         { 96,  { 0x48, 0x68 } },
 684         { 104, { 0x2c, 0x3c } },
 685         { 75,  { 0xfe, 0x80 } },
 686         { 86,  { 0xfe, 0x80 } },
 687         { 88,  { 0xfe, 0x80 } },
 688         { 35,  { 0x50, 0x50 } },
 689         { 97,  { 0x48, 0x48 } },
 690         { 98,  { 0x48, 0x48 } },
 691 };
 692
 693 static void rt73usb_config_ant(struct rt2x00_dev *rt2x00dev,
 694                                struct antenna_setup *ant)
 695 {
 696         const struct antenna_sel *sel;
 697         unsigned int lna;
 698         unsigned int i;
 699         u32 reg;
 700
 701         /*
 702          * We should never come here because rt2x00lib is supposed
 703          * to catch this and send us the correct antenna explicitely.
 704          */
 705         BUG_ON(ant->rx == ANTENNA_SW_DIVERSITY ||
 706                ant->tx == ANTENNA_SW_DIVERSITY);
 707
 708         if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ) {
 709                 sel = antenna_sel_a;
 710                 lna = rt2x00_has_cap_external_lna_a(rt2x00dev);
 711         } else {
 712                 sel = antenna_sel_bg;
 713                 lna = rt2x00_has_cap_external_lna_bg(rt2x00dev);
 714         }
 715
 716         for (i = 0; i < ARRAY_SIZE(antenna_sel_a); i++)
 717                 rt73usb_bbp_write(rt2x00dev, sel[i].word, sel[i].value[lna]);
 718
 719         rt2x00usb_register_read(rt2x00dev, PHY_CSR0, &reg);
 720
 721         rt2x00_set_field32(&reg, PHY_CSR0_PA_PE_BG,
 722                            (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ));
 723         rt2x00_set_field32(&reg, PHY_CSR0_PA_PE_A,
 724                            (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ));
 725
 726         rt2x00usb_register_write(rt2x00dev, PHY_CSR0, reg);
 727
 728         if (rt2x00_rf(rt2x00dev, RF5226) || rt2x00_rf(rt2x00dev, RF5225))
 729                 rt73usb_config_antenna_5x(rt2x00dev, ant);
 730         else if (rt2x00_rf(rt2x00dev, RF2528) || rt2x00_rf(rt2x00dev, RF2527))
 731                 rt73usb_config_antenna_2x(rt2x00dev, ant);
 732 }
 733
 734 static void rt73usb_config_lna_gain(struct rt2x00_dev *rt2x00dev,
 735                                     struct rt2x00lib_conf *libconf)
 736 {
 737         u16 eeprom;
 738         short lna_gain = 0;
 739
 740         if (libconf->conf->chandef.chan->band == IEEE80211_BAND_2GHZ) {
 741                 if (rt2x00_has_cap_external_lna_bg(rt2x00dev))
 742                         lna_gain += 14;
 743
 744                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &eeprom);
 745                 lna_gain -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_BG_1);
 746         } else {
 747                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &eeprom);
 748                 lna_gain -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_A_1);
 749         }
 750
 751         rt2x00dev->lna_gain = lna_gain;
 752 }
 753
 754 static void rt73usb_config_channel(struct rt2x00_dev *rt2x00dev,
 755                                    struct rf_channel *rf, const int txpower)
 756 {
 757         u8 r3;
 758         u8 r94;
 759         u8 smart;
 760
 761         rt2x00_set_field32(&rf->rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));
 762         rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
 763
 764         smart = !(rt2x00_rf(rt2x00dev, RF5225) || rt2x00_rf(rt2x00dev, RF2527));
 765
 766         rt73usb_bbp_read(rt2x00dev, 3, &r3);
 767         rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, smart);
 768         rt73usb_bbp_write(rt2x00dev, 3, r3);
 769
 770         r94 = 6;
 771         if (txpower > MAX_TXPOWER && txpower <= (MAX_TXPOWER + r94))
 772                 r94 += txpower - MAX_TXPOWER;
 773         else if (txpower < MIN_TXPOWER && txpower >= (MIN_TXPOWER - r94))
 774                 r94 += txpower;
 775         rt73usb_bbp_write(rt2x00dev, 94, r94);
 776
 777         rt73usb_rf_write(rt2x00dev, 1, rf->rf1);
 778         rt73usb_rf_write(rt2x00dev, 2, rf->rf2);
 779         rt73usb_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
 780         rt73usb_rf_write(rt2x00dev, 4, rf->rf4);
 781
 782         rt73usb_rf_write(rt2x00dev, 1, rf->rf1);
 783         rt73usb_rf_write(rt2x00dev, 2, rf->rf2);
 784         rt73usb_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
 785         rt73usb_rf_write(rt2x00dev, 4, rf->rf4);
 786
 787         rt73usb_rf_write(rt2x00dev, 1, rf->rf1);
 788         rt73usb_rf_write(rt2x00dev, 2, rf->rf2);
 789         rt73usb_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
 790         rt73usb_rf_write(rt2x00dev, 4, rf->rf4);
 791
 792         udelay(10);
 793 }
 794
 795 static void rt73usb_config_txpower(struct rt2x00_dev *rt2x00dev,
 796                                    const int txpower)
 797 {
 798         struct rf_channel rf;
 799
 800         rt2x00_rf_read(rt2x00dev, 1, &rf.rf1);
 801         rt2x00_rf_read(rt2x00dev, 2, &rf.rf2);
 802         rt2x00_rf_read(rt2x00dev, 3, &rf.rf3);
 803         rt2x00_rf_read(rt2x00dev, 4, &rf.rf4);
 804
 805         rt73usb_config_channel(rt2x00dev, &rf, txpower);
 806 }
 807
 808 static void rt73usb_config_retry_limit(struct rt2x00_dev *rt2x00dev,
 809                                        struct rt2x00lib_conf *libconf)
 810 {
 811         u32 reg;
 812
 813         rt2x00usb_register_read(rt2x00dev, TXRX_CSR4, &reg);
 814         rt2x00_set_field32(&reg, TXRX_CSR4_OFDM_TX_RATE_DOWN, 1);
 815         rt2x00_set_field32(&reg, TXRX_CSR4_OFDM_TX_RATE_STEP, 0);
 816         rt2x00_set_field32(&reg, TXRX_CSR4_OFDM_TX_FALLBACK_CCK, 0);
 817         rt2x00_set_field32(&reg, TXRX_CSR4_LONG_RETRY_LIMIT,
 818                            libconf->conf->long_frame_max_tx_count);
 819         rt2x00_set_field32(&reg, TXRX_CSR4_SHORT_RETRY_LIMIT,
 820                            libconf->conf->short_frame_max_tx_count);
 821         rt2x00usb_register_write(rt2x00dev, TXRX_CSR4, reg);
 822 }
 823
 824 static void rt73usb_config_ps(struct rt2x00_dev *rt2x00dev,
 825                                 struct rt2x00lib_conf *libconf)
 826 {
 827         enum dev_state state =
 828             (libconf->conf->flags & IEEE80211_CONF_PS) ?
 829                 STATE_SLEEP : STATE_AWAKE;
 830         u32 reg;
 831
 832         if (state == STATE_SLEEP) {
 833                 rt2x00usb_register_read(rt2x00dev, MAC_CSR11, &reg);
 834                 rt2x00_set_field32(&reg, MAC_CSR11_DELAY_AFTER_TBCN,
 835                                    rt2x00dev->beacon_int - 10);
 836                 rt2x00_set_field32(&reg, MAC_CSR11_TBCN_BEFORE_WAKEUP,
 837                                    libconf->conf->listen_interval - 1);
 838                 rt2x00_set_field32(&reg, MAC_CSR11_WAKEUP_LATENCY, 5);
 839
 840                 /* We must first disable autowake before it can be enabled */
 841                 rt2x00_set_field32(&reg, MAC_CSR11_AUTOWAKE, 0);
 842                 rt2x00usb_register_write(rt2x00dev, MAC_CSR11, reg);
 843
 844                 rt2x00_set_field32(&reg, MAC_CSR11_AUTOWAKE, 1);
 845                 rt2x00usb_register_write(rt2x00dev, MAC_CSR11, reg);
 846
 847                 rt2x00usb_vendor_request_sw(rt2x00dev, USB_DEVICE_MODE, 0,
 848                                             USB_MODE_SLEEP, REGISTER_TIMEOUT);
 849         } else {
 850                 rt2x00usb_register_read(rt2x00dev, MAC_CSR11, &reg);
 851                 rt2x00_set_field32(&reg, MAC_CSR11_DELAY_AFTER_TBCN, 0);
 852                 rt2x00_set_field32(&reg, MAC_CSR11_TBCN_BEFORE_WAKEUP, 0);
 853                 rt2x00_set_field32(&reg, MAC_CSR11_AUTOWAKE, 0);
 854                 rt2x00_set_field32(&reg, MAC_CSR11_WAKEUP_LATENCY, 0);
 855                 rt2x00usb_register_write(rt2x00dev, MAC_CSR11, reg);
 856
 857                 rt2x00usb_vendor_request_sw(rt2x00dev, USB_DEVICE_MODE, 0,
 858                                             USB_MODE_WAKEUP, REGISTER_TIMEOUT);
 859         }
 860 }
 861
 862 static void rt73usb_config(struct rt2x00_dev *rt2x00dev,
 863                            struct rt2x00lib_conf *libconf,
 864                            const unsigned int flags)
 865 {
 866         /* Always recalculate LNA gain before changing configuration */
 867         rt73usb_config_lna_gain(rt2x00dev, libconf);
 868
 869         if (flags & IEEE80211_CONF_CHANGE_CHANNEL)
 870                 rt73usb_config_channel(rt2x00dev, &libconf->rf,
 871                                        libconf->conf->power_level);
 872         if ((flags & IEEE80211_CONF_CHANGE_POWER) &&
 873             !(flags & IEEE80211_CONF_CHANGE_CHANNEL))
 874                 rt73usb_config_txpower(rt2x00dev, libconf->conf->power_level);
 875         if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
 876                 rt73usb_config_retry_limit(rt2x00dev, libconf);
 877         if (flags & IEEE80211_CONF_CHANGE_PS)
 878                 rt73usb_config_ps(rt2x00dev, libconf);
 879 }
 880
 881 /*
 882  * Link tuning
 883  */
 884 static void rt73usb_link_stats(struct rt2x00_dev *rt2x00dev,
 885                                struct link_qual *qual)
 886 {
 887         u32 reg;
 888
 889         /*
 890          * Update FCS error count from register.
 891          */
 892         rt2x00usb_register_read(rt2x00dev, STA_CSR0, &reg);
 893         qual->rx_failed = rt2x00_get_field32(reg, STA_CSR0_FCS_ERROR);
 894
 895         /*
 896          * Update False CCA count from register.
 897          */
 898         rt2x00usb_register_read(rt2x00dev, STA_CSR1, &reg);
 899         qual->false_cca = rt2x00_get_field32(reg, STA_CSR1_FALSE_CCA_ERROR);
 900 }
 901
 902 static inline void rt73usb_set_vgc(struct rt2x00_dev *rt2x00dev,
 903                                    struct link_qual *qual, u8 vgc_level)
 904 {
 905         if (qual->vgc_level != vgc_level) {
 906                 rt73usb_bbp_write(rt2x00dev, 17, vgc_level);
 907                 qual->vgc_level = vgc_level;
 908                 qual->vgc_level_reg = vgc_level;
 909         }
 910 }
 911
 912 static void rt73usb_reset_tuner(struct rt2x00_dev *rt2x00dev,
 913                                 struct link_qual *qual)
 914 {
 915         rt73usb_set_vgc(rt2x00dev, qual, 0x20);
 916 }
 917
 918 static void rt73usb_link_tuner(struct rt2x00_dev *rt2x00dev,
 919                                struct link_qual *qual, const u32 count)
 920 {
 921         u8 up_bound;
 922         u8 low_bound;
 923
 924         /*
 925          * Determine r17 bounds.
 926          */
 927         if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ) {
 928                 low_bound = 0x28;
 929                 up_bound = 0x48;
 930
 931                 if (rt2x00_has_cap_external_lna_a(rt2x00dev)) {
 932                         low_bound += 0x10;
 933                         up_bound += 0x10;
 934                 }
 935         } else {
 936                 if (qual->rssi > -82) {
 937                         low_bound = 0x1c;
 938                         up_bound = 0x40;
 939                 } else if (qual->rssi > -84) {
 940                         low_bound = 0x1c;
 941                         up_bound = 0x20;
 942                 } else {
 943                         low_bound = 0x1c;
 944                         up_bound = 0x1c;
 945                 }
 946
 947                 if (rt2x00_has_cap_external_lna_bg(rt2x00dev)) {
 948                         low_bound += 0x14;
 949                         up_bound += 0x10;
 950                 }
 951         }
 952
 953         /*
 954          * If we are not associated, we should go straight to the
 955          * dynamic CCA tuning.
 956          */
 957         if (!rt2x00dev->intf_associated)
 958                 goto dynamic_cca_tune;
 959
 960         /*
 961          * Special big-R17 for very short distance
 962          */
 963         if (qual->rssi > -35) {
 964                 rt73usb_set_vgc(rt2x00dev, qual, 0x60);
 965                 return;
 966         }
 967
 968         /*
 969          * Special big-R17 for short distance
 970          */
 971         if (qual->rssi >= -58) {
 972                 rt73usb_set_vgc(rt2x00dev, qual, up_bound);
 973                 return;
 974         }
 975
 976         /*
 977          * Special big-R17 for middle-short distance
 978          */
 979         if (qual->rssi >= -66) {
 980                 rt73usb_set_vgc(rt2x00dev, qual, low_bound + 0x10);
 981                 return;
 982         }
 983
 984         /*
 985          * Special mid-R17 for middle distance
 986          */
 987         if (qual->rssi >= -74) {
 988                 rt73usb_set_vgc(rt2x00dev, qual, low_bound + 0x08);
 989                 return;
 990         }
 991
 992         /*
 993          * Special case: Change up_bound based on the rssi.
 994          * Lower up_bound when rssi is weaker then -74 dBm.
 995          */
 996         up_bound -= 2 * (-74 - qual->rssi);
 997         if (low_bound > up_bound)
 998                 up_bound = low_bound;
 999
1000         if (qual->vgc_level > up_bound) {
1001                 rt73usb_set_vgc(rt2x00dev, qual, up_bound);
1002                 return;
1003         }
1004
1005 dynamic_cca_tune:
1006
1007         /*
1008          * r17 does not yet exceed upper limit, continue and base
1009          * the r17 tuning on the false CCA count.
1010          */
1011         if ((qual->false_cca > 512) && (qual->vgc_level < up_bound))
1012                 rt73usb_set_vgc(rt2x00dev, qual,
1013                                 min_t(u8, qual->vgc_level + 4, up_bound));
1014         else if ((qual->false_cca < 100) && (qual->vgc_level > low_bound))
1015                 rt73usb_set_vgc(rt2x00dev, qual,
1016                                 max_t(u8, qual->vgc_level - 4, low_bound));
1017 }
1018
1019 /*
1020  * Queue handlers.
1021  */
1022 static void rt73usb_start_queue(struct data_queue *queue)
1023 {
1024         struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
1025         u32 reg;
1026
1027         switch (queue->qid) {
1028         case QID_RX:
1029                 rt2x00usb_register_read(rt2x00dev, TXRX_CSR0, &reg);
1030                 rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX, 0);
1031                 rt2x00usb_register_write(rt2x00dev, TXRX_CSR0, reg);
1032                 break;
1033         case QID_BEACON:
1034                 rt2x00usb_register_read(rt2x00dev, TXRX_CSR9, &reg);
1035                 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 1);
1036                 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 1);
1037                 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 1);
1038                 rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, reg);
1039                 break;
1040         default:
1041                 break;
1042         }
1043 }
1044
1045 static void rt73usb_stop_queue(struct data_queue *queue)
1046 {
1047         struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
1048         u32 reg;
1049
1050         switch (queue->qid) {
1051         case QID_RX:
1052                 rt2x00usb_register_read(rt2x00dev, TXRX_CSR0, &reg);
1053                 rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX, 1);
1054                 rt2x00usb_register_write(rt2x00dev, TXRX_CSR0, reg);
1055                 break;
1056         case QID_BEACON:
1057                 rt2x00usb_register_read(rt2x00dev, TXRX_CSR9, &reg);
1058                 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 0);
1059                 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 0);
1060                 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 0);
1061                 rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, reg);
1062                 break;
1063         default:
1064                 break;
1065         }
1066 }
1067
1068 /*
1069  * Firmware functions
1070  */
1071 static char *rt73usb_get_firmware_name(struct rt2x00_dev *rt2x00dev)
1072 {
1073         return FIRMWARE_RT2571;
1074 }
1075
1076 static int rt73usb_check_firmware(struct rt2x00_dev *rt2x00dev,
1077                                   const u8 *data, const size_t len)
1078 {
1079         u16 fw_crc;
1080         u16 crc;
1081
1082         /*
1083          * Only support 2kb firmware files.
1084          */
1085         if (len != 2048)
1086                 return FW_BAD_LENGTH;
1087
1088         /*
1089          * The last 2 bytes in the firmware array are the crc checksum itself,
1090          * this means that we should never pass those 2 bytes to the crc
1091          * algorithm.
1092          */
1093         fw_crc = (data[len - 2] << 8 | data[len - 1]);
1094
1095         /*
1096          * Use the crc itu-t algorithm.
1097          */
1098         crc = crc_itu_t(0, data, len - 2);
1099         crc = crc_itu_t_byte(crc, 0);
1100         crc = crc_itu_t_byte(crc, 0);
1101
1102         return (fw_crc == crc) ? FW_OK : FW_BAD_CRC;
1103 }
1104
1105 static int rt73usb_load_firmware(struct rt2x00_dev *rt2x00dev,
1106                                  const u8 *data, const size_t len)
1107 {
1108         unsigned int i;
1109         int status;
1110         u32 reg;
1111
1112         /*
1113          * Wait for stable hardware.
1114          */
1115         for (i = 0; i < 100; i++) {
1116                 rt2x00usb_register_read(rt2x00dev, MAC_CSR0, &reg);
1117                 if (reg)
1118                         break;
1119                 msleep(1);
1120         }
1121
1122         if (!reg) {
1123                 rt2x00_err(rt2x00dev, "Unstable hardware\n");
1124                 return -EBUSY;
1125         }
1126
1127         /*
1128          * Write firmware to device.
1129          */
1130         rt2x00usb_register_multiwrite(rt2x00dev, FIRMWARE_IMAGE_BASE, data, len);
1131
1132         /*
1133          * Send firmware request to device to load firmware,
1134          * we need to specify a long timeout time.
1135          */
1136         status = rt2x00usb_vendor_request_sw(rt2x00dev, USB_DEVICE_MODE,
1137                                              0, USB_MODE_FIRMWARE,
1138                                              REGISTER_TIMEOUT_FIRMWARE);
1139         if (status < 0) {
1140                 rt2x00_err(rt2x00dev, "Failed to write Firmware to device\n");
1141                 return status;
1142         }
1143
1144         return 0;
1145 }
1146
1147 /*
1148  * Initialization functions.
1149  */
1150 static int rt73usb_init_registers(struct rt2x00_dev *rt2x00dev)
1151 {
1152         u32 reg;
1153
1154         rt2x00usb_register_read(rt2x00dev, TXRX_CSR0, &reg);
1155         rt2x00_set_field32(&reg, TXRX_CSR0_AUTO_TX_SEQ, 1);
1156         rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX, 0);
1157         rt2x00_set_field32(&reg, TXRX_CSR0_TX_WITHOUT_WAITING, 0);
1158         rt2x00usb_register_write(rt2x00dev, TXRX_CSR0, reg);
1159
1160         rt2x00usb_register_read(rt2x00dev, TXRX_CSR1, &reg);
1161         rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID0, 47); /* CCK Signal */
1162         rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID0_VALID, 1);
1163         rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID1, 30); /* Rssi */
1164         rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID1_VALID, 1);
1165         rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID2, 42); /* OFDM Rate */
1166         rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID2_VALID, 1);
1167         rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID3, 30); /* Rssi */
1168         rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID3_VALID, 1);
1169         rt2x00usb_register_write(rt2x00dev, TXRX_CSR1, reg);
1170
1171         /*
1172          * CCK TXD BBP registers
1173          */
1174         rt2x00usb_register_read(rt2x00dev, TXRX_CSR2, &reg);
1175         rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID0, 13);
1176         rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID0_VALID, 1);
1177         rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID1, 12);
1178         rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID1_VALID, 1);
1179         rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID2, 11);
1180         rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID2_VALID, 1);
1181         rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID3, 10);
1182         rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID3_VALID, 1);
1183         rt2x00usb_register_write(rt2x00dev, TXRX_CSR2, reg);
1184
1185         /*
1186          * OFDM TXD BBP registers
1187          */
1188         rt2x00usb_register_read(rt2x00dev, TXRX_CSR3, &reg);
1189         rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID0, 7);
1190         rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID0_VALID, 1);
1191         rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID1, 6);
1192         rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID1_VALID, 1);
1193         rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID2, 5);
1194         rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID2_VALID, 1);
1195         rt2x00usb_register_write(rt2x00dev, TXRX_CSR3, reg);
1196
1197         rt2x00usb_register_read(rt2x00dev, TXRX_CSR7, &reg);
1198         rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_6MBS, 59);
1199         rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_9MBS, 53);
1200         rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_12MBS, 49);
1201         rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_18MBS, 46);
1202         rt2x00usb_register_write(rt2x00dev, TXRX_CSR7, reg);
1203
1204         rt2x00usb_register_read(rt2x00dev, TXRX_CSR8, &reg);
1205         rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_24MBS, 44);
1206         rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_36MBS, 42);
1207         rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_48MBS, 42);
1208         rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_54MBS, 42);
1209         rt2x00usb_register_write(rt2x00dev, TXRX_CSR8, reg);
1210
1211         rt2x00usb_register_read(rt2x00dev, TXRX_CSR9, &reg);
1212         rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_INTERVAL, 0);
1213         rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 0);
1214         rt2x00_set_field32(&reg, TXRX_CSR9_TSF_SYNC, 0);
1215         rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 0);
1216         rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 0);
1217         rt2x00_set_field32(&reg, TXRX_CSR9_TIMESTAMP_COMPENSATE, 0);
1218         rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, reg);
1219
1220         rt2x00usb_register_write(rt2x00dev, TXRX_CSR15, 0x0000000f);
1221
1222         rt2x00usb_register_read(rt2x00dev, MAC_CSR6, &reg);
1223         rt2x00_set_field32(&reg, MAC_CSR6_MAX_FRAME_UNIT, 0xfff);
1224         rt2x00usb_register_write(rt2x00dev, MAC_CSR6, reg);
1225
1226         rt2x00usb_register_write(rt2x00dev, MAC_CSR10, 0x00000718);
1227
1228         if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
1229                 return -EBUSY;
1230
1231         rt2x00usb_register_write(rt2x00dev, MAC_CSR13, 0x00007f00);
1232
1233         /*
1234          * Invalidate all Shared Keys (SEC_CSR0),
1235          * and clear the Shared key Cipher algorithms (SEC_CSR1 & SEC_CSR5)
1236          */
1237         rt2x00usb_register_write(rt2x00dev, SEC_CSR0, 0x00000000);
1238         rt2x00usb_register_write(rt2x00dev, SEC_CSR1, 0x00000000);
1239         rt2x00usb_register_write(rt2x00dev, SEC_CSR5, 0x00000000);
1240
1241         reg = 0x000023b0;
1242         if (rt2x00_rf(rt2x00dev, RF5225) || rt2x00_rf(rt2x00dev, RF2527))
1243                 rt2x00_set_field32(&reg, PHY_CSR1_RF_RPI, 1);
1244         rt2x00usb_register_write(rt2x00dev, PHY_CSR1, reg);
1245
1246         rt2x00usb_register_write(rt2x00dev, PHY_CSR5, 0x00040a06);
1247         rt2x00usb_register_write(rt2x00dev, PHY_CSR6, 0x00080606);
1248         rt2x00usb_register_write(rt2x00dev, PHY_CSR7, 0x00000408);
1249
1250         rt2x00usb_register_read(rt2x00dev, MAC_CSR9, &reg);
1251         rt2x00_set_field32(&reg, MAC_CSR9_CW_SELECT, 0);
1252         rt2x00usb_register_write(rt2x00dev, MAC_CSR9, reg);
1253
1254         /*
1255          * Clear all beacons
1256          * For the Beacon base registers we only need to clear
1257          * the first byte since that byte contains the VALID and OWNER
1258          * bits which (when set to 0) will invalidate the entire beacon.
1259          */
1260         rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE0, 0);
1261         rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE1, 0);
1262         rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE2, 0);
1263         rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE3, 0);
1264
1265         /*
1266          * We must clear the error counters.
1267          * These registers are cleared on read,
1268          * so we may pass a useless variable to store the value.
1269          */
1270         rt2x00usb_register_read(rt2x00dev, STA_CSR0, &reg);
1271         rt2x00usb_register_read(rt2x00dev, STA_CSR1, &reg);
1272         rt2x00usb_register_read(rt2x00dev, STA_CSR2, &reg);
1273
1274         /*
1275          * Reset MAC and BBP registers.
1276          */
1277         rt2x00usb_register_read(rt2x00dev, MAC_CSR1, &reg);
1278         rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 1);
1279         rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 1);
1280         rt2x00usb_register_write(rt2x00dev, MAC_CSR1, reg);
1281
1282         rt2x00usb_register_read(rt2x00dev, MAC_CSR1, &reg);
1283         rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 0);
1284         rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 0);
1285         rt2x00usb_register_write(rt2x00dev, MAC_CSR1, reg);
1286
1287         rt2x00usb_register_read(rt2x00dev, MAC_CSR1, &reg);
1288         rt2x00_set_field32(&reg, MAC_CSR1_HOST_READY, 1);
1289         rt2x00usb_register_write(rt2x00dev, MAC_CSR1, reg);
1290
1291         return 0;
1292 }
1293
1294 static int rt73usb_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
1295 {
1296         unsigned int i;
1297         u8 value;
1298
1299         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1300                 rt73usb_bbp_read(rt2x00dev, 0, &value);
1301                 if ((value != 0xff) && (value != 0x00))
1302                         return 0;
1303                 udelay(REGISTER_BUSY_DELAY);
1304         }
1305
1306         rt2x00_err(rt2x00dev, "BBP register access failed, aborting\n");
1307         return -EACCES;
1308 }
1309
1310 static int rt73usb_init_bbp(struct rt2x00_dev *rt2x00dev)
1311 {
1312         unsigned int i;
1313         u16 eeprom;
1314         u8 reg_id;
1315         u8 value;
1316
1317         if (unlikely(rt73usb_wait_bbp_ready(rt2x00dev)))
1318                 return -EACCES;
1319
1320         rt73usb_bbp_write(rt2x00dev, 3, 0x80);
1321         rt73usb_bbp_write(rt2x00dev, 15, 0x30);
1322         rt73usb_bbp_write(rt2x00dev, 21, 0xc8);
1323         rt73usb_bbp_write(rt2x00dev, 22, 0x38);
1324         rt73usb_bbp_write(rt2x00dev, 23, 0x06);
1325         rt73usb_bbp_write(rt2x00dev, 24, 0xfe);
1326         rt73usb_bbp_write(rt2x00dev, 25, 0x0a);
1327         rt73usb_bbp_write(rt2x00dev, 26, 0x0d);
1328         rt73usb_bbp_write(rt2x00dev, 32, 0x0b);
1329         rt73usb_bbp_write(rt2x00dev, 34, 0x12);
1330         rt73usb_bbp_write(rt2x00dev, 37, 0x07);
1331         rt73usb_bbp_write(rt2x00dev, 39, 0xf8);
1332         rt73usb_bbp_write(rt2x00dev, 41, 0x60);
1333         rt73usb_bbp_write(rt2x00dev, 53, 0x10);
1334         rt73usb_bbp_write(rt2x00dev, 54, 0x18);
1335         rt73usb_bbp_write(rt2x00dev, 60, 0x10);
1336         rt73usb_bbp_write(rt2x00dev, 61, 0x04);
1337         rt73usb_bbp_write(rt2x00dev, 62, 0x04);
1338         rt73usb_bbp_write(rt2x00dev, 75, 0xfe);
1339         rt73usb_bbp_write(rt2x00dev, 86, 0xfe);
1340         rt73usb_bbp_write(rt2x00dev, 88, 0xfe);
1341         rt73usb_bbp_write(rt2x00dev, 90, 0x0f);
1342         rt73usb_bbp_write(rt2x00dev, 99, 0x00);
1343         rt73usb_bbp_write(rt2x00dev, 102, 0x16);
1344         rt73usb_bbp_write(rt2x00dev, 107, 0x04);
1345
1346         for (i = 0; i < EEPROM_BBP_SIZE; i++) {
1347                 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
1348
1349                 if (eeprom != 0xffff && eeprom != 0x0000) {
1350                         reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
1351                         value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
1352                         rt73usb_bbp_write(rt2x00dev, reg_id, value);
1353                 }
1354         }
1355
1356         return 0;
1357 }
1358
1359 /*
1360  * Device state switch handlers.
1361  */
1362 static int rt73usb_enable_radio(struct rt2x00_dev *rt2x00dev)
1363 {
1364         /*
1365          * Initialize all registers.
1366          */
1367         if (unlikely(rt73usb_init_registers(rt2x00dev) ||
1368                      rt73usb_init_bbp(rt2x00dev)))
1369                 return -EIO;
1370
1371         return 0;
1372 }
1373
1374 static void rt73usb_disable_radio(struct rt2x00_dev *rt2x00dev)
1375 {
1376         rt2x00usb_register_write(rt2x00dev, MAC_CSR10, 0x00001818);
1377
1378         /*
1379          * Disable synchronisation.
1380          */
1381         rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, 0);
1382
1383         rt2x00usb_disable_radio(rt2x00dev);
1384 }
1385
1386 static int rt73usb_set_state(struct rt2x00_dev *rt2x00dev, enum dev_state state)
1387 {
1388         u32 reg, reg2;
1389         unsigned int i;
1390         char put_to_sleep;
1391
1392         put_to_sleep = (state != STATE_AWAKE);
1393
1394         rt2x00usb_register_read(rt2x00dev, MAC_CSR12, &reg);
1395         rt2x00_set_field32(&reg, MAC_CSR12_FORCE_WAKEUP, !put_to_sleep);
1396         rt2x00_set_field32(&reg, MAC_CSR12_PUT_TO_SLEEP, put_to_sleep);
1397         rt2x00usb_register_write(rt2x00dev, MAC_CSR12, reg);
1398
1399         /*
1400          * Device is not guaranteed to be in the requested state yet.
1401          * We must wait until the register indicates that the
1402          * device has entered the correct state.
1403          */
1404         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1405                 rt2x00usb_register_read(rt2x00dev, MAC_CSR12, &reg2);
1406                 state = rt2x00_get_field32(reg2, MAC_CSR12_BBP_CURRENT_STATE);
1407                 if (state == !put_to_sleep)
1408                         return 0;
1409                 rt2x00usb_register_write(rt2x00dev, MAC_CSR12, reg);
1410                 msleep(10);
1411         }
1412
1413         return -EBUSY;
1414 }
1415
1416 static int rt73usb_set_device_state(struct rt2x00_dev *rt2x00dev,
1417                                     enum dev_state state)
1418 {
1419         int retval = 0;
1420
1421         switch (state) {
1422         case STATE_RADIO_ON:
1423                 retval = rt73usb_enable_radio(rt2x00dev);
1424                 break;
1425         case STATE_RADIO_OFF:
1426                 rt73usb_disable_radio(rt2x00dev);
1427                 break;
1428         case STATE_RADIO_IRQ_ON:
1429         case STATE_RADIO_IRQ_OFF:
1430                 /* No support, but no error either */
1431                 break;
1432         case STATE_DEEP_SLEEP:
1433         case STATE_SLEEP:
1434         case STATE_STANDBY:
1435         case STATE_AWAKE:
1436                 retval = rt73usb_set_state(rt2x00dev, state);
1437                 break;
1438         default:
1439                 retval = -ENOTSUPP;
1440                 break;
1441         }
1442
1443         if (unlikely(retval))
1444                 rt2x00_err(rt2x00dev, "Device failed to enter state %d (%d)\n",
1445                            state, retval);
1446
1447         return retval;
1448 }
1449
1450 /*
1451  * TX descriptor initialization
1452  */
1453 static void rt73usb_write_tx_desc(struct queue_entry *entry,
1454                                   struct txentry_desc *txdesc)
1455 {
1456         struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
1457         __le32 *txd = (__le32 *) entry->skb->data;
1458         u32 word;
1459
1460         /*
1461          * Start writing the descriptor words.
1462          */
1463         rt2x00_desc_read(txd, 0, &word);
1464         rt2x00_set_field32(&word, TXD_W0_BURST,
1465                            test_bit(ENTRY_TXD_BURST, &txdesc->flags));
1466         rt2x00_set_field32(&word, TXD_W0_VALID, 1);
1467         rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
1468                            test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
1469         rt2x00_set_field32(&word, TXD_W0_ACK,
1470                            test_bit(ENTRY_TXD_ACK, &txdesc->flags));
1471         rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
1472                            test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
1473         rt2x00_set_field32(&word, TXD_W0_OFDM,
1474                            (txdesc->rate_mode == RATE_MODE_OFDM));
1475         rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->u.plcp.ifs);
1476         rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
1477                            test_bit(ENTRY_TXD_RETRY_MODE, &txdesc->flags));
1478         rt2x00_set_field32(&word, TXD_W0_TKIP_MIC,
1479                            test_bit(ENTRY_TXD_ENCRYPT_MMIC, &txdesc->flags));
1480         rt2x00_set_field32(&word, TXD_W0_KEY_TABLE,
1481                            test_bit(ENTRY_TXD_ENCRYPT_PAIRWISE, &txdesc->flags));
1482         rt2x00_set_field32(&word, TXD_W0_KEY_INDEX, txdesc->key_idx);
1483         rt2x00_set_field32(&word, TXD_W0_DATABYTE_COUNT, txdesc->length);
1484         rt2x00_set_field32(&word, TXD_W0_BURST2,
1485                            test_bit(ENTRY_TXD_BURST, &txdesc->flags));
1486         rt2x00_set_field32(&word, TXD_W0_CIPHER_ALG, txdesc->cipher);
1487         rt2x00_desc_write(txd, 0, word);
1488
1489         rt2x00_desc_read(txd, 1, &word);
1490         rt2x00_set_field32(&word, TXD_W1_HOST_Q_ID, entry->queue->qid);
1491         rt2x00_set_field32(&word, TXD_W1_AIFSN, entry->queue->aifs);
1492         rt2x00_set_field32(&word, TXD_W1_CWMIN, entry->queue->cw_min);
1493         rt2x00_set_field32(&word, TXD_W1_CWMAX, entry->queue->cw_max);
1494         rt2x00_set_field32(&word, TXD_W1_IV_OFFSET, txdesc->iv_offset);
1495         rt2x00_set_field32(&word, TXD_W1_HW_SEQUENCE,
1496                            test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags));
1497         rt2x00_desc_write(txd, 1, word);
1498
1499         rt2x00_desc_read(txd, 2, &word);
1500         rt2x00_set_field32(&word, TXD_W2_PLCP_SIGNAL, txdesc->u.plcp.signal);
1501         rt2x00_set_field32(&word, TXD_W2_PLCP_SERVICE, txdesc->u.plcp.service);
1502         rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_LOW,
1503                            txdesc->u.plcp.length_low);
1504         rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_HIGH,
1505                            txdesc->u.plcp.length_high);
1506         rt2x00_desc_write(txd, 2, word);
1507
1508         if (test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags)) {
1509                 _rt2x00_desc_write(txd, 3, skbdesc->iv[0]);
1510                 _rt2x00_desc_write(txd, 4, skbdesc->iv[1]);
1511         }
1512
1513         rt2x00_desc_read(txd, 5, &word);
1514         rt2x00_set_field32(&word, TXD_W5_TX_POWER,
1515                            TXPOWER_TO_DEV(entry->queue->rt2x00dev->tx_power));
1516         rt2x00_set_field32(&word, TXD_W5_WAITING_DMA_DONE_INT, 1);
1517         rt2x00_desc_write(txd, 5, word);
1518
1519         /*
1520          * Register descriptor details in skb frame descriptor.
1521          */
1522         skbdesc->flags |= SKBDESC_DESC_IN_SKB;
1523         skbdesc->desc = txd;
1524         skbdesc->desc_len = TXD_DESC_SIZE;
1525 }
1526
1527 /*
1528  * TX data initialization
1529  */
1530 static void rt73usb_write_beacon(struct queue_entry *entry,
1531                                  struct txentry_desc *txdesc)
1532 {
1533         struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1534         unsigned int beacon_base;
1535         unsigned int padding_len;
1536         u32 orig_reg, reg;
1537
1538         /*
1539          * Disable beaconing while we are reloading the beacon data,
1540          * otherwise we might be sending out invalid data.
1541          */
1542         rt2x00usb_register_read(rt2x00dev, TXRX_CSR9, &reg);
1543         orig_reg = reg;
1544         rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 0);
1545         rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, reg);
1546
1547         /*
1548          * Add space for the descriptor in front of the skb.
1549          */
1550         skb_push(entry->skb, TXD_DESC_SIZE);
1551         memset(entry->skb->data, 0, TXD_DESC_SIZE);
1552
1553         /*
1554          * Write the TX descriptor for the beacon.
1555          */
1556         rt73usb_write_tx_desc(entry, txdesc);
1557
1558         /*
1559          * Dump beacon to userspace through debugfs.
1560          */
1561         rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_BEACON, entry->skb);
1562
1563         /*
1564          * Write entire beacon with descriptor and padding to register.
1565          */
1566         padding_len = roundup(entry->skb->len, 4) - entry->skb->len;
1567         if (padding_len && skb_pad(entry->skb, padding_len)) {
1568                 rt2x00_err(rt2x00dev, "Failure padding beacon, aborting\n");
1569                 /* skb freed by skb_pad() on failure */
1570                 entry->skb = NULL;
1571                 rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, orig_reg);
1572                 return;
1573         }
1574
1575         beacon_base = HW_BEACON_OFFSET(entry->entry_idx);
1576         rt2x00usb_register_multiwrite(rt2x00dev, beacon_base, entry->skb->data,
1577                                       entry->skb->len + padding_len);
1578
1579         /*
1580          * Enable beaconing again.
1581          *
1582          * For Wi-Fi faily generated beacons between participating stations.
1583          * Set TBTT phase adaptive adjustment step to 8us (default 16us)
1584          */
1585         rt2x00usb_register_write(rt2x00dev, TXRX_CSR10, 0x00001008);
1586
1587         rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 1);
1588         rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, reg);
1589
1590         /*
1591          * Clean up the beacon skb.
1592          */
1593         dev_kfree_skb(entry->skb);
1594         entry->skb = NULL;
1595 }
1596
1597 static void rt73usb_clear_beacon(struct queue_entry *entry)
1598 {
1599         struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1600         unsigned int beacon_base;
1601         u32 reg;
1602
1603         /*
1604          * Disable beaconing while we are reloading the beacon data,
1605          * otherwise we might be sending out invalid data.
1606          */
1607         rt2x00usb_register_read(rt2x00dev, TXRX_CSR9, &reg);
1608         rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 0);
1609         rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, reg);
1610
1611         /*
1612          * Clear beacon.
1613          */
1614         beacon_base = HW_BEACON_OFFSET(entry->entry_idx);
1615         rt2x00usb_register_write(rt2x00dev, beacon_base, 0);
1616
1617         /*
1618          * Enable beaconing again.
1619          */
1620         rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 1);
1621         rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, reg);
1622 }
1623
1624 static int rt73usb_get_tx_data_len(struct queue_entry *entry)
1625 {
1626         int length;
1627
1628         /*
1629          * The length _must_ be a multiple of 4,
1630          * but it must _not_ be a multiple of the USB packet size.
1631          */
1632         length = roundup(entry->skb->len, 4);
1633         length += (4 * !(length % entry->queue->usb_maxpacket));
1634
1635         return length;
1636 }
1637
1638 /*
1639  * RX control handlers
1640  */
1641 static int rt73usb_agc_to_rssi(struct rt2x00_dev *rt2x00dev, int rxd_w1)
1642 {
1643         u8 offset = rt2x00dev->lna_gain;
1644         u8 lna;
1645
1646         lna = rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_LNA);
1647         switch (lna) {
1648         case 3:
1649                 offset += 90;
1650                 break;
1651         case 2:
1652                 offset += 74;
1653                 break;
1654         case 1:
1655                 offset += 64;
1656                 break;
1657         default:
1658                 return 0;
1659         }
1660
1661         if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ) {
1662                 if (rt2x00_has_cap_external_lna_a(rt2x00dev)) {
1663                         if (lna == 3 || lna == 2)
1664                                 offset += 10;
1665                 } else {
1666                         if (lna == 3)
1667                                 offset += 6;
1668                         else if (lna == 2)
1669                                 offset += 8;
1670                 }
1671         }
1672
1673         return rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_AGC) * 2 - offset;
1674 }
1675
1676 static void rt73usb_fill_rxdone(struct queue_entry *entry,
1677                                 struct rxdone_entry_desc *rxdesc)
1678 {
1679         struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1680         struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
1681         __le32 *rxd = (__le32 *)entry->skb->data;
1682         u32 word0;
1683         u32 word1;
1684
1685         /*
1686          * Copy descriptor to the skbdesc->desc buffer, making it safe from moving of
1687          * frame data in rt2x00usb.
1688          */
1689         memcpy(skbdesc->desc, rxd, skbdesc->desc_len);
1690         rxd = (__le32 *)skbdesc->desc;
1691
1692         /*
1693          * It is now safe to read the descriptor on all architectures.
1694          */
1695         rt2x00_desc_read(rxd, 0, &word0);
1696         rt2x00_desc_read(rxd, 1, &word1);
1697
1698         if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
1699                 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
1700
1701         rxdesc->cipher = rt2x00_get_field32(word0, RXD_W0_CIPHER_ALG);
1702         rxdesc->cipher_status = rt2x00_get_field32(word0, RXD_W0_CIPHER_ERROR);
1703
1704         if (rxdesc->cipher != CIPHER_NONE) {
1705                 _rt2x00_desc_read(rxd, 2, &rxdesc->iv[0]);
1706                 _rt2x00_desc_read(rxd, 3, &rxdesc->iv[1]);
1707                 rxdesc->dev_flags |= RXDONE_CRYPTO_IV;
1708
1709                 _rt2x00_desc_read(rxd, 4, &rxdesc->icv);
1710                 rxdesc->dev_flags |= RXDONE_CRYPTO_ICV;
1711
1712                 /*
1713                  * Hardware has stripped IV/EIV data from 802.11 frame during
1714                  * decryption. It has provided the data separately but rt2x00lib
1715                  * should decide if it should be reinserted.
1716                  */
1717                 rxdesc->flags |= RX_FLAG_IV_STRIPPED;
1718
1719                 /*
1720                  * The hardware has already checked the Michael Mic and has
1721                  * stripped it from the frame. Signal this to mac80211.
1722                  */
1723                 rxdesc->flags |= RX_FLAG_MMIC_STRIPPED;
1724
1725                 if (rxdesc->cipher_status == RX_CRYPTO_SUCCESS)
1726                         rxdesc->flags |= RX_FLAG_DECRYPTED;
1727                 else if (rxdesc->cipher_status == RX_CRYPTO_FAIL_MIC)
1728                         rxdesc->flags |= RX_FLAG_MMIC_ERROR;
1729         }
1730
1731         /*
1732          * Obtain the status about this packet.
1733          * When frame was received with an OFDM bitrate,
1734          * the signal is the PLCP value. If it was received with
1735          * a CCK bitrate the signal is the rate in 100kbit/s.
1736          */
1737         rxdesc->signal = rt2x00_get_field32(word1, RXD_W1_SIGNAL);
1738         rxdesc->rssi = rt73usb_agc_to_rssi(rt2x00dev, word1);
1739         rxdesc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
1740
1741         if (rt2x00_get_field32(word0, RXD_W0_OFDM))
1742                 rxdesc->dev_flags |= RXDONE_SIGNAL_PLCP;
1743         else
1744                 rxdesc->dev_flags |= RXDONE_SIGNAL_BITRATE;
1745         if (rt2x00_get_field32(word0, RXD_W0_MY_BSS))
1746                 rxdesc->dev_flags |= RXDONE_MY_BSS;
1747
1748         /*
1749          * Set skb pointers, and update frame information.
1750          */
1751         skb_pull(entry->skb, entry->queue->desc_size);
1752         skb_trim(entry->skb, rxdesc->size);
1753 }
1754
1755 /*
1756  * Device probe functions.
1757  */
1758 static int rt73usb_validate_eeprom(struct rt2x00_dev *rt2x00dev)
1759 {
1760         u16 word;
1761         u8 *mac;
1762         s8 value;
1763
1764         rt2x00usb_eeprom_read(rt2x00dev, rt2x00dev->eeprom, EEPROM_SIZE);
1765
1766         /*
1767          * Start validation of the data that has been read.
1768          */
1769         mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
1770         if (!is_valid_ether_addr(mac)) {
1771                 eth_random_addr(mac);
1772                 rt2x00_eeprom_dbg(rt2x00dev, "MAC: %pM\n", mac);
1773         }
1774
1775         rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
1776         if (word == 0xffff) {
1777                 rt2x00_set_field16(&word, EEPROM_ANTENNA_NUM, 2);
1778                 rt2x00_set_field16(&word, EEPROM_ANTENNA_TX_DEFAULT,
1779                                    ANTENNA_B);
1780                 rt2x00_set_field16(&word, EEPROM_ANTENNA_RX_DEFAULT,
1781                                    ANTENNA_B);
1782                 rt2x00_set_field16(&word, EEPROM_ANTENNA_FRAME_TYPE, 0);
1783                 rt2x00_set_field16(&word, EEPROM_ANTENNA_DYN_TXAGC, 0);
1784                 rt2x00_set_field16(&word, EEPROM_ANTENNA_HARDWARE_RADIO, 0);
1785                 rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF5226);
1786                 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
1787                 rt2x00_eeprom_dbg(rt2x00dev, "Antenna: 0x%04x\n", word);
1788         }
1789
1790         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
1791         if (word == 0xffff) {
1792                 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA, 0);
1793                 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
1794                 rt2x00_eeprom_dbg(rt2x00dev, "NIC: 0x%04x\n", word);
1795         }
1796
1797         rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &word);
1798         if (word == 0xffff) {
1799                 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_RDY_G, 0);
1800                 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_RDY_A, 0);
1801                 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_ACT, 0);
1802                 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_0, 0);
1803                 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_1, 0);
1804                 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_2, 0);
1805                 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_3, 0);
1806                 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_4, 0);
1807                 rt2x00_set_field16(&word, EEPROM_LED_LED_MODE,
1808                                    LED_MODE_DEFAULT);
1809                 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED, word);
1810                 rt2x00_eeprom_dbg(rt2x00dev, "Led: 0x%04x\n", word);
1811         }
1812
1813         rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
1814         if (word == 0xffff) {
1815                 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
1816                 rt2x00_set_field16(&word, EEPROM_FREQ_SEQ, 0);
1817                 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
1818                 rt2x00_eeprom_dbg(rt2x00dev, "Freq: 0x%04x\n", word);
1819         }
1820
1821         rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &word);
1822         if (word == 0xffff) {
1823                 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0);
1824                 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0);
1825                 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word);
1826                 rt2x00_eeprom_dbg(rt2x00dev, "RSSI OFFSET BG: 0x%04x\n", word);
1827         } else {
1828                 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_1);
1829                 if (value < -10 || value > 10)
1830                         rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0);
1831                 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_2);
1832                 if (value < -10 || value > 10)
1833                         rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0);
1834                 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word);
1835         }
1836
1837         rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &word);
1838         if (word == 0xffff) {
1839                 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0);
1840                 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0);
1841                 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word);
1842                 rt2x00_eeprom_dbg(rt2x00dev, "RSSI OFFSET A: 0x%04x\n", word);
1843         } else {
1844                 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_1);
1845                 if (value < -10 || value > 10)
1846                         rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0);
1847                 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_2);
1848                 if (value < -10 || value > 10)
1849                         rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0);
1850                 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word);
1851         }
1852
1853         return 0;
1854 }
1855
1856 static int rt73usb_init_eeprom(struct rt2x00_dev *rt2x00dev)
1857 {
1858         u32 reg;
1859         u16 value;
1860         u16 eeprom;
1861
1862         /*
1863          * Read EEPROM word for configuration.
1864          */
1865         rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
1866
1867         /*
1868          * Identify RF chipset.
1869          */
1870         value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
1871         rt2x00usb_register_read(rt2x00dev, MAC_CSR0, &reg);
1872         rt2x00_set_chip(rt2x00dev, rt2x00_get_field32(reg, MAC_CSR0_CHIPSET),
1873                         value, rt2x00_get_field32(reg, MAC_CSR0_REVISION));
1874
1875         if (!rt2x00_rt(rt2x00dev, RT2573) || (rt2x00_rev(rt2x00dev) == 0)) {
1876                 rt2x00_err(rt2x00dev, "Invalid RT chipset detected\n");
1877                 return -ENODEV;
1878         }
1879
1880         if (!rt2x00_rf(rt2x00dev, RF5226) &&
1881             !rt2x00_rf(rt2x00dev, RF2528) &&
1882             !rt2x00_rf(rt2x00dev, RF5225) &&
1883             !rt2x00_rf(rt2x00dev, RF2527)) {
1884                 rt2x00_err(rt2x00dev, "Invalid RF chipset detected\n");
1885                 return -ENODEV;
1886         }
1887
1888         /*
1889          * Identify default antenna configuration.
1890          */
1891         rt2x00dev->default_ant.tx =
1892             rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT);
1893         rt2x00dev->default_ant.rx =
1894             rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT);
1895
1896         /*
1897          * Read the Frame type.
1898          */
1899         if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_FRAME_TYPE))
1900                 __set_bit(CAPABILITY_FRAME_TYPE, &rt2x00dev->cap_flags);
1901
1902         /*
1903          * Detect if this device has an hardware controlled radio.
1904          */
1905         if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO))
1906                 __set_bit(CAPABILITY_HW_BUTTON, &rt2x00dev->cap_flags);
1907
1908         /*
1909          * Read frequency offset.
1910          */
1911         rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
1912         rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
1913
1914         /*
1915          * Read external LNA informations.
1916          */
1917         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
1918
1919         if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA)) {
1920                 __set_bit(CAPABILITY_EXTERNAL_LNA_A, &rt2x00dev->cap_flags);
1921                 __set_bit(CAPABILITY_EXTERNAL_LNA_BG, &rt2x00dev->cap_flags);
1922         }
1923
1924         /*
1925          * Store led settings, for correct led behaviour.
1926          */
1927 #ifdef CONFIG_RT2X00_LIB_LEDS
1928         rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &eeprom);
1929
1930         rt73usb_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
1931         rt73usb_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC);
1932         if (value == LED_MODE_SIGNAL_STRENGTH)
1933                 rt73usb_init_led(rt2x00dev, &rt2x00dev->led_qual,
1934                                  LED_TYPE_QUALITY);
1935
1936         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_LED_MODE, value);
1937         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_0,
1938                            rt2x00_get_field16(eeprom,
1939                                               EEPROM_LED_POLARITY_GPIO_0));
1940         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_1,
1941                            rt2x00_get_field16(eeprom,
1942                                               EEPROM_LED_POLARITY_GPIO_1));
1943         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_2,
1944                            rt2x00_get_field16(eeprom,
1945                                               EEPROM_LED_POLARITY_GPIO_2));
1946         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_3,
1947                            rt2x00_get_field16(eeprom,
1948                                               EEPROM_LED_POLARITY_GPIO_3));
1949         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_4,
1950                            rt2x00_get_field16(eeprom,
1951                                               EEPROM_LED_POLARITY_GPIO_4));
1952         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_ACT,
1953                            rt2x00_get_field16(eeprom, EEPROM_LED_POLARITY_ACT));
1954         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_READY_BG,
1955                            rt2x00_get_field16(eeprom,
1956                                               EEPROM_LED_POLARITY_RDY_G));
1957         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_READY_A,
1958                            rt2x00_get_field16(eeprom,
1959                                               EEPROM_LED_POLARITY_RDY_A));
1960 #endif /* CONFIG_RT2X00_LIB_LEDS */
1961
1962         return 0;
1963 }
1964
1965 /*
1966  * RF value list for RF2528
1967  * Supports: 2.4 GHz
1968  */
1969 static const struct rf_channel rf_vals_bg_2528[] = {
1970         { 1,  0x00002c0c, 0x00000786, 0x00068255, 0x000fea0b },
1971         { 2,  0x00002c0c, 0x00000786, 0x00068255, 0x000fea1f },
1972         { 3,  0x00002c0c, 0x0000078a, 0x00068255, 0x000fea0b },
1973         { 4,  0x00002c0c, 0x0000078a, 0x00068255, 0x000fea1f },
1974         { 5,  0x00002c0c, 0x0000078e, 0x00068255, 0x000fea0b },
1975         { 6,  0x00002c0c, 0x0000078e, 0x00068255, 0x000fea1f },
1976         { 7,  0x00002c0c, 0x00000792, 0x00068255, 0x000fea0b },
1977         { 8,  0x00002c0c, 0x00000792, 0x00068255, 0x000fea1f },
1978         { 9,  0x00002c0c, 0x00000796, 0x00068255, 0x000fea0b },
1979         { 10, 0x00002c0c, 0x00000796, 0x00068255, 0x000fea1f },
1980         { 11, 0x00002c0c, 0x0000079a, 0x00068255, 0x000fea0b },
1981         { 12, 0x00002c0c, 0x0000079a, 0x00068255, 0x000fea1f },
1982         { 13, 0x00002c0c, 0x0000079e, 0x00068255, 0x000fea0b },
1983         { 14, 0x00002c0c, 0x000007a2, 0x00068255, 0x000fea13 },
1984 };
1985
1986 /*
1987  * RF value list for RF5226
1988  * Supports: 2.4 GHz & 5.2 GHz
1989  */
1990 static const struct rf_channel rf_vals_5226[] = {
1991         { 1,  0x00002c0c, 0x00000786, 0x00068255, 0x000fea0b },
1992         { 2,  0x00002c0c, 0x00000786, 0x00068255, 0x000fea1f },
1993         { 3,  0x00002c0c, 0x0000078a, 0x00068255, 0x000fea0b },
1994         { 4,  0x00002c0c, 0x0000078a, 0x00068255, 0x000fea1f },
1995         { 5,  0x00002c0c, 0x0000078e, 0x00068255, 0x000fea0b },
1996         { 6,  0x00002c0c, 0x0000078e, 0x00068255, 0x000fea1f },
1997         { 7,  0x00002c0c, 0x00000792, 0x00068255, 0x000fea0b },
1998         { 8,  0x00002c0c, 0x00000792, 0x00068255, 0x000fea1f },
1999         { 9,  0x00002c0c, 0x00000796, 0x00068255, 0x000fea0b },
2000         { 10, 0x00002c0c, 0x00000796, 0x00068255, 0x000fea1f },
2001         { 11, 0x00002c0c, 0x0000079a, 0x00068255, 0x000fea0b },
2002         { 12, 0x00002c0c, 0x0000079a, 0x00068255, 0x000fea1f },
2003         { 13, 0x00002c0c, 0x0000079e, 0x00068255, 0x000fea0b },
2004         { 14, 0x00002c0c, 0x000007a2, 0x00068255, 0x000fea13 },
2005
2006         /* 802.11 UNI / HyperLan 2 */
2007         { 36, 0x00002c0c, 0x0000099a, 0x00098255, 0x000fea23 },
2008         { 40, 0x00002c0c, 0x000009a2, 0x00098255, 0x000fea03 },
2009         { 44, 0x00002c0c, 0x000009a6, 0x00098255, 0x000fea0b },
2010         { 48, 0x00002c0c, 0x000009aa, 0x00098255, 0x000fea13 },
2011         { 52, 0x00002c0c, 0x000009ae, 0x00098255, 0x000fea1b },
2012         { 56, 0x00002c0c, 0x000009b2, 0x00098255, 0x000fea23 },
2013         { 60, 0x00002c0c, 0x000009ba, 0x00098255, 0x000fea03 },
2014         { 64, 0x00002c0c, 0x000009be, 0x00098255, 0x000fea0b },
2015
2016         /* 802.11 HyperLan 2 */
2017         { 100, 0x00002c0c, 0x00000a2a, 0x000b8255, 0x000fea03 },
2018         { 104, 0x00002c0c, 0x00000a2e, 0x000b8255, 0x000fea0b },
2019         { 108, 0x00002c0c, 0x00000a32, 0x000b8255, 0x000fea13 },
2020         { 112, 0x00002c0c, 0x00000a36, 0x000b8255, 0x000fea1b },
2021         { 116, 0x00002c0c, 0x00000a3a, 0x000b8255, 0x000fea23 },
2022         { 120, 0x00002c0c, 0x00000a82, 0x000b8255, 0x000fea03 },
2023         { 124, 0x00002c0c, 0x00000a86, 0x000b8255, 0x000fea0b },
2024         { 128, 0x00002c0c, 0x00000a8a, 0x000b8255, 0x000fea13 },
2025         { 132, 0x00002c0c, 0x00000a8e, 0x000b8255, 0x000fea1b },
2026         { 136, 0x00002c0c, 0x00000a92, 0x000b8255, 0x000fea23 },
2027
2028         /* 802.11 UNII */
2029         { 140, 0x00002c0c, 0x00000a9a, 0x000b8255, 0x000fea03 },
2030         { 149, 0x00002c0c, 0x00000aa2, 0x000b8255, 0x000fea1f },
2031         { 153, 0x00002c0c, 0x00000aa6, 0x000b8255, 0x000fea27 },
2032         { 157, 0x00002c0c, 0x00000aae, 0x000b8255, 0x000fea07 },
2033         { 161, 0x00002c0c, 0x00000ab2, 0x000b8255, 0x000fea0f },
2034         { 165, 0x00002c0c, 0x00000ab6, 0x000b8255, 0x000fea17 },
2035
2036         /* MMAC(Japan)J52 ch 34,38,42,46 */
2037         { 34, 0x00002c0c, 0x0008099a, 0x000da255, 0x000d3a0b },
2038         { 38, 0x00002c0c, 0x0008099e, 0x000da255, 0x000d3a13 },
2039         { 42, 0x00002c0c, 0x000809a2, 0x000da255, 0x000d3a1b },
2040         { 46, 0x00002c0c, 0x000809a6, 0x000da255, 0x000d3a23 },
2041 };
2042
2043 /*
2044  * RF value list for RF5225 & RF2527
2045  * Supports: 2.4 GHz & 5.2 GHz
2046  */
2047 static const struct rf_channel rf_vals_5225_2527[] = {
2048         { 1,  0x00002ccc, 0x00004786, 0x00068455, 0x000ffa0b },
2049         { 2,  0x00002ccc, 0x00004786, 0x00068455, 0x000ffa1f },
2050         { 3,  0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa0b },
2051         { 4,  0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa1f },
2052         { 5,  0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa0b },
2053         { 6,  0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa1f },
2054         { 7,  0x00002ccc, 0x00004792, 0x00068455, 0x000ffa0b },
2055         { 8,  0x00002ccc, 0x00004792, 0x00068455, 0x000ffa1f },
2056         { 9,  0x00002ccc, 0x00004796, 0x00068455, 0x000ffa0b },
2057         { 10, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa1f },
2058         { 11, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa0b },
2059         { 12, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa1f },
2060         { 13, 0x00002ccc, 0x0000479e, 0x00068455, 0x000ffa0b },
2061         { 14, 0x00002ccc, 0x000047a2, 0x00068455, 0x000ffa13 },
2062
2063         /* 802.11 UNI / HyperLan 2 */
2064         { 36, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa23 },
2065         { 40, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa03 },
2066         { 44, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa0b },
2067         { 48, 0x00002ccc, 0x000049aa, 0x0009be55, 0x000ffa13 },
2068         { 52, 0x00002ccc, 0x000049ae, 0x0009ae55, 0x000ffa1b },
2069         { 56, 0x00002ccc, 0x000049b2, 0x0009ae55, 0x000ffa23 },
2070         { 60, 0x00002ccc, 0x000049ba, 0x0009ae55, 0x000ffa03 },
2071         { 64, 0x00002ccc, 0x000049be, 0x0009ae55, 0x000ffa0b },
2072
2073         /* 802.11 HyperLan 2 */
2074         { 100, 0x00002ccc, 0x00004a2a, 0x000bae55, 0x000ffa03 },
2075         { 104, 0x00002ccc, 0x00004a2e, 0x000bae55, 0x000ffa0b },
2076         { 108, 0x00002ccc, 0x00004a32, 0x000bae55, 0x000ffa13 },
2077         { 112, 0x00002ccc, 0x00004a36, 0x000bae55, 0x000ffa1b },
2078         { 116, 0x00002ccc, 0x00004a3a, 0x000bbe55, 0x000ffa23 },
2079         { 120, 0x00002ccc, 0x00004a82, 0x000bbe55, 0x000ffa03 },
2080         { 124, 0x00002ccc, 0x00004a86, 0x000bbe55, 0x000ffa0b },
2081         { 128, 0x00002ccc, 0x00004a8a, 0x000bbe55, 0x000ffa13 },
2082         { 132, 0x00002ccc, 0x00004a8e, 0x000bbe55, 0x000ffa1b },
2083         { 136, 0x00002ccc, 0x00004a92, 0x000bbe55, 0x000ffa23 },
2084
2085         /* 802.11 UNII */
2086         { 140, 0x00002ccc, 0x00004a9a, 0x000bbe55, 0x000ffa03 },
2087         { 149, 0x00002ccc, 0x00004aa2, 0x000bbe55, 0x000ffa1f },
2088         { 153, 0x00002ccc, 0x00004aa6, 0x000bbe55, 0x000ffa27 },
2089         { 157, 0x00002ccc, 0x00004aae, 0x000bbe55, 0x000ffa07 },
2090         { 161, 0x00002ccc, 0x00004ab2, 0x000bbe55, 0x000ffa0f },
2091         { 165, 0x00002ccc, 0x00004ab6, 0x000bbe55, 0x000ffa17 },
2092
2093         /* MMAC(Japan)J52 ch 34,38,42,46 */
2094         { 34, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa0b },
2095         { 38, 0x00002ccc, 0x0000499e, 0x0009be55, 0x000ffa13 },
2096         { 42, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa1b },
2097         { 46, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa23 },
2098 };
2099
2100
2101 static int rt73usb_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
2102 {
2103         struct hw_mode_spec *spec = &rt2x00dev->spec;
2104         struct channel_info *info;
2105         char *tx_power;
2106         unsigned int i;
2107
2108         /*
2109          * Initialize all hw fields.
2110          *
2111          * Don't set IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING unless we are
2112          * capable of sending the buffered frames out after the DTIM
2113          * transmission using rt2x00lib_beacondone. This will send out
2114          * multicast and broadcast traffic immediately instead of buffering it
2115          * infinitly and thus dropping it after some time.
2116          */
2117         rt2x00dev->hw->flags =
2118             IEEE80211_HW_SIGNAL_DBM |
2119             IEEE80211_HW_SUPPORTS_PS |
2120             IEEE80211_HW_PS_NULLFUNC_STACK;
2121
2122         SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
2123         SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
2124                                 rt2x00_eeprom_addr(rt2x00dev,
2125                                                    EEPROM_MAC_ADDR_0));
2126
2127         /*
2128          * Initialize hw_mode information.
2129          */
2130         spec->supported_bands = SUPPORT_BAND_2GHZ;
2131         spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
2132
2133         if (rt2x00_rf(rt2x00dev, RF2528)) {
2134                 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2528);
2135                 spec->channels = rf_vals_bg_2528;
2136         } else if (rt2x00_rf(rt2x00dev, RF5226)) {
2137                 spec->supported_bands |= SUPPORT_BAND_5GHZ;
2138                 spec->num_channels = ARRAY_SIZE(rf_vals_5226);
2139                 spec->channels = rf_vals_5226;
2140         } else if (rt2x00_rf(rt2x00dev, RF2527)) {
2141                 spec->num_channels = 14;
2142                 spec->channels = rf_vals_5225_2527;
2143         } else if (rt2x00_rf(rt2x00dev, RF5225)) {
2144                 spec->supported_bands |= SUPPORT_BAND_5GHZ;
2145                 spec->num_channels = ARRAY_SIZE(rf_vals_5225_2527);
2146                 spec->channels = rf_vals_5225_2527;
2147         }
2148
2149         /*
2150          * Create channel information array
2151          */
2152         info = kcalloc(spec->num_channels, sizeof(*info), GFP_KERNEL);
2153         if (!info)
2154                 return -ENOMEM;
2155
2156         spec->channels_info = info;
2157
2158         tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_G_START);
2159         for (i = 0; i < 14; i++) {
2160                 info[i].max_power = MAX_TXPOWER;
2161                 info[i].default_power1 = TXPOWER_FROM_DEV(tx_power[i]);
2162         }
2163
2164         if (spec->num_channels > 14) {
2165                 tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A_START);
2166                 for (i = 14; i < spec->num_channels; i++) {
2167                         info[i].max_power = MAX_TXPOWER;
2168                         info[i].default_power1 =
2169                                         TXPOWER_FROM_DEV(tx_power[i - 14]);
2170                 }
2171         }
2172
2173         return 0;
2174 }
2175
2176 static int rt73usb_probe_hw(struct rt2x00_dev *rt2x00dev)
2177 {
2178         int retval;
2179         u32 reg;
2180
2181         /*
2182          * Allocate eeprom data.
2183          */
2184         retval = rt73usb_validate_eeprom(rt2x00dev);
2185         if (retval)
2186                 return retval;
2187
2188         retval = rt73usb_init_eeprom(rt2x00dev);
2189         if (retval)
2190                 return retval;
2191
2192         /*
2193          * Enable rfkill polling by setting GPIO direction of the
2194          * rfkill switch GPIO pin correctly.
2195          */
2196         rt2x00usb_register_read(rt2x00dev, MAC_CSR13, &reg);
2197         rt2x00_set_field32(&reg, MAC_CSR13_DIR7, 0);
2198         rt2x00usb_register_write(rt2x00dev, MAC_CSR13, reg);
2199
2200         /*
2201          * Initialize hw specifications.
2202          */
2203         retval = rt73usb_probe_hw_mode(rt2x00dev);
2204         if (retval)
2205                 return retval;
2206
2207         /*
2208          * This device has multiple filters for control frames,
2209          * but has no a separate filter for PS Poll frames.
2210          */
2211         __set_bit(CAPABILITY_CONTROL_FILTERS, &rt2x00dev->cap_flags);
2212
2213         /*
2214          * This device requires firmware.
2215          */
2216         __set_bit(REQUIRE_FIRMWARE, &rt2x00dev->cap_flags);
2217         if (!modparam_nohwcrypt)
2218                 __set_bit(CAPABILITY_HW_CRYPTO, &rt2x00dev->cap_flags);
2219         __set_bit(CAPABILITY_LINK_TUNING, &rt2x00dev->cap_flags);
2220         __set_bit(REQUIRE_PS_AUTOWAKE, &rt2x00dev->cap_flags);
2221
2222         /*
2223          * Set the rssi offset.
2224          */
2225         rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
2226
2227         return 0;
2228 }
2229
2230 /*
2231  * IEEE80211 stack callback functions.
2232  */
2233 static int rt73usb_conf_tx(struct ieee80211_hw *hw,
2234                            struct ieee80211_vif *vif, u16 queue_idx,
2235                            const struct ieee80211_tx_queue_params *params)
2236 {
2237         struct rt2x00_dev *rt2x00dev = hw->priv;
2238         struct data_queue *queue;
2239         struct rt2x00_field32 field;
2240         int retval;
2241         u32 reg;
2242         u32 offset;
2243
2244         /*
2245          * First pass the configuration through rt2x00lib, that will
2246          * update the queue settings and validate the input. After that
2247          * we are free to update the registers based on the value
2248          * in the queue parameter.
2249          */
2250         retval = rt2x00mac_conf_tx(hw, vif, queue_idx, params);
2251         if (retval)
2252                 return retval;
2253
2254         /*
2255          * We only need to perform additional register initialization
2256          * for WMM queues/
2257          */
2258         if (queue_idx >= 4)
2259                 return 0;
2260
2261         queue = rt2x00queue_get_tx_queue(rt2x00dev, queue_idx);
2262
2263         /* Update WMM TXOP register */
2264         offset = AC_TXOP_CSR0 + (sizeof(u32) * (!!(queue_idx & 2)));
2265         field.bit_offset = (queue_idx & 1) * 16;
2266         field.bit_mask = 0xffff << field.bit_offset;
2267
2268         rt2x00usb_register_read(rt2x00dev, offset, &reg);
2269         rt2x00_set_field32(&reg, field, queue->txop);
2270         rt2x00usb_register_write(rt2x00dev, offset, reg);
2271
2272         /* Update WMM registers */
2273         field.bit_offset = queue_idx * 4;
2274         field.bit_mask = 0xf << field.bit_offset;
2275
2276         rt2x00usb_register_read(rt2x00dev, AIFSN_CSR, &reg);
2277         rt2x00_set_field32(&reg, field, queue->aifs);
2278         rt2x00usb_register_write(rt2x00dev, AIFSN_CSR, reg);
2279
2280         rt2x00usb_register_read(rt2x00dev, CWMIN_CSR, &reg);
2281         rt2x00_set_field32(&reg, field, queue->cw_min);
2282         rt2x00usb_register_write(rt2x00dev, CWMIN_CSR, reg);
2283
2284         rt2x00usb_register_read(rt2x00dev, CWMAX_CSR, &reg);
2285         rt2x00_set_field32(&reg, field, queue->cw_max);
2286         rt2x00usb_register_write(rt2x00dev, CWMAX_CSR, reg);
2287
2288         return 0;
2289 }
2290
2291 static u64 rt73usb_get_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
2292 {
2293         struct rt2x00_dev *rt2x00dev = hw->priv;
2294         u64 tsf;
2295         u32 reg;
2296
2297         rt2x00usb_register_read(rt2x00dev, TXRX_CSR13, &reg);
2298         tsf = (u64) rt2x00_get_field32(reg, TXRX_CSR13_HIGH_TSFTIMER) << 32;
2299         rt2x00usb_register_read(rt2x00dev, TXRX_CSR12, &reg);
2300         tsf |= rt2x00_get_field32(reg, TXRX_CSR12_LOW_TSFTIMER);
2301
2302         return tsf;
2303 }
2304
2305 static const struct ieee80211_ops rt73usb_mac80211_ops = {
2306         .tx                     = rt2x00mac_tx,
2307         .start                  = rt2x00mac_start,
2308         .stop                   = rt2x00mac_stop,
2309         .add_interface          = rt2x00mac_add_interface,
2310         .remove_interface       = rt2x00mac_remove_interface,
2311         .config                 = rt2x00mac_config,
2312         .configure_filter       = rt2x00mac_configure_filter,
2313         .set_tim                = rt2x00mac_set_tim,
2314         .set_key                = rt2x00mac_set_key,
2315         .sw_scan_start          = rt2x00mac_sw_scan_start,
2316         .sw_scan_complete       = rt2x00mac_sw_scan_complete,
2317         .get_stats              = rt2x00mac_get_stats,
2318         .bss_info_changed       = rt2x00mac_bss_info_changed,
2319         .conf_tx                = rt73usb_conf_tx,
2320         .get_tsf                = rt73usb_get_tsf,
2321         .rfkill_poll            = rt2x00mac_rfkill_poll,
2322         .flush                  = rt2x00mac_flush,
2323         .set_antenna            = rt2x00mac_set_antenna,
2324         .get_antenna            = rt2x00mac_get_antenna,
2325         .get_ringparam          = rt2x00mac_get_ringparam,
2326         .tx_frames_pending      = rt2x00mac_tx_frames_pending,
2327 };
2328
2329 static const struct rt2x00lib_ops rt73usb_rt2x00_ops = {
2330         .probe_hw               = rt73usb_probe_hw,
2331         .get_firmware_name      = rt73usb_get_firmware_name,
2332         .check_firmware         = rt73usb_check_firmware,
2333         .load_firmware          = rt73usb_load_firmware,
2334         .initialize             = rt2x00usb_initialize,
2335         .uninitialize           = rt2x00usb_uninitialize,
2336         .clear_entry            = rt2x00usb_clear_entry,
2337         .set_device_state       = rt73usb_set_device_state,
2338         .rfkill_poll            = rt73usb_rfkill_poll,
2339         .link_stats             = rt73usb_link_stats,
2340         .reset_tuner            = rt73usb_reset_tuner,
2341         .link_tuner             = rt73usb_link_tuner,
2342         .watchdog               = rt2x00usb_watchdog,
2343         .start_queue            = rt73usb_start_queue,
2344         .kick_queue             = rt2x00usb_kick_queue,
2345         .stop_queue             = rt73usb_stop_queue,
2346         .flush_queue            = rt2x00usb_flush_queue,
2347         .write_tx_desc          = rt73usb_write_tx_desc,
2348         .write_beacon           = rt73usb_write_beacon,
2349         .clear_beacon           = rt73usb_clear_beacon,
2350         .get_tx_data_len        = rt73usb_get_tx_data_len,
2351         .fill_rxdone            = rt73usb_fill_rxdone,
2352         .config_shared_key      = rt73usb_config_shared_key,
2353         .config_pairwise_key    = rt73usb_config_pairwise_key,
2354         .config_filter          = rt73usb_config_filter,
2355         .config_intf            = rt73usb_config_intf,
2356         .config_erp             = rt73usb_config_erp,
2357         .config_ant             = rt73usb_config_ant,
2358         .config                 = rt73usb_config,
2359 };
2360
2361 static void rt73usb_queue_init(struct data_queue *queue)
2362 {
2363         switch (queue->qid) {
2364         case QID_RX:
2365                 queue->limit = 32;
2366                 queue->data_size = DATA_FRAME_SIZE;
2367                 queue->desc_size = RXD_DESC_SIZE;
2368                 queue->priv_size = sizeof(struct queue_entry_priv_usb);
2369                 break;
2370
2371         case QID_AC_VO:
2372         case QID_AC_VI:
2373         case QID_AC_BE:
2374         case QID_AC_BK:
2375                 queue->limit = 32;
2376                 queue->data_size = DATA_FRAME_SIZE;
2377                 queue->desc_size = TXD_DESC_SIZE;
2378                 queue->priv_size = sizeof(struct queue_entry_priv_usb);
2379                 break;
2380
2381         case QID_BEACON:
2382                 queue->limit = 4;
2383                 queue->data_size = MGMT_FRAME_SIZE;
2384                 queue->desc_size = TXINFO_SIZE;
2385                 queue->priv_size = sizeof(struct queue_entry_priv_usb);
2386                 break;
2387
2388         case QID_ATIM:
2389                 /* fallthrough */
2390         default:
2391                 BUG();
2392                 break;
2393         }
2394 }
2395
2396 static const struct rt2x00_ops rt73usb_ops = {
2397         .name                   = KBUILD_MODNAME,
2398         .max_ap_intf            = 4,
2399         .eeprom_size            = EEPROM_SIZE,
2400         .rf_size                = RF_SIZE,
2401         .tx_queues              = NUM_TX_QUEUES,
2402         .queue_init             = rt73usb_queue_init,
2403         .lib                    = &rt73usb_rt2x00_ops,
2404         .hw                     = &rt73usb_mac80211_ops,
2405 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
2406         .debugfs                = &rt73usb_rt2x00debug,
2407 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
2408 };
2409
2410 /*
2411  * rt73usb module information.
2412  */
2413 static struct usb_device_id rt73usb_device_table[] = {
2414         /* AboCom */
2415         { USB_DEVICE(0x07b8, 0xb21b) },
2416         { USB_DEVICE(0x07b8, 0xb21c) },
2417         { USB_DEVICE(0x07b8, 0xb21d) },
2418         { USB_DEVICE(0x07b8, 0xb21e) },
2419         { USB_DEVICE(0x07b8, 0xb21f) },
2420         /* AL */
2421         { USB_DEVICE(0x14b2, 0x3c10) },
2422         /* Amigo */
2423         { USB_DEVICE(0x148f, 0x9021) },
2424         { USB_DEVICE(0x0eb0, 0x9021) },
2425         /* AMIT  */
2426         { USB_DEVICE(0x18c5, 0x0002) },
2427         /* Askey */
2428         { USB_DEVICE(0x1690, 0x0722) },
2429         /* ASUS */
2430         { USB_DEVICE(0x0b05, 0x1723) },
2431         { USB_DEVICE(0x0b05, 0x1724) },
2432         /* Belkin */
2433         { USB_DEVICE(0x050d, 0x7050) }, /* FCC ID: K7SF5D7050B ver. 3.x */
2434         { USB_DEVICE(0x050d, 0x705a) },
2435         { USB_DEVICE(0x050d, 0x905b) },
2436         { USB_DEVICE(0x050d, 0x905c) },
2437         /* Billionton */
2438         { USB_DEVICE(0x1631, 0xc019) },
2439         { USB_DEVICE(0x08dd, 0x0120) },
2440         /* Buffalo */
2441         { USB_DEVICE(0x0411, 0x00d8) },
2442         { USB_DEVICE(0x0411, 0x00d9) },
2443         { USB_DEVICE(0x0411, 0x00e6) },
2444         { USB_DEVICE(0x0411, 0x00f4) },
2445         { USB_DEVICE(0x0411, 0x0116) },
2446         { USB_DEVICE(0x0411, 0x0119) },
2447         { USB_DEVICE(0x0411, 0x0137) },
2448         /* CEIVA */
2449         { USB_DEVICE(0x178d, 0x02be) },
2450         /* CNet */
2451         { USB_DEVICE(0x1371, 0x9022) },
2452         { USB_DEVICE(0x1371, 0x9032) },
2453         /* Conceptronic */
2454         { USB_DEVICE(0x14b2, 0x3c22) },
2455         /* Corega */
2456         { USB_DEVICE(0x07aa, 0x002e) },
2457         /* D-Link */
2458         { USB_DEVICE(0x07d1, 0x3c03) },
2459         { USB_DEVICE(0x07d1, 0x3c04) },
2460         { USB_DEVICE(0x07d1, 0x3c06) },
2461         { USB_DEVICE(0x07d1, 0x3c07) },
2462         /* Edimax */
2463         { USB_DEVICE(0x7392, 0x7318) },
2464         { USB_DEVICE(0x7392, 0x7618) },
2465         /* EnGenius */
2466         { USB_DEVICE(0x1740, 0x3701) },
2467         /* Gemtek */
2468         { USB_DEVICE(0x15a9, 0x0004) },
2469         /* Gigabyte */
2470         { USB_DEVICE(0x1044, 0x8008) },
2471         { USB_DEVICE(0x1044, 0x800a) },
2472         /* Huawei-3Com */
2473         { USB_DEVICE(0x1472, 0x0009) },
2474         /* Hercules */
2475         { USB_DEVICE(0x06f8, 0xe002) },
2476         { USB_DEVICE(0x06f8, 0xe010) },
2477         { USB_DEVICE(0x06f8, 0xe020) },
2478         /* Linksys */
2479         { USB_DEVICE(0x13b1, 0x0020) },
2480         { USB_DEVICE(0x13b1, 0x0023) },
2481         { USB_DEVICE(0x13b1, 0x0028) },
2482         /* MSI */
2483         { USB_DEVICE(0x0db0, 0x4600) },
2484         { USB_DEVICE(0x0db0, 0x6877) },
2485         { USB_DEVICE(0x0db0, 0x6874) },
2486         { USB_DEVICE(0x0db0, 0xa861) },
2487         { USB_DEVICE(0x0db0, 0xa874) },
2488         /* Ovislink */
2489         { USB_DEVICE(0x1b75, 0x7318) },
2490         /* Ralink */
2491         { USB_DEVICE(0x04bb, 0x093d) },
2492         { USB_DEVICE(0x148f, 0x2573) },
2493         { USB_DEVICE(0x148f, 0x2671) },
2494         { USB_DEVICE(0x0812, 0x3101) },
2495         /* Qcom */
2496         { USB_DEVICE(0x18e8, 0x6196) },
2497         { USB_DEVICE(0x18e8, 0x6229) },
2498         { USB_DEVICE(0x18e8, 0x6238) },
2499         /* Samsung */
2500         { USB_DEVICE(0x04e8, 0x4471) },
2501         /* Senao */
2502         { USB_DEVICE(0x1740, 0x7100) },
2503         /* Sitecom */
2504         { USB_DEVICE(0x0df6, 0x0024) },
2505         { USB_DEVICE(0x0df6, 0x0027) },
2506         { USB_DEVICE(0x0df6, 0x002f) },
2507         { USB_DEVICE(0x0df6, 0x90ac) },
2508         { USB_DEVICE(0x0df6, 0x9712) },
2509         /* Surecom */
2510         { USB_DEVICE(0x0769, 0x31f3) },
2511         /* Tilgin */
2512         { USB_DEVICE(0x6933, 0x5001) },
2513         /* Philips */
2514         { USB_DEVICE(0x0471, 0x200a) },
2515         /* Planex */
2516         { USB_DEVICE(0x2019, 0xab01) },
2517         { USB_DEVICE(0x2019, 0xab50) },
2518         /* WideTell */
2519         { USB_DEVICE(0x7167, 0x3840) },
2520         /* Zcom */
2521         { USB_DEVICE(0x0cde, 0x001c) },
2522         /* ZyXEL */
2523         { USB_DEVICE(0x0586, 0x3415) },
2524         { 0, }
2525 };
2526
2527 MODULE_AUTHOR(DRV_PROJECT);
2528 MODULE_VERSION(DRV_VERSION);
2529 MODULE_DESCRIPTION("Ralink RT73 USB Wireless LAN driver.");
2530 MODULE_SUPPORTED_DEVICE("Ralink RT2571W & RT2671 USB chipset based cards");
2531 MODULE_DEVICE_TABLE(usb, rt73usb_device_table);
2532 MODULE_FIRMWARE(FIRMWARE_RT2571);
2533 MODULE_LICENSE("GPL");
2534
2535 static int rt73usb_probe(struct usb_interface *usb_intf,
2536                          const struct usb_device_id *id)
2537 {
2538         return rt2x00usb_probe(usb_intf, &rt73usb_ops);
2539 }
2540
2541 static struct usb_driver rt73usb_driver = {
2542         .name           = KBUILD_MODNAME,
2543         .id_table       = rt73usb_device_table,
2544         .probe          = rt73usb_probe,
2545         .disconnect     = rt2x00usb_disconnect,
2546         .suspend        = rt2x00usb_suspend,
2547         .resume         = rt2x00usb_resume,
2548         .reset_resume   = rt2x00usb_resume,
2549         .disable_hub_initiated_lpm = 1,
2550 };
2551
2552 module_usb_driver(rt73usb_driver);