drivers/net/wireless/rtlwifi/rtl8192ee/hw.c

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2009-2014  Realtek Corporation.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * The full GNU General Public License is included in this distribution in the
  15  * file called LICENSE.
  16  *
  17  * Contact Information:
  18  * wlanfae <wlanfae@realtek.com>
  19  * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
  20  * Hsinchu 300, Taiwan.
  21  *
  22  * Larry Finger <Larry.Finger@lwfinger.net>
  23  *
  24  *****************************************************************************/
  25
  26 #include "../wifi.h"
  27 #include "../efuse.h"
  28 #include "../base.h"
  29 #include "../regd.h"
  30 #include "../cam.h"
  31 #include "../ps.h"
  32 #include "../pci.h"
  33 #include "reg.h"
  34 #include "def.h"
  35 #include "phy.h"
  36 #include "dm.h"
  37 #include "fw.h"
  38 #include "led.h"
  39 #include "hw.h"
  40 #include "../pwrseqcmd.h"
  41 #include "pwrseq.h"
  42
  43 #define LLT_CONFIG      5
  44
  45 static void _rtl92ee_set_bcn_ctrl_reg(struct ieee80211_hw *hw,
  46                                       u8 set_bits, u8 clear_bits)
  47 {
  48         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
  49         struct rtl_priv *rtlpriv = rtl_priv(hw);
  50
  51         rtlpci->reg_bcn_ctrl_val |= set_bits;
  52         rtlpci->reg_bcn_ctrl_val &= ~clear_bits;
  53
  54         rtl_write_byte(rtlpriv, REG_BCN_CTRL, (u8)rtlpci->reg_bcn_ctrl_val);
  55 }
  56
  57 static void _rtl92ee_stop_tx_beacon(struct ieee80211_hw *hw)
  58 {
  59         struct rtl_priv *rtlpriv = rtl_priv(hw);
  60         u8 tmp;
  61
  62         tmp = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);
  63         rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp & (~BIT(6)));
  64         rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0x64);
  65         tmp = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2);
  66         tmp &= ~(BIT(0));
  67         rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp);
  68 }
  69
  70 static void _rtl92ee_resume_tx_beacon(struct ieee80211_hw *hw)
  71 {
  72         struct rtl_priv *rtlpriv = rtl_priv(hw);
  73         u8 tmp;
  74
  75         tmp = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);
  76         rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp | BIT(6));
  77         rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff);
  78         tmp = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2);
  79         tmp |= BIT(0);
  80         rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp);
  81 }
  82
  83 static void _rtl92ee_enable_bcn_sub_func(struct ieee80211_hw *hw)
  84 {
  85         _rtl92ee_set_bcn_ctrl_reg(hw, 0, BIT(1));
  86 }
  87
  88 static void _rtl92ee_return_beacon_queue_skb(struct ieee80211_hw *hw)
  89 {
  90         struct rtl_priv *rtlpriv = rtl_priv(hw);
  91         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
  92         struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[BEACON_QUEUE];
  93         unsigned long flags;
  94
  95         spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags);
  96         while (skb_queue_len(&ring->queue)) {
  97                 struct rtl_tx_buffer_desc *entry =
  98                                                 &ring->buffer_desc[ring->idx];
  99                 struct sk_buff *skb = __skb_dequeue(&ring->queue);
 100
 101                 pci_unmap_single(rtlpci->pdev,
 102                                  rtlpriv->cfg->ops->get_desc(
 103                                  (u8 *)entry, true, HW_DESC_TXBUFF_ADDR),
 104                                  skb->len, PCI_DMA_TODEVICE);
 105                 kfree_skb(skb);
 106                 ring->idx = (ring->idx + 1) % ring->entries;
 107         }
 108         spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
 109 }
 110
 111 static void _rtl92ee_disable_bcn_sub_func(struct ieee80211_hw *hw)
 112 {
 113         _rtl92ee_set_bcn_ctrl_reg(hw, BIT(1), 0);
 114 }
 115
 116 static void _rtl92ee_set_fw_clock_on(struct ieee80211_hw *hw,
 117                                      u8 rpwm_val, bool b_need_turn_off_ckk)
 118 {
 119         struct rtl_priv *rtlpriv = rtl_priv(hw);
 120         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 121         bool b_support_remote_wake_up;
 122         u32 count = 0, isr_regaddr, content;
 123         bool b_schedule_timer = b_need_turn_off_ckk;
 124
 125         rtlpriv->cfg->ops->get_hw_reg(hw, HAL_DEF_WOWLAN,
 126                                       (u8 *)(&b_support_remote_wake_up));
 127
 128         if (!rtlhal->fw_ready)
 129                 return;
 130         if (!rtlpriv->psc.fw_current_inpsmode)
 131                 return;
 132
 133         while (1) {
 134                 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
 135                 if (rtlhal->fw_clk_change_in_progress) {
 136                         while (rtlhal->fw_clk_change_in_progress) {
 137                                 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
 138                                 count++;
 139                                 udelay(100);
 140                                 if (count > 1000)
 141                                         return;
 142                                 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
 143                         }
 144                         spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
 145                 } else {
 146                         rtlhal->fw_clk_change_in_progress = false;
 147                         spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
 148                         break;
 149                 }
 150         }
 151
 152         if (IS_IN_LOW_POWER_STATE_92E(rtlhal->fw_ps_state)) {
 153                 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_SET_RPWM,
 154                                               (u8 *)(&rpwm_val));
 155                 if (FW_PS_IS_ACK(rpwm_val)) {
 156                         isr_regaddr = REG_HISR;
 157                         content = rtl_read_dword(rtlpriv, isr_regaddr);
 158                         while (!(content & IMR_CPWM) && (count < 500)) {
 159                                 udelay(50);
 160                                 count++;
 161                                 content = rtl_read_dword(rtlpriv, isr_regaddr);
 162                         }
 163
 164                         if (content & IMR_CPWM) {
 165                                 rtl_write_word(rtlpriv, isr_regaddr, 0x0100);
 166                                 rtlhal->fw_ps_state = FW_PS_STATE_RF_ON_92E;
 167                                 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
 168                                          "Receive CPWM INT!!! PSState = %X\n",
 169                                          rtlhal->fw_ps_state);
 170                         }
 171                 }
 172
 173                 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
 174                 rtlhal->fw_clk_change_in_progress = false;
 175                 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
 176                 if (b_schedule_timer) {
 177                         mod_timer(&rtlpriv->works.fw_clockoff_timer,
 178                                   jiffies + MSECS(10));
 179                 }
 180         } else  {
 181                 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
 182                 rtlhal->fw_clk_change_in_progress = false;
 183                 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
 184         }
 185 }
 186
 187 static void _rtl92ee_set_fw_clock_off(struct ieee80211_hw *hw, u8 rpwm_val)
 188 {
 189         struct rtl_priv *rtlpriv = rtl_priv(hw);
 190         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 191         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 192         struct rtl8192_tx_ring *ring;
 193         enum rf_pwrstate rtstate;
 194         bool b_schedule_timer = false;
 195         u8 queue;
 196
 197         if (!rtlhal->fw_ready)
 198                 return;
 199         if (!rtlpriv->psc.fw_current_inpsmode)
 200                 return;
 201         if (!rtlhal->allow_sw_to_change_hwclc)
 202                 return;
 203
 204         rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_RF_STATE, (u8 *)(&rtstate));
 205         if (rtstate == ERFOFF || rtlpriv->psc.inactive_pwrstate == ERFOFF)
 206                 return;
 207
 208         for (queue = 0; queue < RTL_PCI_MAX_TX_QUEUE_COUNT; queue++) {
 209                 ring = &rtlpci->tx_ring[queue];
 210                 if (skb_queue_len(&ring->queue)) {
 211                         b_schedule_timer = true;
 212                         break;
 213                 }
 214         }
 215
 216         if (b_schedule_timer) {
 217                 mod_timer(&rtlpriv->works.fw_clockoff_timer,
 218                           jiffies + MSECS(10));
 219                 return;
 220         }
 221
 222         if (FW_PS_STATE(rtlhal->fw_ps_state) != FW_PS_STATE_RF_OFF_LOW_PWR) {
 223                 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
 224                 if (!rtlhal->fw_clk_change_in_progress) {
 225                         rtlhal->fw_clk_change_in_progress = true;
 226                         spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
 227                         rtlhal->fw_ps_state = FW_PS_STATE(rpwm_val);
 228                         rtl_write_word(rtlpriv, REG_HISR, 0x0100);
 229                         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SET_RPWM,
 230                                                       (u8 *)(&rpwm_val));
 231                         spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
 232                         rtlhal->fw_clk_change_in_progress = false;
 233                         spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
 234                 } else {
 235                         spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
 236                         mod_timer(&rtlpriv->works.fw_clockoff_timer,
 237                                   jiffies + MSECS(10));
 238                 }
 239         }
 240 }
 241
 242 static void _rtl92ee_set_fw_ps_rf_on(struct ieee80211_hw *hw)
 243 {
 244         u8 rpwm_val = 0;
 245
 246         rpwm_val |= (FW_PS_STATE_RF_OFF_92E | FW_PS_ACK);
 247         _rtl92ee_set_fw_clock_on(hw, rpwm_val, true);
 248 }
 249
 250 static void _rtl92ee_set_fw_ps_rf_off_low_power(struct ieee80211_hw *hw)
 251 {
 252         u8 rpwm_val = 0;
 253
 254         rpwm_val |= FW_PS_STATE_RF_OFF_LOW_PWR;
 255         _rtl92ee_set_fw_clock_off(hw, rpwm_val);
 256 }
 257
 258 void rtl92ee_fw_clk_off_timer_callback(unsigned long data)
 259 {
 260         struct ieee80211_hw *hw = (struct ieee80211_hw *)data;
 261
 262         _rtl92ee_set_fw_ps_rf_off_low_power(hw);
 263 }
 264
 265 static void _rtl92ee_fwlps_leave(struct ieee80211_hw *hw)
 266 {
 267         struct rtl_priv *rtlpriv = rtl_priv(hw);
 268         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
 269         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 270         bool fw_current_inps = false;
 271         u8 rpwm_val = 0, fw_pwrmode = FW_PS_ACTIVE_MODE;
 272
 273         if (ppsc->low_power_enable) {
 274                 rpwm_val = (FW_PS_STATE_ALL_ON_92E | FW_PS_ACK);/* RF on */
 275                 _rtl92ee_set_fw_clock_on(hw, rpwm_val, false);
 276                 rtlhal->allow_sw_to_change_hwclc = false;
 277                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_H2C_FW_PWRMODE,
 278                                               (u8 *)(&fw_pwrmode));
 279                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS,
 280                                               (u8 *)(&fw_current_inps));
 281         } else {
 282                 rpwm_val = FW_PS_STATE_ALL_ON_92E;      /* RF on */
 283                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SET_RPWM,
 284                                               (u8 *)(&rpwm_val));
 285                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_H2C_FW_PWRMODE,
 286                                               (u8 *)(&fw_pwrmode));
 287                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS,
 288                                               (u8 *)(&fw_current_inps));
 289         }
 290 }
 291
 292 static void _rtl92ee_fwlps_enter(struct ieee80211_hw *hw)
 293 {
 294         struct rtl_priv *rtlpriv = rtl_priv(hw);
 295         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
 296         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 297         bool fw_current_inps = true;
 298         u8 rpwm_val;
 299
 300         if (ppsc->low_power_enable) {
 301                 rpwm_val = FW_PS_STATE_RF_OFF_LOW_PWR;  /* RF off */
 302                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS,
 303                                               (u8 *)(&fw_current_inps));
 304                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_H2C_FW_PWRMODE,
 305                                               (u8 *)(&ppsc->fwctrl_psmode));
 306                 rtlhal->allow_sw_to_change_hwclc = true;
 307                 _rtl92ee_set_fw_clock_off(hw, rpwm_val);
 308         } else {
 309                 rpwm_val = FW_PS_STATE_RF_OFF_92E;      /* RF off */
 310                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS,
 311                                               (u8 *)(&fw_current_inps));
 312                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_H2C_FW_PWRMODE,
 313                                               (u8 *)(&ppsc->fwctrl_psmode));
 314                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SET_RPWM,
 315                                               (u8 *)(&rpwm_val));
 316         }
 317 }
 318
 319 void rtl92ee_get_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
 320 {
 321         struct rtl_priv *rtlpriv = rtl_priv(hw);
 322         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
 323         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 324
 325         switch (variable) {
 326         case HW_VAR_RCR:
 327                 *((u32 *)(val)) = rtlpci->receive_config;
 328                 break;
 329         case HW_VAR_RF_STATE:
 330                 *((enum rf_pwrstate *)(val)) = ppsc->rfpwr_state;
 331                 break;
 332         case HW_VAR_FWLPS_RF_ON:{
 333                         enum rf_pwrstate rfstate;
 334                         u32 val_rcr;
 335
 336                         rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_RF_STATE,
 337                                                       (u8 *)(&rfstate));
 338                         if (rfstate == ERFOFF) {
 339                                 *((bool *)(val)) = true;
 340                         } else {
 341                                 val_rcr = rtl_read_dword(rtlpriv, REG_RCR);
 342                                 val_rcr &= 0x00070000;
 343                                 if (val_rcr)
 344                                         *((bool *)(val)) = false;
 345                                 else
 346                                         *((bool *)(val)) = true;
 347                         }
 348                 }
 349                 break;
 350         case HW_VAR_FW_PSMODE_STATUS:
 351                 *((bool *)(val)) = ppsc->fw_current_inpsmode;
 352                 break;
 353         case HW_VAR_CORRECT_TSF:{
 354                 u64 tsf;
 355                 u32 *ptsf_low = (u32 *)&tsf;
 356                 u32 *ptsf_high = ((u32 *)&tsf) + 1;
 357
 358                 *ptsf_high = rtl_read_dword(rtlpriv, (REG_TSFTR + 4));
 359                 *ptsf_low = rtl_read_dword(rtlpriv, REG_TSFTR);
 360
 361                 *((u64 *)(val)) = tsf;
 362                 }
 363                 break;
 364         default:
 365                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
 366                          "switch case not process %x\n", variable);
 367                 break;
 368         }
 369 }
 370
 371 static void _rtl92ee_download_rsvd_page(struct ieee80211_hw *hw)
 372 {
 373         struct rtl_priv *rtlpriv = rtl_priv(hw);
 374         u8 tmp_regcr, tmp_reg422;
 375         u8 bcnvalid_reg, txbc_reg;
 376         u8 count = 0, dlbcn_count = 0;
 377         bool b_recover = false;
 378
 379         /*Set REG_CR bit 8. DMA beacon by SW.*/
 380         tmp_regcr = rtl_read_byte(rtlpriv, REG_CR + 1);
 381         rtl_write_byte(rtlpriv, REG_CR + 1, tmp_regcr | BIT(0));
 382
 383         /* Disable Hw protection for a time which revserd for Hw sending beacon.
 384          * Fix download reserved page packet fail
 385          * that access collision with the protection time.
 386          * 2010.05.11. Added by tynli.
 387          */
 388         _rtl92ee_set_bcn_ctrl_reg(hw, 0, BIT(3));
 389         _rtl92ee_set_bcn_ctrl_reg(hw, BIT(4), 0);
 390
 391         /* Set FWHW_TXQ_CTRL 0x422[6]=0 to
 392          * tell Hw the packet is not a real beacon frame.
 393          */
 394         tmp_reg422 = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);
 395         rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp_reg422 & (~BIT(6)));
 396
 397         if (tmp_reg422 & BIT(6))
 398                 b_recover = true;
 399
 400         do {
 401                 /* Clear beacon valid check bit */
 402                 bcnvalid_reg = rtl_read_byte(rtlpriv, REG_DWBCN0_CTRL + 2);
 403                 rtl_write_byte(rtlpriv, REG_DWBCN0_CTRL + 2,
 404                                bcnvalid_reg | BIT(0));
 405
 406                 /* Return Beacon TCB */
 407                 _rtl92ee_return_beacon_queue_skb(hw);
 408
 409                 /* download rsvd page */
 410                 rtl92ee_set_fw_rsvdpagepkt(hw, false);
 411
 412                 txbc_reg = rtl_read_byte(rtlpriv, REG_MGQ_TXBD_NUM + 3);
 413                 count = 0;
 414                 while ((txbc_reg & BIT(4)) && count < 20) {
 415                         count++;
 416                         udelay(10);
 417                         txbc_reg = rtl_read_byte(rtlpriv, REG_MGQ_TXBD_NUM + 3);
 418                 }
 419                 rtl_write_byte(rtlpriv, REG_MGQ_TXBD_NUM + 3,
 420                                txbc_reg | BIT(4));
 421
 422                 /* check rsvd page download OK. */
 423                 bcnvalid_reg = rtl_read_byte(rtlpriv, REG_DWBCN0_CTRL + 2);
 424                 count = 0;
 425                 while (!(bcnvalid_reg & BIT(0)) && count < 20) {
 426                         count++;
 427                         udelay(50);
 428                         bcnvalid_reg = rtl_read_byte(rtlpriv,
 429                                                      REG_DWBCN0_CTRL + 2);
 430                 }
 431
 432                 if (bcnvalid_reg & BIT(0))
 433                         rtl_write_byte(rtlpriv, REG_DWBCN0_CTRL + 2, BIT(0));
 434
 435                 dlbcn_count++;
 436         } while (!(bcnvalid_reg & BIT(0)) && dlbcn_count < 5);
 437
 438         if (!(bcnvalid_reg & BIT(0)))
 439                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
 440                          "Download RSVD page failed!\n");
 441
 442         /* Enable Bcn */
 443         _rtl92ee_set_bcn_ctrl_reg(hw, BIT(3), 0);
 444         _rtl92ee_set_bcn_ctrl_reg(hw, 0, BIT(4));
 445
 446         if (b_recover)
 447                 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp_reg422);
 448
 449         tmp_regcr = rtl_read_byte(rtlpriv, REG_CR + 1);
 450         rtl_write_byte(rtlpriv, REG_CR + 1, tmp_regcr & (~BIT(0)));
 451 }
 452
 453 void rtl92ee_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
 454 {
 455         struct rtl_priv *rtlpriv = rtl_priv(hw);
 456         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 457         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
 458         struct rtl_efuse *efuse = rtl_efuse(rtl_priv(hw));
 459         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
 460         u8 idx;
 461
 462         switch (variable) {
 463         case HW_VAR_ETHER_ADDR:
 464                 for (idx = 0; idx < ETH_ALEN; idx++)
 465                         rtl_write_byte(rtlpriv, (REG_MACID + idx), val[idx]);
 466                 break;
 467         case HW_VAR_BASIC_RATE:{
 468                 u16 b_rate_cfg = ((u16 *)val)[0];
 469
 470                 b_rate_cfg = b_rate_cfg & 0x15f;
 471                 b_rate_cfg |= 0x01;
 472                 b_rate_cfg = (b_rate_cfg | 0xd) & (~BIT(1));
 473                 rtl_write_byte(rtlpriv, REG_RRSR, b_rate_cfg & 0xff);
 474                 rtl_write_byte(rtlpriv, REG_RRSR + 1, (b_rate_cfg >> 8) & 0xff);
 475                 break; }
 476         case HW_VAR_BSSID:
 477                 for (idx = 0; idx < ETH_ALEN; idx++)
 478                         rtl_write_byte(rtlpriv, (REG_BSSID + idx), val[idx]);
 479                 break;
 480         case HW_VAR_SIFS:
 481                 rtl_write_byte(rtlpriv, REG_SIFS_CTX + 1, val[0]);
 482                 rtl_write_byte(rtlpriv, REG_SIFS_TRX + 1, val[1]);
 483
 484                 rtl_write_byte(rtlpriv, REG_SPEC_SIFS + 1, val[0]);
 485                 rtl_write_byte(rtlpriv, REG_MAC_SPEC_SIFS + 1, val[0]);
 486
 487                 if (!mac->ht_enable)
 488                         rtl_write_word(rtlpriv, REG_RESP_SIFS_OFDM, 0x0e0e);
 489                 else
 490                         rtl_write_word(rtlpriv, REG_RESP_SIFS_OFDM,
 491                                        *((u16 *)val));
 492                 break;
 493         case HW_VAR_SLOT_TIME:{
 494                 u8 e_aci;
 495
 496                 RT_TRACE(rtlpriv, COMP_MLME, DBG_TRACE,
 497                          "HW_VAR_SLOT_TIME %x\n", val[0]);
 498
 499                 rtl_write_byte(rtlpriv, REG_SLOT, val[0]);
 500
 501                 for (e_aci = 0; e_aci < AC_MAX; e_aci++) {
 502                         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_AC_PARAM,
 503                                                       (u8 *)(&e_aci));
 504                 }
 505                 break; }
 506         case HW_VAR_ACK_PREAMBLE:{
 507                 u8 reg_tmp;
 508                 u8 short_preamble = (bool)(*(u8 *)val);
 509
 510                 reg_tmp = (rtlpriv->mac80211.cur_40_prime_sc) << 5;
 511                 if (short_preamble)
 512                         reg_tmp |= 0x80;
 513                 rtl_write_byte(rtlpriv, REG_RRSR + 2, reg_tmp);
 514                 rtlpriv->mac80211.short_preamble = short_preamble;
 515                 }
 516                 break;
 517         case HW_VAR_WPA_CONFIG:
 518                 rtl_write_byte(rtlpriv, REG_SECCFG, *((u8 *)val));
 519                 break;
 520         case HW_VAR_AMPDU_FACTOR:{
 521                 u8 regtoset_normal[4] = { 0x41, 0xa8, 0x72, 0xb9 };
 522                 u8 fac;
 523                 u8 *reg = NULL;
 524                 u8 i = 0;
 525
 526                 reg = regtoset_normal;
 527
 528                 fac = *((u8 *)val);
 529                 if (fac <= 3) {
 530                         fac = (1 << (fac + 2));
 531                         if (fac > 0xf)
 532                                 fac = 0xf;
 533                         for (i = 0; i < 4; i++) {
 534                                 if ((reg[i] & 0xf0) > (fac << 4))
 535                                         reg[i] = (reg[i] & 0x0f) |
 536                                                 (fac << 4);
 537                                 if ((reg[i] & 0x0f) > fac)
 538                                         reg[i] = (reg[i] & 0xf0) | fac;
 539                                 rtl_write_byte(rtlpriv,
 540                                                (REG_AGGLEN_LMT + i),
 541                                                reg[i]);
 542                         }
 543                         RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
 544                                  "Set HW_VAR_AMPDU_FACTOR:%#x\n", fac);
 545                 }
 546                 }
 547                 break;
 548         case HW_VAR_AC_PARAM:{
 549                 u8 e_aci = *((u8 *)val);
 550
 551                 if (rtlpci->acm_method != EACMWAY2_SW)
 552                         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_ACM_CTRL,
 553                                                       (u8 *)(&e_aci));
 554                 }
 555                 break;
 556         case HW_VAR_ACM_CTRL:{
 557                 u8 e_aci = *((u8 *)val);
 558                 union aci_aifsn *aifs = (union aci_aifsn *)(&mac->ac[0].aifs);
 559
 560                 u8 acm = aifs->f.acm;
 561                 u8 acm_ctrl = rtl_read_byte(rtlpriv, REG_ACMHWCTRL);
 562
 563                 acm_ctrl = acm_ctrl | ((rtlpci->acm_method == 2) ? 0x0 : 0x1);
 564
 565                 if (acm) {
 566                         switch (e_aci) {
 567                         case AC0_BE:
 568                                 acm_ctrl |= ACMHW_BEQEN;
 569                                 break;
 570                         case AC2_VI:
 571                                 acm_ctrl |= ACMHW_VIQEN;
 572                                 break;
 573                         case AC3_VO:
 574                                 acm_ctrl |= ACMHW_VOQEN;
 575                                 break;
 576                         default:
 577                                 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
 578                                          "HW_VAR_ACM_CTRL acm set failed: eACI is %d\n",
 579                                          acm);
 580                                 break;
 581                         }
 582                 } else {
 583                         switch (e_aci) {
 584                         case AC0_BE:
 585                                 acm_ctrl &= (~ACMHW_BEQEN);
 586                                 break;
 587                         case AC2_VI:
 588                                 acm_ctrl &= (~ACMHW_VIQEN);
 589                                 break;
 590                         case AC3_VO:
 591                                 acm_ctrl &= (~ACMHW_BEQEN);
 592                                 break;
 593                         default:
 594                                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
 595                                          "switch case not process\n");
 596                                 break;
 597                         }
 598                 }
 599
 600                 RT_TRACE(rtlpriv, COMP_QOS, DBG_TRACE,
 601                          "SetHwReg8190pci(): [HW_VAR_ACM_CTRL] Write 0x%X\n",
 602                           acm_ctrl);
 603                 rtl_write_byte(rtlpriv, REG_ACMHWCTRL, acm_ctrl);
 604                 }
 605                 break;
 606         case HW_VAR_RCR:{
 607                 rtl_write_dword(rtlpriv, REG_RCR, ((u32 *)(val))[0]);
 608                 rtlpci->receive_config = ((u32 *)(val))[0];
 609                 }
 610                 break;
 611         case HW_VAR_RETRY_LIMIT:{
 612                 u8 retry_limit = ((u8 *)(val))[0];
 613
 614                 rtl_write_word(rtlpriv, REG_RETRY_LIMIT,
 615                                retry_limit << RETRY_LIMIT_SHORT_SHIFT |
 616                                retry_limit << RETRY_LIMIT_LONG_SHIFT);
 617                 }
 618                 break;
 619         case HW_VAR_DUAL_TSF_RST:
 620                 rtl_write_byte(rtlpriv, REG_DUAL_TSF_RST, (BIT(0) | BIT(1)));
 621                 break;
 622         case HW_VAR_EFUSE_BYTES:
 623                 efuse->efuse_usedbytes = *((u16 *)val);
 624                 break;
 625         case HW_VAR_EFUSE_USAGE:
 626                 efuse->efuse_usedpercentage = *((u8 *)val);
 627                 break;
 628         case HW_VAR_IO_CMD:
 629                 rtl92ee_phy_set_io_cmd(hw, (*(enum io_type *)val));
 630                 break;
 631         case HW_VAR_SET_RPWM:{
 632                 u8 rpwm_val;
 633
 634                 rpwm_val = rtl_read_byte(rtlpriv, REG_PCIE_HRPWM);
 635                 udelay(1);
 636
 637                 if (rpwm_val & BIT(7)) {
 638                         rtl_write_byte(rtlpriv, REG_PCIE_HRPWM, (*(u8 *)val));
 639                 } else {
 640                         rtl_write_byte(rtlpriv, REG_PCIE_HRPWM,
 641                                        ((*(u8 *)val) | BIT(7)));
 642                 }
 643                 }
 644                 break;
 645         case HW_VAR_H2C_FW_PWRMODE:
 646                 rtl92ee_set_fw_pwrmode_cmd(hw, (*(u8 *)val));
 647                 break;
 648         case HW_VAR_FW_PSMODE_STATUS:
 649                 ppsc->fw_current_inpsmode = *((bool *)val);
 650                 break;
 651         case HW_VAR_RESUME_CLK_ON:
 652                 _rtl92ee_set_fw_ps_rf_on(hw);
 653                 break;
 654         case HW_VAR_FW_LPS_ACTION:{
 655                 bool b_enter_fwlps = *((bool *)val);
 656
 657                 if (b_enter_fwlps)
 658                         _rtl92ee_fwlps_enter(hw);
 659                 else
 660                         _rtl92ee_fwlps_leave(hw);
 661                 }
 662                 break;
 663         case HW_VAR_H2C_FW_JOINBSSRPT:{
 664                 u8 mstatus = (*(u8 *)val);
 665
 666                 if (mstatus == RT_MEDIA_CONNECT) {
 667                         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_AID, NULL);
 668                         _rtl92ee_download_rsvd_page(hw);
 669                 }
 670                 rtl92ee_set_fw_media_status_rpt_cmd(hw, mstatus);
 671                 }
 672                 break;
 673         case HW_VAR_H2C_FW_P2P_PS_OFFLOAD:
 674                 rtl92ee_set_p2p_ps_offload_cmd(hw, (*(u8 *)val));
 675                 break;
 676         case HW_VAR_AID:{
 677                 u16 u2btmp;
 678
 679                 u2btmp = rtl_read_word(rtlpriv, REG_BCN_PSR_RPT);
 680                 u2btmp &= 0xC000;
 681                 rtl_write_word(rtlpriv, REG_BCN_PSR_RPT,
 682                                (u2btmp | mac->assoc_id));
 683                 }
 684                 break;
 685         case HW_VAR_CORRECT_TSF:{
 686                 u8 btype_ibss = ((u8 *)(val))[0];
 687
 688                 if (btype_ibss)
 689                         _rtl92ee_stop_tx_beacon(hw);
 690
 691                 _rtl92ee_set_bcn_ctrl_reg(hw, 0, BIT(3));
 692
 693                 rtl_write_dword(rtlpriv, REG_TSFTR,
 694                                 (u32)(mac->tsf & 0xffffffff));
 695                 rtl_write_dword(rtlpriv, REG_TSFTR + 4,
 696                                 (u32)((mac->tsf >> 32) & 0xffffffff));
 697
 698                 _rtl92ee_set_bcn_ctrl_reg(hw, BIT(3), 0);
 699
 700                 if (btype_ibss)
 701                         _rtl92ee_resume_tx_beacon(hw);
 702                 }
 703                 break;
 704         case HW_VAR_KEEP_ALIVE: {
 705                 u8 array[2];
 706
 707                 array[0] = 0xff;
 708                 array[1] = *((u8 *)val);
 709                 rtl92ee_fill_h2c_cmd(hw, H2C_92E_KEEP_ALIVE_CTRL, 2, array);
 710                 }
 711                 break;
 712         default:
 713                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
 714                          "switch case not process %x\n", variable);
 715                 break;
 716         }
 717 }
 718
 719 static bool _rtl92ee_llt_table_init(struct ieee80211_hw *hw)
 720 {
 721         struct rtl_priv *rtlpriv = rtl_priv(hw);
 722         u8 txpktbuf_bndy;
 723         u8 u8tmp, testcnt = 0;
 724
 725         txpktbuf_bndy = 0xFA;
 726
 727         rtl_write_dword(rtlpriv, REG_RQPN, 0x80E90808);
 728
 729         rtl_write_byte(rtlpriv, REG_TRXFF_BNDY, txpktbuf_bndy);
 730         rtl_write_word(rtlpriv, REG_TRXFF_BNDY + 2, 0x3d00 - 1);
 731
 732         rtl_write_byte(rtlpriv, REG_DWBCN0_CTRL + 1, txpktbuf_bndy);
 733         rtl_write_byte(rtlpriv, REG_DWBCN1_CTRL + 1, txpktbuf_bndy);
 734
 735         rtl_write_byte(rtlpriv, REG_BCNQ_BDNY, txpktbuf_bndy);
 736         rtl_write_byte(rtlpriv, REG_BCNQ1_BDNY, txpktbuf_bndy);
 737
 738         rtl_write_byte(rtlpriv, REG_MGQ_BDNY, txpktbuf_bndy);
 739         rtl_write_byte(rtlpriv, 0x45D, txpktbuf_bndy);
 740
 741         rtl_write_byte(rtlpriv, REG_PBP, 0x31);
 742         rtl_write_byte(rtlpriv, REG_RX_DRVINFO_SZ, 0x4);
 743
 744         u8tmp = rtl_read_byte(rtlpriv, REG_AUTO_LLT + 2);
 745         rtl_write_byte(rtlpriv, REG_AUTO_LLT + 2, u8tmp | BIT(0));
 746
 747         while (u8tmp & BIT(0)) {
 748                 u8tmp = rtl_read_byte(rtlpriv, REG_AUTO_LLT + 2);
 749                 udelay(10);
 750                 testcnt++;
 751                 if (testcnt > 10)
 752                         break;
 753         }
 754
 755         return true;
 756 }
 757
 758 static void _rtl92ee_gen_refresh_led_state(struct ieee80211_hw *hw)
 759 {
 760         struct rtl_priv *rtlpriv = rtl_priv(hw);
 761         struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
 762         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
 763         struct rtl_led *pled0 = &pcipriv->ledctl.sw_led0;
 764
 765         if (rtlpriv->rtlhal.up_first_time)
 766                 return;
 767
 768         if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS)
 769                 rtl92ee_sw_led_on(hw, pled0);
 770         else if (ppsc->rfoff_reason == RF_CHANGE_BY_INIT)
 771                 rtl92ee_sw_led_on(hw, pled0);
 772         else
 773                 rtl92ee_sw_led_off(hw, pled0);
 774 }
 775
 776 static bool _rtl92ee_init_mac(struct ieee80211_hw *hw)
 777 {
 778         struct rtl_priv *rtlpriv = rtl_priv(hw);
 779         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 780         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 781
 782         u8 bytetmp;
 783         u16 wordtmp;
 784         u32 dwordtmp;
 785
 786         rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x0);
 787
 788         dwordtmp = rtl_read_dword(rtlpriv, REG_SYS_CFG1);
 789         if (dwordtmp & BIT(24)) {
 790                 rtl_write_byte(rtlpriv, 0x7c, 0xc3);
 791         } else {
 792                 bytetmp = rtl_read_byte(rtlpriv, 0x16);
 793                 rtl_write_byte(rtlpriv, 0x16, bytetmp | BIT(4) | BIT(6));
 794                 rtl_write_byte(rtlpriv, 0x7c, 0x83);
 795         }
 796         /* 1. 40Mhz crystal source*/
 797         bytetmp = rtl_read_byte(rtlpriv, REG_AFE_CTRL2);
 798         bytetmp &= 0xfb;
 799         rtl_write_byte(rtlpriv, REG_AFE_CTRL2, bytetmp);
 800
 801         dwordtmp = rtl_read_dword(rtlpriv, REG_AFE_CTRL4);
 802         dwordtmp &= 0xfffffc7f;
 803         rtl_write_dword(rtlpriv, REG_AFE_CTRL4, dwordtmp);
 804
 805         /* 2. 92E AFE parameter
 806          * MP chip then check version
 807          */
 808         bytetmp = rtl_read_byte(rtlpriv, REG_AFE_CTRL2);
 809         bytetmp &= 0xbf;
 810         rtl_write_byte(rtlpriv, REG_AFE_CTRL2, bytetmp);
 811
 812         dwordtmp = rtl_read_dword(rtlpriv, REG_AFE_CTRL4);
 813         dwordtmp &= 0xffdfffff;
 814         rtl_write_dword(rtlpriv, REG_AFE_CTRL4, dwordtmp);
 815
 816         /* HW Power on sequence */
 817         if (!rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,
 818                                       PWR_INTF_PCI_MSK,
 819                                       RTL8192E_NIC_ENABLE_FLOW)) {
 820                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
 821                          "init MAC Fail as rtl_hal_pwrseqcmdparsing\n");
 822                 return false;
 823         }
 824
 825         /* Release MAC IO register reset */
 826         bytetmp = rtl_read_byte(rtlpriv, REG_CR);
 827         bytetmp = 0xff;
 828         rtl_write_byte(rtlpriv, REG_CR, bytetmp);
 829         mdelay(2);
 830         bytetmp = 0x7f;
 831         rtl_write_byte(rtlpriv, REG_HWSEQ_CTRL, bytetmp);
 832         mdelay(2);
 833
 834         /* Add for wakeup online */
 835         bytetmp = rtl_read_byte(rtlpriv, REG_SYS_CLKR);
 836         rtl_write_byte(rtlpriv, REG_SYS_CLKR, bytetmp | BIT(3));
 837         bytetmp = rtl_read_byte(rtlpriv, REG_GPIO_MUXCFG + 1);
 838         rtl_write_byte(rtlpriv, REG_GPIO_MUXCFG + 1, bytetmp & (~BIT(4)));
 839         /* Release MAC IO register reset */
 840         rtl_write_word(rtlpriv, REG_CR, 0x2ff);
 841
 842         if (!rtlhal->mac_func_enable) {
 843                 if (_rtl92ee_llt_table_init(hw) == false) {
 844                         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
 845                                  "LLT table init fail\n");
 846                         return false;
 847                 }
 848         }
 849
 850         rtl_write_dword(rtlpriv, REG_HISR, 0xffffffff);
 851         rtl_write_dword(rtlpriv, REG_HISRE, 0xffffffff);
 852
 853         wordtmp = rtl_read_word(rtlpriv, REG_TRXDMA_CTRL);
 854         wordtmp &= 0xf;
 855         wordtmp |= 0xF5B1;
 856         rtl_write_word(rtlpriv, REG_TRXDMA_CTRL, wordtmp);
 857         /* Reported Tx status from HW for rate adaptive.*/
 858         rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 1, 0x1F);
 859
 860         /* Set RCR register */
 861         rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config);
 862         rtl_write_word(rtlpriv, REG_RXFLTMAP2, 0xffff);
 863
 864         /* Set TCR register */
 865         rtl_write_dword(rtlpriv, REG_TCR, rtlpci->transmit_config);
 866
 867         /* Set TX/RX descriptor physical address(from OS API). */
 868         rtl_write_dword(rtlpriv, REG_BCNQ_DESA,
 869                         ((u64)rtlpci->tx_ring[BEACON_QUEUE].buffer_desc_dma) &
 870                         DMA_BIT_MASK(32));
 871         rtl_write_dword(rtlpriv, REG_MGQ_DESA,
 872                         (u64)rtlpci->tx_ring[MGNT_QUEUE].buffer_desc_dma &
 873                         DMA_BIT_MASK(32));
 874         rtl_write_dword(rtlpriv, REG_VOQ_DESA,
 875                         (u64)rtlpci->tx_ring[VO_QUEUE].buffer_desc_dma &
 876                         DMA_BIT_MASK(32));
 877         rtl_write_dword(rtlpriv, REG_VIQ_DESA,
 878                         (u64)rtlpci->tx_ring[VI_QUEUE].buffer_desc_dma &
 879                         DMA_BIT_MASK(32));
 880
 881         rtl_write_dword(rtlpriv, REG_BEQ_DESA,
 882                         (u64)rtlpci->tx_ring[BE_QUEUE].buffer_desc_dma &
 883                         DMA_BIT_MASK(32));
 884
 885         dwordtmp = rtl_read_dword(rtlpriv, REG_BEQ_DESA);
 886
 887         rtl_write_dword(rtlpriv, REG_BKQ_DESA,
 888                         (u64)rtlpci->tx_ring[BK_QUEUE].buffer_desc_dma &
 889                         DMA_BIT_MASK(32));
 890         rtl_write_dword(rtlpriv, REG_HQ0_DESA,
 891                         (u64)rtlpci->tx_ring[HIGH_QUEUE].buffer_desc_dma &
 892                         DMA_BIT_MASK(32));
 893
 894         rtl_write_dword(rtlpriv, REG_RX_DESA,
 895                         (u64)rtlpci->rx_ring[RX_MPDU_QUEUE].dma &
 896                         DMA_BIT_MASK(32));
 897
 898         /* if we want to support 64 bit DMA, we should set it here,
 899          * but now we do not support 64 bit DMA
 900          */
 901
 902         rtl_write_dword(rtlpriv, REG_TSFTIMER_HCI, 0x3fffffff);
 903
 904         bytetmp = rtl_read_byte(rtlpriv, REG_PCIE_CTRL_REG + 3);
 905         rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 3, bytetmp | 0xF7);
 906
 907         rtl_write_dword(rtlpriv, REG_INT_MIG, 0);
 908
 909         rtl_write_dword(rtlpriv, REG_MCUTST_1, 0x0);
 910
 911         rtl_write_word(rtlpriv, REG_MGQ_TXBD_NUM,
 912                        TX_DESC_NUM_92E | ((RTL8192EE_SEG_NUM << 12) & 0x3000));
 913         rtl_write_word(rtlpriv, REG_VOQ_TXBD_NUM,
 914                        TX_DESC_NUM_92E | ((RTL8192EE_SEG_NUM << 12) & 0x3000));
 915         rtl_write_word(rtlpriv, REG_VIQ_TXBD_NUM,
 916                        TX_DESC_NUM_92E | ((RTL8192EE_SEG_NUM << 12) & 0x3000));
 917         rtl_write_word(rtlpriv, REG_BEQ_TXBD_NUM,
 918                        TX_DESC_NUM_92E | ((RTL8192EE_SEG_NUM << 12) & 0x3000));
 919         rtl_write_word(rtlpriv, REG_VOQ_TXBD_NUM,
 920                        TX_DESC_NUM_92E | ((RTL8192EE_SEG_NUM << 12) & 0x3000));
 921         rtl_write_word(rtlpriv, REG_BKQ_TXBD_NUM,
 922                        TX_DESC_NUM_92E | ((RTL8192EE_SEG_NUM << 12) & 0x3000));
 923         rtl_write_word(rtlpriv, REG_HI0Q_TXBD_NUM,
 924                        TX_DESC_NUM_92E | ((RTL8192EE_SEG_NUM << 12) & 0x3000));
 925         rtl_write_word(rtlpriv, REG_HI1Q_TXBD_NUM,
 926                        TX_DESC_NUM_92E | ((RTL8192EE_SEG_NUM << 12) & 0x3000));
 927         rtl_write_word(rtlpriv, REG_HI2Q_TXBD_NUM,
 928                        TX_DESC_NUM_92E | ((RTL8192EE_SEG_NUM << 12) & 0x3000));
 929         rtl_write_word(rtlpriv, REG_HI3Q_TXBD_NUM,
 930                        TX_DESC_NUM_92E | ((RTL8192EE_SEG_NUM << 12) & 0x3000));
 931         rtl_write_word(rtlpriv, REG_HI4Q_TXBD_NUM,
 932                        TX_DESC_NUM_92E | ((RTL8192EE_SEG_NUM << 12) & 0x3000));
 933         rtl_write_word(rtlpriv, REG_HI5Q_TXBD_NUM,
 934                        TX_DESC_NUM_92E | ((RTL8192EE_SEG_NUM << 12) & 0x3000));
 935         rtl_write_word(rtlpriv, REG_HI6Q_TXBD_NUM,
 936                        TX_DESC_NUM_92E | ((RTL8192EE_SEG_NUM << 12) & 0x3000));
 937         rtl_write_word(rtlpriv, REG_HI7Q_TXBD_NUM,
 938                        TX_DESC_NUM_92E | ((RTL8192EE_SEG_NUM << 12) & 0x3000));
 939         /*Rx*/
 940 #if (DMA_IS_64BIT == 1)
 941         rtl_write_word(rtlpriv, REG_RX_RXBD_NUM,
 942                        RX_DESC_NUM_92E |
 943                        ((RTL8192EE_SEG_NUM << 13) & 0x6000) | 0x8000);
 944 #else
 945         rtl_write_word(rtlpriv, REG_RX_RXBD_NUM,
 946                        RX_DESC_NUM_92E |
 947                        ((RTL8192EE_SEG_NUM << 13) & 0x6000) | 0x0000);
 948 #endif
 949
 950         rtl_write_dword(rtlpriv, REG_TSFTIMER_HCI, 0XFFFFFFFF);
 951
 952         _rtl92ee_gen_refresh_led_state(hw);
 953         return true;
 954 }
 955
 956 static void _rtl92ee_hw_configure(struct ieee80211_hw *hw)
 957 {
 958         struct rtl_priv *rtlpriv = rtl_priv(hw);
 959         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 960         u32 reg_rrsr;
 961
 962         reg_rrsr = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
 963         /* Init value for RRSR. */
 964         rtl_write_dword(rtlpriv, REG_RRSR, reg_rrsr);
 965
 966         /* ARFB table 9 for 11ac 5G 2SS */
 967         rtl_write_dword(rtlpriv, REG_ARFR0, 0x00000010);
 968         rtl_write_dword(rtlpriv, REG_ARFR0 + 4, 0x3e0ff000);
 969
 970         /* ARFB table 10 for 11ac 5G 1SS */
 971         rtl_write_dword(rtlpriv, REG_ARFR1, 0x00000010);
 972         rtl_write_dword(rtlpriv, REG_ARFR1 + 4, 0x000ff000);
 973
 974         /* Set SLOT time */
 975         rtl_write_byte(rtlpriv, REG_SLOT, 0x09);
 976
 977         /* CF-End setting. */
 978         rtl_write_word(rtlpriv, REG_FWHW_TXQ_CTRL, 0x1F80);
 979
 980         /* Set retry limit */
 981         rtl_write_word(rtlpriv, REG_RETRY_LIMIT, 0x0707);
 982
 983         /* BAR settings */
 984         rtl_write_dword(rtlpriv, REG_BAR_MODE_CTRL, 0x0201ffff);
 985
 986         /* Set Data / Response auto rate fallack retry count */
 987         rtl_write_dword(rtlpriv, REG_DARFRC, 0x01000000);
 988         rtl_write_dword(rtlpriv, REG_DARFRC + 4, 0x07060504);
 989         rtl_write_dword(rtlpriv, REG_RARFRC, 0x01000000);
 990         rtl_write_dword(rtlpriv, REG_RARFRC + 4, 0x07060504);
 991
 992         /* Beacon related, for rate adaptive */
 993         rtl_write_byte(rtlpriv, REG_ATIMWND, 0x2);
 994         rtl_write_byte(rtlpriv, REG_BCN_MAX_ERR, 0xff);
 995
 996         rtlpci->reg_bcn_ctrl_val = 0x1d;
 997         rtl_write_byte(rtlpriv, REG_BCN_CTRL, rtlpci->reg_bcn_ctrl_val);
 998
 999         /* Marked out by Bruce, 2010-09-09.
1000          * This register is configured for the 2nd Beacon (multiple BSSID).
1001          * We shall disable this register if we only support 1 BSSID.
1002          * vivi guess 92d also need this, also 92d now doesnot set this reg
1003          */
1004         rtl_write_byte(rtlpriv, REG_BCN_CTRL_1, 0);
1005
1006         /* TBTT prohibit hold time. Suggested by designer TimChen. */
1007         rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff); /* 8 ms */
1008
1009         rtl_write_byte(rtlpriv, REG_PIFS, 0);
1010         rtl_write_byte(rtlpriv, REG_AGGR_BREAK_TIME, 0x16);
1011
1012         rtl_write_word(rtlpriv, REG_NAV_PROT_LEN, 0x0040);
1013         rtl_write_word(rtlpriv, REG_PROT_MODE_CTRL, 0x08ff);
1014
1015         /* For Rx TP. Suggested by SD1 Richard. Added by tynli. 2010.04.12.*/
1016         rtl_write_dword(rtlpriv, REG_FAST_EDCA_CTRL, 0x03086666);
1017
1018         /* ACKTO for IOT issue. */
1019         rtl_write_byte(rtlpriv, REG_ACKTO, 0x40);
1020
1021         /* Set Spec SIFS (used in NAV) */
1022         rtl_write_word(rtlpriv, REG_SPEC_SIFS, 0x100a);
1023         rtl_write_word(rtlpriv, REG_MAC_SPEC_SIFS, 0x100a);
1024
1025         /* Set SIFS for CCK */
1026         rtl_write_word(rtlpriv, REG_SIFS_CTX, 0x100a);
1027
1028         /* Set SIFS for OFDM */
1029         rtl_write_word(rtlpriv, REG_SIFS_TRX, 0x100a);
1030
1031         /* Note Data sheet don't define */
1032         rtl_write_word(rtlpriv, 0x4C7, 0x80);
1033
1034         rtl_write_byte(rtlpriv, REG_RX_PKT_LIMIT, 0x20);
1035
1036         rtl_write_word(rtlpriv, REG_MAX_AGGR_NUM, 0x1717);
1037
1038         /* Set Multicast Address. 2009.01.07. by tynli. */
1039         rtl_write_dword(rtlpriv, REG_MAR, 0xffffffff);
1040         rtl_write_dword(rtlpriv, REG_MAR + 4, 0xffffffff);
1041 }
1042
1043 static void _rtl92ee_enable_aspm_back_door(struct ieee80211_hw *hw)
1044 {
1045         struct rtl_priv *rtlpriv = rtl_priv(hw);
1046         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1047         u32 tmp32 = 0, count = 0;
1048         u8 tmp8 = 0;
1049
1050         rtl_write_word(rtlpriv, REG_BACKDOOR_DBI_DATA, 0x78);
1051         rtl_write_byte(rtlpriv, REG_BACKDOOR_DBI_DATA + 2, 0x2);
1052         tmp8 = rtl_read_byte(rtlpriv, REG_BACKDOOR_DBI_DATA + 2);
1053         count = 0;
1054         while (tmp8 && count < 20) {
1055                 udelay(10);
1056                 tmp8 = rtl_read_byte(rtlpriv, REG_BACKDOOR_DBI_DATA + 2);
1057                 count++;
1058         }
1059
1060         if (0 == tmp8) {
1061                 tmp32 = rtl_read_dword(rtlpriv, REG_BACKDOOR_DBI_RDATA);
1062                 if ((tmp32 & 0xff00) != 0x2000) {
1063                         tmp32 &= 0xffff00ff;
1064                         rtl_write_dword(rtlpriv, REG_BACKDOOR_DBI_WDATA,
1065                                         tmp32 | BIT(13));
1066                         rtl_write_word(rtlpriv, REG_BACKDOOR_DBI_DATA, 0xf078);
1067                         rtl_write_byte(rtlpriv, REG_BACKDOOR_DBI_DATA + 2, 0x1);
1068
1069                         tmp8 = rtl_read_byte(rtlpriv,
1070                                              REG_BACKDOOR_DBI_DATA + 2);
1071                         count = 0;
1072                         while (tmp8 && count < 20) {
1073                                 udelay(10);
1074                                 tmp8 = rtl_read_byte(rtlpriv,
1075                                                      REG_BACKDOOR_DBI_DATA + 2);
1076                                 count++;
1077                         }
1078                 }
1079         }
1080
1081         rtl_write_word(rtlpriv, REG_BACKDOOR_DBI_DATA, 0x70c);
1082         rtl_write_byte(rtlpriv, REG_BACKDOOR_DBI_DATA + 2, 0x2);
1083         tmp8 = rtl_read_byte(rtlpriv, REG_BACKDOOR_DBI_DATA + 2);
1084         count = 0;
1085         while (tmp8 && count < 20) {
1086                 udelay(10);
1087                 tmp8 = rtl_read_byte(rtlpriv, REG_BACKDOOR_DBI_DATA + 2);
1088                 count++;
1089         }
1090         if (0 == tmp8) {
1091                 tmp32 = rtl_read_dword(rtlpriv, REG_BACKDOOR_DBI_RDATA);
1092                 rtl_write_dword(rtlpriv, REG_BACKDOOR_DBI_WDATA,
1093                                 tmp32 | BIT(31));
1094                 rtl_write_word(rtlpriv, REG_BACKDOOR_DBI_DATA, 0xf70c);
1095                 rtl_write_byte(rtlpriv, REG_BACKDOOR_DBI_DATA + 2, 0x1);
1096         }
1097
1098         tmp8 = rtl_read_byte(rtlpriv, REG_BACKDOOR_DBI_DATA + 2);
1099         count = 0;
1100         while (tmp8 && count < 20) {
1101                 udelay(10);
1102                 tmp8 = rtl_read_byte(rtlpriv, REG_BACKDOOR_DBI_DATA + 2);
1103                 count++;
1104         }
1105
1106         rtl_write_word(rtlpriv, REG_BACKDOOR_DBI_DATA, 0x718);
1107         rtl_write_byte(rtlpriv, REG_BACKDOOR_DBI_DATA + 2, 0x2);
1108         tmp8 = rtl_read_byte(rtlpriv, REG_BACKDOOR_DBI_DATA + 2);
1109         count = 0;
1110         while (tmp8 && count < 20) {
1111                 udelay(10);
1112                 tmp8 = rtl_read_byte(rtlpriv, REG_BACKDOOR_DBI_DATA + 2);
1113                 count++;
1114         }
1115         if (ppsc->support_backdoor || (0 == tmp8)) {
1116                 tmp32 = rtl_read_dword(rtlpriv, REG_BACKDOOR_DBI_RDATA);
1117                 rtl_write_dword(rtlpriv, REG_BACKDOOR_DBI_WDATA,
1118                                 tmp32 | BIT(11) | BIT(12));
1119                 rtl_write_word(rtlpriv, REG_BACKDOOR_DBI_DATA, 0xf718);
1120                 rtl_write_byte(rtlpriv, REG_BACKDOOR_DBI_DATA + 2, 0x1);
1121         }
1122         tmp8 = rtl_read_byte(rtlpriv, REG_BACKDOOR_DBI_DATA + 2);
1123         count = 0;
1124         while (tmp8 && count < 20) {
1125                 udelay(10);
1126                 tmp8 = rtl_read_byte(rtlpriv, REG_BACKDOOR_DBI_DATA + 2);
1127                 count++;
1128         }
1129 }
1130
1131 void rtl92ee_enable_hw_security_config(struct ieee80211_hw *hw)
1132 {
1133         struct rtl_priv *rtlpriv = rtl_priv(hw);
1134         u8 sec_reg_value;
1135         u8 tmp;
1136
1137         RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1138                  "PairwiseEncAlgorithm = %d GroupEncAlgorithm = %d\n",
1139                   rtlpriv->sec.pairwise_enc_algorithm,
1140                   rtlpriv->sec.group_enc_algorithm);
1141
1142         if (rtlpriv->cfg->mod_params->sw_crypto || rtlpriv->sec.use_sw_sec) {
1143                 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
1144                          "not open hw encryption\n");
1145                 return;
1146         }
1147
1148         sec_reg_value = SCR_TXENCENABLE | SCR_RXDECENABLE;
1149
1150         if (rtlpriv->sec.use_defaultkey) {
1151                 sec_reg_value |= SCR_TXUSEDK;
1152                 sec_reg_value |= SCR_RXUSEDK;
1153         }
1154
1155         sec_reg_value |= (SCR_RXBCUSEDK | SCR_TXBCUSEDK);
1156
1157         tmp = rtl_read_byte(rtlpriv, REG_CR + 1);
1158         rtl_write_byte(rtlpriv, REG_CR + 1, tmp | BIT(1));
1159
1160         RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
1161                  "The SECR-value %x\n", sec_reg_value);
1162
1163         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_WPA_CONFIG, &sec_reg_value);
1164 }
1165
1166 int rtl92ee_hw_init(struct ieee80211_hw *hw)
1167 {
1168         struct rtl_priv *rtlpriv = rtl_priv(hw);
1169         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1170         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1171         struct rtl_phy *rtlphy = &rtlpriv->phy;
1172         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1173         bool rtstatus = true;
1174         int err = 0;
1175         u8 tmp_u1b, u1byte;
1176         u32 tmp_u4b;
1177
1178         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, " Rtl8192EE hw init\n");
1179         rtlpriv->rtlhal.being_init_adapter = true;
1180         rtlpriv->intf_ops->disable_aspm(hw);
1181
1182         tmp_u1b = rtl_read_byte(rtlpriv, REG_SYS_CLKR+1);
1183         u1byte = rtl_read_byte(rtlpriv, REG_CR);
1184         if ((tmp_u1b & BIT(3)) && (u1byte != 0 && u1byte != 0xEA)) {
1185                 rtlhal->mac_func_enable = true;
1186         } else {
1187                 rtlhal->mac_func_enable = false;
1188                 rtlhal->fw_ps_state = FW_PS_STATE_ALL_ON_92E;
1189         }
1190
1191         rtstatus = _rtl92ee_init_mac(hw);
1192
1193         rtl_write_byte(rtlpriv, 0x577, 0x03);
1194
1195         /*for Crystal 40 Mhz setting */
1196         rtl_write_byte(rtlpriv, REG_AFE_CTRL4, 0x2A);
1197         rtl_write_byte(rtlpriv, REG_AFE_CTRL4 + 1, 0x00);
1198         rtl_write_byte(rtlpriv, REG_AFE_CTRL2, 0x83);
1199
1200         /*Forced the antenna b to wifi */
1201         if (rtlpriv->btcoexist.btc_info.btcoexist == 1) {
1202                 rtl_write_byte(rtlpriv, 0x64, 0);
1203                 rtl_write_byte(rtlpriv, 0x65, 1);
1204         }
1205         if (!rtstatus) {
1206                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "Init MAC failed\n");
1207                 err = 1;
1208                 return err;
1209         }
1210         rtlhal->rx_tag = 0;
1211         rtl_write_word(rtlpriv, REG_PCIE_CTRL_REG, 0x8000);
1212         err = rtl92ee_download_fw(hw, false);
1213         if (err) {
1214                 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1215                          "Failed to download FW. Init HW without FW now..\n");
1216                 err = 1;
1217                 rtlhal->fw_ready = false;
1218                 return err;
1219         }
1220         rtlhal->fw_ready = true;
1221         /*fw related variable initialize */
1222         ppsc->fw_current_inpsmode = false;
1223         rtlhal->fw_ps_state = FW_PS_STATE_ALL_ON_92E;
1224         rtlhal->fw_clk_change_in_progress = false;
1225         rtlhal->allow_sw_to_change_hwclc = false;
1226         rtlhal->last_hmeboxnum = 0;
1227
1228         rtl92ee_phy_mac_config(hw);
1229
1230         rtl92ee_phy_bb_config(hw);
1231
1232         rtl92ee_phy_rf_config(hw);
1233
1234         rtlphy->rfreg_chnlval[0] = rtl_get_rfreg(hw, RF90_PATH_A,
1235                                                  RF_CHNLBW, RFREG_OFFSET_MASK);
1236         rtlphy->rfreg_chnlval[1] = rtl_get_rfreg(hw, RF90_PATH_B,
1237                                                  RF_CHNLBW, RFREG_OFFSET_MASK);
1238         rtlphy->backup_rf_0x1a = (u32)rtl_get_rfreg(hw, RF90_PATH_A, RF_RX_G1,
1239                                                     RFREG_OFFSET_MASK);
1240         rtlphy->rfreg_chnlval[0] = (rtlphy->rfreg_chnlval[0] & 0xfffff3ff) |
1241                                    BIT(10) | BIT(11);
1242
1243         rtl_set_rfreg(hw, RF90_PATH_A, RF_CHNLBW, RFREG_OFFSET_MASK,
1244                       rtlphy->rfreg_chnlval[0]);
1245         rtl_set_rfreg(hw, RF90_PATH_B, RF_CHNLBW, RFREG_OFFSET_MASK,
1246                       rtlphy->rfreg_chnlval[0]);
1247
1248         /*---- Set CCK and OFDM Block "ON"----*/
1249         rtl_set_bbreg(hw, RFPGA0_RFMOD, BCCKEN, 0x1);
1250         rtl_set_bbreg(hw, RFPGA0_RFMOD, BOFDMEN, 0x1);
1251
1252         /* Must set this,
1253          * otherwise the rx sensitivity will be very pool. Maddest
1254          */
1255         rtl_set_rfreg(hw, RF90_PATH_A, 0xB1, RFREG_OFFSET_MASK, 0x54418);
1256
1257         /*Set Hardware(MAC default setting.)*/
1258         _rtl92ee_hw_configure(hw);
1259
1260         rtlhal->mac_func_enable = true;
1261
1262         rtl_cam_reset_all_entry(hw);
1263         rtl92ee_enable_hw_security_config(hw);
1264
1265         ppsc->rfpwr_state = ERFON;
1266
1267         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_ETHER_ADDR, mac->mac_addr);
1268         _rtl92ee_enable_aspm_back_door(hw);
1269         rtlpriv->intf_ops->enable_aspm(hw);
1270
1271         rtl92ee_bt_hw_init(hw);
1272
1273         rtlpriv->rtlhal.being_init_adapter = false;
1274
1275         if (ppsc->rfpwr_state == ERFON) {
1276                 if (rtlphy->iqk_initialized) {
1277                         rtl92ee_phy_iq_calibrate(hw, true);
1278                 } else {
1279                         rtl92ee_phy_iq_calibrate(hw, false);
1280                         rtlphy->iqk_initialized = true;
1281                 }
1282         }
1283
1284         rtlphy->rfpath_rx_enable[0] = true;
1285         if (rtlphy->rf_type == RF_2T2R)
1286                 rtlphy->rfpath_rx_enable[1] = true;
1287
1288         efuse_one_byte_read(hw, 0x1FA, &tmp_u1b);
1289         if (!(tmp_u1b & BIT(0))) {
1290                 rtl_set_rfreg(hw, RF90_PATH_A, 0x15, 0x0F, 0x05);
1291                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "PA BIAS path A\n");
1292         }
1293
1294         if ((!(tmp_u1b & BIT(1))) && (rtlphy->rf_type == RF_2T2R)) {
1295                 rtl_set_rfreg(hw, RF90_PATH_B, 0x15, 0x0F, 0x05);
1296                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "PA BIAS path B\n");
1297         }
1298
1299         rtl_write_byte(rtlpriv, REG_NAV_UPPER, ((30000 + 127) / 128));
1300
1301         /*Fixed LDPC rx hang issue. */
1302         tmp_u4b = rtl_read_dword(rtlpriv, REG_SYS_SWR_CTRL1);
1303         rtl_write_byte(rtlpriv, REG_SYS_SWR_CTRL2, 0x75);
1304         tmp_u4b =  (tmp_u4b & 0xfff00fff) | (0x7E << 12);
1305         rtl_write_dword(rtlpriv, REG_SYS_SWR_CTRL1, tmp_u4b);
1306
1307         rtl92ee_dm_init(hw);
1308
1309         rtl_write_dword(rtlpriv, 0x4fc, 0);
1310
1311         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1312                  "end of Rtl8192EE hw init %x\n", err);
1313         return 0;
1314 }
1315
1316 static enum version_8192e _rtl92ee_read_chip_version(struct ieee80211_hw *hw)
1317 {
1318         struct rtl_priv *rtlpriv = rtl_priv(hw);
1319         struct rtl_phy *rtlphy = &rtlpriv->phy;
1320         enum version_8192e version = VERSION_UNKNOWN;
1321         u32 value32;
1322
1323         rtlphy->rf_type = RF_2T2R;
1324
1325         value32 = rtl_read_dword(rtlpriv, REG_SYS_CFG1);
1326         if (value32 & TRP_VAUX_EN)
1327                 version = (enum version_8192e)VERSION_TEST_CHIP_2T2R_8192E;
1328         else
1329                 version = (enum version_8192e)VERSION_NORMAL_CHIP_2T2R_8192E;
1330
1331         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1332                  "Chip RF Type: %s\n", (rtlphy->rf_type == RF_2T2R) ?
1333                   "RF_2T2R" : "RF_1T1R");
1334
1335         return version;
1336 }
1337
1338 static int _rtl92ee_set_media_status(struct ieee80211_hw *hw,
1339                                      enum nl80211_iftype type)
1340 {
1341         struct rtl_priv *rtlpriv = rtl_priv(hw);
1342         u8 bt_msr = rtl_read_byte(rtlpriv, MSR) & 0xfc;
1343         enum led_ctl_mode ledaction = LED_CTL_NO_LINK;
1344         u8 mode = MSR_NOLINK;
1345
1346         switch (type) {
1347         case NL80211_IFTYPE_UNSPECIFIED:
1348                 mode = MSR_NOLINK;
1349                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1350                          "Set Network type to NO LINK!\n");
1351                 break;
1352         case NL80211_IFTYPE_ADHOC:
1353         case NL80211_IFTYPE_MESH_POINT:
1354                 mode = MSR_ADHOC;
1355                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1356                          "Set Network type to Ad Hoc!\n");
1357                 break;
1358         case NL80211_IFTYPE_STATION:
1359                 mode = MSR_INFRA;
1360                 ledaction = LED_CTL_LINK;
1361                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1362                          "Set Network type to STA!\n");
1363                 break;
1364         case NL80211_IFTYPE_AP:
1365                 mode = MSR_AP;
1366                 ledaction = LED_CTL_LINK;
1367                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1368                          "Set Network type to AP!\n");
1369                 break;
1370         default:
1371                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1372                          "Network type %d not support!\n", type);
1373                 return 1;
1374         }
1375
1376         /* MSR_INFRA == Link in infrastructure network;
1377          * MSR_ADHOC == Link in ad hoc network;
1378          * Therefore, check link state is necessary.
1379          *
1380          * MSR_AP == AP mode; link state is not cared here.
1381          */
1382         if (mode != MSR_AP && rtlpriv->mac80211.link_state < MAC80211_LINKED) {
1383                 mode = MSR_NOLINK;
1384                 ledaction = LED_CTL_NO_LINK;
1385         }
1386
1387         if (mode == MSR_NOLINK || mode == MSR_INFRA) {
1388                 _rtl92ee_stop_tx_beacon(hw);
1389                 _rtl92ee_enable_bcn_sub_func(hw);
1390         } else if (mode == MSR_ADHOC || mode == MSR_AP) {
1391                 _rtl92ee_resume_tx_beacon(hw);
1392                 _rtl92ee_disable_bcn_sub_func(hw);
1393         } else {
1394                 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1395                          "Set HW_VAR_MEDIA_STATUS: No such media status(%x).\n",
1396                          mode);
1397         }
1398
1399         rtl_write_byte(rtlpriv, (MSR), bt_msr | mode);
1400         rtlpriv->cfg->ops->led_control(hw, ledaction);
1401         if (mode == MSR_AP)
1402                 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x00);
1403         else
1404                 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x66);
1405         return 0;
1406 }
1407
1408 void rtl92ee_set_check_bssid(struct ieee80211_hw *hw, bool check_bssid)
1409 {
1410         struct rtl_priv *rtlpriv = rtl_priv(hw);
1411         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1412         u32 reg_rcr = rtlpci->receive_config;
1413
1414         if (rtlpriv->psc.rfpwr_state != ERFON)
1415                 return;
1416
1417         if (check_bssid) {
1418                 reg_rcr |= (RCR_CBSSID_DATA | RCR_CBSSID_BCN);
1419                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR,
1420                                               (u8 *)(&reg_rcr));
1421                 _rtl92ee_set_bcn_ctrl_reg(hw, 0, BIT(4));
1422         } else {
1423                 reg_rcr &= (~(RCR_CBSSID_DATA | RCR_CBSSID_BCN));
1424                 _rtl92ee_set_bcn_ctrl_reg(hw, BIT(4), 0);
1425                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR,
1426                                               (u8 *)(&reg_rcr));
1427         }
1428 }
1429
1430 int rtl92ee_set_network_type(struct ieee80211_hw *hw, enum nl80211_iftype type)
1431 {
1432         struct rtl_priv *rtlpriv = rtl_priv(hw);
1433
1434         if (_rtl92ee_set_media_status(hw, type))
1435                 return -EOPNOTSUPP;
1436
1437         if (rtlpriv->mac80211.link_state == MAC80211_LINKED) {
1438                 if (type != NL80211_IFTYPE_AP &&
1439                     type != NL80211_IFTYPE_MESH_POINT)
1440                         rtl92ee_set_check_bssid(hw, true);
1441         } else {
1442                 rtl92ee_set_check_bssid(hw, false);
1443         }
1444
1445         return 0;
1446 }
1447
1448 /* don't set REG_EDCA_BE_PARAM here because mac80211 will send pkt when scan */
1449 void rtl92ee_set_qos(struct ieee80211_hw *hw, int aci)
1450 {
1451         struct rtl_priv *rtlpriv = rtl_priv(hw);
1452
1453         rtl92ee_dm_init_edca_turbo(hw);
1454         switch (aci) {
1455         case AC1_BK:
1456                 rtl_write_dword(rtlpriv, REG_EDCA_BK_PARAM, 0xa44f);
1457                 break;
1458         case AC0_BE:
1459                 /* rtl_write_dword(rtlpriv, REG_EDCA_BE_PARAM, u4b_ac_param); */
1460                 break;
1461         case AC2_VI:
1462                 rtl_write_dword(rtlpriv, REG_EDCA_VI_PARAM, 0x5e4322);
1463                 break;
1464         case AC3_VO:
1465                 rtl_write_dword(rtlpriv, REG_EDCA_VO_PARAM, 0x2f3222);
1466                 break;
1467         default:
1468                 RT_ASSERT(false, "invalid aci: %d !\n", aci);
1469                 break;
1470         }
1471 }
1472
1473 static void rtl92ee_clear_interrupt(struct ieee80211_hw *hw)
1474 {
1475         struct rtl_priv *rtlpriv = rtl_priv(hw);
1476         u32 tmp;
1477
1478         tmp = rtl_read_dword(rtlpriv, REG_HISR);
1479         rtl_write_dword(rtlpriv, REG_HISR, tmp);
1480
1481         tmp = rtl_read_dword(rtlpriv, REG_HISRE);
1482         rtl_write_dword(rtlpriv, REG_HISRE, tmp);
1483
1484         tmp = rtl_read_dword(rtlpriv, REG_HSISR);
1485         rtl_write_dword(rtlpriv, REG_HSISR, tmp);
1486 }
1487
1488 void rtl92ee_enable_interrupt(struct ieee80211_hw *hw)
1489 {
1490         struct rtl_priv *rtlpriv = rtl_priv(hw);
1491         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1492
1493         rtl92ee_clear_interrupt(hw);/*clear it here first*/
1494
1495         rtl_write_dword(rtlpriv, REG_HIMR, rtlpci->irq_mask[0] & 0xFFFFFFFF);
1496         rtl_write_dword(rtlpriv, REG_HIMRE, rtlpci->irq_mask[1] & 0xFFFFFFFF);
1497         rtlpci->irq_enabled = true;
1498 }
1499
1500 void rtl92ee_disable_interrupt(struct ieee80211_hw *hw)
1501 {
1502         struct rtl_priv *rtlpriv = rtl_priv(hw);
1503         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1504
1505         rtl_write_dword(rtlpriv, REG_HIMR, IMR_DISABLED);
1506         rtl_write_dword(rtlpriv, REG_HIMRE, IMR_DISABLED);
1507         rtlpci->irq_enabled = false;
1508         /*synchronize_irq(rtlpci->pdev->irq);*/
1509 }
1510
1511 static void _rtl92ee_poweroff_adapter(struct ieee80211_hw *hw)
1512 {
1513         struct rtl_priv *rtlpriv = rtl_priv(hw);
1514         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1515         u8 u1b_tmp;
1516
1517         rtlhal->mac_func_enable = false;
1518
1519         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "POWER OFF adapter\n");
1520
1521         /* Run LPS WL RFOFF flow */
1522         rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,
1523                                  PWR_INTF_PCI_MSK, RTL8192E_NIC_LPS_ENTER_FLOW);
1524         /* turn off RF */
1525         rtl_write_byte(rtlpriv, REG_RF_CTRL, 0x00);
1526
1527         /* ==== Reset digital sequence   ======  */
1528         if ((rtl_read_byte(rtlpriv, REG_MCUFWDL) & BIT(7)) && rtlhal->fw_ready)
1529                 rtl92ee_firmware_selfreset(hw);
1530
1531         /* Reset MCU  */
1532         u1b_tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1);
1533         rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, (u1b_tmp & (~BIT(2))));
1534
1535         /* reset MCU ready status */
1536         rtl_write_byte(rtlpriv, REG_MCUFWDL, 0x00);
1537
1538         /* HW card disable configuration. */
1539         rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,
1540                                  PWR_INTF_PCI_MSK, RTL8192E_NIC_DISABLE_FLOW);
1541
1542         /* Reset MCU IO Wrapper */
1543         u1b_tmp = rtl_read_byte(rtlpriv, REG_RSV_CTRL + 1);
1544         rtl_write_byte(rtlpriv, REG_RSV_CTRL + 1, (u1b_tmp & (~BIT(0))));
1545         u1b_tmp = rtl_read_byte(rtlpriv, REG_RSV_CTRL + 1);
1546         rtl_write_byte(rtlpriv, REG_RSV_CTRL + 1, (u1b_tmp | BIT(0)));
1547
1548         /* lock ISO/CLK/Power control register */
1549         rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x0E);
1550 }
1551
1552 void rtl92ee_card_disable(struct ieee80211_hw *hw)
1553 {
1554         struct rtl_priv *rtlpriv = rtl_priv(hw);
1555         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1556         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1557         enum nl80211_iftype opmode;
1558
1559         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "RTL8192ee card disable\n");
1560
1561         RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
1562
1563         mac->link_state = MAC80211_NOLINK;
1564         opmode = NL80211_IFTYPE_UNSPECIFIED;
1565
1566         _rtl92ee_set_media_status(hw, opmode);
1567
1568         if (rtlpriv->rtlhal.driver_is_goingto_unload ||
1569             ppsc->rfoff_reason > RF_CHANGE_BY_PS)
1570                 rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF);
1571
1572         _rtl92ee_poweroff_adapter(hw);
1573
1574         /* after power off we should do iqk again */
1575         rtlpriv->phy.iqk_initialized = false;
1576 }
1577
1578 void rtl92ee_interrupt_recognized(struct ieee80211_hw *hw,
1579                                   u32 *p_inta, u32 *p_intb)
1580 {
1581         struct rtl_priv *rtlpriv = rtl_priv(hw);
1582         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1583
1584         *p_inta = rtl_read_dword(rtlpriv, ISR) & rtlpci->irq_mask[0];
1585         rtl_write_dword(rtlpriv, ISR, *p_inta);
1586
1587         *p_intb = rtl_read_dword(rtlpriv, REG_HISRE) & rtlpci->irq_mask[1];
1588         rtl_write_dword(rtlpriv, REG_HISRE, *p_intb);
1589 }
1590
1591 void rtl92ee_set_beacon_related_registers(struct ieee80211_hw *hw)
1592 {
1593         struct rtl_priv *rtlpriv = rtl_priv(hw);
1594         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1595         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1596         u16 bcn_interval, atim_window;
1597
1598         bcn_interval = mac->beacon_interval;
1599         atim_window = 2;        /*FIX MERGE */
1600         rtl92ee_disable_interrupt(hw);
1601         rtl_write_word(rtlpriv, REG_ATIMWND, atim_window);
1602         rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval);
1603         rtl_write_word(rtlpriv, REG_BCNTCFG, 0x660f);
1604         rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_CCK, 0x18);
1605         rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_OFDM, 0x18);
1606         rtl_write_byte(rtlpriv, 0x606, 0x30);
1607         rtlpci->reg_bcn_ctrl_val |= BIT(3);
1608         rtl_write_byte(rtlpriv, REG_BCN_CTRL, (u8)rtlpci->reg_bcn_ctrl_val);
1609 }
1610
1611 void rtl92ee_set_beacon_interval(struct ieee80211_hw *hw)
1612 {
1613         struct rtl_priv *rtlpriv = rtl_priv(hw);
1614         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1615         u16 bcn_interval = mac->beacon_interval;
1616
1617         RT_TRACE(rtlpriv, COMP_BEACON, DBG_DMESG,
1618                  "beacon_interval:%d\n", bcn_interval);
1619         rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval);
1620 }
1621
1622 void rtl92ee_update_interrupt_mask(struct ieee80211_hw *hw,
1623                                    u32 add_msr, u32 rm_msr)
1624 {
1625         struct rtl_priv *rtlpriv = rtl_priv(hw);
1626         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1627
1628         RT_TRACE(rtlpriv, COMP_INTR, DBG_LOUD,
1629                  "add_msr:%x, rm_msr:%x\n", add_msr, rm_msr);
1630
1631         if (add_msr)
1632                 rtlpci->irq_mask[0] |= add_msr;
1633         if (rm_msr)
1634                 rtlpci->irq_mask[0] &= (~rm_msr);
1635         rtl92ee_disable_interrupt(hw);
1636         rtl92ee_enable_interrupt(hw);
1637 }
1638
1639 static u8 _rtl92ee_get_chnl_group(u8 chnl)
1640 {
1641         u8 group = 0;
1642
1643         if (chnl <= 14) {
1644                 if (1 <= chnl && chnl <= 2)
1645                         group = 0;
1646                 else if (3 <= chnl && chnl <= 5)
1647                         group = 1;
1648                 else if (6 <= chnl && chnl <= 8)
1649                         group = 2;
1650                 else if (9 <= chnl && chnl <= 11)
1651                         group = 3;
1652                 else if (12 <= chnl && chnl <= 14)
1653                         group = 4;
1654         } else {
1655                 if (36 <= chnl && chnl <= 42)
1656                         group = 0;
1657                 else if (44 <= chnl && chnl <= 48)
1658                         group = 1;
1659                 else if (50 <= chnl && chnl <= 58)
1660                         group = 2;
1661                 else if (60 <= chnl && chnl <= 64)
1662                         group = 3;
1663                 else if (100 <= chnl && chnl <= 106)
1664                         group = 4;
1665                 else if (108 <= chnl && chnl <= 114)
1666                         group = 5;
1667                 else if (116 <= chnl && chnl <= 122)
1668                         group = 6;
1669                 else if (124 <= chnl && chnl <= 130)
1670                         group = 7;
1671                 else if (132 <= chnl && chnl <= 138)
1672                         group = 8;
1673                 else if (140 <= chnl && chnl <= 144)
1674                         group = 9;
1675                 else if (149 <= chnl && chnl <= 155)
1676                         group = 10;
1677                 else if (157 <= chnl && chnl <= 161)
1678                         group = 11;
1679                 else if (165 <= chnl && chnl <= 171)
1680                         group = 12;
1681                 else if (173 <= chnl && chnl <= 177)
1682                         group = 13;
1683         }
1684         return group;
1685 }
1686
1687 static void _rtl8192ee_read_power_value_fromprom(struct ieee80211_hw *hw,
1688                                                  struct txpower_info_2g *pwr2g,
1689                                                  struct txpower_info_5g *pwr5g,
1690                                                  bool autoload_fail, u8 *hwinfo)
1691 {
1692         struct rtl_priv *rtlpriv = rtl_priv(hw);
1693         u32 rf, addr = EEPROM_TX_PWR_INX, group, i = 0;
1694
1695         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1696                  "hal_ReadPowerValueFromPROM92E(): PROMContent[0x%x]=0x%x\n",
1697                  (addr + 1), hwinfo[addr + 1]);
1698         if (0xFF == hwinfo[addr+1])  /*YJ,add,120316*/
1699                 autoload_fail = true;
1700
1701         if (autoload_fail) {
1702                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1703                          "auto load fail : Use Default value!\n");
1704                 for (rf = 0 ; rf < MAX_RF_PATH ; rf++) {
1705                         /* 2.4G default value */
1706                         for (group = 0 ; group < MAX_CHNL_GROUP_24G; group++) {
1707                                 pwr2g->index_cck_base[rf][group] = 0x2D;
1708                                 pwr2g->index_bw40_base[rf][group] = 0x2D;
1709                         }
1710                         for (i = 0; i < MAX_TX_COUNT; i++) {
1711                                 if (i == 0) {
1712                                         pwr2g->bw20_diff[rf][0] = 0x02;
1713                                         pwr2g->ofdm_diff[rf][0] = 0x04;
1714                                 } else {
1715                                         pwr2g->bw20_diff[rf][i] = 0xFE;
1716                                         pwr2g->bw40_diff[rf][i] = 0xFE;
1717                                         pwr2g->cck_diff[rf][i] = 0xFE;
1718                                         pwr2g->ofdm_diff[rf][i] = 0xFE;
1719                                 }
1720                         }
1721
1722                         /*5G default value*/
1723                         for (group = 0 ; group < MAX_CHNL_GROUP_5G; group++)
1724                                 pwr5g->index_bw40_base[rf][group] = 0x2A;
1725
1726                         for (i = 0; i < MAX_TX_COUNT; i++) {
1727                                 if (i == 0) {
1728                                         pwr5g->ofdm_diff[rf][0] = 0x04;
1729                                         pwr5g->bw20_diff[rf][0] = 0x00;
1730                                         pwr5g->bw80_diff[rf][0] = 0xFE;
1731                                         pwr5g->bw160_diff[rf][0] = 0xFE;
1732                                 } else {
1733                                         pwr5g->ofdm_diff[rf][0] = 0xFE;
1734                                         pwr5g->bw20_diff[rf][0] = 0xFE;
1735                                         pwr5g->bw40_diff[rf][0] = 0xFE;
1736                                         pwr5g->bw80_diff[rf][0] = 0xFE;
1737                                         pwr5g->bw160_diff[rf][0] = 0xFE;
1738                                 }
1739                         }
1740                 }
1741                 return;
1742         }
1743
1744         rtl_priv(hw)->efuse.txpwr_fromeprom = true;
1745
1746         for (rf = 0 ; rf < MAX_RF_PATH ; rf++) {
1747                 /*2.4G default value*/
1748                 for (group = 0 ; group < MAX_CHNL_GROUP_24G; group++) {
1749                         pwr2g->index_cck_base[rf][group] = hwinfo[addr++];
1750                         if (pwr2g->index_cck_base[rf][group] == 0xFF)
1751                                 pwr2g->index_cck_base[rf][group] = 0x2D;
1752                 }
1753                 for (group = 0 ; group < MAX_CHNL_GROUP_24G - 1; group++) {
1754                         pwr2g->index_bw40_base[rf][group] = hwinfo[addr++];
1755                         if (pwr2g->index_bw40_base[rf][group] == 0xFF)
1756                                 pwr2g->index_bw40_base[rf][group] = 0x2D;
1757                 }
1758                 for (i = 0; i < MAX_TX_COUNT; i++) {
1759                         if (i == 0) {
1760                                 pwr2g->bw40_diff[rf][i] = 0;
1761                                 if (hwinfo[addr] == 0xFF) {
1762                                         pwr2g->bw20_diff[rf][i] = 0x02;
1763                                 } else {
1764                                         pwr2g->bw20_diff[rf][i] = (hwinfo[addr]
1765                                                                    & 0xf0) >> 4;
1766                                         if (pwr2g->bw20_diff[rf][i] & BIT(3))
1767                                                 pwr2g->bw20_diff[rf][i] |= 0xF0;
1768                                 }
1769
1770                                 if (hwinfo[addr] == 0xFF) {
1771                                         pwr2g->ofdm_diff[rf][i] = 0x04;
1772                                 } else {
1773                                         pwr2g->ofdm_diff[rf][i] = (hwinfo[addr]
1774                                                                    & 0x0f);
1775                                         if (pwr2g->ofdm_diff[rf][i] & BIT(3))
1776                                                 pwr2g->ofdm_diff[rf][i] |= 0xF0;
1777                                 }
1778                                 pwr2g->cck_diff[rf][i] = 0;
1779                                 addr++;
1780                         } else {
1781                                 if (hwinfo[addr] == 0xFF) {
1782                                         pwr2g->bw40_diff[rf][i] = 0xFE;
1783                                 } else {
1784                                         pwr2g->bw40_diff[rf][i] = (hwinfo[addr]
1785                                                                    & 0xf0) >> 4;
1786                                         if (pwr2g->bw40_diff[rf][i] & BIT(3))
1787                                                 pwr2g->bw40_diff[rf][i] |= 0xF0;
1788                                 }
1789
1790                                 if (hwinfo[addr] == 0xFF) {
1791                                         pwr2g->bw20_diff[rf][i] = 0xFE;
1792                                 } else {
1793                                         pwr2g->bw20_diff[rf][i] = (hwinfo[addr]
1794                                                                    & 0x0f);
1795                                         if (pwr2g->bw20_diff[rf][i] & BIT(3))
1796                                                 pwr2g->bw20_diff[rf][i] |= 0xF0;
1797                                 }
1798                                 addr++;
1799
1800                                 if (hwinfo[addr] == 0xFF) {
1801                                         pwr2g->ofdm_diff[rf][i] = 0xFE;
1802                                 } else {
1803                                         pwr2g->ofdm_diff[rf][i] = (hwinfo[addr]
1804                                                                    & 0xf0) >> 4;
1805                                         if (pwr2g->ofdm_diff[rf][i] & BIT(3))
1806                                                 pwr2g->ofdm_diff[rf][i] |= 0xF0;
1807                                 }
1808
1809                                 if (hwinfo[addr] == 0xFF) {
1810                                         pwr2g->cck_diff[rf][i] = 0xFE;
1811                                 } else {
1812                                         pwr2g->cck_diff[rf][i] = (hwinfo[addr]
1813                                                                   & 0x0f);
1814                                         if (pwr2g->cck_diff[rf][i] & BIT(3))
1815                                                 pwr2g->cck_diff[rf][i] |= 0xF0;
1816                                 }
1817                                 addr++;
1818                         }
1819                 }
1820
1821                 /*5G default value*/
1822                 for (group = 0 ; group < MAX_CHNL_GROUP_5G; group++) {
1823                         pwr5g->index_bw40_base[rf][group] = hwinfo[addr++];
1824                         if (pwr5g->index_bw40_base[rf][group] == 0xFF)
1825                                 pwr5g->index_bw40_base[rf][group] = 0xFE;
1826                 }
1827
1828                 for (i = 0; i < MAX_TX_COUNT; i++) {
1829                         if (i == 0) {
1830                                 pwr5g->bw40_diff[rf][i] = 0;
1831
1832                                 if (hwinfo[addr] == 0xFF) {
1833                                         pwr5g->bw20_diff[rf][i] = 0;
1834                                 } else {
1835                                         pwr5g->bw20_diff[rf][0] = (hwinfo[addr]
1836                                                                    & 0xf0) >> 4;
1837                                         if (pwr5g->bw20_diff[rf][i] & BIT(3))
1838                                                 pwr5g->bw20_diff[rf][i] |= 0xF0;
1839                                 }
1840
1841                                 if (hwinfo[addr] == 0xFF) {
1842                                         pwr5g->ofdm_diff[rf][i] = 0x04;
1843                                 } else {
1844                                         pwr5g->ofdm_diff[rf][0] = (hwinfo[addr]
1845                                                                    & 0x0f);
1846                                         if (pwr5g->ofdm_diff[rf][i] & BIT(3))
1847                                                 pwr5g->ofdm_diff[rf][i] |= 0xF0;
1848                                 }
1849                                 addr++;
1850                         } else {
1851                                 if (hwinfo[addr] == 0xFF) {
1852                                         pwr5g->bw40_diff[rf][i] = 0xFE;
1853                                 } else {
1854                                         pwr5g->bw40_diff[rf][i] = (hwinfo[addr]
1855                                                                   & 0xf0) >> 4;
1856                                         if (pwr5g->bw40_diff[rf][i] & BIT(3))
1857                                                 pwr5g->bw40_diff[rf][i] |= 0xF0;
1858                                 }
1859
1860                                 if (hwinfo[addr] == 0xFF) {
1861                                         pwr5g->bw20_diff[rf][i] = 0xFE;
1862                                 } else {
1863                                         pwr5g->bw20_diff[rf][i] = (hwinfo[addr]
1864                                                                    & 0x0f);
1865                                         if (pwr5g->bw20_diff[rf][i] & BIT(3))
1866                                                 pwr5g->bw20_diff[rf][i] |= 0xF0;
1867                                 }
1868                                 addr++;
1869                         }
1870                 }
1871
1872                 if (hwinfo[addr] == 0xFF) {
1873                         pwr5g->ofdm_diff[rf][1] = 0xFE;
1874                         pwr5g->ofdm_diff[rf][2] = 0xFE;
1875                 } else {
1876                         pwr5g->ofdm_diff[rf][1] = (hwinfo[addr] & 0xf0) >> 4;
1877                         pwr5g->ofdm_diff[rf][2] = (hwinfo[addr] & 0x0f);
1878                 }
1879                 addr++;
1880
1881                 if (hwinfo[addr] == 0xFF)
1882                         pwr5g->ofdm_diff[rf][3] = 0xFE;
1883                 else
1884                         pwr5g->ofdm_diff[rf][3] = (hwinfo[addr] & 0x0f);
1885                 addr++;
1886
1887                 for (i = 1; i < MAX_TX_COUNT; i++) {
1888                         if (pwr5g->ofdm_diff[rf][i] == 0xFF)
1889                                 pwr5g->ofdm_diff[rf][i] = 0xFE;
1890                         else if (pwr5g->ofdm_diff[rf][i] & BIT(3))
1891                                 pwr5g->ofdm_diff[rf][i] |= 0xF0;
1892                 }
1893
1894                 for (i = 0; i < MAX_TX_COUNT; i++) {
1895                         if (hwinfo[addr] == 0xFF) {
1896                                 pwr5g->bw80_diff[rf][i] = 0xFE;
1897                         } else {
1898                                 pwr5g->bw80_diff[rf][i] = (hwinfo[addr] & 0xf0)
1899                                                           >> 4;
1900                                 if (pwr5g->bw80_diff[rf][i] & BIT(3))
1901                                         pwr5g->bw80_diff[rf][i] |= 0xF0;
1902                         }
1903
1904                         if (hwinfo[addr] == 0xFF) {
1905                                 pwr5g->bw160_diff[rf][i] = 0xFE;
1906                         } else {
1907                                 pwr5g->bw160_diff[rf][i] =
1908                                   (hwinfo[addr] & 0x0f);
1909                                 if (pwr5g->bw160_diff[rf][i] & BIT(3))
1910                                         pwr5g->bw160_diff[rf][i] |= 0xF0;
1911                         }
1912                         addr++;
1913                 }
1914         }
1915 }
1916
1917 static void _rtl92ee_read_txpower_info_from_hwpg(struct ieee80211_hw *hw,
1918                                                  bool autoload_fail, u8 *hwinfo)
1919 {
1920         struct rtl_priv *rtlpriv = rtl_priv(hw);
1921         struct rtl_efuse *efu = rtl_efuse(rtl_priv(hw));
1922         struct txpower_info_2g pwr2g;
1923         struct txpower_info_5g pwr5g;
1924         u8 channel5g[CHANNEL_MAX_NUMBER_5G] = {
1925                 36, 38, 40, 42, 44, 46, 48, 50, 52, 54,
1926                 56, 58, 60, 62, 64, 100, 102, 104, 106,
1927                 108, 110, 112, 114, 116, 118, 120, 122,
1928                 124, 126, 128, 130, 132, 134, 136, 138,
1929                 140, 142, 144, 149, 151, 153, 155, 157,
1930                 159, 161, 163, 165, 167, 168, 169, 171,
1931                 173, 175, 177
1932         };
1933         u8 channel5g_80m[CHANNEL_MAX_NUMBER_5G_80M] = {
1934                 42, 58, 106, 122, 138, 155, 171
1935         };
1936         u8 rf, idx;
1937         u8 i;
1938
1939         _rtl8192ee_read_power_value_fromprom(hw, &pwr2g, &pwr5g,
1940                                              autoload_fail, hwinfo);
1941
1942         for (rf = 0; rf < MAX_RF_PATH; rf++) {
1943                 for (i = 0; i < 14; i++) {
1944                         idx = _rtl92ee_get_chnl_group(i + 1);
1945
1946                         if (i == CHANNEL_MAX_NUMBER_2G - 1) {
1947                                 efu->txpwrlevel_cck[rf][i] =
1948                                                 pwr2g.index_cck_base[rf][5];
1949                                 efu->txpwrlevel_ht40_1s[rf][i] =
1950                                                 pwr2g.index_bw40_base[rf][idx];
1951                         } else {
1952                                 efu->txpwrlevel_cck[rf][i] =
1953                                                 pwr2g.index_cck_base[rf][idx];
1954                                 efu->txpwrlevel_ht40_1s[rf][i] =
1955                                                 pwr2g.index_bw40_base[rf][idx];
1956                         }
1957                 }
1958                 for (i = 0; i < CHANNEL_MAX_NUMBER_5G; i++) {
1959                         idx = _rtl92ee_get_chnl_group(channel5g[i]);
1960                         efu->txpwr_5g_bw40base[rf][i] =
1961                                         pwr5g.index_bw40_base[rf][idx];
1962                 }
1963                 for (i = 0; i < CHANNEL_MAX_NUMBER_5G_80M; i++) {
1964                         u8 upper, lower;
1965
1966                         idx = _rtl92ee_get_chnl_group(channel5g_80m[i]);
1967                         upper = pwr5g.index_bw40_base[rf][idx];
1968                         lower = pwr5g.index_bw40_base[rf][idx + 1];
1969
1970                         efu->txpwr_5g_bw80base[rf][i] = (upper + lower) / 2;
1971                 }
1972                 for (i = 0; i < MAX_TX_COUNT; i++) {
1973                         efu->txpwr_cckdiff[rf][i] = pwr2g.cck_diff[rf][i];
1974                         efu->txpwr_legacyhtdiff[rf][i] = pwr2g.ofdm_diff[rf][i];
1975                         efu->txpwr_ht20diff[rf][i] = pwr2g.bw20_diff[rf][i];
1976                         efu->txpwr_ht40diff[rf][i] = pwr2g.bw40_diff[rf][i];
1977
1978                         efu->txpwr_5g_ofdmdiff[rf][i] = pwr5g.ofdm_diff[rf][i];
1979                         efu->txpwr_5g_bw20diff[rf][i] = pwr5g.bw20_diff[rf][i];
1980                         efu->txpwr_5g_bw40diff[rf][i] = pwr5g.bw40_diff[rf][i];
1981                         efu->txpwr_5g_bw80diff[rf][i] = pwr5g.bw80_diff[rf][i];
1982                 }
1983         }
1984
1985         if (!autoload_fail)
1986                 efu->eeprom_thermalmeter = hwinfo[EEPROM_THERMAL_METER_92E];
1987         else
1988                 efu->eeprom_thermalmeter = EEPROM_DEFAULT_THERMALMETER;
1989
1990         if (efu->eeprom_thermalmeter == 0xff || autoload_fail) {
1991                 efu->apk_thermalmeterignore = true;
1992                 efu->eeprom_thermalmeter = EEPROM_DEFAULT_THERMALMETER;
1993         }
1994
1995         efu->thermalmeter[0] = efu->eeprom_thermalmeter;
1996         RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1997                 "thermalmeter = 0x%x\n", efu->eeprom_thermalmeter);
1998
1999         if (!autoload_fail) {
2000                 efu->eeprom_regulatory = hwinfo[EEPROM_RF_BOARD_OPTION_92E]
2001                                          & 0x07;
2002                 if (hwinfo[EEPROM_RF_BOARD_OPTION_92E] == 0xFF)
2003                         efu->eeprom_regulatory = 0;
2004         } else {
2005                 efu->eeprom_regulatory = 0;
2006         }
2007         RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
2008                 "eeprom_regulatory = 0x%x\n", efu->eeprom_regulatory);
2009 }
2010
2011 static void _rtl92ee_read_adapter_info(struct ieee80211_hw *hw)
2012 {
2013         struct rtl_priv *rtlpriv = rtl_priv(hw);
2014         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
2015         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
2016         u16 i, usvalue;
2017         u8 hwinfo[HWSET_MAX_SIZE];
2018         u16 eeprom_id;
2019
2020         if (rtlefuse->epromtype == EEPROM_BOOT_EFUSE) {
2021                 rtl_efuse_shadow_map_update(hw);
2022
2023                 memcpy(hwinfo, &rtlefuse->efuse_map[EFUSE_INIT_MAP][0],
2024                        HWSET_MAX_SIZE);
2025         } else if (rtlefuse->epromtype == EEPROM_93C46) {
2026                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
2027                          "RTL819X Not boot from eeprom, check it !!");
2028                 return;
2029         } else {
2030                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
2031                          "boot from neither eeprom nor efuse, check it !!");
2032                 return;
2033         }
2034
2035         RT_PRINT_DATA(rtlpriv, COMP_INIT, DBG_DMESG, "MAP\n",
2036                       hwinfo, HWSET_MAX_SIZE);
2037
2038         eeprom_id = *((u16 *)&hwinfo[0]);
2039         if (eeprom_id != RTL8192E_EEPROM_ID) {
2040                 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
2041                          "EEPROM ID(%#x) is invalid!!\n", eeprom_id);
2042                 rtlefuse->autoload_failflag = true;
2043         } else {
2044                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Autoload OK\n");
2045                 rtlefuse->autoload_failflag = false;
2046         }
2047
2048         if (rtlefuse->autoload_failflag)
2049                 return;
2050         /*VID DID SVID SDID*/
2051         rtlefuse->eeprom_vid = *(u16 *)&hwinfo[EEPROM_VID];
2052         rtlefuse->eeprom_did = *(u16 *)&hwinfo[EEPROM_DID];
2053         rtlefuse->eeprom_svid = *(u16 *)&hwinfo[EEPROM_SVID];
2054         rtlefuse->eeprom_smid = *(u16 *)&hwinfo[EEPROM_SMID];
2055         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "EEPROMId = 0x%4x\n", eeprom_id);
2056         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2057                  "EEPROM VID = 0x%4x\n", rtlefuse->eeprom_vid);
2058         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2059                  "EEPROM DID = 0x%4x\n", rtlefuse->eeprom_did);
2060         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2061                  "EEPROM SVID = 0x%4x\n", rtlefuse->eeprom_svid);
2062         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2063                  "EEPROM SMID = 0x%4x\n", rtlefuse->eeprom_smid);
2064         /*customer ID*/
2065         rtlefuse->eeprom_oemid = *(u8 *)&hwinfo[EEPROM_CUSTOMER_ID];
2066         if (rtlefuse->eeprom_oemid == 0xFF)
2067                 rtlefuse->eeprom_oemid = 0;
2068
2069         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2070                  "EEPROM Customer ID: 0x%2x\n", rtlefuse->eeprom_oemid);
2071         /*EEPROM version*/
2072         rtlefuse->eeprom_version = *(u8 *)&hwinfo[EEPROM_VERSION];
2073         /*mac address*/
2074         for (i = 0; i < 6; i += 2) {
2075                 usvalue = *(u16 *)&hwinfo[EEPROM_MAC_ADDR + i];
2076                 *((u16 *)(&rtlefuse->dev_addr[i])) = usvalue;
2077         }
2078
2079         RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
2080                  "dev_addr: %pM\n", rtlefuse->dev_addr);
2081         /*channel plan */
2082         rtlefuse->eeprom_channelplan = *(u8 *)&hwinfo[EEPROM_CHANNELPLAN];
2083         /* set channel paln to world wide 13 */
2084         rtlefuse->channel_plan = COUNTRY_CODE_WORLD_WIDE_13;
2085         /*tx power*/
2086         _rtl92ee_read_txpower_info_from_hwpg(hw, rtlefuse->autoload_failflag,
2087                                              hwinfo);
2088
2089         rtl92ee_read_bt_coexist_info_from_hwpg(hw, rtlefuse->autoload_failflag,
2090                                                hwinfo);
2091
2092         /*board type*/
2093         rtlefuse->board_type = (((*(u8 *)&hwinfo[EEPROM_RF_BOARD_OPTION_92E])
2094                                 & 0xE0) >> 5);
2095         if ((*(u8 *)&hwinfo[EEPROM_RF_BOARD_OPTION_92E]) == 0xFF)
2096                 rtlefuse->board_type = 0;
2097
2098         rtlhal->board_type = rtlefuse->board_type;
2099         /*parse xtal*/
2100         rtlefuse->crystalcap = hwinfo[EEPROM_XTAL_92E];
2101         if (hwinfo[EEPROM_XTAL_92E] == 0xFF)
2102                 rtlefuse->crystalcap = 0x20;
2103
2104         /*antenna diversity*/
2105         rtlefuse->antenna_div_type = NO_ANTDIV;
2106         rtlefuse->antenna_div_cfg = 0;
2107
2108         if (rtlhal->oem_id == RT_CID_DEFAULT) {
2109                 switch (rtlefuse->eeprom_oemid) {
2110                 case EEPROM_CID_DEFAULT:
2111                         if (rtlefuse->eeprom_did == 0x818B) {
2112                                 if ((rtlefuse->eeprom_svid == 0x10EC) &&
2113                                     (rtlefuse->eeprom_smid == 0x001B))
2114                                         rtlhal->oem_id = RT_CID_819X_LENOVO;
2115                         } else {
2116                                 rtlhal->oem_id = RT_CID_DEFAULT;
2117                         }
2118                         break;
2119                 default:
2120                         rtlhal->oem_id = RT_CID_DEFAULT;
2121                         break;
2122                 }
2123         }
2124 }
2125
2126 static void _rtl92ee_hal_customized_behavior(struct ieee80211_hw *hw)
2127 {
2128         struct rtl_priv *rtlpriv = rtl_priv(hw);
2129         struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
2130         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
2131
2132         pcipriv->ledctl.led_opendrain = true;
2133
2134         RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
2135                  "RT Customized ID: 0x%02X\n", rtlhal->oem_id);
2136 }
2137
2138 void rtl92ee_read_eeprom_info(struct ieee80211_hw *hw)
2139 {
2140         struct rtl_priv *rtlpriv = rtl_priv(hw);
2141         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
2142         struct rtl_phy *rtlphy = &rtlpriv->phy;
2143         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
2144         u8 tmp_u1b;
2145
2146         rtlhal->version = _rtl92ee_read_chip_version(hw);
2147         if (get_rf_type(rtlphy) == RF_1T1R) {
2148                 rtlpriv->dm.rfpath_rxenable[0] = true;
2149         } else {
2150                 rtlpriv->dm.rfpath_rxenable[0] = true;
2151                 rtlpriv->dm.rfpath_rxenable[1] = true;
2152         }
2153         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "VersionID = 0x%4x\n",
2154                  rtlhal->version);
2155         tmp_u1b = rtl_read_byte(rtlpriv, REG_9346CR);
2156         if (tmp_u1b & BIT(4)) {
2157                 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EEPROM\n");
2158                 rtlefuse->epromtype = EEPROM_93C46;
2159         } else {
2160                 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EFUSE\n");
2161                 rtlefuse->epromtype = EEPROM_BOOT_EFUSE;
2162         }
2163         if (tmp_u1b & BIT(5)) {
2164                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Autoload OK\n");
2165                 rtlefuse->autoload_failflag = false;
2166                 _rtl92ee_read_adapter_info(hw);
2167         } else {
2168                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "Autoload ERR!!\n");
2169         }
2170         _rtl92ee_hal_customized_behavior(hw);
2171
2172         rtlphy->rfpath_rx_enable[0] = true;
2173         if (rtlphy->rf_type == RF_2T2R)
2174                 rtlphy->rfpath_rx_enable[1] = true;
2175 }
2176
2177 static u8 _rtl92ee_mrate_idx_to_arfr_id(struct ieee80211_hw *hw, u8 rate_index)
2178 {
2179         u8 ret = 0;
2180
2181         switch (rate_index) {
2182         case RATR_INX_WIRELESS_NGB:
2183                 ret = 0;
2184                 break;
2185         case RATR_INX_WIRELESS_N:
2186         case RATR_INX_WIRELESS_NG:
2187                 ret = 4;
2188                 break;
2189         case RATR_INX_WIRELESS_NB:
2190                 ret = 2;
2191                 break;
2192         case RATR_INX_WIRELESS_GB:
2193                 ret = 6;
2194                 break;
2195         case RATR_INX_WIRELESS_G:
2196                 ret = 7;
2197                 break;
2198         case RATR_INX_WIRELESS_B:
2199                 ret = 8;
2200                 break;
2201         default:
2202                 ret = 0;
2203                 break;
2204         }
2205         return ret;
2206 }
2207
2208 static void rtl92ee_update_hal_rate_mask(struct ieee80211_hw *hw,
2209                                          struct ieee80211_sta *sta,
2210                                          u8 rssi_level)
2211 {
2212         struct rtl_priv *rtlpriv = rtl_priv(hw);
2213         struct rtl_phy *rtlphy = &rtlpriv->phy;
2214         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2215         struct rtl_sta_info *sta_entry = NULL;
2216         u32 ratr_bitmap;
2217         u8 ratr_index;
2218         u8 curtxbw_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SUP_WIDTH_20_40)
2219                              ? 1 : 0;
2220         u8 b_curshortgi_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ?
2221                                 1 : 0;
2222         u8 b_curshortgi_20mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ?
2223                                 1 : 0;
2224         enum wireless_mode wirelessmode = 0;
2225         bool b_shortgi = false;
2226         u8 rate_mask[7] = {0};
2227         u8 macid = 0;
2228         /*u8 mimo_ps = IEEE80211_SMPS_OFF;*/
2229         sta_entry = (struct rtl_sta_info *)sta->drv_priv;
2230         wirelessmode = sta_entry->wireless_mode;
2231         if (mac->opmode == NL80211_IFTYPE_STATION ||
2232             mac->opmode == NL80211_IFTYPE_MESH_POINT)
2233                 curtxbw_40mhz = mac->bw_40;
2234         else if (mac->opmode == NL80211_IFTYPE_AP ||
2235                  mac->opmode == NL80211_IFTYPE_ADHOC)
2236                 macid = sta->aid + 1;
2237
2238         ratr_bitmap = sta->supp_rates[0];
2239         if (mac->opmode == NL80211_IFTYPE_ADHOC)
2240                 ratr_bitmap = 0xfff;
2241
2242         ratr_bitmap |= (sta->ht_cap.mcs.rx_mask[1] << 20 |
2243                         sta->ht_cap.mcs.rx_mask[0] << 12);
2244
2245         switch (wirelessmode) {
2246         case WIRELESS_MODE_B:
2247                 ratr_index = RATR_INX_WIRELESS_B;
2248                 if (ratr_bitmap & 0x0000000c)
2249                         ratr_bitmap &= 0x0000000d;
2250                 else
2251                         ratr_bitmap &= 0x0000000f;
2252                 break;
2253         case WIRELESS_MODE_G:
2254                 ratr_index = RATR_INX_WIRELESS_GB;
2255
2256                 if (rssi_level == 1)
2257                         ratr_bitmap &= 0x00000f00;
2258                 else if (rssi_level == 2)
2259                         ratr_bitmap &= 0x00000ff0;
2260                 else
2261                         ratr_bitmap &= 0x00000ff5;
2262                 break;
2263         case WIRELESS_MODE_N_24G:
2264                 if (curtxbw_40mhz)
2265                         ratr_index = RATR_INX_WIRELESS_NGB;
2266                 else
2267                         ratr_index = RATR_INX_WIRELESS_NB;
2268
2269                 if (rtlphy->rf_type == RF_1T1R) {
2270                         if (curtxbw_40mhz) {
2271                                 if (rssi_level == 1)
2272                                         ratr_bitmap &= 0x000f0000;
2273                                 else if (rssi_level == 2)
2274                                         ratr_bitmap &= 0x000ff000;
2275                                 else
2276                                         ratr_bitmap &= 0x000ff015;
2277                         } else {
2278                                 if (rssi_level == 1)
2279                                         ratr_bitmap &= 0x000f0000;
2280                                 else if (rssi_level == 2)
2281                                         ratr_bitmap &= 0x000ff000;
2282                                 else
2283                                         ratr_bitmap &= 0x000ff005;
2284                         }
2285                 } else {
2286                         if (curtxbw_40mhz) {
2287                                 if (rssi_level == 1)
2288                                         ratr_bitmap &= 0x0f8f0000;
2289                                 else if (rssi_level == 2)
2290                                         ratr_bitmap &= 0x0ffff000;
2291                                 else
2292                                         ratr_bitmap &= 0x0ffff015;
2293                         } else {
2294                                 if (rssi_level == 1)
2295                                         ratr_bitmap &= 0x0f8f0000;
2296                                 else if (rssi_level == 2)
2297                                         ratr_bitmap &= 0x0ffff000;
2298                                 else
2299                                         ratr_bitmap &= 0x0ffff005;
2300                         }
2301                 }
2302
2303                 if ((curtxbw_40mhz && b_curshortgi_40mhz) ||
2304                     (!curtxbw_40mhz && b_curshortgi_20mhz)) {
2305                         if (macid == 0)
2306                                 b_shortgi = true;
2307                         else if (macid == 1)
2308                                 b_shortgi = false;
2309                 }
2310                 break;
2311         default:
2312                 ratr_index = RATR_INX_WIRELESS_NGB;
2313
2314                 if (rtlphy->rf_type == RF_1T1R)
2315                         ratr_bitmap &= 0x000ff0ff;
2316                 else
2317                         ratr_bitmap &= 0x0f8ff0ff;
2318                 break;
2319         }
2320         ratr_index = _rtl92ee_mrate_idx_to_arfr_id(hw, ratr_index);
2321         sta_entry->ratr_index = ratr_index;
2322
2323         RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG,
2324                  "ratr_bitmap :%x\n", ratr_bitmap);
2325         *(u32 *)&rate_mask = (ratr_bitmap & 0x0fffffff) |
2326                                        (ratr_index << 28);
2327         rate_mask[0] = macid;
2328         rate_mask[1] = ratr_index | (b_shortgi ? 0x80 : 0x00);
2329         rate_mask[2] = curtxbw_40mhz;
2330         rate_mask[3] = (u8)(ratr_bitmap & 0x000000ff);
2331         rate_mask[4] = (u8)((ratr_bitmap & 0x0000ff00) >> 8);
2332         rate_mask[5] = (u8)((ratr_bitmap & 0x00ff0000) >> 16);
2333         rate_mask[6] = (u8)((ratr_bitmap & 0xff000000) >> 24);
2334         RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG,
2335                  "Rate_index:%x, ratr_val:%x, %x:%x:%x:%x:%x:%x:%x\n",
2336                   ratr_index, ratr_bitmap, rate_mask[0], rate_mask[1],
2337                   rate_mask[2], rate_mask[3], rate_mask[4],
2338                   rate_mask[5], rate_mask[6]);
2339         rtl92ee_fill_h2c_cmd(hw, H2C_92E_RA_MASK, 7, rate_mask);
2340         _rtl92ee_set_bcn_ctrl_reg(hw, BIT(3), 0);
2341 }
2342
2343 void rtl92ee_update_hal_rate_tbl(struct ieee80211_hw *hw,
2344                                  struct ieee80211_sta *sta, u8 rssi_level)
2345 {
2346         struct rtl_priv *rtlpriv = rtl_priv(hw);
2347
2348         if (rtlpriv->dm.useramask)
2349                 rtl92ee_update_hal_rate_mask(hw, sta, rssi_level);
2350 }
2351
2352 void rtl92ee_update_channel_access_setting(struct ieee80211_hw *hw)
2353 {
2354         struct rtl_priv *rtlpriv = rtl_priv(hw);
2355         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2356         u16 sifs_timer;
2357
2358         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SLOT_TIME,
2359                                       (u8 *)&mac->slot_time);
2360         if (!mac->ht_enable)
2361                 sifs_timer = 0x0a0a;
2362         else
2363                 sifs_timer = 0x0e0e;
2364         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SIFS, (u8 *)&sifs_timer);
2365 }
2366
2367 bool rtl92ee_gpio_radio_on_off_checking(struct ieee80211_hw *hw, u8 *valid)
2368 {
2369         *valid = 1;
2370         return true;
2371 }
2372
2373 void rtl92ee_set_key(struct ieee80211_hw *hw, u32 key_index,
2374                      u8 *p_macaddr, bool is_group, u8 enc_algo,
2375                      bool is_wepkey, bool clear_all)
2376 {
2377         struct rtl_priv *rtlpriv = rtl_priv(hw);
2378         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2379         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
2380         u8 *macaddr = p_macaddr;
2381         u32 entry_id = 0;
2382         bool is_pairwise = false;
2383
2384         static u8 cam_const_addr[4][6] = {
2385                 {0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
2386                 {0x00, 0x00, 0x00, 0x00, 0x00, 0x01},
2387                 {0x00, 0x00, 0x00, 0x00, 0x00, 0x02},
2388                 {0x00, 0x00, 0x00, 0x00, 0x00, 0x03}
2389         };
2390         static u8 cam_const_broad[] = {
2391                 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
2392         };
2393
2394         if (clear_all) {
2395                 u8 idx = 0;
2396                 u8 cam_offset = 0;
2397                 u8 clear_number = 5;
2398
2399                 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, "clear_all\n");
2400
2401                 for (idx = 0; idx < clear_number; idx++) {
2402                         rtl_cam_mark_invalid(hw, cam_offset + idx);
2403                         rtl_cam_empty_entry(hw, cam_offset + idx);
2404
2405                         if (idx < 5) {
2406                                 memset(rtlpriv->sec.key_buf[idx], 0,
2407                                        MAX_KEY_LEN);
2408                                 rtlpriv->sec.key_len[idx] = 0;
2409                         }
2410                 }
2411
2412         } else {
2413                 switch (enc_algo) {
2414                 case WEP40_ENCRYPTION:
2415                         enc_algo = CAM_WEP40;
2416                         break;
2417                 case WEP104_ENCRYPTION:
2418                         enc_algo = CAM_WEP104;
2419                         break;
2420                 case TKIP_ENCRYPTION:
2421                         enc_algo = CAM_TKIP;
2422                         break;
2423                 case AESCCMP_ENCRYPTION:
2424                         enc_algo = CAM_AES;
2425                         break;
2426                 default:
2427                         RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
2428                                  "switch case not process\n");
2429                         enc_algo = CAM_TKIP;
2430                         break;
2431                 }
2432
2433                 if (is_wepkey || rtlpriv->sec.use_defaultkey) {
2434                         macaddr = cam_const_addr[key_index];
2435                         entry_id = key_index;
2436                 } else {
2437                         if (is_group) {
2438                                 macaddr = cam_const_broad;
2439                                 entry_id = key_index;
2440                         } else {
2441                                 if (mac->opmode == NL80211_IFTYPE_AP ||
2442                                     mac->opmode == NL80211_IFTYPE_MESH_POINT) {
2443                                         entry_id = rtl_cam_get_free_entry(hw,
2444                                                                      p_macaddr);
2445                                         if (entry_id >=  TOTAL_CAM_ENTRY) {
2446                                                 RT_TRACE(rtlpriv, COMP_SEC,
2447                                                          DBG_EMERG,
2448                                                          "Can not find free hw security cam entry\n");
2449                                                 return;
2450                                         }
2451                                 } else {
2452                                         entry_id = CAM_PAIRWISE_KEY_POSITION;
2453                                 }
2454
2455                                 key_index = PAIRWISE_KEYIDX;
2456                                 is_pairwise = true;
2457                         }
2458                 }
2459
2460                 if (rtlpriv->sec.key_len[key_index] == 0) {
2461                         RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2462                                  "delete one entry, entry_id is %d\n",
2463                                  entry_id);
2464                         if (mac->opmode == NL80211_IFTYPE_AP ||
2465                             mac->opmode == NL80211_IFTYPE_MESH_POINT)
2466                                 rtl_cam_del_entry(hw, p_macaddr);
2467                         rtl_cam_delete_one_entry(hw, p_macaddr, entry_id);
2468                 } else {
2469                         RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2470                                  "add one entry\n");
2471                         if (is_pairwise) {
2472                                 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2473                                          "set Pairwiase key\n");
2474
2475                                 rtl_cam_add_one_entry(hw, macaddr, key_index,
2476                                                entry_id, enc_algo,
2477                                                CAM_CONFIG_NO_USEDK,
2478                                                rtlpriv->sec.key_buf[key_index]);
2479                         } else {
2480                                 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2481                                          "set group key\n");
2482
2483                                 if (mac->opmode == NL80211_IFTYPE_ADHOC) {
2484                                         rtl_cam_add_one_entry(hw,
2485                                                 rtlefuse->dev_addr,
2486                                                 PAIRWISE_KEYIDX,
2487                                                 CAM_PAIRWISE_KEY_POSITION,
2488                                                 enc_algo, CAM_CONFIG_NO_USEDK,
2489                                                 rtlpriv->sec.key_buf[entry_id]);
2490                                 }
2491
2492                                 rtl_cam_add_one_entry(hw, macaddr, key_index,
2493                                                 entry_id, enc_algo,
2494                                                 CAM_CONFIG_NO_USEDK,
2495                                                 rtlpriv->sec.key_buf[entry_id]);
2496                         }
2497                 }
2498         }
2499 }
2500
2501 void rtl92ee_read_bt_coexist_info_from_hwpg(struct ieee80211_hw *hw,
2502                                             bool auto_load_fail, u8 *hwinfo)
2503 {
2504         struct rtl_priv *rtlpriv = rtl_priv(hw);
2505         u8 value;
2506
2507         if (!auto_load_fail) {
2508                 value = hwinfo[EEPROM_RF_BOARD_OPTION_92E];
2509                 if (((value & 0xe0) >> 5) == 0x1)
2510                         rtlpriv->btcoexist.btc_info.btcoexist = 1;
2511                 else
2512                         rtlpriv->btcoexist.btc_info.btcoexist = 0;
2513
2514                 rtlpriv->btcoexist.btc_info.bt_type = BT_RTL8192E;
2515                 rtlpriv->btcoexist.btc_info.ant_num = ANT_TOTAL_X2;
2516         } else {
2517                 rtlpriv->btcoexist.btc_info.btcoexist = 1;
2518                 rtlpriv->btcoexist.btc_info.bt_type = BT_RTL8192E;
2519                 rtlpriv->btcoexist.btc_info.ant_num = ANT_TOTAL_X1;
2520         }
2521 }
2522
2523 void rtl92ee_bt_reg_init(struct ieee80211_hw *hw)
2524 {
2525         struct rtl_priv *rtlpriv = rtl_priv(hw);
2526
2527         /* 0:Low, 1:High, 2:From Efuse. */
2528         rtlpriv->btcoexist.reg_bt_iso = 2;
2529         /* 0:Idle, 1:None-SCO, 2:SCO, 3:From Counter. */
2530         rtlpriv->btcoexist.reg_bt_sco = 3;
2531         /* 0:Disable BT control A-MPDU, 1:Enable BT control A-MPDU. */
2532         rtlpriv->btcoexist.reg_bt_sco = 0;
2533 }
2534
2535 void rtl92ee_bt_hw_init(struct ieee80211_hw *hw)
2536 {
2537         struct rtl_priv *rtlpriv = rtl_priv(hw);
2538
2539         if (rtlpriv->cfg->ops->get_btc_status())
2540                 rtlpriv->btcoexist.btc_ops->btc_init_hw_config(rtlpriv);
2541 }
2542
2543 void rtl92ee_suspend(struct ieee80211_hw *hw)
2544 {
2545 }
2546
2547 void rtl92ee_resume(struct ieee80211_hw *hw)
2548 {
2549 }
2550
2551 /* Turn on AAP (RCR:bit 0) for promicuous mode. */
2552 void rtl92ee_allow_all_destaddr(struct ieee80211_hw *hw,
2553                                 bool allow_all_da, bool write_into_reg)
2554 {
2555         struct rtl_priv *rtlpriv = rtl_priv(hw);
2556         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
2557
2558         if (allow_all_da)       /* Set BIT0 */
2559                 rtlpci->receive_config |= RCR_AAP;
2560         else                    /* Clear BIT0 */
2561                 rtlpci->receive_config &= ~RCR_AAP;
2562
2563         if (write_into_reg)
2564                 rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config);
2565
2566         RT_TRACE(rtlpriv, COMP_TURBO | COMP_INIT, DBG_LOUD,
2567                  "receive_config=0x%08X, write_into_reg=%d\n",
2568                   rtlpci->receive_config, write_into_reg);
2569 }