drivers/net/wireless/rtlwifi/rtl8192ee/trx.c

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2009-2014  Realtek Corporation.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * The full GNU General Public License is included in this distribution in the
  15  * file called LICENSE.
  16  *
  17  * Contact Information:
  18  * wlanfae <wlanfae@realtek.com>
  19  * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
  20  * Hsinchu 300, Taiwan.
  21  *
  22  * Larry Finger <Larry.Finger@lwfinger.net>
  23  *
  24  *****************************************************************************/
  25
  26 #include "../wifi.h"
  27 #include "../pci.h"
  28 #include "../base.h"
  29 #include "../stats.h"
  30 #include "reg.h"
  31 #include "def.h"
  32 #include "phy.h"
  33 #include "trx.h"
  34 #include "led.h"
  35 #include "dm.h"
  36 #include "fw.h"
  37
  38 static u8 _rtl92ee_map_hwqueue_to_fwqueue(struct sk_buff *skb, u8 hw_queue)
  39 {
  40         __le16 fc = rtl_get_fc(skb);
  41
  42         if (unlikely(ieee80211_is_beacon(fc)))
  43                 return QSLT_BEACON;
  44         if (ieee80211_is_mgmt(fc) || ieee80211_is_ctl(fc))
  45                 return QSLT_MGNT;
  46
  47         return skb->priority;
  48 }
  49
  50 static void _rtl92ee_query_rxphystatus(struct ieee80211_hw *hw,
  51                                        struct rtl_stats *pstatus, u8 *pdesc,
  52                                        struct rx_fwinfo *p_drvinfo,
  53                                        bool bpacket_match_bssid,
  54                                        bool bpacket_toself,
  55                                        bool packet_beacon)
  56 {
  57         struct rtl_priv *rtlpriv = rtl_priv(hw);
  58         struct phy_status_rpt *p_phystrpt = (struct phy_status_rpt *)p_drvinfo;
  59         char rx_pwr_all = 0, rx_pwr[4];
  60         u8 rf_rx_num = 0, evm, pwdb_all;
  61         u8 i, max_spatial_stream;
  62         u32 rssi, total_rssi = 0;
  63         bool is_cck = pstatus->is_cck;
  64         u8 lan_idx, vga_idx;
  65
  66         /* Record it for next packet processing */
  67         pstatus->packet_matchbssid = bpacket_match_bssid;
  68         pstatus->packet_toself = bpacket_toself;
  69         pstatus->packet_beacon = packet_beacon;
  70         pstatus->rx_mimo_signalquality[0] = -1;
  71         pstatus->rx_mimo_signalquality[1] = -1;
  72
  73         if (is_cck) {
  74                 u8 cck_highpwr;
  75                 u8 cck_agc_rpt;
  76                 /* CCK Driver info Structure is not the same as OFDM packet. */
  77                 cck_agc_rpt = p_phystrpt->cck_agc_rpt_ofdm_cfosho_a;
  78
  79                 /* (1)Hardware does not provide RSSI for CCK
  80                  * (2)PWDB, Average PWDB cacluated by
  81                  * hardware (for rate adaptive)
  82                  */
  83                 cck_highpwr = (u8)rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2,
  84                                                  BIT(9));
  85
  86                 lan_idx = ((cck_agc_rpt & 0xE0) >> 5);
  87                 vga_idx = (cck_agc_rpt & 0x1f);
  88                 switch (lan_idx) {
  89                 case 7: /*VGA_idx = 27~2*/
  90                                 if (vga_idx <= 27)
  91                                         rx_pwr_all = -100 + 2 * (27 - vga_idx);
  92                                 else
  93                                         rx_pwr_all = -100;
  94                                 break;
  95                 case 6: /*VGA_idx = 2~0*/
  96                                 rx_pwr_all = -48 + 2 * (2 - vga_idx);
  97                                 break;
  98                 case 5: /*VGA_idx = 7~5*/
  99                                 rx_pwr_all = -42 + 2 * (7 - vga_idx);
 100                                 break;
 101                 case 4: /*VGA_idx = 7~4*/
 102                                 rx_pwr_all = -36 + 2 * (7 - vga_idx);
 103                                 break;
 104                 case 3: /*VGA_idx = 7~0*/
 105                                 rx_pwr_all = -24 + 2 * (7 - vga_idx);
 106                                 break;
 107                 case 2: /*VGA_idx = 5~0*/
 108                                 if (cck_highpwr)
 109                                         rx_pwr_all = -12 + 2 * (5 - vga_idx);
 110                                 else
 111                                         rx_pwr_all = -6 + 2 * (5 - vga_idx);
 112                                 break;
 113                 case 1:
 114                                 rx_pwr_all = 8 - 2 * vga_idx;
 115                                 break;
 116                 case 0:
 117                                 rx_pwr_all = 14 - 2 * vga_idx;
 118                                 break;
 119                 default:
 120                                 break;
 121                 }
 122                 rx_pwr_all += 16;
 123                 pwdb_all = rtl_query_rxpwrpercentage(rx_pwr_all);
 124
 125                 if (!cck_highpwr) {
 126                         if (pwdb_all >= 80)
 127                                 pwdb_all = ((pwdb_all - 80) << 1) +
 128                                            ((pwdb_all - 80) >> 1) + 80;
 129                         else if ((pwdb_all <= 78) && (pwdb_all >= 20))
 130                                 pwdb_all += 3;
 131                         if (pwdb_all > 100)
 132                                 pwdb_all = 100;
 133                 }
 134
 135                 pstatus->rx_pwdb_all = pwdb_all;
 136                 pstatus->bt_rx_rssi_percentage = pwdb_all;
 137                 pstatus->recvsignalpower = rx_pwr_all;
 138
 139                 /* (3) Get Signal Quality (EVM) */
 140                 if (bpacket_match_bssid) {
 141                         u8 sq, sq_rpt;
 142
 143                         if (pstatus->rx_pwdb_all > 40) {
 144                                 sq = 100;
 145                         } else {
 146                                 sq_rpt = p_phystrpt->cck_sig_qual_ofdm_pwdb_all;
 147                                 if (sq_rpt > 64)
 148                                         sq = 0;
 149                                 else if (sq_rpt < 20)
 150                                         sq = 100;
 151                                 else
 152                                         sq = ((64 - sq_rpt) * 100) / 44;
 153                         }
 154
 155                         pstatus->signalquality = sq;
 156                         pstatus->rx_mimo_signalquality[0] = sq;
 157                         pstatus->rx_mimo_signalquality[1] = -1;
 158                 }
 159         } else {
 160                 /* (1)Get RSSI for HT rate */
 161                 for (i = RF90_PATH_A; i < RF6052_MAX_PATH; i++) {
 162                         /* we will judge RF RX path now. */
 163                         if (rtlpriv->dm.rfpath_rxenable[i])
 164                                 rf_rx_num++;
 165
 166                         rx_pwr[i] = ((p_phystrpt->path_agc[i].gain & 0x3f) * 2)
 167                                     - 110;
 168
 169                         pstatus->rx_pwr[i] = rx_pwr[i];
 170                         /* Translate DBM to percentage. */
 171                         rssi = rtl_query_rxpwrpercentage(rx_pwr[i]);
 172                         total_rssi += rssi;
 173
 174                         pstatus->rx_mimo_signalstrength[i] = (u8)rssi;
 175                 }
 176
 177                 /* (2)PWDB, Average PWDB cacluated by
 178                  * hardware (for rate adaptive)
 179                  */
 180                 rx_pwr_all = ((p_phystrpt->cck_sig_qual_ofdm_pwdb_all >> 1)
 181                               & 0x7f) - 110;
 182
 183                 pwdb_all = rtl_query_rxpwrpercentage(rx_pwr_all);
 184                 pstatus->rx_pwdb_all = pwdb_all;
 185                 pstatus->bt_rx_rssi_percentage = pwdb_all;
 186                 pstatus->rxpower = rx_pwr_all;
 187                 pstatus->recvsignalpower = rx_pwr_all;
 188
 189                 /* (3)EVM of HT rate */
 190                 if (pstatus->rate >= DESC_RATEMCS8 &&
 191                     pstatus->rate <= DESC_RATEMCS15)
 192                         max_spatial_stream = 2;
 193                 else
 194                         max_spatial_stream = 1;
 195
 196                 for (i = 0; i < max_spatial_stream; i++) {
 197                         evm = rtl_evm_db_to_percentage(
 198                                                 p_phystrpt->stream_rxevm[i]);
 199
 200                         if (bpacket_match_bssid) {
 201                                 /* Fill value in RFD, Get the first
 202                                  * spatial stream only
 203                                  */
 204                                 if (i == 0)
 205                                         pstatus->signalquality = (u8)(evm &
 206                                                                        0xff);
 207                                 pstatus->rx_mimo_signalquality[i] = (u8)(evm &
 208                                                                           0xff);
 209                         }
 210                 }
 211
 212                 if (bpacket_match_bssid) {
 213                         for (i = RF90_PATH_A; i <= RF90_PATH_B; i++)
 214                                 rtl_priv(hw)->dm.cfo_tail[i] =
 215                                         (int)p_phystrpt->path_cfotail[i];
 216
 217                         if (rtl_priv(hw)->dm.packet_count == 0xffffffff)
 218                                 rtl_priv(hw)->dm.packet_count = 0;
 219                         else
 220                                 rtl_priv(hw)->dm.packet_count++;
 221                 }
 222         }
 223
 224         /* UI BSS List signal strength(in percentage),
 225          * make it good looking, from 0~100.
 226          */
 227         if (is_cck)
 228                 pstatus->signalstrength = (u8)(rtl_signal_scale_mapping(hw,
 229                                                                      pwdb_all));
 230         else if (rf_rx_num != 0)
 231                 pstatus->signalstrength = (u8)(rtl_signal_scale_mapping(hw,
 232                                                       total_rssi /= rf_rx_num));
 233 }
 234
 235 static void _rtl92ee_translate_rx_signal_stuff(struct ieee80211_hw *hw,
 236                                                struct sk_buff *skb,
 237                                                struct rtl_stats *pstatus,
 238                                                u8 *pdesc,
 239                                                struct rx_fwinfo *p_drvinfo)
 240 {
 241         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
 242         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
 243         struct ieee80211_hdr *hdr;
 244         u8 *tmp_buf;
 245         u8 *praddr;
 246         u8 *psaddr;
 247         __le16 fc;
 248         bool packet_matchbssid, packet_toself, packet_beacon;
 249
 250         tmp_buf = skb->data + pstatus->rx_drvinfo_size +
 251                   pstatus->rx_bufshift + 24;
 252
 253         hdr = (struct ieee80211_hdr *)tmp_buf;
 254         fc = hdr->frame_control;
 255         praddr = hdr->addr1;
 256         psaddr = ieee80211_get_SA(hdr);
 257         ether_addr_copy(pstatus->psaddr, psaddr);
 258
 259         packet_matchbssid = (!ieee80211_is_ctl(fc) &&
 260                                (ether_addr_equal(mac->bssid,
 261                                                 ieee80211_has_tods(fc) ?
 262                                                 hdr->addr1 :
 263                                                 ieee80211_has_fromds(fc) ?
 264                                                 hdr->addr2 : hdr->addr3)) &&
 265                                 (!pstatus->hwerror) && (!pstatus->crc) &&
 266                                 (!pstatus->icv));
 267
 268         packet_toself = packet_matchbssid &&
 269                          (ether_addr_equal(praddr, rtlefuse->dev_addr));
 270
 271         if (ieee80211_is_beacon(fc))
 272                 packet_beacon = true;
 273         else
 274                 packet_beacon = false;
 275
 276         if (packet_beacon && packet_matchbssid)
 277                 rtl_priv(hw)->dm.dbginfo.num_qry_beacon_pkt++;
 278
 279         if (packet_matchbssid && ieee80211_is_data_qos(hdr->frame_control) &&
 280             !is_multicast_ether_addr(ieee80211_get_DA(hdr))) {
 281                 struct ieee80211_qos_hdr *hdr_qos =
 282                                             (struct ieee80211_qos_hdr *)tmp_buf;
 283                 u16 tid = le16_to_cpu(hdr_qos->qos_ctrl) & 0xf;
 284
 285                 if (tid != 0 && tid != 3)
 286                         rtl_priv(hw)->dm.dbginfo.num_non_be_pkt++;
 287         }
 288
 289         _rtl92ee_query_rxphystatus(hw, pstatus, pdesc, p_drvinfo,
 290                                    packet_matchbssid, packet_toself,
 291                                    packet_beacon);
 292         rtl_process_phyinfo(hw, tmp_buf, pstatus);
 293 }
 294
 295 static void _rtl92ee_insert_emcontent(struct rtl_tcb_desc *ptcb_desc,
 296                                       u8 *virtualaddress)
 297 {
 298         u32 dwtmp = 0;
 299
 300         memset(virtualaddress, 0, 8);
 301
 302         SET_EARLYMODE_PKTNUM(virtualaddress, ptcb_desc->empkt_num);
 303         if (ptcb_desc->empkt_num == 1) {
 304                 dwtmp = ptcb_desc->empkt_len[0];
 305         } else {
 306                 dwtmp = ptcb_desc->empkt_len[0];
 307                 dwtmp += ((dwtmp % 4) ? (4 - dwtmp % 4) : 0) + 4;
 308                 dwtmp += ptcb_desc->empkt_len[1];
 309         }
 310         SET_EARLYMODE_LEN0(virtualaddress, dwtmp);
 311
 312         if (ptcb_desc->empkt_num <= 3) {
 313                 dwtmp = ptcb_desc->empkt_len[2];
 314         } else {
 315                 dwtmp = ptcb_desc->empkt_len[2];
 316                 dwtmp += ((dwtmp % 4) ? (4 - dwtmp % 4) : 0) + 4;
 317                 dwtmp += ptcb_desc->empkt_len[3];
 318         }
 319         SET_EARLYMODE_LEN1(virtualaddress, dwtmp);
 320         if (ptcb_desc->empkt_num <= 5) {
 321                 dwtmp = ptcb_desc->empkt_len[4];
 322         } else {
 323                 dwtmp = ptcb_desc->empkt_len[4];
 324                 dwtmp += ((dwtmp % 4) ? (4 - dwtmp % 4) : 0) + 4;
 325                 dwtmp += ptcb_desc->empkt_len[5];
 326         }
 327         SET_EARLYMODE_LEN2_1(virtualaddress, dwtmp & 0xF);
 328         SET_EARLYMODE_LEN2_2(virtualaddress, dwtmp >> 4);
 329         if (ptcb_desc->empkt_num <= 7) {
 330                 dwtmp = ptcb_desc->empkt_len[6];
 331         } else {
 332                 dwtmp = ptcb_desc->empkt_len[6];
 333                 dwtmp += ((dwtmp % 4) ? (4 - dwtmp % 4) : 0) + 4;
 334                 dwtmp += ptcb_desc->empkt_len[7];
 335         }
 336         SET_EARLYMODE_LEN3(virtualaddress, dwtmp);
 337         if (ptcb_desc->empkt_num <= 9) {
 338                 dwtmp = ptcb_desc->empkt_len[8];
 339         } else {
 340                 dwtmp = ptcb_desc->empkt_len[8];
 341                 dwtmp += ((dwtmp % 4) ? (4 - dwtmp % 4) : 0) + 4;
 342                 dwtmp += ptcb_desc->empkt_len[9];
 343         }
 344         SET_EARLYMODE_LEN4(virtualaddress, dwtmp);
 345 }
 346
 347 bool rtl92ee_rx_query_desc(struct ieee80211_hw *hw,
 348                            struct rtl_stats *status,
 349                            struct ieee80211_rx_status *rx_status,
 350                            u8 *pdesc, struct sk_buff *skb)
 351 {
 352         struct rtl_priv *rtlpriv = rtl_priv(hw);
 353         struct rx_fwinfo *p_drvinfo;
 354         struct ieee80211_hdr *hdr;
 355         u32 phystatus = GET_RX_DESC_PHYST(pdesc);
 356
 357         status->length = (u16)GET_RX_DESC_PKT_LEN(pdesc);
 358         status->rx_drvinfo_size = (u8)GET_RX_DESC_DRV_INFO_SIZE(pdesc) *
 359                                   RX_DRV_INFO_SIZE_UNIT;
 360         status->rx_bufshift = (u8)(GET_RX_DESC_SHIFT(pdesc) & 0x03);
 361         status->icv = (u16)GET_RX_DESC_ICV(pdesc);
 362         status->crc = (u16)GET_RX_DESC_CRC32(pdesc);
 363         status->hwerror = (status->crc | status->icv);
 364         status->decrypted = !GET_RX_DESC_SWDEC(pdesc);
 365         status->rate = (u8)GET_RX_DESC_RXMCS(pdesc);
 366         status->isampdu = (bool)(GET_RX_DESC_PAGGR(pdesc) == 1);
 367                 status->timestamp_low = GET_RX_DESC_TSFL(pdesc);
 368         status->is_cck = RTL92EE_RX_HAL_IS_CCK_RATE(status->rate);
 369
 370         status->macid = GET_RX_DESC_MACID(pdesc);
 371         if (GET_RX_STATUS_DESC_MAGIC_MATCH(pdesc))
 372                 status->wake_match = BIT(2);
 373         else if (GET_RX_STATUS_DESC_MAGIC_MATCH(pdesc))
 374                 status->wake_match = BIT(1);
 375         else if (GET_RX_STATUS_DESC_UNICAST_MATCH(pdesc))
 376                 status->wake_match = BIT(0);
 377         else
 378                 status->wake_match = 0;
 379         if (status->wake_match)
 380                 RT_TRACE(rtlpriv, COMP_RXDESC, DBG_LOUD,
 381                          "GGGGGGGGGGGGGet Wakeup Packet!! WakeMatch=%d\n",
 382                          status->wake_match);
 383         rx_status->freq = hw->conf.chandef.chan->center_freq;
 384         rx_status->band = hw->conf.chandef.chan->band;
 385
 386         hdr = (struct ieee80211_hdr *)(skb->data + status->rx_drvinfo_size +
 387                                        status->rx_bufshift + 24);
 388
 389         if (status->crc)
 390                 rx_status->flag |= RX_FLAG_FAILED_FCS_CRC;
 391
 392         if (status->rx_is40Mhzpacket)
 393                 rx_status->flag |= RX_FLAG_40MHZ;
 394
 395         if (status->is_ht)
 396                 rx_status->flag |= RX_FLAG_HT;
 397
 398         rx_status->flag |= RX_FLAG_MACTIME_START;
 399
 400         /* hw will set status->decrypted true, if it finds the
 401          * frame is open data frame or mgmt frame.
 402          * So hw will not decryption robust managment frame
 403          * for IEEE80211w but still set status->decrypted
 404          * true, so here we should set it back to undecrypted
 405          * for IEEE80211w frame, and mac80211 sw will help
 406          * to decrypt it
 407          */
 408         if (status->decrypted) {
 409                 if ((!_ieee80211_is_robust_mgmt_frame(hdr)) &&
 410                     (ieee80211_has_protected(hdr->frame_control)))
 411                         rx_status->flag |= RX_FLAG_DECRYPTED;
 412                 else
 413                         rx_status->flag &= ~RX_FLAG_DECRYPTED;
 414         }
 415
 416         /* rate_idx: index of data rate into band's
 417          * supported rates or MCS index if HT rates
 418          * are use (RX_FLAG_HT)
 419          * Notice: this is diff with windows define
 420          */
 421         rx_status->rate_idx = rtlwifi_rate_mapping(hw, status->is_ht,
 422                                                    false, status->rate);
 423
 424         rx_status->mactime = status->timestamp_low;
 425         if (phystatus) {
 426                 p_drvinfo = (struct rx_fwinfo *)(skb->data +
 427                                                  status->rx_bufshift + 24);
 428
 429                 _rtl92ee_translate_rx_signal_stuff(hw, skb, status, pdesc,
 430                                                    p_drvinfo);
 431         }
 432         rx_status->signal = status->recvsignalpower + 10;
 433         if (status->packet_report_type == TX_REPORT2) {
 434                 status->macid_valid_entry[0] =
 435                         GET_RX_RPT2_DESC_MACID_VALID_1(pdesc);
 436                 status->macid_valid_entry[1] =
 437                         GET_RX_RPT2_DESC_MACID_VALID_2(pdesc);
 438         }
 439         return true;
 440 }
 441
 442 /*in Windows, this == Rx_92EE_Interrupt*/
 443 void rtl92ee_rx_check_dma_ok(struct ieee80211_hw *hw, u8 *header_desc,
 444                              u8 queue_index)
 445 {
 446         u8 first_seg = 0;
 447         u8 last_seg = 0;
 448         u16 total_len = 0;
 449         u16 read_cnt = 0;
 450
 451         if (header_desc == NULL)
 452                 return;
 453
 454         total_len = (u16)GET_RX_BUFFER_DESC_TOTAL_LENGTH(header_desc);
 455
 456         first_seg = (u8)GET_RX_BUFFER_DESC_FS(header_desc);
 457
 458         last_seg = (u8)GET_RX_BUFFER_DESC_LS(header_desc);
 459
 460         while (total_len == 0 && first_seg == 0 && last_seg == 0) {
 461                 read_cnt++;
 462                 total_len = (u16)GET_RX_BUFFER_DESC_TOTAL_LENGTH(header_desc);
 463                 first_seg = (u8)GET_RX_BUFFER_DESC_FS(header_desc);
 464                 last_seg = (u8)GET_RX_BUFFER_DESC_LS(header_desc);
 465
 466                 if (read_cnt > 20)
 467                         break;
 468         }
 469 }
 470
 471 u16 rtl92ee_rx_desc_buff_remained_cnt(struct ieee80211_hw *hw, u8 queue_index)
 472 {
 473         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 474         struct rtl_priv *rtlpriv = rtl_priv(hw);
 475         u16 read_point = 0, write_point = 0, remind_cnt = 0;
 476         u32 tmp_4byte = 0;
 477         static u16 last_read_point;
 478         static bool start_rx;
 479
 480         tmp_4byte = rtl_read_dword(rtlpriv, REG_RXQ_TXBD_IDX);
 481         read_point = (u16)((tmp_4byte>>16) & 0x7ff);
 482         write_point = (u16)(tmp_4byte & 0x7ff);
 483
 484         if (write_point != rtlpci->rx_ring[queue_index].next_rx_rp) {
 485                 RT_TRACE(rtlpriv, COMP_RXDESC, DBG_DMESG,
 486                          "!!!write point is 0x%x, reg 0x3B4 value is 0x%x\n",
 487                           write_point, tmp_4byte);
 488                 tmp_4byte = rtl_read_dword(rtlpriv, REG_RXQ_TXBD_IDX);
 489                 read_point = (u16)((tmp_4byte>>16) & 0x7ff);
 490                 write_point = (u16)(tmp_4byte & 0x7ff);
 491         }
 492
 493         if (read_point > 0)
 494                 start_rx = true;
 495         if (!start_rx)
 496                 return 0;
 497
 498         if ((last_read_point > (RX_DESC_NUM_92E / 2)) &&
 499             (read_point <= (RX_DESC_NUM_92E / 2))) {
 500                 remind_cnt = RX_DESC_NUM_92E - write_point;
 501         } else {
 502                 remind_cnt = (read_point >= write_point) ?
 503                              (read_point - write_point) :
 504                              (RX_DESC_NUM_92E - write_point + read_point);
 505         }
 506
 507         if (remind_cnt == 0)
 508                 return 0;
 509
 510         rtlpci->rx_ring[queue_index].next_rx_rp = write_point;
 511
 512         last_read_point = read_point;
 513         return remind_cnt;
 514 }
 515
 516 static u16 get_desc_addr_fr_q_idx(u16 queue_index)
 517 {
 518         u16 desc_address = REG_BEQ_TXBD_IDX;
 519
 520         switch (queue_index) {
 521         case BK_QUEUE:
 522                 desc_address = REG_BKQ_TXBD_IDX;
 523                 break;
 524         case BE_QUEUE:
 525                 desc_address = REG_BEQ_TXBD_IDX;
 526                 break;
 527         case VI_QUEUE:
 528                 desc_address = REG_VIQ_TXBD_IDX;
 529                 break;
 530         case VO_QUEUE:
 531                 desc_address = REG_VOQ_TXBD_IDX;
 532                 break;
 533         case BEACON_QUEUE:
 534                 desc_address = REG_BEQ_TXBD_IDX;
 535                 break;
 536         case TXCMD_QUEUE:
 537                 desc_address = REG_BEQ_TXBD_IDX;
 538                 break;
 539         case MGNT_QUEUE:
 540                 desc_address = REG_MGQ_TXBD_IDX;
 541                 break;
 542         case HIGH_QUEUE:
 543                 desc_address = REG_HI0Q_TXBD_IDX;
 544                 break;
 545         case HCCA_QUEUE:
 546                 desc_address = REG_BEQ_TXBD_IDX;
 547                 break;
 548         default:
 549                 break;
 550         }
 551         return desc_address;
 552 }
 553
 554 void rtl92ee_pre_fill_tx_bd_desc(struct ieee80211_hw *hw,
 555                                  u8 *tx_bd_desc, u8 *desc, u8 queue_index,
 556                                  struct sk_buff *skb, dma_addr_t addr)
 557 {
 558         struct rtl_priv *rtlpriv = rtl_priv(hw);
 559         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 560         u32 pkt_len = skb->len;
 561         u16 desc_size = 40; /*tx desc size*/
 562         u32 psblen = 0;
 563         u16 tx_page_size = 0;
 564         u32 total_packet_size = 0;
 565         u16 current_bd_desc;
 566         u8 i = 0;
 567         u16 real_desc_size = 0x28;
 568         u16     append_early_mode_size = 0;
 569 #if (RTL8192EE_SEG_NUM == 0)
 570         u8 segmentnum = 2;
 571 #elif (RTL8192EE_SEG_NUM == 1)
 572         u8 segmentnum = 4;
 573 #elif (RTL8192EE_SEG_NUM == 2)
 574         u8 segmentnum = 8;
 575 #endif
 576
 577         tx_page_size = 2;
 578         current_bd_desc = rtlpci->tx_ring[queue_index].cur_tx_wp;
 579
 580         total_packet_size = desc_size+pkt_len;
 581
 582         if (rtlpriv->rtlhal.earlymode_enable)   {
 583                 if (queue_index < BEACON_QUEUE) {
 584                         append_early_mode_size = 8;
 585                         total_packet_size += append_early_mode_size;
 586                 }
 587         }
 588
 589         if (tx_page_size > 0) {
 590                 psblen = (pkt_len + real_desc_size + append_early_mode_size) /
 591                          (tx_page_size * 128);
 592
 593                 if (psblen * (tx_page_size * 128) < total_packet_size)
 594                         psblen += 1;
 595         }
 596
 597         /* Reset */
 598         SET_TX_BUFF_DESC_LEN_0(tx_bd_desc, 0);
 599         SET_TX_BUFF_DESC_PSB(tx_bd_desc, 0);
 600         SET_TX_BUFF_DESC_OWN(tx_bd_desc, 0);
 601
 602         for (i = 1; i < segmentnum; i++) {
 603                 SET_TXBUFFER_DESC_LEN_WITH_OFFSET(tx_bd_desc, i, 0);
 604                 SET_TXBUFFER_DESC_AMSDU_WITH_OFFSET(tx_bd_desc, i, 0);
 605                 SET_TXBUFFER_DESC_ADD_LOW_WITH_OFFSET(tx_bd_desc, i, 0);
 606 #if (DMA_IS_64BIT == 1)
 607                 SET_TXBUFFER_DESC_ADD_HIGT_WITH_OFFSET(tx_bd_desc, i, 0);
 608 #endif
 609         }
 610         SET_TX_BUFF_DESC_LEN_1(tx_bd_desc, 0);
 611         SET_TX_BUFF_DESC_AMSDU_1(tx_bd_desc, 0);
 612
 613         SET_TX_BUFF_DESC_LEN_2(tx_bd_desc, 0);
 614         SET_TX_BUFF_DESC_AMSDU_2(tx_bd_desc, 0);
 615         SET_TX_BUFF_DESC_LEN_3(tx_bd_desc, 0);
 616         SET_TX_BUFF_DESC_AMSDU_3(tx_bd_desc, 0);
 617         /* Clear all status */
 618         CLEAR_PCI_TX_DESC_CONTENT(desc, TX_DESC_SIZE);
 619
 620         if (rtlpriv->rtlhal.earlymode_enable) {
 621                 if (queue_index < BEACON_QUEUE) {
 622                         /* This if needs braces */
 623                         SET_TX_BUFF_DESC_LEN_0(tx_bd_desc, desc_size + 8);
 624                 } else {
 625                         SET_TX_BUFF_DESC_LEN_0(tx_bd_desc, desc_size);
 626                 }
 627         } else {
 628                 SET_TX_BUFF_DESC_LEN_0(tx_bd_desc, desc_size);
 629         }
 630         SET_TX_BUFF_DESC_PSB(tx_bd_desc, psblen);
 631         SET_TX_BUFF_DESC_ADDR_LOW_0(tx_bd_desc,
 632                                     rtlpci->tx_ring[queue_index].dma +
 633                                     (current_bd_desc * TX_DESC_SIZE));
 634
 635         SET_TXBUFFER_DESC_LEN_WITH_OFFSET(tx_bd_desc, 1, pkt_len);
 636         /* don't using extendsion mode. */
 637         SET_TXBUFFER_DESC_AMSDU_WITH_OFFSET(tx_bd_desc, 1, 0);
 638         SET_TXBUFFER_DESC_ADD_LOW_WITH_OFFSET(tx_bd_desc, 1, addr);
 639
 640         SET_TX_DESC_PKT_SIZE(desc, (u16)(pkt_len));
 641         SET_TX_DESC_TX_BUFFER_SIZE(desc, (u16)(pkt_len));
 642 }
 643
 644 void rtl92ee_tx_fill_desc(struct ieee80211_hw *hw,
 645                           struct ieee80211_hdr *hdr, u8 *pdesc_tx,
 646                           u8 *pbd_desc_tx,
 647                           struct ieee80211_tx_info *info,
 648                           struct ieee80211_sta *sta,
 649                           struct sk_buff *skb,
 650                           u8 hw_queue, struct rtl_tcb_desc *ptcb_desc)
 651 {
 652         struct rtl_priv *rtlpriv = rtl_priv(hw);
 653         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
 654         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 655         struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
 656         u8 *pdesc = (u8 *)pdesc_tx;
 657         u16 seq_number;
 658         __le16 fc = hdr->frame_control;
 659         unsigned int buf_len = 0;
 660         u8 fw_qsel = _rtl92ee_map_hwqueue_to_fwqueue(skb, hw_queue);
 661         bool firstseg = ((hdr->seq_ctrl &
 662                             cpu_to_le16(IEEE80211_SCTL_FRAG)) == 0);
 663         bool lastseg = ((hdr->frame_control &
 664                            cpu_to_le16(IEEE80211_FCTL_MOREFRAGS)) == 0);
 665         dma_addr_t mapping;
 666         u8 bw_40 = 0;
 667         u8 short_gi = 0;
 668
 669         if (mac->opmode == NL80211_IFTYPE_STATION) {
 670                 bw_40 = mac->bw_40;
 671         } else if (mac->opmode == NL80211_IFTYPE_AP ||
 672                    mac->opmode == NL80211_IFTYPE_ADHOC) {
 673                 if (sta)
 674                         bw_40 = sta->ht_cap.cap &
 675                                 IEEE80211_HT_CAP_SUP_WIDTH_20_40;
 676         }
 677         seq_number = (le16_to_cpu(hdr->seq_ctrl) & IEEE80211_SCTL_SEQ) >> 4;
 678         rtl_get_tcb_desc(hw, info, sta, skb, ptcb_desc);
 679         /* reserve 8 byte for AMPDU early mode */
 680         if (rtlhal->earlymode_enable) {
 681                 skb_push(skb, EM_HDR_LEN);
 682                 memset(skb->data, 0, EM_HDR_LEN);
 683         }
 684         buf_len = skb->len;
 685         mapping = pci_map_single(rtlpci->pdev, skb->data, skb->len,
 686                                  PCI_DMA_TODEVICE);
 687         if (pci_dma_mapping_error(rtlpci->pdev, mapping)) {
 688                 RT_TRACE(rtlpriv, COMP_SEND, DBG_TRACE,
 689                          "DMA mapping error");
 690                 return;
 691         }
 692
 693         if (pbd_desc_tx != NULL)
 694                 rtl92ee_pre_fill_tx_bd_desc(hw, pbd_desc_tx, pdesc, hw_queue,
 695                                             skb, mapping);
 696
 697         if (ieee80211_is_nullfunc(fc) || ieee80211_is_ctl(fc)) {
 698                 firstseg = true;
 699                 lastseg = true;
 700         }
 701         if (firstseg) {
 702                 if (rtlhal->earlymode_enable) {
 703                         SET_TX_DESC_PKT_OFFSET(pdesc, 1);
 704                         SET_TX_DESC_OFFSET(pdesc,
 705                                            USB_HWDESC_HEADER_LEN + EM_HDR_LEN);
 706                         if (ptcb_desc->empkt_num) {
 707                                 RT_TRACE(rtlpriv, COMP_SEND, DBG_TRACE,
 708                                          "Insert 8 byte.pTcb->EMPktNum:%d\n",
 709                                           ptcb_desc->empkt_num);
 710                                 _rtl92ee_insert_emcontent(ptcb_desc,
 711                                                           (u8 *)(skb->data));
 712                         }
 713                 } else {
 714                         SET_TX_DESC_OFFSET(pdesc, USB_HWDESC_HEADER_LEN);
 715                 }
 716
 717                 SET_TX_DESC_TX_RATE(pdesc, ptcb_desc->hw_rate);
 718
 719                 if (ieee80211_is_mgmt(fc)) {
 720                         ptcb_desc->use_driver_rate = true;
 721                 } else {
 722                         if (rtlpriv->ra.is_special_data) {
 723                                 ptcb_desc->use_driver_rate = true;
 724                                 SET_TX_DESC_TX_RATE(pdesc, DESC_RATE11M);
 725                         } else {
 726                                 ptcb_desc->use_driver_rate = false;
 727                         }
 728                 }
 729
 730                 if (ptcb_desc->hw_rate > DESC_RATEMCS0)
 731                         short_gi = (ptcb_desc->use_shortgi) ? 1 : 0;
 732                 else
 733                         short_gi = (ptcb_desc->use_shortpreamble) ? 1 : 0;
 734
 735                 if (info->flags & IEEE80211_TX_CTL_AMPDU) {
 736                         SET_TX_DESC_AGG_ENABLE(pdesc, 1);
 737                         SET_TX_DESC_MAX_AGG_NUM(pdesc, 0x14);
 738                 }
 739                 SET_TX_DESC_SEQ(pdesc, seq_number);
 740                 SET_TX_DESC_RTS_ENABLE(pdesc,
 741                                        ((ptcb_desc->rts_enable &&
 742                                          !ptcb_desc->cts_enable) ? 1 : 0));
 743                 SET_TX_DESC_HW_RTS_ENABLE(pdesc, 0);
 744                 SET_TX_DESC_CTS2SELF(pdesc,
 745                                      ((ptcb_desc->cts_enable) ? 1 : 0));
 746
 747                 SET_TX_DESC_RTS_RATE(pdesc, ptcb_desc->rts_rate);
 748                 SET_TX_DESC_RTS_SC(pdesc, ptcb_desc->rts_sc);
 749                 SET_TX_DESC_RTS_SHORT(pdesc,
 750                                 ((ptcb_desc->rts_rate <= DESC_RATE54M) ?
 751                                  (ptcb_desc->rts_use_shortpreamble ? 1 : 0) :
 752                                  (ptcb_desc->rts_use_shortgi ? 1 : 0)));
 753
 754                 if (ptcb_desc->tx_enable_sw_calc_duration)
 755                         SET_TX_DESC_NAV_USE_HDR(pdesc, 1);
 756
 757                 if (bw_40) {
 758                         if (ptcb_desc->packet_bw == HT_CHANNEL_WIDTH_20_40) {
 759                                 SET_TX_DESC_DATA_BW(pdesc, 1);
 760                                 SET_TX_DESC_TX_SUB_CARRIER(pdesc, 3);
 761                         } else {
 762                                 SET_TX_DESC_DATA_BW(pdesc, 0);
 763                                 SET_TX_DESC_TX_SUB_CARRIER(pdesc,
 764                                                            mac->cur_40_prime_sc);
 765                         }
 766                 } else {
 767                         SET_TX_DESC_DATA_BW(pdesc, 0);
 768                         SET_TX_DESC_TX_SUB_CARRIER(pdesc, 0);
 769                 }
 770
 771                 SET_TX_DESC_LINIP(pdesc, 0);
 772                 if (sta) {
 773                         u8 ampdu_density = sta->ht_cap.ampdu_density;
 774
 775                         SET_TX_DESC_AMPDU_DENSITY(pdesc, ampdu_density);
 776                 }
 777                 if (info->control.hw_key) {
 778                         struct ieee80211_key_conf *key = info->control.hw_key;
 779
 780                         switch (key->cipher) {
 781                         case WLAN_CIPHER_SUITE_WEP40:
 782                         case WLAN_CIPHER_SUITE_WEP104:
 783                         case WLAN_CIPHER_SUITE_TKIP:
 784                                 SET_TX_DESC_SEC_TYPE(pdesc, 0x1);
 785                                 break;
 786                         case WLAN_CIPHER_SUITE_CCMP:
 787                                 SET_TX_DESC_SEC_TYPE(pdesc, 0x3);
 788                                 break;
 789                         default:
 790                                 SET_TX_DESC_SEC_TYPE(pdesc, 0x0);
 791                                 break;
 792                         }
 793                 }
 794
 795                 SET_TX_DESC_QUEUE_SEL(pdesc, fw_qsel);
 796                 SET_TX_DESC_DATA_RATE_FB_LIMIT(pdesc, 0x1F);
 797                 SET_TX_DESC_RTS_RATE_FB_LIMIT(pdesc, 0xF);
 798                 SET_TX_DESC_DISABLE_FB(pdesc,
 799                                        ptcb_desc->disable_ratefallback ? 1 : 0);
 800                 SET_TX_DESC_USE_RATE(pdesc, ptcb_desc->use_driver_rate ? 1 : 0);
 801
 802                 /*SET_TX_DESC_PWR_STATUS(pdesc, pwr_status);*/
 803                 /* Set TxRate and RTSRate in TxDesc  */
 804                 /* This prevent Tx initial rate of new-coming packets */
 805                 /* from being overwritten by retried  packet rate.*/
 806                 if (!ptcb_desc->use_driver_rate) {
 807                         /*SET_TX_DESC_RTS_RATE(pdesc, 0x08); */
 808                         /* SET_TX_DESC_TX_RATE(pdesc, 0x0b); */
 809                 }
 810                 if (ieee80211_is_data_qos(fc)) {
 811                         if (mac->rdg_en) {
 812                                 RT_TRACE(rtlpriv, COMP_SEND, DBG_TRACE,
 813                                          "Enable RDG function.\n");
 814                                 SET_TX_DESC_RDG_ENABLE(pdesc, 1);
 815                                 SET_TX_DESC_HTC(pdesc, 1);
 816                         }
 817                 }
 818         }
 819
 820         SET_TX_DESC_FIRST_SEG(pdesc, (firstseg ? 1 : 0));
 821         SET_TX_DESC_LAST_SEG(pdesc, (lastseg ? 1 : 0));
 822         SET_TX_DESC_TX_BUFFER_ADDRESS(pdesc, mapping);
 823         if (rtlpriv->dm.useramask) {
 824                 SET_TX_DESC_RATE_ID(pdesc, ptcb_desc->ratr_index);
 825                 SET_TX_DESC_MACID(pdesc, ptcb_desc->mac_id);
 826         } else {
 827                 SET_TX_DESC_RATE_ID(pdesc, 0xC + ptcb_desc->ratr_index);
 828                 SET_TX_DESC_MACID(pdesc, ptcb_desc->ratr_index);
 829         }
 830
 831         SET_TX_DESC_MORE_FRAG(pdesc, (lastseg ? 0 : 1));
 832         if (is_multicast_ether_addr(ieee80211_get_DA(hdr)) ||
 833             is_broadcast_ether_addr(ieee80211_get_DA(hdr))) {
 834                 SET_TX_DESC_BMC(pdesc, 1);
 835         }
 836         RT_TRACE(rtlpriv, COMP_SEND, DBG_TRACE, "\n");
 837 }
 838
 839 void rtl92ee_tx_fill_cmddesc(struct ieee80211_hw *hw,
 840                              u8 *pdesc, bool firstseg,
 841                              bool lastseg, struct sk_buff *skb)
 842 {
 843         struct rtl_priv *rtlpriv = rtl_priv(hw);
 844         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 845         u8 fw_queue = QSLT_BEACON;
 846         dma_addr_t mapping = pci_map_single(rtlpci->pdev,
 847                                             skb->data, skb->len,
 848                                             PCI_DMA_TODEVICE);
 849         u8 txdesc_len = 40;
 850
 851         if (pci_dma_mapping_error(rtlpci->pdev, mapping)) {
 852                 RT_TRACE(rtlpriv, COMP_SEND, DBG_TRACE,
 853                          "DMA mapping error");
 854                 return;
 855         }
 856         CLEAR_PCI_TX_DESC_CONTENT(pdesc, txdesc_len);
 857
 858         if (firstseg)
 859                 SET_TX_DESC_OFFSET(pdesc, txdesc_len);
 860
 861         SET_TX_DESC_TX_RATE(pdesc, DESC_RATE1M);
 862
 863         SET_TX_DESC_SEQ(pdesc, 0);
 864
 865         SET_TX_DESC_LINIP(pdesc, 0);
 866
 867         SET_TX_DESC_QUEUE_SEL(pdesc, fw_queue);
 868
 869         SET_TX_DESC_FIRST_SEG(pdesc, 1);
 870         SET_TX_DESC_LAST_SEG(pdesc, 1);
 871
 872         SET_TX_DESC_TX_BUFFER_SIZE(pdesc, (u16)(skb->len));
 873
 874         SET_TX_DESC_TX_BUFFER_ADDRESS(pdesc, mapping);
 875
 876         SET_TX_DESC_RATE_ID(pdesc, 7);
 877         SET_TX_DESC_MACID(pdesc, 0);
 878
 879         SET_TX_DESC_OWN(pdesc, 1);
 880
 881         SET_TX_DESC_PKT_SIZE((u8 *)pdesc, (u16)(skb->len));
 882
 883         SET_TX_DESC_FIRST_SEG(pdesc, 1);
 884         SET_TX_DESC_LAST_SEG(pdesc, 1);
 885
 886         SET_TX_DESC_OFFSET(pdesc, 40);
 887
 888         SET_TX_DESC_USE_RATE(pdesc, 1);
 889
 890         RT_PRINT_DATA(rtlpriv, COMP_CMD, DBG_LOUD,
 891                       "H2C Tx Cmd Content\n", pdesc, txdesc_len);
 892 }
 893
 894 void rtl92ee_set_desc(struct ieee80211_hw *hw, u8 *pdesc, bool istx,
 895                       u8 desc_name, u8 *val)
 896 {
 897         struct rtl_priv *rtlpriv = rtl_priv(hw);
 898         u16 cur_tx_rp = 0;
 899         u16 cur_tx_wp = 0;
 900         static u16 last_txw_point;
 901         static bool over_run;
 902         u32 tmp = 0;
 903         u8 q_idx = *val;
 904
 905         if (istx) {
 906                 switch (desc_name) {
 907                 case HW_DESC_TX_NEXTDESC_ADDR:
 908                         SET_TX_DESC_NEXT_DESC_ADDRESS(pdesc, *(u32 *)val);
 909                         break;
 910                 case HW_DESC_OWN:{
 911                         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 912                         struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[q_idx];
 913                         u16 max_tx_desc = ring->entries;
 914
 915                         if (q_idx == BEACON_QUEUE) {
 916                                 ring->cur_tx_wp = 0;
 917                                 ring->cur_tx_rp = 0;
 918                                 SET_TX_BUFF_DESC_OWN(pdesc, 1);
 919                                 return;
 920                         }
 921
 922                         ring->cur_tx_wp = ((ring->cur_tx_wp + 1) % max_tx_desc);
 923
 924                         if (over_run) {
 925                                 ring->cur_tx_wp = 0;
 926                                 over_run = false;
 927                         }
 928                         if (ring->avl_desc > 1) {
 929                                 ring->avl_desc--;
 930
 931                                 rtl_write_word(rtlpriv,
 932                                                get_desc_addr_fr_q_idx(q_idx),
 933                                                ring->cur_tx_wp);
 934
 935                                 if (q_idx == 1)
 936                                         last_txw_point = cur_tx_wp;
 937                         }
 938
 939                         if (ring->avl_desc < (max_tx_desc - 15)) {
 940                                 u16 point_diff = 0;
 941
 942                                 tmp =
 943                                   rtl_read_dword(rtlpriv,
 944                                                  get_desc_addr_fr_q_idx(q_idx));
 945                                 cur_tx_rp = (u16)((tmp >> 16) & 0x0fff);
 946                                 cur_tx_wp = (u16)(tmp & 0x0fff);
 947
 948                                 ring->cur_tx_wp = cur_tx_wp;
 949                                 ring->cur_tx_rp = cur_tx_rp;
 950                                 point_diff = ((cur_tx_rp > cur_tx_wp) ?
 951                                               (cur_tx_rp - cur_tx_wp) :
 952                                               (TX_DESC_NUM_92E - 1 -
 953                                                cur_tx_wp + cur_tx_rp));
 954
 955                                 ring->avl_desc = point_diff;
 956                         }
 957                 }
 958                 break;
 959                 }
 960         } else {
 961                 switch (desc_name) {
 962                 case HW_DESC_RX_PREPARE:
 963                         SET_RX_BUFFER_DESC_LS(pdesc, 0);
 964                         SET_RX_BUFFER_DESC_FS(pdesc, 0);
 965                         SET_RX_BUFFER_DESC_TOTAL_LENGTH(pdesc, 0);
 966
 967                         SET_RX_BUFFER_DESC_DATA_LENGTH(pdesc,
 968                                                        MAX_RECEIVE_BUFFER_SIZE +
 969                                                        RX_DESC_SIZE);
 970
 971                         SET_RX_BUFFER_PHYSICAL_LOW(pdesc, *(u32 *)val);
 972                         break;
 973                 case HW_DESC_RXERO:
 974                         SET_RX_DESC_EOR(pdesc, 1);
 975                         break;
 976                 default:
 977                         RT_ASSERT(false,
 978                                   "ERR rxdesc :%d not process\n", desc_name);
 979                         break;
 980                 }
 981         }
 982 }
 983
 984 u32 rtl92ee_get_desc(u8 *pdesc, bool istx, u8 desc_name)
 985 {
 986         u32 ret = 0;
 987
 988         if (istx) {
 989                 switch (desc_name) {
 990                 case HW_DESC_OWN:
 991                         ret = GET_TX_DESC_OWN(pdesc);
 992                         break;
 993                 case HW_DESC_TXBUFF_ADDR:
 994                         ret = GET_TXBUFFER_DESC_ADDR_LOW(pdesc, 1);
 995                         break;
 996                 default:
 997                         RT_ASSERT(false,
 998                                   "ERR txdesc :%d not process\n", desc_name);
 999                         break;
1000                 }
1001         } else {
1002                 switch (desc_name) {
1003                 case HW_DESC_OWN:
1004                         ret = GET_RX_DESC_OWN(pdesc);
1005                         break;
1006                 case HW_DESC_RXPKT_LEN:
1007                         ret = GET_RX_DESC_PKT_LEN(pdesc);
1008                         break;
1009                 case HW_DESC_RXBUFF_ADDR:
1010                         ret = GET_RX_DESC_BUFF_ADDR(pdesc);
1011                         break;
1012                 default:
1013                         RT_ASSERT(false,
1014                                   "ERR rxdesc :%d not process\n", desc_name);
1015                         break;
1016                 }
1017         }
1018         return ret;
1019 }
1020
1021 bool rtl92ee_is_tx_desc_closed(struct ieee80211_hw *hw, u8 hw_queue, u16 index)
1022 {
1023         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1024         struct rtl_priv *rtlpriv = rtl_priv(hw);
1025         u16 read_point, write_point, available_desc_num;
1026         bool ret = false;
1027         static u8 stop_report_cnt;
1028         struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[hw_queue];
1029
1030         /*checking Read/Write Point each interrupt wastes CPU */
1031         if (stop_report_cnt > 15 || !rtlpriv->link_info.busytraffic) {
1032                 u16 point_diff = 0;
1033                 u16 cur_tx_rp, cur_tx_wp;
1034                 u32 tmpu32 = 0;
1035
1036                 tmpu32 =
1037                   rtl_read_dword(rtlpriv,
1038                                  get_desc_addr_fr_q_idx(hw_queue));
1039                 cur_tx_rp = (u16)((tmpu32 >> 16) & 0x0fff);
1040                 cur_tx_wp = (u16)(tmpu32 & 0x0fff);
1041
1042                 ring->cur_tx_wp = cur_tx_wp;
1043                 ring->cur_tx_rp = cur_tx_rp;
1044                 point_diff = ((cur_tx_rp > cur_tx_wp) ?
1045                               (cur_tx_rp - cur_tx_wp) :
1046                               (TX_DESC_NUM_92E - cur_tx_wp + cur_tx_rp));
1047
1048                 ring->avl_desc = point_diff;
1049         }
1050
1051         read_point = ring->cur_tx_rp;
1052         write_point = ring->cur_tx_wp;
1053         available_desc_num = ring->avl_desc;
1054
1055         if (write_point > read_point) {
1056                 if (index < write_point && index >= read_point)
1057                         ret = false;
1058                 else
1059                         ret = true;
1060         } else if (write_point < read_point) {
1061                 if (index > write_point && index < read_point)
1062                         ret = true;
1063                 else
1064                         ret = false;
1065         } else {
1066                 if (index != read_point)
1067                         ret = true;
1068         }
1069
1070         if (hw_queue == BEACON_QUEUE)
1071                 ret = true;
1072
1073         if (rtlpriv->rtlhal.driver_is_goingto_unload ||
1074             rtlpriv->psc.rfoff_reason > RF_CHANGE_BY_PS)
1075                 ret = true;
1076
1077         if (hw_queue < BEACON_QUEUE) {
1078                 if (!ret)
1079                         stop_report_cnt++;
1080                 else
1081                         stop_report_cnt = 0;
1082         }
1083
1084         return ret;
1085 }
1086
1087 void rtl92ee_tx_polling(struct ieee80211_hw *hw, u8 hw_queue)
1088 {
1089 }
1090
1091 u32 rtl92ee_rx_command_packet(struct ieee80211_hw *hw,
1092                               struct rtl_stats status,
1093                               struct sk_buff *skb)
1094 {
1095         u32 result = 0;
1096         struct rtl_priv *rtlpriv = rtl_priv(hw);
1097
1098         switch (status.packet_report_type) {
1099         case NORMAL_RX:
1100                 result = 0;
1101                 break;
1102         case C2H_PACKET:
1103                 rtl92ee_c2h_packet_handler(hw, skb->data, (u8)skb->len);
1104                 result = 1;
1105                 break;
1106         default:
1107                 RT_TRACE(rtlpriv, COMP_RECV, DBG_TRACE,
1108                          "Unknown packet type %d\n", status.packet_report_type);
1109                 break;
1110         }
1111
1112         return result;
1113 }