drivers/net/wireless/rtlwifi/rtl8192se/phy.c

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2009-2012  Realtek Corporation.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  17  *
  18  * The full GNU General Public License is included in this distribution in the
  19  * file called LICENSE.
  20  *
  21  * Contact Information:
  22  * wlanfae <wlanfae@realtek.com>
  23  * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
  24  * Hsinchu 300, Taiwan.
  25  *
  26  * Larry Finger <Larry.Finger@lwfinger.net>
  27  *
  28  *****************************************************************************/
  29
  30 #include "../wifi.h"
  31 #include "../pci.h"
  32 #include "../ps.h"
  33 #include "../core.h"
  34 #include "reg.h"
  35 #include "def.h"
  36 #include "phy.h"
  37 #include "rf.h"
  38 #include "dm.h"
  39 #include "fw.h"
  40 #include "hw.h"
  41 #include "table.h"
  42
  43 static u32 _rtl92s_phy_calculate_bit_shift(u32 bitmask)
  44 {
  45         u32 i;
  46
  47         for (i = 0; i <= 31; i++) {
  48                 if (((bitmask >> i) & 0x1) == 1)
  49                         break;
  50         }
  51
  52         return i;
  53 }
  54
  55 u32 rtl92s_phy_query_bb_reg(struct ieee80211_hw *hw, u32 regaddr, u32 bitmask)
  56 {
  57         struct rtl_priv *rtlpriv = rtl_priv(hw);
  58         u32 returnvalue = 0, originalvalue, bitshift;
  59
  60         RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, "regaddr(%#x), bitmask(%#x)\n",
  61                  regaddr, bitmask);
  62
  63         originalvalue = rtl_read_dword(rtlpriv, regaddr);
  64         bitshift = _rtl92s_phy_calculate_bit_shift(bitmask);
  65         returnvalue = (originalvalue & bitmask) >> bitshift;
  66
  67         RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, "BBR MASK=0x%x Addr[0x%x]=0x%x\n",
  68                  bitmask, regaddr, originalvalue);
  69
  70         return returnvalue;
  71
  72 }
  73
  74 void rtl92s_phy_set_bb_reg(struct ieee80211_hw *hw, u32 regaddr, u32 bitmask,
  75                            u32 data)
  76 {
  77         struct rtl_priv *rtlpriv = rtl_priv(hw);
  78         u32 originalvalue, bitshift;
  79
  80         RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
  81                  "regaddr(%#x), bitmask(%#x), data(%#x)\n",
  82                  regaddr, bitmask, data);
  83
  84         if (bitmask != MASKDWORD) {
  85                 originalvalue = rtl_read_dword(rtlpriv, regaddr);
  86                 bitshift = _rtl92s_phy_calculate_bit_shift(bitmask);
  87                 data = ((originalvalue & (~bitmask)) | (data << bitshift));
  88         }
  89
  90         rtl_write_dword(rtlpriv, regaddr, data);
  91
  92         RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
  93                  "regaddr(%#x), bitmask(%#x), data(%#x)\n",
  94                  regaddr, bitmask, data);
  95
  96 }
  97
  98 static u32 _rtl92s_phy_rf_serial_read(struct ieee80211_hw *hw,
  99                                       enum radio_path rfpath, u32 offset)
 100 {
 101
 102         struct rtl_priv *rtlpriv = rtl_priv(hw);
 103         struct rtl_phy *rtlphy = &(rtlpriv->phy);
 104         struct bb_reg_def *pphyreg = &rtlphy->phyreg_def[rfpath];
 105         u32 newoffset;
 106         u32 tmplong, tmplong2;
 107         u8 rfpi_enable = 0;
 108         u32 retvalue = 0;
 109
 110         offset &= 0x3f;
 111         newoffset = offset;
 112
 113         tmplong = rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD);
 114
 115         if (rfpath == RF90_PATH_A)
 116                 tmplong2 = tmplong;
 117         else
 118                 tmplong2 = rtl_get_bbreg(hw, pphyreg->rfhssi_para2, MASKDWORD);
 119
 120         tmplong2 = (tmplong2 & (~BLSSI_READADDRESS)) | (newoffset << 23) |
 121                         BLSSI_READEDGE;
 122
 123         rtl_set_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD,
 124                       tmplong & (~BLSSI_READEDGE));
 125
 126         mdelay(1);
 127
 128         rtl_set_bbreg(hw, pphyreg->rfhssi_para2, MASKDWORD, tmplong2);
 129         mdelay(1);
 130
 131         rtl_set_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD, tmplong |
 132                       BLSSI_READEDGE);
 133         mdelay(1);
 134
 135         if (rfpath == RF90_PATH_A)
 136                 rfpi_enable = (u8)rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER1,
 137                                                 BIT(8));
 138         else if (rfpath == RF90_PATH_B)
 139                 rfpi_enable = (u8)rtl_get_bbreg(hw, RFPGA0_XB_HSSIPARAMETER1,
 140                                                 BIT(8));
 141
 142         if (rfpi_enable)
 143                 retvalue = rtl_get_bbreg(hw, pphyreg->rf_rbpi,
 144                                          BLSSI_READBACK_DATA);
 145         else
 146                 retvalue = rtl_get_bbreg(hw, pphyreg->rf_rb,
 147                                          BLSSI_READBACK_DATA);
 148
 149         retvalue = rtl_get_bbreg(hw, pphyreg->rf_rb,
 150                                  BLSSI_READBACK_DATA);
 151
 152         RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, "RFR-%d Addr[0x%x]=0x%x\n",
 153                  rfpath, pphyreg->rf_rb, retvalue);
 154
 155         return retvalue;
 156
 157 }
 158
 159 static void _rtl92s_phy_rf_serial_write(struct ieee80211_hw *hw,
 160                                         enum radio_path rfpath, u32 offset,
 161                                         u32 data)
 162 {
 163         struct rtl_priv *rtlpriv = rtl_priv(hw);
 164         struct rtl_phy *rtlphy = &(rtlpriv->phy);
 165         struct bb_reg_def *pphyreg = &rtlphy->phyreg_def[rfpath];
 166         u32 data_and_addr = 0;
 167         u32 newoffset;
 168
 169         offset &= 0x3f;
 170         newoffset = offset;
 171
 172         data_and_addr = ((newoffset << 20) | (data & 0x000fffff)) & 0x0fffffff;
 173         rtl_set_bbreg(hw, pphyreg->rf3wire_offset, MASKDWORD, data_and_addr);
 174
 175         RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, "RFW-%d Addr[0x%x]=0x%x\n",
 176                  rfpath, pphyreg->rf3wire_offset, data_and_addr);
 177 }
 178
 179
 180 u32 rtl92s_phy_query_rf_reg(struct ieee80211_hw *hw, enum radio_path rfpath,
 181                             u32 regaddr, u32 bitmask)
 182 {
 183         struct rtl_priv *rtlpriv = rtl_priv(hw);
 184         u32 original_value, readback_value, bitshift;
 185
 186         RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
 187                  "regaddr(%#x), rfpath(%#x), bitmask(%#x)\n",
 188                  regaddr, rfpath, bitmask);
 189
 190         spin_lock(&rtlpriv->locks.rf_lock);
 191
 192         original_value = _rtl92s_phy_rf_serial_read(hw, rfpath, regaddr);
 193
 194         bitshift = _rtl92s_phy_calculate_bit_shift(bitmask);
 195         readback_value = (original_value & bitmask) >> bitshift;
 196
 197         spin_unlock(&rtlpriv->locks.rf_lock);
 198
 199         RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
 200                  "regaddr(%#x), rfpath(%#x), bitmask(%#x), original_value(%#x)\n",
 201                  regaddr, rfpath, bitmask, original_value);
 202
 203         return readback_value;
 204 }
 205
 206 void rtl92s_phy_set_rf_reg(struct ieee80211_hw *hw, enum radio_path rfpath,
 207                            u32 regaddr, u32 bitmask, u32 data)
 208 {
 209         struct rtl_priv *rtlpriv = rtl_priv(hw);
 210         struct rtl_phy *rtlphy = &(rtlpriv->phy);
 211         u32 original_value, bitshift;
 212
 213         if (!((rtlphy->rf_pathmap >> rfpath) & 0x1))
 214                 return;
 215
 216         RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
 217                  "regaddr(%#x), bitmask(%#x), data(%#x), rfpath(%#x)\n",
 218                  regaddr, bitmask, data, rfpath);
 219
 220         spin_lock(&rtlpriv->locks.rf_lock);
 221
 222         if (bitmask != RFREG_OFFSET_MASK) {
 223                 original_value = _rtl92s_phy_rf_serial_read(hw, rfpath,
 224                                                             regaddr);
 225                 bitshift = _rtl92s_phy_calculate_bit_shift(bitmask);
 226                 data = ((original_value & (~bitmask)) | (data << bitshift));
 227         }
 228
 229         _rtl92s_phy_rf_serial_write(hw, rfpath, regaddr, data);
 230
 231         spin_unlock(&rtlpriv->locks.rf_lock);
 232
 233         RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
 234                  "regaddr(%#x), bitmask(%#x), data(%#x), rfpath(%#x)\n",
 235                  regaddr, bitmask, data, rfpath);
 236
 237 }
 238
 239 void rtl92s_phy_scan_operation_backup(struct ieee80211_hw *hw,
 240                                       u8 operation)
 241 {
 242         struct rtl_priv *rtlpriv = rtl_priv(hw);
 243         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 244
 245         if (!is_hal_stop(rtlhal)) {
 246                 switch (operation) {
 247                 case SCAN_OPT_BACKUP:
 248                         rtl92s_phy_set_fw_cmd(hw, FW_CMD_PAUSE_DM_BY_SCAN);
 249                         break;
 250                 case SCAN_OPT_RESTORE:
 251                         rtl92s_phy_set_fw_cmd(hw, FW_CMD_RESUME_DM_BY_SCAN);
 252                         break;
 253                 default:
 254                         RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
 255                                  "Unknown operation\n");
 256                         break;
 257                 }
 258         }
 259 }
 260
 261 void rtl92s_phy_set_bw_mode(struct ieee80211_hw *hw,
 262                             enum nl80211_channel_type ch_type)
 263 {
 264         struct rtl_priv *rtlpriv = rtl_priv(hw);
 265         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 266         struct rtl_phy *rtlphy = &(rtlpriv->phy);
 267         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
 268         u8 reg_bw_opmode;
 269
 270         RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE, "Switch to %s bandwidth\n",
 271                  rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20 ?
 272                  "20MHz" : "40MHz");
 273
 274         if (rtlphy->set_bwmode_inprogress)
 275                 return;
 276         if (is_hal_stop(rtlhal))
 277                 return;
 278
 279         rtlphy->set_bwmode_inprogress = true;
 280
 281         reg_bw_opmode = rtl_read_byte(rtlpriv, BW_OPMODE);
 282         /* dummy read */
 283         rtl_read_byte(rtlpriv, RRSR + 2);
 284
 285         switch (rtlphy->current_chan_bw) {
 286         case HT_CHANNEL_WIDTH_20:
 287                 reg_bw_opmode |= BW_OPMODE_20MHZ;
 288                 rtl_write_byte(rtlpriv, BW_OPMODE, reg_bw_opmode);
 289                 break;
 290         case HT_CHANNEL_WIDTH_20_40:
 291                 reg_bw_opmode &= ~BW_OPMODE_20MHZ;
 292                 rtl_write_byte(rtlpriv, BW_OPMODE, reg_bw_opmode);
 293                 break;
 294         default:
 295                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
 296                          "unknown bandwidth: %#X\n", rtlphy->current_chan_bw);
 297                 break;
 298         }
 299
 300         switch (rtlphy->current_chan_bw) {
 301         case HT_CHANNEL_WIDTH_20:
 302                 rtl_set_bbreg(hw, RFPGA0_RFMOD, BRFMOD, 0x0);
 303                 rtl_set_bbreg(hw, RFPGA1_RFMOD, BRFMOD, 0x0);
 304
 305                 if (rtlhal->version >= VERSION_8192S_BCUT)
 306                         rtl_write_byte(rtlpriv, RFPGA0_ANALOGPARAMETER2, 0x58);
 307                 break;
 308         case HT_CHANNEL_WIDTH_20_40:
 309                 rtl_set_bbreg(hw, RFPGA0_RFMOD, BRFMOD, 0x1);
 310                 rtl_set_bbreg(hw, RFPGA1_RFMOD, BRFMOD, 0x1);
 311
 312                 rtl_set_bbreg(hw, RCCK0_SYSTEM, BCCK_SIDEBAND,
 313                                 (mac->cur_40_prime_sc >> 1));
 314                 rtl_set_bbreg(hw, ROFDM1_LSTF, 0xC00, mac->cur_40_prime_sc);
 315
 316                 if (rtlhal->version >= VERSION_8192S_BCUT)
 317                         rtl_write_byte(rtlpriv, RFPGA0_ANALOGPARAMETER2, 0x18);
 318                 break;
 319         default:
 320                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
 321                          "unknown bandwidth: %#X\n", rtlphy->current_chan_bw);
 322                 break;
 323         }
 324
 325         rtl92s_phy_rf6052_set_bandwidth(hw, rtlphy->current_chan_bw);
 326         rtlphy->set_bwmode_inprogress = false;
 327         RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE, "<==\n");
 328 }
 329
 330 static bool _rtl92s_phy_set_sw_chnl_cmdarray(struct swchnlcmd *cmdtable,
 331                 u32 cmdtableidx, u32 cmdtablesz, enum swchnlcmd_id cmdid,
 332                 u32 para1, u32 para2, u32 msdelay)
 333 {
 334         struct swchnlcmd *pcmd;
 335
 336         if (cmdtable == NULL) {
 337                 RT_ASSERT(false, "cmdtable cannot be NULL\n");
 338                 return false;
 339         }
 340
 341         if (cmdtableidx >= cmdtablesz)
 342                 return false;
 343
 344         pcmd = cmdtable + cmdtableidx;
 345         pcmd->cmdid = cmdid;
 346         pcmd->para1 = para1;
 347         pcmd->para2 = para2;
 348         pcmd->msdelay = msdelay;
 349
 350         return true;
 351 }
 352
 353 static bool _rtl92s_phy_sw_chnl_step_by_step(struct ieee80211_hw *hw,
 354              u8 channel, u8 *stage, u8 *step, u32 *delay)
 355 {
 356         struct rtl_priv *rtlpriv = rtl_priv(hw);
 357         struct rtl_phy *rtlphy = &(rtlpriv->phy);
 358         struct swchnlcmd precommoncmd[MAX_PRECMD_CNT];
 359         u32 precommoncmdcnt;
 360         struct swchnlcmd postcommoncmd[MAX_POSTCMD_CNT];
 361         u32 postcommoncmdcnt;
 362         struct swchnlcmd rfdependcmd[MAX_RFDEPENDCMD_CNT];
 363         u32 rfdependcmdcnt;
 364         struct swchnlcmd *currentcmd = NULL;
 365         u8 rfpath;
 366         u8 num_total_rfpath = rtlphy->num_total_rfpath;
 367
 368         precommoncmdcnt = 0;
 369         _rtl92s_phy_set_sw_chnl_cmdarray(precommoncmd, precommoncmdcnt++,
 370                         MAX_PRECMD_CNT, CMDID_SET_TXPOWEROWER_LEVEL, 0, 0, 0);
 371         _rtl92s_phy_set_sw_chnl_cmdarray(precommoncmd, precommoncmdcnt++,
 372                         MAX_PRECMD_CNT, CMDID_END, 0, 0, 0);
 373
 374         postcommoncmdcnt = 0;
 375
 376         _rtl92s_phy_set_sw_chnl_cmdarray(postcommoncmd, postcommoncmdcnt++,
 377                         MAX_POSTCMD_CNT, CMDID_END, 0, 0, 0);
 378
 379         rfdependcmdcnt = 0;
 380
 381         RT_ASSERT((channel >= 1 && channel <= 14),
 382                   "invalid channel for Zebra: %d\n", channel);
 383
 384         _rtl92s_phy_set_sw_chnl_cmdarray(rfdependcmd, rfdependcmdcnt++,
 385                                          MAX_RFDEPENDCMD_CNT, CMDID_RF_WRITEREG,
 386                                          RF_CHNLBW, channel, 10);
 387
 388         _rtl92s_phy_set_sw_chnl_cmdarray(rfdependcmd, rfdependcmdcnt++,
 389                         MAX_RFDEPENDCMD_CNT, CMDID_END, 0, 0, 0);
 390
 391         do {
 392                 switch (*stage) {
 393                 case 0:
 394                         currentcmd = &precommoncmd[*step];
 395                         break;
 396                 case 1:
 397                         currentcmd = &rfdependcmd[*step];
 398                         break;
 399                 case 2:
 400                         currentcmd = &postcommoncmd[*step];
 401                         break;
 402                 }
 403
 404                 if (currentcmd->cmdid == CMDID_END) {
 405                         if ((*stage) == 2) {
 406                                 return true;
 407                         } else {
 408                                 (*stage)++;
 409                                 (*step) = 0;
 410                                 continue;
 411                         }
 412                 }
 413
 414                 switch (currentcmd->cmdid) {
 415                 case CMDID_SET_TXPOWEROWER_LEVEL:
 416                         rtl92s_phy_set_txpower(hw, channel);
 417                         break;
 418                 case CMDID_WRITEPORT_ULONG:
 419                         rtl_write_dword(rtlpriv, currentcmd->para1,
 420                                         currentcmd->para2);
 421                         break;
 422                 case CMDID_WRITEPORT_USHORT:
 423                         rtl_write_word(rtlpriv, currentcmd->para1,
 424                                        (u16)currentcmd->para2);
 425                         break;
 426                 case CMDID_WRITEPORT_UCHAR:
 427                         rtl_write_byte(rtlpriv, currentcmd->para1,
 428                                        (u8)currentcmd->para2);
 429                         break;
 430                 case CMDID_RF_WRITEREG:
 431                         for (rfpath = 0; rfpath < num_total_rfpath; rfpath++) {
 432                                 rtlphy->rfreg_chnlval[rfpath] =
 433                                          ((rtlphy->rfreg_chnlval[rfpath] &
 434                                          0xfffffc00) | currentcmd->para2);
 435                                 rtl_set_rfreg(hw, (enum radio_path)rfpath,
 436                                               currentcmd->para1,
 437                                               RFREG_OFFSET_MASK,
 438                                               rtlphy->rfreg_chnlval[rfpath]);
 439                         }
 440                         break;
 441                 default:
 442                         RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
 443                                  "switch case not processed\n");
 444                         break;
 445                 }
 446
 447                 break;
 448         } while (true);
 449
 450         (*delay) = currentcmd->msdelay;
 451         (*step)++;
 452         return false;
 453 }
 454
 455 u8 rtl92s_phy_sw_chnl(struct ieee80211_hw *hw)
 456 {
 457         struct rtl_priv *rtlpriv = rtl_priv(hw);
 458         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 459         struct rtl_phy *rtlphy = &(rtlpriv->phy);
 460         u32 delay;
 461         bool ret;
 462
 463         RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE, "switch to channel%d\n",
 464                  rtlphy->current_channel);
 465
 466         if (rtlphy->sw_chnl_inprogress)
 467                 return 0;
 468
 469         if (rtlphy->set_bwmode_inprogress)
 470                 return 0;
 471
 472         if (is_hal_stop(rtlhal))
 473                 return 0;
 474
 475         rtlphy->sw_chnl_inprogress = true;
 476         rtlphy->sw_chnl_stage = 0;
 477         rtlphy->sw_chnl_step = 0;
 478
 479         do {
 480                 if (!rtlphy->sw_chnl_inprogress)
 481                         break;
 482
 483                 ret = _rtl92s_phy_sw_chnl_step_by_step(hw,
 484                                  rtlphy->current_channel,
 485                                  &rtlphy->sw_chnl_stage,
 486                                  &rtlphy->sw_chnl_step, &delay);
 487                 if (!ret) {
 488                         if (delay > 0)
 489                                 mdelay(delay);
 490                         else
 491                                 continue;
 492                 } else {
 493                         rtlphy->sw_chnl_inprogress = false;
 494                 }
 495                 break;
 496         } while (true);
 497
 498         rtlphy->sw_chnl_inprogress = false;
 499
 500         RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE, "<==\n");
 501
 502         return 1;
 503 }
 504
 505 static void _rtl92se_phy_set_rf_sleep(struct ieee80211_hw *hw)
 506 {
 507         struct rtl_priv *rtlpriv = rtl_priv(hw);
 508         u8 u1btmp;
 509
 510         u1btmp = rtl_read_byte(rtlpriv, LDOV12D_CTRL);
 511         u1btmp |= BIT(0);
 512
 513         rtl_write_byte(rtlpriv, LDOV12D_CTRL, u1btmp);
 514         rtl_write_byte(rtlpriv, SPS1_CTRL, 0x0);
 515         rtl_write_byte(rtlpriv, TXPAUSE, 0xFF);
 516         rtl_write_word(rtlpriv, CMDR, 0x57FC);
 517         udelay(100);
 518
 519         rtl_write_word(rtlpriv, CMDR, 0x77FC);
 520         rtl_write_byte(rtlpriv, PHY_CCA, 0x0);
 521         udelay(10);
 522
 523         rtl_write_word(rtlpriv, CMDR, 0x37FC);
 524         udelay(10);
 525
 526         rtl_write_word(rtlpriv, CMDR, 0x77FC);
 527         udelay(10);
 528
 529         rtl_write_word(rtlpriv, CMDR, 0x57FC);
 530
 531         /* we should chnge GPIO to input mode
 532          * this will drop away current about 25mA*/
 533         rtl8192se_gpiobit3_cfg_inputmode(hw);
 534 }
 535
 536 bool rtl92s_phy_set_rf_power_state(struct ieee80211_hw *hw,
 537                                    enum rf_pwrstate rfpwr_state)
 538 {
 539         struct rtl_priv *rtlpriv = rtl_priv(hw);
 540         struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
 541         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
 542         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
 543         bool bresult = true;
 544         u8 i, queue_id;
 545         struct rtl8192_tx_ring *ring = NULL;
 546
 547         if (rfpwr_state == ppsc->rfpwr_state)
 548                 return false;
 549
 550         switch (rfpwr_state) {
 551         case ERFON:{
 552                         if ((ppsc->rfpwr_state == ERFOFF) &&
 553                             RT_IN_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC)) {
 554
 555                                 bool rtstatus;
 556                                 u32 InitializeCount = 0;
 557                                 do {
 558                                         InitializeCount++;
 559                                         RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
 560                                                  "IPS Set eRf nic enable\n");
 561                                         rtstatus = rtl_ps_enable_nic(hw);
 562                                 } while (!rtstatus && (InitializeCount < 10));
 563
 564                                 RT_CLEAR_PS_LEVEL(ppsc,
 565                                                   RT_RF_OFF_LEVL_HALT_NIC);
 566                         } else {
 567                                 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
 568                                          "awake, sleeped:%d ms state_inap:%x\n",
 569                                          jiffies_to_msecs(jiffies -
 570                                                           ppsc->
 571                                                           last_sleep_jiffies),
 572                                          rtlpriv->psc.state_inap);
 573                                 ppsc->last_awake_jiffies = jiffies;
 574                                 rtl_write_word(rtlpriv, CMDR, 0x37FC);
 575                                 rtl_write_byte(rtlpriv, TXPAUSE, 0x00);
 576                                 rtl_write_byte(rtlpriv, PHY_CCA, 0x3);
 577                         }
 578
 579                         if (mac->link_state == MAC80211_LINKED)
 580                                 rtlpriv->cfg->ops->led_control(hw,
 581                                                          LED_CTL_LINK);
 582                         else
 583                                 rtlpriv->cfg->ops->led_control(hw,
 584                                                          LED_CTL_NO_LINK);
 585                         break;
 586                 }
 587         case ERFOFF:{
 588                         if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_HALT_NIC) {
 589                                 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
 590                                          "IPS Set eRf nic disable\n");
 591                                 rtl_ps_disable_nic(hw);
 592                                 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
 593                         } else {
 594                                 if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS)
 595                                         rtlpriv->cfg->ops->led_control(hw,
 596                                                          LED_CTL_NO_LINK);
 597                                 else
 598                                         rtlpriv->cfg->ops->led_control(hw,
 599                                                          LED_CTL_POWER_OFF);
 600                         }
 601                         break;
 602                 }
 603         case ERFSLEEP:
 604                         if (ppsc->rfpwr_state == ERFOFF)
 605                                 return false;
 606
 607                         for (queue_id = 0, i = 0;
 608                              queue_id < RTL_PCI_MAX_TX_QUEUE_COUNT;) {
 609                                 ring = &pcipriv->dev.tx_ring[queue_id];
 610                                 if (skb_queue_len(&ring->queue) == 0 ||
 611                                         queue_id == BEACON_QUEUE) {
 612                                         queue_id++;
 613                                         continue;
 614                                 } else {
 615                                         RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
 616                                                  "eRf Off/Sleep: %d times TcbBusyQueue[%d] = %d before doze!\n",
 617                                                  i + 1, queue_id,
 618                                                  skb_queue_len(&ring->queue));
 619
 620                                         udelay(10);
 621                                         i++;
 622                                 }
 623
 624                                 if (i >= MAX_DOZE_WAITING_TIMES_9x) {
 625                                         RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
 626                                                  "ERFOFF: %d times TcbBusyQueue[%d] = %d !\n",
 627                                                  MAX_DOZE_WAITING_TIMES_9x,
 628                                                  queue_id,
 629                                                  skb_queue_len(&ring->queue));
 630                                         break;
 631                                 }
 632                         }
 633
 634                         RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
 635                                  "Set ERFSLEEP awaked:%d ms\n",
 636                                  jiffies_to_msecs(jiffies -
 637                                                   ppsc->last_awake_jiffies));
 638
 639                         RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
 640                                  "sleep awaked:%d ms state_inap:%x\n",
 641                                  jiffies_to_msecs(jiffies -
 642                                                   ppsc->last_awake_jiffies),
 643                                  rtlpriv->psc.state_inap);
 644                         ppsc->last_sleep_jiffies = jiffies;
 645                         _rtl92se_phy_set_rf_sleep(hw);
 646             break;
 647         default:
 648                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
 649                          "switch case not processed\n");
 650                 bresult = false;
 651                 break;
 652         }
 653
 654         if (bresult)
 655                 ppsc->rfpwr_state = rfpwr_state;
 656
 657         return bresult;
 658 }
 659
 660 static bool _rtl92s_phy_config_rfpa_bias_current(struct ieee80211_hw *hw,
 661                                                  enum radio_path rfpath)
 662 {
 663         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 664         bool rtstatus = true;
 665         u32 tmpval = 0;
 666
 667         /* If inferiority IC, we have to increase the PA bias current */
 668         if (rtlhal->ic_class != IC_INFERIORITY_A) {
 669                 tmpval = rtl92s_phy_query_rf_reg(hw, rfpath, RF_IPA, 0xf);
 670                 rtl92s_phy_set_rf_reg(hw, rfpath, RF_IPA, 0xf, tmpval + 1);
 671         }
 672
 673         return rtstatus;
 674 }
 675
 676 static void _rtl92s_store_pwrindex_diffrate_offset(struct ieee80211_hw *hw,
 677                 u32 reg_addr, u32 bitmask, u32 data)
 678 {
 679         struct rtl_priv *rtlpriv = rtl_priv(hw);
 680         struct rtl_phy *rtlphy = &(rtlpriv->phy);
 681         int index;
 682
 683         if (reg_addr == RTXAGC_RATE18_06)
 684                 index = 0;
 685         else if (reg_addr == RTXAGC_RATE54_24)
 686                 index = 1;
 687         else if (reg_addr == RTXAGC_CCK_MCS32)
 688                 index = 6;
 689         else if (reg_addr == RTXAGC_MCS03_MCS00)
 690                 index = 2;
 691         else if (reg_addr == RTXAGC_MCS07_MCS04)
 692                 index = 3;
 693         else if (reg_addr == RTXAGC_MCS11_MCS08)
 694                 index = 4;
 695         else if (reg_addr == RTXAGC_MCS15_MCS12)
 696                 index = 5;
 697         else
 698                 return;
 699
 700         rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][index] = data;
 701         if (index == 5)
 702                 rtlphy->pwrgroup_cnt++;
 703 }
 704
 705 static void _rtl92s_phy_init_register_definition(struct ieee80211_hw *hw)
 706 {
 707         struct rtl_priv *rtlpriv = rtl_priv(hw);
 708         struct rtl_phy *rtlphy = &(rtlpriv->phy);
 709
 710         /*RF Interface Sowrtware Control */
 711         rtlphy->phyreg_def[RF90_PATH_A].rfintfs = RFPGA0_XAB_RFINTERFACESW;
 712         rtlphy->phyreg_def[RF90_PATH_B].rfintfs = RFPGA0_XAB_RFINTERFACESW;
 713         rtlphy->phyreg_def[RF90_PATH_C].rfintfs = RFPGA0_XCD_RFINTERFACESW;
 714         rtlphy->phyreg_def[RF90_PATH_D].rfintfs = RFPGA0_XCD_RFINTERFACESW;
 715
 716         /* RF Interface Readback Value */
 717         rtlphy->phyreg_def[RF90_PATH_A].rfintfi = RFPGA0_XAB_RFINTERFACERB;
 718         rtlphy->phyreg_def[RF90_PATH_B].rfintfi = RFPGA0_XAB_RFINTERFACERB;
 719         rtlphy->phyreg_def[RF90_PATH_C].rfintfi = RFPGA0_XCD_RFINTERFACERB;
 720         rtlphy->phyreg_def[RF90_PATH_D].rfintfi = RFPGA0_XCD_RFINTERFACERB;
 721
 722         /* RF Interface Output (and Enable) */
 723         rtlphy->phyreg_def[RF90_PATH_A].rfintfo = RFPGA0_XA_RFINTERFACEOE;
 724         rtlphy->phyreg_def[RF90_PATH_B].rfintfo = RFPGA0_XB_RFINTERFACEOE;
 725         rtlphy->phyreg_def[RF90_PATH_C].rfintfo = RFPGA0_XC_RFINTERFACEOE;
 726         rtlphy->phyreg_def[RF90_PATH_D].rfintfo = RFPGA0_XD_RFINTERFACEOE;
 727
 728         /* RF Interface (Output and)  Enable */
 729         rtlphy->phyreg_def[RF90_PATH_A].rfintfe = RFPGA0_XA_RFINTERFACEOE;
 730         rtlphy->phyreg_def[RF90_PATH_B].rfintfe = RFPGA0_XB_RFINTERFACEOE;
 731         rtlphy->phyreg_def[RF90_PATH_C].rfintfe = RFPGA0_XC_RFINTERFACEOE;
 732         rtlphy->phyreg_def[RF90_PATH_D].rfintfe = RFPGA0_XD_RFINTERFACEOE;
 733
 734         /* Addr of LSSI. Wirte RF register by driver */
 735         rtlphy->phyreg_def[RF90_PATH_A].rf3wire_offset =
 736                                                  RFPGA0_XA_LSSIPARAMETER;
 737         rtlphy->phyreg_def[RF90_PATH_B].rf3wire_offset =
 738                                                  RFPGA0_XB_LSSIPARAMETER;
 739         rtlphy->phyreg_def[RF90_PATH_C].rf3wire_offset =
 740                                                  RFPGA0_XC_LSSIPARAMETER;
 741         rtlphy->phyreg_def[RF90_PATH_D].rf3wire_offset =
 742                                                  RFPGA0_XD_LSSIPARAMETER;
 743
 744         /* RF parameter */
 745         rtlphy->phyreg_def[RF90_PATH_A].rflssi_select = RFPGA0_XAB_RFPARAMETER;
 746         rtlphy->phyreg_def[RF90_PATH_B].rflssi_select = RFPGA0_XAB_RFPARAMETER;
 747         rtlphy->phyreg_def[RF90_PATH_C].rflssi_select = RFPGA0_XCD_RFPARAMETER;
 748         rtlphy->phyreg_def[RF90_PATH_D].rflssi_select = RFPGA0_XCD_RFPARAMETER;
 749
 750         /* Tx AGC Gain Stage (same for all path. Should we remove this?) */
 751         rtlphy->phyreg_def[RF90_PATH_A].rftxgain_stage = RFPGA0_TXGAINSTAGE;
 752         rtlphy->phyreg_def[RF90_PATH_B].rftxgain_stage = RFPGA0_TXGAINSTAGE;
 753         rtlphy->phyreg_def[RF90_PATH_C].rftxgain_stage = RFPGA0_TXGAINSTAGE;
 754         rtlphy->phyreg_def[RF90_PATH_D].rftxgain_stage = RFPGA0_TXGAINSTAGE;
 755
 756         /* Tranceiver A~D HSSI Parameter-1 */
 757         rtlphy->phyreg_def[RF90_PATH_A].rfhssi_para1 = RFPGA0_XA_HSSIPARAMETER1;
 758         rtlphy->phyreg_def[RF90_PATH_B].rfhssi_para1 = RFPGA0_XB_HSSIPARAMETER1;
 759         rtlphy->phyreg_def[RF90_PATH_C].rfhssi_para1 = RFPGA0_XC_HSSIPARAMETER1;
 760         rtlphy->phyreg_def[RF90_PATH_D].rfhssi_para1 = RFPGA0_XD_HSSIPARAMETER1;
 761
 762         /* Tranceiver A~D HSSI Parameter-2 */
 763         rtlphy->phyreg_def[RF90_PATH_A].rfhssi_para2 = RFPGA0_XA_HSSIPARAMETER2;
 764         rtlphy->phyreg_def[RF90_PATH_B].rfhssi_para2 = RFPGA0_XB_HSSIPARAMETER2;
 765         rtlphy->phyreg_def[RF90_PATH_C].rfhssi_para2 = RFPGA0_XC_HSSIPARAMETER2;
 766         rtlphy->phyreg_def[RF90_PATH_D].rfhssi_para2 = RFPGA0_XD_HSSIPARAMETER2;
 767
 768         /* RF switch Control */
 769         rtlphy->phyreg_def[RF90_PATH_A].rfsw_ctrl = RFPGA0_XAB_SWITCHCONTROL;
 770         rtlphy->phyreg_def[RF90_PATH_B].rfsw_ctrl = RFPGA0_XAB_SWITCHCONTROL;
 771         rtlphy->phyreg_def[RF90_PATH_C].rfsw_ctrl = RFPGA0_XCD_SWITCHCONTROL;
 772         rtlphy->phyreg_def[RF90_PATH_D].rfsw_ctrl = RFPGA0_XCD_SWITCHCONTROL;
 773
 774         /* AGC control 1  */
 775         rtlphy->phyreg_def[RF90_PATH_A].rfagc_control1 = ROFDM0_XAAGCCORE1;
 776         rtlphy->phyreg_def[RF90_PATH_B].rfagc_control1 = ROFDM0_XBAGCCORE1;
 777         rtlphy->phyreg_def[RF90_PATH_C].rfagc_control1 = ROFDM0_XCAGCCORE1;
 778         rtlphy->phyreg_def[RF90_PATH_D].rfagc_control1 = ROFDM0_XDAGCCORE1;
 779
 780         /* AGC control 2  */
 781         rtlphy->phyreg_def[RF90_PATH_A].rfagc_control2 = ROFDM0_XAAGCCORE2;
 782         rtlphy->phyreg_def[RF90_PATH_B].rfagc_control2 = ROFDM0_XBAGCCORE2;
 783         rtlphy->phyreg_def[RF90_PATH_C].rfagc_control2 = ROFDM0_XCAGCCORE2;
 784         rtlphy->phyreg_def[RF90_PATH_D].rfagc_control2 = ROFDM0_XDAGCCORE2;
 785
 786         /* RX AFE control 1  */
 787         rtlphy->phyreg_def[RF90_PATH_A].rfrxiq_imbal = ROFDM0_XARXIQIMBALANCE;
 788         rtlphy->phyreg_def[RF90_PATH_B].rfrxiq_imbal = ROFDM0_XBRXIQIMBALANCE;
 789         rtlphy->phyreg_def[RF90_PATH_C].rfrxiq_imbal = ROFDM0_XCRXIQIMBALANCE;
 790         rtlphy->phyreg_def[RF90_PATH_D].rfrxiq_imbal = ROFDM0_XDRXIQIMBALANCE;
 791
 792         /* RX AFE control 1   */
 793         rtlphy->phyreg_def[RF90_PATH_A].rfrx_afe = ROFDM0_XARXAFE;
 794         rtlphy->phyreg_def[RF90_PATH_B].rfrx_afe = ROFDM0_XBRXAFE;
 795         rtlphy->phyreg_def[RF90_PATH_C].rfrx_afe = ROFDM0_XCRXAFE;
 796         rtlphy->phyreg_def[RF90_PATH_D].rfrx_afe = ROFDM0_XDRXAFE;
 797
 798         /* Tx AFE control 1  */
 799         rtlphy->phyreg_def[RF90_PATH_A].rftxiq_imbal = ROFDM0_XATXIQIMBALANCE;
 800         rtlphy->phyreg_def[RF90_PATH_B].rftxiq_imbal = ROFDM0_XBTXIQIMBALANCE;
 801         rtlphy->phyreg_def[RF90_PATH_C].rftxiq_imbal = ROFDM0_XCTXIQIMBALANCE;
 802         rtlphy->phyreg_def[RF90_PATH_D].rftxiq_imbal = ROFDM0_XDTXIQIMBALANCE;
 803
 804         /* Tx AFE control 2  */
 805         rtlphy->phyreg_def[RF90_PATH_A].rftx_afe = ROFDM0_XATXAFE;
 806         rtlphy->phyreg_def[RF90_PATH_B].rftx_afe = ROFDM0_XBTXAFE;
 807         rtlphy->phyreg_def[RF90_PATH_C].rftx_afe = ROFDM0_XCTXAFE;
 808         rtlphy->phyreg_def[RF90_PATH_D].rftx_afe = ROFDM0_XDTXAFE;
 809
 810         /* Tranceiver LSSI Readback */
 811         rtlphy->phyreg_def[RF90_PATH_A].rf_rb = RFPGA0_XA_LSSIREADBACK;
 812         rtlphy->phyreg_def[RF90_PATH_B].rf_rb = RFPGA0_XB_LSSIREADBACK;
 813         rtlphy->phyreg_def[RF90_PATH_C].rf_rb = RFPGA0_XC_LSSIREADBACK;
 814         rtlphy->phyreg_def[RF90_PATH_D].rf_rb = RFPGA0_XD_LSSIREADBACK;
 815
 816         /* Tranceiver LSSI Readback PI mode  */
 817         rtlphy->phyreg_def[RF90_PATH_A].rf_rbpi = TRANSCEIVERA_HSPI_READBACK;
 818         rtlphy->phyreg_def[RF90_PATH_B].rf_rbpi = TRANSCEIVERB_HSPI_READBACK;
 819 }
 820
 821
 822 static bool _rtl92s_phy_config_bb(struct ieee80211_hw *hw, u8 configtype)
 823 {
 824         int i;
 825         u32 *phy_reg_table;
 826         u32 *agc_table;
 827         u16 phy_reg_len, agc_len;
 828
 829         agc_len = AGCTAB_ARRAYLENGTH;
 830         agc_table = rtl8192seagctab_array;
 831         /* Default RF_type: 2T2R */
 832         phy_reg_len = PHY_REG_2T2RARRAYLENGTH;
 833         phy_reg_table = rtl8192sephy_reg_2t2rarray;
 834
 835         if (configtype == BASEBAND_CONFIG_PHY_REG) {
 836                 for (i = 0; i < phy_reg_len; i = i + 2) {
 837                         rtl_addr_delay(phy_reg_table[i]);
 838
 839                         /* Add delay for ECS T20 & LG malow platform, */
 840                         udelay(1);
 841
 842                         rtl92s_phy_set_bb_reg(hw, phy_reg_table[i], MASKDWORD,
 843                                         phy_reg_table[i + 1]);
 844                 }
 845         } else if (configtype == BASEBAND_CONFIG_AGC_TAB) {
 846                 for (i = 0; i < agc_len; i = i + 2) {
 847                         rtl92s_phy_set_bb_reg(hw, agc_table[i], MASKDWORD,
 848                                         agc_table[i + 1]);
 849
 850                         /* Add delay for ECS T20 & LG malow platform */
 851                         udelay(1);
 852                 }
 853         }
 854
 855         return true;
 856 }
 857
 858 static bool _rtl92s_phy_set_bb_to_diff_rf(struct ieee80211_hw *hw,
 859                                           u8 configtype)
 860 {
 861         struct rtl_priv *rtlpriv = rtl_priv(hw);
 862         struct rtl_phy *rtlphy = &(rtlpriv->phy);
 863         u32 *phy_regarray2xtxr_table;
 864         u16 phy_regarray2xtxr_len;
 865         int i;
 866
 867         if (rtlphy->rf_type == RF_1T1R) {
 868                 phy_regarray2xtxr_table = rtl8192sephy_changeto_1t1rarray;
 869                 phy_regarray2xtxr_len = PHY_CHANGETO_1T1RARRAYLENGTH;
 870         } else if (rtlphy->rf_type == RF_1T2R) {
 871                 phy_regarray2xtxr_table = rtl8192sephy_changeto_1t2rarray;
 872                 phy_regarray2xtxr_len = PHY_CHANGETO_1T2RARRAYLENGTH;
 873         } else {
 874                 return false;
 875         }
 876
 877         if (configtype == BASEBAND_CONFIG_PHY_REG) {
 878                 for (i = 0; i < phy_regarray2xtxr_len; i = i + 3) {
 879                         rtl_addr_delay(phy_regarray2xtxr_table[i]);
 880
 881                         rtl92s_phy_set_bb_reg(hw, phy_regarray2xtxr_table[i],
 882                                 phy_regarray2xtxr_table[i + 1],
 883                                 phy_regarray2xtxr_table[i + 2]);
 884                 }
 885         }
 886
 887         return true;
 888 }
 889
 890 static bool _rtl92s_phy_config_bb_with_pg(struct ieee80211_hw *hw,
 891                                           u8 configtype)
 892 {
 893         int i;
 894         u32 *phy_table_pg;
 895         u16 phy_pg_len;
 896
 897         phy_pg_len = PHY_REG_ARRAY_PGLENGTH;
 898         phy_table_pg = rtl8192sephy_reg_array_pg;
 899
 900         if (configtype == BASEBAND_CONFIG_PHY_REG) {
 901                 for (i = 0; i < phy_pg_len; i = i + 3) {
 902                         rtl_addr_delay(phy_table_pg[i]);
 903
 904                         _rtl92s_store_pwrindex_diffrate_offset(hw,
 905                                         phy_table_pg[i],
 906                                         phy_table_pg[i + 1],
 907                                         phy_table_pg[i + 2]);
 908                         rtl92s_phy_set_bb_reg(hw, phy_table_pg[i],
 909                                         phy_table_pg[i + 1],
 910                                         phy_table_pg[i + 2]);
 911                 }
 912         }
 913
 914         return true;
 915 }
 916
 917 static bool _rtl92s_phy_bb_config_parafile(struct ieee80211_hw *hw)
 918 {
 919         struct rtl_priv *rtlpriv = rtl_priv(hw);
 920         struct rtl_phy *rtlphy = &(rtlpriv->phy);
 921         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
 922         bool rtstatus = true;
 923
 924         /* 1. Read PHY_REG.TXT BB INIT!! */
 925         /* We will separate as 1T1R/1T2R/1T2R_GREEN/2T2R */
 926         if (rtlphy->rf_type == RF_1T2R || rtlphy->rf_type == RF_2T2R ||
 927             rtlphy->rf_type == RF_1T1R || rtlphy->rf_type == RF_2T2R_GREEN) {
 928                 rtstatus = _rtl92s_phy_config_bb(hw, BASEBAND_CONFIG_PHY_REG);
 929
 930                 if (rtlphy->rf_type != RF_2T2R &&
 931                     rtlphy->rf_type != RF_2T2R_GREEN)
 932                         /* so we should reconfig BB reg with the right
 933                          * PHY parameters. */
 934                         rtstatus = _rtl92s_phy_set_bb_to_diff_rf(hw,
 935                                                 BASEBAND_CONFIG_PHY_REG);
 936         } else {
 937                 rtstatus = false;
 938         }
 939
 940         if (!rtstatus) {
 941                 RT_TRACE(rtlpriv, COMP_INIT, DBG_EMERG,
 942                          "Write BB Reg Fail!!\n");
 943                 goto phy_BB8190_Config_ParaFile_Fail;
 944         }
 945
 946         /* 2. If EEPROM or EFUSE autoload OK, We must config by
 947          *    PHY_REG_PG.txt */
 948         if (rtlefuse->autoload_failflag == false) {
 949                 rtlphy->pwrgroup_cnt = 0;
 950
 951                 rtstatus = _rtl92s_phy_config_bb_with_pg(hw,
 952                                                  BASEBAND_CONFIG_PHY_REG);
 953         }
 954         if (!rtstatus) {
 955                 RT_TRACE(rtlpriv, COMP_INIT, DBG_EMERG,
 956                          "_rtl92s_phy_bb_config_parafile(): BB_PG Reg Fail!!\n");
 957                 goto phy_BB8190_Config_ParaFile_Fail;
 958         }
 959
 960         /* 3. BB AGC table Initialization */
 961         rtstatus = _rtl92s_phy_config_bb(hw, BASEBAND_CONFIG_AGC_TAB);
 962
 963         if (!rtstatus) {
 964                 pr_err("%s(): AGC Table Fail\n", __func__);
 965                 goto phy_BB8190_Config_ParaFile_Fail;
 966         }
 967
 968         /* Check if the CCK HighPower is turned ON. */
 969         /* This is used to calculate PWDB. */
 970         rtlphy->cck_high_power = (bool)(rtl92s_phy_query_bb_reg(hw,
 971                         RFPGA0_XA_HSSIPARAMETER2, 0x200));
 972
 973 phy_BB8190_Config_ParaFile_Fail:
 974         return rtstatus;
 975 }
 976
 977 u8 rtl92s_phy_config_rf(struct ieee80211_hw *hw, enum radio_path rfpath)
 978 {
 979         struct rtl_priv *rtlpriv = rtl_priv(hw);
 980         struct rtl_phy *rtlphy = &(rtlpriv->phy);
 981         int i;
 982         bool rtstatus = true;
 983         u32 *radio_a_table;
 984         u32 *radio_b_table;
 985         u16 radio_a_tblen, radio_b_tblen;
 986
 987         radio_a_tblen = RADIOA_1T_ARRAYLENGTH;
 988         radio_a_table = rtl8192seradioa_1t_array;
 989
 990         /* Using Green mode array table for RF_2T2R_GREEN */
 991         if (rtlphy->rf_type == RF_2T2R_GREEN) {
 992                 radio_b_table = rtl8192seradiob_gm_array;
 993                 radio_b_tblen = RADIOB_GM_ARRAYLENGTH;
 994         } else {
 995                 radio_b_table = rtl8192seradiob_array;
 996                 radio_b_tblen = RADIOB_ARRAYLENGTH;
 997         }
 998
 999         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Radio No %x\n", rfpath);
1000         rtstatus = true;
1001
1002         switch (rfpath) {
1003         case RF90_PATH_A:
1004                 for (i = 0; i < radio_a_tblen; i = i + 2) {
1005                         rtl_rfreg_delay(hw, rfpath, radio_a_table[i],
1006                                         MASK20BITS, radio_a_table[i + 1]);
1007
1008                 }
1009
1010                 /* PA Bias current for inferiority IC */
1011                 _rtl92s_phy_config_rfpa_bias_current(hw, rfpath);
1012                 break;
1013         case RF90_PATH_B:
1014                 for (i = 0; i < radio_b_tblen; i = i + 2) {
1015                         rtl_rfreg_delay(hw, rfpath, radio_b_table[i],
1016                                         MASK20BITS, radio_b_table[i + 1]);
1017                 }
1018                 break;
1019         case RF90_PATH_C:
1020                 ;
1021                 break;
1022         case RF90_PATH_D:
1023                 ;
1024                 break;
1025         default:
1026                 break;
1027         }
1028
1029         return rtstatus;
1030 }
1031
1032
1033 bool rtl92s_phy_mac_config(struct ieee80211_hw *hw)
1034 {
1035         struct rtl_priv *rtlpriv = rtl_priv(hw);
1036         u32 i;
1037         u32 arraylength;
1038         u32 *ptraArray;
1039
1040         arraylength = MAC_2T_ARRAYLENGTH;
1041         ptraArray = rtl8192semac_2t_array;
1042
1043         for (i = 0; i < arraylength; i = i + 2)
1044                 rtl_write_byte(rtlpriv, ptraArray[i], (u8)ptraArray[i + 1]);
1045
1046         return true;
1047 }
1048
1049
1050 bool rtl92s_phy_bb_config(struct ieee80211_hw *hw)
1051 {
1052         struct rtl_priv *rtlpriv = rtl_priv(hw);
1053         struct rtl_phy *rtlphy = &(rtlpriv->phy);
1054         bool rtstatus = true;
1055         u8 pathmap, index, rf_num = 0;
1056         u8 path1, path2;
1057
1058         _rtl92s_phy_init_register_definition(hw);
1059
1060         /* Config BB and AGC */
1061         rtstatus = _rtl92s_phy_bb_config_parafile(hw);
1062
1063
1064         /* Check BB/RF confiuration setting. */
1065         /* We only need to configure RF which is turned on. */
1066         path1 = (u8)(rtl92s_phy_query_bb_reg(hw, RFPGA0_TXINFO, 0xf));
1067         mdelay(10);
1068         path2 = (u8)(rtl92s_phy_query_bb_reg(hw, ROFDM0_TRXPATHENABLE, 0xf));
1069         pathmap = path1 | path2;
1070
1071         rtlphy->rf_pathmap = pathmap;
1072         for (index = 0; index < 4; index++) {
1073                 if ((pathmap >> index) & 0x1)
1074                         rf_num++;
1075         }
1076
1077         if ((rtlphy->rf_type == RF_1T1R && rf_num != 1) ||
1078             (rtlphy->rf_type == RF_1T2R && rf_num != 2) ||
1079             (rtlphy->rf_type == RF_2T2R && rf_num != 2) ||
1080             (rtlphy->rf_type == RF_2T2R_GREEN && rf_num != 2)) {
1081                 RT_TRACE(rtlpriv, COMP_INIT, DBG_EMERG,
1082                          "RF_Type(%x) does not match RF_Num(%x)!!\n",
1083                          rtlphy->rf_type, rf_num);
1084                 RT_TRACE(rtlpriv, COMP_INIT, DBG_EMERG,
1085                          "path1 0x%x, path2 0x%x, pathmap 0x%x\n",
1086                          path1, path2, pathmap);
1087         }
1088
1089         return rtstatus;
1090 }
1091
1092 bool rtl92s_phy_rf_config(struct ieee80211_hw *hw)
1093 {
1094         struct rtl_priv *rtlpriv = rtl_priv(hw);
1095         struct rtl_phy *rtlphy = &(rtlpriv->phy);
1096
1097         /* Initialize general global value */
1098         if (rtlphy->rf_type == RF_1T1R)
1099                 rtlphy->num_total_rfpath = 1;
1100         else
1101                 rtlphy->num_total_rfpath = 2;
1102
1103         /* Config BB and RF */
1104         return rtl92s_phy_rf6052_config(hw);
1105 }
1106
1107 void rtl92s_phy_get_hw_reg_originalvalue(struct ieee80211_hw *hw)
1108 {
1109         struct rtl_priv *rtlpriv = rtl_priv(hw);
1110         struct rtl_phy *rtlphy = &(rtlpriv->phy);
1111
1112         /* read rx initial gain */
1113         rtlphy->default_initialgain[0] = rtl_get_bbreg(hw,
1114                         ROFDM0_XAAGCCORE1, MASKBYTE0);
1115         rtlphy->default_initialgain[1] = rtl_get_bbreg(hw,
1116                         ROFDM0_XBAGCCORE1, MASKBYTE0);
1117         rtlphy->default_initialgain[2] = rtl_get_bbreg(hw,
1118                         ROFDM0_XCAGCCORE1, MASKBYTE0);
1119         rtlphy->default_initialgain[3] = rtl_get_bbreg(hw,
1120                         ROFDM0_XDAGCCORE1, MASKBYTE0);
1121         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1122                  "Default initial gain (c50=0x%x, c58=0x%x, c60=0x%x, c68=0x%x)\n",
1123                  rtlphy->default_initialgain[0],
1124                  rtlphy->default_initialgain[1],
1125                  rtlphy->default_initialgain[2],
1126                  rtlphy->default_initialgain[3]);
1127
1128         /* read framesync */
1129         rtlphy->framesync = rtl_get_bbreg(hw, ROFDM0_RXDETECTOR3, MASKBYTE0);
1130         rtlphy->framesync_c34 = rtl_get_bbreg(hw, ROFDM0_RXDETECTOR2,
1131                                               MASKDWORD);
1132         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1133                  "Default framesync (0x%x) = 0x%x\n",
1134                  ROFDM0_RXDETECTOR3, rtlphy->framesync);
1135
1136 }
1137
1138 static void _rtl92s_phy_get_txpower_index(struct ieee80211_hw *hw, u8 channel,
1139                                           u8 *cckpowerlevel, u8 *ofdmpowerLevel)
1140 {
1141         struct rtl_priv *rtlpriv = rtl_priv(hw);
1142         struct rtl_phy *rtlphy = &(rtlpriv->phy);
1143         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1144         u8 index = (channel - 1);
1145
1146         /* 1. CCK */
1147         /* RF-A */
1148         cckpowerlevel[0] = rtlefuse->txpwrlevel_cck[0][index];
1149         /* RF-B */
1150         cckpowerlevel[1] = rtlefuse->txpwrlevel_cck[1][index];
1151
1152         /* 2. OFDM for 1T or 2T */
1153         if (rtlphy->rf_type == RF_1T2R || rtlphy->rf_type == RF_1T1R) {
1154                 /* Read HT 40 OFDM TX power */
1155                 ofdmpowerLevel[0] = rtlefuse->txpwrlevel_ht40_1s[0][index];
1156                 ofdmpowerLevel[1] = rtlefuse->txpwrlevel_ht40_1s[1][index];
1157         } else if (rtlphy->rf_type == RF_2T2R) {
1158                 /* Read HT 40 OFDM TX power */
1159                 ofdmpowerLevel[0] = rtlefuse->txpwrlevel_ht40_2s[0][index];
1160                 ofdmpowerLevel[1] = rtlefuse->txpwrlevel_ht40_2s[1][index];
1161         } else {
1162                 ofdmpowerLevel[0] = 0;
1163                 ofdmpowerLevel[1] = 0;
1164         }
1165 }
1166
1167 static void _rtl92s_phy_ccxpower_indexcheck(struct ieee80211_hw *hw,
1168                 u8 channel, u8 *cckpowerlevel, u8 *ofdmpowerlevel)
1169 {
1170         struct rtl_priv *rtlpriv = rtl_priv(hw);
1171         struct rtl_phy *rtlphy = &(rtlpriv->phy);
1172
1173         rtlphy->cur_cck_txpwridx = cckpowerlevel[0];
1174         rtlphy->cur_ofdm24g_txpwridx = ofdmpowerlevel[0];
1175 }
1176
1177 void rtl92s_phy_set_txpower(struct ieee80211_hw *hw, u8 channel)
1178 {
1179         struct rtl_priv *rtlpriv = rtl_priv(hw);
1180         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1181         /* [0]:RF-A, [1]:RF-B */
1182         u8 cckpowerlevel[2], ofdmpowerLevel[2];
1183
1184         if (!rtlefuse->txpwr_fromeprom)
1185                 return;
1186
1187         /* Mainly we use RF-A Tx Power to write the Tx Power registers,
1188          * but the RF-B Tx Power must be calculated by the antenna diff.
1189          * So we have to rewrite Antenna gain offset register here.
1190          * Please refer to BB register 0x80c
1191          * 1. For CCK.
1192          * 2. For OFDM 1T or 2T */
1193         _rtl92s_phy_get_txpower_index(hw, channel, &cckpowerlevel[0],
1194                         &ofdmpowerLevel[0]);
1195
1196         RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
1197                  "Channel-%d, cckPowerLevel (A / B) = 0x%x / 0x%x, ofdmPowerLevel (A / B) = 0x%x / 0x%x\n",
1198                  channel, cckpowerlevel[0], cckpowerlevel[1],
1199                  ofdmpowerLevel[0], ofdmpowerLevel[1]);
1200
1201         _rtl92s_phy_ccxpower_indexcheck(hw, channel, &cckpowerlevel[0],
1202                         &ofdmpowerLevel[0]);
1203
1204         rtl92s_phy_rf6052_set_ccktxpower(hw, cckpowerlevel[0]);
1205         rtl92s_phy_rf6052_set_ofdmtxpower(hw, &ofdmpowerLevel[0], channel);
1206
1207 }
1208
1209 void rtl92s_phy_chk_fwcmd_iodone(struct ieee80211_hw *hw)
1210 {
1211         struct rtl_priv *rtlpriv = rtl_priv(hw);
1212         u16 pollingcnt = 10000;
1213         u32 tmpvalue;
1214
1215         /* Make sure that CMD IO has be accepted by FW. */
1216         do {
1217                 udelay(10);
1218
1219                 tmpvalue = rtl_read_dword(rtlpriv, WFM5);
1220                 if (tmpvalue == 0)
1221                         break;
1222         } while (--pollingcnt);
1223
1224         if (pollingcnt == 0)
1225                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "Set FW Cmd fail!!\n");
1226 }
1227
1228
1229 static void _rtl92s_phy_set_fwcmd_io(struct ieee80211_hw *hw)
1230 {
1231         struct rtl_priv *rtlpriv = rtl_priv(hw);
1232         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1233         struct rtl_phy *rtlphy = &(rtlpriv->phy);
1234         u32 input, current_aid = 0;
1235
1236         if (is_hal_stop(rtlhal))
1237                 return;
1238
1239         if (hal_get_firmwareversion(rtlpriv) < 0x34)
1240                 goto skip;
1241         /* We re-map RA related CMD IO to combinational ones */
1242         /* if FW version is v.52 or later. */
1243         switch (rtlhal->current_fwcmd_io) {
1244         case FW_CMD_RA_REFRESH_N:
1245                 rtlhal->current_fwcmd_io = FW_CMD_RA_REFRESH_N_COMB;
1246                 break;
1247         case FW_CMD_RA_REFRESH_BG:
1248                 rtlhal->current_fwcmd_io = FW_CMD_RA_REFRESH_BG_COMB;
1249                 break;
1250         default:
1251                 break;
1252         }
1253
1254 skip:
1255         switch (rtlhal->current_fwcmd_io) {
1256         case FW_CMD_RA_RESET:
1257                 RT_TRACE(rtlpriv, COMP_CMD, DBG_DMESG, "FW_CMD_RA_RESET\n");
1258                 rtl_write_dword(rtlpriv, WFM5, FW_RA_RESET);
1259                 rtl92s_phy_chk_fwcmd_iodone(hw);
1260                 break;
1261         case FW_CMD_RA_ACTIVE:
1262                 RT_TRACE(rtlpriv, COMP_CMD, DBG_DMESG, "FW_CMD_RA_ACTIVE\n");
1263                 rtl_write_dword(rtlpriv, WFM5, FW_RA_ACTIVE);
1264                 rtl92s_phy_chk_fwcmd_iodone(hw);
1265                 break;
1266         case FW_CMD_RA_REFRESH_N:
1267                 RT_TRACE(rtlpriv, COMP_CMD, DBG_DMESG, "FW_CMD_RA_REFRESH_N\n");
1268                 input = FW_RA_REFRESH;
1269                 rtl_write_dword(rtlpriv, WFM5, input);
1270                 rtl92s_phy_chk_fwcmd_iodone(hw);
1271                 rtl_write_dword(rtlpriv, WFM5, FW_RA_ENABLE_RSSI_MASK);
1272                 rtl92s_phy_chk_fwcmd_iodone(hw);
1273                 break;
1274         case FW_CMD_RA_REFRESH_BG:
1275                 RT_TRACE(rtlpriv, COMP_CMD, DBG_DMESG,
1276                          "FW_CMD_RA_REFRESH_BG\n");
1277                 rtl_write_dword(rtlpriv, WFM5, FW_RA_REFRESH);
1278                 rtl92s_phy_chk_fwcmd_iodone(hw);
1279                 rtl_write_dword(rtlpriv, WFM5, FW_RA_DISABLE_RSSI_MASK);
1280                 rtl92s_phy_chk_fwcmd_iodone(hw);
1281                 break;
1282         case FW_CMD_RA_REFRESH_N_COMB:
1283                 RT_TRACE(rtlpriv, COMP_CMD, DBG_DMESG,
1284                          "FW_CMD_RA_REFRESH_N_COMB\n");
1285                 input = FW_RA_IOT_N_COMB;
1286                 rtl_write_dword(rtlpriv, WFM5, input);
1287                 rtl92s_phy_chk_fwcmd_iodone(hw);
1288                 break;
1289         case FW_CMD_RA_REFRESH_BG_COMB:
1290                 RT_TRACE(rtlpriv, COMP_CMD, DBG_DMESG,
1291                          "FW_CMD_RA_REFRESH_BG_COMB\n");
1292                 input = FW_RA_IOT_BG_COMB;
1293                 rtl_write_dword(rtlpriv, WFM5, input);
1294                 rtl92s_phy_chk_fwcmd_iodone(hw);
1295                 break;
1296         case FW_CMD_IQK_ENABLE:
1297                 RT_TRACE(rtlpriv, COMP_CMD, DBG_DMESG, "FW_CMD_IQK_ENABLE\n");
1298                 rtl_write_dword(rtlpriv, WFM5, FW_IQK_ENABLE);
1299                 rtl92s_phy_chk_fwcmd_iodone(hw);
1300                 break;
1301         case FW_CMD_PAUSE_DM_BY_SCAN:
1302                 /* Lower initial gain */
1303                 rtl_set_bbreg(hw, ROFDM0_XAAGCCORE1, MASKBYTE0, 0x17);
1304                 rtl_set_bbreg(hw, ROFDM0_XBAGCCORE1, MASKBYTE0, 0x17);
1305                 /* CCA threshold */
1306                 rtl_set_bbreg(hw, RCCK0_CCA, MASKBYTE2, 0x40);
1307                 break;
1308         case FW_CMD_RESUME_DM_BY_SCAN:
1309                 /* CCA threshold */
1310                 rtl_set_bbreg(hw, RCCK0_CCA, MASKBYTE2, 0xcd);
1311                 rtl92s_phy_set_txpower(hw, rtlphy->current_channel);
1312                 break;
1313         case FW_CMD_HIGH_PWR_DISABLE:
1314                 if (rtlpriv->dm.dm_flag & HAL_DM_HIPWR_DISABLE)
1315                         break;
1316
1317                 /* Lower initial gain */
1318                 rtl_set_bbreg(hw, ROFDM0_XAAGCCORE1, MASKBYTE0, 0x17);
1319                 rtl_set_bbreg(hw, ROFDM0_XBAGCCORE1, MASKBYTE0, 0x17);
1320                 /* CCA threshold */
1321                 rtl_set_bbreg(hw, RCCK0_CCA, MASKBYTE2, 0x40);
1322                 break;
1323         case FW_CMD_HIGH_PWR_ENABLE:
1324                 if ((rtlpriv->dm.dm_flag & HAL_DM_HIPWR_DISABLE) ||
1325                         rtlpriv->dm.dynamic_txpower_enable)
1326                         break;
1327
1328                 /* CCA threshold */
1329                 rtl_set_bbreg(hw, RCCK0_CCA, MASKBYTE2, 0xcd);
1330                 break;
1331         case FW_CMD_LPS_ENTER:
1332                 RT_TRACE(rtlpriv, COMP_CMD, DBG_DMESG, "FW_CMD_LPS_ENTER\n");
1333                 current_aid = rtlpriv->mac80211.assoc_id;
1334                 rtl_write_dword(rtlpriv, WFM5, (FW_LPS_ENTER |
1335                                 ((current_aid | 0xc000) << 8)));
1336                 rtl92s_phy_chk_fwcmd_iodone(hw);
1337                 /* FW set TXOP disable here, so disable EDCA
1338                  * turbo mode until driver leave LPS */
1339                 break;
1340         case FW_CMD_LPS_LEAVE:
1341                 RT_TRACE(rtlpriv, COMP_CMD, DBG_DMESG, "FW_CMD_LPS_LEAVE\n");
1342                 rtl_write_dword(rtlpriv, WFM5, FW_LPS_LEAVE);
1343                 rtl92s_phy_chk_fwcmd_iodone(hw);
1344                 break;
1345         case FW_CMD_ADD_A2_ENTRY:
1346                 RT_TRACE(rtlpriv, COMP_CMD, DBG_DMESG, "FW_CMD_ADD_A2_ENTRY\n");
1347                 rtl_write_dword(rtlpriv, WFM5, FW_ADD_A2_ENTRY);
1348                 rtl92s_phy_chk_fwcmd_iodone(hw);
1349                 break;
1350         case FW_CMD_CTRL_DM_BY_DRIVER:
1351                 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD,
1352                          "FW_CMD_CTRL_DM_BY_DRIVER\n");
1353                 rtl_write_dword(rtlpriv, WFM5, FW_CTRL_DM_BY_DRIVER);
1354                 rtl92s_phy_chk_fwcmd_iodone(hw);
1355                 break;
1356
1357         default:
1358                 break;
1359         }
1360
1361         rtl92s_phy_chk_fwcmd_iodone(hw);
1362
1363         /* Clear FW CMD operation flag. */
1364         rtlhal->set_fwcmd_inprogress = false;
1365 }
1366
1367 bool rtl92s_phy_set_fw_cmd(struct ieee80211_hw *hw, enum fwcmd_iotype fw_cmdio)
1368 {
1369         struct rtl_priv *rtlpriv = rtl_priv(hw);
1370         struct dig_t *digtable = &rtlpriv->dm_digtable;
1371         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1372         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1373         u32     fw_param = FW_CMD_IO_PARA_QUERY(rtlpriv);
1374         u16     fw_cmdmap = FW_CMD_IO_QUERY(rtlpriv);
1375         bool postprocessing = false;
1376
1377         RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD,
1378                  "Set FW Cmd(%#x), set_fwcmd_inprogress(%d)\n",
1379                  fw_cmdio, rtlhal->set_fwcmd_inprogress);
1380
1381         do {
1382                 /* We re-map to combined FW CMD ones if firmware version */
1383                 /* is v.53 or later. */
1384                 if (hal_get_firmwareversion(rtlpriv) >= 0x35) {
1385                         switch (fw_cmdio) {
1386                         case FW_CMD_RA_REFRESH_N:
1387                                 fw_cmdio = FW_CMD_RA_REFRESH_N_COMB;
1388                                 break;
1389                         case FW_CMD_RA_REFRESH_BG:
1390                                 fw_cmdio = FW_CMD_RA_REFRESH_BG_COMB;
1391                                 break;
1392                         default:
1393                                 break;
1394                         }
1395                 } else {
1396                         if ((fw_cmdio == FW_CMD_IQK_ENABLE) ||
1397                             (fw_cmdio == FW_CMD_RA_REFRESH_N) ||
1398                             (fw_cmdio == FW_CMD_RA_REFRESH_BG)) {
1399                                 postprocessing = true;
1400                                 break;
1401                         }
1402                 }
1403
1404                 /* If firmware version is v.62 or later,
1405                  * use FW_CMD_IO_SET for FW_CMD_CTRL_DM_BY_DRIVER */
1406                 if (hal_get_firmwareversion(rtlpriv) >= 0x3E) {
1407                         if (fw_cmdio == FW_CMD_CTRL_DM_BY_DRIVER)
1408                                 fw_cmdio = FW_CMD_CTRL_DM_BY_DRIVER_NEW;
1409                 }
1410
1411
1412                 /* We shall revise all FW Cmd IO into Reg0x364
1413                  * DM map table in the future. */
1414                 switch (fw_cmdio) {
1415                 case FW_CMD_RA_INIT:
1416                         RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, "RA init!!\n");
1417                         fw_cmdmap |= FW_RA_INIT_CTL;
1418                         FW_CMD_IO_SET(rtlpriv, fw_cmdmap);
1419                         /* Clear control flag to sync with FW. */
1420                         FW_CMD_IO_CLR(rtlpriv, FW_RA_INIT_CTL);
1421                         break;
1422                 case FW_CMD_DIG_DISABLE:
1423                         RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD,
1424                                  "Set DIG disable!!\n");
1425                         fw_cmdmap &= ~FW_DIG_ENABLE_CTL;
1426                         FW_CMD_IO_SET(rtlpriv, fw_cmdmap);
1427                         break;
1428                 case FW_CMD_DIG_ENABLE:
1429                 case FW_CMD_DIG_RESUME:
1430                         if (!(rtlpriv->dm.dm_flag & HAL_DM_DIG_DISABLE)) {
1431                                 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD,
1432                                          "Set DIG enable or resume!!\n");
1433                                 fw_cmdmap |= (FW_DIG_ENABLE_CTL | FW_SS_CTL);
1434                                 FW_CMD_IO_SET(rtlpriv, fw_cmdmap);
1435                         }
1436                         break;
1437                 case FW_CMD_DIG_HALT:
1438                         RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD,
1439                                  "Set DIG halt!!\n");
1440                         fw_cmdmap &= ~(FW_DIG_ENABLE_CTL | FW_SS_CTL);
1441                         FW_CMD_IO_SET(rtlpriv, fw_cmdmap);
1442                         break;
1443                 case FW_CMD_TXPWR_TRACK_THERMAL: {
1444                         u8      thermalval = 0;
1445                         fw_cmdmap |= FW_PWR_TRK_CTL;
1446
1447                         /* Clear FW parameter in terms of thermal parts. */
1448                         fw_param &= FW_PWR_TRK_PARAM_CLR;
1449
1450                         thermalval = rtlpriv->dm.thermalvalue;
1451                         fw_param |= ((thermalval << 24) |
1452                                      (rtlefuse->thermalmeter[0] << 16));
1453
1454                         RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD,
1455                                  "Set TxPwr tracking!! FwCmdMap(%#x), FwParam(%#x)\n",
1456                                  fw_cmdmap, fw_param);
1457
1458                         FW_CMD_PARA_SET(rtlpriv, fw_param);
1459                         FW_CMD_IO_SET(rtlpriv, fw_cmdmap);
1460
1461                         /* Clear control flag to sync with FW. */
1462                         FW_CMD_IO_CLR(rtlpriv, FW_PWR_TRK_CTL);
1463                         }
1464                         break;
1465                 /* The following FW CMDs are only compatible to
1466                  * v.53 or later. */
1467                 case FW_CMD_RA_REFRESH_N_COMB:
1468                         fw_cmdmap |= FW_RA_N_CTL;
1469
1470                         /* Clear RA BG mode control. */
1471                         fw_cmdmap &= ~(FW_RA_BG_CTL | FW_RA_INIT_CTL);
1472
1473                         /* Clear FW parameter in terms of RA parts. */
1474                         fw_param &= FW_RA_PARAM_CLR;
1475
1476                         RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD,
1477                                  "[FW CMD] [New Version] Set RA/IOT Comb in n mode!! FwCmdMap(%#x), FwParam(%#x)\n",
1478                                  fw_cmdmap, fw_param);
1479
1480                         FW_CMD_PARA_SET(rtlpriv, fw_param);
1481                         FW_CMD_IO_SET(rtlpriv, fw_cmdmap);
1482
1483                         /* Clear control flag to sync with FW. */
1484                         FW_CMD_IO_CLR(rtlpriv, FW_RA_N_CTL);
1485                         break;
1486                 case FW_CMD_RA_REFRESH_BG_COMB:
1487                         fw_cmdmap |= FW_RA_BG_CTL;
1488
1489                         /* Clear RA n-mode control. */
1490                         fw_cmdmap &= ~(FW_RA_N_CTL | FW_RA_INIT_CTL);
1491                         /* Clear FW parameter in terms of RA parts. */
1492                         fw_param &= FW_RA_PARAM_CLR;
1493
1494                         FW_CMD_PARA_SET(rtlpriv, fw_param);
1495                         FW_CMD_IO_SET(rtlpriv, fw_cmdmap);
1496
1497                         /* Clear control flag to sync with FW. */
1498                         FW_CMD_IO_CLR(rtlpriv, FW_RA_BG_CTL);
1499                         break;
1500                 case FW_CMD_IQK_ENABLE:
1501                         fw_cmdmap |= FW_IQK_CTL;
1502                         FW_CMD_IO_SET(rtlpriv, fw_cmdmap);
1503                         /* Clear control flag to sync with FW. */
1504                         FW_CMD_IO_CLR(rtlpriv, FW_IQK_CTL);
1505                         break;
1506                 /* The following FW CMD is compatible to v.62 or later.  */
1507                 case FW_CMD_CTRL_DM_BY_DRIVER_NEW:
1508                         fw_cmdmap |= FW_DRIVER_CTRL_DM_CTL;
1509                         FW_CMD_IO_SET(rtlpriv, fw_cmdmap);
1510                         break;
1511                 /*  The followed FW Cmds needs post-processing later. */
1512                 case FW_CMD_RESUME_DM_BY_SCAN:
1513                         fw_cmdmap |= (FW_DIG_ENABLE_CTL |
1514                                       FW_HIGH_PWR_ENABLE_CTL |
1515                                       FW_SS_CTL);
1516
1517                         if (rtlpriv->dm.dm_flag & HAL_DM_DIG_DISABLE ||
1518                                 !digtable->dig_enable_flag)
1519                                 fw_cmdmap &= ~FW_DIG_ENABLE_CTL;
1520
1521                         if ((rtlpriv->dm.dm_flag & HAL_DM_HIPWR_DISABLE) ||
1522                             rtlpriv->dm.dynamic_txpower_enable)
1523                                 fw_cmdmap &= ~FW_HIGH_PWR_ENABLE_CTL;
1524
1525                         if ((digtable->dig_ext_port_stage ==
1526                             DIG_EXT_PORT_STAGE_0) ||
1527                             (digtable->dig_ext_port_stage ==
1528                             DIG_EXT_PORT_STAGE_1))
1529                                 fw_cmdmap &= ~FW_DIG_ENABLE_CTL;
1530
1531                         FW_CMD_IO_SET(rtlpriv, fw_cmdmap);
1532                         postprocessing = true;
1533                         break;
1534                 case FW_CMD_PAUSE_DM_BY_SCAN:
1535                         fw_cmdmap &= ~(FW_DIG_ENABLE_CTL |
1536                                        FW_HIGH_PWR_ENABLE_CTL |
1537                                        FW_SS_CTL);
1538                         FW_CMD_IO_SET(rtlpriv, fw_cmdmap);
1539                         postprocessing = true;
1540                         break;
1541                 case FW_CMD_HIGH_PWR_DISABLE:
1542                         fw_cmdmap &= ~FW_HIGH_PWR_ENABLE_CTL;
1543                         FW_CMD_IO_SET(rtlpriv, fw_cmdmap);
1544                         postprocessing = true;
1545                         break;
1546                 case FW_CMD_HIGH_PWR_ENABLE:
1547                         if (!(rtlpriv->dm.dm_flag & HAL_DM_HIPWR_DISABLE) &&
1548                             !rtlpriv->dm.dynamic_txpower_enable) {
1549                                 fw_cmdmap |= (FW_HIGH_PWR_ENABLE_CTL |
1550                                               FW_SS_CTL);
1551                                 FW_CMD_IO_SET(rtlpriv, fw_cmdmap);
1552                                 postprocessing = true;
1553                         }
1554                         break;
1555                 case FW_CMD_DIG_MODE_FA:
1556                         fw_cmdmap |= FW_FA_CTL;
1557                         FW_CMD_IO_SET(rtlpriv, fw_cmdmap);
1558                         break;
1559                 case FW_CMD_DIG_MODE_SS:
1560                         fw_cmdmap &= ~FW_FA_CTL;
1561                         FW_CMD_IO_SET(rtlpriv, fw_cmdmap);
1562                         break;
1563                 case FW_CMD_PAPE_CONTROL:
1564                         RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD,
1565                                  "[FW CMD] Set PAPE Control\n");
1566                         fw_cmdmap &= ~FW_PAPE_CTL_BY_SW_HW;
1567
1568                         FW_CMD_IO_SET(rtlpriv, fw_cmdmap);
1569                         break;
1570                 default:
1571                         /* Pass to original FW CMD processing callback
1572                          * routine. */
1573                         postprocessing = true;
1574                         break;
1575                 }
1576         } while (false);
1577
1578         /* We shall post processing these FW CMD if
1579          * variable postprocessing is set.
1580          */
1581         if (postprocessing && !rtlhal->set_fwcmd_inprogress) {
1582                 rtlhal->set_fwcmd_inprogress = true;
1583                 /* Update current FW Cmd for callback use. */
1584                 rtlhal->current_fwcmd_io = fw_cmdio;
1585         } else {
1586                 return false;
1587         }
1588
1589         _rtl92s_phy_set_fwcmd_io(hw);
1590         return true;
1591 }
1592
1593 static  void _rtl92s_phy_check_ephy_switchready(struct ieee80211_hw *hw)
1594 {
1595         struct rtl_priv *rtlpriv = rtl_priv(hw);
1596         u32     delay = 100;
1597         u8      regu1;
1598
1599         regu1 = rtl_read_byte(rtlpriv, 0x554);
1600         while ((regu1 & BIT(5)) && (delay > 0)) {
1601                 regu1 = rtl_read_byte(rtlpriv, 0x554);
1602                 delay--;
1603                 /* We delay only 50us to prevent
1604                  * being scheduled out. */
1605                 udelay(50);
1606         }
1607 }
1608
1609 void rtl92s_phy_switch_ephy_parameter(struct ieee80211_hw *hw)
1610 {
1611         struct rtl_priv *rtlpriv = rtl_priv(hw);
1612         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1613
1614         /* The way to be capable to switch clock request
1615          * when the PG setting does not support clock request.
1616          * This is the backdoor solution to switch clock
1617          * request before ASPM or D3. */
1618         rtl_write_dword(rtlpriv, 0x540, 0x73c11);
1619         rtl_write_dword(rtlpriv, 0x548, 0x2407c);
1620
1621         /* Switch EPHY parameter!!!! */
1622         rtl_write_word(rtlpriv, 0x550, 0x1000);
1623         rtl_write_byte(rtlpriv, 0x554, 0x20);
1624         _rtl92s_phy_check_ephy_switchready(hw);
1625
1626         rtl_write_word(rtlpriv, 0x550, 0xa0eb);
1627         rtl_write_byte(rtlpriv, 0x554, 0x3e);
1628         _rtl92s_phy_check_ephy_switchready(hw);
1629
1630         rtl_write_word(rtlpriv, 0x550, 0xff80);
1631         rtl_write_byte(rtlpriv, 0x554, 0x39);
1632         _rtl92s_phy_check_ephy_switchready(hw);
1633
1634         /* Delay L1 enter time */
1635         if (ppsc->support_aspm && !ppsc->support_backdoor)
1636                 rtl_write_byte(rtlpriv, 0x560, 0x40);
1637         else
1638                 rtl_write_byte(rtlpriv, 0x560, 0x00);
1639
1640 }
1641
1642 void rtl92s_phy_set_beacon_hwreg(struct ieee80211_hw *hw, u16 beaconinterval)
1643 {
1644         struct rtl_priv *rtlpriv = rtl_priv(hw);
1645         u32 new_bcn_num = 0;
1646
1647         if (hal_get_firmwareversion(rtlpriv) >= 0x33) {
1648                 /* Fw v.51 and later. */
1649                 rtl_write_dword(rtlpriv, WFM5, 0xF1000000 |
1650                                 (beaconinterval << 8));
1651         } else {
1652                 new_bcn_num = beaconinterval * 32 - 64;
1653                 rtl_write_dword(rtlpriv, WFM3 + 4, new_bcn_num);
1654                 rtl_write_dword(rtlpriv, WFM3, 0xB026007C);
1655         }
1656 }