1 /******************************************************************************
3 * Copyright(c) 2009-2012 Realtek Corporation.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
26 * Larry Finger <Larry.Finger@lwfinger.net>
28 *****************************************************************************/
43 static u32 _rtl92s_phy_calculate_bit_shift(u32 bitmask)
47 for (i = 0; i <= 31; i++) {
48 if (((bitmask >> i) & 0x1) == 1)
55 u32 rtl92s_phy_query_bb_reg(struct ieee80211_hw *hw, u32 regaddr, u32 bitmask)
57 struct rtl_priv *rtlpriv = rtl_priv(hw);
58 u32 returnvalue = 0, originalvalue, bitshift;
60 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, "regaddr(%#x), bitmask(%#x)\n",
63 originalvalue = rtl_read_dword(rtlpriv, regaddr);
64 bitshift = _rtl92s_phy_calculate_bit_shift(bitmask);
65 returnvalue = (originalvalue & bitmask) >> bitshift;
67 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, "BBR MASK=0x%x Addr[0x%x]=0x%x\n",
68 bitmask, regaddr, originalvalue);
74 void rtl92s_phy_set_bb_reg(struct ieee80211_hw *hw, u32 regaddr, u32 bitmask,
77 struct rtl_priv *rtlpriv = rtl_priv(hw);
78 u32 originalvalue, bitshift;
80 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
81 "regaddr(%#x), bitmask(%#x), data(%#x)\n",
82 regaddr, bitmask, data);
84 if (bitmask != MASKDWORD) {
85 originalvalue = rtl_read_dword(rtlpriv, regaddr);
86 bitshift = _rtl92s_phy_calculate_bit_shift(bitmask);
87 data = ((originalvalue & (~bitmask)) | (data << bitshift));
90 rtl_write_dword(rtlpriv, regaddr, data);
92 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
93 "regaddr(%#x), bitmask(%#x), data(%#x)\n",
94 regaddr, bitmask, data);
98 static u32 _rtl92s_phy_rf_serial_read(struct ieee80211_hw *hw,
99 enum radio_path rfpath, u32 offset)
102 struct rtl_priv *rtlpriv = rtl_priv(hw);
103 struct rtl_phy *rtlphy = &(rtlpriv->phy);
104 struct bb_reg_def *pphyreg = &rtlphy->phyreg_def[rfpath];
106 u32 tmplong, tmplong2;
113 tmplong = rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD);
115 if (rfpath == RF90_PATH_A)
118 tmplong2 = rtl_get_bbreg(hw, pphyreg->rfhssi_para2, MASKDWORD);
120 tmplong2 = (tmplong2 & (~BLSSI_READADDRESS)) | (newoffset << 23) |
123 rtl_set_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD,
124 tmplong & (~BLSSI_READEDGE));
128 rtl_set_bbreg(hw, pphyreg->rfhssi_para2, MASKDWORD, tmplong2);
131 rtl_set_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD, tmplong |
135 if (rfpath == RF90_PATH_A)
136 rfpi_enable = (u8)rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER1,
138 else if (rfpath == RF90_PATH_B)
139 rfpi_enable = (u8)rtl_get_bbreg(hw, RFPGA0_XB_HSSIPARAMETER1,
143 retvalue = rtl_get_bbreg(hw, pphyreg->rf_rbpi,
144 BLSSI_READBACK_DATA);
146 retvalue = rtl_get_bbreg(hw, pphyreg->rf_rb,
147 BLSSI_READBACK_DATA);
149 retvalue = rtl_get_bbreg(hw, pphyreg->rf_rb,
150 BLSSI_READBACK_DATA);
152 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, "RFR-%d Addr[0x%x]=0x%x\n",
153 rfpath, pphyreg->rf_rb, retvalue);
159 static void _rtl92s_phy_rf_serial_write(struct ieee80211_hw *hw,
160 enum radio_path rfpath, u32 offset,
163 struct rtl_priv *rtlpriv = rtl_priv(hw);
164 struct rtl_phy *rtlphy = &(rtlpriv->phy);
165 struct bb_reg_def *pphyreg = &rtlphy->phyreg_def[rfpath];
166 u32 data_and_addr = 0;
172 data_and_addr = ((newoffset << 20) | (data & 0x000fffff)) & 0x0fffffff;
173 rtl_set_bbreg(hw, pphyreg->rf3wire_offset, MASKDWORD, data_and_addr);
175 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, "RFW-%d Addr[0x%x]=0x%x\n",
176 rfpath, pphyreg->rf3wire_offset, data_and_addr);
180 u32 rtl92s_phy_query_rf_reg(struct ieee80211_hw *hw, enum radio_path rfpath,
181 u32 regaddr, u32 bitmask)
183 struct rtl_priv *rtlpriv = rtl_priv(hw);
184 u32 original_value, readback_value, bitshift;
186 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
187 "regaddr(%#x), rfpath(%#x), bitmask(%#x)\n",
188 regaddr, rfpath, bitmask);
190 spin_lock(&rtlpriv->locks.rf_lock);
192 original_value = _rtl92s_phy_rf_serial_read(hw, rfpath, regaddr);
194 bitshift = _rtl92s_phy_calculate_bit_shift(bitmask);
195 readback_value = (original_value & bitmask) >> bitshift;
197 spin_unlock(&rtlpriv->locks.rf_lock);
199 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
200 "regaddr(%#x), rfpath(%#x), bitmask(%#x), original_value(%#x)\n",
201 regaddr, rfpath, bitmask, original_value);
203 return readback_value;
206 void rtl92s_phy_set_rf_reg(struct ieee80211_hw *hw, enum radio_path rfpath,
207 u32 regaddr, u32 bitmask, u32 data)
209 struct rtl_priv *rtlpriv = rtl_priv(hw);
210 struct rtl_phy *rtlphy = &(rtlpriv->phy);
211 u32 original_value, bitshift;
213 if (!((rtlphy->rf_pathmap >> rfpath) & 0x1))
216 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
217 "regaddr(%#x), bitmask(%#x), data(%#x), rfpath(%#x)\n",
218 regaddr, bitmask, data, rfpath);
220 spin_lock(&rtlpriv->locks.rf_lock);
222 if (bitmask != RFREG_OFFSET_MASK) {
223 original_value = _rtl92s_phy_rf_serial_read(hw, rfpath,
225 bitshift = _rtl92s_phy_calculate_bit_shift(bitmask);
226 data = ((original_value & (~bitmask)) | (data << bitshift));
229 _rtl92s_phy_rf_serial_write(hw, rfpath, regaddr, data);
231 spin_unlock(&rtlpriv->locks.rf_lock);
233 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
234 "regaddr(%#x), bitmask(%#x), data(%#x), rfpath(%#x)\n",
235 regaddr, bitmask, data, rfpath);
239 void rtl92s_phy_scan_operation_backup(struct ieee80211_hw *hw,
242 struct rtl_priv *rtlpriv = rtl_priv(hw);
243 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
245 if (!is_hal_stop(rtlhal)) {
247 case SCAN_OPT_BACKUP:
248 rtl92s_phy_set_fw_cmd(hw, FW_CMD_PAUSE_DM_BY_SCAN);
250 case SCAN_OPT_RESTORE:
251 rtl92s_phy_set_fw_cmd(hw, FW_CMD_RESUME_DM_BY_SCAN);
254 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
255 "Unknown operation\n");
261 void rtl92s_phy_set_bw_mode(struct ieee80211_hw *hw,
262 enum nl80211_channel_type ch_type)
264 struct rtl_priv *rtlpriv = rtl_priv(hw);
265 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
266 struct rtl_phy *rtlphy = &(rtlpriv->phy);
267 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
270 RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE, "Switch to %s bandwidth\n",
271 rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20 ?
274 if (rtlphy->set_bwmode_inprogress)
276 if (is_hal_stop(rtlhal))
279 rtlphy->set_bwmode_inprogress = true;
281 reg_bw_opmode = rtl_read_byte(rtlpriv, BW_OPMODE);
283 rtl_read_byte(rtlpriv, RRSR + 2);
285 switch (rtlphy->current_chan_bw) {
286 case HT_CHANNEL_WIDTH_20:
287 reg_bw_opmode |= BW_OPMODE_20MHZ;
288 rtl_write_byte(rtlpriv, BW_OPMODE, reg_bw_opmode);
290 case HT_CHANNEL_WIDTH_20_40:
291 reg_bw_opmode &= ~BW_OPMODE_20MHZ;
292 rtl_write_byte(rtlpriv, BW_OPMODE, reg_bw_opmode);
295 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
296 "unknown bandwidth: %#X\n", rtlphy->current_chan_bw);
300 switch (rtlphy->current_chan_bw) {
301 case HT_CHANNEL_WIDTH_20:
302 rtl_set_bbreg(hw, RFPGA0_RFMOD, BRFMOD, 0x0);
303 rtl_set_bbreg(hw, RFPGA1_RFMOD, BRFMOD, 0x0);
305 if (rtlhal->version >= VERSION_8192S_BCUT)
306 rtl_write_byte(rtlpriv, RFPGA0_ANALOGPARAMETER2, 0x58);
308 case HT_CHANNEL_WIDTH_20_40:
309 rtl_set_bbreg(hw, RFPGA0_RFMOD, BRFMOD, 0x1);
310 rtl_set_bbreg(hw, RFPGA1_RFMOD, BRFMOD, 0x1);
312 rtl_set_bbreg(hw, RCCK0_SYSTEM, BCCK_SIDEBAND,
313 (mac->cur_40_prime_sc >> 1));
314 rtl_set_bbreg(hw, ROFDM1_LSTF, 0xC00, mac->cur_40_prime_sc);
316 if (rtlhal->version >= VERSION_8192S_BCUT)
317 rtl_write_byte(rtlpriv, RFPGA0_ANALOGPARAMETER2, 0x18);
320 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
321 "unknown bandwidth: %#X\n", rtlphy->current_chan_bw);
325 rtl92s_phy_rf6052_set_bandwidth(hw, rtlphy->current_chan_bw);
326 rtlphy->set_bwmode_inprogress = false;
327 RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE, "<==\n");
330 static bool _rtl92s_phy_set_sw_chnl_cmdarray(struct swchnlcmd *cmdtable,
331 u32 cmdtableidx, u32 cmdtablesz, enum swchnlcmd_id cmdid,
332 u32 para1, u32 para2, u32 msdelay)
334 struct swchnlcmd *pcmd;
336 if (cmdtable == NULL) {
337 RT_ASSERT(false, "cmdtable cannot be NULL\n");
341 if (cmdtableidx >= cmdtablesz)
344 pcmd = cmdtable + cmdtableidx;
348 pcmd->msdelay = msdelay;
353 static bool _rtl92s_phy_sw_chnl_step_by_step(struct ieee80211_hw *hw,
354 u8 channel, u8 *stage, u8 *step, u32 *delay)
356 struct rtl_priv *rtlpriv = rtl_priv(hw);
357 struct rtl_phy *rtlphy = &(rtlpriv->phy);
358 struct swchnlcmd precommoncmd[MAX_PRECMD_CNT];
360 struct swchnlcmd postcommoncmd[MAX_POSTCMD_CNT];
361 u32 postcommoncmdcnt;
362 struct swchnlcmd rfdependcmd[MAX_RFDEPENDCMD_CNT];
364 struct swchnlcmd *currentcmd = NULL;
366 u8 num_total_rfpath = rtlphy->num_total_rfpath;
369 _rtl92s_phy_set_sw_chnl_cmdarray(precommoncmd, precommoncmdcnt++,
370 MAX_PRECMD_CNT, CMDID_SET_TXPOWEROWER_LEVEL, 0, 0, 0);
371 _rtl92s_phy_set_sw_chnl_cmdarray(precommoncmd, precommoncmdcnt++,
372 MAX_PRECMD_CNT, CMDID_END, 0, 0, 0);
374 postcommoncmdcnt = 0;
376 _rtl92s_phy_set_sw_chnl_cmdarray(postcommoncmd, postcommoncmdcnt++,
377 MAX_POSTCMD_CNT, CMDID_END, 0, 0, 0);
381 RT_ASSERT((channel >= 1 && channel <= 14),
382 "invalid channel for Zebra: %d\n", channel);
384 _rtl92s_phy_set_sw_chnl_cmdarray(rfdependcmd, rfdependcmdcnt++,
385 MAX_RFDEPENDCMD_CNT, CMDID_RF_WRITEREG,
386 RF_CHNLBW, channel, 10);
388 _rtl92s_phy_set_sw_chnl_cmdarray(rfdependcmd, rfdependcmdcnt++,
389 MAX_RFDEPENDCMD_CNT, CMDID_END, 0, 0, 0);
394 currentcmd = &precommoncmd[*step];
397 currentcmd = &rfdependcmd[*step];
400 currentcmd = &postcommoncmd[*step];
404 if (currentcmd->cmdid == CMDID_END) {
414 switch (currentcmd->cmdid) {
415 case CMDID_SET_TXPOWEROWER_LEVEL:
416 rtl92s_phy_set_txpower(hw, channel);
418 case CMDID_WRITEPORT_ULONG:
419 rtl_write_dword(rtlpriv, currentcmd->para1,
422 case CMDID_WRITEPORT_USHORT:
423 rtl_write_word(rtlpriv, currentcmd->para1,
424 (u16)currentcmd->para2);
426 case CMDID_WRITEPORT_UCHAR:
427 rtl_write_byte(rtlpriv, currentcmd->para1,
428 (u8)currentcmd->para2);
430 case CMDID_RF_WRITEREG:
431 for (rfpath = 0; rfpath < num_total_rfpath; rfpath++) {
432 rtlphy->rfreg_chnlval[rfpath] =
433 ((rtlphy->rfreg_chnlval[rfpath] &
434 0xfffffc00) | currentcmd->para2);
435 rtl_set_rfreg(hw, (enum radio_path)rfpath,
438 rtlphy->rfreg_chnlval[rfpath]);
442 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
443 "switch case not processed\n");
450 (*delay) = currentcmd->msdelay;
455 u8 rtl92s_phy_sw_chnl(struct ieee80211_hw *hw)
457 struct rtl_priv *rtlpriv = rtl_priv(hw);
458 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
459 struct rtl_phy *rtlphy = &(rtlpriv->phy);
463 RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE, "switch to channel%d\n",
464 rtlphy->current_channel);
466 if (rtlphy->sw_chnl_inprogress)
469 if (rtlphy->set_bwmode_inprogress)
472 if (is_hal_stop(rtlhal))
475 rtlphy->sw_chnl_inprogress = true;
476 rtlphy->sw_chnl_stage = 0;
477 rtlphy->sw_chnl_step = 0;
480 if (!rtlphy->sw_chnl_inprogress)
483 ret = _rtl92s_phy_sw_chnl_step_by_step(hw,
484 rtlphy->current_channel,
485 &rtlphy->sw_chnl_stage,
486 &rtlphy->sw_chnl_step, &delay);
493 rtlphy->sw_chnl_inprogress = false;
498 rtlphy->sw_chnl_inprogress = false;
500 RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE, "<==\n");
505 static void _rtl92se_phy_set_rf_sleep(struct ieee80211_hw *hw)
507 struct rtl_priv *rtlpriv = rtl_priv(hw);
510 u1btmp = rtl_read_byte(rtlpriv, LDOV12D_CTRL);
513 rtl_write_byte(rtlpriv, LDOV12D_CTRL, u1btmp);
514 rtl_write_byte(rtlpriv, SPS1_CTRL, 0x0);
515 rtl_write_byte(rtlpriv, TXPAUSE, 0xFF);
516 rtl_write_word(rtlpriv, CMDR, 0x57FC);
519 rtl_write_word(rtlpriv, CMDR, 0x77FC);
520 rtl_write_byte(rtlpriv, PHY_CCA, 0x0);
523 rtl_write_word(rtlpriv, CMDR, 0x37FC);
526 rtl_write_word(rtlpriv, CMDR, 0x77FC);
529 rtl_write_word(rtlpriv, CMDR, 0x57FC);
531 /* we should chnge GPIO to input mode
532 * this will drop away current about 25mA*/
533 rtl8192se_gpiobit3_cfg_inputmode(hw);
536 bool rtl92s_phy_set_rf_power_state(struct ieee80211_hw *hw,
537 enum rf_pwrstate rfpwr_state)
539 struct rtl_priv *rtlpriv = rtl_priv(hw);
540 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
541 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
542 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
545 struct rtl8192_tx_ring *ring = NULL;
547 if (rfpwr_state == ppsc->rfpwr_state)
550 switch (rfpwr_state) {
552 if ((ppsc->rfpwr_state == ERFOFF) &&
553 RT_IN_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC)) {
556 u32 InitializeCount = 0;
559 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
560 "IPS Set eRf nic enable\n");
561 rtstatus = rtl_ps_enable_nic(hw);
562 } while (!rtstatus && (InitializeCount < 10));
564 RT_CLEAR_PS_LEVEL(ppsc,
565 RT_RF_OFF_LEVL_HALT_NIC);
567 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
568 "awake, sleeped:%d ms state_inap:%x\n",
569 jiffies_to_msecs(jiffies -
572 rtlpriv->psc.state_inap);
573 ppsc->last_awake_jiffies = jiffies;
574 rtl_write_word(rtlpriv, CMDR, 0x37FC);
575 rtl_write_byte(rtlpriv, TXPAUSE, 0x00);
576 rtl_write_byte(rtlpriv, PHY_CCA, 0x3);
579 if (mac->link_state == MAC80211_LINKED)
580 rtlpriv->cfg->ops->led_control(hw,
583 rtlpriv->cfg->ops->led_control(hw,
588 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_HALT_NIC) {
589 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
590 "IPS Set eRf nic disable\n");
591 rtl_ps_disable_nic(hw);
592 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
594 if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS)
595 rtlpriv->cfg->ops->led_control(hw,
598 rtlpriv->cfg->ops->led_control(hw,
604 if (ppsc->rfpwr_state == ERFOFF)
607 for (queue_id = 0, i = 0;
608 queue_id < RTL_PCI_MAX_TX_QUEUE_COUNT;) {
609 ring = &pcipriv->dev.tx_ring[queue_id];
610 if (skb_queue_len(&ring->queue) == 0 ||
611 queue_id == BEACON_QUEUE) {
615 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
616 "eRf Off/Sleep: %d times TcbBusyQueue[%d] = %d before doze!\n",
618 skb_queue_len(&ring->queue));
624 if (i >= MAX_DOZE_WAITING_TIMES_9x) {
625 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
626 "ERFOFF: %d times TcbBusyQueue[%d] = %d !\n",
627 MAX_DOZE_WAITING_TIMES_9x,
629 skb_queue_len(&ring->queue));
634 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
635 "Set ERFSLEEP awaked:%d ms\n",
636 jiffies_to_msecs(jiffies -
637 ppsc->last_awake_jiffies));
639 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
640 "sleep awaked:%d ms state_inap:%x\n",
641 jiffies_to_msecs(jiffies -
642 ppsc->last_awake_jiffies),
643 rtlpriv->psc.state_inap);
644 ppsc->last_sleep_jiffies = jiffies;
645 _rtl92se_phy_set_rf_sleep(hw);
648 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
649 "switch case not processed\n");
655 ppsc->rfpwr_state = rfpwr_state;
660 static bool _rtl92s_phy_config_rfpa_bias_current(struct ieee80211_hw *hw,
661 enum radio_path rfpath)
663 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
664 bool rtstatus = true;
667 /* If inferiority IC, we have to increase the PA bias current */
668 if (rtlhal->ic_class != IC_INFERIORITY_A) {
669 tmpval = rtl92s_phy_query_rf_reg(hw, rfpath, RF_IPA, 0xf);
670 rtl92s_phy_set_rf_reg(hw, rfpath, RF_IPA, 0xf, tmpval + 1);
676 static void _rtl92s_store_pwrindex_diffrate_offset(struct ieee80211_hw *hw,
677 u32 reg_addr, u32 bitmask, u32 data)
679 struct rtl_priv *rtlpriv = rtl_priv(hw);
680 struct rtl_phy *rtlphy = &(rtlpriv->phy);
683 if (reg_addr == RTXAGC_RATE18_06)
685 else if (reg_addr == RTXAGC_RATE54_24)
687 else if (reg_addr == RTXAGC_CCK_MCS32)
689 else if (reg_addr == RTXAGC_MCS03_MCS00)
691 else if (reg_addr == RTXAGC_MCS07_MCS04)
693 else if (reg_addr == RTXAGC_MCS11_MCS08)
695 else if (reg_addr == RTXAGC_MCS15_MCS12)
700 rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][index] = data;
702 rtlphy->pwrgroup_cnt++;
705 static void _rtl92s_phy_init_register_definition(struct ieee80211_hw *hw)
707 struct rtl_priv *rtlpriv = rtl_priv(hw);
708 struct rtl_phy *rtlphy = &(rtlpriv->phy);
710 /*RF Interface Sowrtware Control */
711 rtlphy->phyreg_def[RF90_PATH_A].rfintfs = RFPGA0_XAB_RFINTERFACESW;
712 rtlphy->phyreg_def[RF90_PATH_B].rfintfs = RFPGA0_XAB_RFINTERFACESW;
713 rtlphy->phyreg_def[RF90_PATH_C].rfintfs = RFPGA0_XCD_RFINTERFACESW;
714 rtlphy->phyreg_def[RF90_PATH_D].rfintfs = RFPGA0_XCD_RFINTERFACESW;
716 /* RF Interface Readback Value */
717 rtlphy->phyreg_def[RF90_PATH_A].rfintfi = RFPGA0_XAB_RFINTERFACERB;
718 rtlphy->phyreg_def[RF90_PATH_B].rfintfi = RFPGA0_XAB_RFINTERFACERB;
719 rtlphy->phyreg_def[RF90_PATH_C].rfintfi = RFPGA0_XCD_RFINTERFACERB;
720 rtlphy->phyreg_def[RF90_PATH_D].rfintfi = RFPGA0_XCD_RFINTERFACERB;
722 /* RF Interface Output (and Enable) */
723 rtlphy->phyreg_def[RF90_PATH_A].rfintfo = RFPGA0_XA_RFINTERFACEOE;
724 rtlphy->phyreg_def[RF90_PATH_B].rfintfo = RFPGA0_XB_RFINTERFACEOE;
725 rtlphy->phyreg_def[RF90_PATH_C].rfintfo = RFPGA0_XC_RFINTERFACEOE;
726 rtlphy->phyreg_def[RF90_PATH_D].rfintfo = RFPGA0_XD_RFINTERFACEOE;
728 /* RF Interface (Output and) Enable */
729 rtlphy->phyreg_def[RF90_PATH_A].rfintfe = RFPGA0_XA_RFINTERFACEOE;
730 rtlphy->phyreg_def[RF90_PATH_B].rfintfe = RFPGA0_XB_RFINTERFACEOE;
731 rtlphy->phyreg_def[RF90_PATH_C].rfintfe = RFPGA0_XC_RFINTERFACEOE;
732 rtlphy->phyreg_def[RF90_PATH_D].rfintfe = RFPGA0_XD_RFINTERFACEOE;
734 /* Addr of LSSI. Wirte RF register by driver */
735 rtlphy->phyreg_def[RF90_PATH_A].rf3wire_offset =
736 RFPGA0_XA_LSSIPARAMETER;
737 rtlphy->phyreg_def[RF90_PATH_B].rf3wire_offset =
738 RFPGA0_XB_LSSIPARAMETER;
739 rtlphy->phyreg_def[RF90_PATH_C].rf3wire_offset =
740 RFPGA0_XC_LSSIPARAMETER;
741 rtlphy->phyreg_def[RF90_PATH_D].rf3wire_offset =
742 RFPGA0_XD_LSSIPARAMETER;
745 rtlphy->phyreg_def[RF90_PATH_A].rflssi_select = RFPGA0_XAB_RFPARAMETER;
746 rtlphy->phyreg_def[RF90_PATH_B].rflssi_select = RFPGA0_XAB_RFPARAMETER;
747 rtlphy->phyreg_def[RF90_PATH_C].rflssi_select = RFPGA0_XCD_RFPARAMETER;
748 rtlphy->phyreg_def[RF90_PATH_D].rflssi_select = RFPGA0_XCD_RFPARAMETER;
750 /* Tx AGC Gain Stage (same for all path. Should we remove this?) */
751 rtlphy->phyreg_def[RF90_PATH_A].rftxgain_stage = RFPGA0_TXGAINSTAGE;
752 rtlphy->phyreg_def[RF90_PATH_B].rftxgain_stage = RFPGA0_TXGAINSTAGE;
753 rtlphy->phyreg_def[RF90_PATH_C].rftxgain_stage = RFPGA0_TXGAINSTAGE;
754 rtlphy->phyreg_def[RF90_PATH_D].rftxgain_stage = RFPGA0_TXGAINSTAGE;
756 /* Tranceiver A~D HSSI Parameter-1 */
757 rtlphy->phyreg_def[RF90_PATH_A].rfhssi_para1 = RFPGA0_XA_HSSIPARAMETER1;
758 rtlphy->phyreg_def[RF90_PATH_B].rfhssi_para1 = RFPGA0_XB_HSSIPARAMETER1;
759 rtlphy->phyreg_def[RF90_PATH_C].rfhssi_para1 = RFPGA0_XC_HSSIPARAMETER1;
760 rtlphy->phyreg_def[RF90_PATH_D].rfhssi_para1 = RFPGA0_XD_HSSIPARAMETER1;
762 /* Tranceiver A~D HSSI Parameter-2 */
763 rtlphy->phyreg_def[RF90_PATH_A].rfhssi_para2 = RFPGA0_XA_HSSIPARAMETER2;
764 rtlphy->phyreg_def[RF90_PATH_B].rfhssi_para2 = RFPGA0_XB_HSSIPARAMETER2;
765 rtlphy->phyreg_def[RF90_PATH_C].rfhssi_para2 = RFPGA0_XC_HSSIPARAMETER2;
766 rtlphy->phyreg_def[RF90_PATH_D].rfhssi_para2 = RFPGA0_XD_HSSIPARAMETER2;
768 /* RF switch Control */
769 rtlphy->phyreg_def[RF90_PATH_A].rfsw_ctrl = RFPGA0_XAB_SWITCHCONTROL;
770 rtlphy->phyreg_def[RF90_PATH_B].rfsw_ctrl = RFPGA0_XAB_SWITCHCONTROL;
771 rtlphy->phyreg_def[RF90_PATH_C].rfsw_ctrl = RFPGA0_XCD_SWITCHCONTROL;
772 rtlphy->phyreg_def[RF90_PATH_D].rfsw_ctrl = RFPGA0_XCD_SWITCHCONTROL;
775 rtlphy->phyreg_def[RF90_PATH_A].rfagc_control1 = ROFDM0_XAAGCCORE1;
776 rtlphy->phyreg_def[RF90_PATH_B].rfagc_control1 = ROFDM0_XBAGCCORE1;
777 rtlphy->phyreg_def[RF90_PATH_C].rfagc_control1 = ROFDM0_XCAGCCORE1;
778 rtlphy->phyreg_def[RF90_PATH_D].rfagc_control1 = ROFDM0_XDAGCCORE1;
781 rtlphy->phyreg_def[RF90_PATH_A].rfagc_control2 = ROFDM0_XAAGCCORE2;
782 rtlphy->phyreg_def[RF90_PATH_B].rfagc_control2 = ROFDM0_XBAGCCORE2;
783 rtlphy->phyreg_def[RF90_PATH_C].rfagc_control2 = ROFDM0_XCAGCCORE2;
784 rtlphy->phyreg_def[RF90_PATH_D].rfagc_control2 = ROFDM0_XDAGCCORE2;
786 /* RX AFE control 1 */
787 rtlphy->phyreg_def[RF90_PATH_A].rfrxiq_imbal = ROFDM0_XARXIQIMBALANCE;
788 rtlphy->phyreg_def[RF90_PATH_B].rfrxiq_imbal = ROFDM0_XBRXIQIMBALANCE;
789 rtlphy->phyreg_def[RF90_PATH_C].rfrxiq_imbal = ROFDM0_XCRXIQIMBALANCE;
790 rtlphy->phyreg_def[RF90_PATH_D].rfrxiq_imbal = ROFDM0_XDRXIQIMBALANCE;
792 /* RX AFE control 1 */
793 rtlphy->phyreg_def[RF90_PATH_A].rfrx_afe = ROFDM0_XARXAFE;
794 rtlphy->phyreg_def[RF90_PATH_B].rfrx_afe = ROFDM0_XBRXAFE;
795 rtlphy->phyreg_def[RF90_PATH_C].rfrx_afe = ROFDM0_XCRXAFE;
796 rtlphy->phyreg_def[RF90_PATH_D].rfrx_afe = ROFDM0_XDRXAFE;
798 /* Tx AFE control 1 */
799 rtlphy->phyreg_def[RF90_PATH_A].rftxiq_imbal = ROFDM0_XATXIQIMBALANCE;
800 rtlphy->phyreg_def[RF90_PATH_B].rftxiq_imbal = ROFDM0_XBTXIQIMBALANCE;
801 rtlphy->phyreg_def[RF90_PATH_C].rftxiq_imbal = ROFDM0_XCTXIQIMBALANCE;
802 rtlphy->phyreg_def[RF90_PATH_D].rftxiq_imbal = ROFDM0_XDTXIQIMBALANCE;
804 /* Tx AFE control 2 */
805 rtlphy->phyreg_def[RF90_PATH_A].rftx_afe = ROFDM0_XATXAFE;
806 rtlphy->phyreg_def[RF90_PATH_B].rftx_afe = ROFDM0_XBTXAFE;
807 rtlphy->phyreg_def[RF90_PATH_C].rftx_afe = ROFDM0_XCTXAFE;
808 rtlphy->phyreg_def[RF90_PATH_D].rftx_afe = ROFDM0_XDTXAFE;
810 /* Tranceiver LSSI Readback */
811 rtlphy->phyreg_def[RF90_PATH_A].rf_rb = RFPGA0_XA_LSSIREADBACK;
812 rtlphy->phyreg_def[RF90_PATH_B].rf_rb = RFPGA0_XB_LSSIREADBACK;
813 rtlphy->phyreg_def[RF90_PATH_C].rf_rb = RFPGA0_XC_LSSIREADBACK;
814 rtlphy->phyreg_def[RF90_PATH_D].rf_rb = RFPGA0_XD_LSSIREADBACK;
816 /* Tranceiver LSSI Readback PI mode */
817 rtlphy->phyreg_def[RF90_PATH_A].rf_rbpi = TRANSCEIVERA_HSPI_READBACK;
818 rtlphy->phyreg_def[RF90_PATH_B].rf_rbpi = TRANSCEIVERB_HSPI_READBACK;
822 static bool _rtl92s_phy_config_bb(struct ieee80211_hw *hw, u8 configtype)
827 u16 phy_reg_len, agc_len;
829 agc_len = AGCTAB_ARRAYLENGTH;
830 agc_table = rtl8192seagctab_array;
831 /* Default RF_type: 2T2R */
832 phy_reg_len = PHY_REG_2T2RARRAYLENGTH;
833 phy_reg_table = rtl8192sephy_reg_2t2rarray;
835 if (configtype == BASEBAND_CONFIG_PHY_REG) {
836 for (i = 0; i < phy_reg_len; i = i + 2) {
837 rtl_addr_delay(phy_reg_table[i]);
839 /* Add delay for ECS T20 & LG malow platform, */
842 rtl92s_phy_set_bb_reg(hw, phy_reg_table[i], MASKDWORD,
843 phy_reg_table[i + 1]);
845 } else if (configtype == BASEBAND_CONFIG_AGC_TAB) {
846 for (i = 0; i < agc_len; i = i + 2) {
847 rtl92s_phy_set_bb_reg(hw, agc_table[i], MASKDWORD,
850 /* Add delay for ECS T20 & LG malow platform */
858 static bool _rtl92s_phy_set_bb_to_diff_rf(struct ieee80211_hw *hw,
861 struct rtl_priv *rtlpriv = rtl_priv(hw);
862 struct rtl_phy *rtlphy = &(rtlpriv->phy);
863 u32 *phy_regarray2xtxr_table;
864 u16 phy_regarray2xtxr_len;
867 if (rtlphy->rf_type == RF_1T1R) {
868 phy_regarray2xtxr_table = rtl8192sephy_changeto_1t1rarray;
869 phy_regarray2xtxr_len = PHY_CHANGETO_1T1RARRAYLENGTH;
870 } else if (rtlphy->rf_type == RF_1T2R) {
871 phy_regarray2xtxr_table = rtl8192sephy_changeto_1t2rarray;
872 phy_regarray2xtxr_len = PHY_CHANGETO_1T2RARRAYLENGTH;
877 if (configtype == BASEBAND_CONFIG_PHY_REG) {
878 for (i = 0; i < phy_regarray2xtxr_len; i = i + 3) {
879 rtl_addr_delay(phy_regarray2xtxr_table[i]);
881 rtl92s_phy_set_bb_reg(hw, phy_regarray2xtxr_table[i],
882 phy_regarray2xtxr_table[i + 1],
883 phy_regarray2xtxr_table[i + 2]);
890 static bool _rtl92s_phy_config_bb_with_pg(struct ieee80211_hw *hw,
897 phy_pg_len = PHY_REG_ARRAY_PGLENGTH;
898 phy_table_pg = rtl8192sephy_reg_array_pg;
900 if (configtype == BASEBAND_CONFIG_PHY_REG) {
901 for (i = 0; i < phy_pg_len; i = i + 3) {
902 rtl_addr_delay(phy_table_pg[i]);
904 _rtl92s_store_pwrindex_diffrate_offset(hw,
907 phy_table_pg[i + 2]);
908 rtl92s_phy_set_bb_reg(hw, phy_table_pg[i],
910 phy_table_pg[i + 2]);
917 static bool _rtl92s_phy_bb_config_parafile(struct ieee80211_hw *hw)
919 struct rtl_priv *rtlpriv = rtl_priv(hw);
920 struct rtl_phy *rtlphy = &(rtlpriv->phy);
921 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
922 bool rtstatus = true;
924 /* 1. Read PHY_REG.TXT BB INIT!! */
925 /* We will separate as 1T1R/1T2R/1T2R_GREEN/2T2R */
926 if (rtlphy->rf_type == RF_1T2R || rtlphy->rf_type == RF_2T2R ||
927 rtlphy->rf_type == RF_1T1R || rtlphy->rf_type == RF_2T2R_GREEN) {
928 rtstatus = _rtl92s_phy_config_bb(hw, BASEBAND_CONFIG_PHY_REG);
930 if (rtlphy->rf_type != RF_2T2R &&
931 rtlphy->rf_type != RF_2T2R_GREEN)
932 /* so we should reconfig BB reg with the right
934 rtstatus = _rtl92s_phy_set_bb_to_diff_rf(hw,
935 BASEBAND_CONFIG_PHY_REG);
941 RT_TRACE(rtlpriv, COMP_INIT, DBG_EMERG,
942 "Write BB Reg Fail!!\n");
943 goto phy_BB8190_Config_ParaFile_Fail;
946 /* 2. If EEPROM or EFUSE autoload OK, We must config by
948 if (rtlefuse->autoload_failflag == false) {
949 rtlphy->pwrgroup_cnt = 0;
951 rtstatus = _rtl92s_phy_config_bb_with_pg(hw,
952 BASEBAND_CONFIG_PHY_REG);
955 RT_TRACE(rtlpriv, COMP_INIT, DBG_EMERG,
956 "_rtl92s_phy_bb_config_parafile(): BB_PG Reg Fail!!\n");
957 goto phy_BB8190_Config_ParaFile_Fail;
960 /* 3. BB AGC table Initialization */
961 rtstatus = _rtl92s_phy_config_bb(hw, BASEBAND_CONFIG_AGC_TAB);
964 pr_err("%s(): AGC Table Fail\n", __func__);
965 goto phy_BB8190_Config_ParaFile_Fail;
968 /* Check if the CCK HighPower is turned ON. */
969 /* This is used to calculate PWDB. */
970 rtlphy->cck_high_power = (bool)(rtl92s_phy_query_bb_reg(hw,
971 RFPGA0_XA_HSSIPARAMETER2, 0x200));
973 phy_BB8190_Config_ParaFile_Fail:
977 u8 rtl92s_phy_config_rf(struct ieee80211_hw *hw, enum radio_path rfpath)
979 struct rtl_priv *rtlpriv = rtl_priv(hw);
980 struct rtl_phy *rtlphy = &(rtlpriv->phy);
982 bool rtstatus = true;
985 u16 radio_a_tblen, radio_b_tblen;
987 radio_a_tblen = RADIOA_1T_ARRAYLENGTH;
988 radio_a_table = rtl8192seradioa_1t_array;
990 /* Using Green mode array table for RF_2T2R_GREEN */
991 if (rtlphy->rf_type == RF_2T2R_GREEN) {
992 radio_b_table = rtl8192seradiob_gm_array;
993 radio_b_tblen = RADIOB_GM_ARRAYLENGTH;
995 radio_b_table = rtl8192seradiob_array;
996 radio_b_tblen = RADIOB_ARRAYLENGTH;
999 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Radio No %x\n", rfpath);
1004 for (i = 0; i < radio_a_tblen; i = i + 2) {
1005 rtl_rfreg_delay(hw, rfpath, radio_a_table[i],
1006 MASK20BITS, radio_a_table[i + 1]);
1010 /* PA Bias current for inferiority IC */
1011 _rtl92s_phy_config_rfpa_bias_current(hw, rfpath);
1014 for (i = 0; i < radio_b_tblen; i = i + 2) {
1015 rtl_rfreg_delay(hw, rfpath, radio_b_table[i],
1016 MASK20BITS, radio_b_table[i + 1]);
1033 bool rtl92s_phy_mac_config(struct ieee80211_hw *hw)
1035 struct rtl_priv *rtlpriv = rtl_priv(hw);
1040 arraylength = MAC_2T_ARRAYLENGTH;
1041 ptraArray = rtl8192semac_2t_array;
1043 for (i = 0; i < arraylength; i = i + 2)
1044 rtl_write_byte(rtlpriv, ptraArray[i], (u8)ptraArray[i + 1]);
1050 bool rtl92s_phy_bb_config(struct ieee80211_hw *hw)
1052 struct rtl_priv *rtlpriv = rtl_priv(hw);
1053 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1054 bool rtstatus = true;
1055 u8 pathmap, index, rf_num = 0;
1058 _rtl92s_phy_init_register_definition(hw);
1060 /* Config BB and AGC */
1061 rtstatus = _rtl92s_phy_bb_config_parafile(hw);
1064 /* Check BB/RF confiuration setting. */
1065 /* We only need to configure RF which is turned on. */
1066 path1 = (u8)(rtl92s_phy_query_bb_reg(hw, RFPGA0_TXINFO, 0xf));
1068 path2 = (u8)(rtl92s_phy_query_bb_reg(hw, ROFDM0_TRXPATHENABLE, 0xf));
1069 pathmap = path1 | path2;
1071 rtlphy->rf_pathmap = pathmap;
1072 for (index = 0; index < 4; index++) {
1073 if ((pathmap >> index) & 0x1)
1077 if ((rtlphy->rf_type == RF_1T1R && rf_num != 1) ||
1078 (rtlphy->rf_type == RF_1T2R && rf_num != 2) ||
1079 (rtlphy->rf_type == RF_2T2R && rf_num != 2) ||
1080 (rtlphy->rf_type == RF_2T2R_GREEN && rf_num != 2)) {
1081 RT_TRACE(rtlpriv, COMP_INIT, DBG_EMERG,
1082 "RF_Type(%x) does not match RF_Num(%x)!!\n",
1083 rtlphy->rf_type, rf_num);
1084 RT_TRACE(rtlpriv, COMP_INIT, DBG_EMERG,
1085 "path1 0x%x, path2 0x%x, pathmap 0x%x\n",
1086 path1, path2, pathmap);
1092 bool rtl92s_phy_rf_config(struct ieee80211_hw *hw)
1094 struct rtl_priv *rtlpriv = rtl_priv(hw);
1095 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1097 /* Initialize general global value */
1098 if (rtlphy->rf_type == RF_1T1R)
1099 rtlphy->num_total_rfpath = 1;
1101 rtlphy->num_total_rfpath = 2;
1103 /* Config BB and RF */
1104 return rtl92s_phy_rf6052_config(hw);
1107 void rtl92s_phy_get_hw_reg_originalvalue(struct ieee80211_hw *hw)
1109 struct rtl_priv *rtlpriv = rtl_priv(hw);
1110 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1112 /* read rx initial gain */
1113 rtlphy->default_initialgain[0] = rtl_get_bbreg(hw,
1114 ROFDM0_XAAGCCORE1, MASKBYTE0);
1115 rtlphy->default_initialgain[1] = rtl_get_bbreg(hw,
1116 ROFDM0_XBAGCCORE1, MASKBYTE0);
1117 rtlphy->default_initialgain[2] = rtl_get_bbreg(hw,
1118 ROFDM0_XCAGCCORE1, MASKBYTE0);
1119 rtlphy->default_initialgain[3] = rtl_get_bbreg(hw,
1120 ROFDM0_XDAGCCORE1, MASKBYTE0);
1121 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1122 "Default initial gain (c50=0x%x, c58=0x%x, c60=0x%x, c68=0x%x)\n",
1123 rtlphy->default_initialgain[0],
1124 rtlphy->default_initialgain[1],
1125 rtlphy->default_initialgain[2],
1126 rtlphy->default_initialgain[3]);
1128 /* read framesync */
1129 rtlphy->framesync = rtl_get_bbreg(hw, ROFDM0_RXDETECTOR3, MASKBYTE0);
1130 rtlphy->framesync_c34 = rtl_get_bbreg(hw, ROFDM0_RXDETECTOR2,
1132 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1133 "Default framesync (0x%x) = 0x%x\n",
1134 ROFDM0_RXDETECTOR3, rtlphy->framesync);
1138 static void _rtl92s_phy_get_txpower_index(struct ieee80211_hw *hw, u8 channel,
1139 u8 *cckpowerlevel, u8 *ofdmpowerLevel)
1141 struct rtl_priv *rtlpriv = rtl_priv(hw);
1142 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1143 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1144 u8 index = (channel - 1);
1148 cckpowerlevel[0] = rtlefuse->txpwrlevel_cck[0][index];
1150 cckpowerlevel[1] = rtlefuse->txpwrlevel_cck[1][index];
1152 /* 2. OFDM for 1T or 2T */
1153 if (rtlphy->rf_type == RF_1T2R || rtlphy->rf_type == RF_1T1R) {
1154 /* Read HT 40 OFDM TX power */
1155 ofdmpowerLevel[0] = rtlefuse->txpwrlevel_ht40_1s[0][index];
1156 ofdmpowerLevel[1] = rtlefuse->txpwrlevel_ht40_1s[1][index];
1157 } else if (rtlphy->rf_type == RF_2T2R) {
1158 /* Read HT 40 OFDM TX power */
1159 ofdmpowerLevel[0] = rtlefuse->txpwrlevel_ht40_2s[0][index];
1160 ofdmpowerLevel[1] = rtlefuse->txpwrlevel_ht40_2s[1][index];
1162 ofdmpowerLevel[0] = 0;
1163 ofdmpowerLevel[1] = 0;
1167 static void _rtl92s_phy_ccxpower_indexcheck(struct ieee80211_hw *hw,
1168 u8 channel, u8 *cckpowerlevel, u8 *ofdmpowerlevel)
1170 struct rtl_priv *rtlpriv = rtl_priv(hw);
1171 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1173 rtlphy->cur_cck_txpwridx = cckpowerlevel[0];
1174 rtlphy->cur_ofdm24g_txpwridx = ofdmpowerlevel[0];
1177 void rtl92s_phy_set_txpower(struct ieee80211_hw *hw, u8 channel)
1179 struct rtl_priv *rtlpriv = rtl_priv(hw);
1180 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1181 /* [0]:RF-A, [1]:RF-B */
1182 u8 cckpowerlevel[2], ofdmpowerLevel[2];
1184 if (!rtlefuse->txpwr_fromeprom)
1187 /* Mainly we use RF-A Tx Power to write the Tx Power registers,
1188 * but the RF-B Tx Power must be calculated by the antenna diff.
1189 * So we have to rewrite Antenna gain offset register here.
1190 * Please refer to BB register 0x80c
1192 * 2. For OFDM 1T or 2T */
1193 _rtl92s_phy_get_txpower_index(hw, channel, &cckpowerlevel[0],
1194 &ofdmpowerLevel[0]);
1196 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
1197 "Channel-%d, cckPowerLevel (A / B) = 0x%x / 0x%x, ofdmPowerLevel (A / B) = 0x%x / 0x%x\n",
1198 channel, cckpowerlevel[0], cckpowerlevel[1],
1199 ofdmpowerLevel[0], ofdmpowerLevel[1]);
1201 _rtl92s_phy_ccxpower_indexcheck(hw, channel, &cckpowerlevel[0],
1202 &ofdmpowerLevel[0]);
1204 rtl92s_phy_rf6052_set_ccktxpower(hw, cckpowerlevel[0]);
1205 rtl92s_phy_rf6052_set_ofdmtxpower(hw, &ofdmpowerLevel[0], channel);
1209 void rtl92s_phy_chk_fwcmd_iodone(struct ieee80211_hw *hw)
1211 struct rtl_priv *rtlpriv = rtl_priv(hw);
1212 u16 pollingcnt = 10000;
1215 /* Make sure that CMD IO has be accepted by FW. */
1219 tmpvalue = rtl_read_dword(rtlpriv, WFM5);
1222 } while (--pollingcnt);
1224 if (pollingcnt == 0)
1225 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "Set FW Cmd fail!!\n");
1229 static void _rtl92s_phy_set_fwcmd_io(struct ieee80211_hw *hw)
1231 struct rtl_priv *rtlpriv = rtl_priv(hw);
1232 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1233 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1234 u32 input, current_aid = 0;
1236 if (is_hal_stop(rtlhal))
1239 if (hal_get_firmwareversion(rtlpriv) < 0x34)
1241 /* We re-map RA related CMD IO to combinational ones */
1242 /* if FW version is v.52 or later. */
1243 switch (rtlhal->current_fwcmd_io) {
1244 case FW_CMD_RA_REFRESH_N:
1245 rtlhal->current_fwcmd_io = FW_CMD_RA_REFRESH_N_COMB;
1247 case FW_CMD_RA_REFRESH_BG:
1248 rtlhal->current_fwcmd_io = FW_CMD_RA_REFRESH_BG_COMB;
1255 switch (rtlhal->current_fwcmd_io) {
1256 case FW_CMD_RA_RESET:
1257 RT_TRACE(rtlpriv, COMP_CMD, DBG_DMESG, "FW_CMD_RA_RESET\n");
1258 rtl_write_dword(rtlpriv, WFM5, FW_RA_RESET);
1259 rtl92s_phy_chk_fwcmd_iodone(hw);
1261 case FW_CMD_RA_ACTIVE:
1262 RT_TRACE(rtlpriv, COMP_CMD, DBG_DMESG, "FW_CMD_RA_ACTIVE\n");
1263 rtl_write_dword(rtlpriv, WFM5, FW_RA_ACTIVE);
1264 rtl92s_phy_chk_fwcmd_iodone(hw);
1266 case FW_CMD_RA_REFRESH_N:
1267 RT_TRACE(rtlpriv, COMP_CMD, DBG_DMESG, "FW_CMD_RA_REFRESH_N\n");
1268 input = FW_RA_REFRESH;
1269 rtl_write_dword(rtlpriv, WFM5, input);
1270 rtl92s_phy_chk_fwcmd_iodone(hw);
1271 rtl_write_dword(rtlpriv, WFM5, FW_RA_ENABLE_RSSI_MASK);
1272 rtl92s_phy_chk_fwcmd_iodone(hw);
1274 case FW_CMD_RA_REFRESH_BG:
1275 RT_TRACE(rtlpriv, COMP_CMD, DBG_DMESG,
1276 "FW_CMD_RA_REFRESH_BG\n");
1277 rtl_write_dword(rtlpriv, WFM5, FW_RA_REFRESH);
1278 rtl92s_phy_chk_fwcmd_iodone(hw);
1279 rtl_write_dword(rtlpriv, WFM5, FW_RA_DISABLE_RSSI_MASK);
1280 rtl92s_phy_chk_fwcmd_iodone(hw);
1282 case FW_CMD_RA_REFRESH_N_COMB:
1283 RT_TRACE(rtlpriv, COMP_CMD, DBG_DMESG,
1284 "FW_CMD_RA_REFRESH_N_COMB\n");
1285 input = FW_RA_IOT_N_COMB;
1286 rtl_write_dword(rtlpriv, WFM5, input);
1287 rtl92s_phy_chk_fwcmd_iodone(hw);
1289 case FW_CMD_RA_REFRESH_BG_COMB:
1290 RT_TRACE(rtlpriv, COMP_CMD, DBG_DMESG,
1291 "FW_CMD_RA_REFRESH_BG_COMB\n");
1292 input = FW_RA_IOT_BG_COMB;
1293 rtl_write_dword(rtlpriv, WFM5, input);
1294 rtl92s_phy_chk_fwcmd_iodone(hw);
1296 case FW_CMD_IQK_ENABLE:
1297 RT_TRACE(rtlpriv, COMP_CMD, DBG_DMESG, "FW_CMD_IQK_ENABLE\n");
1298 rtl_write_dword(rtlpriv, WFM5, FW_IQK_ENABLE);
1299 rtl92s_phy_chk_fwcmd_iodone(hw);
1301 case FW_CMD_PAUSE_DM_BY_SCAN:
1302 /* Lower initial gain */
1303 rtl_set_bbreg(hw, ROFDM0_XAAGCCORE1, MASKBYTE0, 0x17);
1304 rtl_set_bbreg(hw, ROFDM0_XBAGCCORE1, MASKBYTE0, 0x17);
1306 rtl_set_bbreg(hw, RCCK0_CCA, MASKBYTE2, 0x40);
1308 case FW_CMD_RESUME_DM_BY_SCAN:
1310 rtl_set_bbreg(hw, RCCK0_CCA, MASKBYTE2, 0xcd);
1311 rtl92s_phy_set_txpower(hw, rtlphy->current_channel);
1313 case FW_CMD_HIGH_PWR_DISABLE:
1314 if (rtlpriv->dm.dm_flag & HAL_DM_HIPWR_DISABLE)
1317 /* Lower initial gain */
1318 rtl_set_bbreg(hw, ROFDM0_XAAGCCORE1, MASKBYTE0, 0x17);
1319 rtl_set_bbreg(hw, ROFDM0_XBAGCCORE1, MASKBYTE0, 0x17);
1321 rtl_set_bbreg(hw, RCCK0_CCA, MASKBYTE2, 0x40);
1323 case FW_CMD_HIGH_PWR_ENABLE:
1324 if ((rtlpriv->dm.dm_flag & HAL_DM_HIPWR_DISABLE) ||
1325 rtlpriv->dm.dynamic_txpower_enable)
1329 rtl_set_bbreg(hw, RCCK0_CCA, MASKBYTE2, 0xcd);
1331 case FW_CMD_LPS_ENTER:
1332 RT_TRACE(rtlpriv, COMP_CMD, DBG_DMESG, "FW_CMD_LPS_ENTER\n");
1333 current_aid = rtlpriv->mac80211.assoc_id;
1334 rtl_write_dword(rtlpriv, WFM5, (FW_LPS_ENTER |
1335 ((current_aid | 0xc000) << 8)));
1336 rtl92s_phy_chk_fwcmd_iodone(hw);
1337 /* FW set TXOP disable here, so disable EDCA
1338 * turbo mode until driver leave LPS */
1340 case FW_CMD_LPS_LEAVE:
1341 RT_TRACE(rtlpriv, COMP_CMD, DBG_DMESG, "FW_CMD_LPS_LEAVE\n");
1342 rtl_write_dword(rtlpriv, WFM5, FW_LPS_LEAVE);
1343 rtl92s_phy_chk_fwcmd_iodone(hw);
1345 case FW_CMD_ADD_A2_ENTRY:
1346 RT_TRACE(rtlpriv, COMP_CMD, DBG_DMESG, "FW_CMD_ADD_A2_ENTRY\n");
1347 rtl_write_dword(rtlpriv, WFM5, FW_ADD_A2_ENTRY);
1348 rtl92s_phy_chk_fwcmd_iodone(hw);
1350 case FW_CMD_CTRL_DM_BY_DRIVER:
1351 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD,
1352 "FW_CMD_CTRL_DM_BY_DRIVER\n");
1353 rtl_write_dword(rtlpriv, WFM5, FW_CTRL_DM_BY_DRIVER);
1354 rtl92s_phy_chk_fwcmd_iodone(hw);
1361 rtl92s_phy_chk_fwcmd_iodone(hw);
1363 /* Clear FW CMD operation flag. */
1364 rtlhal->set_fwcmd_inprogress = false;
1367 bool rtl92s_phy_set_fw_cmd(struct ieee80211_hw *hw, enum fwcmd_iotype fw_cmdio)
1369 struct rtl_priv *rtlpriv = rtl_priv(hw);
1370 struct dig_t *digtable = &rtlpriv->dm_digtable;
1371 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1372 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1373 u32 fw_param = FW_CMD_IO_PARA_QUERY(rtlpriv);
1374 u16 fw_cmdmap = FW_CMD_IO_QUERY(rtlpriv);
1375 bool postprocessing = false;
1377 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD,
1378 "Set FW Cmd(%#x), set_fwcmd_inprogress(%d)\n",
1379 fw_cmdio, rtlhal->set_fwcmd_inprogress);
1382 /* We re-map to combined FW CMD ones if firmware version */
1383 /* is v.53 or later. */
1384 if (hal_get_firmwareversion(rtlpriv) >= 0x35) {
1386 case FW_CMD_RA_REFRESH_N:
1387 fw_cmdio = FW_CMD_RA_REFRESH_N_COMB;
1389 case FW_CMD_RA_REFRESH_BG:
1390 fw_cmdio = FW_CMD_RA_REFRESH_BG_COMB;
1396 if ((fw_cmdio == FW_CMD_IQK_ENABLE) ||
1397 (fw_cmdio == FW_CMD_RA_REFRESH_N) ||
1398 (fw_cmdio == FW_CMD_RA_REFRESH_BG)) {
1399 postprocessing = true;
1404 /* If firmware version is v.62 or later,
1405 * use FW_CMD_IO_SET for FW_CMD_CTRL_DM_BY_DRIVER */
1406 if (hal_get_firmwareversion(rtlpriv) >= 0x3E) {
1407 if (fw_cmdio == FW_CMD_CTRL_DM_BY_DRIVER)
1408 fw_cmdio = FW_CMD_CTRL_DM_BY_DRIVER_NEW;
1412 /* We shall revise all FW Cmd IO into Reg0x364
1413 * DM map table in the future. */
1415 case FW_CMD_RA_INIT:
1416 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, "RA init!!\n");
1417 fw_cmdmap |= FW_RA_INIT_CTL;
1418 FW_CMD_IO_SET(rtlpriv, fw_cmdmap);
1419 /* Clear control flag to sync with FW. */
1420 FW_CMD_IO_CLR(rtlpriv, FW_RA_INIT_CTL);
1422 case FW_CMD_DIG_DISABLE:
1423 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD,
1424 "Set DIG disable!!\n");
1425 fw_cmdmap &= ~FW_DIG_ENABLE_CTL;
1426 FW_CMD_IO_SET(rtlpriv, fw_cmdmap);
1428 case FW_CMD_DIG_ENABLE:
1429 case FW_CMD_DIG_RESUME:
1430 if (!(rtlpriv->dm.dm_flag & HAL_DM_DIG_DISABLE)) {
1431 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD,
1432 "Set DIG enable or resume!!\n");
1433 fw_cmdmap |= (FW_DIG_ENABLE_CTL | FW_SS_CTL);
1434 FW_CMD_IO_SET(rtlpriv, fw_cmdmap);
1437 case FW_CMD_DIG_HALT:
1438 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD,
1439 "Set DIG halt!!\n");
1440 fw_cmdmap &= ~(FW_DIG_ENABLE_CTL | FW_SS_CTL);
1441 FW_CMD_IO_SET(rtlpriv, fw_cmdmap);
1443 case FW_CMD_TXPWR_TRACK_THERMAL: {
1445 fw_cmdmap |= FW_PWR_TRK_CTL;
1447 /* Clear FW parameter in terms of thermal parts. */
1448 fw_param &= FW_PWR_TRK_PARAM_CLR;
1450 thermalval = rtlpriv->dm.thermalvalue;
1451 fw_param |= ((thermalval << 24) |
1452 (rtlefuse->thermalmeter[0] << 16));
1454 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD,
1455 "Set TxPwr tracking!! FwCmdMap(%#x), FwParam(%#x)\n",
1456 fw_cmdmap, fw_param);
1458 FW_CMD_PARA_SET(rtlpriv, fw_param);
1459 FW_CMD_IO_SET(rtlpriv, fw_cmdmap);
1461 /* Clear control flag to sync with FW. */
1462 FW_CMD_IO_CLR(rtlpriv, FW_PWR_TRK_CTL);
1465 /* The following FW CMDs are only compatible to
1467 case FW_CMD_RA_REFRESH_N_COMB:
1468 fw_cmdmap |= FW_RA_N_CTL;
1470 /* Clear RA BG mode control. */
1471 fw_cmdmap &= ~(FW_RA_BG_CTL | FW_RA_INIT_CTL);
1473 /* Clear FW parameter in terms of RA parts. */
1474 fw_param &= FW_RA_PARAM_CLR;
1476 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD,
1477 "[FW CMD] [New Version] Set RA/IOT Comb in n mode!! FwCmdMap(%#x), FwParam(%#x)\n",
1478 fw_cmdmap, fw_param);
1480 FW_CMD_PARA_SET(rtlpriv, fw_param);
1481 FW_CMD_IO_SET(rtlpriv, fw_cmdmap);
1483 /* Clear control flag to sync with FW. */
1484 FW_CMD_IO_CLR(rtlpriv, FW_RA_N_CTL);
1486 case FW_CMD_RA_REFRESH_BG_COMB:
1487 fw_cmdmap |= FW_RA_BG_CTL;
1489 /* Clear RA n-mode control. */
1490 fw_cmdmap &= ~(FW_RA_N_CTL | FW_RA_INIT_CTL);
1491 /* Clear FW parameter in terms of RA parts. */
1492 fw_param &= FW_RA_PARAM_CLR;
1494 FW_CMD_PARA_SET(rtlpriv, fw_param);
1495 FW_CMD_IO_SET(rtlpriv, fw_cmdmap);
1497 /* Clear control flag to sync with FW. */
1498 FW_CMD_IO_CLR(rtlpriv, FW_RA_BG_CTL);
1500 case FW_CMD_IQK_ENABLE:
1501 fw_cmdmap |= FW_IQK_CTL;
1502 FW_CMD_IO_SET(rtlpriv, fw_cmdmap);
1503 /* Clear control flag to sync with FW. */
1504 FW_CMD_IO_CLR(rtlpriv, FW_IQK_CTL);
1506 /* The following FW CMD is compatible to v.62 or later. */
1507 case FW_CMD_CTRL_DM_BY_DRIVER_NEW:
1508 fw_cmdmap |= FW_DRIVER_CTRL_DM_CTL;
1509 FW_CMD_IO_SET(rtlpriv, fw_cmdmap);
1511 /* The followed FW Cmds needs post-processing later. */
1512 case FW_CMD_RESUME_DM_BY_SCAN:
1513 fw_cmdmap |= (FW_DIG_ENABLE_CTL |
1514 FW_HIGH_PWR_ENABLE_CTL |
1517 if (rtlpriv->dm.dm_flag & HAL_DM_DIG_DISABLE ||
1518 !digtable->dig_enable_flag)
1519 fw_cmdmap &= ~FW_DIG_ENABLE_CTL;
1521 if ((rtlpriv->dm.dm_flag & HAL_DM_HIPWR_DISABLE) ||
1522 rtlpriv->dm.dynamic_txpower_enable)
1523 fw_cmdmap &= ~FW_HIGH_PWR_ENABLE_CTL;
1525 if ((digtable->dig_ext_port_stage ==
1526 DIG_EXT_PORT_STAGE_0) ||
1527 (digtable->dig_ext_port_stage ==
1528 DIG_EXT_PORT_STAGE_1))
1529 fw_cmdmap &= ~FW_DIG_ENABLE_CTL;
1531 FW_CMD_IO_SET(rtlpriv, fw_cmdmap);
1532 postprocessing = true;
1534 case FW_CMD_PAUSE_DM_BY_SCAN:
1535 fw_cmdmap &= ~(FW_DIG_ENABLE_CTL |
1536 FW_HIGH_PWR_ENABLE_CTL |
1538 FW_CMD_IO_SET(rtlpriv, fw_cmdmap);
1539 postprocessing = true;
1541 case FW_CMD_HIGH_PWR_DISABLE:
1542 fw_cmdmap &= ~FW_HIGH_PWR_ENABLE_CTL;
1543 FW_CMD_IO_SET(rtlpriv, fw_cmdmap);
1544 postprocessing = true;
1546 case FW_CMD_HIGH_PWR_ENABLE:
1547 if (!(rtlpriv->dm.dm_flag & HAL_DM_HIPWR_DISABLE) &&
1548 !rtlpriv->dm.dynamic_txpower_enable) {
1549 fw_cmdmap |= (FW_HIGH_PWR_ENABLE_CTL |
1551 FW_CMD_IO_SET(rtlpriv, fw_cmdmap);
1552 postprocessing = true;
1555 case FW_CMD_DIG_MODE_FA:
1556 fw_cmdmap |= FW_FA_CTL;
1557 FW_CMD_IO_SET(rtlpriv, fw_cmdmap);
1559 case FW_CMD_DIG_MODE_SS:
1560 fw_cmdmap &= ~FW_FA_CTL;
1561 FW_CMD_IO_SET(rtlpriv, fw_cmdmap);
1563 case FW_CMD_PAPE_CONTROL:
1564 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD,
1565 "[FW CMD] Set PAPE Control\n");
1566 fw_cmdmap &= ~FW_PAPE_CTL_BY_SW_HW;
1568 FW_CMD_IO_SET(rtlpriv, fw_cmdmap);
1571 /* Pass to original FW CMD processing callback
1573 postprocessing = true;
1578 /* We shall post processing these FW CMD if
1579 * variable postprocessing is set.
1581 if (postprocessing && !rtlhal->set_fwcmd_inprogress) {
1582 rtlhal->set_fwcmd_inprogress = true;
1583 /* Update current FW Cmd for callback use. */
1584 rtlhal->current_fwcmd_io = fw_cmdio;
1589 _rtl92s_phy_set_fwcmd_io(hw);
1593 static void _rtl92s_phy_check_ephy_switchready(struct ieee80211_hw *hw)
1595 struct rtl_priv *rtlpriv = rtl_priv(hw);
1599 regu1 = rtl_read_byte(rtlpriv, 0x554);
1600 while ((regu1 & BIT(5)) && (delay > 0)) {
1601 regu1 = rtl_read_byte(rtlpriv, 0x554);
1603 /* We delay only 50us to prevent
1604 * being scheduled out. */
1609 void rtl92s_phy_switch_ephy_parameter(struct ieee80211_hw *hw)
1611 struct rtl_priv *rtlpriv = rtl_priv(hw);
1612 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1614 /* The way to be capable to switch clock request
1615 * when the PG setting does not support clock request.
1616 * This is the backdoor solution to switch clock
1617 * request before ASPM or D3. */
1618 rtl_write_dword(rtlpriv, 0x540, 0x73c11);
1619 rtl_write_dword(rtlpriv, 0x548, 0x2407c);
1621 /* Switch EPHY parameter!!!! */
1622 rtl_write_word(rtlpriv, 0x550, 0x1000);
1623 rtl_write_byte(rtlpriv, 0x554, 0x20);
1624 _rtl92s_phy_check_ephy_switchready(hw);
1626 rtl_write_word(rtlpriv, 0x550, 0xa0eb);
1627 rtl_write_byte(rtlpriv, 0x554, 0x3e);
1628 _rtl92s_phy_check_ephy_switchready(hw);
1630 rtl_write_word(rtlpriv, 0x550, 0xff80);
1631 rtl_write_byte(rtlpriv, 0x554, 0x39);
1632 _rtl92s_phy_check_ephy_switchready(hw);
1634 /* Delay L1 enter time */
1635 if (ppsc->support_aspm && !ppsc->support_backdoor)
1636 rtl_write_byte(rtlpriv, 0x560, 0x40);
1638 rtl_write_byte(rtlpriv, 0x560, 0x00);
1642 void rtl92s_phy_set_beacon_hwreg(struct ieee80211_hw *hw, u16 beaconinterval)
1644 struct rtl_priv *rtlpriv = rtl_priv(hw);
1645 u32 new_bcn_num = 0;
1647 if (hal_get_firmwareversion(rtlpriv) >= 0x33) {
1648 /* Fw v.51 and later. */
1649 rtl_write_dword(rtlpriv, WFM5, 0xF1000000 |
1650 (beaconinterval << 8));
1652 new_bcn_num = beaconinterval * 32 - 64;
1653 rtl_write_dword(rtlpriv, WFM3 + 4, new_bcn_num);
1654 rtl_write_dword(rtlpriv, WFM3, 0xB026007C);