1 /******************************************************************************
3 * Copyright(c) 2009-2014 Realtek Corporation.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
22 * Larry Finger <Larry.Finger@lwfinger.net>
24 *****************************************************************************/
32 #include "../rtl8723com/phy_common.h"
35 #include "../rtl8723com/dm_common.h"
39 static bool _rtl8723be_phy_bb8723b_config_parafile(struct ieee80211_hw *hw);
40 static bool _rtl8723be_phy_config_mac_with_headerfile(struct ieee80211_hw *hw);
41 static bool _rtl8723be_phy_config_bb_with_headerfile(struct ieee80211_hw *hw,
43 static bool _rtl8723be_phy_config_bb_with_pgheaderfile(struct ieee80211_hw *hw,
45 static bool _rtl8723be_phy_sw_chnl_step_by_step(struct ieee80211_hw *hw,
46 u8 channel, u8 *stage,
47 u8 *step, u32 *delay);
49 static void rtl8723be_phy_set_rf_on(struct ieee80211_hw *hw);
50 static void rtl8723be_phy_set_io(struct ieee80211_hw *hw);
52 u32 rtl8723be_phy_query_rf_reg(struct ieee80211_hw *hw, enum radio_path rfpath,
53 u32 regaddr, u32 bitmask)
55 struct rtl_priv *rtlpriv = rtl_priv(hw);
56 u32 original_value, readback_value, bitshift;
59 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
60 "regaddr(%#x), rfpath(%#x), bitmask(%#x)\n",
61 regaddr, rfpath, bitmask);
63 spin_lock_irqsave(&rtlpriv->locks.rf_lock, flags);
65 original_value = rtl8723_phy_rf_serial_read(hw, rfpath, regaddr);
66 bitshift = rtl8723_phy_calculate_bit_shift(bitmask);
67 readback_value = (original_value & bitmask) >> bitshift;
69 spin_unlock_irqrestore(&rtlpriv->locks.rf_lock, flags);
71 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
72 "regaddr(%#x), rfpath(%#x), bitmask(%#x), original_value(%#x)\n",
73 regaddr, rfpath, bitmask, original_value);
75 return readback_value;
78 void rtl8723be_phy_set_rf_reg(struct ieee80211_hw *hw, enum radio_path path,
79 u32 regaddr, u32 bitmask, u32 data)
81 struct rtl_priv *rtlpriv = rtl_priv(hw);
82 u32 original_value, bitshift;
85 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
86 "regaddr(%#x), bitmask(%#x), data(%#x), rfpath(%#x)\n",
87 regaddr, bitmask, data, path);
89 spin_lock_irqsave(&rtlpriv->locks.rf_lock, flags);
91 if (bitmask != RFREG_OFFSET_MASK) {
92 original_value = rtl8723_phy_rf_serial_read(hw, path,
94 bitshift = rtl8723_phy_calculate_bit_shift(bitmask);
95 data = ((original_value & (~bitmask)) |
99 rtl8723_phy_rf_serial_write(hw, path, regaddr, data);
101 spin_unlock_irqrestore(&rtlpriv->locks.rf_lock, flags);
103 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
104 "regaddr(%#x), bitmask(%#x), data(%#x), rfpath(%#x)\n",
105 regaddr, bitmask, data, path);
109 bool rtl8723be_phy_mac_config(struct ieee80211_hw *hw)
111 struct rtl_priv *rtlpriv = rtl_priv(hw);
112 bool rtstatus = _rtl8723be_phy_config_mac_with_headerfile(hw);
114 rtl_write_byte(rtlpriv, 0x04CA, 0x0B);
118 bool rtl8723be_phy_bb_config(struct ieee80211_hw *hw)
120 bool rtstatus = true;
121 struct rtl_priv *rtlpriv = rtl_priv(hw);
123 u8 b_reg_hwparafile = 1;
125 u8 crystalcap = rtlpriv->efuse.crystalcap;
126 rtl8723_phy_init_bb_rf_reg_def(hw);
127 regval = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN);
128 rtl_write_word(rtlpriv, REG_SYS_FUNC_EN,
129 regval | BIT(13) | BIT(0) | BIT(1));
131 rtl_write_byte(rtlpriv, REG_RF_CTRL, RF_EN | RF_RSTB | RF_SDMRSTB);
132 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN,
133 FEN_PPLL | FEN_PCIEA | FEN_DIO_PCIE |
134 FEN_BB_GLB_RSTN | FEN_BBRSTB);
135 tmp = rtl_read_dword(rtlpriv, 0x4c);
136 rtl_write_dword(rtlpriv, 0x4c, tmp | BIT(23));
138 rtl_write_byte(rtlpriv, REG_AFE_XTAL_CTRL + 1, 0x80);
140 if (b_reg_hwparafile == 1)
141 rtstatus = _rtl8723be_phy_bb8723b_config_parafile(hw);
143 crystalcap = crystalcap & 0x3F;
144 rtl_set_bbreg(hw, REG_MAC_PHY_CTRL, 0xFFF000,
145 (crystalcap | crystalcap << 6));
150 bool rtl8723be_phy_rf_config(struct ieee80211_hw *hw)
152 return rtl8723be_phy_rf6052_config(hw);
155 static bool _rtl8723be_check_condition(struct ieee80211_hw *hw,
158 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
159 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
160 u32 _board = rtlefuse->board_type; /*need efuse define*/
161 u32 _interface = rtlhal->interface;
162 u32 _platform = 0x08;/*SupportPlatform */
163 u32 cond = condition;
165 if (condition == 0xCDCDCDCD)
168 cond = condition & 0xFF;
169 if ((_board & cond) == 0 && cond != 0x1F)
172 cond = condition & 0xFF00;
174 if ((_interface & cond) == 0 && cond != 0x07)
177 cond = condition & 0xFF0000;
179 if ((_platform & cond) == 0 && cond != 0x0F)
184 static void _rtl8723be_config_rf_reg(struct ieee80211_hw *hw, u32 addr,
185 u32 data, enum radio_path rfpath,
188 if (addr == 0xfe || addr == 0xffe) {
189 /* In order not to disturb BT music
190 * when wifi init.(1ant NIC only)
194 rtl_set_rfreg(hw, rfpath, regaddr, RFREG_OFFSET_MASK, data);
198 static void _rtl8723be_config_rf_radio_a(struct ieee80211_hw *hw,
201 u32 content = 0x1000; /*RF Content: radio_a_txt*/
202 u32 maskforphyset = (u32)(content & 0xE000);
204 _rtl8723be_config_rf_reg(hw, addr, data, RF90_PATH_A,
205 addr | maskforphyset);
209 static void _rtl8723be_phy_init_tx_power_by_rate(struct ieee80211_hw *hw)
211 struct rtl_priv *rtlpriv = rtl_priv(hw);
212 struct rtl_phy *rtlphy = &rtlpriv->phy;
214 u8 band, path, txnum, section;
216 for (band = BAND_ON_2_4G; band <= BAND_ON_5G; ++band)
217 for (path = 0; path < TX_PWR_BY_RATE_NUM_RF; ++path)
218 for (txnum = 0; txnum < TX_PWR_BY_RATE_NUM_RF; ++txnum)
220 section < TX_PWR_BY_RATE_NUM_SECTION;
222 rtlphy->tx_power_by_rate_offset
223 [band][path][txnum][section] = 0;
226 static void _rtl8723be_config_bb_reg(struct ieee80211_hw *hw,
231 } else if (addr == 0xfd) {
233 } else if (addr == 0xfc) {
235 } else if (addr == 0xfb) {
237 } else if (addr == 0xfa) {
239 } else if (addr == 0xf9) {
242 rtl_set_bbreg(hw, addr, MASKDWORD, data);
247 static void _rtl8723be_phy_set_txpower_by_rate_base(struct ieee80211_hw *hw,
249 u8 path, u8 rate_section,
252 struct rtl_priv *rtlpriv = rtl_priv(hw);
253 struct rtl_phy *rtlphy = &rtlpriv->phy;
255 if (path > RF90_PATH_D) {
256 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
257 "Invalid Rf Path %d in phy_SetTxPowerByRatBase()\n",
262 if (band == BAND_ON_2_4G) {
263 switch (rate_section) {
265 rtlphy->txpwr_by_rate_base_24g[path][txnum][0] = value;
268 rtlphy->txpwr_by_rate_base_24g[path][txnum][1] = value;
271 rtlphy->txpwr_by_rate_base_24g[path][txnum][2] = value;
274 rtlphy->txpwr_by_rate_base_24g[path][txnum][3] = value;
277 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
278 "Invalid RateSection %d in Band 2.4G, Rf Path %d, %dTx in PHY_SetTxPowerByRateBase()\n",
279 rate_section, path, txnum);
283 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
284 "Invalid Band %d in PHY_SetTxPowerByRateBase()\n",
290 static u8 _rtl8723be_phy_get_txpower_by_rate_base(struct ieee80211_hw *hw,
291 u8 band, u8 path, u8 txnum,
294 struct rtl_priv *rtlpriv = rtl_priv(hw);
295 struct rtl_phy *rtlphy = &rtlpriv->phy;
297 if (path > RF90_PATH_D) {
298 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
299 "Invalid Rf Path %d in PHY_GetTxPowerByRateBase()\n",
304 if (band == BAND_ON_2_4G) {
305 switch (rate_section) {
307 value = rtlphy->txpwr_by_rate_base_24g[path][txnum][0];
310 value = rtlphy->txpwr_by_rate_base_24g[path][txnum][1];
313 value = rtlphy->txpwr_by_rate_base_24g[path][txnum][2];
316 value = rtlphy->txpwr_by_rate_base_24g[path][txnum][3];
319 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
320 "Invalid RateSection %d in Band 2.4G, Rf Path %d, %dTx in PHY_GetTxPowerByRateBase()\n",
321 rate_section, path, txnum);
325 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
326 "Invalid Band %d in PHY_GetTxPowerByRateBase()\n",
333 static void _rtl8723be_phy_store_txpower_by_rate_base(struct ieee80211_hw *hw)
335 struct rtl_priv *rtlpriv = rtl_priv(hw);
336 struct rtl_phy *rtlphy = &rtlpriv->phy;
338 u8 base = 0, path = 0;
340 for (path = RF90_PATH_A; path <= RF90_PATH_B; ++path) {
341 if (path == RF90_PATH_A) {
342 rawvalue = (u16)(rtlphy->tx_power_by_rate_offset
343 [BAND_ON_2_4G][path][RF_1TX][3] >> 24) & 0xFF;
344 base = (rawvalue >> 4) * 10 + (rawvalue & 0xF);
345 _rtl8723be_phy_set_txpower_by_rate_base(hw,
346 BAND_ON_2_4G, path, CCK, RF_1TX, base);
347 } else if (path == RF90_PATH_B) {
348 rawvalue = (u16)(rtlphy->tx_power_by_rate_offset
349 [BAND_ON_2_4G][path][RF_1TX][3] >> 0) & 0xFF;
350 base = (rawvalue >> 4) * 10 + (rawvalue & 0xF);
351 _rtl8723be_phy_set_txpower_by_rate_base(hw,
356 rawvalue = (u16)(rtlphy->tx_power_by_rate_offset
357 [BAND_ON_2_4G][path][RF_1TX][1] >> 24) & 0xFF;
358 base = (rawvalue >> 4) * 10 + (rawvalue & 0xF);
359 _rtl8723be_phy_set_txpower_by_rate_base(hw, BAND_ON_2_4G,
363 rawvalue = (u16)(rtlphy->tx_power_by_rate_offset
364 [BAND_ON_2_4G][path][RF_1TX][5] >> 24) & 0xFF;
365 base = (rawvalue >> 4) * 10 + (rawvalue & 0xF);
366 _rtl8723be_phy_set_txpower_by_rate_base(hw, BAND_ON_2_4G,
370 rawvalue = (u16)(rtlphy->tx_power_by_rate_offset
371 [BAND_ON_2_4G][path][RF_2TX][7] >> 24) & 0xFF;
372 base = (rawvalue >> 4) * 10 + (rawvalue & 0xF);
373 _rtl8723be_phy_set_txpower_by_rate_base(hw, BAND_ON_2_4G,
379 static void _phy_convert_txpower_dbm_to_relative_value(u32 *data, u8 start,
386 for (i = 3; i >= 0; --i) {
387 if (i >= start && i <= end) {
388 /* Get the exact value */
389 temp_value = (u8)(*data >> (i * 8)) & 0xF;
390 temp_value += ((u8)((*data >> (i*8 + 4)) & 0xF)) * 10;
392 /* Change the value to a relative value */
393 temp_value = (temp_value > base_val) ?
394 temp_value - base_val :
395 base_val - temp_value;
397 temp_value = (u8)(*data >> (i * 8)) & 0xFF;
400 temp_data |= temp_value;
405 static void _rtl8723be_phy_convert_txpower_dbm_to_relative_value(
406 struct ieee80211_hw *hw)
408 struct rtl_priv *rtlpriv = rtl_priv(hw);
409 struct rtl_phy *rtlphy = &rtlpriv->phy;
410 u8 base = 0, rfpath = RF90_PATH_A;
412 base = _rtl8723be_phy_get_txpower_by_rate_base(hw,
413 BAND_ON_2_4G, rfpath, RF_1TX, CCK);
414 _phy_convert_txpower_dbm_to_relative_value(
415 &rtlphy->tx_power_by_rate_offset[BAND_ON_2_4G][rfpath][RF_1TX][2],
417 _phy_convert_txpower_dbm_to_relative_value(
418 &rtlphy->tx_power_by_rate_offset[BAND_ON_2_4G][rfpath][RF_1TX][3],
421 base = _rtl8723be_phy_get_txpower_by_rate_base(hw, BAND_ON_2_4G, rfpath,
423 _phy_convert_txpower_dbm_to_relative_value(
424 &rtlphy->tx_power_by_rate_offset[BAND_ON_2_4G][rfpath][RF_1TX][0],
426 _phy_convert_txpower_dbm_to_relative_value(
427 &rtlphy->tx_power_by_rate_offset[BAND_ON_2_4G][rfpath][RF_1TX][1],
430 base = _rtl8723be_phy_get_txpower_by_rate_base(hw, BAND_ON_2_4G,
431 rfpath, RF_1TX, HT_MCS0_MCS7);
432 _phy_convert_txpower_dbm_to_relative_value(
433 &rtlphy->tx_power_by_rate_offset[BAND_ON_2_4G][rfpath][RF_1TX][4],
435 _phy_convert_txpower_dbm_to_relative_value(
436 &rtlphy->tx_power_by_rate_offset[BAND_ON_2_4G][rfpath][RF_1TX][5],
439 base = _rtl8723be_phy_get_txpower_by_rate_base(hw, BAND_ON_2_4G,
442 _phy_convert_txpower_dbm_to_relative_value(
443 &rtlphy->tx_power_by_rate_offset[BAND_ON_2_4G][rfpath][RF_2TX][6],
446 _phy_convert_txpower_dbm_to_relative_value(
447 &rtlphy->tx_power_by_rate_offset[BAND_ON_2_4G][rfpath][RF_2TX][7],
450 RT_TRACE(rtlpriv, COMP_POWER, DBG_TRACE,
451 "<===_rtl8723be_phy_convert_txpower_dbm_to_relative_value()\n");
454 static void phy_txpower_by_rate_config(struct ieee80211_hw *hw)
456 _rtl8723be_phy_store_txpower_by_rate_base(hw);
457 _rtl8723be_phy_convert_txpower_dbm_to_relative_value(hw);
460 static bool _rtl8723be_phy_bb8723b_config_parafile(struct ieee80211_hw *hw)
462 struct rtl_priv *rtlpriv = rtl_priv(hw);
463 struct rtl_phy *rtlphy = &rtlpriv->phy;
464 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
467 rtstatus = _rtl8723be_phy_config_bb_with_headerfile(hw,
468 BASEBAND_CONFIG_PHY_REG);
470 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "Write BB Reg Fail!!");
473 _rtl8723be_phy_init_tx_power_by_rate(hw);
474 if (!rtlefuse->autoload_failflag) {
475 rtlphy->pwrgroup_cnt = 0;
476 rtstatus = _rtl8723be_phy_config_bb_with_pgheaderfile(hw,
477 BASEBAND_CONFIG_PHY_REG);
479 phy_txpower_by_rate_config(hw);
481 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "BB_PG Reg Fail!!");
484 rtstatus = _rtl8723be_phy_config_bb_with_headerfile(hw,
485 BASEBAND_CONFIG_AGC_TAB);
487 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "AGC Table Fail\n");
490 rtlphy->cck_high_power = (bool)(rtl_get_bbreg(hw,
491 RFPGA0_XA_HSSIPARAMETER2,
496 static bool _rtl8723be_phy_config_mac_with_headerfile(struct ieee80211_hw *hw)
498 struct rtl_priv *rtlpriv = rtl_priv(hw);
503 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "Read rtl8723beMACPHY_Array\n");
504 arraylength = RTL8723BEMAC_1T_ARRAYLEN;
505 ptrarray = RTL8723BEMAC_1T_ARRAY;
506 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
507 "Img:RTL8723bEMAC_1T_ARRAY LEN %d\n", arraylength);
508 for (i = 0; i < arraylength; i = i + 2)
509 rtl_write_byte(rtlpriv, ptrarray[i], (u8)ptrarray[i + 1]);
513 static bool _rtl8723be_phy_config_bb_with_headerfile(struct ieee80211_hw *hw,
516 #define READ_NEXT_PAIR(v1, v2, i) \
519 v1 = array_table[i];\
520 v2 = array_table[i+1]; \
526 struct rtl_priv *rtlpriv = rtl_priv(hw);
529 if (configtype == BASEBAND_CONFIG_PHY_REG) {
530 arraylen = RTL8723BEPHY_REG_1TARRAYLEN;
531 array_table = RTL8723BEPHY_REG_1TARRAY;
533 for (i = 0; i < arraylen; i = i + 2) {
535 v2 = array_table[i+1];
536 if (v1 < 0xcdcdcdcd) {
537 _rtl8723be_config_bb_reg(hw, v1, v2);
538 } else {/*This line is the start line of branch.*/
539 /* to protect READ_NEXT_PAIR not overrun */
540 if (i >= arraylen - 2)
543 if (!_rtl8723be_check_condition(hw,
545 /*Discard the following
546 *(offset, data) pairs
548 READ_NEXT_PAIR(v1, v2, i);
549 while (v2 != 0xDEAD &&
553 READ_NEXT_PAIR(v1, v2, i);
555 i -= 2; /* prevent from for-loop += 2*/
556 /*Configure matched pairs and
557 *skip to end of if-else.
560 READ_NEXT_PAIR(v1, v2, i);
561 while (v2 != 0xDEAD &&
565 _rtl8723be_config_bb_reg(hw,
567 READ_NEXT_PAIR(v1, v2, i);
570 while (v2 != 0xDEAD && i < arraylen - 2)
571 READ_NEXT_PAIR(v1, v2, i);
575 } else if (configtype == BASEBAND_CONFIG_AGC_TAB) {
576 arraylen = RTL8723BEAGCTAB_1TARRAYLEN;
577 array_table = RTL8723BEAGCTAB_1TARRAY;
579 for (i = 0; i < arraylen; i = i + 2) {
581 v2 = array_table[i+1];
582 if (v1 < 0xCDCDCDCD) {
583 rtl_set_bbreg(hw, array_table[i],
588 } else {/*This line is the start line of branch.*/
589 /* to protect READ_NEXT_PAIR not overrun */
590 if (i >= arraylen - 2)
593 if (!_rtl8723be_check_condition(hw,
595 /*Discard the following
596 *(offset, data) pairs
598 READ_NEXT_PAIR(v1, v2, i);
599 while (v2 != 0xDEAD &&
603 READ_NEXT_PAIR(v1, v2, i);
605 i -= 2; /* prevent from for-loop += 2*/
606 /*Configure matched pairs and
607 *skip to end of if-else.
610 READ_NEXT_PAIR(v1, v2, i);
611 while (v2 != 0xDEAD &&
615 rtl_set_bbreg(hw, array_table[i],
619 READ_NEXT_PAIR(v1, v2, i);
622 while (v2 != 0xDEAD && i < arraylen - 2)
623 READ_NEXT_PAIR(v1, v2, i);
626 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
627 "The agctab_array_table[0] is %x Rtl818EEPHY_REGArray[1] is %x\n",
628 array_table[i], array_table[i + 1]);
634 static u8 _rtl8723be_get_rate_section_index(u32 regaddr)
639 case RTXAGC_A_RATE18_06:
642 case RTXAGC_A_RATE54_24:
645 case RTXAGC_A_CCK1_MCS32:
648 case RTXAGC_B_CCK11_A_CCK2_11:
651 case RTXAGC_A_MCS03_MCS00:
654 case RTXAGC_A_MCS07_MCS04:
657 case RTXAGC_A_MCS11_MCS08:
660 case RTXAGC_A_MCS15_MCS12:
663 case RTXAGC_B_RATE18_06:
666 case RTXAGC_B_RATE54_24:
669 case RTXAGC_B_CCK1_55_MCS32:
672 case RTXAGC_B_MCS03_MCS00:
675 case RTXAGC_B_MCS07_MCS04:
678 case RTXAGC_B_MCS11_MCS08:
681 case RTXAGC_B_MCS15_MCS12:
686 if (regaddr >= 0xC20 && regaddr <= 0xC4C)
687 index = (u8)((regaddr - 0xC20) / 4);
688 else if (regaddr >= 0xE20 && regaddr <= 0xE4C)
689 index = (u8)((regaddr - 0xE20) / 4);
695 static void _rtl8723be_store_tx_power_by_rate(struct ieee80211_hw *hw,
696 u32 band, u32 rfpath,
697 u32 txnum, u32 regaddr,
698 u32 bitmask, u32 data)
700 struct rtl_priv *rtlpriv = rtl_priv(hw);
701 struct rtl_phy *rtlphy = &rtlpriv->phy;
702 u8 rate_section = _rtl8723be_get_rate_section_index(regaddr);
704 if (band != BAND_ON_2_4G && band != BAND_ON_5G) {
705 RT_TRACE(rtlpriv, FPHY, PHY_TXPWR, "Invalid Band %d\n", band);
708 if (rfpath > MAX_RF_PATH - 1) {
709 RT_TRACE(rtlpriv, FPHY, PHY_TXPWR,
710 "Invalid RfPath %d\n", rfpath);
713 if (txnum > MAX_RF_PATH - 1) {
714 RT_TRACE(rtlpriv, FPHY, PHY_TXPWR, "Invalid TxNum %d\n", txnum);
718 rtlphy->tx_power_by_rate_offset[band][rfpath][txnum][rate_section] =
723 static bool _rtl8723be_phy_config_bb_with_pgheaderfile(struct ieee80211_hw *hw,
726 struct rtl_priv *rtlpriv = rtl_priv(hw);
728 u32 *phy_regarray_table_pg;
729 u16 phy_regarray_pg_len;
730 u32 v1 = 0, v2 = 0, v3 = 0, v4 = 0, v5 = 0, v6 = 0;
732 phy_regarray_pg_len = RTL8723BEPHY_REG_ARRAY_PGLEN;
733 phy_regarray_table_pg = RTL8723BEPHY_REG_ARRAY_PG;
735 if (configtype == BASEBAND_CONFIG_PHY_REG) {
736 for (i = 0; i < phy_regarray_pg_len; i = i + 6) {
737 v1 = phy_regarray_table_pg[i];
738 v2 = phy_regarray_table_pg[i+1];
739 v3 = phy_regarray_table_pg[i+2];
740 v4 = phy_regarray_table_pg[i+3];
741 v5 = phy_regarray_table_pg[i+4];
742 v6 = phy_regarray_table_pg[i+5];
744 if (v1 < 0xcdcdcdcd) {
745 if (phy_regarray_table_pg[i] == 0xfe ||
746 phy_regarray_table_pg[i] == 0xffe)
749 _rtl8723be_store_tx_power_by_rate(hw,
750 v1, v2, v3, v4, v5, v6);
755 RT_TRACE(rtlpriv, COMP_SEND, DBG_TRACE,
756 "configtype != BaseBand_Config_PHY_REG\n");
761 bool rtl8723be_phy_config_rf_with_headerfile(struct ieee80211_hw *hw,
762 enum radio_path rfpath)
764 #define READ_NEXT_RF_PAIR(v1, v2, i) \
767 v1 = radioa_array_table[i]; \
768 v2 = radioa_array_table[i+1]; \
772 bool rtstatus = true;
773 u32 *radioa_array_table;
775 struct rtl_priv *rtlpriv = rtl_priv(hw);
776 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
779 radioa_arraylen = RTL8723BE_RADIOA_1TARRAYLEN;
780 radioa_array_table = RTL8723BE_RADIOA_1TARRAY;
781 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
782 "Radio_A:RTL8723BE_RADIOA_1TARRAY %d\n", radioa_arraylen);
783 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Radio No %x\n", rfpath);
787 for (i = 0; i < radioa_arraylen; i = i + 2) {
788 v1 = radioa_array_table[i];
789 v2 = radioa_array_table[i+1];
790 if (v1 < 0xcdcdcdcd) {
791 _rtl8723be_config_rf_radio_a(hw, v1, v2);
792 } else {/*This line is the start line of branch.*/
793 /* to protect READ_NEXT_PAIR not overrun */
794 if (i >= radioa_arraylen - 2)
797 if (!_rtl8723be_check_condition(hw,
798 radioa_array_table[i])) {
799 /*Discard the following
800 *(offset, data) pairs
802 READ_NEXT_RF_PAIR(v1, v2, i);
803 while (v2 != 0xDEAD &&
806 i < radioa_arraylen - 2) {
807 READ_NEXT_RF_PAIR(v1, v2, i);
809 i -= 2; /* prevent from for-loop += 2*/
811 /*Configure matched pairs
812 *and skip to end of if-else.
814 READ_NEXT_RF_PAIR(v1, v2, i);
815 while (v2 != 0xDEAD &&
818 i < radioa_arraylen - 2) {
819 _rtl8723be_config_rf_radio_a(hw,
821 READ_NEXT_RF_PAIR(v1, v2, i);
824 while (v2 != 0xDEAD &&
825 i < radioa_arraylen - 2) {
826 READ_NEXT_RF_PAIR(v1, v2, i);
832 if (rtlhal->oem_id == RT_CID_819X_HP)
833 _rtl8723be_config_rf_radio_a(hw, 0x52, 0x7E4BD);
839 RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
840 "switch case not process\n");
846 void rtl8723be_phy_get_hw_reg_originalvalue(struct ieee80211_hw *hw)
848 struct rtl_priv *rtlpriv = rtl_priv(hw);
849 struct rtl_phy *rtlphy = &rtlpriv->phy;
851 rtlphy->default_initialgain[0] =
852 (u8)rtl_get_bbreg(hw, ROFDM0_XAAGCCORE1, MASKBYTE0);
853 rtlphy->default_initialgain[1] =
854 (u8)rtl_get_bbreg(hw, ROFDM0_XBAGCCORE1, MASKBYTE0);
855 rtlphy->default_initialgain[2] =
856 (u8)rtl_get_bbreg(hw, ROFDM0_XCAGCCORE1, MASKBYTE0);
857 rtlphy->default_initialgain[3] =
858 (u8)rtl_get_bbreg(hw, ROFDM0_XDAGCCORE1, MASKBYTE0);
860 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
861 "Default initial gain (c50=0x%x, c58=0x%x, c60=0x%x, c68=0x%x\n",
862 rtlphy->default_initialgain[0],
863 rtlphy->default_initialgain[1],
864 rtlphy->default_initialgain[2],
865 rtlphy->default_initialgain[3]);
867 rtlphy->framesync = (u8)rtl_get_bbreg(hw, ROFDM0_RXDETECTOR3,
869 rtlphy->framesync_c34 = rtl_get_bbreg(hw, ROFDM0_RXDETECTOR2,
872 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
873 "Default framesync (0x%x) = 0x%x\n",
874 ROFDM0_RXDETECTOR3, rtlphy->framesync);
877 void rtl8723be_phy_get_txpower_level(struct ieee80211_hw *hw, long *powerlevel)
879 struct rtl_priv *rtlpriv = rtl_priv(hw);
880 struct rtl_phy *rtlphy = &rtlpriv->phy;
884 txpwr_level = rtlphy->cur_cck_txpwridx;
885 txpwr_dbm = rtl8723_phy_txpwr_idx_to_dbm(hw, WIRELESS_MODE_B,
887 txpwr_level = rtlphy->cur_ofdm24g_txpwridx;
888 if (rtl8723_phy_txpwr_idx_to_dbm(hw, WIRELESS_MODE_G, txpwr_level) >
891 rtl8723_phy_txpwr_idx_to_dbm(hw, WIRELESS_MODE_G,
893 txpwr_level = rtlphy->cur_ofdm24g_txpwridx;
894 if (rtl8723_phy_txpwr_idx_to_dbm(hw, WIRELESS_MODE_N_24G,
895 txpwr_level) > txpwr_dbm)
897 rtl8723_phy_txpwr_idx_to_dbm(hw, WIRELESS_MODE_N_24G,
899 *powerlevel = txpwr_dbm;
902 static u8 _rtl8723be_phy_get_ratesection_intxpower_byrate(enum radio_path path,
913 case DESC92C_RATE5_5M:
914 if (path == RF90_PATH_A)
916 else if (path == RF90_PATH_B)
920 case DESC92C_RATE11M:
926 case DESC92C_RATE12M:
927 case DESC92C_RATE18M:
931 case DESC92C_RATE24M:
932 case DESC92C_RATE36M:
933 case DESC92C_RATE48M:
934 case DESC92C_RATE54M:
938 case DESC92C_RATEMCS0:
939 case DESC92C_RATEMCS1:
940 case DESC92C_RATEMCS2:
941 case DESC92C_RATEMCS3:
945 case DESC92C_RATEMCS4:
946 case DESC92C_RATEMCS5:
947 case DESC92C_RATEMCS6:
948 case DESC92C_RATEMCS7:
952 case DESC92C_RATEMCS8:
953 case DESC92C_RATEMCS9:
954 case DESC92C_RATEMCS10:
955 case DESC92C_RATEMCS11:
959 case DESC92C_RATEMCS12:
960 case DESC92C_RATEMCS13:
961 case DESC92C_RATEMCS14:
962 case DESC92C_RATEMCS15:
967 RT_ASSERT(true, "Rate_Section is Illegal\n");
974 static u8 _rtl8723be_get_txpower_by_rate(struct ieee80211_hw *hw,
976 enum radio_path rfpath, u8 rate)
978 struct rtl_priv *rtlpriv = rtl_priv(hw);
979 struct rtl_phy *rtlphy = &rtlpriv->phy;
980 u8 shift = 0, rate_section, tx_num;
981 char tx_pwr_diff = 0;
983 rate_section = _rtl8723be_phy_get_ratesection_intxpower_byrate(rfpath,
985 tx_num = RF_TX_NUM_NONIMPLEMENT;
987 if (tx_num == RF_TX_NUM_NONIMPLEMENT) {
988 if (rate >= DESC92C_RATEMCS8 && rate <= DESC92C_RATEMCS15)
996 case DESC92C_RATE24M:
997 case DESC92C_RATEMCS0:
998 case DESC92C_RATEMCS4:
999 case DESC92C_RATEMCS8:
1000 case DESC92C_RATEMCS12:
1003 case DESC92C_RATE1M:
1004 case DESC92C_RATE2M:
1005 case DESC92C_RATE9M:
1006 case DESC92C_RATE36M:
1007 case DESC92C_RATEMCS1:
1008 case DESC92C_RATEMCS5:
1009 case DESC92C_RATEMCS9:
1010 case DESC92C_RATEMCS13:
1013 case DESC92C_RATE5_5M:
1014 case DESC92C_RATE12M:
1015 case DESC92C_RATE48M:
1016 case DESC92C_RATEMCS2:
1017 case DESC92C_RATEMCS6:
1018 case DESC92C_RATEMCS10:
1019 case DESC92C_RATEMCS14:
1022 case DESC92C_RATE11M:
1023 case DESC92C_RATE18M:
1024 case DESC92C_RATE54M:
1025 case DESC92C_RATEMCS3:
1026 case DESC92C_RATEMCS7:
1027 case DESC92C_RATEMCS11:
1028 case DESC92C_RATEMCS15:
1032 RT_ASSERT(true, "Rate_Section is Illegal\n");
1035 tx_pwr_diff = (u8)(rtlphy->tx_power_by_rate_offset[band][rfpath][tx_num]
1036 [rate_section] >> shift) & 0xff;
1041 static u8 _rtl8723be_get_txpower_index(struct ieee80211_hw *hw, u8 path,
1042 u8 rate, u8 bandwidth, u8 channel)
1044 struct rtl_priv *rtlpriv = rtl_priv(hw);
1045 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1046 u8 index = (channel - 1);
1048 u8 power_diff_byrate = 0;
1050 if (channel > 14 || channel < 1) {
1052 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
1053 "Illegal channel!\n");
1055 if (RX_HAL_IS_CCK_RATE(rate))
1056 txpower = rtlefuse->txpwrlevel_cck[path][index];
1057 else if (DESC92C_RATE6M <= rate)
1058 txpower = rtlefuse->txpwrlevel_ht40_1s[path][index];
1060 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
1063 if (DESC92C_RATE6M <= rate && rate <= DESC92C_RATE54M &&
1064 !RX_HAL_IS_CCK_RATE(rate))
1065 txpower += rtlefuse->txpwr_legacyhtdiff[0][TX_1S];
1067 if (bandwidth == HT_CHANNEL_WIDTH_20) {
1068 if (DESC92C_RATEMCS0 <= rate && rate <= DESC92C_RATEMCS15)
1069 txpower += rtlefuse->txpwr_ht20diff[0][TX_1S];
1070 if (DESC92C_RATEMCS8 <= rate && rate <= DESC92C_RATEMCS15)
1071 txpower += rtlefuse->txpwr_ht20diff[0][TX_2S];
1072 } else if (bandwidth == HT_CHANNEL_WIDTH_20_40) {
1073 if (DESC92C_RATEMCS0 <= rate && rate <= DESC92C_RATEMCS15)
1074 txpower += rtlefuse->txpwr_ht40diff[0][TX_1S];
1075 if (DESC92C_RATEMCS8 <= rate && rate <= DESC92C_RATEMCS15)
1076 txpower += rtlefuse->txpwr_ht40diff[0][TX_2S];
1079 if (rtlefuse->eeprom_regulatory != 2)
1080 power_diff_byrate = _rtl8723be_get_txpower_by_rate(hw,
1084 txpower += power_diff_byrate;
1086 if (txpower > MAX_POWER_INDEX)
1087 txpower = MAX_POWER_INDEX;
1092 static void _rtl8723be_phy_set_txpower_index(struct ieee80211_hw *hw,
1093 u8 power_index, u8 path, u8 rate)
1095 struct rtl_priv *rtlpriv = rtl_priv(hw);
1096 if (path == RF90_PATH_A) {
1098 case DESC92C_RATE1M:
1099 rtl8723_phy_set_bb_reg(hw, RTXAGC_A_CCK1_MCS32,
1100 MASKBYTE1, power_index);
1102 case DESC92C_RATE2M:
1103 rtl8723_phy_set_bb_reg(hw, RTXAGC_B_CCK11_A_CCK2_11,
1104 MASKBYTE1, power_index);
1106 case DESC92C_RATE5_5M:
1107 rtl8723_phy_set_bb_reg(hw, RTXAGC_B_CCK11_A_CCK2_11,
1108 MASKBYTE2, power_index);
1110 case DESC92C_RATE11M:
1111 rtl8723_phy_set_bb_reg(hw, RTXAGC_B_CCK11_A_CCK2_11,
1112 MASKBYTE3, power_index);
1115 case DESC92C_RATE6M:
1116 rtl8723_phy_set_bb_reg(hw, RTXAGC_A_RATE18_06,
1117 MASKBYTE0, power_index);
1119 case DESC92C_RATE9M:
1120 rtl8723_phy_set_bb_reg(hw, RTXAGC_A_RATE18_06,
1121 MASKBYTE1, power_index);
1123 case DESC92C_RATE12M:
1124 rtl8723_phy_set_bb_reg(hw, RTXAGC_A_RATE18_06,
1125 MASKBYTE2, power_index);
1127 case DESC92C_RATE18M:
1128 rtl8723_phy_set_bb_reg(hw, RTXAGC_A_RATE18_06,
1129 MASKBYTE3, power_index);
1132 case DESC92C_RATE24M:
1133 rtl8723_phy_set_bb_reg(hw, RTXAGC_A_RATE54_24,
1134 MASKBYTE0, power_index);
1136 case DESC92C_RATE36M:
1137 rtl8723_phy_set_bb_reg(hw, RTXAGC_A_RATE54_24,
1138 MASKBYTE1, power_index);
1140 case DESC92C_RATE48M:
1141 rtl8723_phy_set_bb_reg(hw, RTXAGC_A_RATE54_24,
1142 MASKBYTE2, power_index);
1144 case DESC92C_RATE54M:
1145 rtl8723_phy_set_bb_reg(hw, RTXAGC_A_RATE54_24,
1146 MASKBYTE3, power_index);
1149 case DESC92C_RATEMCS0:
1150 rtl8723_phy_set_bb_reg(hw, RTXAGC_A_MCS03_MCS00,
1151 MASKBYTE0, power_index);
1153 case DESC92C_RATEMCS1:
1154 rtl8723_phy_set_bb_reg(hw, RTXAGC_A_MCS03_MCS00,
1155 MASKBYTE1, power_index);
1157 case DESC92C_RATEMCS2:
1158 rtl8723_phy_set_bb_reg(hw, RTXAGC_A_MCS03_MCS00,
1159 MASKBYTE2, power_index);
1161 case DESC92C_RATEMCS3:
1162 rtl8723_phy_set_bb_reg(hw, RTXAGC_A_MCS03_MCS00,
1163 MASKBYTE3, power_index);
1166 case DESC92C_RATEMCS4:
1167 rtl8723_phy_set_bb_reg(hw, RTXAGC_A_MCS07_MCS04,
1168 MASKBYTE0, power_index);
1170 case DESC92C_RATEMCS5:
1171 rtl8723_phy_set_bb_reg(hw, RTXAGC_A_MCS07_MCS04,
1172 MASKBYTE1, power_index);
1174 case DESC92C_RATEMCS6:
1175 rtl8723_phy_set_bb_reg(hw, RTXAGC_A_MCS07_MCS04,
1176 MASKBYTE2, power_index);
1178 case DESC92C_RATEMCS7:
1179 rtl8723_phy_set_bb_reg(hw, RTXAGC_A_MCS07_MCS04,
1180 MASKBYTE3, power_index);
1183 case DESC92C_RATEMCS8:
1184 rtl8723_phy_set_bb_reg(hw, RTXAGC_A_MCS11_MCS08,
1185 MASKBYTE0, power_index);
1187 case DESC92C_RATEMCS9:
1188 rtl8723_phy_set_bb_reg(hw, RTXAGC_A_MCS11_MCS08,
1189 MASKBYTE1, power_index);
1191 case DESC92C_RATEMCS10:
1192 rtl8723_phy_set_bb_reg(hw, RTXAGC_A_MCS11_MCS08,
1193 MASKBYTE2, power_index);
1195 case DESC92C_RATEMCS11:
1196 rtl8723_phy_set_bb_reg(hw, RTXAGC_A_MCS11_MCS08,
1197 MASKBYTE3, power_index);
1201 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD, "Invalid Rate!!\n");
1205 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD, "Invalid RFPath!!\n");
1209 void rtl8723be_phy_set_txpower_level(struct ieee80211_hw *hw, u8 channel)
1211 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1212 u8 cck_rates[] = {DESC92C_RATE1M, DESC92C_RATE2M,
1213 DESC92C_RATE5_5M, DESC92C_RATE11M};
1214 u8 ofdm_rates[] = {DESC92C_RATE6M, DESC92C_RATE9M,
1215 DESC92C_RATE12M, DESC92C_RATE18M,
1216 DESC92C_RATE24M, DESC92C_RATE36M,
1217 DESC92C_RATE48M, DESC92C_RATE54M};
1218 u8 ht_rates_1t[] = {DESC92C_RATEMCS0, DESC92C_RATEMCS1,
1219 DESC92C_RATEMCS2, DESC92C_RATEMCS3,
1220 DESC92C_RATEMCS4, DESC92C_RATEMCS5,
1221 DESC92C_RATEMCS6, DESC92C_RATEMCS7};
1225 if (!rtlefuse->txpwr_fromeprom)
1228 size = sizeof(cck_rates) / sizeof(u8);
1229 for (i = 0; i < size; i++) {
1230 power_index = _rtl8723be_get_txpower_index(hw, RF90_PATH_A,
1232 rtl_priv(hw)->phy.current_chan_bw,
1234 _rtl8723be_phy_set_txpower_index(hw, power_index, RF90_PATH_A,
1237 size = sizeof(ofdm_rates) / sizeof(u8);
1238 for (i = 0; i < size; i++) {
1239 power_index = _rtl8723be_get_txpower_index(hw, RF90_PATH_A,
1241 rtl_priv(hw)->phy.current_chan_bw,
1243 _rtl8723be_phy_set_txpower_index(hw, power_index, RF90_PATH_A,
1246 size = sizeof(ht_rates_1t) / sizeof(u8);
1247 for (i = 0; i < size; i++) {
1248 power_index = _rtl8723be_get_txpower_index(hw, RF90_PATH_A,
1250 rtl_priv(hw)->phy.current_chan_bw,
1252 _rtl8723be_phy_set_txpower_index(hw, power_index, RF90_PATH_A,
1257 void rtl8723be_phy_scan_operation_backup(struct ieee80211_hw *hw, u8 operation)
1259 struct rtl_priv *rtlpriv = rtl_priv(hw);
1260 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1261 enum io_type iotype;
1263 if (!is_hal_stop(rtlhal)) {
1264 switch (operation) {
1265 case SCAN_OPT_BACKUP_BAND0:
1266 iotype = IO_CMD_PAUSE_BAND0_DM_BY_SCAN;
1267 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_IO_CMD,
1271 case SCAN_OPT_RESTORE:
1272 iotype = IO_CMD_RESUME_DM_BY_SCAN;
1273 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_IO_CMD,
1277 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1278 "Unknown Scan Backup operation.\n");
1284 void rtl8723be_phy_set_bw_mode_callback(struct ieee80211_hw *hw)
1286 struct rtl_priv *rtlpriv = rtl_priv(hw);
1287 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1288 struct rtl_phy *rtlphy = &rtlpriv->phy;
1289 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1293 RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE,
1294 "Switch to %s bandwidth\n",
1295 rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20 ?
1298 if (is_hal_stop(rtlhal)) {
1299 rtlphy->set_bwmode_inprogress = false;
1303 reg_bw_opmode = rtl_read_byte(rtlpriv, REG_BWOPMODE);
1304 reg_prsr_rsc = rtl_read_byte(rtlpriv, REG_RRSR + 2);
1306 switch (rtlphy->current_chan_bw) {
1307 case HT_CHANNEL_WIDTH_20:
1308 reg_bw_opmode |= BW_OPMODE_20MHZ;
1309 rtl_write_byte(rtlpriv, REG_BWOPMODE, reg_bw_opmode);
1311 case HT_CHANNEL_WIDTH_20_40:
1312 reg_bw_opmode &= ~BW_OPMODE_20MHZ;
1313 rtl_write_byte(rtlpriv, REG_BWOPMODE, reg_bw_opmode);
1314 reg_prsr_rsc = (reg_prsr_rsc & 0x90) |
1315 (mac->cur_40_prime_sc << 5);
1316 rtl_write_byte(rtlpriv, REG_RRSR + 2, reg_prsr_rsc);
1319 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1320 "unknown bandwidth: %#X\n", rtlphy->current_chan_bw);
1324 switch (rtlphy->current_chan_bw) {
1325 case HT_CHANNEL_WIDTH_20:
1326 rtl_set_bbreg(hw, RFPGA0_RFMOD, BRFMOD, 0x0);
1327 rtl_set_bbreg(hw, RFPGA1_RFMOD, BRFMOD, 0x0);
1328 /* rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10), 1);*/
1330 case HT_CHANNEL_WIDTH_20_40:
1331 rtl_set_bbreg(hw, RFPGA0_RFMOD, BRFMOD, 0x1);
1332 rtl_set_bbreg(hw, RFPGA1_RFMOD, BRFMOD, 0x1);
1334 rtl_set_bbreg(hw, RCCK0_SYSTEM, BCCK_SIDEBAND,
1335 (mac->cur_40_prime_sc >> 1));
1336 rtl_set_bbreg(hw, ROFDM1_LSTF, 0xC00, mac->cur_40_prime_sc);
1337 /*rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10), 0);*/
1339 rtl_set_bbreg(hw, 0x818, (BIT(26) | BIT(27)),
1340 (mac->cur_40_prime_sc ==
1341 HAL_PRIME_CHNL_OFFSET_LOWER) ? 2 : 1);
1344 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1345 "unknown bandwidth: %#X\n", rtlphy->current_chan_bw);
1348 rtl8723be_phy_rf6052_set_bandwidth(hw, rtlphy->current_chan_bw);
1349 rtlphy->set_bwmode_inprogress = false;
1350 RT_TRACE(rtlpriv, COMP_SCAN, DBG_LOUD, "\n");
1353 void rtl8723be_phy_set_bw_mode(struct ieee80211_hw *hw,
1354 enum nl80211_channel_type ch_type)
1356 struct rtl_priv *rtlpriv = rtl_priv(hw);
1357 struct rtl_phy *rtlphy = &rtlpriv->phy;
1358 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1359 u8 tmp_bw = rtlphy->current_chan_bw;
1361 if (rtlphy->set_bwmode_inprogress)
1363 rtlphy->set_bwmode_inprogress = true;
1364 if ((!is_hal_stop(rtlhal)) && !(RT_CANNOT_IO(hw))) {
1365 rtl8723be_phy_set_bw_mode_callback(hw);
1367 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1368 "false driver sleep or unload\n");
1369 rtlphy->set_bwmode_inprogress = false;
1370 rtlphy->current_chan_bw = tmp_bw;
1374 void rtl8723be_phy_sw_chnl_callback(struct ieee80211_hw *hw)
1376 struct rtl_priv *rtlpriv = rtl_priv(hw);
1377 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1378 struct rtl_phy *rtlphy = &rtlpriv->phy;
1381 RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE,
1382 "switch to channel%d\n", rtlphy->current_channel);
1383 if (is_hal_stop(rtlhal))
1386 if (!rtlphy->sw_chnl_inprogress)
1388 if (!_rtl8723be_phy_sw_chnl_step_by_step(hw,
1389 rtlphy->current_channel,
1390 &rtlphy->sw_chnl_stage,
1391 &rtlphy->sw_chnl_step,
1398 rtlphy->sw_chnl_inprogress = false;
1402 RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE, "\n");
1405 u8 rtl8723be_phy_sw_chnl(struct ieee80211_hw *hw)
1407 struct rtl_priv *rtlpriv = rtl_priv(hw);
1408 struct rtl_phy *rtlphy = &rtlpriv->phy;
1409 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1411 if (rtlphy->sw_chnl_inprogress)
1413 if (rtlphy->set_bwmode_inprogress)
1415 RT_ASSERT((rtlphy->current_channel <= 14),
1416 "WIRELESS_MODE_G but channel>14");
1417 rtlphy->sw_chnl_inprogress = true;
1418 rtlphy->sw_chnl_stage = 0;
1419 rtlphy->sw_chnl_step = 0;
1420 if (!(is_hal_stop(rtlhal)) && !(RT_CANNOT_IO(hw))) {
1421 rtl8723be_phy_sw_chnl_callback(hw);
1422 RT_TRACE(rtlpriv, COMP_CHAN, DBG_LOUD,
1423 "sw_chnl_inprogress false schdule workitem current channel %d\n",
1424 rtlphy->current_channel);
1425 rtlphy->sw_chnl_inprogress = false;
1427 RT_TRACE(rtlpriv, COMP_CHAN, DBG_LOUD,
1428 "sw_chnl_inprogress false driver sleep or unload\n");
1429 rtlphy->sw_chnl_inprogress = false;
1434 static bool _rtl8723be_phy_sw_chnl_step_by_step(struct ieee80211_hw *hw,
1435 u8 channel, u8 *stage,
1436 u8 *step, u32 *delay)
1438 struct rtl_priv *rtlpriv = rtl_priv(hw);
1439 struct rtl_phy *rtlphy = &rtlpriv->phy;
1440 struct swchnlcmd precommoncmd[MAX_PRECMD_CNT];
1441 u32 precommoncmdcnt;
1442 struct swchnlcmd postcommoncmd[MAX_POSTCMD_CNT];
1443 u32 postcommoncmdcnt;
1444 struct swchnlcmd rfdependcmd[MAX_RFDEPENDCMD_CNT];
1446 struct swchnlcmd *currentcmd = NULL;
1448 u8 num_total_rfpath = rtlphy->num_total_rfpath;
1450 precommoncmdcnt = 0;
1451 rtl8723_phy_set_sw_chnl_cmdarray(precommoncmd, precommoncmdcnt++,
1453 CMDID_SET_TXPOWEROWER_LEVEL,
1455 rtl8723_phy_set_sw_chnl_cmdarray(precommoncmd, precommoncmdcnt++,
1456 MAX_PRECMD_CNT, CMDID_END, 0, 0, 0);
1458 postcommoncmdcnt = 0;
1460 rtl8723_phy_set_sw_chnl_cmdarray(postcommoncmd, postcommoncmdcnt++,
1461 MAX_POSTCMD_CNT, CMDID_END,
1466 RT_ASSERT((channel >= 1 && channel <= 14),
1467 "illegal channel for Zebra: %d\n", channel);
1469 rtl8723_phy_set_sw_chnl_cmdarray(rfdependcmd, rfdependcmdcnt++,
1470 MAX_RFDEPENDCMD_CNT,
1472 RF_CHNLBW, channel, 10);
1474 rtl8723_phy_set_sw_chnl_cmdarray(rfdependcmd, rfdependcmdcnt++,
1475 MAX_RFDEPENDCMD_CNT,
1476 CMDID_END, 0, 0, 0);
1481 currentcmd = &precommoncmd[*step];
1484 currentcmd = &rfdependcmd[*step];
1487 currentcmd = &postcommoncmd[*step];
1490 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1491 "Invalid 'stage' = %d, Check it!\n", *stage);
1495 if (currentcmd->cmdid == CMDID_END) {
1496 if ((*stage) == 2) {
1505 switch (currentcmd->cmdid) {
1506 case CMDID_SET_TXPOWEROWER_LEVEL:
1507 rtl8723be_phy_set_txpower_level(hw, channel);
1509 case CMDID_WRITEPORT_ULONG:
1510 rtl_write_dword(rtlpriv, currentcmd->para1,
1513 case CMDID_WRITEPORT_USHORT:
1514 rtl_write_word(rtlpriv, currentcmd->para1,
1515 (u16)currentcmd->para2);
1517 case CMDID_WRITEPORT_UCHAR:
1518 rtl_write_byte(rtlpriv, currentcmd->para1,
1519 (u8)currentcmd->para2);
1521 case CMDID_RF_WRITEREG:
1522 for (rfpath = 0; rfpath < num_total_rfpath; rfpath++) {
1523 rtlphy->rfreg_chnlval[rfpath] =
1524 ((rtlphy->rfreg_chnlval[rfpath] &
1525 0xfffffc00) | currentcmd->para2);
1527 rtl_set_rfreg(hw, (enum radio_path)rfpath,
1530 rtlphy->rfreg_chnlval[rfpath]);
1534 RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
1535 "switch case not process\n");
1542 (*delay) = currentcmd->msdelay;
1547 static u8 _rtl8723be_phy_path_a_iqk(struct ieee80211_hw *hw)
1549 u32 reg_eac, reg_e94, reg_e9c, tmp;
1552 /* leave IQK mode */
1553 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000);
1554 /* switch to path A */
1555 rtl_set_bbreg(hw, 0x948, MASKDWORD, 0x00000000);
1556 /* enable path A PA in TXIQK mode */
1557 rtl_set_rfreg(hw, RF90_PATH_A, RF_WE_LUT, RFREG_OFFSET_MASK, 0x800a0);
1558 rtl_set_rfreg(hw, RF90_PATH_A, RF_RCK_OS, RFREG_OFFSET_MASK, 0x20000);
1559 rtl_set_rfreg(hw, RF90_PATH_A, RF_TXPA_G1, RFREG_OFFSET_MASK, 0x0003f);
1560 rtl_set_rfreg(hw, RF90_PATH_A, RF_TXPA_G2, RFREG_OFFSET_MASK, 0xc7f87);
1563 /* path-A IQK setting */
1565 rtl_set_bbreg(hw, RTX_IQK, MASKDWORD, 0x01007c00);
1566 rtl_set_bbreg(hw, RRX_IQK, MASKDWORD, 0x01004800);
1567 /* path-A IQK setting */
1568 rtl_set_bbreg(hw, RTX_IQK_TONE_A, MASKDWORD, 0x18008c1c);
1569 rtl_set_bbreg(hw, RRX_IQK_TONE_A, MASKDWORD, 0x38008c1c);
1570 rtl_set_bbreg(hw, RTX_IQK_TONE_B, MASKDWORD, 0x38008c1c);
1571 rtl_set_bbreg(hw, RRX_IQK_TONE_B, MASKDWORD, 0x38008c1c);
1573 rtl_set_bbreg(hw, RTX_IQK_PI_A, MASKDWORD, 0x821403ea);
1574 rtl_set_bbreg(hw, RRX_IQK_PI_A, MASKDWORD, 0x28160000);
1575 rtl_set_bbreg(hw, RTX_IQK_PI_B, MASKDWORD, 0x82110000);
1576 rtl_set_bbreg(hw, RRX_IQK_PI_B, MASKDWORD, 0x28110000);
1577 /* LO calibration setting */
1578 rtl_set_bbreg(hw, RIQK_AGC_RSP, MASKDWORD, 0x00462911);
1579 /* enter IQK mode */
1580 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000);
1582 /* One shot, path A LOK & IQK */
1583 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf9000000);
1584 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf8000000);
1586 mdelay(IQK_DELAY_TIME);
1588 /* leave IQK mode */
1589 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000);
1592 reg_eac = rtl_get_bbreg(hw, 0xeac, MASKDWORD);
1593 reg_e94 = rtl_get_bbreg(hw, 0xe94, MASKDWORD);
1594 reg_e9c = rtl_get_bbreg(hw, 0xe9c, MASKDWORD);
1596 if (!(reg_eac & BIT(28)) &&
1597 (((reg_e94 & 0x03FF0000) >> 16) != 0x142) &&
1598 (((reg_e9c & 0x03FF0000) >> 16) != 0x42))
1600 else /* if Tx not OK, ignore Rx */
1603 /* Allen 20131125 */
1604 tmp = (reg_e9c & 0x03FF0000) >> 16;
1605 if ((tmp & 0x200) > 0)
1608 if (!(reg_eac & BIT(28)) &&
1609 (((reg_e94 & 0x03FF0000) >> 16) < 0x110) &&
1610 (((reg_e94 & 0x03FF0000) >> 16) > 0xf0) &&
1613 else /* if Tx not OK, ignore Rx */
1619 /* bit0 = 1 => Tx OK, bit1 = 1 => Rx OK */
1620 static u8 _rtl8723be_phy_path_a_rx_iqk(struct ieee80211_hw *hw)
1622 u32 reg_eac, reg_e94, reg_e9c, reg_ea4, u32tmp, tmp;
1625 /* leave IQK mode */
1626 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000);
1628 /* switch to path A */
1629 rtl_set_bbreg(hw, 0x948, MASKDWORD, 0x00000000);
1631 /* 1 Get TXIMR setting */
1632 /* modify RXIQK mode table */
1633 rtl_set_rfreg(hw, RF90_PATH_A, RF_WE_LUT, 0x80000, 0x1);
1634 rtl_set_rfreg(hw, RF90_PATH_A, RF_RCK_OS, RFREG_OFFSET_MASK, 0x30000);
1635 rtl_set_rfreg(hw, RF90_PATH_A, RF_TXPA_G1, RFREG_OFFSET_MASK, 0x0001f);
1636 /* LNA2 off, PA on for Dcut */
1637 rtl_set_rfreg(hw, RF90_PATH_A, RF_TXPA_G2, RFREG_OFFSET_MASK, 0xf7fb7);
1638 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000);
1641 rtl_set_bbreg(hw, RTX_IQK, MASKDWORD, 0x01007c00);
1642 rtl_set_bbreg(hw, RRX_IQK, MASKDWORD, 0x01004800);
1644 /* path-A IQK setting */
1645 rtl_set_bbreg(hw, RTX_IQK_TONE_A, MASKDWORD, 0x18008c1c);
1646 rtl_set_bbreg(hw, RRX_IQK_TONE_A, MASKDWORD, 0x38008c1c);
1647 rtl_set_bbreg(hw, RTX_IQK_TONE_B, MASKDWORD, 0x38008c1c);
1648 rtl_set_bbreg(hw, RRX_IQK_TONE_B, MASKDWORD, 0x38008c1c);
1650 rtl_set_bbreg(hw, RTX_IQK_PI_A, MASKDWORD, 0x82160ff0);
1651 rtl_set_bbreg(hw, RRX_IQK_PI_A, MASKDWORD, 0x28110000);
1652 rtl_set_bbreg(hw, RTX_IQK_PI_B, MASKDWORD, 0x82110000);
1653 rtl_set_bbreg(hw, RRX_IQK_PI_B, MASKDWORD, 0x28110000);
1655 /* LO calibration setting */
1656 rtl_set_bbreg(hw, RIQK_AGC_RSP, MASKDWORD, 0x0046a911);
1658 /* enter IQK mode */
1659 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000);
1661 /* One shot, path A LOK & IQK */
1662 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf9000000);
1663 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf8000000);
1665 mdelay(IQK_DELAY_TIME);
1667 /* leave IQK mode */
1668 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000);
1671 reg_eac = rtl_get_bbreg(hw, RRX_POWER_AFTER_IQK_A_2, MASKDWORD);
1672 reg_e94 = rtl_get_bbreg(hw, RTX_POWER_BEFORE_IQK_A, MASKDWORD);
1673 reg_e9c = rtl_get_bbreg(hw, RTX_POWER_AFTER_IQK_A, MASKDWORD);
1675 if (!(reg_eac & BIT(28)) &&
1676 (((reg_e94 & 0x03FF0000) >> 16) != 0x142) &&
1677 (((reg_e9c & 0x03FF0000) >> 16) != 0x42))
1679 else /* if Tx not OK, ignore Rx */
1682 /* Allen 20131125 */
1683 tmp = (reg_e9c & 0x03FF0000) >> 16;
1684 if ((tmp & 0x200) > 0)
1687 if (!(reg_eac & BIT(28)) &&
1688 (((reg_e94 & 0x03FF0000) >> 16) < 0x110) &&
1689 (((reg_e94 & 0x03FF0000) >> 16) > 0xf0) &&
1692 else /* if Tx not OK, ignore Rx */
1695 u32tmp = 0x80007C00 | (reg_e94 & 0x3FF0000) |
1696 ((reg_e9c & 0x3FF0000) >> 16);
1697 rtl_set_bbreg(hw, RTX_IQK, MASKDWORD, u32tmp);
1700 /* modify RXIQK mode table */
1701 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000);
1702 rtl_set_rfreg(hw, RF90_PATH_A, RF_WE_LUT, 0x80000, 0x1);
1703 rtl_set_rfreg(hw, RF90_PATH_A, RF_RCK_OS, RFREG_OFFSET_MASK, 0x30000);
1704 rtl_set_rfreg(hw, RF90_PATH_A, RF_TXPA_G1, RFREG_OFFSET_MASK, 0x0001f);
1705 /* LAN2 on, PA off for Dcut */
1706 rtl_set_rfreg(hw, RF90_PATH_A, RF_TXPA_G2, RFREG_OFFSET_MASK, 0xf7d77);
1708 /* PA, PAD setting */
1709 rtl_set_rfreg(hw, RF90_PATH_A, 0xdf, RFREG_OFFSET_MASK, 0xf80);
1710 rtl_set_rfreg(hw, RF90_PATH_A, 0x55, RFREG_OFFSET_MASK, 0x4021f);
1713 rtl_set_bbreg(hw, RRX_IQK, MASKDWORD, 0x01004800);
1715 /* path-A IQK setting */
1716 rtl_set_bbreg(hw, RTX_IQK_TONE_A, MASKDWORD, 0x38008c1c);
1717 rtl_set_bbreg(hw, RRX_IQK_TONE_A, MASKDWORD, 0x18008c1c);
1718 rtl_set_bbreg(hw, RTX_IQK_TONE_B, MASKDWORD, 0x38008c1c);
1719 rtl_set_bbreg(hw, RRX_IQK_TONE_B, MASKDWORD, 0x38008c1c);
1721 rtl_set_bbreg(hw, RTX_IQK_PI_A, MASKDWORD, 0x82110000);
1722 rtl_set_bbreg(hw, RRX_IQK_PI_A, MASKDWORD, 0x2816001f);
1723 rtl_set_bbreg(hw, RTX_IQK_PI_B, MASKDWORD, 0x82110000);
1724 rtl_set_bbreg(hw, RRX_IQK_PI_B, MASKDWORD, 0x28110000);
1726 /* LO calibration setting */
1727 rtl_set_bbreg(hw, RIQK_AGC_RSP, MASKDWORD, 0x0046a8d1);
1729 /* enter IQK mode */
1730 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000);
1732 /* One shot, path A LOK & IQK */
1733 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf9000000);
1734 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf8000000);
1736 mdelay(IQK_DELAY_TIME);
1738 /* leave IQK mode */
1739 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000);
1742 reg_eac = rtl_get_bbreg(hw, RRX_POWER_AFTER_IQK_A_2, MASKDWORD);
1743 reg_ea4 = rtl_get_bbreg(hw, RRX_POWER_BEFORE_IQK_A_2, MASKDWORD);
1745 /* leave IQK mode */
1746 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000);
1747 rtl_set_rfreg(hw, RF90_PATH_A, 0xdf, RFREG_OFFSET_MASK, 0x780);
1749 /* Allen 20131125 */
1750 tmp = (reg_eac & 0x03FF0000) >> 16;
1751 if ((tmp & 0x200) > 0)
1753 /* if Tx is OK, check whether Rx is OK */
1754 if (!(reg_eac & BIT(27)) &&
1755 (((reg_ea4 & 0x03FF0000) >> 16) != 0x132) &&
1756 (((reg_eac & 0x03FF0000) >> 16) != 0x36))
1758 else if (!(reg_eac & BIT(27)) &&
1759 (((reg_ea4 & 0x03FF0000) >> 16) < 0x110) &&
1760 (((reg_ea4 & 0x03FF0000) >> 16) > 0xf0) &&
1767 static u8 _rtl8723be_phy_path_b_iqk(struct ieee80211_hw *hw)
1769 u32 reg_eac, reg_e94, reg_e9c, tmp;
1772 /* leave IQK mode */
1773 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000);
1774 /* switch to path B */
1775 rtl_set_bbreg(hw, 0x948, MASKDWORD, 0x00000280);
1777 /* enable path B PA in TXIQK mode */
1778 rtl_set_rfreg(hw, RF90_PATH_A, 0xed, RFREG_OFFSET_MASK, 0x00020);
1779 rtl_set_rfreg(hw, RF90_PATH_A, 0x43, RFREG_OFFSET_MASK, 0x40fc1);
1783 rtl_set_bbreg(hw, RTX_IQK, MASKDWORD, 0x01007c00);
1784 rtl_set_bbreg(hw, RRX_IQK, MASKDWORD, 0x01004800);
1785 /* path-A IQK setting */
1786 rtl_set_bbreg(hw, RTX_IQK_TONE_A, MASKDWORD, 0x18008c1c);
1787 rtl_set_bbreg(hw, RRX_IQK_TONE_A, MASKDWORD, 0x38008c1c);
1788 rtl_set_bbreg(hw, RTX_IQK_TONE_B, MASKDWORD, 0x38008c1c);
1789 rtl_set_bbreg(hw, RRX_IQK_TONE_B, MASKDWORD, 0x38008c1c);
1791 rtl_set_bbreg(hw, RTX_IQK_PI_A, MASKDWORD, 0x821403ea);
1792 rtl_set_bbreg(hw, RRX_IQK_PI_A, MASKDWORD, 0x28110000);
1793 rtl_set_bbreg(hw, RTX_IQK_PI_B, MASKDWORD, 0x82110000);
1794 rtl_set_bbreg(hw, RRX_IQK_PI_B, MASKDWORD, 0x28110000);
1796 /* LO calibration setting */
1797 rtl_set_bbreg(hw, RIQK_AGC_RSP, MASKDWORD, 0x00462911);
1799 /* enter IQK mode */
1800 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000);
1802 /* One shot, path B LOK & IQK */
1803 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf9000000);
1804 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf8000000);
1806 mdelay(IQK_DELAY_TIME);
1808 /* leave IQK mode */
1809 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000);
1812 reg_eac = rtl_get_bbreg(hw, RRX_POWER_AFTER_IQK_A_2, MASKDWORD);
1813 reg_e94 = rtl_get_bbreg(hw, RTX_POWER_BEFORE_IQK_A, MASKDWORD);
1814 reg_e9c = rtl_get_bbreg(hw, RTX_POWER_AFTER_IQK_A, MASKDWORD);
1816 if (!(reg_eac & BIT(28)) &&
1817 (((reg_e94 & 0x03FF0000) >> 16) != 0x142) &&
1818 (((reg_e9c & 0x03FF0000) >> 16) != 0x42))
1823 /* Allen 20131125 */
1824 tmp = (reg_e9c & 0x03FF0000) >> 16;
1825 if ((tmp & 0x200) > 0)
1828 if (!(reg_eac & BIT(28)) &&
1829 (((reg_e94 & 0x03FF0000) >> 16) < 0x110) &&
1830 (((reg_e94 & 0x03FF0000) >> 16) > 0xf0) &&
1839 /* bit0 = 1 => Tx OK, bit1 = 1 => Rx OK */
1840 static u8 _rtl8723be_phy_path_b_rx_iqk(struct ieee80211_hw *hw)
1842 u32 reg_e94, reg_e9c, reg_ea4, reg_eac, u32tmp, tmp;
1845 /* leave IQK mode */
1846 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000);
1847 /* switch to path B */
1848 rtl_set_bbreg(hw, 0x948, MASKDWORD, 0x00000280);
1850 /* 1 Get TXIMR setting */
1851 /* modify RXIQK mode table */
1852 rtl_set_rfreg(hw, RF90_PATH_A, RF_WE_LUT, RFREG_OFFSET_MASK, 0x800a0);
1853 rtl_set_rfreg(hw, RF90_PATH_A, RF_RCK_OS, RFREG_OFFSET_MASK, 0x30000);
1854 rtl_set_rfreg(hw, RF90_PATH_A, RF_TXPA_G1, RFREG_OFFSET_MASK, 0x0001f);
1855 rtl_set_rfreg(hw, RF90_PATH_A, RF_TXPA_G2, RFREG_OFFSET_MASK, 0xf7ff7);
1857 /* open PA S1 & SMIXER */
1858 rtl_set_rfreg(hw, RF90_PATH_A, 0xed, RFREG_OFFSET_MASK, 0x00020);
1859 rtl_set_rfreg(hw, RF90_PATH_A, 0x43, RFREG_OFFSET_MASK, 0x60fed);
1862 rtl_set_bbreg(hw, RTX_IQK, MASKDWORD, 0x01007c00);
1863 rtl_set_bbreg(hw, RRX_IQK, MASKDWORD, 0x01004800);
1865 /* path-B IQK setting */
1866 rtl_set_bbreg(hw, RTX_IQK_TONE_A, MASKDWORD, 0x18008c1c);
1867 rtl_set_bbreg(hw, RRX_IQK_TONE_A, MASKDWORD, 0x38008c1c);
1868 rtl_set_bbreg(hw, RTX_IQK_TONE_B, MASKDWORD, 0x38008c1c);
1869 rtl_set_bbreg(hw, RRX_IQK_TONE_B, MASKDWORD, 0x38008c1c);
1871 rtl_set_bbreg(hw, RTX_IQK_PI_A, MASKDWORD, 0x82160ff0);
1872 rtl_set_bbreg(hw, RRX_IQK_PI_A, MASKDWORD, 0x28110000);
1873 rtl_set_bbreg(hw, RTX_IQK_PI_B, MASKDWORD, 0x82110000);
1874 rtl_set_bbreg(hw, RRX_IQK_PI_B, MASKDWORD, 0x28110000);
1876 /* LO calibration setting */
1877 rtl_set_bbreg(hw, RIQK_AGC_RSP, MASKDWORD, 0x0046a911);
1878 /* enter IQK mode */
1879 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000);
1881 /* One shot, path B TXIQK @ RXIQK */
1882 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf9000000);
1883 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf8000000);
1885 mdelay(IQK_DELAY_TIME);
1887 /* leave IQK mode */
1888 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000);
1890 reg_eac = rtl_get_bbreg(hw, RRX_POWER_AFTER_IQK_A_2, MASKDWORD);
1891 reg_e94 = rtl_get_bbreg(hw, RTX_POWER_BEFORE_IQK_A, MASKDWORD);
1892 reg_e9c = rtl_get_bbreg(hw, RTX_POWER_AFTER_IQK_A, MASKDWORD);
1894 if (!(reg_eac & BIT(28)) &&
1895 (((reg_e94 & 0x03FF0000) >> 16) != 0x142) &&
1896 (((reg_e9c & 0x03FF0000) >> 16) != 0x42))
1898 else /* if Tx not OK, ignore Rx */
1901 /* Allen 20131125 */
1902 tmp = (reg_e9c & 0x03FF0000) >> 16;
1903 if ((tmp & 0x200) > 0)
1906 if (!(reg_eac & BIT(28)) &&
1907 (((reg_e94 & 0x03FF0000) >> 16) < 0x110) &&
1908 (((reg_e94 & 0x03FF0000) >> 16) > 0xf0) &&
1914 u32tmp = 0x80007C00 | (reg_e94 & 0x3FF0000) |
1915 ((reg_e9c & 0x3FF0000) >> 16);
1916 rtl_set_bbreg(hw, RTX_IQK, MASKDWORD, u32tmp);
1920 /* <20121009, Kordan> RF Mode = 3 */
1921 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000);
1922 rtl_set_rfreg(hw, RF90_PATH_A, RF_WE_LUT, 0x80000, 0x1);
1923 rtl_set_rfreg(hw, RF90_PATH_A, RF_RCK_OS, RFREG_OFFSET_MASK, 0x30000);
1924 rtl_set_rfreg(hw, RF90_PATH_A, RF_TXPA_G1, RFREG_OFFSET_MASK, 0x0001f);
1925 rtl_set_rfreg(hw, RF90_PATH_A, RF_TXPA_G2, RFREG_OFFSET_MASK, 0xf7d77);
1926 rtl_set_rfreg(hw, RF90_PATH_A, RF_WE_LUT, 0x80000, 0x0);
1928 /* open PA S1 & close SMIXER */
1929 rtl_set_rfreg(hw, RF90_PATH_A, 0xed, RFREG_OFFSET_MASK, 0x00020);
1930 rtl_set_rfreg(hw, RF90_PATH_A, 0x43, RFREG_OFFSET_MASK, 0x60fbd);
1933 rtl_set_bbreg(hw, RRX_IQK, MASKDWORD, 0x01004800);
1935 /* path-B IQK setting */
1936 rtl_set_bbreg(hw, RTX_IQK_TONE_A, MASKDWORD, 0x38008c1c);
1937 rtl_set_bbreg(hw, RRX_IQK_TONE_A, MASKDWORD, 0x18008c1c);
1938 rtl_set_bbreg(hw, RTX_IQK_TONE_B, MASKDWORD, 0x38008c1c);
1939 rtl_set_bbreg(hw, RRX_IQK_TONE_B, MASKDWORD, 0x38008c1c);
1941 rtl_set_bbreg(hw, RTX_IQK_PI_A, MASKDWORD, 0x82110000);
1942 rtl_set_bbreg(hw, RRX_IQK_PI_A, MASKDWORD, 0x2816001f);
1943 rtl_set_bbreg(hw, RTX_IQK_PI_B, MASKDWORD, 0x82110000);
1944 rtl_set_bbreg(hw, RRX_IQK_PI_B, MASKDWORD, 0x28110000);
1946 /* LO calibration setting */
1947 rtl_set_bbreg(hw, RIQK_AGC_RSP, MASKDWORD, 0x0046a8d1);
1948 /* enter IQK mode */
1949 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000);
1951 /* One shot, path B LOK & IQK */
1952 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf9000000);
1953 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf8000000);
1955 mdelay(IQK_DELAY_TIME);
1957 /* leave IQK mode */
1958 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000);
1960 reg_eac = rtl_get_bbreg(hw, RRX_POWER_AFTER_IQK_A_2, MASKDWORD);
1961 reg_ea4 = rtl_get_bbreg(hw, RRX_POWER_BEFORE_IQK_A_2, MASKDWORD);
1963 /* Allen 20131125 */
1964 tmp = (reg_eac & 0x03FF0000) >> 16;
1965 if ((tmp & 0x200) > 0)
1968 /* if Tx is OK, check whether Rx is OK */
1969 if (!(reg_eac & BIT(27)) &&
1970 (((reg_ea4 & 0x03FF0000) >> 16) != 0x132) &&
1971 (((reg_eac & 0x03FF0000) >> 16) != 0x36))
1973 else if (!(reg_eac & BIT(27)) &&
1974 (((reg_ea4 & 0x03FF0000) >> 16) < 0x110) &&
1975 (((reg_ea4 & 0x03FF0000) >> 16) > 0xf0) &&
1984 static void _rtl8723be_phy_path_b_fill_iqk_matrix(struct ieee80211_hw *hw,
1990 u32 oldval_1, x, tx1_a, reg;
1993 if (final_candidate == 0xFF) {
1995 } else if (b_iqk_ok) {
1996 oldval_1 = (rtl_get_bbreg(hw, ROFDM0_XBTXIQIMBALANCE,
1997 MASKDWORD) >> 22) & 0x3FF;
1998 x = result[final_candidate][4];
1999 if ((x & 0x00000200) != 0)
2001 tx1_a = (x * oldval_1) >> 8;
2002 rtl_set_bbreg(hw, ROFDM0_XBTXIQIMBALANCE, 0x3FF, tx1_a);
2003 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(27),
2004 ((x * oldval_1 >> 7) & 0x1));
2005 y = result[final_candidate][5];
2006 if ((y & 0x00000200) != 0)
2008 tx1_c = (y * oldval_1) >> 8;
2009 rtl_set_bbreg(hw, ROFDM0_XDTXAFE, 0xF0000000,
2010 ((tx1_c & 0x3C0) >> 6));
2011 rtl_set_bbreg(hw, ROFDM0_XBTXIQIMBALANCE, 0x003F0000,
2013 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(25),
2014 ((y * oldval_1 >> 7) & 0x1));
2017 reg = result[final_candidate][6];
2018 rtl_set_bbreg(hw, ROFDM0_XBRXIQIMBALANCE, 0x3FF, reg);
2019 reg = result[final_candidate][7] & 0x3F;
2020 rtl_set_bbreg(hw, ROFDM0_XBRXIQIMBALANCE, 0xFC00, reg);
2021 reg = (result[final_candidate][7] >> 6) & 0xF;
2022 /* rtl_set_bbreg(hw, 0xca0, 0xF0000000, reg); */
2026 static bool _rtl8723be_phy_simularity_compare(struct ieee80211_hw *hw,
2027 long result[][8], u8 c1, u8 c2)
2029 u32 i, j, diff, simularity_bitmap, bound = 0;
2031 u8 final_candidate[2] = {0xFF, 0xFF}; /* for path A and path B */
2032 bool bresult = true; /* is2t = true*/
2033 s32 tmp1 = 0, tmp2 = 0;
2037 simularity_bitmap = 0;
2039 for (i = 0; i < bound; i++) {
2040 if ((i == 1) || (i == 3) || (i == 5) || (i == 7)) {
2041 if ((result[c1][i] & 0x00000200) != 0)
2042 tmp1 = result[c1][i] | 0xFFFFFC00;
2044 tmp1 = result[c1][i];
2046 if ((result[c2][i] & 0x00000200) != 0)
2047 tmp2 = result[c2][i] | 0xFFFFFC00;
2049 tmp2 = result[c2][i];
2051 tmp1 = result[c1][i];
2052 tmp2 = result[c2][i];
2055 diff = (tmp1 > tmp2) ? (tmp1 - tmp2) : (tmp2 - tmp1);
2057 if (diff > MAX_TOLERANCE) {
2058 if ((i == 2 || i == 6) && !simularity_bitmap) {
2059 if (result[c1][i] + result[c1][i + 1] == 0)
2060 final_candidate[(i / 4)] = c2;
2061 else if (result[c2][i] + result[c2][i + 1] == 0)
2062 final_candidate[(i / 4)] = c1;
2064 simularity_bitmap |= (1 << i);
2066 simularity_bitmap |= (1 << i);
2070 if (simularity_bitmap == 0) {
2071 for (i = 0; i < (bound / 4); i++) {
2072 if (final_candidate[i] != 0xFF) {
2073 for (j = i * 4; j < (i + 1) * 4 - 2; j++)
2075 result[final_candidate[i]][j];
2081 if (!(simularity_bitmap & 0x03)) { /* path A TX OK */
2082 for (i = 0; i < 2; i++)
2083 result[3][i] = result[c1][i];
2085 if (!(simularity_bitmap & 0x0c)) { /* path A RX OK */
2086 for (i = 2; i < 4; i++)
2087 result[3][i] = result[c1][i];
2089 if (!(simularity_bitmap & 0x30)) { /* path B TX OK */
2090 for (i = 4; i < 6; i++)
2091 result[3][i] = result[c1][i];
2093 if (!(simularity_bitmap & 0xc0)) { /* path B RX OK */
2094 for (i = 6; i < 8; i++)
2095 result[3][i] = result[c1][i];
2101 static void _rtl8723be_phy_iq_calibrate(struct ieee80211_hw *hw,
2102 long result[][8], u8 t, bool is2t)
2104 struct rtl_priv *rtlpriv = rtl_priv(hw);
2105 struct rtl_phy *rtlphy = &rtlpriv->phy;
2107 u8 patha_ok, pathb_ok;
2108 u32 adda_reg[IQK_ADDA_REG_NUM] = {
2109 0x85c, 0xe6c, 0xe70, 0xe74,
2110 0xe78, 0xe7c, 0xe80, 0xe84,
2111 0xe88, 0xe8c, 0xed0, 0xed4,
2112 0xed8, 0xedc, 0xee0, 0xeec
2115 u32 iqk_mac_reg[IQK_MAC_REG_NUM] = {
2116 0x522, 0x550, 0x551, 0x040
2118 u32 iqk_bb_reg[IQK_BB_REG_NUM] = {
2119 ROFDM0_TRXPATHENABLE, ROFDM0_TRMUXPAR,
2120 RFPGA0_XCD_RFINTERFACESW, 0xb68, 0xb6c,
2124 const u32 retrycount = 2;
2126 u32 path_sel_bb;/* path_sel_rf */
2128 u8 tmp_reg_c50, tmp_reg_c58;
2130 tmp_reg_c50 = rtl_get_bbreg(hw, 0xc50, MASKBYTE0);
2131 tmp_reg_c58 = rtl_get_bbreg(hw, 0xc58, MASKBYTE0);
2134 rtl8723_save_adda_registers(hw, adda_reg,
2135 rtlphy->adda_backup, 16);
2136 rtl8723_phy_save_mac_registers(hw, iqk_mac_reg,
2137 rtlphy->iqk_mac_backup);
2138 rtl8723_save_adda_registers(hw, iqk_bb_reg,
2139 rtlphy->iqk_bb_backup,
2142 rtl8723_phy_path_adda_on(hw, adda_reg, true, is2t);
2144 rtlphy->rfpi_enable = (u8)rtl_get_bbreg(hw,
2145 RFPGA0_XA_HSSIPARAMETER1,
2149 path_sel_bb = rtl_get_bbreg(hw, 0x948, MASKDWORD);
2151 rtl8723_phy_mac_setting_calibration(hw, iqk_mac_reg,
2152 rtlphy->iqk_mac_backup);
2154 rtl_set_bbreg(hw, 0xa04, 0x0f000000, 0xf);
2155 rtl_set_bbreg(hw, 0xc04, MASKDWORD, 0x03a05600);
2156 rtl_set_bbreg(hw, 0xc08, MASKDWORD, 0x000800e4);
2157 rtl_set_bbreg(hw, 0x874, MASKDWORD, 0x22204000);
2160 for (i = 0; i < retrycount; i++) {
2161 patha_ok = _rtl8723be_phy_path_a_iqk(hw);
2162 if (patha_ok == 0x01) {
2163 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2164 "Path A Tx IQK Success!!\n");
2165 result[t][0] = (rtl_get_bbreg(hw, 0xe94, MASKDWORD) &
2167 result[t][1] = (rtl_get_bbreg(hw, 0xe9c, MASKDWORD) &
2171 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2172 "Path A Tx IQK Fail!!\n");
2176 for (i = 0; i < retrycount; i++) {
2177 patha_ok = _rtl8723be_phy_path_a_rx_iqk(hw);
2178 if (patha_ok == 0x03) {
2179 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2180 "Path A Rx IQK Success!!\n");
2181 result[t][2] = (rtl_get_bbreg(hw, 0xea4, MASKDWORD) &
2183 result[t][3] = (rtl_get_bbreg(hw, 0xeac, MASKDWORD) &
2187 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2188 "Path A Rx IQK Fail!!\n");
2191 if (0x00 == patha_ok)
2192 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Path A IQK Fail!!\n");
2196 for (i = 0; i < retrycount; i++) {
2197 pathb_ok = _rtl8723be_phy_path_b_iqk(hw);
2198 if (pathb_ok == 0x01) {
2199 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2200 "Path B Tx IQK Success!!\n");
2201 result[t][4] = (rtl_get_bbreg(hw, 0xe94,
2204 result[t][5] = (rtl_get_bbreg(hw, 0xe9c,
2209 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2210 "Path B Tx IQK Fail!!\n");
2213 for (i = 0; i < retrycount; i++) {
2214 pathb_ok = _rtl8723be_phy_path_b_rx_iqk(hw);
2215 if (pathb_ok == 0x03) {
2216 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2217 "Path B Rx IQK Success!!\n");
2218 result[t][6] = (rtl_get_bbreg(hw, 0xea4,
2221 result[t][7] = (rtl_get_bbreg(hw, 0xeac,
2226 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2227 "Path B Rx IQK Fail!!\n");
2231 /* Back to BB mode, load original value */
2232 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0);
2235 rtl8723_phy_reload_adda_registers(hw, adda_reg,
2236 rtlphy->adda_backup, 16);
2237 rtl8723_phy_reload_mac_registers(hw, iqk_mac_reg,
2238 rtlphy->iqk_mac_backup);
2239 rtl8723_phy_reload_adda_registers(hw, iqk_bb_reg,
2240 rtlphy->iqk_bb_backup,
2243 rtl_set_bbreg(hw, 0x948, MASKDWORD, path_sel_bb);
2244 /*rtl_set_rfreg(hw, RF90_PATH_B, 0xb0, 0xfffff, path_sel_rf);*/
2246 rtl_set_bbreg(hw, 0xc50, MASKBYTE0, 0x50);
2247 rtl_set_bbreg(hw, 0xc50, MASKBYTE0, tmp_reg_c50);
2249 rtl_set_bbreg(hw, 0xc58, MASKBYTE0, 0x50);
2250 rtl_set_bbreg(hw, 0xc58, MASKBYTE0, tmp_reg_c58);
2252 rtl_set_bbreg(hw, 0xe30, MASKDWORD, 0x01008c00);
2253 rtl_set_bbreg(hw, 0xe34, MASKDWORD, 0x01008c00);
2255 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "8723be IQK Finish!!\n");
2258 static u8 _get_right_chnl_place_for_iqk(u8 chnl)
2260 u8 channel_all[TARGET_CHNL_NUM_2G_5G] = {
2261 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12,
2262 13, 14, 36, 38, 40, 42, 44, 46,
2263 48, 50, 52, 54, 56, 58, 60, 62, 64,
2264 100, 102, 104, 106, 108, 110,
2265 112, 114, 116, 118, 120, 122,
2266 124, 126, 128, 130, 132, 134, 136,
2267 138, 140, 149, 151, 153, 155, 157,
2268 159, 161, 163, 165};
2272 for (place = 14; place < sizeof(channel_all); place++) {
2273 if (channel_all[place] == chnl)
2280 static void _rtl8723be_phy_lc_calibrate(struct ieee80211_hw *hw, bool is2t)
2283 u32 rf_a_mode = 0, rf_b_mode = 0, lc_cal;
2284 struct rtl_priv *rtlpriv = rtl_priv(hw);
2286 tmpreg = rtl_read_byte(rtlpriv, 0xd03);
2288 if ((tmpreg & 0x70) != 0)
2289 rtl_write_byte(rtlpriv, 0xd03, tmpreg & 0x8F);
2291 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF);
2293 if ((tmpreg & 0x70) != 0) {
2294 rf_a_mode = rtl_get_rfreg(hw, RF90_PATH_A, 0x00, MASK12BITS);
2297 rf_b_mode = rtl_get_rfreg(hw, RF90_PATH_B, 0x00,
2300 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, MASK12BITS,
2301 (rf_a_mode & 0x8FFFF) | 0x10000);
2304 rtl_set_rfreg(hw, RF90_PATH_B, 0x00, MASK12BITS,
2305 (rf_b_mode & 0x8FFFF) | 0x10000);
2307 lc_cal = rtl_get_rfreg(hw, RF90_PATH_A, 0x18, MASK12BITS);
2309 rtl_set_rfreg(hw, RF90_PATH_A, 0xb0, RFREG_OFFSET_MASK, 0xdfbe0);
2310 rtl_set_rfreg(hw, RF90_PATH_A, 0x18, MASK12BITS, 0x8c0a);
2312 /* In order not to disturb BT music when wifi init.(1ant NIC only) */
2314 /* In order not to disturb BT music when wifi init.(1ant NIC only) */
2317 rtl_set_rfreg(hw, RF90_PATH_A, 0xb0, RFREG_OFFSET_MASK, 0xdffe0);
2319 if ((tmpreg & 0x70) != 0) {
2320 rtl_write_byte(rtlpriv, 0xd03, tmpreg);
2321 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, MASK12BITS, rf_a_mode);
2324 rtl_set_rfreg(hw, RF90_PATH_B, 0x00,
2325 MASK12BITS, rf_b_mode);
2327 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00);
2329 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "\n");
2333 static void _rtl8723be_phy_set_rfpath_switch(struct ieee80211_hw *hw,
2334 bool bmain, bool is2t)
2336 struct rtl_priv *rtlpriv = rtl_priv(hw);
2337 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "\n");
2339 if (bmain) /* left antenna */
2340 rtl_set_bbreg(hw, 0x92C, MASKDWORD, 0x1);
2342 rtl_set_bbreg(hw, 0x92C, MASKDWORD, 0x2);
2345 #undef IQK_ADDA_REG_NUM
2346 #undef IQK_DELAY_TIME
2347 /* IQK is merge from Merge Temp */
2348 void rtl8723be_phy_iq_calibrate(struct ieee80211_hw *hw, bool b_recovery)
2350 struct rtl_priv *rtlpriv = rtl_priv(hw);
2351 struct rtl_phy *rtlphy = &rtlpriv->phy;
2353 u8 i, final_candidate, idx;
2354 bool b_patha_ok, b_pathb_ok;
2355 long reg_e94, reg_e9c, reg_ea4, reg_eac, reg_eb4, reg_ebc, reg_ec4;
2356 long reg_ecc, reg_tmp = 0;
2357 bool is12simular, is13simular, is23simular;
2358 u32 iqk_bb_reg[9] = {
2359 ROFDM0_XARXIQIMBALANCE,
2360 ROFDM0_XBRXIQIMBALANCE,
2361 ROFDM0_ECCATHRESHOLD,
2362 ROFDM0_AGCRSSITABLE,
2363 ROFDM0_XATXIQIMBALANCE,
2364 ROFDM0_XBTXIQIMBALANCE,
2369 u32 path_sel_bb = 0; /* path_sel_rf = 0 */
2371 if (rtlphy->lck_inprogress)
2374 spin_lock(&rtlpriv->locks.iqk_lock);
2375 rtlphy->lck_inprogress = true;
2376 spin_unlock(&rtlpriv->locks.iqk_lock);
2379 rtl8723_phy_reload_adda_registers(hw, iqk_bb_reg,
2380 rtlphy->iqk_bb_backup, 9);
2384 path_sel_bb = rtl_get_bbreg(hw, 0x948, MASKDWORD);
2385 /* path_sel_rf = rtl_get_rfreg(hw, RF90_PATH_A, 0xb0, 0xfffff); */
2387 for (i = 0; i < 8; i++) {
2393 final_candidate = 0xff;
2396 is12simular = false;
2397 is23simular = false;
2398 is13simular = false;
2399 for (i = 0; i < 3; i++) {
2400 _rtl8723be_phy_iq_calibrate(hw, result, i, true);
2402 is12simular = _rtl8723be_phy_simularity_compare(hw,
2406 final_candidate = 0;
2411 is13simular = _rtl8723be_phy_simularity_compare(hw,
2415 final_candidate = 0;
2418 is23simular = _rtl8723be_phy_simularity_compare(hw,
2422 final_candidate = 1;
2424 for (i = 0; i < 8; i++)
2425 reg_tmp += result[3][i];
2428 final_candidate = 3;
2430 final_candidate = 0xFF;
2434 for (i = 0; i < 4; i++) {
2435 reg_e94 = result[i][0];
2436 reg_e9c = result[i][1];
2437 reg_ea4 = result[i][2];
2438 reg_eac = result[i][3];
2439 reg_eb4 = result[i][4];
2440 reg_ebc = result[i][5];
2441 reg_ec4 = result[i][6];
2442 reg_ecc = result[i][7];
2444 if (final_candidate != 0xff) {
2445 reg_e94 = result[final_candidate][0];
2446 rtlphy->reg_e94 = reg_e94;
2447 reg_e9c = result[final_candidate][1];
2448 rtlphy->reg_e9c = reg_e9c;
2449 reg_ea4 = result[final_candidate][2];
2450 reg_eac = result[final_candidate][3];
2451 reg_eb4 = result[final_candidate][4];
2452 rtlphy->reg_eb4 = reg_eb4;
2453 reg_ebc = result[final_candidate][5];
2454 rtlphy->reg_ebc = reg_ebc;
2455 reg_ec4 = result[final_candidate][6];
2456 reg_ecc = result[final_candidate][7];
2460 rtlphy->reg_e94 = 0x100;
2461 rtlphy->reg_eb4 = 0x100;
2462 rtlphy->reg_e9c = 0x0;
2463 rtlphy->reg_ebc = 0x0;
2466 rtl8723_phy_path_a_fill_iqk_matrix(hw, b_patha_ok, result,
2470 _rtl8723be_phy_path_b_fill_iqk_matrix(hw, b_pathb_ok, result,
2474 idx = _get_right_chnl_place_for_iqk(rtlphy->current_channel);
2476 if (final_candidate < 4) {
2477 for (i = 0; i < IQK_MATRIX_REG_NUM; i++)
2478 rtlphy->iqk_matrix[idx].value[0][i] =
2479 result[final_candidate][i];
2480 rtlphy->iqk_matrix[idx].iqk_done = true;
2483 rtl8723_save_adda_registers(hw, iqk_bb_reg,
2484 rtlphy->iqk_bb_backup, 9);
2486 rtl_set_bbreg(hw, 0x948, MASKDWORD, path_sel_bb);
2487 /* rtl_set_rfreg(hw, RF90_PATH_A, 0xb0, 0xfffff, path_sel_rf); */
2489 spin_lock(&rtlpriv->locks.iqk_lock);
2490 rtlphy->lck_inprogress = false;
2491 spin_unlock(&rtlpriv->locks.iqk_lock);
2494 void rtl8723be_phy_lc_calibrate(struct ieee80211_hw *hw)
2496 struct rtl_priv *rtlpriv = rtl_priv(hw);
2497 struct rtl_phy *rtlphy = &rtlpriv->phy;
2498 struct rtl_hal *rtlhal = &rtlpriv->rtlhal;
2499 u32 timeout = 2000, timecount = 0;
2501 while (rtlpriv->mac80211.act_scanning && timecount < timeout) {
2506 rtlphy->lck_inprogress = true;
2507 RTPRINT(rtlpriv, FINIT, INIT_IQK,
2508 "LCK:Start!!! currentband %x delay %d ms\n",
2509 rtlhal->current_bandtype, timecount);
2511 _rtl8723be_phy_lc_calibrate(hw, false);
2513 rtlphy->lck_inprogress = false;
2516 void rtl8723be_phy_set_rfpath_switch(struct ieee80211_hw *hw, bool bmain)
2518 _rtl8723be_phy_set_rfpath_switch(hw, bmain, true);
2521 bool rtl8723be_phy_set_io_cmd(struct ieee80211_hw *hw, enum io_type iotype)
2523 struct rtl_priv *rtlpriv = rtl_priv(hw);
2524 struct rtl_phy *rtlphy = &rtlpriv->phy;
2525 bool b_postprocessing = false;
2527 RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE,
2528 "-->IO Cmd(%#x), set_io_inprogress(%d)\n",
2529 iotype, rtlphy->set_io_inprogress);
2532 case IO_CMD_RESUME_DM_BY_SCAN:
2533 RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE,
2534 "[IO CMD] Resume DM after scan.\n");
2535 b_postprocessing = true;
2537 case IO_CMD_PAUSE_BAND0_DM_BY_SCAN:
2538 RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE,
2539 "[IO CMD] Pause DM before scan.\n");
2540 b_postprocessing = true;
2543 RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
2544 "switch case not process\n");
2548 if (b_postprocessing && !rtlphy->set_io_inprogress) {
2549 rtlphy->set_io_inprogress = true;
2550 rtlphy->current_io_type = iotype;
2554 rtl8723be_phy_set_io(hw);
2555 RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE, "IO Type(%#x)\n", iotype);
2559 static void rtl8723be_phy_set_io(struct ieee80211_hw *hw)
2561 struct rtl_priv *rtlpriv = rtl_priv(hw);
2562 struct dig_t *dm_digtable = &rtlpriv->dm_digtable;
2563 struct rtl_phy *rtlphy = &rtlpriv->phy;
2565 RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE,
2566 "--->Cmd(%#x), set_io_inprogress(%d)\n",
2567 rtlphy->current_io_type, rtlphy->set_io_inprogress);
2568 switch (rtlphy->current_io_type) {
2569 case IO_CMD_RESUME_DM_BY_SCAN:
2570 dm_digtable->cur_igvalue = rtlphy->initgain_backup.xaagccore1;
2571 /*rtl92c_dm_write_dig(hw);*/
2572 rtl8723be_phy_set_txpower_level(hw, rtlphy->current_channel);
2573 rtl_set_bbreg(hw, RCCK0_CCA, 0xff0000, 0x83);
2575 case IO_CMD_PAUSE_BAND0_DM_BY_SCAN:
2576 rtlphy->initgain_backup.xaagccore1 = dm_digtable->cur_igvalue;
2577 dm_digtable->cur_igvalue = 0x17;
2578 rtl_set_bbreg(hw, RCCK0_CCA, 0xff0000, 0x40);
2581 RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
2582 "switch case not process\n");
2585 rtlphy->set_io_inprogress = false;
2586 RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE,
2587 "(%#x)\n", rtlphy->current_io_type);
2590 static void rtl8723be_phy_set_rf_on(struct ieee80211_hw *hw)
2592 struct rtl_priv *rtlpriv = rtl_priv(hw);
2594 rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x2b);
2595 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3);
2596 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2);
2597 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3);
2598 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00);
2601 static void _rtl8723be_phy_set_rf_sleep(struct ieee80211_hw *hw)
2603 struct rtl_priv *rtlpriv = rtl_priv(hw);
2605 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF);
2606 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, RFREG_OFFSET_MASK, 0x00);
2607 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2);
2608 rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x22);
2611 static bool _rtl8723be_phy_set_rf_power_state(struct ieee80211_hw *hw,
2612 enum rf_pwrstate rfpwr_state)
2614 struct rtl_priv *rtlpriv = rtl_priv(hw);
2615 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
2616 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2617 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
2618 bool bresult = true;
2620 struct rtl8192_tx_ring *ring = NULL;
2622 switch (rfpwr_state) {
2624 if ((ppsc->rfpwr_state == ERFOFF) &&
2625 RT_IN_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC)) {
2627 u32 initializecount = 0;
2630 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
2631 "IPS Set eRf nic enable\n");
2632 rtstatus = rtl_ps_enable_nic(hw);
2633 } while (!rtstatus && (initializecount < 10));
2634 RT_CLEAR_PS_LEVEL(ppsc,
2635 RT_RF_OFF_LEVL_HALT_NIC);
2637 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
2638 "Set ERFON sleeped:%d ms\n",
2639 jiffies_to_msecs(jiffies -
2640 ppsc->last_sleep_jiffies));
2641 ppsc->last_awake_jiffies = jiffies;
2642 rtl8723be_phy_set_rf_on(hw);
2644 if (mac->link_state == MAC80211_LINKED)
2645 rtlpriv->cfg->ops->led_control(hw, LED_CTL_LINK);
2647 rtlpriv->cfg->ops->led_control(hw, LED_CTL_NO_LINK);
2652 for (queue_id = 0, i = 0;
2653 queue_id < RTL_PCI_MAX_TX_QUEUE_COUNT;) {
2654 ring = &pcipriv->dev.tx_ring[queue_id];
2655 /* Don't check BEACON Q.
2656 * BEACON Q is always not empty,
2657 * because '_rtl8723be_cmd_send_packet'
2659 if (queue_id == BEACON_QUEUE ||
2660 skb_queue_len(&ring->queue) == 0) {
2664 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
2665 "eRf Off/Sleep: %d times TcbBusyQueue[%d] =%d before doze!\n",
2667 skb_queue_len(&ring->queue));
2672 if (i >= MAX_DOZE_WAITING_TIMES_9x) {
2673 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
2674 "ERFSLEEP: %d times TcbBusyQueue[%d] = %d !\n",
2675 MAX_DOZE_WAITING_TIMES_9x,
2677 skb_queue_len(&ring->queue));
2682 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_HALT_NIC) {
2683 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
2684 "IPS Set eRf nic disable\n");
2685 rtl_ps_disable_nic(hw);
2686 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
2688 if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS) {
2689 rtlpriv->cfg->ops->led_control(hw,
2692 rtlpriv->cfg->ops->led_control(hw,
2699 if (ppsc->rfpwr_state == ERFOFF)
2701 for (queue_id = 0, i = 0;
2702 queue_id < RTL_PCI_MAX_TX_QUEUE_COUNT;) {
2703 ring = &pcipriv->dev.tx_ring[queue_id];
2704 if (skb_queue_len(&ring->queue) == 0) {
2708 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
2709 "eRf Off/Sleep: %d times TcbBusyQueue[%d] =%d before doze!\n",
2711 skb_queue_len(&ring->queue));
2716 if (i >= MAX_DOZE_WAITING_TIMES_9x) {
2717 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
2718 "ERFSLEEP: %d times TcbBusyQueue[%d] = %d !\n",
2719 MAX_DOZE_WAITING_TIMES_9x,
2721 skb_queue_len(&ring->queue));
2725 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
2726 "Set ERFSLEEP awaked:%d ms\n",
2727 jiffies_to_msecs(jiffies -
2728 ppsc->last_awake_jiffies));
2729 ppsc->last_sleep_jiffies = jiffies;
2730 _rtl8723be_phy_set_rf_sleep(hw);
2734 RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
2735 "switch case not process\n");
2740 ppsc->rfpwr_state = rfpwr_state;
2744 bool rtl8723be_phy_set_rf_power_state(struct ieee80211_hw *hw,
2745 enum rf_pwrstate rfpwr_state)
2747 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
2749 bool bresult = false;
2751 if (rfpwr_state == ppsc->rfpwr_state)
2753 bresult = _rtl8723be_phy_set_rf_power_state(hw, rfpwr_state);