1 /******************************************************************************
3 * Copyright(c) 2009-2010 Realtek Corporation.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
26 * Larry Finger <Larry.Finger@lwfinger.net>
28 *****************************************************************************/
30 #ifndef __RTL_WIFI_H__
31 #define __RTL_WIFI_H__
33 #include <linux/sched.h>
34 #include <linux/firmware.h>
35 #include <linux/etherdevice.h>
36 #include <linux/vmalloc.h>
37 #include <linux/usb.h>
38 #include <net/mac80211.h>
41 #define RF_CHANGE_BY_INIT 0
42 #define RF_CHANGE_BY_IPS BIT(28)
43 #define RF_CHANGE_BY_PS BIT(29)
44 #define RF_CHANGE_BY_HW BIT(30)
45 #define RF_CHANGE_BY_SW BIT(31)
47 #define IQK_ADDA_REG_NUM 16
48 #define IQK_MAC_REG_NUM 4
50 #define MAX_KEY_LEN 61
51 #define KEY_BUF_SIZE 5
54 /*aci: 0x00 Best Effort*/
55 /*aci: 0x01 Background*/
58 /*Max: define total number.*/
64 #define QOS_QUEUE_NUM 4
65 #define RTL_MAC80211_NUM_QUEUE 5
67 #define QBSS_LOAD_SIZE 5
68 #define MAX_WMMELE_LENGTH 64
70 #define TOTAL_CAM_ENTRY 32
72 /*slot time for 11g. */
73 #define RTL_SLOT_TIME_9 9
74 #define RTL_SLOT_TIME_20 20
76 /*related with tcp/ip. */
78 #define ETH_P_PAE 0x888E /*Port Access Entity (IEEE 802.1X) */
79 #define ETH_P_IP 0x0800 /*Internet Protocol packet */
80 #define ETH_P_ARP 0x0806 /*Address Resolution packet */
82 #define PROTOC_TYPE_SIZE 2
84 /*related with 802.11 frame*/
85 #define MAC80211_3ADDR_LEN 24
86 #define MAC80211_4ADDR_LEN 30
88 #define CHANNEL_MAX_NUMBER (14 + 24 + 21) /* 14 is the max channel no */
89 #define CHANNEL_GROUP_MAX (3 + 9) /* ch1~3, 4~9, 10~14 = three groups */
90 #define MAX_PG_GROUP 13
91 #define CHANNEL_GROUP_MAX_2G 3
92 #define CHANNEL_GROUP_IDX_5GL 3
93 #define CHANNEL_GROUP_IDX_5GM 6
94 #define CHANNEL_GROUP_IDX_5GH 9
95 #define CHANNEL_GROUP_MAX_5G 9
96 #define CHANNEL_MAX_NUMBER_2G 14
97 #define AVG_THERMAL_NUM 8
98 #define MAX_TID_COUNT 9
115 enum rt_eeprom_type {
122 RTL_STATUS_INTERFACE_START = 0,
126 HARDWARE_TYPE_RTL8192E,
127 HARDWARE_TYPE_RTL8192U,
128 HARDWARE_TYPE_RTL8192SE,
129 HARDWARE_TYPE_RTL8192SU,
130 HARDWARE_TYPE_RTL8192CE,
131 HARDWARE_TYPE_RTL8192CU,
132 HARDWARE_TYPE_RTL8192DE,
133 HARDWARE_TYPE_RTL8192DU,
134 HARDWARE_TYPE_RTL8723E,
135 HARDWARE_TYPE_RTL8723U,
141 #define IS_HARDWARE_TYPE_8192SU(rtlhal) \
142 (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SU)
143 #define IS_HARDWARE_TYPE_8192SE(rtlhal) \
144 (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SE)
145 #define IS_HARDWARE_TYPE_8192CE(rtlhal) \
146 (rtlhal->hw_type == HARDWARE_TYPE_RTL8192CE)
147 #define IS_HARDWARE_TYPE_8192CU(rtlhal) \
148 (rtlhal->hw_type == HARDWARE_TYPE_RTL8192CU)
149 #define IS_HARDWARE_TYPE_8192DE(rtlhal) \
150 (rtlhal->hw_type == HARDWARE_TYPE_RTL8192DE)
151 #define IS_HARDWARE_TYPE_8192DU(rtlhal) \
152 (rtlhal->hw_type == HARDWARE_TYPE_RTL8192DU)
153 #define IS_HARDWARE_TYPE_8723E(rtlhal) \
154 (rtlhal->hw_type == HARDWARE_TYPE_RTL8723E)
155 #define IS_HARDWARE_TYPE_8723U(rtlhal) \
156 (rtlhal->hw_type == HARDWARE_TYPE_RTL8723U)
157 #define IS_HARDWARE_TYPE_8192S(rtlhal) \
158 (IS_HARDWARE_TYPE_8192SE(rtlhal) || IS_HARDWARE_TYPE_8192SU(rtlhal))
159 #define IS_HARDWARE_TYPE_8192C(rtlhal) \
160 (IS_HARDWARE_TYPE_8192CE(rtlhal) || IS_HARDWARE_TYPE_8192CU(rtlhal))
161 #define IS_HARDWARE_TYPE_8192D(rtlhal) \
162 (IS_HARDWARE_TYPE_8192DE(rtlhal) || IS_HARDWARE_TYPE_8192DU(rtlhal))
163 #define IS_HARDWARE_TYPE_8723(rtlhal) \
164 (IS_HARDWARE_TYPE_8723E(rtlhal) || IS_HARDWARE_TYPE_8723U(rtlhal))
165 #define IS_HARDWARE_TYPE_8723U(rtlhal) \
166 (rtlhal->hw_type == HARDWARE_TYPE_RTL8723U)
168 #define RX_HAL_IS_CCK_RATE(_pdesc)\
169 (_pdesc->rxmcs == DESC92_RATE1M || \
170 _pdesc->rxmcs == DESC92_RATE2M || \
171 _pdesc->rxmcs == DESC92_RATE5_5M || \
172 _pdesc->rxmcs == DESC92_RATE11M)
174 enum scan_operation_backup_opt {
197 u32 rfswitch_control;
200 u32 rfrxiq_imbalance;
202 u32 rftxiq_imbalance;
205 u32 rflssi_readbackpi;
209 IO_CMD_PAUSE_DM_BY_SCAN = 0,
210 IO_CMD_RESUME_DM_BY_SCAN = 1,
215 HW_VAR_MULTICAST_REG,
219 HW_VAR_SECURITY_CONF,
220 HW_VAR_BEACON_INTERVAL,
222 HW_VAR_LISTEN_INTERVAL,
235 HW_VAR_RATE_FALLBACK_CONTROL,
236 HW_VAR_CONTENTION_WINDOW,
241 HW_VAR_AMPDU_MIN_SPACE,
242 HW_VAR_SHORTGI_DENSITY,
244 HW_VAR_MCS_RATE_AVAILABLE,
247 HW_VAR_DIS_Req_Qsize,
248 HW_VAR_CCX_CHNL_LOAD,
249 HW_VAR_CCX_NOISE_HISTOGRAM,
256 HW_VAR_SET_DEV_POWER,
266 HW_VAR_USER_CONTROL_TURBO_MODE,
272 HW_VAR_AUTOLOAD_STATUS,
273 HW_VAR_RF_2R_DISABLE,
275 HW_VAR_H2C_FW_PWRMODE,
276 HW_VAR_H2C_FW_JOINBSSRPT,
277 HW_VAR_FW_PSMODE_STATUS,
278 HW_VAR_1X1_RECV_COMBINE,
279 HW_VAR_STOP_SEND_BEACON,
284 HW_VAR_H2C_FW_UPDATE_GTK,
287 HW_VAR_WF_IS_MAC_ADDR,
288 HW_VAR_H2C_FW_OFFLOAD,
291 HW_VAR_HANDLE_FW_C2H,
292 HW_VAR_DL_FW_RSVD_PAGE,
294 HW_VAR_HW_SEQ_ENABLE,
299 HW_VAR_SWITCH_EPHY_WoWLAN,
300 HW_VAR_INT_MIGRATION,
311 enum _RT_MEDIA_STATUS {
312 RT_MEDIA_DISCONNECT = 0,
318 RT_CID_8187_ALPHA0 = 1,
319 RT_CID_8187_SERCOMM_PS = 2,
320 RT_CID_8187_HW_LED = 3,
321 RT_CID_8187_NETGEAR = 4,
323 RT_CID_819x_CAMEO = 6,
324 RT_CID_819x_RUNTOP = 7,
325 RT_CID_819x_Senao = 8,
327 RT_CID_819x_Netcore = 10,
328 RT_CID_Nettronix = 11,
332 RT_CID_819x_ALPHA = 15,
333 RT_CID_819x_Sitecom = 16,
335 RT_CID_819x_Lenovo = 18,
336 RT_CID_819x_QMI = 19,
337 RT_CID_819x_Edimax_Belkin = 20,
338 RT_CID_819x_Sercomm_Belkin = 21,
339 RT_CID_819x_CAMEO1 = 22,
340 RT_CID_819x_MSI = 23,
341 RT_CID_819x_Acer = 24,
343 RT_CID_819x_CLEVO = 28,
344 RT_CID_819x_Arcadyan_Belkin = 29,
345 RT_CID_819x_SAMSUNG = 30,
346 RT_CID_819x_WNC_COREGA = 31,
347 RT_CID_819x_Foxcoon = 32,
348 RT_CID_819x_DELL = 33,
354 HW_DESC_TX_NEXTDESC_ADDR,
362 PRIME_CHNL_OFFSET_DONT_CARE = 0,
363 PRIME_CHNL_OFFSET_LOWER = 1,
364 PRIME_CHNL_OFFSET_UPPER = 2,
374 enum ht_channel_width {
375 HT_CHANNEL_WIDTH_20 = 0,
376 HT_CHANNEL_WIDTH_20_40 = 1,
379 /* Ref: 802.11i sepc D10.0 7.3.2.25.1
380 Cipher Suites Encryption Algorithms */
383 WEP40_ENCRYPTION = 1,
385 RSERVED_ENCRYPTION = 3,
386 AESCCMP_ENCRYPTION = 4,
387 WEP104_ENCRYPTION = 5,
392 _HAL_STATE_START = 1,
395 enum rtl_desc92_rate {
396 DESC92_RATE1M = 0x00,
397 DESC92_RATE2M = 0x01,
398 DESC92_RATE5_5M = 0x02,
399 DESC92_RATE11M = 0x03,
401 DESC92_RATE6M = 0x04,
402 DESC92_RATE9M = 0x05,
403 DESC92_RATE12M = 0x06,
404 DESC92_RATE18M = 0x07,
405 DESC92_RATE24M = 0x08,
406 DESC92_RATE36M = 0x09,
407 DESC92_RATE48M = 0x0a,
408 DESC92_RATE54M = 0x0b,
410 DESC92_RATEMCS0 = 0x0c,
411 DESC92_RATEMCS1 = 0x0d,
412 DESC92_RATEMCS2 = 0x0e,
413 DESC92_RATEMCS3 = 0x0f,
414 DESC92_RATEMCS4 = 0x10,
415 DESC92_RATEMCS5 = 0x11,
416 DESC92_RATEMCS6 = 0x12,
417 DESC92_RATEMCS7 = 0x13,
418 DESC92_RATEMCS8 = 0x14,
419 DESC92_RATEMCS9 = 0x15,
420 DESC92_RATEMCS10 = 0x16,
421 DESC92_RATEMCS11 = 0x17,
422 DESC92_RATEMCS12 = 0x18,
423 DESC92_RATEMCS13 = 0x19,
424 DESC92_RATEMCS14 = 0x1a,
425 DESC92_RATEMCS15 = 0x1b,
426 DESC92_RATEMCS15_SG = 0x1c,
427 DESC92_RATEMCS32 = 0x20,
450 EFUSE_HWSET_MAX_SIZE,
451 EFUSE_MAX_SECTION_MAP,
452 EFUSE_REAL_CONTENT_SIZE,
453 EFUSE_OOB_PROTECT_BYTES_LEN,
468 RTL_IMR_BCNDMAINT6, /*Beacon DMA Interrupt 6 */
469 RTL_IMR_BCNDMAINT5, /*Beacon DMA Interrupt 5 */
470 RTL_IMR_BCNDMAINT4, /*Beacon DMA Interrupt 4 */
471 RTL_IMR_BCNDMAINT3, /*Beacon DMA Interrupt 3 */
472 RTL_IMR_BCNDMAINT2, /*Beacon DMA Interrupt 2 */
473 RTL_IMR_BCNDMAINT1, /*Beacon DMA Interrupt 1 */
474 RTL_IMR_BCNDOK8, /*Beacon Queue DMA OK Interrup 8 */
475 RTL_IMR_BCNDOK7, /*Beacon Queue DMA OK Interrup 7 */
476 RTL_IMR_BCNDOK6, /*Beacon Queue DMA OK Interrup 6 */
477 RTL_IMR_BCNDOK5, /*Beacon Queue DMA OK Interrup 5 */
478 RTL_IMR_BCNDOK4, /*Beacon Queue DMA OK Interrup 4 */
479 RTL_IMR_BCNDOK3, /*Beacon Queue DMA OK Interrup 3 */
480 RTL_IMR_BCNDOK2, /*Beacon Queue DMA OK Interrup 2 */
481 RTL_IMR_BCNDOK1, /*Beacon Queue DMA OK Interrup 1 */
482 RTL_IMR_TIMEOUT2, /*Timeout interrupt 2 */
483 RTL_IMR_TIMEOUT1, /*Timeout interrupt 1 */
484 RTL_IMR_TXFOVW, /*Transmit FIFO Overflow */
485 RTL_IMR_PSTIMEOUT, /*Power save time out interrupt */
486 RTL_IMR_BcnInt, /*Beacon DMA Interrupt 0 */
487 RTL_IMR_RXFOVW, /*Receive FIFO Overflow */
488 RTL_IMR_RDU, /*Receive Descriptor Unavailable */
489 RTL_IMR_ATIMEND, /*For 92C,ATIM Window End Interrupt */
490 RTL_IMR_BDOK, /*Beacon Queue DMA OK Interrup */
491 RTL_IMR_HIGHDOK, /*High Queue DMA OK Interrupt */
492 RTL_IMR_COMDOK, /*Command Queue DMA OK Interrupt*/
493 RTL_IMR_TBDOK, /*Transmit Beacon OK interrup */
494 RTL_IMR_MGNTDOK, /*Management Queue DMA OK Interrupt */
495 RTL_IMR_TBDER, /*For 92C,Transmit Beacon Error Interrupt */
496 RTL_IMR_BKDOK, /*AC_BK DMA OK Interrupt */
497 RTL_IMR_BEDOK, /*AC_BE DMA OK Interrupt */
498 RTL_IMR_VIDOK, /*AC_VI DMA OK Interrupt */
499 RTL_IMR_VODOK, /*AC_VO DMA Interrupt */
500 RTL_IMR_ROK, /*Receive DMA OK Interrupt */
501 RTL_IBSS_INT_MASKS, /*(RTL_IMR_BcnInt | RTL_IMR_TBDOK |
504 /*CCK Rates, TxHT = 0 */
510 /*OFDM Rates, TxHT = 0 */
527 /*Firmware PS mode for control LPS.*/
529 FW_PS_ACTIVE_MODE = 0,
534 FW_PS_UAPSD_WMM_MODE = 5,
535 FW_PS_UAPSD_MODE = 6,
537 FW_PS_WWLAN_MODE = 8,
538 FW_PS_PM_Radio_Off = 9,
539 FW_PS_PM_Card_Disable = 10,
543 EACTIVE, /*Active/Continuous access. */
544 EMAXPS, /*Max power save mode. */
545 EFASTPS, /*Fast power save mode. */
546 EAUTOPS, /*Auto power save mode. */
551 LED_CTL_POWER_ON = 1,
556 LED_CTL_SITE_SURVEY = 6,
557 LED_CTL_POWER_OFF = 7,
558 LED_CTL_START_TO_LINK = 8,
559 LED_CTL_START_WPS = 9,
560 LED_CTL_STOP_WPS = 10,
571 /*acm implementation method.*/
573 eAcmWay0_SwAndHw = 0,
579 SINGLEMAC_SINGLEPHY = 0,
592 Ref: WMM spec 2.2.2: WME Parameter Element, p.12.*/
606 WIRELESS_MODE_UNKNOWN = 0x00,
607 WIRELESS_MODE_A = 0x01,
608 WIRELESS_MODE_B = 0x02,
609 WIRELESS_MODE_G = 0x04,
610 WIRELESS_MODE_AUTO = 0x08,
611 WIRELESS_MODE_N_24G = 0x10,
612 WIRELESS_MODE_N_5G = 0x20
615 #define IS_WIRELESS_MODE_A(wirelessmode) \
616 (wirelessmode == WIRELESS_MODE_A)
617 #define IS_WIRELESS_MODE_B(wirelessmode) \
618 (wirelessmode == WIRELESS_MODE_B)
619 #define IS_WIRELESS_MODE_G(wirelessmode) \
620 (wirelessmode == WIRELESS_MODE_G)
621 #define IS_WIRELESS_MODE_N_24G(wirelessmode) \
622 (wirelessmode == WIRELESS_MODE_N_24G)
623 #define IS_WIRELESS_MODE_N_5G(wirelessmode) \
624 (wirelessmode == WIRELESS_MODE_N_5G)
626 enum ratr_table_mode {
627 RATR_INX_WIRELESS_NGB = 0,
628 RATR_INX_WIRELESS_NG = 1,
629 RATR_INX_WIRELESS_NB = 2,
630 RATR_INX_WIRELESS_N = 3,
631 RATR_INX_WIRELESS_GB = 4,
632 RATR_INX_WIRELESS_G = 5,
633 RATR_INX_WIRELESS_B = 6,
634 RATR_INX_WIRELESS_MC = 7,
635 RATR_INX_WIRELESS_A = 8,
638 enum rtl_link_state {
640 MAC80211_LINKING = 1,
642 MAC80211_LINKED_SCANNING = 3,
659 struct octet_string {
664 struct rtl_hdr_3addr {
674 struct rtl_info_element {
680 struct rtl_probe_rsp {
681 struct rtl_hdr_3addr header;
683 __le16 beacon_interval;
685 /*SSID, supported rates, FH params, DS params,
686 CF params, IBSS params, TIM (if beacon), RSN */
687 struct rtl_info_element info_element[0];
691 /*ledpin Identify how to implement this SW led.*/
694 enum rtl_led_pin ledpin;
700 struct rtl_led sw_led0;
701 struct rtl_led sw_led1;
704 struct rtl_qos_parameters {
712 struct rt_smooth_data {
713 u32 elements[100]; /*array to store values */
714 u32 index; /*index to current array to store */
715 u32 total_num; /*num of valid elements */
716 u32 total_val; /*sum of valid elements */
719 struct false_alarm_statistics {
721 u32 cnt_rate_illegal;
724 u32 cnt_fast_fsync_fail;
725 u32 cnt_sb_search_fail;
740 struct wireless_stats {
741 unsigned long txbytesunicast;
742 unsigned long txbytesmulticast;
743 unsigned long txbytesbroadcast;
744 unsigned long rxbytesunicast;
747 /*Correct smoothed ss in Dbm, only used
748 in driver to report real power now. */
749 long recv_signal_power;
751 long last_sigstrength_inpercent;
753 u32 rssi_calculate_cnt;
755 /*Transformed, in dbm. Beautified signal
756 strength for UI, not correct. */
757 long signal_strength;
759 u8 rx_rssi_percentage[4];
760 u8 rx_evm_percentage[2];
762 struct rt_smooth_data ui_rssi;
763 struct rt_smooth_data ui_link_quality;
766 struct rate_adaptive {
767 u8 rate_adaptive_disabled;
771 u32 high_rssi_thresh_for_ra;
772 u32 high2low_rssi_thresh_for_ra;
773 u8 low2high_rssi_thresh_for_ra40m;
774 u32 low_rssi_thresh_for_ra40M;
775 u8 low2high_rssi_thresh_for_ra20m;
776 u32 low_rssi_thresh_for_ra20M;
777 u32 upper_rssi_threshold_ratr;
778 u32 middleupper_rssi_threshold_ratr;
779 u32 middle_rssi_threshold_ratr;
780 u32 middlelow_rssi_threshold_ratr;
781 u32 low_rssi_threshold_ratr;
782 u32 ultralow_rssi_threshold_ratr;
783 u32 low_rssi_threshold_ratr_40m;
784 u32 low_rssi_threshold_ratr_20m;
787 u32 ping_rssi_thresh_for_ra;
792 struct regd_pair_mapping {
798 struct rtl_regulatory {
806 struct regd_pair_mapping *regpair;
810 bool rfkill_state; /*0 is off, 1 is on */
813 #define IQK_MATRIX_REG_NUM 8
814 #define IQK_MATRIX_SETTINGS_NUM (1 + 24 + 21)
815 struct iqk_matrix_regs {
817 long value[1][IQK_MATRIX_REG_NUM];
820 struct phy_parameters {
825 enum hw_param_tab_index {
840 struct bb_reg_def phyreg_def[4]; /*Radio A/B/C/D */
841 struct init_gain initgain_backup;
842 enum io_type current_io_type;
847 u8 set_bwmode_inprogress;
848 u8 sw_chnl_inprogress;
853 u8 set_io_inprogress;
856 /* record for power tracking */
868 u32 reg_c04, reg_c08, reg_874;
870 u32 iqk_mac_backup[IQK_MAC_REG_NUM];
871 u32 iqk_bb_backup[10];
875 struct iqk_matrix_regs iqk_matrix_regsetting[IQK_MATRIX_SETTINGS_NUM];
881 /* MAX_PG_GROUP groups of pwr diff by rates */
882 u32 mcs_txpwrlevel_origoffset[MAX_PG_GROUP][16];
883 u8 default_initialgain[4];
885 /* the current Tx power level */
887 u8 cur_ofdm24g_txpwridx;
889 u32 rfreg_chnlval[2];
891 u32 reg_rf3c[2]; /* pathA / pathB */
898 struct phy_parameters hwparam_tables[MAX_TAB];
902 #define MAX_TID_COUNT 9
903 #define RTL_AGG_STOP 0
904 #define RTL_AGG_PROGRESS 1
905 #define RTL_AGG_START 2
906 #define RTL_AGG_OPERATIONAL 3
907 #define RTL_AGG_OFF 0
909 #define RTL_AGG_EMPTYING_HW_QUEUE_ADDBA 2
910 #define RTL_AGG_EMPTYING_HW_QUEUE_DELBA 3
921 struct rtl_tid_data {
923 struct rtl_ht_agg agg;
926 struct rtl_sta_info {
930 struct rtl_tid_data tids[MAX_TID_COUNT];
936 struct mutex bb_mutex;
939 unsigned long pci_mem_end; /*shared mem end */
940 unsigned long pci_mem_start; /*shared mem start */
943 unsigned long pci_base_addr; /*device I/O address */
945 void (*write8_async) (struct rtl_priv *rtlpriv, u32 addr, u8 val);
946 void (*write16_async) (struct rtl_priv *rtlpriv, u32 addr, __le16 val);
947 void (*write32_async) (struct rtl_priv *rtlpriv, u32 addr, __le32 val);
949 u8(*read8_sync) (struct rtl_priv *rtlpriv, u32 addr);
950 u16(*read16_sync) (struct rtl_priv *rtlpriv, u32 addr);
951 u32(*read32_sync) (struct rtl_priv *rtlpriv, u32 addr);
956 u8 mac_addr[ETH_ALEN];
957 u8 mac80211_registered;
963 struct ieee80211_supported_band bands[IEEE80211_NUM_BANDS];
964 struct ieee80211_hw *hw;
965 struct ieee80211_vif *vif;
966 enum nl80211_iftype opmode;
968 /*Probe Beacon management */
969 struct rtl_tid_data tids[MAX_TID_COUNT];
970 enum rtl_link_state link_state;
988 struct sk_buff_head skb_waitq[MAX_TID_COUNT];
989 u8 earlymode_threshold;
997 u8 mcs[16]; /* 16 bytes mcs for HT rates. */
998 u32 basic_rates; /* b/g rates */
1003 u8 mode; /* wireless mode */
1008 u8 cur_40_prime_sc_bk;
1015 int beacon_interval;
1018 u8 min_space_cfg; /*For Min spacing configurations */
1020 u8 current_ampdu_factor;
1021 u8 current_ampdu_density;
1024 struct ieee80211_tx_queue_params edca_param[RTL_MAC80211_NUM_QUEUE];
1025 struct rtl_qos_parameters ac[AC_MAX];
1029 struct ieee80211_hw *hw;
1031 enum intf_type interface;
1032 u16 hw_type; /*92c or 92d or 92s and so on */
1035 u32 version; /*version of chip */
1036 u8 state; /*stop 0, start 1 */
1043 bool h2c_setinprogress;
1046 /*Reserve page start offset except beacon in TxQ. */
1047 u8 fw_rsvdpage_startoffset;
1050 /* FW Cmd IO related */
1053 bool set_fwcmd_inprogress;
1054 u8 current_fwcmd_io;
1057 bool driver_going2unload;
1059 /*AMPDU init min space*/
1060 u8 minspace_cfg; /*For Min spacing configurations */
1063 enum macphy_mode macphymode;
1064 enum band_type current_bandtype; /* 0:2.4G, 1:5G */
1065 enum band_type current_bandtypebackup;
1066 enum band_type bandset;
1067 /* dual MAC 0--Mac0 1--Mac1 */
1069 /* just for DualMac S3S4 */
1071 bool earlymode_enable;
1073 bool during_mac0init_radiob;
1074 bool during_mac1init_radioa;
1075 bool reloadtxpowerindex;
1076 /* True if IMR or IQK have done
1077 for 2.4G in scan progress */
1078 bool load_imrandiqk_setting_for2g;
1080 bool disable_amsdu_8k;
1083 struct rtl_security {
1088 bool use_defaultkey;
1089 /*Encryption Algorithm for Unicast Packet */
1090 enum rt_enc_alg pairwise_enc_algorithm;
1091 /*Encryption Algorithm for Brocast/Multicast */
1092 enum rt_enc_alg group_enc_algorithm;
1093 /*Cam Entry Bitmap */
1094 u32 hwsec_cam_bitmap;
1095 u8 hwsec_cam_sta_addr[TOTAL_CAM_ENTRY][ETH_ALEN];
1096 /*local Key buffer, indx 0 is for
1097 pairwise key 1-4 is for agoup key. */
1098 u8 key_buf[KEY_BUF_SIZE][MAX_KEY_LEN];
1099 u8 key_len[KEY_BUF_SIZE];
1101 /*The pointer of Pairwise Key,
1102 it always points to KeyBuf[4] */
1107 /*PHY status for Dynamic Management */
1108 long entry_min_undecoratedsmoothed_pwdb;
1109 long undecorated_smoothed_pwdb; /*out dm */
1110 long entry_max_undecoratedsmoothed_pwdb;
1111 bool dm_initialgain_enable;
1112 bool dynamic_txpower_enable;
1113 bool current_turbo_edca;
1114 bool is_any_nonbepkts; /*out dm */
1115 bool is_cur_rdlstate;
1116 bool txpower_trackinginit;
1117 bool disable_framebursting;
1119 bool txpower_tracking;
1121 bool rfpath_rxenable[4];
1122 bool inform_fw_driverctrldm;
1123 bool current_mrc_switch;
1126 u8 thermalvalue_rxgain;
1127 u8 thermalvalue_iqk;
1128 u8 thermalvalue_lck;
1131 u8 thermalvalue_avg[AVG_THERMAL_NUM];
1132 u8 thermalvalue_avg_index;
1134 u8 dynamic_txhighpower_lvl; /*Tx high power level */
1135 u8 dm_flag; /*Indicate each dynamic mechanism's status. */
1137 u8 txpower_track_control;
1138 bool interrupt_migration;
1139 bool disable_tx_int;
1144 #define EFUSE_MAX_LOGICAL_SIZE 256
1149 u16 max_physical_size;
1151 u8 efuse_map[2][EFUSE_MAX_LOGICAL_SIZE];
1152 u16 efuse_usedbytes;
1153 u8 efuse_usedpercentage;
1154 #ifdef EFUSE_REPG_WORKAROUND
1155 bool efuse_re_pg_sec1flag;
1156 u8 efuse_re_pg_data[8];
1159 u8 autoload_failflag;
1168 u16 eeprom_channelplan;
1175 bool txpwr_fromeprom;
1176 u8 eeprom_crystalcap;
1178 u8 eeprom_tssi_5g[3][2]; /* for 5GL/5GM/5GH band. */
1179 u8 eeprom_pwrlimit_ht20[CHANNEL_GROUP_MAX];
1180 u8 eeprom_pwrlimit_ht40[CHANNEL_GROUP_MAX];
1181 u8 eeprom_chnlarea_txpwr_cck[2][CHANNEL_GROUP_MAX_2G];
1182 u8 eeprom_chnlarea_txpwr_ht40_1s[2][CHANNEL_GROUP_MAX];
1183 u8 eeprom_chnlarea_txpwr_ht40_2sdiif[2][CHANNEL_GROUP_MAX];
1184 u8 txpwrlevel_cck[2][CHANNEL_MAX_NUMBER_2G];
1185 u8 txpwrlevel_ht40_1s[2][CHANNEL_MAX_NUMBER]; /*For HT 40MHZ pwr */
1186 u8 txpwrlevel_ht40_2s[2][CHANNEL_MAX_NUMBER]; /*For HT 40MHZ pwr */
1188 u8 internal_pa_5g[2]; /* pathA / pathB */
1192 /*For power group */
1193 u8 eeprom_pwrgroup[2][3];
1194 u8 pwrgroup_ht20[2][CHANNEL_MAX_NUMBER];
1195 u8 pwrgroup_ht40[2][CHANNEL_MAX_NUMBER];
1197 char txpwr_ht20diff[2][CHANNEL_MAX_NUMBER]; /*HT 20<->40 Pwr diff */
1198 /*For HT<->legacy pwr diff*/
1199 u8 txpwr_legacyhtdiff[2][CHANNEL_MAX_NUMBER];
1200 u8 txpwr_safetyflag; /* Band edge enable flag */
1201 u16 eeprom_txpowerdiff;
1202 u8 legacy_httxpowerdiff; /* Legacy to HT rate power diff */
1203 u8 antenna_txpwdiff[3];
1205 u8 eeprom_regulatory;
1206 u8 eeprom_thermalmeter;
1207 u8 thermalmeter[2]; /*ThermalMeter, index 0 for RFIC0, 1 for RFIC1 */
1209 u8 crystalcap; /* CrystalCap. */
1213 u8 legacy_ht_txpowerdiff; /*Legacy to HT rate power diff */
1214 bool apk_thermalmeterignore;
1216 bool b1x1_recvcombine;
1224 bool pwrdomain_protect;
1225 bool in_powersavemode;
1226 bool rfchange_inprogress;
1227 bool swrf_processing;
1231 * just for PCIE ASPM
1232 * If it supports ASPM, Offset[560h] = 0x40,
1233 * otherwise Offset[560h] = 0x00.
1237 bool support_backdoor;
1240 enum rt_psmode dot11_psmode; /*Power save mode configured. */
1245 /*For Fw control LPS mode */
1247 /*Record Fw PS mode status. */
1248 bool fw_current_inpsmode;
1249 u8 reg_max_lps_awakeintvl;
1261 /*just for PCIE ASPM */
1262 u8 const_amdpci_aspm;
1265 enum rf_pwrstate inactive_pwrstate;
1266 enum rf_pwrstate rfpwr_state; /*cur power state */
1272 bool multi_buffered;
1274 unsigned int dtim_counter;
1275 unsigned int sleep_ms;
1276 unsigned long last_sleep_jiffies;
1277 unsigned long last_awake_jiffies;
1278 unsigned long last_delaylps_stamp_jiffies;
1279 unsigned long last_dtim;
1280 unsigned long last_beacon;
1281 unsigned long last_action;
1282 unsigned long last_slept;
1290 u16 rate; /*in 100 kbps */
1291 u8 received_channel;
1300 u8 signalquality; /*in 0-100 index. */
1302 * Real power in dBm for this packet,
1303 * no beautification and aggregation.
1305 s32 recvsignalpower;
1306 s8 rxpower; /*in dBm Translate from PWdB */
1307 u8 signalstrength; /*in 0-100 index. */
1311 u16 shortpreamble:1;
1322 bool rx_is40Mhzpacket;
1324 u8 rx_mimo_signalstrength[4]; /*in 0~100 index */
1325 s8 rx_mimo_signalquality[2];
1326 bool packet_matchbssid;
1330 bool packet_beacon; /*for rssi */
1331 char cck_adc_pwdb[4]; /*for rx path selection */
1334 struct rt_link_detect {
1335 u32 num_tx_in4period[4];
1336 u32 num_rx_in4period[4];
1338 u32 num_tx_inperiod;
1339 u32 num_rx_inperiod;
1342 bool higher_busytraffic;
1343 bool higher_busyrxtraffic;
1345 u32 tidtx_in4period[MAX_TID_COUNT][4];
1346 u32 tidtx_inperiod[MAX_TID_COUNT];
1347 bool higher_busytxtraffic[MAX_TID_COUNT];
1350 struct rtl_tcb_desc {
1358 u8 rts_use_shortpreamble:1;
1359 u8 rts_use_shortgi:1;
1365 u8 use_shortpreamble:1;
1366 u8 use_driver_rate:1;
1367 u8 disable_ratefallback:1;
1379 /* The max value by HW */
1383 struct rtl_hal_ops {
1384 int (*init_sw_vars) (struct ieee80211_hw *hw);
1385 void (*deinit_sw_vars) (struct ieee80211_hw *hw);
1386 void (*read_chip_version)(struct ieee80211_hw *hw);
1387 void (*read_eeprom_info) (struct ieee80211_hw *hw);
1388 void (*interrupt_recognized) (struct ieee80211_hw *hw,
1389 u32 *p_inta, u32 *p_intb);
1390 int (*hw_init) (struct ieee80211_hw *hw);
1391 void (*hw_disable) (struct ieee80211_hw *hw);
1392 void (*hw_suspend) (struct ieee80211_hw *hw);
1393 void (*hw_resume) (struct ieee80211_hw *hw);
1394 void (*enable_interrupt) (struct ieee80211_hw *hw);
1395 void (*disable_interrupt) (struct ieee80211_hw *hw);
1396 int (*set_network_type) (struct ieee80211_hw *hw,
1397 enum nl80211_iftype type);
1398 void (*set_chk_bssid)(struct ieee80211_hw *hw,
1400 void (*set_bw_mode) (struct ieee80211_hw *hw,
1401 enum nl80211_channel_type ch_type);
1402 u8(*switch_channel) (struct ieee80211_hw *hw);
1403 void (*set_qos) (struct ieee80211_hw *hw, int aci);
1404 void (*set_bcn_reg) (struct ieee80211_hw *hw);
1405 void (*set_bcn_intv) (struct ieee80211_hw *hw);
1406 void (*update_interrupt_mask) (struct ieee80211_hw *hw,
1407 u32 add_msr, u32 rm_msr);
1408 void (*get_hw_reg) (struct ieee80211_hw *hw, u8 variable, u8 *val);
1409 void (*set_hw_reg) (struct ieee80211_hw *hw, u8 variable, u8 *val);
1410 void (*update_rate_tbl) (struct ieee80211_hw *hw,
1411 struct ieee80211_sta *sta, u8 rssi_level);
1412 void (*update_rate_mask) (struct ieee80211_hw *hw, u8 rssi_level);
1413 void (*fill_tx_desc) (struct ieee80211_hw *hw,
1414 struct ieee80211_hdr *hdr, u8 *pdesc_tx,
1415 struct ieee80211_tx_info *info,
1416 struct sk_buff *skb, u8 hw_queue,
1417 struct rtl_tcb_desc *ptcb_desc);
1418 void (*fill_fake_txdesc) (struct ieee80211_hw *hw, u8 *pDesc,
1419 u32 buffer_len, bool bIsPsPoll);
1420 void (*fill_tx_cmddesc) (struct ieee80211_hw *hw, u8 *pdesc,
1421 bool firstseg, bool lastseg,
1422 struct sk_buff *skb);
1423 bool (*cmd_send_packet)(struct ieee80211_hw *hw, struct sk_buff *skb);
1424 bool (*query_rx_desc) (struct ieee80211_hw *hw,
1425 struct rtl_stats *stats,
1426 struct ieee80211_rx_status *rx_status,
1427 u8 *pdesc, struct sk_buff *skb);
1428 void (*set_channel_access) (struct ieee80211_hw *hw);
1429 bool (*radio_onoff_checking) (struct ieee80211_hw *hw, u8 *valid);
1430 void (*dm_watchdog) (struct ieee80211_hw *hw);
1431 void (*scan_operation_backup) (struct ieee80211_hw *hw, u8 operation);
1432 bool (*set_rf_power_state) (struct ieee80211_hw *hw,
1433 enum rf_pwrstate rfpwr_state);
1434 void (*led_control) (struct ieee80211_hw *hw,
1435 enum led_ctl_mode ledaction);
1436 void (*set_desc) (u8 *pdesc, bool istx, u8 desc_name, u8 *val);
1437 u32 (*get_desc) (u8 *pdesc, bool istx, u8 desc_name);
1438 void (*tx_polling) (struct ieee80211_hw *hw, u8 hw_queue);
1439 void (*enable_hw_sec) (struct ieee80211_hw *hw);
1440 void (*set_key) (struct ieee80211_hw *hw, u32 key_index,
1441 u8 *macaddr, bool is_group, u8 enc_algo,
1442 bool is_wepkey, bool clear_all);
1443 void (*init_sw_leds) (struct ieee80211_hw *hw);
1444 void (*deinit_sw_leds) (struct ieee80211_hw *hw);
1445 u32 (*get_bbreg) (struct ieee80211_hw *hw, u32 regaddr, u32 bitmask);
1446 void (*set_bbreg) (struct ieee80211_hw *hw, u32 regaddr, u32 bitmask,
1448 u32 (*get_rfreg) (struct ieee80211_hw *hw, enum radio_path rfpath,
1449 u32 regaddr, u32 bitmask);
1450 void (*set_rfreg) (struct ieee80211_hw *hw, enum radio_path rfpath,
1451 u32 regaddr, u32 bitmask, u32 data);
1452 void (*linked_set_reg) (struct ieee80211_hw *hw);
1453 bool (*phy_rf6052_config) (struct ieee80211_hw *hw);
1454 void (*phy_rf6052_set_cck_txpower) (struct ieee80211_hw *hw,
1456 void (*phy_rf6052_set_ofdm_txpower) (struct ieee80211_hw *hw,
1457 u8 *ppowerlevel, u8 channel);
1458 bool (*config_bb_with_headerfile) (struct ieee80211_hw *hw,
1460 bool (*config_bb_with_pgheaderfile) (struct ieee80211_hw *hw,
1462 void (*phy_lc_calibrate) (struct ieee80211_hw *hw, bool is2t);
1463 void (*phy_set_bw_mode_callback) (struct ieee80211_hw *hw);
1464 void (*dm_dynamic_txpower) (struct ieee80211_hw *hw);
1467 struct rtl_intf_ops {
1469 void (*read_efuse_byte)(struct ieee80211_hw *hw, u16 _offset, u8 *pbuf);
1470 int (*adapter_start) (struct ieee80211_hw *hw);
1471 void (*adapter_stop) (struct ieee80211_hw *hw);
1473 int (*adapter_tx) (struct ieee80211_hw *hw, struct sk_buff *skb,
1474 struct rtl_tcb_desc *ptcb_desc);
1475 void (*flush)(struct ieee80211_hw *hw, bool drop);
1476 int (*reset_trx_ring) (struct ieee80211_hw *hw);
1477 bool (*waitq_insert) (struct ieee80211_hw *hw, struct sk_buff *skb);
1480 void (*disable_aspm) (struct ieee80211_hw *hw);
1481 void (*enable_aspm) (struct ieee80211_hw *hw);
1486 struct rtl_mod_params {
1487 /* default: 0 = using hardware encryption */
1490 /* default: 0 = DBG_EMERG (0)*/
1493 /* default: 1 = using no linked power save */
1496 /* default: 1 = using linked sw power save */
1499 /* default: 1 = using linked fw power save */
1503 struct rtl_hal_usbint_cfg {
1510 void (*usb_rx_hdl)(struct ieee80211_hw *, struct sk_buff *);
1511 void (*usb_rx_segregate_hdl)(struct ieee80211_hw *, struct sk_buff *,
1512 struct sk_buff_head *);
1515 void (*usb_tx_cleanup)(struct ieee80211_hw *, struct sk_buff *);
1516 int (*usb_tx_post_hdl)(struct ieee80211_hw *, struct urb *,
1518 struct sk_buff *(*usb_tx_aggregate_hdl)(struct ieee80211_hw *,
1519 struct sk_buff_head *);
1521 /* endpoint mapping */
1522 int (*usb_endpoint_mapping)(struct ieee80211_hw *hw);
1523 u16 (*usb_mq_to_hwq)(__le16 fc, u16 mac80211_queue_index);
1526 struct rtl_hal_cfg {
1528 bool write_readback;
1531 struct rtl_hal_ops *ops;
1532 struct rtl_mod_params *mod_params;
1533 struct rtl_hal_usbint_cfg *usb_interface_cfg;
1535 /*this map used for some registers or vars
1536 defined int HAL but used in MAIN */
1537 u32 maps[RTL_VAR_MAP_MAX];
1543 struct mutex conf_mutex;
1546 spinlock_t ips_lock;
1547 spinlock_t irq_th_lock;
1548 spinlock_t h2c_lock;
1549 spinlock_t rf_ps_lock;
1551 spinlock_t lps_lock;
1552 spinlock_t waitq_lock;
1555 spinlock_t cck_and_rw_pagea_lock;
1559 struct ieee80211_hw *hw;
1562 struct timer_list watchdog_timer;
1565 struct tasklet_struct irq_tasklet;
1566 struct tasklet_struct irq_prepare_bcn_tasklet;
1569 struct workqueue_struct *rtl_wq;
1570 struct delayed_work watchdog_wq;
1571 struct delayed_work ips_nic_off_wq;
1574 struct delayed_work ps_work;
1575 struct delayed_work ps_rfon_wq;
1576 struct tasklet_struct ips_leave_tasklet;
1580 u32 dbgp_type[DBGP_TYPE_MAX];
1581 u32 global_debuglevel;
1582 u64 global_debugcomponents;
1584 /* add for proc debug */
1585 struct proc_dir_entry *proc_dir;
1590 struct rtl_locks locks;
1591 struct rtl_works works;
1592 struct rtl_mac mac80211;
1593 struct rtl_hal rtlhal;
1594 struct rtl_regulatory regd;
1595 struct rtl_rfkill rfkill;
1599 struct rtl_security sec;
1600 struct rtl_efuse efuse;
1602 struct rtl_ps_ctl psc;
1603 struct rate_adaptive ra;
1604 struct wireless_stats stats;
1605 struct rt_link_detect link_info;
1606 struct false_alarm_statistics falsealm_cnt;
1608 struct rtl_rate_priv *rate_priv;
1610 struct rtl_debug dbg;
1613 *hal_cfg : for diff cards
1614 *intf_ops : for diff interrface usb/pcie
1616 struct rtl_hal_cfg *cfg;
1617 struct rtl_intf_ops *intf_ops;
1619 /*this var will be set by set_bit,
1620 and was used to indicate status of
1621 interface or hardware */
1622 unsigned long status;
1624 /*This must be the last item so
1625 that it points to the data allocated
1626 beyond this structure like:
1627 rtl_pci_priv or rtl_usb_priv */
1631 #define rtl_priv(hw) (((struct rtl_priv *)(hw)->priv))
1632 #define rtl_mac(rtlpriv) (&((rtlpriv)->mac80211))
1633 #define rtl_hal(rtlpriv) (&((rtlpriv)->rtlhal))
1634 #define rtl_efuse(rtlpriv) (&((rtlpriv)->efuse))
1635 #define rtl_psc(rtlpriv) (&((rtlpriv)->psc))
1638 /***************************************
1639 Bluetooth Co-existence Related
1640 ****************************************/
1661 enum bt_service_type {
1668 BT_OTHER_ACTION = 6,
1674 enum bt_radio_shared {
1675 BT_RADIO_SHARED = 0,
1676 BT_RADIO_INDIVIDUAL = 1,
1679 struct bt_coexist_info {
1681 /* EEPROM BT info. */
1682 u8 eeprom_bt_coexist;
1684 u8 eeprom_bt_ant_num;
1685 u8 eeprom_bt_ant_isolation;
1686 u8 eeprom_bt_radio_shared;
1692 u8 bt_cur_state; /* 0:on, 1:off */
1693 u8 bt_ant_isolation; /* 0:good, 1:bad */
1694 u8 bt_pape_ctrl; /* 0:SW, 1:SW/HW dynamic */
1696 u8 bt_radio_shared_type;
1697 u8 bt_rfreg_origin_1e;
1698 u8 bt_rfreg_origin_1f;
1706 bool bt_busy_traffic;
1707 bool bt_traffic_mode_set;
1708 bool bt_non_traffic_mode_set;
1710 bool fw_coexist_all_off;
1711 bool sw_coexist_all_off;
1714 u8 bt_pre_rssi_state;
1722 /****************************************
1723 mem access macro define start
1724 Call endian free function when
1725 1. Read/write packet content.
1726 2. Before write integer to IO.
1727 3. After read integer from IO.
1728 ****************************************/
1729 /* Convert little data endian to host ordering */
1730 #define EF1BYTE(_val) \
1732 #define EF2BYTE(_val) \
1734 #define EF4BYTE(_val) \
1737 /* Read data from memory */
1738 #define READEF1BYTE(_ptr) \
1739 EF1BYTE(*((u8 *)(_ptr)))
1740 /* Read le16 data from memory and convert to host ordering */
1741 #define READEF2BYTE(_ptr) \
1742 EF2BYTE(*((u16 *)(_ptr)))
1743 #define READEF4BYTE(_ptr) \
1744 EF4BYTE(*((u32 *)(_ptr)))
1746 /* Write data to memory */
1747 #define WRITEEF1BYTE(_ptr, _val) \
1748 (*((u8 *)(_ptr))) = EF1BYTE(_val)
1749 /* Write le16 data to memory in host ordering */
1750 #define WRITEEF2BYTE(_ptr, _val) \
1751 (*((u16 *)(_ptr))) = EF2BYTE(_val)
1752 #define WRITEEF4BYTE(_ptr, _val) \
1753 (*((u16 *)(_ptr))) = EF2BYTE(_val)
1755 /* Create a bit mask
1757 * BIT_LEN_MASK_32(0) => 0x00000000
1758 * BIT_LEN_MASK_32(1) => 0x00000001
1759 * BIT_LEN_MASK_32(2) => 0x00000003
1760 * BIT_LEN_MASK_32(32) => 0xFFFFFFFF
1762 #define BIT_LEN_MASK_32(__bitlen) \
1763 (0xFFFFFFFF >> (32 - (__bitlen)))
1764 #define BIT_LEN_MASK_16(__bitlen) \
1765 (0xFFFF >> (16 - (__bitlen)))
1766 #define BIT_LEN_MASK_8(__bitlen) \
1767 (0xFF >> (8 - (__bitlen)))
1769 /* Create an offset bit mask
1771 * BIT_OFFSET_LEN_MASK_32(0, 2) => 0x00000003
1772 * BIT_OFFSET_LEN_MASK_32(16, 2) => 0x00030000
1774 #define BIT_OFFSET_LEN_MASK_32(__bitoffset, __bitlen) \
1775 (BIT_LEN_MASK_32(__bitlen) << (__bitoffset))
1776 #define BIT_OFFSET_LEN_MASK_16(__bitoffset, __bitlen) \
1777 (BIT_LEN_MASK_16(__bitlen) << (__bitoffset))
1778 #define BIT_OFFSET_LEN_MASK_8(__bitoffset, __bitlen) \
1779 (BIT_LEN_MASK_8(__bitlen) << (__bitoffset))
1782 * Return 4-byte value in host byte ordering from
1783 * 4-byte pointer in little-endian system.
1785 #define LE_P4BYTE_TO_HOST_4BYTE(__pstart) \
1786 (EF4BYTE(*((u32 *)(__pstart))))
1787 #define LE_P2BYTE_TO_HOST_2BYTE(__pstart) \
1788 (EF2BYTE(*((u16 *)(__pstart))))
1789 #define LE_P1BYTE_TO_HOST_1BYTE(__pstart) \
1790 (EF1BYTE(*((u8 *)(__pstart))))
1793 Translate subfield (continuous bits in little-endian) of 4-byte
1794 value to host byte ordering.*/
1795 #define LE_BITS_TO_4BYTE(__pstart, __bitoffset, __bitlen) \
1797 (LE_P4BYTE_TO_HOST_4BYTE(__pstart) >> (__bitoffset)) & \
1798 BIT_LEN_MASK_32(__bitlen) \
1800 #define LE_BITS_TO_2BYTE(__pstart, __bitoffset, __bitlen) \
1802 (LE_P2BYTE_TO_HOST_2BYTE(__pstart) >> (__bitoffset)) & \
1803 BIT_LEN_MASK_16(__bitlen) \
1805 #define LE_BITS_TO_1BYTE(__pstart, __bitoffset, __bitlen) \
1807 (LE_P1BYTE_TO_HOST_1BYTE(__pstart) >> (__bitoffset)) & \
1808 BIT_LEN_MASK_8(__bitlen) \
1812 * Mask subfield (continuous bits in little-endian) of 4-byte value
1813 * and return the result in 4-byte value in host byte ordering.
1815 #define LE_BITS_CLEARED_TO_4BYTE(__pstart, __bitoffset, __bitlen) \
1817 LE_P4BYTE_TO_HOST_4BYTE(__pstart) & \
1818 (~BIT_OFFSET_LEN_MASK_32(__bitoffset, __bitlen)) \
1820 #define LE_BITS_CLEARED_TO_2BYTE(__pstart, __bitoffset, __bitlen) \
1822 LE_P2BYTE_TO_HOST_2BYTE(__pstart) & \
1823 (~BIT_OFFSET_LEN_MASK_16(__bitoffset, __bitlen)) \
1825 #define LE_BITS_CLEARED_TO_1BYTE(__pstart, __bitoffset, __bitlen) \
1827 LE_P1BYTE_TO_HOST_1BYTE(__pstart) & \
1828 (~BIT_OFFSET_LEN_MASK_8(__bitoffset, __bitlen)) \
1832 * Set subfield of little-endian 4-byte value to specified value.
1834 #define SET_BITS_TO_LE_4BYTE(__pstart, __bitoffset, __bitlen, __val) \
1835 *((u32 *)(__pstart)) = EF4BYTE \
1837 LE_BITS_CLEARED_TO_4BYTE(__pstart, __bitoffset, __bitlen) | \
1838 ((((u32)__val) & BIT_LEN_MASK_32(__bitlen)) << (__bitoffset)) \
1840 #define SET_BITS_TO_LE_2BYTE(__pstart, __bitoffset, __bitlen, __val) \
1841 *((u16 *)(__pstart)) = EF2BYTE \
1843 LE_BITS_CLEARED_TO_2BYTE(__pstart, __bitoffset, __bitlen) | \
1844 ((((u16)__val) & BIT_LEN_MASK_16(__bitlen)) << (__bitoffset)) \
1846 #define SET_BITS_TO_LE_1BYTE(__pstart, __bitoffset, __bitlen, __val) \
1847 *((u8 *)(__pstart)) = EF1BYTE \
1849 LE_BITS_CLEARED_TO_1BYTE(__pstart, __bitoffset, __bitlen) | \
1850 ((((u8)__val) & BIT_LEN_MASK_8(__bitlen)) << (__bitoffset)) \
1853 #define N_BYTE_ALIGMENT(__value, __aligment) ((__aligment == 1) ? \
1854 (__value) : (((__value + __aligment - 1) / __aligment) * __aligment))
1856 /****************************************
1857 mem access macro define end
1858 ****************************************/
1860 #define byte(x, n) ((x >> (8 * n)) & 0xff)
1862 #define packet_get_type(_packet) (EF1BYTE((_packet).octet[0]) & 0xFC)
1863 #define RTL_WATCH_DOG_TIME 2000
1864 #define MSECS(t) msecs_to_jiffies(t)
1865 #define WLAN_FC_GET_VERS(fc) (le16_to_cpu(fc) & IEEE80211_FCTL_VERS)
1866 #define WLAN_FC_GET_TYPE(fc) (le16_to_cpu(fc) & IEEE80211_FCTL_FTYPE)
1867 #define WLAN_FC_GET_STYPE(fc) (le16_to_cpu(fc) & IEEE80211_FCTL_STYPE)
1868 #define WLAN_FC_MORE_DATA(fc) (le16_to_cpu(fc) & IEEE80211_FCTL_MOREDATA)
1869 #define SEQ_TO_SN(seq) (((seq) & IEEE80211_SCTL_SEQ) >> 4)
1870 #define SN_TO_SEQ(ssn) (((ssn) << 4) & IEEE80211_SCTL_SEQ)
1871 #define MAX_SN ((IEEE80211_SCTL_SEQ) >> 4)
1873 #define RT_RF_OFF_LEVL_ASPM BIT(0) /*PCI ASPM */
1874 #define RT_RF_OFF_LEVL_CLK_REQ BIT(1) /*PCI clock request */
1875 #define RT_RF_OFF_LEVL_PCI_D3 BIT(2) /*PCI D3 mode */
1876 /*NIC halt, re-initialize hw parameters*/
1877 #define RT_RF_OFF_LEVL_HALT_NIC BIT(3)
1878 #define RT_RF_OFF_LEVL_FREE_FW BIT(4) /*FW free, re-download the FW */
1879 #define RT_RF_OFF_LEVL_FW_32K BIT(5) /*FW in 32k */
1880 /*Always enable ASPM and Clock Req in initialization.*/
1881 #define RT_RF_PS_LEVEL_ALWAYS_ASPM BIT(6)
1882 /* no matter RFOFF or SLEEP we set PS_ASPM_LEVL*/
1883 #define RT_PS_LEVEL_ASPM BIT(7)
1884 /*When LPS is on, disable 2R if no packet is received or transmittd.*/
1885 #define RT_RF_LPS_DISALBE_2R BIT(30)
1886 #define RT_RF_LPS_LEVEL_ASPM BIT(31) /*LPS with ASPM */
1887 #define RT_IN_PS_LEVEL(ppsc, _ps_flg) \
1888 ((ppsc->cur_ps_level & _ps_flg) ? true : false)
1889 #define RT_CLEAR_PS_LEVEL(ppsc, _ps_flg) \
1890 (ppsc->cur_ps_level &= (~(_ps_flg)))
1891 #define RT_SET_PS_LEVEL(ppsc, _ps_flg) \
1892 (ppsc->cur_ps_level |= _ps_flg)
1894 #define container_of_dwork_rtl(x, y, z) \
1895 container_of(container_of(x, struct delayed_work, work), y, z)
1897 #define FILL_OCTET_STRING(_os, _octet, _len) \
1898 (_os).octet = (u8 *)(_octet); \
1899 (_os).length = (_len);
1901 #define CP_MACADDR(des, src) \
1902 ((des)[0] = (src)[0], (des)[1] = (src)[1],\
1903 (des)[2] = (src)[2], (des)[3] = (src)[3],\
1904 (des)[4] = (src)[4], (des)[5] = (src)[5])
1906 static inline u8 rtl_read_byte(struct rtl_priv *rtlpriv, u32 addr)
1908 return rtlpriv->io.read8_sync(rtlpriv, addr);
1911 static inline u16 rtl_read_word(struct rtl_priv *rtlpriv, u32 addr)
1913 return rtlpriv->io.read16_sync(rtlpriv, addr);
1916 static inline u32 rtl_read_dword(struct rtl_priv *rtlpriv, u32 addr)
1918 return rtlpriv->io.read32_sync(rtlpriv, addr);
1921 static inline void rtl_write_byte(struct rtl_priv *rtlpriv, u32 addr, u8 val8)
1923 rtlpriv->io.write8_async(rtlpriv, addr, val8);
1925 if (rtlpriv->cfg->write_readback)
1926 rtlpriv->io.read8_sync(rtlpriv, addr);
1929 static inline void rtl_write_word(struct rtl_priv *rtlpriv, u32 addr, u16 val16)
1931 rtlpriv->io.write16_async(rtlpriv, addr, val16);
1933 if (rtlpriv->cfg->write_readback)
1934 rtlpriv->io.read16_sync(rtlpriv, addr);
1937 static inline void rtl_write_dword(struct rtl_priv *rtlpriv,
1938 u32 addr, u32 val32)
1940 rtlpriv->io.write32_async(rtlpriv, addr, val32);
1942 if (rtlpriv->cfg->write_readback)
1943 rtlpriv->io.read32_sync(rtlpriv, addr);
1946 static inline u32 rtl_get_bbreg(struct ieee80211_hw *hw,
1947 u32 regaddr, u32 bitmask)
1949 return ((struct rtl_priv *)(hw)->priv)->cfg->ops->get_bbreg(hw,
1954 static inline void rtl_set_bbreg(struct ieee80211_hw *hw, u32 regaddr,
1955 u32 bitmask, u32 data)
1957 ((struct rtl_priv *)(hw)->priv)->cfg->ops->set_bbreg(hw,
1963 static inline u32 rtl_get_rfreg(struct ieee80211_hw *hw,
1964 enum radio_path rfpath, u32 regaddr,
1967 return ((struct rtl_priv *)(hw)->priv)->cfg->ops->get_rfreg(hw,
1973 static inline void rtl_set_rfreg(struct ieee80211_hw *hw,
1974 enum radio_path rfpath, u32 regaddr,
1975 u32 bitmask, u32 data)
1977 ((struct rtl_priv *)(hw)->priv)->cfg->ops->set_rfreg(hw,
1982 static inline bool is_hal_stop(struct rtl_hal *rtlhal)
1984 return (_HAL_STATE_STOP == rtlhal->state);
1987 static inline void set_hal_start(struct rtl_hal *rtlhal)
1989 rtlhal->state = _HAL_STATE_START;
1992 static inline void set_hal_stop(struct rtl_hal *rtlhal)
1994 rtlhal->state = _HAL_STATE_STOP;
1997 static inline u8 get_rf_type(struct rtl_phy *rtlphy)
1999 return rtlphy->rf_type;
2002 static inline struct ieee80211_hdr *rtl_get_hdr(struct sk_buff *skb)
2004 return (struct ieee80211_hdr *)(skb->data);
2007 static inline __le16 rtl_get_fc(struct sk_buff *skb)
2009 return rtl_get_hdr(skb)->frame_control;
2012 static inline u16 rtl_get_tid_h(struct ieee80211_hdr *hdr)
2014 return (ieee80211_get_qos_ctl(hdr))[0] & IEEE80211_QOS_CTL_TID_MASK;
2017 static inline u16 rtl_get_tid(struct sk_buff *skb)
2019 return rtl_get_tid_h(rtl_get_hdr(skb));
2022 static inline struct ieee80211_sta *get_sta(struct ieee80211_hw *hw,
2023 struct ieee80211_vif *vif,
2026 return ieee80211_find_sta(vif, bssid);