drivers/net/wireless/ti/wl12xx/main.c

   1 /*
   2  * This file is part of wl1271
   3  *
   4  * Copyright (C) 2008-2010 Nokia Corporation
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License
   8  * version 2 as published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope that it will be useful, but
  11  * WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  13  * General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
  18  * 02110-1301 USA
  19  *
  20  */
  21
  22 #include <linux/module.h>
  23 #include <linux/platform_device.h>
  24
  25 #include <linux/err.h>
  26
  27 #include <linux/wl12xx.h>
  28
  29 #include "../wlcore/wlcore.h"
  30 #include "../wlcore/debug.h"
  31 #include "../wlcore/io.h"
  32 #include "../wlcore/acx.h"
  33 #include "../wlcore/tx.h"
  34 #include "../wlcore/rx.h"
  35 #include "../wlcore/boot.h"
  36
  37 #include "wl12xx.h"
  38 #include "reg.h"
  39 #include "cmd.h"
  40 #include "acx.h"
  41 #include "scan.h"
  42 #include "debugfs.h"
  43
  44 static char *fref_param;
  45 static char *tcxo_param;
  46
  47 static struct wlcore_conf wl12xx_conf = {
  48         .sg = {
  49                 .params = {
  50                         [CONF_SG_ACL_BT_MASTER_MIN_BR] = 10,
  51                         [CONF_SG_ACL_BT_MASTER_MAX_BR] = 180,
  52                         [CONF_SG_ACL_BT_SLAVE_MIN_BR] = 10,
  53                         [CONF_SG_ACL_BT_SLAVE_MAX_BR] = 180,
  54                         [CONF_SG_ACL_BT_MASTER_MIN_EDR] = 10,
  55                         [CONF_SG_ACL_BT_MASTER_MAX_EDR] = 80,
  56                         [CONF_SG_ACL_BT_SLAVE_MIN_EDR] = 10,
  57                         [CONF_SG_ACL_BT_SLAVE_MAX_EDR] = 80,
  58                         [CONF_SG_ACL_WLAN_PS_MASTER_BR] = 8,
  59                         [CONF_SG_ACL_WLAN_PS_SLAVE_BR] = 8,
  60                         [CONF_SG_ACL_WLAN_PS_MASTER_EDR] = 20,
  61                         [CONF_SG_ACL_WLAN_PS_SLAVE_EDR] = 20,
  62                         [CONF_SG_ACL_WLAN_ACTIVE_MASTER_MIN_BR] = 20,
  63                         [CONF_SG_ACL_WLAN_ACTIVE_MASTER_MAX_BR] = 35,
  64                         [CONF_SG_ACL_WLAN_ACTIVE_SLAVE_MIN_BR] = 16,
  65                         [CONF_SG_ACL_WLAN_ACTIVE_SLAVE_MAX_BR] = 35,
  66                         [CONF_SG_ACL_WLAN_ACTIVE_MASTER_MIN_EDR] = 32,
  67                         [CONF_SG_ACL_WLAN_ACTIVE_MASTER_MAX_EDR] = 50,
  68                         [CONF_SG_ACL_WLAN_ACTIVE_SLAVE_MIN_EDR] = 28,
  69                         [CONF_SG_ACL_WLAN_ACTIVE_SLAVE_MAX_EDR] = 50,
  70                         [CONF_SG_ACL_ACTIVE_SCAN_WLAN_BR] = 10,
  71                         [CONF_SG_ACL_ACTIVE_SCAN_WLAN_EDR] = 20,
  72                         [CONF_SG_ACL_PASSIVE_SCAN_BT_BR] = 75,
  73                         [CONF_SG_ACL_PASSIVE_SCAN_WLAN_BR] = 15,
  74                         [CONF_SG_ACL_PASSIVE_SCAN_BT_EDR] = 27,
  75                         [CONF_SG_ACL_PASSIVE_SCAN_WLAN_EDR] = 17,
  76                         /* active scan params */
  77                         [CONF_SG_AUTO_SCAN_PROBE_REQ] = 170,
  78                         [CONF_SG_ACTIVE_SCAN_DURATION_FACTOR_HV3] = 50,
  79                         [CONF_SG_ACTIVE_SCAN_DURATION_FACTOR_A2DP] = 100,
  80                         /* passive scan params */
  81                         [CONF_SG_PASSIVE_SCAN_DURATION_FACTOR_A2DP_BR] = 800,
  82                         [CONF_SG_PASSIVE_SCAN_DURATION_FACTOR_A2DP_EDR] = 200,
  83                         [CONF_SG_PASSIVE_SCAN_DURATION_FACTOR_HV3] = 200,
  84                         /* passive scan in dual antenna params */
  85                         [CONF_SG_CONSECUTIVE_HV3_IN_PASSIVE_SCAN] = 0,
  86                         [CONF_SG_BCN_HV3_COLLISION_THRESH_IN_PASSIVE_SCAN] = 0,
  87                         [CONF_SG_TX_RX_PROTECTION_BWIDTH_IN_PASSIVE_SCAN] = 0,
  88                         /* general params */
  89                         [CONF_SG_STA_FORCE_PS_IN_BT_SCO] = 1,
  90                         [CONF_SG_ANTENNA_CONFIGURATION] = 0,
  91                         [CONF_SG_BEACON_MISS_PERCENT] = 60,
  92                         [CONF_SG_DHCP_TIME] = 5000,
  93                         [CONF_SG_RXT] = 1200,
  94                         [CONF_SG_TXT] = 1000,
  95                         [CONF_SG_ADAPTIVE_RXT_TXT] = 1,
  96                         [CONF_SG_GENERAL_USAGE_BIT_MAP] = 3,
  97                         [CONF_SG_HV3_MAX_SERVED] = 6,
  98                         [CONF_SG_PS_POLL_TIMEOUT] = 10,
  99                         [CONF_SG_UPSD_TIMEOUT] = 10,
 100                         [CONF_SG_CONSECUTIVE_CTS_THRESHOLD] = 2,
 101                         [CONF_SG_STA_RX_WINDOW_AFTER_DTIM] = 5,
 102                         [CONF_SG_STA_CONNECTION_PROTECTION_TIME] = 30,
 103                         /* AP params */
 104                         [CONF_AP_BEACON_MISS_TX] = 3,
 105                         [CONF_AP_RX_WINDOW_AFTER_BEACON] = 10,
 106                         [CONF_AP_BEACON_WINDOW_INTERVAL] = 2,
 107                         [CONF_AP_CONNECTION_PROTECTION_TIME] = 0,
 108                         [CONF_AP_BT_ACL_VAL_BT_SERVE_TIME] = 25,
 109                         [CONF_AP_BT_ACL_VAL_WL_SERVE_TIME] = 25,
 110                         /* CTS Diluting params */
 111                         [CONF_SG_CTS_DILUTED_BAD_RX_PACKETS_TH] = 0,
 112                         [CONF_SG_CTS_CHOP_IN_DUAL_ANT_SCO_MASTER] = 0,
 113                 },
 114                 .state = CONF_SG_PROTECTIVE,
 115         },
 116         .rx = {
 117                 .rx_msdu_life_time           = 512000,
 118                 .packet_detection_threshold  = 0,
 119                 .ps_poll_timeout             = 15,
 120                 .upsd_timeout                = 15,
 121                 .rts_threshold               = IEEE80211_MAX_RTS_THRESHOLD,
 122                 .rx_cca_threshold            = 0,
 123                 .irq_blk_threshold           = 0xFFFF,
 124                 .irq_pkt_threshold           = 0,
 125                 .irq_timeout                 = 600,
 126                 .queue_type                  = CONF_RX_QUEUE_TYPE_LOW_PRIORITY,
 127         },
 128         .tx = {
 129                 .tx_energy_detection         = 0,
 130                 .sta_rc_conf                 = {
 131                         .enabled_rates       = 0,
 132                         .short_retry_limit   = 10,
 133                         .long_retry_limit    = 10,
 134                         .aflags              = 0,
 135                 },
 136                 .ac_conf_count               = 4,
 137                 .ac_conf                     = {
 138                         [CONF_TX_AC_BE] = {
 139                                 .ac          = CONF_TX_AC_BE,
 140                                 .cw_min      = 15,
 141                                 .cw_max      = 63,
 142                                 .aifsn       = 3,
 143                                 .tx_op_limit = 0,
 144                         },
 145                         [CONF_TX_AC_BK] = {
 146                                 .ac          = CONF_TX_AC_BK,
 147                                 .cw_min      = 15,
 148                                 .cw_max      = 63,
 149                                 .aifsn       = 7,
 150                                 .tx_op_limit = 0,
 151                         },
 152                         [CONF_TX_AC_VI] = {
 153                                 .ac          = CONF_TX_AC_VI,
 154                                 .cw_min      = 15,
 155                                 .cw_max      = 63,
 156                                 .aifsn       = CONF_TX_AIFS_PIFS,
 157                                 .tx_op_limit = 3008,
 158                         },
 159                         [CONF_TX_AC_VO] = {
 160                                 .ac          = CONF_TX_AC_VO,
 161                                 .cw_min      = 15,
 162                                 .cw_max      = 63,
 163                                 .aifsn       = CONF_TX_AIFS_PIFS,
 164                                 .tx_op_limit = 1504,
 165                         },
 166                 },
 167                 .max_tx_retries = 100,
 168                 .ap_aging_period = 300,
 169                 .tid_conf_count = 4,
 170                 .tid_conf = {
 171                         [CONF_TX_AC_BE] = {
 172                                 .queue_id    = CONF_TX_AC_BE,
 173                                 .channel_type = CONF_CHANNEL_TYPE_EDCF,
 174                                 .tsid        = CONF_TX_AC_BE,
 175                                 .ps_scheme   = CONF_PS_SCHEME_LEGACY,
 176                                 .ack_policy  = CONF_ACK_POLICY_LEGACY,
 177                                 .apsd_conf   = {0, 0},
 178                         },
 179                         [CONF_TX_AC_BK] = {
 180                                 .queue_id    = CONF_TX_AC_BK,
 181                                 .channel_type = CONF_CHANNEL_TYPE_EDCF,
 182                                 .tsid        = CONF_TX_AC_BK,
 183                                 .ps_scheme   = CONF_PS_SCHEME_LEGACY,
 184                                 .ack_policy  = CONF_ACK_POLICY_LEGACY,
 185                                 .apsd_conf   = {0, 0},
 186                         },
 187                         [CONF_TX_AC_VI] = {
 188                                 .queue_id    = CONF_TX_AC_VI,
 189                                 .channel_type = CONF_CHANNEL_TYPE_EDCF,
 190                                 .tsid        = CONF_TX_AC_VI,
 191                                 .ps_scheme   = CONF_PS_SCHEME_LEGACY,
 192                                 .ack_policy  = CONF_ACK_POLICY_LEGACY,
 193                                 .apsd_conf   = {0, 0},
 194                         },
 195                         [CONF_TX_AC_VO] = {
 196                                 .queue_id    = CONF_TX_AC_VO,
 197                                 .channel_type = CONF_CHANNEL_TYPE_EDCF,
 198                                 .tsid        = CONF_TX_AC_VO,
 199                                 .ps_scheme   = CONF_PS_SCHEME_LEGACY,
 200                                 .ack_policy  = CONF_ACK_POLICY_LEGACY,
 201                                 .apsd_conf   = {0, 0},
 202                         },
 203                 },
 204                 .frag_threshold              = IEEE80211_MAX_FRAG_THRESHOLD,
 205                 .tx_compl_timeout            = 700,
 206                 .tx_compl_threshold          = 4,
 207                 .basic_rate                  = CONF_HW_BIT_RATE_1MBPS,
 208                 .basic_rate_5                = CONF_HW_BIT_RATE_6MBPS,
 209                 .tmpl_short_retry_limit      = 10,
 210                 .tmpl_long_retry_limit       = 10,
 211                 .tx_watchdog_timeout         = 5000,
 212         },
 213         .conn = {
 214                 .wake_up_event               = CONF_WAKE_UP_EVENT_DTIM,
 215                 .listen_interval             = 1,
 216                 .suspend_wake_up_event       = CONF_WAKE_UP_EVENT_N_DTIM,
 217                 .suspend_listen_interval     = 3,
 218                 .bcn_filt_mode               = CONF_BCN_FILT_MODE_ENABLED,
 219                 .bcn_filt_ie_count           = 3,
 220                 .bcn_filt_ie = {
 221                         [0] = {
 222                                 .ie          = WLAN_EID_CHANNEL_SWITCH,
 223                                 .rule        = CONF_BCN_RULE_PASS_ON_APPEARANCE,
 224                         },
 225                         [1] = {
 226                                 .ie          = WLAN_EID_HT_OPERATION,
 227                                 .rule        = CONF_BCN_RULE_PASS_ON_CHANGE,
 228                         },
 229                         [2] = {
 230                                 .ie          = WLAN_EID_ERP_INFO,
 231                                 .rule        = CONF_BCN_RULE_PASS_ON_CHANGE,
 232                         },
 233                 },
 234                 .synch_fail_thold            = 12,
 235                 .bss_lose_timeout            = 400,
 236                 .beacon_rx_timeout           = 10000,
 237                 .broadcast_timeout           = 20000,
 238                 .rx_broadcast_in_ps          = 1,
 239                 .ps_poll_threshold           = 10,
 240                 .bet_enable                  = CONF_BET_MODE_ENABLE,
 241                 .bet_max_consecutive         = 50,
 242                 .psm_entry_retries           = 8,
 243                 .psm_exit_retries            = 16,
 244                 .psm_entry_nullfunc_retries  = 3,
 245                 .dynamic_ps_timeout          = 1500,
 246                 .forced_ps                   = false,
 247                 .keep_alive_interval         = 55000,
 248                 .max_listen_interval         = 20,
 249                 .sta_sleep_auth              = WL1271_PSM_ILLEGAL,
 250         },
 251         .itrim = {
 252                 .enable = false,
 253                 .timeout = 50000,
 254         },
 255         .pm_config = {
 256                 .host_clk_settling_time = 5000,
 257                 .host_fast_wakeup_support = CONF_FAST_WAKEUP_DISABLE,
 258         },
 259         .roam_trigger = {
 260                 .trigger_pacing               = 1,
 261                 .avg_weight_rssi_beacon       = 20,
 262                 .avg_weight_rssi_data         = 10,
 263                 .avg_weight_snr_beacon        = 20,
 264                 .avg_weight_snr_data          = 10,
 265         },
 266         .scan = {
 267                 .min_dwell_time_active        = 7500,
 268                 .max_dwell_time_active        = 30000,
 269                 .min_dwell_time_passive       = 100000,
 270                 .max_dwell_time_passive       = 100000,
 271                 .num_probe_reqs               = 2,
 272                 .split_scan_timeout           = 50000,
 273         },
 274         .sched_scan = {
 275                 /*
 276                  * Values are in TU/1000 but since sched scan FW command
 277                  * params are in TUs rounding up may occur.
 278                  */
 279                 .base_dwell_time                = 7500,
 280                 .max_dwell_time_delta           = 22500,
 281                 /* based on 250bits per probe @1Mbps */
 282                 .dwell_time_delta_per_probe     = 2000,
 283                 /* based on 250bits per probe @6Mbps (plus a bit more) */
 284                 .dwell_time_delta_per_probe_5   = 350,
 285                 .dwell_time_passive             = 100000,
 286                 .dwell_time_dfs                 = 150000,
 287                 .num_probe_reqs                 = 2,
 288                 .rssi_threshold                 = -90,
 289                 .snr_threshold                  = 0,
 290         },
 291         .ht = {
 292                 .rx_ba_win_size = 8,
 293                 .tx_ba_win_size = 64,
 294                 .inactivity_timeout = 10000,
 295                 .tx_ba_tid_bitmap = CONF_TX_BA_ENABLED_TID_BITMAP,
 296         },
 297         /*
 298          * Memory config for wl127x chips is given in the
 299          * wl12xx_default_priv_conf struct. The below configuration is
 300          * for wl128x chips.
 301          */
 302         .mem = {
 303                 .num_stations                 = 1,
 304                 .ssid_profiles                = 1,
 305                 .rx_block_num                 = 40,
 306                 .tx_min_block_num             = 40,
 307                 .dynamic_memory               = 1,
 308                 .min_req_tx_blocks            = 45,
 309                 .min_req_rx_blocks            = 22,
 310                 .tx_min                       = 27,
 311         },
 312         .fm_coex = {
 313                 .enable                       = true,
 314                 .swallow_period               = 5,
 315                 .n_divider_fref_set_1         = 0xff,       /* default */
 316                 .n_divider_fref_set_2         = 12,
 317                 .m_divider_fref_set_1         = 0xffff,
 318                 .m_divider_fref_set_2         = 148,        /* default */
 319                 .coex_pll_stabilization_time  = 0xffffffff, /* default */
 320                 .ldo_stabilization_time       = 0xffff,     /* default */
 321                 .fm_disturbed_band_margin     = 0xff,       /* default */
 322                 .swallow_clk_diff             = 0xff,       /* default */
 323         },
 324         .rx_streaming = {
 325                 .duration                      = 150,
 326                 .queues                        = 0x1,
 327                 .interval                      = 20,
 328                 .always                        = 0,
 329         },
 330         .fwlog = {
 331                 .mode                         = WL12XX_FWLOG_ON_DEMAND,
 332                 .mem_blocks                   = 2,
 333                 .severity                     = 0,
 334                 .timestamp                    = WL12XX_FWLOG_TIMESTAMP_DISABLED,
 335                 .output                       = WL12XX_FWLOG_OUTPUT_HOST,
 336                 .threshold                    = 0,
 337         },
 338         .rate = {
 339                 .rate_retry_score = 32000,
 340                 .per_add = 8192,
 341                 .per_th1 = 2048,
 342                 .per_th2 = 4096,
 343                 .max_per = 8100,
 344                 .inverse_curiosity_factor = 5,
 345                 .tx_fail_low_th = 4,
 346                 .tx_fail_high_th = 10,
 347                 .per_alpha_shift = 4,
 348                 .per_add_shift = 13,
 349                 .per_beta1_shift = 10,
 350                 .per_beta2_shift = 8,
 351                 .rate_check_up = 2,
 352                 .rate_check_down = 12,
 353                 .rate_retry_policy = {
 354                         0x00, 0x00, 0x00, 0x00, 0x00,
 355                         0x00, 0x00, 0x00, 0x00, 0x00,
 356                         0x00, 0x00, 0x00,
 357                 },
 358         },
 359         .hangover = {
 360                 .recover_time               = 0,
 361                 .hangover_period            = 20,
 362                 .dynamic_mode               = 1,
 363                 .early_termination_mode     = 1,
 364                 .max_period                 = 20,
 365                 .min_period                 = 1,
 366                 .increase_delta             = 1,
 367                 .decrease_delta             = 2,
 368                 .quiet_time                 = 4,
 369                 .increase_time              = 1,
 370                 .window_size                = 16,
 371         },
 372 };
 373
 374 static struct wl12xx_priv_conf wl12xx_default_priv_conf = {
 375         .rf = {
 376                 .tx_per_channel_power_compensation_2 = {
 377                         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 378                 },
 379                 .tx_per_channel_power_compensation_5 = {
 380                         0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 381                         0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 382                         0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 383                 },
 384         },
 385         .mem_wl127x = {
 386                 .num_stations                 = 1,
 387                 .ssid_profiles                = 1,
 388                 .rx_block_num                 = 70,
 389                 .tx_min_block_num             = 40,
 390                 .dynamic_memory               = 1,
 391                 .min_req_tx_blocks            = 100,
 392                 .min_req_rx_blocks            = 22,
 393                 .tx_min                       = 27,
 394         },
 395
 396 };
 397
 398 #define WL12XX_TX_HW_BLOCK_SPARE_DEFAULT        1
 399 #define WL12XX_TX_HW_BLOCK_GEM_SPARE            2
 400 #define WL12XX_TX_HW_BLOCK_SIZE                 252
 401
 402 static const u8 wl12xx_rate_to_idx_2ghz[] = {
 403         /* MCS rates are used only with 11n */
 404         7,                             /* WL12XX_CONF_HW_RXTX_RATE_MCS7_SGI */
 405         7,                             /* WL12XX_CONF_HW_RXTX_RATE_MCS7 */
 406         6,                             /* WL12XX_CONF_HW_RXTX_RATE_MCS6 */
 407         5,                             /* WL12XX_CONF_HW_RXTX_RATE_MCS5 */
 408         4,                             /* WL12XX_CONF_HW_RXTX_RATE_MCS4 */
 409         3,                             /* WL12XX_CONF_HW_RXTX_RATE_MCS3 */
 410         2,                             /* WL12XX_CONF_HW_RXTX_RATE_MCS2 */
 411         1,                             /* WL12XX_CONF_HW_RXTX_RATE_MCS1 */
 412         0,                             /* WL12XX_CONF_HW_RXTX_RATE_MCS0 */
 413
 414         11,                            /* WL12XX_CONF_HW_RXTX_RATE_54   */
 415         10,                            /* WL12XX_CONF_HW_RXTX_RATE_48   */
 416         9,                             /* WL12XX_CONF_HW_RXTX_RATE_36   */
 417         8,                             /* WL12XX_CONF_HW_RXTX_RATE_24   */
 418
 419         /* TI-specific rate */
 420         CONF_HW_RXTX_RATE_UNSUPPORTED, /* WL12XX_CONF_HW_RXTX_RATE_22   */
 421
 422         7,                             /* WL12XX_CONF_HW_RXTX_RATE_18   */
 423         6,                             /* WL12XX_CONF_HW_RXTX_RATE_12   */
 424         3,                             /* WL12XX_CONF_HW_RXTX_RATE_11   */
 425         5,                             /* WL12XX_CONF_HW_RXTX_RATE_9    */
 426         4,                             /* WL12XX_CONF_HW_RXTX_RATE_6    */
 427         2,                             /* WL12XX_CONF_HW_RXTX_RATE_5_5  */
 428         1,                             /* WL12XX_CONF_HW_RXTX_RATE_2    */
 429         0                              /* WL12XX_CONF_HW_RXTX_RATE_1    */
 430 };
 431
 432 static const u8 wl12xx_rate_to_idx_5ghz[] = {
 433         /* MCS rates are used only with 11n */
 434         7,                             /* WL12XX_CONF_HW_RXTX_RATE_MCS7_SGI */
 435         7,                             /* WL12XX_CONF_HW_RXTX_RATE_MCS7 */
 436         6,                             /* WL12XX_CONF_HW_RXTX_RATE_MCS6 */
 437         5,                             /* WL12XX_CONF_HW_RXTX_RATE_MCS5 */
 438         4,                             /* WL12XX_CONF_HW_RXTX_RATE_MCS4 */
 439         3,                             /* WL12XX_CONF_HW_RXTX_RATE_MCS3 */
 440         2,                             /* WL12XX_CONF_HW_RXTX_RATE_MCS2 */
 441         1,                             /* WL12XX_CONF_HW_RXTX_RATE_MCS1 */
 442         0,                             /* WL12XX_CONF_HW_RXTX_RATE_MCS0 */
 443
 444         7,                             /* WL12XX_CONF_HW_RXTX_RATE_54   */
 445         6,                             /* WL12XX_CONF_HW_RXTX_RATE_48   */
 446         5,                             /* WL12XX_CONF_HW_RXTX_RATE_36   */
 447         4,                             /* WL12XX_CONF_HW_RXTX_RATE_24   */
 448
 449         /* TI-specific rate */
 450         CONF_HW_RXTX_RATE_UNSUPPORTED, /* WL12XX_CONF_HW_RXTX_RATE_22   */
 451
 452         3,                             /* WL12XX_CONF_HW_RXTX_RATE_18   */
 453         2,                             /* WL12XX_CONF_HW_RXTX_RATE_12   */
 454         CONF_HW_RXTX_RATE_UNSUPPORTED, /* WL12XX_CONF_HW_RXTX_RATE_11   */
 455         1,                             /* WL12XX_CONF_HW_RXTX_RATE_9    */
 456         0,                             /* WL12XX_CONF_HW_RXTX_RATE_6    */
 457         CONF_HW_RXTX_RATE_UNSUPPORTED, /* WL12XX_CONF_HW_RXTX_RATE_5_5  */
 458         CONF_HW_RXTX_RATE_UNSUPPORTED, /* WL12XX_CONF_HW_RXTX_RATE_2    */
 459         CONF_HW_RXTX_RATE_UNSUPPORTED  /* WL12XX_CONF_HW_RXTX_RATE_1    */
 460 };
 461
 462 static const u8 *wl12xx_band_rate_to_idx[] = {
 463         [IEEE80211_BAND_2GHZ] = wl12xx_rate_to_idx_2ghz,
 464         [IEEE80211_BAND_5GHZ] = wl12xx_rate_to_idx_5ghz
 465 };
 466
 467 enum wl12xx_hw_rates {
 468         WL12XX_CONF_HW_RXTX_RATE_MCS7_SGI = 0,
 469         WL12XX_CONF_HW_RXTX_RATE_MCS7,
 470         WL12XX_CONF_HW_RXTX_RATE_MCS6,
 471         WL12XX_CONF_HW_RXTX_RATE_MCS5,
 472         WL12XX_CONF_HW_RXTX_RATE_MCS4,
 473         WL12XX_CONF_HW_RXTX_RATE_MCS3,
 474         WL12XX_CONF_HW_RXTX_RATE_MCS2,
 475         WL12XX_CONF_HW_RXTX_RATE_MCS1,
 476         WL12XX_CONF_HW_RXTX_RATE_MCS0,
 477         WL12XX_CONF_HW_RXTX_RATE_54,
 478         WL12XX_CONF_HW_RXTX_RATE_48,
 479         WL12XX_CONF_HW_RXTX_RATE_36,
 480         WL12XX_CONF_HW_RXTX_RATE_24,
 481         WL12XX_CONF_HW_RXTX_RATE_22,
 482         WL12XX_CONF_HW_RXTX_RATE_18,
 483         WL12XX_CONF_HW_RXTX_RATE_12,
 484         WL12XX_CONF_HW_RXTX_RATE_11,
 485         WL12XX_CONF_HW_RXTX_RATE_9,
 486         WL12XX_CONF_HW_RXTX_RATE_6,
 487         WL12XX_CONF_HW_RXTX_RATE_5_5,
 488         WL12XX_CONF_HW_RXTX_RATE_2,
 489         WL12XX_CONF_HW_RXTX_RATE_1,
 490         WL12XX_CONF_HW_RXTX_RATE_MAX,
 491 };
 492
 493 static struct wlcore_partition_set wl12xx_ptable[PART_TABLE_LEN] = {
 494         [PART_DOWN] = {
 495                 .mem = {
 496                         .start = 0x00000000,
 497                         .size  = 0x000177c0
 498                 },
 499                 .reg = {
 500                         .start = REGISTERS_BASE,
 501                         .size  = 0x00008800
 502                 },
 503                 .mem2 = {
 504                         .start = 0x00000000,
 505                         .size  = 0x00000000
 506                 },
 507                 .mem3 = {
 508                         .start = 0x00000000,
 509                         .size  = 0x00000000
 510                 },
 511         },
 512
 513         [PART_BOOT] = { /* in wl12xx we can use a mix of work and down
 514                          * partition here */
 515                 .mem = {
 516                         .start = 0x00040000,
 517                         .size  = 0x00014fc0
 518                 },
 519                 .reg = {
 520                         .start = REGISTERS_BASE,
 521                         .size  = 0x00008800
 522                 },
 523                 .mem2 = {
 524                         .start = 0x00000000,
 525                         .size  = 0x00000000
 526                 },
 527                 .mem3 = {
 528                         .start = 0x00000000,
 529                         .size  = 0x00000000
 530                 },
 531         },
 532
 533         [PART_WORK] = {
 534                 .mem = {
 535                         .start = 0x00040000,
 536                         .size  = 0x00014fc0
 537                 },
 538                 .reg = {
 539                         .start = REGISTERS_BASE,
 540                         .size  = 0x0000a000
 541                 },
 542                 .mem2 = {
 543                         .start = 0x003004f8,
 544                         .size  = 0x00000004
 545                 },
 546                 .mem3 = {
 547                         .start = 0x00040404,
 548                         .size  = 0x00000000
 549                 },
 550         },
 551
 552         [PART_DRPW] = {
 553                 .mem = {
 554                         .start = 0x00040000,
 555                         .size  = 0x00014fc0
 556                 },
 557                 .reg = {
 558                         .start = DRPW_BASE,
 559                         .size  = 0x00006000
 560                 },
 561                 .mem2 = {
 562                         .start = 0x00000000,
 563                         .size  = 0x00000000
 564                 },
 565                 .mem3 = {
 566                         .start = 0x00000000,
 567                         .size  = 0x00000000
 568                 }
 569         }
 570 };
 571
 572 static const int wl12xx_rtable[REG_TABLE_LEN] = {
 573         [REG_ECPU_CONTROL]              = WL12XX_REG_ECPU_CONTROL,
 574         [REG_INTERRUPT_NO_CLEAR]        = WL12XX_REG_INTERRUPT_NO_CLEAR,
 575         [REG_INTERRUPT_ACK]             = WL12XX_REG_INTERRUPT_ACK,
 576         [REG_COMMAND_MAILBOX_PTR]       = WL12XX_REG_COMMAND_MAILBOX_PTR,
 577         [REG_EVENT_MAILBOX_PTR]         = WL12XX_REG_EVENT_MAILBOX_PTR,
 578         [REG_INTERRUPT_TRIG]            = WL12XX_REG_INTERRUPT_TRIG,
 579         [REG_INTERRUPT_MASK]            = WL12XX_REG_INTERRUPT_MASK,
 580         [REG_PC_ON_RECOVERY]            = WL12XX_SCR_PAD4,
 581         [REG_CHIP_ID_B]                 = WL12XX_CHIP_ID_B,
 582         [REG_CMD_MBOX_ADDRESS]          = WL12XX_CMD_MBOX_ADDRESS,
 583
 584         /* data access memory addresses, used with partition translation */
 585         [REG_SLV_MEM_DATA]              = WL1271_SLV_MEM_DATA,
 586         [REG_SLV_REG_DATA]              = WL1271_SLV_REG_DATA,
 587
 588         /* raw data access memory addresses */
 589         [REG_RAW_FW_STATUS_ADDR]        = FW_STATUS_ADDR,
 590 };
 591
 592 /* TODO: maybe move to a new header file? */
 593 #define WL127X_FW_NAME_MULTI    "ti-connectivity/wl127x-fw-5-mr.bin"
 594 #define WL127X_FW_NAME_SINGLE   "ti-connectivity/wl127x-fw-5-sr.bin"
 595 #define WL127X_PLT_FW_NAME      "ti-connectivity/wl127x-fw-5-plt.bin"
 596
 597 #define WL128X_FW_NAME_MULTI    "ti-connectivity/wl128x-fw-5-mr.bin"
 598 #define WL128X_FW_NAME_SINGLE   "ti-connectivity/wl128x-fw-5-sr.bin"
 599 #define WL128X_PLT_FW_NAME      "ti-connectivity/wl128x-fw-5-plt.bin"
 600
 601 static int wl127x_prepare_read(struct wl1271 *wl, u32 rx_desc, u32 len)
 602 {
 603         int ret;
 604
 605         if (wl->chip.id != CHIP_ID_1283_PG20) {
 606                 struct wl1271_acx_mem_map *wl_mem_map = wl->target_mem_map;
 607                 struct wl127x_rx_mem_pool_addr rx_mem_addr;
 608
 609                 /*
 610                  * Choose the block we want to read
 611                  * For aggregated packets, only the first memory block
 612                  * should be retrieved. The FW takes care of the rest.
 613                  */
 614                 u32 mem_block = rx_desc & RX_MEM_BLOCK_MASK;
 615
 616                 rx_mem_addr.addr = (mem_block << 8) +
 617                         le32_to_cpu(wl_mem_map->packet_memory_pool_start);
 618
 619                 rx_mem_addr.addr_extra = rx_mem_addr.addr + 4;
 620
 621                 ret = wlcore_write(wl, WL1271_SLV_REG_DATA, &rx_mem_addr,
 622                                    sizeof(rx_mem_addr), false);
 623                 if (ret < 0)
 624                         return ret;
 625         }
 626
 627         return 0;
 628 }
 629
 630 static int wl12xx_identify_chip(struct wl1271 *wl)
 631 {
 632         int ret = 0;
 633
 634         switch (wl->chip.id) {
 635         case CHIP_ID_1271_PG10:
 636                 wl1271_warning("chip id 0x%x (1271 PG10) support is obsolete",
 637                                wl->chip.id);
 638
 639                 wl->quirks |= WLCORE_QUIRK_LEGACY_NVS |
 640                               WLCORE_QUIRK_DUAL_PROBE_TMPL |
 641                               WLCORE_QUIRK_TKIP_HEADER_SPACE |
 642                               WLCORE_QUIRK_START_STA_FAILS;
 643                 wl->sr_fw_name = WL127X_FW_NAME_SINGLE;
 644                 wl->mr_fw_name = WL127X_FW_NAME_MULTI;
 645                 memcpy(&wl->conf.mem, &wl12xx_default_priv_conf.mem_wl127x,
 646                        sizeof(wl->conf.mem));
 647
 648                 /* read data preparation is only needed by wl127x */
 649                 wl->ops->prepare_read = wl127x_prepare_read;
 650
 651                 wlcore_set_min_fw_ver(wl, WL127X_CHIP_VER, WL127X_IFTYPE_VER,
 652                                       WL127X_MAJOR_VER, WL127X_SUBTYPE_VER,
 653                                       WL127X_MINOR_VER);
 654                 break;
 655
 656         case CHIP_ID_1271_PG20:
 657                 wl1271_debug(DEBUG_BOOT, "chip id 0x%x (1271 PG20)",
 658                              wl->chip.id);
 659
 660                 wl->quirks |= WLCORE_QUIRK_LEGACY_NVS |
 661                               WLCORE_QUIRK_DUAL_PROBE_TMPL |
 662                               WLCORE_QUIRK_TKIP_HEADER_SPACE |
 663                               WLCORE_QUIRK_START_STA_FAILS;
 664                 wl->plt_fw_name = WL127X_PLT_FW_NAME;
 665                 wl->sr_fw_name = WL127X_FW_NAME_SINGLE;
 666                 wl->mr_fw_name = WL127X_FW_NAME_MULTI;
 667                 memcpy(&wl->conf.mem, &wl12xx_default_priv_conf.mem_wl127x,
 668                        sizeof(wl->conf.mem));
 669
 670                 /* read data preparation is only needed by wl127x */
 671                 wl->ops->prepare_read = wl127x_prepare_read;
 672
 673                 wlcore_set_min_fw_ver(wl, WL127X_CHIP_VER, WL127X_IFTYPE_VER,
 674                                       WL127X_MAJOR_VER, WL127X_SUBTYPE_VER,
 675                                       WL127X_MINOR_VER);
 676                 break;
 677
 678         case CHIP_ID_1283_PG20:
 679                 wl1271_debug(DEBUG_BOOT, "chip id 0x%x (1283 PG20)",
 680                              wl->chip.id);
 681                 wl->plt_fw_name = WL128X_PLT_FW_NAME;
 682                 wl->sr_fw_name = WL128X_FW_NAME_SINGLE;
 683                 wl->mr_fw_name = WL128X_FW_NAME_MULTI;
 684
 685                 /* wl128x requires TX blocksize alignment */
 686                 wl->quirks |= WLCORE_QUIRK_TX_BLOCKSIZE_ALIGN |
 687                               WLCORE_QUIRK_DUAL_PROBE_TMPL |
 688                               WLCORE_QUIRK_TKIP_HEADER_SPACE |
 689                               WLCORE_QUIRK_START_STA_FAILS;
 690
 691                 wlcore_set_min_fw_ver(wl, WL128X_CHIP_VER, WL128X_IFTYPE_VER,
 692                                       WL128X_MAJOR_VER, WL128X_SUBTYPE_VER,
 693                                       WL128X_MINOR_VER);
 694                 break;
 695         case CHIP_ID_1283_PG10:
 696         default:
 697                 wl1271_warning("unsupported chip id: 0x%x", wl->chip.id);
 698                 ret = -ENODEV;
 699                 goto out;
 700         }
 701
 702         /* common settings */
 703         wl->scan_templ_id_2_4 = CMD_TEMPL_APP_PROBE_REQ_2_4_LEGACY;
 704         wl->scan_templ_id_5 = CMD_TEMPL_APP_PROBE_REQ_5_LEGACY;
 705         wl->sched_scan_templ_id_2_4 = CMD_TEMPL_CFG_PROBE_REQ_2_4;
 706         wl->sched_scan_templ_id_5 = CMD_TEMPL_CFG_PROBE_REQ_5;
 707         wl->max_channels_5 = WL12XX_MAX_CHANNELS_5GHZ;
 708 out:
 709         return ret;
 710 }
 711
 712 static int __must_check wl12xx_top_reg_write(struct wl1271 *wl, int addr,
 713                                              u16 val)
 714 {
 715         int ret;
 716
 717         /* write address >> 1 + 0x30000 to OCP_POR_CTR */
 718         addr = (addr >> 1) + 0x30000;
 719         ret = wlcore_write32(wl, WL12XX_OCP_POR_CTR, addr);
 720         if (ret < 0)
 721                 goto out;
 722
 723         /* write value to OCP_POR_WDATA */
 724         ret = wlcore_write32(wl, WL12XX_OCP_DATA_WRITE, val);
 725         if (ret < 0)
 726                 goto out;
 727
 728         /* write 1 to OCP_CMD */
 729         ret = wlcore_write32(wl, WL12XX_OCP_CMD, OCP_CMD_WRITE);
 730         if (ret < 0)
 731                 goto out;
 732
 733 out:
 734         return ret;
 735 }
 736
 737 static int __must_check wl12xx_top_reg_read(struct wl1271 *wl, int addr,
 738                                             u16 *out)
 739 {
 740         u32 val;
 741         int timeout = OCP_CMD_LOOP;
 742         int ret;
 743
 744         /* write address >> 1 + 0x30000 to OCP_POR_CTR */
 745         addr = (addr >> 1) + 0x30000;
 746         ret = wlcore_write32(wl, WL12XX_OCP_POR_CTR, addr);
 747         if (ret < 0)
 748                 return ret;
 749
 750         /* write 2 to OCP_CMD */
 751         ret = wlcore_write32(wl, WL12XX_OCP_CMD, OCP_CMD_READ);
 752         if (ret < 0)
 753                 return ret;
 754
 755         /* poll for data ready */
 756         do {
 757                 ret = wlcore_read32(wl, WL12XX_OCP_DATA_READ, &val);
 758                 if (ret < 0)
 759                         return ret;
 760         } while (!(val & OCP_READY_MASK) && --timeout);
 761
 762         if (!timeout) {
 763                 wl1271_warning("Top register access timed out.");
 764                 return -ETIMEDOUT;
 765         }
 766
 767         /* check data status and return if OK */
 768         if ((val & OCP_STATUS_MASK) != OCP_STATUS_OK) {
 769                 wl1271_warning("Top register access returned error.");
 770                 return -EIO;
 771         }
 772
 773         if (out)
 774                 *out = val & 0xffff;
 775
 776         return 0;
 777 }
 778
 779 static int wl128x_switch_tcxo_to_fref(struct wl1271 *wl)
 780 {
 781         u16 spare_reg;
 782         int ret;
 783
 784         /* Mask bits [2] & [8:4] in the sys_clk_cfg register */
 785         ret = wl12xx_top_reg_read(wl, WL_SPARE_REG, &spare_reg);
 786         if (ret < 0)
 787                 return ret;
 788
 789         if (spare_reg == 0xFFFF)
 790                 return -EFAULT;
 791         spare_reg |= (BIT(3) | BIT(5) | BIT(6));
 792         ret = wl12xx_top_reg_write(wl, WL_SPARE_REG, spare_reg);
 793         if (ret < 0)
 794                 return ret;
 795
 796         /* Enable FREF_CLK_REQ & mux MCS and coex PLLs to FREF */
 797         ret = wl12xx_top_reg_write(wl, SYS_CLK_CFG_REG,
 798                                    WL_CLK_REQ_TYPE_PG2 | MCS_PLL_CLK_SEL_FREF);
 799         if (ret < 0)
 800                 return ret;
 801
 802         /* Delay execution for 15msec, to let the HW settle */
 803         mdelay(15);
 804
 805         return 0;
 806 }
 807
 808 static bool wl128x_is_tcxo_valid(struct wl1271 *wl)
 809 {
 810         u16 tcxo_detection;
 811         int ret;
 812
 813         ret = wl12xx_top_reg_read(wl, TCXO_CLK_DETECT_REG, &tcxo_detection);
 814         if (ret < 0)
 815                 return false;
 816
 817         if (tcxo_detection & TCXO_DET_FAILED)
 818                 return false;
 819
 820         return true;
 821 }
 822
 823 static bool wl128x_is_fref_valid(struct wl1271 *wl)
 824 {
 825         u16 fref_detection;
 826         int ret;
 827
 828         ret = wl12xx_top_reg_read(wl, FREF_CLK_DETECT_REG, &fref_detection);
 829         if (ret < 0)
 830                 return false;
 831
 832         if (fref_detection & FREF_CLK_DETECT_FAIL)
 833                 return false;
 834
 835         return true;
 836 }
 837
 838 static int wl128x_manually_configure_mcs_pll(struct wl1271 *wl)
 839 {
 840         int ret;
 841
 842         ret = wl12xx_top_reg_write(wl, MCS_PLL_M_REG, MCS_PLL_M_REG_VAL);
 843         if (ret < 0)
 844                 goto out;
 845
 846         ret = wl12xx_top_reg_write(wl, MCS_PLL_N_REG, MCS_PLL_N_REG_VAL);
 847         if (ret < 0)
 848                 goto out;
 849
 850         ret = wl12xx_top_reg_write(wl, MCS_PLL_CONFIG_REG,
 851                                    MCS_PLL_CONFIG_REG_VAL);
 852
 853 out:
 854         return ret;
 855 }
 856
 857 static int wl128x_configure_mcs_pll(struct wl1271 *wl, int clk)
 858 {
 859         u16 spare_reg;
 860         u16 pll_config;
 861         u8 input_freq;
 862         struct wl12xx_priv *priv = wl->priv;
 863         int ret;
 864
 865         /* Mask bits [3:1] in the sys_clk_cfg register */
 866         ret = wl12xx_top_reg_read(wl, WL_SPARE_REG, &spare_reg);
 867         if (ret < 0)
 868                 return ret;
 869
 870         if (spare_reg == 0xFFFF)
 871                 return -EFAULT;
 872         spare_reg |= BIT(2);
 873         ret = wl12xx_top_reg_write(wl, WL_SPARE_REG, spare_reg);
 874         if (ret < 0)
 875                 return ret;
 876
 877         /* Handle special cases of the TCXO clock */
 878         if (priv->tcxo_clock == WL12XX_TCXOCLOCK_16_8 ||
 879             priv->tcxo_clock == WL12XX_TCXOCLOCK_33_6)
 880                 return wl128x_manually_configure_mcs_pll(wl);
 881
 882         /* Set the input frequency according to the selected clock source */
 883         input_freq = (clk & 1) + 1;
 884
 885         ret = wl12xx_top_reg_read(wl, MCS_PLL_CONFIG_REG, &pll_config);
 886         if (ret < 0)
 887                 return ret;
 888
 889         if (pll_config == 0xFFFF)
 890                 return -EFAULT;
 891         pll_config |= (input_freq << MCS_SEL_IN_FREQ_SHIFT);
 892         pll_config |= MCS_PLL_ENABLE_HP;
 893         ret = wl12xx_top_reg_write(wl, MCS_PLL_CONFIG_REG, pll_config);
 894
 895         return ret;
 896 }
 897
 898 /*
 899  * WL128x has two clocks input - TCXO and FREF.
 900  * TCXO is the main clock of the device, while FREF is used to sync
 901  * between the GPS and the cellular modem.
 902  * In cases where TCXO is 32.736MHz or 16.368MHz, the FREF will be used
 903  * as the WLAN/BT main clock.
 904  */
 905 static int wl128x_boot_clk(struct wl1271 *wl, int *selected_clock)
 906 {
 907         struct wl12xx_priv *priv = wl->priv;
 908         u16 sys_clk_cfg;
 909         int ret;
 910
 911         /* For XTAL-only modes, FREF will be used after switching from TCXO */
 912         if (priv->ref_clock == WL12XX_REFCLOCK_26_XTAL ||
 913             priv->ref_clock == WL12XX_REFCLOCK_38_XTAL) {
 914                 if (!wl128x_switch_tcxo_to_fref(wl))
 915                         return -EINVAL;
 916                 goto fref_clk;
 917         }
 918
 919         /* Query the HW, to determine which clock source we should use */
 920         ret = wl12xx_top_reg_read(wl, SYS_CLK_CFG_REG, &sys_clk_cfg);
 921         if (ret < 0)
 922                 return ret;
 923
 924         if (sys_clk_cfg == 0xFFFF)
 925                 return -EINVAL;
 926         if (sys_clk_cfg & PRCM_CM_EN_MUX_WLAN_FREF)
 927                 goto fref_clk;
 928
 929         /* If TCXO is either 32.736MHz or 16.368MHz, switch to FREF */
 930         if (priv->tcxo_clock == WL12XX_TCXOCLOCK_16_368 ||
 931             priv->tcxo_clock == WL12XX_TCXOCLOCK_32_736) {
 932                 if (!wl128x_switch_tcxo_to_fref(wl))
 933                         return -EINVAL;
 934                 goto fref_clk;
 935         }
 936
 937         /* TCXO clock is selected */
 938         if (!wl128x_is_tcxo_valid(wl))
 939                 return -EINVAL;
 940         *selected_clock = priv->tcxo_clock;
 941         goto config_mcs_pll;
 942
 943 fref_clk:
 944         /* FREF clock is selected */
 945         if (!wl128x_is_fref_valid(wl))
 946                 return -EINVAL;
 947         *selected_clock = priv->ref_clock;
 948
 949 config_mcs_pll:
 950         return wl128x_configure_mcs_pll(wl, *selected_clock);
 951 }
 952
 953 static int wl127x_boot_clk(struct wl1271 *wl)
 954 {
 955         struct wl12xx_priv *priv = wl->priv;
 956         u32 pause;
 957         u32 clk;
 958         int ret;
 959
 960         if (WL127X_PG_GET_MAJOR(wl->hw_pg_ver) < 3)
 961                 wl->quirks |= WLCORE_QUIRK_END_OF_TRANSACTION;
 962
 963         if (priv->ref_clock == CONF_REF_CLK_19_2_E ||
 964             priv->ref_clock == CONF_REF_CLK_38_4_E ||
 965             priv->ref_clock == CONF_REF_CLK_38_4_M_XTAL)
 966                 /* ref clk: 19.2/38.4/38.4-XTAL */
 967                 clk = 0x3;
 968         else if (priv->ref_clock == CONF_REF_CLK_26_E ||
 969                  priv->ref_clock == CONF_REF_CLK_26_M_XTAL ||
 970                  priv->ref_clock == CONF_REF_CLK_52_E)
 971                 /* ref clk: 26/52 */
 972                 clk = 0x5;
 973         else
 974                 return -EINVAL;
 975
 976         if (priv->ref_clock != CONF_REF_CLK_19_2_E) {
 977                 u16 val;
 978                 /* Set clock type (open drain) */
 979                 ret = wl12xx_top_reg_read(wl, OCP_REG_CLK_TYPE, &val);
 980                 if (ret < 0)
 981                         goto out;
 982
 983                 val &= FREF_CLK_TYPE_BITS;
 984                 ret = wl12xx_top_reg_write(wl, OCP_REG_CLK_TYPE, val);
 985                 if (ret < 0)
 986                         goto out;
 987
 988                 /* Set clock pull mode (no pull) */
 989                 ret = wl12xx_top_reg_read(wl, OCP_REG_CLK_PULL, &val);
 990                 if (ret < 0)
 991                         goto out;
 992
 993                 val |= NO_PULL;
 994                 ret = wl12xx_top_reg_write(wl, OCP_REG_CLK_PULL, val);
 995                 if (ret < 0)
 996                         goto out;
 997         } else {
 998                 u16 val;
 999                 /* Set clock polarity */
1000                 ret = wl12xx_top_reg_read(wl, OCP_REG_CLK_POLARITY, &val);
1001                 if (ret < 0)
1002                         goto out;
1003
1004                 val &= FREF_CLK_POLARITY_BITS;
1005                 val |= CLK_REQ_OUTN_SEL;
1006                 ret = wl12xx_top_reg_write(wl, OCP_REG_CLK_POLARITY, val);
1007                 if (ret < 0)
1008                         goto out;
1009         }
1010
1011         ret = wlcore_write32(wl, WL12XX_PLL_PARAMETERS, clk);
1012         if (ret < 0)
1013                 goto out;
1014
1015         ret = wlcore_read32(wl, WL12XX_PLL_PARAMETERS, &pause);
1016         if (ret < 0)
1017                 goto out;
1018
1019         wl1271_debug(DEBUG_BOOT, "pause1 0x%x", pause);
1020
1021         pause &= ~(WU_COUNTER_PAUSE_VAL);
1022         pause |= WU_COUNTER_PAUSE_VAL;
1023         ret = wlcore_write32(wl, WL12XX_WU_COUNTER_PAUSE, pause);
1024
1025 out:
1026         return ret;
1027 }
1028
1029 static int wl1271_boot_soft_reset(struct wl1271 *wl)
1030 {
1031         unsigned long timeout;
1032         u32 boot_data;
1033         int ret = 0;
1034
1035         /* perform soft reset */
1036         ret = wlcore_write32(wl, WL12XX_SLV_SOFT_RESET, ACX_SLV_SOFT_RESET_BIT);
1037         if (ret < 0)
1038                 goto out;
1039
1040         /* SOFT_RESET is self clearing */
1041         timeout = jiffies + usecs_to_jiffies(SOFT_RESET_MAX_TIME);
1042         while (1) {
1043                 ret = wlcore_read32(wl, WL12XX_SLV_SOFT_RESET, &boot_data);
1044                 if (ret < 0)
1045                         goto out;
1046
1047                 wl1271_debug(DEBUG_BOOT, "soft reset bootdata 0x%x", boot_data);
1048                 if ((boot_data & ACX_SLV_SOFT_RESET_BIT) == 0)
1049                         break;
1050
1051                 if (time_after(jiffies, timeout)) {
1052                         /* 1.2 check pWhalBus->uSelfClearTime if the
1053                          * timeout was reached */
1054                         wl1271_error("soft reset timeout");
1055                         return -1;
1056                 }
1057
1058                 udelay(SOFT_RESET_STALL_TIME);
1059         }
1060
1061         /* disable Rx/Tx */
1062         ret = wlcore_write32(wl, WL12XX_ENABLE, 0x0);
1063         if (ret < 0)
1064                 goto out;
1065
1066         /* disable auto calibration on start*/
1067         ret = wlcore_write32(wl, WL12XX_SPARE_A2, 0xffff);
1068
1069 out:
1070         return ret;
1071 }
1072
1073 static int wl12xx_pre_boot(struct wl1271 *wl)
1074 {
1075         struct wl12xx_priv *priv = wl->priv;
1076         int ret = 0;
1077         u32 clk;
1078         int selected_clock = -1;
1079
1080         if (wl->chip.id == CHIP_ID_1283_PG20) {
1081                 ret = wl128x_boot_clk(wl, &selected_clock);
1082                 if (ret < 0)
1083                         goto out;
1084         } else {
1085                 ret = wl127x_boot_clk(wl);
1086                 if (ret < 0)
1087                         goto out;
1088         }
1089
1090         /* Continue the ELP wake up sequence */
1091         ret = wlcore_write32(wl, WL12XX_WELP_ARM_COMMAND, WELP_ARM_COMMAND_VAL);
1092         if (ret < 0)
1093                 goto out;
1094
1095         udelay(500);
1096
1097         ret = wlcore_set_partition(wl, &wl->ptable[PART_DRPW]);
1098         if (ret < 0)
1099                 goto out;
1100
1101         /* Read-modify-write DRPW_SCRATCH_START register (see next state)
1102            to be used by DRPw FW. The RTRIM value will be added by the FW
1103            before taking DRPw out of reset */
1104
1105         ret = wlcore_read32(wl, WL12XX_DRPW_SCRATCH_START, &clk);
1106         if (ret < 0)
1107                 goto out;
1108
1109         wl1271_debug(DEBUG_BOOT, "clk2 0x%x", clk);
1110
1111         if (wl->chip.id == CHIP_ID_1283_PG20)
1112                 clk |= ((selected_clock & 0x3) << 1) << 4;
1113         else
1114                 clk |= (priv->ref_clock << 1) << 4;
1115
1116         ret = wlcore_write32(wl, WL12XX_DRPW_SCRATCH_START, clk);
1117         if (ret < 0)
1118                 goto out;
1119
1120         ret = wlcore_set_partition(wl, &wl->ptable[PART_WORK]);
1121         if (ret < 0)
1122                 goto out;
1123
1124         /* Disable interrupts */
1125         ret = wlcore_write_reg(wl, REG_INTERRUPT_MASK, WL1271_ACX_INTR_ALL);
1126         if (ret < 0)
1127                 goto out;
1128
1129         ret = wl1271_boot_soft_reset(wl);
1130         if (ret < 0)
1131                 goto out;
1132
1133 out:
1134         return ret;
1135 }
1136
1137 static int wl12xx_pre_upload(struct wl1271 *wl)
1138 {
1139         u32 tmp;
1140         u16 polarity;
1141         int ret;
1142
1143         /* write firmware's last address (ie. it's length) to
1144          * ACX_EEPROMLESS_IND_REG */
1145         wl1271_debug(DEBUG_BOOT, "ACX_EEPROMLESS_IND_REG");
1146
1147         ret = wlcore_write32(wl, WL12XX_EEPROMLESS_IND, WL12XX_EEPROMLESS_IND);
1148         if (ret < 0)
1149                 goto out;
1150
1151         ret = wlcore_read_reg(wl, REG_CHIP_ID_B, &tmp);
1152         if (ret < 0)
1153                 goto out;
1154
1155         wl1271_debug(DEBUG_BOOT, "chip id 0x%x", tmp);
1156
1157         /* 6. read the EEPROM parameters */
1158         ret = wlcore_read32(wl, WL12XX_SCR_PAD2, &tmp);
1159         if (ret < 0)
1160                 goto out;
1161
1162         /* WL1271: The reference driver skips steps 7 to 10 (jumps directly
1163          * to upload_fw) */
1164
1165         if (wl->chip.id == CHIP_ID_1283_PG20) {
1166                 ret = wl12xx_top_reg_write(wl, SDIO_IO_DS, HCI_IO_DS_6MA);
1167                 if (ret < 0)
1168                         goto out;
1169         }
1170
1171         /* polarity must be set before the firmware is loaded */
1172         ret = wl12xx_top_reg_read(wl, OCP_REG_POLARITY, &polarity);
1173         if (ret < 0)
1174                 goto out;
1175
1176         /* We use HIGH polarity, so unset the LOW bit */
1177         polarity &= ~POLARITY_LOW;
1178         ret = wl12xx_top_reg_write(wl, OCP_REG_POLARITY, polarity);
1179
1180 out:
1181         return ret;
1182 }
1183
1184 static int wl12xx_enable_interrupts(struct wl1271 *wl)
1185 {
1186         int ret;
1187
1188         ret = wlcore_write_reg(wl, REG_INTERRUPT_MASK,
1189                                WL12XX_ACX_ALL_EVENTS_VECTOR);
1190         if (ret < 0)
1191                 goto out;
1192
1193         wlcore_enable_interrupts(wl);
1194         ret = wlcore_write_reg(wl, REG_INTERRUPT_MASK,
1195                                WL1271_ACX_INTR_ALL & ~(WL12XX_INTR_MASK));
1196         if (ret < 0)
1197                 goto disable_interrupts;
1198
1199         ret = wlcore_write32(wl, WL12XX_HI_CFG, HI_CFG_DEF_VAL);
1200         if (ret < 0)
1201                 goto disable_interrupts;
1202
1203         return ret;
1204
1205 disable_interrupts:
1206         wlcore_disable_interrupts(wl);
1207
1208 out:
1209         return ret;
1210 }
1211
1212 static int wl12xx_boot(struct wl1271 *wl)
1213 {
1214         int ret;
1215
1216         ret = wl12xx_pre_boot(wl);
1217         if (ret < 0)
1218                 goto out;
1219
1220         ret = wlcore_boot_upload_nvs(wl);
1221         if (ret < 0)
1222                 goto out;
1223
1224         ret = wl12xx_pre_upload(wl);
1225         if (ret < 0)
1226                 goto out;
1227
1228         ret = wlcore_boot_upload_firmware(wl);
1229         if (ret < 0)
1230                 goto out;
1231
1232         ret = wlcore_boot_run_firmware(wl);
1233         if (ret < 0)
1234                 goto out;
1235
1236         ret = wl12xx_enable_interrupts(wl);
1237
1238 out:
1239         return ret;
1240 }
1241
1242 static int wl12xx_trigger_cmd(struct wl1271 *wl, int cmd_box_addr,
1243                                void *buf, size_t len)
1244 {
1245         int ret;
1246
1247         ret = wlcore_write(wl, cmd_box_addr, buf, len, false);
1248         if (ret < 0)
1249                 return ret;
1250
1251         ret = wlcore_write_reg(wl, REG_INTERRUPT_TRIG, WL12XX_INTR_TRIG_CMD);
1252
1253         return ret;
1254 }
1255
1256 static int wl12xx_ack_event(struct wl1271 *wl)
1257 {
1258         return wlcore_write_reg(wl, REG_INTERRUPT_TRIG,
1259                                 WL12XX_INTR_TRIG_EVENT_ACK);
1260 }
1261
1262 static u32 wl12xx_calc_tx_blocks(struct wl1271 *wl, u32 len, u32 spare_blks)
1263 {
1264         u32 blk_size = WL12XX_TX_HW_BLOCK_SIZE;
1265         u32 align_len = wlcore_calc_packet_alignment(wl, len);
1266
1267         return (align_len + blk_size - 1) / blk_size + spare_blks;
1268 }
1269
1270 static void
1271 wl12xx_set_tx_desc_blocks(struct wl1271 *wl, struct wl1271_tx_hw_descr *desc,
1272                           u32 blks, u32 spare_blks)
1273 {
1274         if (wl->chip.id == CHIP_ID_1283_PG20) {
1275                 desc->wl128x_mem.total_mem_blocks = blks;
1276         } else {
1277                 desc->wl127x_mem.extra_blocks = spare_blks;
1278                 desc->wl127x_mem.total_mem_blocks = blks;
1279         }
1280 }
1281
1282 static void
1283 wl12xx_set_tx_desc_data_len(struct wl1271 *wl, struct wl1271_tx_hw_descr *desc,
1284                             struct sk_buff *skb)
1285 {
1286         u32 aligned_len = wlcore_calc_packet_alignment(wl, skb->len);
1287
1288         if (wl->chip.id == CHIP_ID_1283_PG20) {
1289                 desc->wl128x_mem.extra_bytes = aligned_len - skb->len;
1290                 desc->length = cpu_to_le16(aligned_len >> 2);
1291
1292                 wl1271_debug(DEBUG_TX,
1293                              "tx_fill_hdr: hlid: %d len: %d life: %d mem: %d extra: %d",
1294                              desc->hlid,
1295                              le16_to_cpu(desc->length),
1296                              le16_to_cpu(desc->life_time),
1297                              desc->wl128x_mem.total_mem_blocks,
1298                              desc->wl128x_mem.extra_bytes);
1299         } else {
1300                 /* calculate number of padding bytes */
1301                 int pad = aligned_len - skb->len;
1302                 desc->tx_attr |=
1303                         cpu_to_le16(pad << TX_HW_ATTR_OFST_LAST_WORD_PAD);
1304
1305                 /* Store the aligned length in terms of words */
1306                 desc->length = cpu_to_le16(aligned_len >> 2);
1307
1308                 wl1271_debug(DEBUG_TX,
1309                              "tx_fill_hdr: pad: %d hlid: %d len: %d life: %d mem: %d",
1310                              pad, desc->hlid,
1311                              le16_to_cpu(desc->length),
1312                              le16_to_cpu(desc->life_time),
1313                              desc->wl127x_mem.total_mem_blocks);
1314         }
1315 }
1316
1317 static enum wl_rx_buf_align
1318 wl12xx_get_rx_buf_align(struct wl1271 *wl, u32 rx_desc)
1319 {
1320         if (rx_desc & RX_BUF_UNALIGNED_PAYLOAD)
1321                 return WLCORE_RX_BUF_UNALIGNED;
1322
1323         return WLCORE_RX_BUF_ALIGNED;
1324 }
1325
1326 static u32 wl12xx_get_rx_packet_len(struct wl1271 *wl, void *rx_data,
1327                                     u32 data_len)
1328 {
1329         struct wl1271_rx_descriptor *desc = rx_data;
1330
1331         /* invalid packet */
1332         if (data_len < sizeof(*desc) ||
1333             data_len < sizeof(*desc) + desc->pad_len)
1334                 return 0;
1335
1336         return data_len - sizeof(*desc) - desc->pad_len;
1337 }
1338
1339 static int wl12xx_tx_delayed_compl(struct wl1271 *wl)
1340 {
1341         if (wl->fw_status_1->tx_results_counter ==
1342             (wl->tx_results_count & 0xff))
1343                 return 0;
1344
1345         return wlcore_tx_complete(wl);
1346 }
1347
1348 static int wl12xx_hw_init(struct wl1271 *wl)
1349 {
1350         int ret;
1351
1352         if (wl->chip.id == CHIP_ID_1283_PG20) {
1353                 u32 host_cfg_bitmap = HOST_IF_CFG_RX_FIFO_ENABLE;
1354
1355                 ret = wl128x_cmd_general_parms(wl);
1356                 if (ret < 0)
1357                         goto out;
1358
1359                 /*
1360                  * If we are in calibrator based auto detect then we got the FEM nr
1361                  * in wl->fem_manuf. No need to continue further
1362                  */
1363                 if (wl->plt_mode == PLT_FEM_DETECT)
1364                         goto out;
1365
1366                 ret = wl128x_cmd_radio_parms(wl);
1367                 if (ret < 0)
1368                         goto out;
1369
1370                 if (wl->quirks & WLCORE_QUIRK_TX_BLOCKSIZE_ALIGN)
1371                         /* Enable SDIO padding */
1372                         host_cfg_bitmap |= HOST_IF_CFG_TX_PAD_TO_SDIO_BLK;
1373
1374                 /* Must be before wl1271_acx_init_mem_config() */
1375                 ret = wl1271_acx_host_if_cfg_bitmap(wl, host_cfg_bitmap);
1376                 if (ret < 0)
1377                         goto out;
1378         } else {
1379                 ret = wl1271_cmd_general_parms(wl);
1380                 if (ret < 0)
1381                         goto out;
1382
1383                 /*
1384                  * If we are in calibrator based auto detect then we got the FEM nr
1385                  * in wl->fem_manuf. No need to continue further
1386                  */
1387                 if (wl->plt_mode == PLT_FEM_DETECT)
1388                         goto out;
1389
1390                 ret = wl1271_cmd_radio_parms(wl);
1391                 if (ret < 0)
1392                         goto out;
1393                 ret = wl1271_cmd_ext_radio_parms(wl);
1394                 if (ret < 0)
1395                         goto out;
1396         }
1397 out:
1398         return ret;
1399 }
1400
1401 static u32 wl12xx_sta_get_ap_rate_mask(struct wl1271 *wl,
1402                                        struct wl12xx_vif *wlvif)
1403 {
1404         return wlvif->rate_set;
1405 }
1406
1407 static int wl12xx_identify_fw(struct wl1271 *wl)
1408 {
1409         unsigned int *fw_ver = wl->chip.fw_ver;
1410
1411         /* Only new station firmwares support routing fw logs to the host */
1412         if ((fw_ver[FW_VER_IF_TYPE] == FW_VER_IF_TYPE_STA) &&
1413             (fw_ver[FW_VER_MINOR] < FW_VER_MINOR_FWLOG_STA_MIN))
1414                 wl->quirks |= WLCORE_QUIRK_FWLOG_NOT_IMPLEMENTED;
1415
1416         /* This feature is not yet supported for AP mode */
1417         if (fw_ver[FW_VER_IF_TYPE] == FW_VER_IF_TYPE_AP)
1418                 wl->quirks |= WLCORE_QUIRK_FWLOG_NOT_IMPLEMENTED;
1419
1420         return 0;
1421 }
1422
1423 static void wl12xx_conf_init(struct wl1271 *wl)
1424 {
1425         struct wl12xx_priv *priv = wl->priv;
1426
1427         /* apply driver default configuration */
1428         memcpy(&wl->conf, &wl12xx_conf, sizeof(wl12xx_conf));
1429
1430         /* apply default private configuration */
1431         memcpy(&priv->conf, &wl12xx_default_priv_conf, sizeof(priv->conf));
1432 }
1433
1434 static bool wl12xx_mac_in_fuse(struct wl1271 *wl)
1435 {
1436         bool supported = false;
1437         u8 major, minor;
1438
1439         if (wl->chip.id == CHIP_ID_1283_PG20) {
1440                 major = WL128X_PG_GET_MAJOR(wl->hw_pg_ver);
1441                 minor = WL128X_PG_GET_MINOR(wl->hw_pg_ver);
1442
1443                 /* in wl128x we have the MAC address if the PG is >= (2, 1) */
1444                 if (major > 2 || (major == 2 && minor >= 1))
1445                         supported = true;
1446         } else {
1447                 major = WL127X_PG_GET_MAJOR(wl->hw_pg_ver);
1448                 minor = WL127X_PG_GET_MINOR(wl->hw_pg_ver);
1449
1450                 /* in wl127x we have the MAC address if the PG is >= (3, 1) */
1451                 if (major == 3 && minor >= 1)
1452                         supported = true;
1453         }
1454
1455         wl1271_debug(DEBUG_PROBE,
1456                      "PG Ver major = %d minor = %d, MAC %s present",
1457                      major, minor, supported ? "is" : "is not");
1458
1459         return supported;
1460 }
1461
1462 static int wl12xx_get_fuse_mac(struct wl1271 *wl)
1463 {
1464         u32 mac1, mac2;
1465         int ret;
1466
1467         ret = wlcore_set_partition(wl, &wl->ptable[PART_DRPW]);
1468         if (ret < 0)
1469                 goto out;
1470
1471         ret = wlcore_read32(wl, WL12XX_REG_FUSE_BD_ADDR_1, &mac1);
1472         if (ret < 0)
1473                 goto out;
1474
1475         ret = wlcore_read32(wl, WL12XX_REG_FUSE_BD_ADDR_2, &mac2);
1476         if (ret < 0)
1477                 goto out;
1478
1479         /* these are the two parts of the BD_ADDR */
1480         wl->fuse_oui_addr = ((mac2 & 0xffff) << 8) +
1481                 ((mac1 & 0xff000000) >> 24);
1482         wl->fuse_nic_addr = mac1 & 0xffffff;
1483
1484         ret = wlcore_set_partition(wl, &wl->ptable[PART_DOWN]);
1485
1486 out:
1487         return ret;
1488 }
1489
1490 static int wl12xx_get_pg_ver(struct wl1271 *wl, s8 *ver)
1491 {
1492         u16 die_info;
1493         int ret;
1494
1495         if (wl->chip.id == CHIP_ID_1283_PG20)
1496                 ret = wl12xx_top_reg_read(wl, WL128X_REG_FUSE_DATA_2_1,
1497                                           &die_info);
1498         else
1499                 ret = wl12xx_top_reg_read(wl, WL127X_REG_FUSE_DATA_2_1,
1500                                           &die_info);
1501
1502         if (ret >= 0 && ver)
1503                 *ver = (s8)((die_info & PG_VER_MASK) >> PG_VER_OFFSET);
1504
1505         return ret;
1506 }
1507
1508 static int wl12xx_get_mac(struct wl1271 *wl)
1509 {
1510         if (wl12xx_mac_in_fuse(wl))
1511                 return wl12xx_get_fuse_mac(wl);
1512
1513         return 0;
1514 }
1515
1516 static void wl12xx_set_tx_desc_csum(struct wl1271 *wl,
1517                                     struct wl1271_tx_hw_descr *desc,
1518                                     struct sk_buff *skb)
1519 {
1520         desc->wl12xx_reserved = 0;
1521 }
1522
1523 static int wl12xx_plt_init(struct wl1271 *wl)
1524 {
1525         int ret;
1526
1527         ret = wl->ops->boot(wl);
1528         if (ret < 0)
1529                 goto out;
1530
1531         ret = wl->ops->hw_init(wl);
1532         if (ret < 0)
1533                 goto out_irq_disable;
1534
1535         /*
1536          * If we are in calibrator based auto detect then we got the FEM nr
1537          * in wl->fem_manuf. No need to continue further
1538          */
1539         if (wl->plt_mode == PLT_FEM_DETECT)
1540                 goto out;
1541
1542         ret = wl1271_acx_init_mem_config(wl);
1543         if (ret < 0)
1544                 goto out_irq_disable;
1545
1546         ret = wl12xx_acx_mem_cfg(wl);
1547         if (ret < 0)
1548                 goto out_free_memmap;
1549
1550         /* Enable data path */
1551         ret = wl1271_cmd_data_path(wl, 1);
1552         if (ret < 0)
1553                 goto out_free_memmap;
1554
1555         /* Configure for CAM power saving (ie. always active) */
1556         ret = wl1271_acx_sleep_auth(wl, WL1271_PSM_CAM);
1557         if (ret < 0)
1558                 goto out_free_memmap;
1559
1560         /* configure PM */
1561         ret = wl1271_acx_pm_config(wl);
1562         if (ret < 0)
1563                 goto out_free_memmap;
1564
1565         goto out;
1566
1567 out_free_memmap:
1568         kfree(wl->target_mem_map);
1569         wl->target_mem_map = NULL;
1570
1571 out_irq_disable:
1572         mutex_unlock(&wl->mutex);
1573         /* Unlocking the mutex in the middle of handling is
1574            inherently unsafe. In this case we deem it safe to do,
1575            because we need to let any possibly pending IRQ out of
1576            the system (and while we are WL1271_STATE_OFF the IRQ
1577            work function will not do anything.) Also, any other
1578            possible concurrent operations will fail due to the
1579            current state, hence the wl1271 struct should be safe. */
1580         wlcore_disable_interrupts(wl);
1581         mutex_lock(&wl->mutex);
1582 out:
1583         return ret;
1584 }
1585
1586 static int wl12xx_get_spare_blocks(struct wl1271 *wl, bool is_gem)
1587 {
1588         if (is_gem)
1589                 return WL12XX_TX_HW_BLOCK_GEM_SPARE;
1590
1591         return WL12XX_TX_HW_BLOCK_SPARE_DEFAULT;
1592 }
1593
1594 static int wl12xx_set_key(struct wl1271 *wl, enum set_key_cmd cmd,
1595                           struct ieee80211_vif *vif,
1596                           struct ieee80211_sta *sta,
1597                           struct ieee80211_key_conf *key_conf)
1598 {
1599         return wlcore_set_key(wl, cmd, vif, sta, key_conf);
1600 }
1601
1602 static int wl12xx_setup(struct wl1271 *wl);
1603
1604 static struct wlcore_ops wl12xx_ops = {
1605         .setup                  = wl12xx_setup,
1606         .identify_chip          = wl12xx_identify_chip,
1607         .identify_fw            = wl12xx_identify_fw,
1608         .boot                   = wl12xx_boot,
1609         .plt_init               = wl12xx_plt_init,
1610         .trigger_cmd            = wl12xx_trigger_cmd,
1611         .ack_event              = wl12xx_ack_event,
1612         .calc_tx_blocks         = wl12xx_calc_tx_blocks,
1613         .set_tx_desc_blocks     = wl12xx_set_tx_desc_blocks,
1614         .set_tx_desc_data_len   = wl12xx_set_tx_desc_data_len,
1615         .get_rx_buf_align       = wl12xx_get_rx_buf_align,
1616         .get_rx_packet_len      = wl12xx_get_rx_packet_len,
1617         .tx_immediate_compl     = NULL,
1618         .tx_delayed_compl       = wl12xx_tx_delayed_compl,
1619         .hw_init                = wl12xx_hw_init,
1620         .init_vif               = NULL,
1621         .sta_get_ap_rate_mask   = wl12xx_sta_get_ap_rate_mask,
1622         .get_pg_ver             = wl12xx_get_pg_ver,
1623         .get_mac                = wl12xx_get_mac,
1624         .set_tx_desc_csum       = wl12xx_set_tx_desc_csum,
1625         .set_rx_csum            = NULL,
1626         .ap_get_mimo_wide_rate_mask = NULL,
1627         .debugfs_init           = wl12xx_debugfs_add_files,
1628         .scan_start             = wl12xx_scan_start,
1629         .scan_stop              = wl12xx_scan_stop,
1630         .scan_completed         = wl12xx_scan_completed,
1631         .sched_scan_start       = wl12xx_sched_scan_start,
1632         .sched_scan_stop        = wl12xx_scan_sched_scan_stop,
1633         .get_spare_blocks       = wl12xx_get_spare_blocks,
1634         .set_key                = wl12xx_set_key,
1635         .pre_pkt_send           = NULL,
1636 };
1637
1638 static struct ieee80211_sta_ht_cap wl12xx_ht_cap = {
1639         .cap = IEEE80211_HT_CAP_GRN_FLD | IEEE80211_HT_CAP_SGI_20 |
1640                (1 << IEEE80211_HT_CAP_RX_STBC_SHIFT),
1641         .ht_supported = true,
1642         .ampdu_factor = IEEE80211_HT_MAX_AMPDU_8K,
1643         .ampdu_density = IEEE80211_HT_MPDU_DENSITY_8,
1644         .mcs = {
1645                 .rx_mask = { 0xff, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
1646                 .rx_highest = cpu_to_le16(72),
1647                 .tx_params = IEEE80211_HT_MCS_TX_DEFINED,
1648                 },
1649 };
1650
1651 static int wl12xx_setup(struct wl1271 *wl)
1652 {
1653         struct wl12xx_priv *priv = wl->priv;
1654         struct wl12xx_platform_data *pdata = wl->pdev->dev.platform_data;
1655
1656         wl->rtable = wl12xx_rtable;
1657         wl->num_tx_desc = WL12XX_NUM_TX_DESCRIPTORS;
1658         wl->num_rx_desc = WL12XX_NUM_RX_DESCRIPTORS;
1659         wl->num_mac_addr = WL12XX_NUM_MAC_ADDRESSES;
1660         wl->band_rate_to_idx = wl12xx_band_rate_to_idx;
1661         wl->hw_tx_rate_tbl_size = WL12XX_CONF_HW_RXTX_RATE_MAX;
1662         wl->hw_min_ht_rate = WL12XX_CONF_HW_RXTX_RATE_MCS0;
1663         wl->fw_status_priv_len = 0;
1664         wl->stats.fw_stats_len = sizeof(struct wl12xx_acx_statistics);
1665         wlcore_set_ht_cap(wl, IEEE80211_BAND_2GHZ, &wl12xx_ht_cap);
1666         wlcore_set_ht_cap(wl, IEEE80211_BAND_5GHZ, &wl12xx_ht_cap);
1667         wl12xx_conf_init(wl);
1668
1669         if (!fref_param) {
1670                 priv->ref_clock = pdata->board_ref_clock;
1671         } else {
1672                 if (!strcmp(fref_param, "19.2"))
1673                         priv->ref_clock = WL12XX_REFCLOCK_19;
1674                 else if (!strcmp(fref_param, "26"))
1675                         priv->ref_clock = WL12XX_REFCLOCK_26;
1676                 else if (!strcmp(fref_param, "26x"))
1677                         priv->ref_clock = WL12XX_REFCLOCK_26_XTAL;
1678                 else if (!strcmp(fref_param, "38.4"))
1679                         priv->ref_clock = WL12XX_REFCLOCK_38;
1680                 else if (!strcmp(fref_param, "38.4x"))
1681                         priv->ref_clock = WL12XX_REFCLOCK_38_XTAL;
1682                 else if (!strcmp(fref_param, "52"))
1683                         priv->ref_clock = WL12XX_REFCLOCK_52;
1684                 else
1685                         wl1271_error("Invalid fref parameter %s", fref_param);
1686         }
1687
1688         if (!tcxo_param) {
1689                 priv->tcxo_clock = pdata->board_tcxo_clock;
1690         } else {
1691                 if (!strcmp(tcxo_param, "19.2"))
1692                         priv->tcxo_clock = WL12XX_TCXOCLOCK_19_2;
1693                 else if (!strcmp(tcxo_param, "26"))
1694                         priv->tcxo_clock = WL12XX_TCXOCLOCK_26;
1695                 else if (!strcmp(tcxo_param, "38.4"))
1696                         priv->tcxo_clock = WL12XX_TCXOCLOCK_38_4;
1697                 else if (!strcmp(tcxo_param, "52"))
1698                         priv->tcxo_clock = WL12XX_TCXOCLOCK_52;
1699                 else if (!strcmp(tcxo_param, "16.368"))
1700                         priv->tcxo_clock = WL12XX_TCXOCLOCK_16_368;
1701                 else if (!strcmp(tcxo_param, "32.736"))
1702                         priv->tcxo_clock = WL12XX_TCXOCLOCK_32_736;
1703                 else if (!strcmp(tcxo_param, "16.8"))
1704                         priv->tcxo_clock = WL12XX_TCXOCLOCK_16_8;
1705                 else if (!strcmp(tcxo_param, "33.6"))
1706                         priv->tcxo_clock = WL12XX_TCXOCLOCK_33_6;
1707                 else
1708                         wl1271_error("Invalid tcxo parameter %s", tcxo_param);
1709         }
1710
1711         return 0;
1712 }
1713
1714 static int __devinit wl12xx_probe(struct platform_device *pdev)
1715 {
1716         struct wl1271 *wl;
1717         struct ieee80211_hw *hw;
1718         int ret;
1719
1720         hw = wlcore_alloc_hw(sizeof(struct wl12xx_priv),
1721                              WL12XX_AGGR_BUFFER_SIZE);
1722         if (IS_ERR(hw)) {
1723                 wl1271_error("can't allocate hw");
1724                 ret = PTR_ERR(hw);
1725                 goto out;
1726         }
1727
1728         wl = hw->priv;
1729         wl->ops = &wl12xx_ops;
1730         wl->ptable = wl12xx_ptable;
1731         ret = wlcore_probe(wl, pdev);
1732         if (ret)
1733                 goto out_free;
1734
1735         return ret;
1736
1737 out_free:
1738         wlcore_free_hw(wl);
1739 out:
1740         return ret;
1741 }
1742
1743 static const struct platform_device_id wl12xx_id_table[] __devinitconst = {
1744         { "wl12xx", 0 },
1745         {  } /* Terminating Entry */
1746 };
1747 MODULE_DEVICE_TABLE(platform, wl12xx_id_table);
1748
1749 static struct platform_driver wl12xx_driver = {
1750         .probe          = wl12xx_probe,
1751         .remove         = __devexit_p(wlcore_remove),
1752         .id_table       = wl12xx_id_table,
1753         .driver = {
1754                 .name   = "wl12xx_driver",
1755                 .owner  = THIS_MODULE,
1756         }
1757 };
1758
1759 module_platform_driver(wl12xx_driver);
1760
1761 module_param_named(fref, fref_param, charp, 0);
1762 MODULE_PARM_DESC(fref, "FREF clock: 19.2, 26, 26x, 38.4, 38.4x, 52");
1763
1764 module_param_named(tcxo, tcxo_param, charp, 0);
1765 MODULE_PARM_DESC(tcxo,
1766                  "TCXO clock: 19.2, 26, 38.4, 52, 16.368, 32.736, 16.8, 33.6");
1767
1768 MODULE_LICENSE("GPL v2");
1769 MODULE_AUTHOR("Luciano Coelho <coelho@ti.com>");
1770 MODULE_FIRMWARE(WL127X_FW_NAME_SINGLE);
1771 MODULE_FIRMWARE(WL127X_FW_NAME_MULTI);
1772 MODULE_FIRMWARE(WL127X_PLT_FW_NAME);
1773 MODULE_FIRMWARE(WL128X_FW_NAME_SINGLE);
1774 MODULE_FIRMWARE(WL128X_FW_NAME_MULTI);
1775 MODULE_FIRMWARE(WL128X_PLT_FW_NAME);