2 * I2C Link Layer for PN544 HCI based Driver
4 * Copyright (C) 2012 Intel Corporation. All rights reserved.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, see <http://www.gnu.org/licenses/>.
19 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
21 #include <linux/crc-ccitt.h>
22 #include <linux/module.h>
23 #include <linux/i2c.h>
24 #include <linux/gpio.h>
25 #include <linux/miscdevice.h>
26 #include <linux/interrupt.h>
27 #include <linux/delay.h>
28 #include <linux/nfc.h>
29 #include <linux/firmware.h>
30 #include <linux/unaligned/access_ok.h>
31 #include <linux/platform_data/pn544.h>
33 #include <net/nfc/hci.h>
34 #include <net/nfc/llc.h>
35 #include <net/nfc/nfc.h>
39 #define PN544_I2C_FRAME_HEADROOM 1
40 #define PN544_I2C_FRAME_TAILROOM 2
42 /* framing in HCI mode */
43 #define PN544_HCI_I2C_LLC_LEN 1
44 #define PN544_HCI_I2C_LLC_CRC 2
45 #define PN544_HCI_I2C_LLC_LEN_CRC (PN544_HCI_I2C_LLC_LEN + \
46 PN544_HCI_I2C_LLC_CRC)
47 #define PN544_HCI_I2C_LLC_MIN_SIZE (1 + PN544_HCI_I2C_LLC_LEN_CRC)
48 #define PN544_HCI_I2C_LLC_MAX_PAYLOAD 29
49 #define PN544_HCI_I2C_LLC_MAX_SIZE (PN544_HCI_I2C_LLC_LEN_CRC + 1 + \
50 PN544_HCI_I2C_LLC_MAX_PAYLOAD)
52 static struct i2c_device_id pn544_hci_i2c_id_table[] = {
57 MODULE_DEVICE_TABLE(i2c, pn544_hci_i2c_id_table);
59 #define PN544_HCI_I2C_DRIVER_NAME "pn544_hci_i2c"
61 #define PN544_FW_CMD_WRITE 0x08
62 #define PN544_FW_CMD_CHECK 0x06
64 struct pn544_i2c_fw_frame_write {
72 struct pn544_i2c_fw_frame_check {
80 struct pn544_i2c_fw_frame_response {
85 struct pn544_i2c_fw_blob {
91 #define PN544_FW_CMD_RESULT_TIMEOUT 0x01
92 #define PN544_FW_CMD_RESULT_BAD_CRC 0x02
93 #define PN544_FW_CMD_RESULT_ACCESS_DENIED 0x08
94 #define PN544_FW_CMD_RESULT_PROTOCOL_ERROR 0x0B
95 #define PN544_FW_CMD_RESULT_INVALID_PARAMETER 0x11
96 #define PN544_FW_CMD_RESULT_INVALID_LENGTH 0x18
97 #define PN544_FW_CMD_RESULT_WRITE_FAILED 0x74
99 #define MIN(X, Y) ((X) < (Y) ? (X) : (Y))
101 #define PN544_FW_WRITE_BUFFER_MAX_LEN 0x9f7
102 #define PN544_FW_I2C_MAX_PAYLOAD PN544_HCI_I2C_LLC_MAX_SIZE
103 #define PN544_FW_I2C_WRITE_FRAME_HEADER_LEN 8
104 #define PN544_FW_I2C_WRITE_DATA_MAX_LEN MIN((PN544_FW_I2C_MAX_PAYLOAD -\
105 PN544_FW_I2C_WRITE_FRAME_HEADER_LEN),\
106 PN544_FW_WRITE_BUFFER_MAX_LEN)
108 #define FW_WORK_STATE_IDLE 1
109 #define FW_WORK_STATE_START 2
110 #define FW_WORK_STATE_WAIT_WRITE_ANSWER 3
111 #define FW_WORK_STATE_WAIT_CHECK_ANSWER 4
113 struct pn544_i2c_phy {
114 struct i2c_client *i2c_dev;
115 struct nfc_hci_dev *hdev;
117 unsigned int gpio_en;
118 unsigned int gpio_irq;
119 unsigned int gpio_fw;
120 unsigned int en_polarity;
122 struct work_struct fw_work;
124 char firmware_name[NFC_FIRMWARE_NAME_MAXSIZE + 1];
125 const struct firmware *fw;
126 u32 fw_blob_dest_addr;
128 const u8 *fw_blob_data;
136 * < 0 if hardware error occured (e.g. i2c err)
137 * and prevents normal operation.
141 #define I2C_DUMP_SKB(info, skb) \
143 pr_debug("%s:\n", info); \
144 print_hex_dump(KERN_DEBUG, "i2c: ", DUMP_PREFIX_OFFSET, \
145 16, 1, (skb)->data, (skb)->len, 0); \
148 static void pn544_hci_i2c_platform_init(struct pn544_i2c_phy *phy)
150 int polarity, retry, ret;
151 char rset_cmd[] = { 0x05, 0xF9, 0x04, 0x00, 0xC3, 0xE5 };
152 int count = sizeof(rset_cmd);
154 nfc_info(&phy->i2c_dev->dev, "Detecting nfc_en polarity\n");
156 /* Disable fw download */
157 gpio_set_value(phy->gpio_fw, 0);
159 for (polarity = 0; polarity < 2; polarity++) {
160 phy->en_polarity = polarity;
164 gpio_set_value(phy->gpio_en, !phy->en_polarity);
165 usleep_range(10000, 15000);
168 gpio_set_value(phy->gpio_en, phy->en_polarity);
169 usleep_range(10000, 15000);
172 dev_dbg(&phy->i2c_dev->dev, "Sending reset cmd\n");
173 ret = i2c_master_send(phy->i2c_dev, rset_cmd, count);
175 nfc_info(&phy->i2c_dev->dev,
176 "nfc_en polarity : active %s\n",
177 (polarity == 0 ? "low" : "high"));
183 nfc_err(&phy->i2c_dev->dev,
184 "Could not detect nfc_en polarity, fallback to active high\n");
187 gpio_set_value(phy->gpio_en, !phy->en_polarity);
190 static void pn544_hci_i2c_enable_mode(struct pn544_i2c_phy *phy, int run_mode)
192 gpio_set_value(phy->gpio_fw, run_mode == PN544_FW_MODE ? 1 : 0);
193 gpio_set_value(phy->gpio_en, phy->en_polarity);
194 usleep_range(10000, 15000);
196 phy->run_mode = run_mode;
199 static int pn544_hci_i2c_enable(void *phy_id)
201 struct pn544_i2c_phy *phy = phy_id;
203 pr_info("%s\n", __func__);
205 pn544_hci_i2c_enable_mode(phy, PN544_HCI_MODE);
212 static void pn544_hci_i2c_disable(void *phy_id)
214 struct pn544_i2c_phy *phy = phy_id;
216 gpio_set_value(phy->gpio_fw, 0);
217 gpio_set_value(phy->gpio_en, !phy->en_polarity);
218 usleep_range(10000, 15000);
220 gpio_set_value(phy->gpio_en, phy->en_polarity);
221 usleep_range(10000, 15000);
223 gpio_set_value(phy->gpio_en, !phy->en_polarity);
224 usleep_range(10000, 15000);
229 static void pn544_hci_i2c_add_len_crc(struct sk_buff *skb)
235 *skb_push(skb, 1) = len;
237 crc = crc_ccitt(0xffff, skb->data, skb->len);
239 *skb_put(skb, 1) = crc & 0xff;
240 *skb_put(skb, 1) = crc >> 8;
243 static void pn544_hci_i2c_remove_len_crc(struct sk_buff *skb)
245 skb_pull(skb, PN544_I2C_FRAME_HEADROOM);
246 skb_trim(skb, PN544_I2C_FRAME_TAILROOM);
250 * Writing a frame must not return the number of written bytes.
251 * It must return either zero for success, or <0 for error.
252 * In addition, it must not alter the skb
254 static int pn544_hci_i2c_write(void *phy_id, struct sk_buff *skb)
257 struct pn544_i2c_phy *phy = phy_id;
258 struct i2c_client *client = phy->i2c_dev;
260 if (phy->hard_fault != 0)
261 return phy->hard_fault;
263 usleep_range(3000, 6000);
265 pn544_hci_i2c_add_len_crc(skb);
267 I2C_DUMP_SKB("i2c frame written", skb);
269 r = i2c_master_send(client, skb->data, skb->len);
271 if (r == -EREMOTEIO) { /* Retry, chip was in standby */
272 usleep_range(6000, 10000);
273 r = i2c_master_send(client, skb->data, skb->len);
283 pn544_hci_i2c_remove_len_crc(skb);
288 static int check_crc(u8 *buf, int buflen)
294 crc = crc_ccitt(0xffff, buf, len - 2);
297 if (buf[len - 2] != (crc & 0xff) || buf[len - 1] != (crc >> 8)) {
298 pr_err("CRC error 0x%x != 0x%x 0x%x\n",
299 crc, buf[len - 1], buf[len - 2]);
300 pr_info("%s: BAD CRC\n", __func__);
301 print_hex_dump(KERN_DEBUG, "crc: ", DUMP_PREFIX_NONE,
302 16, 2, buf, buflen, false);
309 * Reads an shdlc frame and returns it in a newly allocated sk_buff. Guarantees
310 * that i2c bus will be flushed and that next read will start on a new frame.
311 * returned skb contains only LLC header and payload.
313 * -EREMOTEIO : i2c read error (fatal)
314 * -EBADMSG : frame was incorrect and discarded
315 * -ENOMEM : cannot allocate skb, frame dropped
317 static int pn544_hci_i2c_read(struct pn544_i2c_phy *phy, struct sk_buff **skb)
321 u8 tmp[PN544_HCI_I2C_LLC_MAX_SIZE - 1];
322 struct i2c_client *client = phy->i2c_dev;
324 r = i2c_master_recv(client, &len, 1);
326 nfc_err(&client->dev, "cannot read len byte\n");
330 if ((len < (PN544_HCI_I2C_LLC_MIN_SIZE - 1)) ||
331 (len > (PN544_HCI_I2C_LLC_MAX_SIZE - 1))) {
332 nfc_err(&client->dev, "invalid len byte\n");
337 *skb = alloc_skb(1 + len, GFP_KERNEL);
343 *skb_put(*skb, 1) = len;
345 r = i2c_master_recv(client, skb_put(*skb, len), len);
351 I2C_DUMP_SKB("i2c frame read", *skb);
353 r = check_crc((*skb)->data, (*skb)->len);
361 skb_trim(*skb, (*skb)->len - 2);
363 usleep_range(3000, 6000);
368 if (i2c_master_recv(client, tmp, sizeof(tmp)) < 0)
371 usleep_range(3000, 6000);
376 static int pn544_hci_i2c_fw_read_status(struct pn544_i2c_phy *phy)
379 struct pn544_i2c_fw_frame_response response;
380 struct i2c_client *client = phy->i2c_dev;
382 r = i2c_master_recv(client, (char *) &response, sizeof(response));
383 if (r != sizeof(response)) {
384 nfc_err(&client->dev, "cannot read fw status\n");
388 usleep_range(3000, 6000);
390 switch (response.status) {
393 case PN544_FW_CMD_RESULT_TIMEOUT:
395 case PN544_FW_CMD_RESULT_BAD_CRC:
397 case PN544_FW_CMD_RESULT_ACCESS_DENIED:
399 case PN544_FW_CMD_RESULT_PROTOCOL_ERROR:
401 case PN544_FW_CMD_RESULT_INVALID_PARAMETER:
403 case PN544_FW_CMD_RESULT_INVALID_LENGTH:
405 case PN544_FW_CMD_RESULT_WRITE_FAILED:
413 * Reads an shdlc frame from the chip. This is not as straightforward as it
414 * seems. There are cases where we could loose the frame start synchronization.
415 * The frame format is len-data-crc, and corruption can occur anywhere while
416 * transiting on i2c bus, such that we could read an invalid len.
417 * In order to recover synchronization with the next frame, we must be sure
418 * to read the real amount of data without using the len byte. We do this by
419 * assuming the following:
420 * - the chip will always present only one single complete frame on the bus
421 * before triggering the interrupt
422 * - the chip will not present a new frame until we have completely read
423 * the previous one (or until we have handled the interrupt).
424 * The tricky case is when we read a corrupted len that is less than the real
425 * len. We must detect this here in order to determine that we need to flush
426 * the bus. This is the reason why we check the crc here.
428 static irqreturn_t pn544_hci_i2c_irq_thread_fn(int irq, void *phy_id)
430 struct pn544_i2c_phy *phy = phy_id;
431 struct i2c_client *client;
432 struct sk_buff *skb = NULL;
435 if (!phy || irq != phy->i2c_dev->irq) {
440 client = phy->i2c_dev;
441 dev_dbg(&client->dev, "IRQ\n");
443 if (phy->hard_fault != 0)
446 if (phy->run_mode == PN544_FW_MODE) {
447 phy->fw_cmd_result = pn544_hci_i2c_fw_read_status(phy);
448 schedule_work(&phy->fw_work);
450 r = pn544_hci_i2c_read(phy, &skb);
451 if (r == -EREMOTEIO) {
454 nfc_hci_recv_frame(phy->hdev, NULL);
457 } else if ((r == -ENOMEM) || (r == -EBADMSG)) {
461 nfc_hci_recv_frame(phy->hdev, skb);
466 static struct nfc_phy_ops i2c_phy_ops = {
467 .write = pn544_hci_i2c_write,
468 .enable = pn544_hci_i2c_enable,
469 .disable = pn544_hci_i2c_disable,
472 static int pn544_hci_i2c_fw_download(void *phy_id, const char *firmware_name)
474 struct pn544_i2c_phy *phy = phy_id;
476 pr_info("Starting Firmware Download (%s)\n", firmware_name);
478 strcpy(phy->firmware_name, firmware_name);
480 phy->fw_work_state = FW_WORK_STATE_START;
482 schedule_work(&phy->fw_work);
487 static void pn544_hci_i2c_fw_work_complete(struct pn544_i2c_phy *phy,
490 pr_info("Firmware Download Complete, result=%d\n", result);
492 pn544_hci_i2c_disable(phy);
494 phy->fw_work_state = FW_WORK_STATE_IDLE;
497 release_firmware(phy->fw);
501 nfc_fw_download_done(phy->hdev->ndev, phy->firmware_name, (u32) -result);
504 static int pn544_hci_i2c_fw_write_cmd(struct i2c_client *client, u32 dest_addr,
505 const u8 *data, u16 datalen)
507 u8 frame[PN544_FW_I2C_MAX_PAYLOAD];
508 struct pn544_i2c_fw_frame_write *framep;
513 if (datalen > PN544_FW_I2C_WRITE_DATA_MAX_LEN)
514 datalen = PN544_FW_I2C_WRITE_DATA_MAX_LEN;
516 framep = (struct pn544_i2c_fw_frame_write *) frame;
518 params_len = sizeof(framep->be_dest_addr) +
519 sizeof(framep->be_datalen) + datalen;
520 framelen = params_len + sizeof(framep->cmd) +
521 sizeof(framep->be_length);
523 framep->cmd = PN544_FW_CMD_WRITE;
525 put_unaligned_be16(params_len, &framep->be_length);
527 framep->be_dest_addr[0] = (dest_addr & 0xff0000) >> 16;
528 framep->be_dest_addr[1] = (dest_addr & 0xff00) >> 8;
529 framep->be_dest_addr[2] = dest_addr & 0xff;
531 put_unaligned_be16(datalen, &framep->be_datalen);
533 memcpy(framep->data, data, datalen);
535 r = i2c_master_send(client, frame, framelen);
545 static int pn544_hci_i2c_fw_check_cmd(struct i2c_client *client, u32 start_addr,
546 const u8 *data, u16 datalen)
548 struct pn544_i2c_fw_frame_check frame;
552 /* calculate local crc for the data we want to check */
553 crc = crc_ccitt(0xffff, data, datalen);
555 frame.cmd = PN544_FW_CMD_CHECK;
557 put_unaligned_be16(sizeof(frame.be_start_addr) +
558 sizeof(frame.be_datalen) + sizeof(frame.be_crc),
561 /* tell the chip the memory region to which our crc applies */
562 frame.be_start_addr[0] = (start_addr & 0xff0000) >> 16;
563 frame.be_start_addr[1] = (start_addr & 0xff00) >> 8;
564 frame.be_start_addr[2] = start_addr & 0xff;
566 put_unaligned_be16(datalen, &frame.be_datalen);
569 * and give our local crc. Chip will calculate its own crc for the
570 * region and compare with ours.
572 put_unaligned_be16(crc, &frame.be_crc);
574 r = i2c_master_send(client, (const char *) &frame, sizeof(frame));
576 if (r == sizeof(frame))
584 static int pn544_hci_i2c_fw_write_chunk(struct pn544_i2c_phy *phy)
588 r = pn544_hci_i2c_fw_write_cmd(phy->i2c_dev,
589 phy->fw_blob_dest_addr + phy->fw_written,
590 phy->fw_blob_data + phy->fw_written,
591 phy->fw_blob_size - phy->fw_written);
595 phy->fw_written += r;
596 phy->fw_work_state = FW_WORK_STATE_WAIT_WRITE_ANSWER;
601 static void pn544_hci_i2c_fw_work(struct work_struct *work)
603 struct pn544_i2c_phy *phy = container_of(work, struct pn544_i2c_phy,
606 struct pn544_i2c_fw_blob *blob;
608 switch (phy->fw_work_state) {
609 case FW_WORK_STATE_START:
610 pn544_hci_i2c_enable_mode(phy, PN544_FW_MODE);
612 r = request_firmware(&phy->fw, phy->firmware_name,
615 goto exit_state_start;
617 blob = (struct pn544_i2c_fw_blob *) phy->fw->data;
618 phy->fw_blob_size = get_unaligned_be32(&blob->be_size);
619 phy->fw_blob_dest_addr = get_unaligned_be32(&blob->be_destaddr);
620 phy->fw_blob_data = blob->data;
623 r = pn544_hci_i2c_fw_write_chunk(phy);
627 pn544_hci_i2c_fw_work_complete(phy, r);
630 case FW_WORK_STATE_WAIT_WRITE_ANSWER:
631 r = phy->fw_cmd_result;
633 goto exit_state_wait_write_answer;
635 if (phy->fw_written == phy->fw_blob_size) {
636 r = pn544_hci_i2c_fw_check_cmd(phy->i2c_dev,
637 phy->fw_blob_dest_addr,
641 goto exit_state_wait_write_answer;
642 phy->fw_work_state = FW_WORK_STATE_WAIT_CHECK_ANSWER;
646 r = pn544_hci_i2c_fw_write_chunk(phy);
648 exit_state_wait_write_answer:
650 pn544_hci_i2c_fw_work_complete(phy, r);
653 case FW_WORK_STATE_WAIT_CHECK_ANSWER:
654 r = phy->fw_cmd_result;
656 goto exit_state_wait_check_answer;
658 blob = (struct pn544_i2c_fw_blob *) (phy->fw_blob_data +
660 phy->fw_blob_size = get_unaligned_be32(&blob->be_size);
661 if (phy->fw_blob_size != 0) {
662 phy->fw_blob_dest_addr =
663 get_unaligned_be32(&blob->be_destaddr);
664 phy->fw_blob_data = blob->data;
667 r = pn544_hci_i2c_fw_write_chunk(phy);
670 exit_state_wait_check_answer:
671 if (r < 0 || phy->fw_blob_size == 0)
672 pn544_hci_i2c_fw_work_complete(phy, r);
680 static int pn544_hci_i2c_probe(struct i2c_client *client,
681 const struct i2c_device_id *id)
683 struct pn544_i2c_phy *phy;
684 struct pn544_nfc_platform_data *pdata;
687 dev_dbg(&client->dev, "%s\n", __func__);
688 dev_dbg(&client->dev, "IRQ: %d\n", client->irq);
690 if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) {
691 nfc_err(&client->dev, "Need I2C_FUNC_I2C\n");
695 phy = devm_kzalloc(&client->dev, sizeof(struct pn544_i2c_phy),
698 nfc_err(&client->dev,
699 "Cannot allocate memory for pn544 i2c phy.\n");
703 INIT_WORK(&phy->fw_work, pn544_hci_i2c_fw_work);
704 phy->fw_work_state = FW_WORK_STATE_IDLE;
706 phy->i2c_dev = client;
707 i2c_set_clientdata(client, phy);
709 pdata = client->dev.platform_data;
711 nfc_err(&client->dev, "No platform data\n");
715 if (pdata->request_resources == NULL) {
716 nfc_err(&client->dev, "request_resources() missing\n");
720 r = pdata->request_resources(client);
722 nfc_err(&client->dev, "Cannot get platform resources\n");
726 phy->gpio_en = pdata->get_gpio(NFC_GPIO_ENABLE);
727 phy->gpio_fw = pdata->get_gpio(NFC_GPIO_FW_RESET);
728 phy->gpio_irq = pdata->get_gpio(NFC_GPIO_IRQ);
730 pn544_hci_i2c_platform_init(phy);
732 r = request_threaded_irq(client->irq, NULL, pn544_hci_i2c_irq_thread_fn,
733 IRQF_TRIGGER_RISING | IRQF_ONESHOT,
734 PN544_HCI_I2C_DRIVER_NAME, phy);
736 nfc_err(&client->dev, "Unable to register IRQ handler\n");
740 r = pn544_hci_probe(phy, &i2c_phy_ops, LLC_SHDLC_NAME,
741 PN544_I2C_FRAME_HEADROOM, PN544_I2C_FRAME_TAILROOM,
742 PN544_HCI_I2C_LLC_MAX_PAYLOAD,
743 pn544_hci_i2c_fw_download, &phy->hdev);
750 free_irq(client->irq, phy);
753 if (pdata->free_resources != NULL)
754 pdata->free_resources();
759 static int pn544_hci_i2c_remove(struct i2c_client *client)
761 struct pn544_i2c_phy *phy = i2c_get_clientdata(client);
762 struct pn544_nfc_platform_data *pdata = client->dev.platform_data;
764 dev_dbg(&client->dev, "%s\n", __func__);
766 cancel_work_sync(&phy->fw_work);
767 if (phy->fw_work_state != FW_WORK_STATE_IDLE)
768 pn544_hci_i2c_fw_work_complete(phy, -ENODEV);
770 pn544_hci_remove(phy->hdev);
773 pn544_hci_i2c_disable(phy);
775 free_irq(client->irq, phy);
776 if (pdata->free_resources)
777 pdata->free_resources();
782 static struct i2c_driver pn544_hci_i2c_driver = {
784 .name = PN544_HCI_I2C_DRIVER_NAME,
786 .probe = pn544_hci_i2c_probe,
787 .id_table = pn544_hci_i2c_id_table,
788 .remove = pn544_hci_i2c_remove,
791 module_i2c_driver(pn544_hci_i2c_driver);
793 MODULE_LICENSE("GPL");
794 MODULE_DESCRIPTION(DRIVER_DESC);