3 * Purpose: PCI Message Signaled Interrupt (MSI)
5 * Copyright (C) 2003-2004 Intel
6 * Copyright (C) Tom Long Nguyen (tom.l.nguyen@intel.com)
11 #include <linux/irq.h>
12 #include <linux/interrupt.h>
13 #include <linux/export.h>
14 #include <linux/ioport.h>
15 #include <linux/pci.h>
16 #include <linux/proc_fs.h>
17 #include <linux/msi.h>
18 #include <linux/smp.h>
19 #include <linux/errno.h>
21 #include <linux/slab.h>
25 static int pci_msi_enable = 1;
26 int pci_msi_ignore_mask;
28 #define msix_table_size(flags) ((flags & PCI_MSIX_FLAGS_QSIZE) + 1)
33 struct msi_controller * __weak pcibios_msi_controller(struct pci_dev *dev)
38 static struct msi_controller *pci_msi_controller(struct pci_dev *dev)
40 struct msi_controller *msi_ctrl = dev->bus->msi;
45 return pcibios_msi_controller(dev);
48 int __weak arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc)
50 struct msi_controller *chip = pci_msi_controller(dev);
53 if (!chip || !chip->setup_irq)
56 err = chip->setup_irq(chip, dev, desc);
60 irq_set_chip_data(desc->irq, chip);
65 void __weak arch_teardown_msi_irq(unsigned int irq)
67 struct msi_controller *chip = irq_get_chip_data(irq);
69 if (!chip || !chip->teardown_irq)
72 chip->teardown_irq(chip, irq);
75 int __weak arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
77 struct msi_desc *entry;
81 * If an architecture wants to support multiple MSI, it needs to
82 * override arch_setup_msi_irqs()
84 if (type == PCI_CAP_ID_MSI && nvec > 1)
87 list_for_each_entry(entry, &dev->msi_list, list) {
88 ret = arch_setup_msi_irq(dev, entry);
99 * We have a default implementation available as a separate non-weak
100 * function, as it is used by the Xen x86 PCI code
102 void default_teardown_msi_irqs(struct pci_dev *dev)
105 struct msi_desc *entry;
107 list_for_each_entry(entry, &dev->msi_list, list)
109 for (i = 0; i < entry->nvec_used; i++)
110 arch_teardown_msi_irq(entry->irq + i);
113 void __weak arch_teardown_msi_irqs(struct pci_dev *dev)
115 return default_teardown_msi_irqs(dev);
118 static void default_restore_msi_irq(struct pci_dev *dev, int irq)
120 struct msi_desc *entry;
123 if (dev->msix_enabled) {
124 list_for_each_entry(entry, &dev->msi_list, list) {
125 if (irq == entry->irq)
128 } else if (dev->msi_enabled) {
129 entry = irq_get_msi_desc(irq);
133 __pci_write_msi_msg(entry, &entry->msg);
136 void __weak arch_restore_msi_irqs(struct pci_dev *dev)
138 return default_restore_msi_irqs(dev);
141 static void msi_set_enable(struct pci_dev *dev, int enable)
145 pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control);
146 control &= ~PCI_MSI_FLAGS_ENABLE;
148 control |= PCI_MSI_FLAGS_ENABLE;
149 pci_write_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, control);
152 static void msix_clear_and_set_ctrl(struct pci_dev *dev, u16 clear, u16 set)
156 pci_read_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, &ctrl);
159 pci_write_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, ctrl);
162 static inline __attribute_const__ u32 msi_mask(unsigned x)
164 /* Don't shift by >= width of type */
167 return (1 << (1 << x)) - 1;
171 * PCI 2.3 does not specify mask bits for each MSI interrupt. Attempting to
172 * mask all MSI interrupts by clearing the MSI enable bit does not work
173 * reliably as devices without an INTx disable bit will then generate a
174 * level IRQ which will never be cleared.
176 u32 __msi_mask_irq(struct msi_desc *desc, u32 mask, u32 flag)
178 u32 mask_bits = desc->masked;
180 if (pci_msi_ignore_mask || !desc->msi_attrib.maskbit)
185 pci_write_config_dword(desc->dev, desc->mask_pos, mask_bits);
190 static void msi_mask_irq(struct msi_desc *desc, u32 mask, u32 flag)
192 desc->masked = __msi_mask_irq(desc, mask, flag);
196 * This internal function does not flush PCI writes to the device.
197 * All users must ensure that they read from the device before either
198 * assuming that the device state is up to date, or returning out of this
199 * file. This saves a few milliseconds when initialising devices with lots
200 * of MSI-X interrupts.
202 u32 __msix_mask_irq(struct msi_desc *desc, u32 flag)
204 u32 mask_bits = desc->masked;
205 unsigned offset = desc->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE +
206 PCI_MSIX_ENTRY_VECTOR_CTRL;
208 if (pci_msi_ignore_mask)
211 mask_bits &= ~PCI_MSIX_ENTRY_CTRL_MASKBIT;
213 mask_bits |= PCI_MSIX_ENTRY_CTRL_MASKBIT;
214 writel(mask_bits, desc->mask_base + offset);
219 static void msix_mask_irq(struct msi_desc *desc, u32 flag)
221 desc->masked = __msix_mask_irq(desc, flag);
224 static void msi_set_mask_bit(struct irq_data *data, u32 flag)
226 struct msi_desc *desc = irq_data_get_msi(data);
228 if (desc->msi_attrib.is_msix) {
229 msix_mask_irq(desc, flag);
230 readl(desc->mask_base); /* Flush write to device */
232 unsigned offset = data->irq - desc->irq;
233 msi_mask_irq(desc, 1 << offset, flag << offset);
237 void mask_msi_irq(struct irq_data *data)
239 msi_set_mask_bit(data, 1);
242 void unmask_msi_irq(struct irq_data *data)
244 msi_set_mask_bit(data, 0);
247 void default_restore_msi_irqs(struct pci_dev *dev)
249 struct msi_desc *entry;
251 list_for_each_entry(entry, &dev->msi_list, list)
252 default_restore_msi_irq(dev, entry->irq);
255 void __pci_read_msi_msg(struct msi_desc *entry, struct msi_msg *msg)
257 BUG_ON(entry->dev->current_state != PCI_D0);
259 if (entry->msi_attrib.is_msix) {
260 void __iomem *base = entry->mask_base +
261 entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE;
263 msg->address_lo = readl(base + PCI_MSIX_ENTRY_LOWER_ADDR);
264 msg->address_hi = readl(base + PCI_MSIX_ENTRY_UPPER_ADDR);
265 msg->data = readl(base + PCI_MSIX_ENTRY_DATA);
267 struct pci_dev *dev = entry->dev;
268 int pos = dev->msi_cap;
271 pci_read_config_dword(dev, pos + PCI_MSI_ADDRESS_LO,
273 if (entry->msi_attrib.is_64) {
274 pci_read_config_dword(dev, pos + PCI_MSI_ADDRESS_HI,
276 pci_read_config_word(dev, pos + PCI_MSI_DATA_64, &data);
279 pci_read_config_word(dev, pos + PCI_MSI_DATA_32, &data);
285 void __get_cached_msi_msg(struct msi_desc *entry, struct msi_msg *msg)
287 /* Assert that the cache is valid, assuming that
288 * valid messages are not all-zeroes. */
289 BUG_ON(!(entry->msg.address_hi | entry->msg.address_lo |
295 void get_cached_msi_msg(unsigned int irq, struct msi_msg *msg)
297 struct msi_desc *entry = irq_get_msi_desc(irq);
299 __get_cached_msi_msg(entry, msg);
301 EXPORT_SYMBOL_GPL(get_cached_msi_msg);
303 void __pci_write_msi_msg(struct msi_desc *entry, struct msi_msg *msg)
305 if (entry->dev->current_state != PCI_D0) {
306 /* Don't touch the hardware now */
307 } else if (entry->msi_attrib.is_msix) {
309 base = entry->mask_base +
310 entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE;
312 writel(msg->address_lo, base + PCI_MSIX_ENTRY_LOWER_ADDR);
313 writel(msg->address_hi, base + PCI_MSIX_ENTRY_UPPER_ADDR);
314 writel(msg->data, base + PCI_MSIX_ENTRY_DATA);
316 struct pci_dev *dev = entry->dev;
317 int pos = dev->msi_cap;
320 pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &msgctl);
321 msgctl &= ~PCI_MSI_FLAGS_QSIZE;
322 msgctl |= entry->msi_attrib.multiple << 4;
323 pci_write_config_word(dev, pos + PCI_MSI_FLAGS, msgctl);
325 pci_write_config_dword(dev, pos + PCI_MSI_ADDRESS_LO,
327 if (entry->msi_attrib.is_64) {
328 pci_write_config_dword(dev, pos + PCI_MSI_ADDRESS_HI,
330 pci_write_config_word(dev, pos + PCI_MSI_DATA_64,
333 pci_write_config_word(dev, pos + PCI_MSI_DATA_32,
340 void pci_write_msi_msg(unsigned int irq, struct msi_msg *msg)
342 struct msi_desc *entry = irq_get_msi_desc(irq);
344 __pci_write_msi_msg(entry, msg);
346 EXPORT_SYMBOL_GPL(pci_write_msi_msg);
348 static void free_msi_irqs(struct pci_dev *dev)
350 struct msi_desc *entry, *tmp;
351 struct attribute **msi_attrs;
352 struct device_attribute *dev_attr;
355 list_for_each_entry(entry, &dev->msi_list, list)
357 for (i = 0; i < entry->nvec_used; i++)
358 BUG_ON(irq_has_action(entry->irq + i));
360 arch_teardown_msi_irqs(dev);
362 list_for_each_entry_safe(entry, tmp, &dev->msi_list, list) {
363 if (entry->msi_attrib.is_msix) {
364 if (list_is_last(&entry->list, &dev->msi_list))
365 iounmap(entry->mask_base);
368 list_del(&entry->list);
372 if (dev->msi_irq_groups) {
373 sysfs_remove_groups(&dev->dev.kobj, dev->msi_irq_groups);
374 msi_attrs = dev->msi_irq_groups[0]->attrs;
375 while (msi_attrs[count]) {
376 dev_attr = container_of(msi_attrs[count],
377 struct device_attribute, attr);
378 kfree(dev_attr->attr.name);
383 kfree(dev->msi_irq_groups[0]);
384 kfree(dev->msi_irq_groups);
385 dev->msi_irq_groups = NULL;
389 static struct msi_desc *alloc_msi_entry(struct pci_dev *dev)
391 struct msi_desc *desc = kzalloc(sizeof(*desc), GFP_KERNEL);
395 INIT_LIST_HEAD(&desc->list);
401 static void pci_intx_for_msi(struct pci_dev *dev, int enable)
403 if (!(dev->dev_flags & PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG))
404 pci_intx(dev, enable);
407 static void __pci_restore_msi_state(struct pci_dev *dev)
410 struct msi_desc *entry;
412 if (!dev->msi_enabled)
415 entry = irq_get_msi_desc(dev->irq);
417 pci_intx_for_msi(dev, 0);
418 msi_set_enable(dev, 0);
419 arch_restore_msi_irqs(dev);
421 pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control);
422 msi_mask_irq(entry, msi_mask(entry->msi_attrib.multi_cap),
424 control &= ~PCI_MSI_FLAGS_QSIZE;
425 control |= (entry->msi_attrib.multiple << 4) | PCI_MSI_FLAGS_ENABLE;
426 pci_write_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, control);
429 static void __pci_restore_msix_state(struct pci_dev *dev)
431 struct msi_desc *entry;
433 if (!dev->msix_enabled)
435 BUG_ON(list_empty(&dev->msi_list));
437 /* route the table */
438 pci_intx_for_msi(dev, 0);
439 msix_clear_and_set_ctrl(dev, 0,
440 PCI_MSIX_FLAGS_ENABLE | PCI_MSIX_FLAGS_MASKALL);
442 arch_restore_msi_irqs(dev);
443 list_for_each_entry(entry, &dev->msi_list, list)
444 msix_mask_irq(entry, entry->masked);
446 msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_MASKALL, 0);
449 void pci_restore_msi_state(struct pci_dev *dev)
451 __pci_restore_msi_state(dev);
452 __pci_restore_msix_state(dev);
454 EXPORT_SYMBOL_GPL(pci_restore_msi_state);
456 static ssize_t msi_mode_show(struct device *dev, struct device_attribute *attr,
459 struct msi_desc *entry;
463 retval = kstrtoul(attr->attr.name, 10, &irq);
467 entry = irq_get_msi_desc(irq);
469 return sprintf(buf, "%s\n",
470 entry->msi_attrib.is_msix ? "msix" : "msi");
475 static int populate_msi_sysfs(struct pci_dev *pdev)
477 struct attribute **msi_attrs;
478 struct attribute *msi_attr;
479 struct device_attribute *msi_dev_attr;
480 struct attribute_group *msi_irq_group;
481 const struct attribute_group **msi_irq_groups;
482 struct msi_desc *entry;
487 /* Determine how many msi entries we have */
488 list_for_each_entry(entry, &pdev->msi_list, list)
493 /* Dynamically create the MSI attributes for the PCI device */
494 msi_attrs = kzalloc(sizeof(void *) * (num_msi + 1), GFP_KERNEL);
497 list_for_each_entry(entry, &pdev->msi_list, list) {
498 msi_dev_attr = kzalloc(sizeof(*msi_dev_attr), GFP_KERNEL);
501 msi_attrs[count] = &msi_dev_attr->attr;
503 sysfs_attr_init(&msi_dev_attr->attr);
504 msi_dev_attr->attr.name = kasprintf(GFP_KERNEL, "%d",
506 if (!msi_dev_attr->attr.name)
508 msi_dev_attr->attr.mode = S_IRUGO;
509 msi_dev_attr->show = msi_mode_show;
513 msi_irq_group = kzalloc(sizeof(*msi_irq_group), GFP_KERNEL);
516 msi_irq_group->name = "msi_irqs";
517 msi_irq_group->attrs = msi_attrs;
519 msi_irq_groups = kzalloc(sizeof(void *) * 2, GFP_KERNEL);
521 goto error_irq_group;
522 msi_irq_groups[0] = msi_irq_group;
524 ret = sysfs_create_groups(&pdev->dev.kobj, msi_irq_groups);
526 goto error_irq_groups;
527 pdev->msi_irq_groups = msi_irq_groups;
532 kfree(msi_irq_groups);
534 kfree(msi_irq_group);
537 msi_attr = msi_attrs[count];
539 msi_dev_attr = container_of(msi_attr, struct device_attribute, attr);
540 kfree(msi_attr->name);
543 msi_attr = msi_attrs[count];
549 static struct msi_desc *msi_setup_entry(struct pci_dev *dev, int nvec)
552 struct msi_desc *entry;
554 /* MSI Entry Initialization */
555 entry = alloc_msi_entry(dev);
559 pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control);
561 entry->msi_attrib.is_msix = 0;
562 entry->msi_attrib.is_64 = !!(control & PCI_MSI_FLAGS_64BIT);
563 entry->msi_attrib.entry_nr = 0;
564 entry->msi_attrib.maskbit = !!(control & PCI_MSI_FLAGS_MASKBIT);
565 entry->msi_attrib.default_irq = dev->irq; /* Save IOAPIC IRQ */
566 entry->msi_attrib.multi_cap = (control & PCI_MSI_FLAGS_QMASK) >> 1;
567 entry->msi_attrib.multiple = ilog2(__roundup_pow_of_two(nvec));
568 entry->nvec_used = nvec;
570 if (control & PCI_MSI_FLAGS_64BIT)
571 entry->mask_pos = dev->msi_cap + PCI_MSI_MASK_64;
573 entry->mask_pos = dev->msi_cap + PCI_MSI_MASK_32;
575 /* Save the initial mask status */
576 if (entry->msi_attrib.maskbit)
577 pci_read_config_dword(dev, entry->mask_pos, &entry->masked);
583 * msi_capability_init - configure device's MSI capability structure
584 * @dev: pointer to the pci_dev data structure of MSI device function
585 * @nvec: number of interrupts to allocate
587 * Setup the MSI capability structure of the device with the requested
588 * number of interrupts. A return value of zero indicates the successful
589 * setup of an entry with the new MSI irq. A negative return value indicates
590 * an error, and a positive return value indicates the number of interrupts
591 * which could have been allocated.
593 static int msi_capability_init(struct pci_dev *dev, int nvec)
595 struct msi_desc *entry;
599 msi_set_enable(dev, 0); /* Disable MSI during set up */
601 entry = msi_setup_entry(dev, nvec);
605 /* All MSIs are unmasked by default, Mask them all */
606 mask = msi_mask(entry->msi_attrib.multi_cap);
607 msi_mask_irq(entry, mask, mask);
609 list_add_tail(&entry->list, &dev->msi_list);
611 /* Configure MSI capability structure */
612 ret = arch_setup_msi_irqs(dev, nvec, PCI_CAP_ID_MSI);
614 msi_mask_irq(entry, mask, ~mask);
619 ret = populate_msi_sysfs(dev);
621 msi_mask_irq(entry, mask, ~mask);
626 /* Set MSI enabled bits */
627 pci_intx_for_msi(dev, 0);
628 msi_set_enable(dev, 1);
629 dev->msi_enabled = 1;
631 dev->irq = entry->irq;
635 static void __iomem *msix_map_region(struct pci_dev *dev, unsigned nr_entries)
637 resource_size_t phys_addr;
641 pci_read_config_dword(dev, dev->msix_cap + PCI_MSIX_TABLE,
643 bir = (u8)(table_offset & PCI_MSIX_TABLE_BIR);
644 table_offset &= PCI_MSIX_TABLE_OFFSET;
645 phys_addr = pci_resource_start(dev, bir) + table_offset;
647 return ioremap_nocache(phys_addr, nr_entries * PCI_MSIX_ENTRY_SIZE);
650 static int msix_setup_entries(struct pci_dev *dev, void __iomem *base,
651 struct msix_entry *entries, int nvec)
653 struct msi_desc *entry;
656 for (i = 0; i < nvec; i++) {
657 entry = alloc_msi_entry(dev);
663 /* No enough memory. Don't try again */
667 entry->msi_attrib.is_msix = 1;
668 entry->msi_attrib.is_64 = 1;
669 entry->msi_attrib.entry_nr = entries[i].entry;
670 entry->msi_attrib.default_irq = dev->irq;
671 entry->mask_base = base;
672 entry->nvec_used = 1;
674 list_add_tail(&entry->list, &dev->msi_list);
680 static void msix_program_entries(struct pci_dev *dev,
681 struct msix_entry *entries)
683 struct msi_desc *entry;
686 list_for_each_entry(entry, &dev->msi_list, list) {
687 int offset = entries[i].entry * PCI_MSIX_ENTRY_SIZE +
688 PCI_MSIX_ENTRY_VECTOR_CTRL;
690 entries[i].vector = entry->irq;
691 entry->masked = readl(entry->mask_base + offset);
692 msix_mask_irq(entry, 1);
698 * msix_capability_init - configure device's MSI-X capability
699 * @dev: pointer to the pci_dev data structure of MSI-X device function
700 * @entries: pointer to an array of struct msix_entry entries
701 * @nvec: number of @entries
703 * Setup the MSI-X capability structure of device function with a
704 * single MSI-X irq. A return of zero indicates the successful setup of
705 * requested MSI-X entries with allocated irqs or non-zero for otherwise.
707 static int msix_capability_init(struct pci_dev *dev,
708 struct msix_entry *entries, int nvec)
714 /* Ensure MSI-X is disabled while it is set up */
715 msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_ENABLE, 0);
717 pci_read_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, &control);
718 /* Request & Map MSI-X table region */
719 base = msix_map_region(dev, msix_table_size(control));
723 ret = msix_setup_entries(dev, base, entries, nvec);
727 ret = arch_setup_msi_irqs(dev, nvec, PCI_CAP_ID_MSIX);
732 * Some devices require MSI-X to be enabled before we can touch the
733 * MSI-X registers. We need to mask all the vectors to prevent
734 * interrupts coming in before they're fully set up.
736 msix_clear_and_set_ctrl(dev, 0,
737 PCI_MSIX_FLAGS_MASKALL | PCI_MSIX_FLAGS_ENABLE);
739 msix_program_entries(dev, entries);
741 ret = populate_msi_sysfs(dev);
745 /* Set MSI-X enabled bits and unmask the function */
746 pci_intx_for_msi(dev, 0);
747 dev->msix_enabled = 1;
749 msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_MASKALL, 0);
756 * If we had some success, report the number of irqs
757 * we succeeded in setting up.
759 struct msi_desc *entry;
762 list_for_each_entry(entry, &dev->msi_list, list) {
777 * pci_msi_supported - check whether MSI may be enabled on a device
778 * @dev: pointer to the pci_dev data structure of MSI device function
779 * @nvec: how many MSIs have been requested ?
781 * Look at global flags, the device itself, and its parent buses
782 * to determine if MSI/-X are supported for the device. If MSI/-X is
783 * supported return 1, else return 0.
785 static int pci_msi_supported(struct pci_dev *dev, int nvec)
789 /* MSI must be globally enabled and supported by the device */
793 if (!dev || dev->no_msi || dev->current_state != PCI_D0)
797 * You can't ask to have 0 or less MSIs configured.
799 * b) the list manipulation code assumes nvec >= 1.
805 * Any bridge which does NOT route MSI transactions from its
806 * secondary bus to its primary bus must set NO_MSI flag on
807 * the secondary pci_bus.
808 * We expect only arch-specific PCI host bus controller driver
809 * or quirks for specific PCI bridges to be setting NO_MSI.
811 for (bus = dev->bus; bus; bus = bus->parent)
812 if (bus->bus_flags & PCI_BUS_FLAGS_NO_MSI)
819 * pci_msi_vec_count - Return the number of MSI vectors a device can send
820 * @dev: device to report about
822 * This function returns the number of MSI vectors a device requested via
823 * Multiple Message Capable register. It returns a negative errno if the
824 * device is not capable sending MSI interrupts. Otherwise, the call succeeds
825 * and returns a power of two, up to a maximum of 2^5 (32), according to the
828 int pci_msi_vec_count(struct pci_dev *dev)
836 pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &msgctl);
837 ret = 1 << ((msgctl & PCI_MSI_FLAGS_QMASK) >> 1);
841 EXPORT_SYMBOL(pci_msi_vec_count);
843 void pci_msi_shutdown(struct pci_dev *dev)
845 struct msi_desc *desc;
848 if (!pci_msi_enable || !dev || !dev->msi_enabled)
851 BUG_ON(list_empty(&dev->msi_list));
852 desc = list_first_entry(&dev->msi_list, struct msi_desc, list);
854 msi_set_enable(dev, 0);
855 pci_intx_for_msi(dev, 1);
856 dev->msi_enabled = 0;
858 /* Return the device with MSI unmasked as initial states */
859 mask = msi_mask(desc->msi_attrib.multi_cap);
860 /* Keep cached state to be restored */
861 __msi_mask_irq(desc, mask, ~mask);
863 /* Restore dev->irq to its default pin-assertion irq */
864 dev->irq = desc->msi_attrib.default_irq;
867 void pci_disable_msi(struct pci_dev *dev)
869 if (!pci_msi_enable || !dev || !dev->msi_enabled)
872 pci_msi_shutdown(dev);
875 EXPORT_SYMBOL(pci_disable_msi);
878 * pci_msix_vec_count - return the number of device's MSI-X table entries
879 * @dev: pointer to the pci_dev data structure of MSI-X device function
880 * This function returns the number of device's MSI-X table entries and
881 * therefore the number of MSI-X vectors device is capable of sending.
882 * It returns a negative errno if the device is not capable of sending MSI-X
885 int pci_msix_vec_count(struct pci_dev *dev)
892 pci_read_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, &control);
893 return msix_table_size(control);
895 EXPORT_SYMBOL(pci_msix_vec_count);
898 * pci_enable_msix - configure device's MSI-X capability structure
899 * @dev: pointer to the pci_dev data structure of MSI-X device function
900 * @entries: pointer to an array of MSI-X entries
901 * @nvec: number of MSI-X irqs requested for allocation by device driver
903 * Setup the MSI-X capability structure of device function with the number
904 * of requested irqs upon its software driver call to request for
905 * MSI-X mode enabled on its hardware device function. A return of zero
906 * indicates the successful configuration of MSI-X capability structure
907 * with new allocated MSI-X irqs. A return of < 0 indicates a failure.
908 * Or a return of > 0 indicates that driver request is exceeding the number
909 * of irqs or MSI-X vectors available. Driver should use the returned value to
910 * re-send its request.
912 int pci_enable_msix(struct pci_dev *dev, struct msix_entry *entries, int nvec)
917 if (!pci_msi_supported(dev, nvec))
923 nr_entries = pci_msix_vec_count(dev);
926 if (nvec > nr_entries)
929 /* Check for any invalid entries */
930 for (i = 0; i < nvec; i++) {
931 if (entries[i].entry >= nr_entries)
932 return -EINVAL; /* invalid entry */
933 for (j = i + 1; j < nvec; j++) {
934 if (entries[i].entry == entries[j].entry)
935 return -EINVAL; /* duplicate entry */
938 WARN_ON(!!dev->msix_enabled);
940 /* Check whether driver already requested for MSI irq */
941 if (dev->msi_enabled) {
942 dev_info(&dev->dev, "can't enable MSI-X (MSI IRQ already assigned)\n");
945 return msix_capability_init(dev, entries, nvec);
947 EXPORT_SYMBOL(pci_enable_msix);
949 void pci_msix_shutdown(struct pci_dev *dev)
951 struct msi_desc *entry;
953 if (!pci_msi_enable || !dev || !dev->msix_enabled)
956 /* Return the device with MSI-X masked as initial states */
957 list_for_each_entry(entry, &dev->msi_list, list) {
958 /* Keep cached states to be restored */
959 __msix_mask_irq(entry, 1);
962 msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_ENABLE, 0);
963 pci_intx_for_msi(dev, 1);
964 dev->msix_enabled = 0;
967 void pci_disable_msix(struct pci_dev *dev)
969 if (!pci_msi_enable || !dev || !dev->msix_enabled)
972 pci_msix_shutdown(dev);
975 EXPORT_SYMBOL(pci_disable_msix);
977 void pci_no_msi(void)
983 * pci_msi_enabled - is MSI enabled?
985 * Returns true if MSI has not been disabled by the command-line option
988 int pci_msi_enabled(void)
990 return pci_msi_enable;
992 EXPORT_SYMBOL(pci_msi_enabled);
994 void pci_msi_init_pci_dev(struct pci_dev *dev)
996 INIT_LIST_HEAD(&dev->msi_list);
998 /* Disable the msi hardware to avoid screaming interrupts
999 * during boot. This is the power on reset default so
1000 * usually this should be a noop.
1002 dev->msi_cap = pci_find_capability(dev, PCI_CAP_ID_MSI);
1004 msi_set_enable(dev, 0);
1006 dev->msix_cap = pci_find_capability(dev, PCI_CAP_ID_MSIX);
1008 msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_ENABLE, 0);
1012 * pci_enable_msi_range - configure device's MSI capability structure
1013 * @dev: device to configure
1014 * @minvec: minimal number of interrupts to configure
1015 * @maxvec: maximum number of interrupts to configure
1017 * This function tries to allocate a maximum possible number of interrupts in a
1018 * range between @minvec and @maxvec. It returns a negative errno if an error
1019 * occurs. If it succeeds, it returns the actual number of interrupts allocated
1020 * and updates the @dev's irq member to the lowest new interrupt number;
1021 * the other interrupt numbers allocated to this device are consecutive.
1023 int pci_enable_msi_range(struct pci_dev *dev, int minvec, int maxvec)
1028 if (!pci_msi_supported(dev, minvec))
1031 WARN_ON(!!dev->msi_enabled);
1033 /* Check whether driver already requested MSI-X irqs */
1034 if (dev->msix_enabled) {
1036 "can't enable MSI (MSI-X already enabled)\n");
1040 if (maxvec < minvec)
1043 nvec = pci_msi_vec_count(dev);
1046 else if (nvec < minvec)
1048 else if (nvec > maxvec)
1052 rc = msi_capability_init(dev, nvec);
1055 } else if (rc > 0) {
1064 EXPORT_SYMBOL(pci_enable_msi_range);
1067 * pci_enable_msix_range - configure device's MSI-X capability structure
1068 * @dev: pointer to the pci_dev data structure of MSI-X device function
1069 * @entries: pointer to an array of MSI-X entries
1070 * @minvec: minimum number of MSI-X irqs requested
1071 * @maxvec: maximum number of MSI-X irqs requested
1073 * Setup the MSI-X capability structure of device function with a maximum
1074 * possible number of interrupts in the range between @minvec and @maxvec
1075 * upon its software driver call to request for MSI-X mode enabled on its
1076 * hardware device function. It returns a negative errno if an error occurs.
1077 * If it succeeds, it returns the actual number of interrupts allocated and
1078 * indicates the successful configuration of MSI-X capability structure
1079 * with new allocated MSI-X interrupts.
1081 int pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries,
1082 int minvec, int maxvec)
1087 if (maxvec < minvec)
1091 rc = pci_enable_msix(dev, entries, nvec);
1094 } else if (rc > 0) {
1103 EXPORT_SYMBOL(pci_enable_msix_range);