2 * PCI Bus Services, see include/linux/pci.h for further explanation.
4 * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter,
7 * Copyright 1997 -- 2000 Martin Mares <mj@ucw.cz>
10 #include <linux/acpi.h>
11 #include <linux/kernel.h>
12 #include <linux/delay.h>
13 #include <linux/dmi.h>
14 #include <linux/init.h>
16 #include <linux/of_pci.h>
17 #include <linux/pci.h>
19 #include <linux/slab.h>
20 #include <linux/module.h>
21 #include <linux/spinlock.h>
22 #include <linux/string.h>
23 #include <linux/log2.h>
24 #include <linux/pci-aspm.h>
25 #include <linux/pm_wakeup.h>
26 #include <linux/interrupt.h>
27 #include <linux/device.h>
28 #include <linux/pm_runtime.h>
29 #include <linux/pci_hotplug.h>
30 #include <linux/vmalloc.h>
31 #include <asm/setup.h>
33 #include <linux/aer.h>
36 const char *pci_power_names[] = {
37 "error", "D0", "D1", "D2", "D3hot", "D3cold", "unknown",
39 EXPORT_SYMBOL_GPL(pci_power_names);
41 int isa_dma_bridge_buggy;
42 EXPORT_SYMBOL(isa_dma_bridge_buggy);
45 EXPORT_SYMBOL(pci_pci_problems);
47 unsigned int pci_pm_d3_delay;
49 static void pci_pme_list_scan(struct work_struct *work);
51 static LIST_HEAD(pci_pme_list);
52 static DEFINE_MUTEX(pci_pme_list_mutex);
53 static DECLARE_DELAYED_WORK(pci_pme_work, pci_pme_list_scan);
55 struct pci_pme_device {
56 struct list_head list;
60 #define PME_TIMEOUT 1000 /* How long between PME checks */
62 static void pci_dev_d3_sleep(struct pci_dev *dev)
64 unsigned int delay = dev->d3_delay;
66 if (delay < pci_pm_d3_delay)
67 delay = pci_pm_d3_delay;
72 #ifdef CONFIG_PCI_DOMAINS
73 int pci_domains_supported = 1;
76 #define DEFAULT_CARDBUS_IO_SIZE (256)
77 #define DEFAULT_CARDBUS_MEM_SIZE (64*1024*1024)
78 /* pci=cbmemsize=nnM,cbiosize=nn can override this */
79 unsigned long pci_cardbus_io_size = DEFAULT_CARDBUS_IO_SIZE;
80 unsigned long pci_cardbus_mem_size = DEFAULT_CARDBUS_MEM_SIZE;
82 #define DEFAULT_HOTPLUG_IO_SIZE (256)
83 #define DEFAULT_HOTPLUG_MEM_SIZE (2*1024*1024)
84 /* pci=hpmemsize=nnM,hpiosize=nn can override this */
85 unsigned long pci_hotplug_io_size = DEFAULT_HOTPLUG_IO_SIZE;
86 unsigned long pci_hotplug_mem_size = DEFAULT_HOTPLUG_MEM_SIZE;
88 #define DEFAULT_HOTPLUG_BUS_SIZE 1
89 unsigned long pci_hotplug_bus_size = DEFAULT_HOTPLUG_BUS_SIZE;
91 enum pcie_bus_config_types pcie_bus_config = PCIE_BUS_DEFAULT;
94 * The default CLS is used if arch didn't set CLS explicitly and not
95 * all pci devices agree on the same value. Arch can override either
96 * the dfl or actual value as it sees fit. Don't forget this is
97 * measured in 32-bit words, not bytes.
99 u8 pci_dfl_cache_line_size = L1_CACHE_BYTES >> 2;
100 u8 pci_cache_line_size;
103 * If we set up a device for bus mastering, we need to check the latency
104 * timer as certain BIOSes forget to set it properly.
106 unsigned int pcibios_max_latency = 255;
108 /* If set, the PCIe ARI capability will not be used. */
109 static bool pcie_ari_disabled;
111 /* Disable bridge_d3 for all PCIe ports */
112 static bool pci_bridge_d3_disable;
113 /* Force bridge_d3 for all PCIe ports */
114 static bool pci_bridge_d3_force;
116 static int __init pcie_port_pm_setup(char *str)
118 if (!strcmp(str, "off"))
119 pci_bridge_d3_disable = true;
120 else if (!strcmp(str, "force"))
121 pci_bridge_d3_force = true;
124 __setup("pcie_port_pm=", pcie_port_pm_setup);
127 * pci_bus_max_busnr - returns maximum PCI bus number of given bus' children
128 * @bus: pointer to PCI bus structure to search
130 * Given a PCI bus, returns the highest PCI bus number present in the set
131 * including the given PCI bus and its list of child PCI buses.
133 unsigned char pci_bus_max_busnr(struct pci_bus *bus)
136 unsigned char max, n;
138 max = bus->busn_res.end;
139 list_for_each_entry(tmp, &bus->children, node) {
140 n = pci_bus_max_busnr(tmp);
146 EXPORT_SYMBOL_GPL(pci_bus_max_busnr);
148 #ifdef CONFIG_HAS_IOMEM
149 void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar)
151 struct resource *res = &pdev->resource[bar];
154 * Make sure the BAR is actually a memory resource, not an IO resource
156 if (res->flags & IORESOURCE_UNSET || !(res->flags & IORESOURCE_MEM)) {
157 dev_warn(&pdev->dev, "can't ioremap BAR %d: %pR\n", bar, res);
160 return ioremap_nocache(res->start, resource_size(res));
162 EXPORT_SYMBOL_GPL(pci_ioremap_bar);
164 void __iomem *pci_ioremap_wc_bar(struct pci_dev *pdev, int bar)
167 * Make sure the BAR is actually a memory resource, not an IO resource
169 if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) {
173 return ioremap_wc(pci_resource_start(pdev, bar),
174 pci_resource_len(pdev, bar));
176 EXPORT_SYMBOL_GPL(pci_ioremap_wc_bar);
180 static int __pci_find_next_cap_ttl(struct pci_bus *bus, unsigned int devfn,
181 u8 pos, int cap, int *ttl)
186 pci_bus_read_config_byte(bus, devfn, pos, &pos);
192 pci_bus_read_config_word(bus, devfn, pos, &ent);
204 static int __pci_find_next_cap(struct pci_bus *bus, unsigned int devfn,
207 int ttl = PCI_FIND_CAP_TTL;
209 return __pci_find_next_cap_ttl(bus, devfn, pos, cap, &ttl);
212 int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap)
214 return __pci_find_next_cap(dev->bus, dev->devfn,
215 pos + PCI_CAP_LIST_NEXT, cap);
217 EXPORT_SYMBOL_GPL(pci_find_next_capability);
219 static int __pci_bus_find_cap_start(struct pci_bus *bus,
220 unsigned int devfn, u8 hdr_type)
224 pci_bus_read_config_word(bus, devfn, PCI_STATUS, &status);
225 if (!(status & PCI_STATUS_CAP_LIST))
229 case PCI_HEADER_TYPE_NORMAL:
230 case PCI_HEADER_TYPE_BRIDGE:
231 return PCI_CAPABILITY_LIST;
232 case PCI_HEADER_TYPE_CARDBUS:
233 return PCI_CB_CAPABILITY_LIST;
240 * pci_find_capability - query for devices' capabilities
241 * @dev: PCI device to query
242 * @cap: capability code
244 * Tell if a device supports a given PCI capability.
245 * Returns the address of the requested capability structure within the
246 * device's PCI configuration space or 0 in case the device does not
247 * support it. Possible values for @cap:
249 * %PCI_CAP_ID_PM Power Management
250 * %PCI_CAP_ID_AGP Accelerated Graphics Port
251 * %PCI_CAP_ID_VPD Vital Product Data
252 * %PCI_CAP_ID_SLOTID Slot Identification
253 * %PCI_CAP_ID_MSI Message Signalled Interrupts
254 * %PCI_CAP_ID_CHSWP CompactPCI HotSwap
255 * %PCI_CAP_ID_PCIX PCI-X
256 * %PCI_CAP_ID_EXP PCI Express
258 int pci_find_capability(struct pci_dev *dev, int cap)
262 pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type);
264 pos = __pci_find_next_cap(dev->bus, dev->devfn, pos, cap);
268 EXPORT_SYMBOL(pci_find_capability);
271 * pci_bus_find_capability - query for devices' capabilities
272 * @bus: the PCI bus to query
273 * @devfn: PCI device to query
274 * @cap: capability code
276 * Like pci_find_capability() but works for pci devices that do not have a
277 * pci_dev structure set up yet.
279 * Returns the address of the requested capability structure within the
280 * device's PCI configuration space or 0 in case the device does not
283 int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap)
288 pci_bus_read_config_byte(bus, devfn, PCI_HEADER_TYPE, &hdr_type);
290 pos = __pci_bus_find_cap_start(bus, devfn, hdr_type & 0x7f);
292 pos = __pci_find_next_cap(bus, devfn, pos, cap);
296 EXPORT_SYMBOL(pci_bus_find_capability);
299 * pci_find_next_ext_capability - Find an extended capability
300 * @dev: PCI device to query
301 * @start: address at which to start looking (0 to start at beginning of list)
302 * @cap: capability code
304 * Returns the address of the next matching extended capability structure
305 * within the device's PCI configuration space or 0 if the device does
306 * not support it. Some capabilities can occur several times, e.g., the
307 * vendor-specific capability, and this provides a way to find them all.
309 int pci_find_next_ext_capability(struct pci_dev *dev, int start, int cap)
313 int pos = PCI_CFG_SPACE_SIZE;
315 /* minimum 8 bytes per capability */
316 ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8;
318 if (dev->cfg_size <= PCI_CFG_SPACE_SIZE)
324 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
328 * If we have no capabilities, this is indicated by cap ID,
329 * cap version and next pointer all being 0.
335 if (PCI_EXT_CAP_ID(header) == cap && pos != start)
338 pos = PCI_EXT_CAP_NEXT(header);
339 if (pos < PCI_CFG_SPACE_SIZE)
342 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
348 EXPORT_SYMBOL_GPL(pci_find_next_ext_capability);
351 * pci_find_ext_capability - Find an extended capability
352 * @dev: PCI device to query
353 * @cap: capability code
355 * Returns the address of the requested extended capability structure
356 * within the device's PCI configuration space or 0 if the device does
357 * not support it. Possible values for @cap:
359 * %PCI_EXT_CAP_ID_ERR Advanced Error Reporting
360 * %PCI_EXT_CAP_ID_VC Virtual Channel
361 * %PCI_EXT_CAP_ID_DSN Device Serial Number
362 * %PCI_EXT_CAP_ID_PWR Power Budgeting
364 int pci_find_ext_capability(struct pci_dev *dev, int cap)
366 return pci_find_next_ext_capability(dev, 0, cap);
368 EXPORT_SYMBOL_GPL(pci_find_ext_capability);
370 static int __pci_find_next_ht_cap(struct pci_dev *dev, int pos, int ht_cap)
372 int rc, ttl = PCI_FIND_CAP_TTL;
375 if (ht_cap == HT_CAPTYPE_SLAVE || ht_cap == HT_CAPTYPE_HOST)
376 mask = HT_3BIT_CAP_MASK;
378 mask = HT_5BIT_CAP_MASK;
380 pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn, pos,
381 PCI_CAP_ID_HT, &ttl);
383 rc = pci_read_config_byte(dev, pos + 3, &cap);
384 if (rc != PCIBIOS_SUCCESSFUL)
387 if ((cap & mask) == ht_cap)
390 pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn,
391 pos + PCI_CAP_LIST_NEXT,
392 PCI_CAP_ID_HT, &ttl);
398 * pci_find_next_ht_capability - query a device's Hypertransport capabilities
399 * @dev: PCI device to query
400 * @pos: Position from which to continue searching
401 * @ht_cap: Hypertransport capability code
403 * To be used in conjunction with pci_find_ht_capability() to search for
404 * all capabilities matching @ht_cap. @pos should always be a value returned
405 * from pci_find_ht_capability().
407 * NB. To be 100% safe against broken PCI devices, the caller should take
408 * steps to avoid an infinite loop.
410 int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap)
412 return __pci_find_next_ht_cap(dev, pos + PCI_CAP_LIST_NEXT, ht_cap);
414 EXPORT_SYMBOL_GPL(pci_find_next_ht_capability);
417 * pci_find_ht_capability - query a device's Hypertransport capabilities
418 * @dev: PCI device to query
419 * @ht_cap: Hypertransport capability code
421 * Tell if a device supports a given Hypertransport capability.
422 * Returns an address within the device's PCI configuration space
423 * or 0 in case the device does not support the request capability.
424 * The address points to the PCI capability, of type PCI_CAP_ID_HT,
425 * which has a Hypertransport capability matching @ht_cap.
427 int pci_find_ht_capability(struct pci_dev *dev, int ht_cap)
431 pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type);
433 pos = __pci_find_next_ht_cap(dev, pos, ht_cap);
437 EXPORT_SYMBOL_GPL(pci_find_ht_capability);
440 * pci_find_parent_resource - return resource region of parent bus of given region
441 * @dev: PCI device structure contains resources to be searched
442 * @res: child resource record for which parent is sought
444 * For given resource region of given device, return the resource
445 * region of parent bus the given region is contained in.
447 struct resource *pci_find_parent_resource(const struct pci_dev *dev,
448 struct resource *res)
450 const struct pci_bus *bus = dev->bus;
454 pci_bus_for_each_resource(bus, r, i) {
457 if (res->start && resource_contains(r, res)) {
460 * If the window is prefetchable but the BAR is
461 * not, the allocator made a mistake.
463 if (r->flags & IORESOURCE_PREFETCH &&
464 !(res->flags & IORESOURCE_PREFETCH))
468 * If we're below a transparent bridge, there may
469 * be both a positively-decoded aperture and a
470 * subtractively-decoded region that contain the BAR.
471 * We want the positively-decoded one, so this depends
472 * on pci_bus_for_each_resource() giving us those
480 EXPORT_SYMBOL(pci_find_parent_resource);
483 * pci_find_resource - Return matching PCI device resource
484 * @dev: PCI device to query
485 * @res: Resource to look for
487 * Goes over standard PCI resources (BARs) and checks if the given resource
488 * is partially or fully contained in any of them. In that case the
489 * matching resource is returned, %NULL otherwise.
491 struct resource *pci_find_resource(struct pci_dev *dev, struct resource *res)
495 for (i = 0; i < PCI_ROM_RESOURCE; i++) {
496 struct resource *r = &dev->resource[i];
498 if (r->start && resource_contains(r, res))
504 EXPORT_SYMBOL(pci_find_resource);
507 * pci_find_pcie_root_port - return PCIe Root Port
508 * @dev: PCI device to query
510 * Traverse up the parent chain and return the PCIe Root Port PCI Device
511 * for a given PCI Device.
513 struct pci_dev *pci_find_pcie_root_port(struct pci_dev *dev)
515 struct pci_dev *bridge, *highest_pcie_bridge = NULL;
517 bridge = pci_upstream_bridge(dev);
518 while (bridge && pci_is_pcie(bridge)) {
519 highest_pcie_bridge = bridge;
520 bridge = pci_upstream_bridge(bridge);
523 if (pci_pcie_type(highest_pcie_bridge) != PCI_EXP_TYPE_ROOT_PORT)
526 return highest_pcie_bridge;
528 EXPORT_SYMBOL(pci_find_pcie_root_port);
531 * pci_wait_for_pending - wait for @mask bit(s) to clear in status word @pos
532 * @dev: the PCI device to operate on
533 * @pos: config space offset of status word
534 * @mask: mask of bit(s) to care about in status word
536 * Return 1 when mask bit(s) in status word clear, 0 otherwise.
538 int pci_wait_for_pending(struct pci_dev *dev, int pos, u16 mask)
542 /* Wait for Transaction Pending bit clean */
543 for (i = 0; i < 4; i++) {
546 msleep((1 << (i - 1)) * 100);
548 pci_read_config_word(dev, pos, &status);
549 if (!(status & mask))
557 * pci_restore_bars - restore a device's BAR values (e.g. after wake-up)
558 * @dev: PCI device to have its BARs restored
560 * Restore the BAR values for a given device, so as to make it
561 * accessible by its driver.
563 static void pci_restore_bars(struct pci_dev *dev)
567 /* Per SR-IOV spec 3.4.1.11, VF BARs are RO zero */
571 for (i = 0; i < PCI_BRIDGE_RESOURCES; i++)
572 pci_update_resource(dev, i);
575 static const struct pci_platform_pm_ops *pci_platform_pm;
577 int pci_set_platform_pm(const struct pci_platform_pm_ops *ops)
579 if (!ops->is_manageable || !ops->set_state || !ops->choose_state ||
580 !ops->sleep_wake || !ops->run_wake || !ops->need_resume)
582 pci_platform_pm = ops;
586 static inline bool platform_pci_power_manageable(struct pci_dev *dev)
588 return pci_platform_pm ? pci_platform_pm->is_manageable(dev) : false;
591 static inline int platform_pci_set_power_state(struct pci_dev *dev,
594 return pci_platform_pm ? pci_platform_pm->set_state(dev, t) : -ENOSYS;
597 static inline pci_power_t platform_pci_choose_state(struct pci_dev *dev)
599 return pci_platform_pm ?
600 pci_platform_pm->choose_state(dev) : PCI_POWER_ERROR;
603 static inline int platform_pci_sleep_wake(struct pci_dev *dev, bool enable)
605 return pci_platform_pm ?
606 pci_platform_pm->sleep_wake(dev, enable) : -ENODEV;
609 static inline int platform_pci_run_wake(struct pci_dev *dev, bool enable)
611 return pci_platform_pm ?
612 pci_platform_pm->run_wake(dev, enable) : -ENODEV;
615 static inline bool platform_pci_need_resume(struct pci_dev *dev)
617 return pci_platform_pm ? pci_platform_pm->need_resume(dev) : false;
621 * pci_raw_set_power_state - Use PCI PM registers to set the power state of
623 * @dev: PCI device to handle.
624 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into.
627 * -EINVAL if the requested state is invalid.
628 * -EIO if device does not support PCI PM or its PM capabilities register has a
629 * wrong version, or device doesn't support the requested state.
630 * 0 if device already is in the requested state.
631 * 0 if device's power state has been successfully changed.
633 static int pci_raw_set_power_state(struct pci_dev *dev, pci_power_t state)
636 bool need_restore = false;
638 /* Check if we're already there */
639 if (dev->current_state == state)
645 if (state < PCI_D0 || state > PCI_D3hot)
648 /* Validate current state:
649 * Can enter D0 from any state, but if we can only go deeper
650 * to sleep if we're already in a low power state
652 if (state != PCI_D0 && dev->current_state <= PCI_D3cold
653 && dev->current_state > state) {
654 dev_err(&dev->dev, "invalid power transition (from state %d to %d)\n",
655 dev->current_state, state);
659 /* check if this device supports the desired state */
660 if ((state == PCI_D1 && !dev->d1_support)
661 || (state == PCI_D2 && !dev->d2_support))
664 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
666 /* If we're (effectively) in D3, force entire word to 0.
667 * This doesn't affect PME_Status, disables PME_En, and
668 * sets PowerState to 0.
670 switch (dev->current_state) {
674 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
679 case PCI_UNKNOWN: /* Boot-up */
680 if ((pmcsr & PCI_PM_CTRL_STATE_MASK) == PCI_D3hot
681 && !(pmcsr & PCI_PM_CTRL_NO_SOFT_RESET))
683 /* Fall-through: force to D0 */
689 /* enter specified state */
690 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr);
692 /* Mandatory power management transition delays */
693 /* see PCI PM 1.1 5.6.1 table 18 */
694 if (state == PCI_D3hot || dev->current_state == PCI_D3hot)
695 pci_dev_d3_sleep(dev);
696 else if (state == PCI_D2 || dev->current_state == PCI_D2)
697 udelay(PCI_PM_D2_DELAY);
699 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
700 dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK);
701 if (dev->current_state != state && printk_ratelimit())
702 dev_info(&dev->dev, "Refused to change power state, currently in D%d\n",
706 * According to section 5.4.1 of the "PCI BUS POWER MANAGEMENT
707 * INTERFACE SPECIFICATION, REV. 1.2", a device transitioning
708 * from D3hot to D0 _may_ perform an internal reset, thereby
709 * going to "D0 Uninitialized" rather than "D0 Initialized".
710 * For example, at least some versions of the 3c905B and the
711 * 3c556B exhibit this behaviour.
713 * At least some laptop BIOSen (e.g. the Thinkpad T21) leave
714 * devices in a D3hot state at boot. Consequently, we need to
715 * restore at least the BARs so that the device will be
716 * accessible to its driver.
719 pci_restore_bars(dev);
722 pcie_aspm_pm_state_change(dev->bus->self);
728 * pci_update_current_state - Read PCI power state of given device from its
729 * PCI PM registers and cache it
730 * @dev: PCI device to handle.
731 * @state: State to cache in case the device doesn't have the PM capability
733 void pci_update_current_state(struct pci_dev *dev, pci_power_t state)
739 * Configuration space is not accessible for device in
740 * D3cold, so just keep or set D3cold for safety
742 if (dev->current_state == PCI_D3cold)
744 if (state == PCI_D3cold) {
745 dev->current_state = PCI_D3cold;
748 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
749 dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK);
751 dev->current_state = state;
756 * pci_power_up - Put the given device into D0 forcibly
757 * @dev: PCI device to power up
759 void pci_power_up(struct pci_dev *dev)
761 if (platform_pci_power_manageable(dev))
762 platform_pci_set_power_state(dev, PCI_D0);
764 pci_raw_set_power_state(dev, PCI_D0);
765 pci_update_current_state(dev, PCI_D0);
769 * pci_platform_power_transition - Use platform to change device power state
770 * @dev: PCI device to handle.
771 * @state: State to put the device into.
773 static int pci_platform_power_transition(struct pci_dev *dev, pci_power_t state)
777 if (platform_pci_power_manageable(dev)) {
778 error = platform_pci_set_power_state(dev, state);
780 pci_update_current_state(dev, state);
784 if (error && !dev->pm_cap) /* Fall back to PCI_D0 */
785 dev->current_state = PCI_D0;
791 * pci_wakeup - Wake up a PCI device
792 * @pci_dev: Device to handle.
793 * @ign: ignored parameter
795 static int pci_wakeup(struct pci_dev *pci_dev, void *ign)
797 pci_wakeup_event(pci_dev);
798 pm_request_resume(&pci_dev->dev);
803 * pci_wakeup_bus - Walk given bus and wake up devices on it
804 * @bus: Top bus of the subtree to walk.
806 static void pci_wakeup_bus(struct pci_bus *bus)
809 pci_walk_bus(bus, pci_wakeup, NULL);
813 * __pci_start_power_transition - Start power transition of a PCI device
814 * @dev: PCI device to handle.
815 * @state: State to put the device into.
817 static void __pci_start_power_transition(struct pci_dev *dev, pci_power_t state)
819 if (state == PCI_D0) {
820 pci_platform_power_transition(dev, PCI_D0);
822 * Mandatory power management transition delays, see
823 * PCI Express Base Specification Revision 2.0 Section
824 * 6.6.1: Conventional Reset. Do not delay for
825 * devices powered on/off by corresponding bridge,
826 * because have already delayed for the bridge.
828 if (dev->runtime_d3cold) {
829 msleep(dev->d3cold_delay);
831 * When powering on a bridge from D3cold, the
832 * whole hierarchy may be powered on into
833 * D0uninitialized state, resume them to give
834 * them a chance to suspend again
836 pci_wakeup_bus(dev->subordinate);
842 * __pci_dev_set_current_state - Set current state of a PCI device
843 * @dev: Device to handle
844 * @data: pointer to state to be set
846 static int __pci_dev_set_current_state(struct pci_dev *dev, void *data)
848 pci_power_t state = *(pci_power_t *)data;
850 dev->current_state = state;
855 * __pci_bus_set_current_state - Walk given bus and set current state of devices
856 * @bus: Top bus of the subtree to walk.
857 * @state: state to be set
859 static void __pci_bus_set_current_state(struct pci_bus *bus, pci_power_t state)
862 pci_walk_bus(bus, __pci_dev_set_current_state, &state);
866 * __pci_complete_power_transition - Complete power transition of a PCI device
867 * @dev: PCI device to handle.
868 * @state: State to put the device into.
870 * This function should not be called directly by device drivers.
872 int __pci_complete_power_transition(struct pci_dev *dev, pci_power_t state)
878 ret = pci_platform_power_transition(dev, state);
879 /* Power off the bridge may power off the whole hierarchy */
880 if (!ret && state == PCI_D3cold)
881 __pci_bus_set_current_state(dev->subordinate, PCI_D3cold);
884 EXPORT_SYMBOL_GPL(__pci_complete_power_transition);
887 * pci_set_power_state - Set the power state of a PCI device
888 * @dev: PCI device to handle.
889 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into.
891 * Transition a device to a new power state, using the platform firmware and/or
892 * the device's PCI PM registers.
895 * -EINVAL if the requested state is invalid.
896 * -EIO if device does not support PCI PM or its PM capabilities register has a
897 * wrong version, or device doesn't support the requested state.
898 * 0 if device already is in the requested state.
899 * 0 if device's power state has been successfully changed.
901 int pci_set_power_state(struct pci_dev *dev, pci_power_t state)
905 /* bound the state we're entering */
906 if (state > PCI_D3cold)
908 else if (state < PCI_D0)
910 else if ((state == PCI_D1 || state == PCI_D2) && pci_no_d1d2(dev))
912 * If the device or the parent bridge do not support PCI PM,
913 * ignore the request if we're doing anything other than putting
914 * it into D0 (which would only happen on boot).
918 /* Check if we're already there */
919 if (dev->current_state == state)
922 __pci_start_power_transition(dev, state);
924 /* This device is quirked not to be put into D3, so
925 don't put it in D3 */
926 if (state >= PCI_D3hot && (dev->dev_flags & PCI_DEV_FLAGS_NO_D3))
930 * To put device in D3cold, we put device into D3hot in native
931 * way, then put device into D3cold with platform ops
933 error = pci_raw_set_power_state(dev, state > PCI_D3hot ?
936 if (!__pci_complete_power_transition(dev, state))
941 EXPORT_SYMBOL(pci_set_power_state);
944 * pci_choose_state - Choose the power state of a PCI device
945 * @dev: PCI device to be suspended
946 * @state: target sleep state for the whole system. This is the value
947 * that is passed to suspend() function.
949 * Returns PCI power state suitable for given device and given system
953 pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state)
960 ret = platform_pci_choose_state(dev);
961 if (ret != PCI_POWER_ERROR)
964 switch (state.event) {
967 case PM_EVENT_FREEZE:
968 case PM_EVENT_PRETHAW:
969 /* REVISIT both freeze and pre-thaw "should" use D0 */
970 case PM_EVENT_SUSPEND:
971 case PM_EVENT_HIBERNATE:
974 dev_info(&dev->dev, "unrecognized suspend event %d\n",
980 EXPORT_SYMBOL(pci_choose_state);
982 #define PCI_EXP_SAVE_REGS 7
984 static struct pci_cap_saved_state *_pci_find_saved_cap(struct pci_dev *pci_dev,
985 u16 cap, bool extended)
987 struct pci_cap_saved_state *tmp;
989 hlist_for_each_entry(tmp, &pci_dev->saved_cap_space, next) {
990 if (tmp->cap.cap_extended == extended && tmp->cap.cap_nr == cap)
996 struct pci_cap_saved_state *pci_find_saved_cap(struct pci_dev *dev, char cap)
998 return _pci_find_saved_cap(dev, cap, false);
1001 struct pci_cap_saved_state *pci_find_saved_ext_cap(struct pci_dev *dev, u16 cap)
1003 return _pci_find_saved_cap(dev, cap, true);
1006 static int pci_save_pcie_state(struct pci_dev *dev)
1009 struct pci_cap_saved_state *save_state;
1012 if (!pci_is_pcie(dev))
1015 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP);
1017 dev_err(&dev->dev, "buffer not found in %s\n", __func__);
1021 cap = (u16 *)&save_state->cap.data[0];
1022 pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &cap[i++]);
1023 pcie_capability_read_word(dev, PCI_EXP_LNKCTL, &cap[i++]);
1024 pcie_capability_read_word(dev, PCI_EXP_SLTCTL, &cap[i++]);
1025 pcie_capability_read_word(dev, PCI_EXP_RTCTL, &cap[i++]);
1026 pcie_capability_read_word(dev, PCI_EXP_DEVCTL2, &cap[i++]);
1027 pcie_capability_read_word(dev, PCI_EXP_LNKCTL2, &cap[i++]);
1028 pcie_capability_read_word(dev, PCI_EXP_SLTCTL2, &cap[i++]);
1033 static void pci_restore_pcie_state(struct pci_dev *dev)
1036 struct pci_cap_saved_state *save_state;
1039 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP);
1043 cap = (u16 *)&save_state->cap.data[0];
1044 pcie_capability_write_word(dev, PCI_EXP_DEVCTL, cap[i++]);
1045 pcie_capability_write_word(dev, PCI_EXP_LNKCTL, cap[i++]);
1046 pcie_capability_write_word(dev, PCI_EXP_SLTCTL, cap[i++]);
1047 pcie_capability_write_word(dev, PCI_EXP_RTCTL, cap[i++]);
1048 pcie_capability_write_word(dev, PCI_EXP_DEVCTL2, cap[i++]);
1049 pcie_capability_write_word(dev, PCI_EXP_LNKCTL2, cap[i++]);
1050 pcie_capability_write_word(dev, PCI_EXP_SLTCTL2, cap[i++]);
1054 static int pci_save_pcix_state(struct pci_dev *dev)
1057 struct pci_cap_saved_state *save_state;
1059 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
1063 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX);
1065 dev_err(&dev->dev, "buffer not found in %s\n", __func__);
1069 pci_read_config_word(dev, pos + PCI_X_CMD,
1070 (u16 *)save_state->cap.data);
1075 static void pci_restore_pcix_state(struct pci_dev *dev)
1078 struct pci_cap_saved_state *save_state;
1081 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX);
1082 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
1083 if (!save_state || !pos)
1085 cap = (u16 *)&save_state->cap.data[0];
1087 pci_write_config_word(dev, pos + PCI_X_CMD, cap[i++]);
1092 * pci_save_state - save the PCI configuration space of a device before suspending
1093 * @dev: - PCI device that we're dealing with
1095 int pci_save_state(struct pci_dev *dev)
1098 /* XXX: 100% dword access ok here? */
1099 for (i = 0; i < 16; i++)
1100 pci_read_config_dword(dev, i * 4, &dev->saved_config_space[i]);
1101 dev->state_saved = true;
1103 i = pci_save_pcie_state(dev);
1107 i = pci_save_pcix_state(dev);
1111 return pci_save_vc_state(dev);
1113 EXPORT_SYMBOL(pci_save_state);
1115 static void pci_restore_config_dword(struct pci_dev *pdev, int offset,
1116 u32 saved_val, int retry)
1120 pci_read_config_dword(pdev, offset, &val);
1121 if (val == saved_val)
1125 dev_dbg(&pdev->dev, "restoring config space at offset %#x (was %#x, writing %#x)\n",
1126 offset, val, saved_val);
1127 pci_write_config_dword(pdev, offset, saved_val);
1131 pci_read_config_dword(pdev, offset, &val);
1132 if (val == saved_val)
1139 static void pci_restore_config_space_range(struct pci_dev *pdev,
1140 int start, int end, int retry)
1144 for (index = end; index >= start; index--)
1145 pci_restore_config_dword(pdev, 4 * index,
1146 pdev->saved_config_space[index],
1150 static void pci_restore_config_space(struct pci_dev *pdev)
1152 if (pdev->hdr_type == PCI_HEADER_TYPE_NORMAL) {
1153 pci_restore_config_space_range(pdev, 10, 15, 0);
1154 /* Restore BARs before the command register. */
1155 pci_restore_config_space_range(pdev, 4, 9, 10);
1156 pci_restore_config_space_range(pdev, 0, 3, 0);
1158 pci_restore_config_space_range(pdev, 0, 15, 0);
1163 * pci_restore_state - Restore the saved state of a PCI device
1164 * @dev: - PCI device that we're dealing with
1166 void pci_restore_state(struct pci_dev *dev)
1168 if (!dev->state_saved)
1171 /* PCI Express register must be restored first */
1172 pci_restore_pcie_state(dev);
1173 pci_restore_ats_state(dev);
1174 pci_restore_vc_state(dev);
1176 pci_cleanup_aer_error_status_regs(dev);
1178 pci_restore_config_space(dev);
1180 pci_restore_pcix_state(dev);
1181 pci_restore_msi_state(dev);
1183 /* Restore ACS and IOV configuration state */
1184 pci_enable_acs(dev);
1185 pci_restore_iov_state(dev);
1187 dev->state_saved = false;
1189 EXPORT_SYMBOL(pci_restore_state);
1191 struct pci_saved_state {
1192 u32 config_space[16];
1193 struct pci_cap_saved_data cap[0];
1197 * pci_store_saved_state - Allocate and return an opaque struct containing
1198 * the device saved state.
1199 * @dev: PCI device that we're dealing with
1201 * Return NULL if no state or error.
1203 struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev)
1205 struct pci_saved_state *state;
1206 struct pci_cap_saved_state *tmp;
1207 struct pci_cap_saved_data *cap;
1210 if (!dev->state_saved)
1213 size = sizeof(*state) + sizeof(struct pci_cap_saved_data);
1215 hlist_for_each_entry(tmp, &dev->saved_cap_space, next)
1216 size += sizeof(struct pci_cap_saved_data) + tmp->cap.size;
1218 state = kzalloc(size, GFP_KERNEL);
1222 memcpy(state->config_space, dev->saved_config_space,
1223 sizeof(state->config_space));
1226 hlist_for_each_entry(tmp, &dev->saved_cap_space, next) {
1227 size_t len = sizeof(struct pci_cap_saved_data) + tmp->cap.size;
1228 memcpy(cap, &tmp->cap, len);
1229 cap = (struct pci_cap_saved_data *)((u8 *)cap + len);
1231 /* Empty cap_save terminates list */
1235 EXPORT_SYMBOL_GPL(pci_store_saved_state);
1238 * pci_load_saved_state - Reload the provided save state into struct pci_dev.
1239 * @dev: PCI device that we're dealing with
1240 * @state: Saved state returned from pci_store_saved_state()
1242 int pci_load_saved_state(struct pci_dev *dev,
1243 struct pci_saved_state *state)
1245 struct pci_cap_saved_data *cap;
1247 dev->state_saved = false;
1252 memcpy(dev->saved_config_space, state->config_space,
1253 sizeof(state->config_space));
1257 struct pci_cap_saved_state *tmp;
1259 tmp = _pci_find_saved_cap(dev, cap->cap_nr, cap->cap_extended);
1260 if (!tmp || tmp->cap.size != cap->size)
1263 memcpy(tmp->cap.data, cap->data, tmp->cap.size);
1264 cap = (struct pci_cap_saved_data *)((u8 *)cap +
1265 sizeof(struct pci_cap_saved_data) + cap->size);
1268 dev->state_saved = true;
1271 EXPORT_SYMBOL_GPL(pci_load_saved_state);
1274 * pci_load_and_free_saved_state - Reload the save state pointed to by state,
1275 * and free the memory allocated for it.
1276 * @dev: PCI device that we're dealing with
1277 * @state: Pointer to saved state returned from pci_store_saved_state()
1279 int pci_load_and_free_saved_state(struct pci_dev *dev,
1280 struct pci_saved_state **state)
1282 int ret = pci_load_saved_state(dev, *state);
1287 EXPORT_SYMBOL_GPL(pci_load_and_free_saved_state);
1289 int __weak pcibios_enable_device(struct pci_dev *dev, int bars)
1291 return pci_enable_resources(dev, bars);
1294 static int do_pci_enable_device(struct pci_dev *dev, int bars)
1297 struct pci_dev *bridge;
1301 err = pci_set_power_state(dev, PCI_D0);
1302 if (err < 0 && err != -EIO)
1305 bridge = pci_upstream_bridge(dev);
1307 pcie_aspm_powersave_config_link(bridge);
1309 err = pcibios_enable_device(dev, bars);
1312 pci_fixup_device(pci_fixup_enable, dev);
1314 if (dev->msi_enabled || dev->msix_enabled)
1317 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin);
1319 pci_read_config_word(dev, PCI_COMMAND, &cmd);
1320 if (cmd & PCI_COMMAND_INTX_DISABLE)
1321 pci_write_config_word(dev, PCI_COMMAND,
1322 cmd & ~PCI_COMMAND_INTX_DISABLE);
1329 * pci_reenable_device - Resume abandoned device
1330 * @dev: PCI device to be resumed
1332 * Note this function is a backend of pci_default_resume and is not supposed
1333 * to be called by normal code, write proper resume handler and use it instead.
1335 int pci_reenable_device(struct pci_dev *dev)
1337 if (pci_is_enabled(dev))
1338 return do_pci_enable_device(dev, (1 << PCI_NUM_RESOURCES) - 1);
1341 EXPORT_SYMBOL(pci_reenable_device);
1343 static void pci_enable_bridge(struct pci_dev *dev)
1345 struct pci_dev *bridge;
1348 bridge = pci_upstream_bridge(dev);
1350 pci_enable_bridge(bridge);
1352 if (pci_is_enabled(dev)) {
1353 if (!dev->is_busmaster)
1354 pci_set_master(dev);
1358 retval = pci_enable_device(dev);
1360 dev_err(&dev->dev, "Error enabling bridge (%d), continuing\n",
1362 pci_set_master(dev);
1365 static int pci_enable_device_flags(struct pci_dev *dev, unsigned long flags)
1367 struct pci_dev *bridge;
1372 * Power state could be unknown at this point, either due to a fresh
1373 * boot or a device removal call. So get the current power state
1374 * so that things like MSI message writing will behave as expected
1375 * (e.g. if the device really is in D0 at enable time).
1379 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
1380 dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK);
1383 if (atomic_inc_return(&dev->enable_cnt) > 1)
1384 return 0; /* already enabled */
1386 bridge = pci_upstream_bridge(dev);
1388 pci_enable_bridge(bridge);
1390 /* only skip sriov related */
1391 for (i = 0; i <= PCI_ROM_RESOURCE; i++)
1392 if (dev->resource[i].flags & flags)
1394 for (i = PCI_BRIDGE_RESOURCES; i < DEVICE_COUNT_RESOURCE; i++)
1395 if (dev->resource[i].flags & flags)
1398 err = do_pci_enable_device(dev, bars);
1400 atomic_dec(&dev->enable_cnt);
1405 * pci_enable_device_io - Initialize a device for use with IO space
1406 * @dev: PCI device to be initialized
1408 * Initialize device before it's used by a driver. Ask low-level code
1409 * to enable I/O resources. Wake up the device if it was suspended.
1410 * Beware, this function can fail.
1412 int pci_enable_device_io(struct pci_dev *dev)
1414 return pci_enable_device_flags(dev, IORESOURCE_IO);
1416 EXPORT_SYMBOL(pci_enable_device_io);
1419 * pci_enable_device_mem - Initialize a device for use with Memory space
1420 * @dev: PCI device to be initialized
1422 * Initialize device before it's used by a driver. Ask low-level code
1423 * to enable Memory resources. Wake up the device if it was suspended.
1424 * Beware, this function can fail.
1426 int pci_enable_device_mem(struct pci_dev *dev)
1428 return pci_enable_device_flags(dev, IORESOURCE_MEM);
1430 EXPORT_SYMBOL(pci_enable_device_mem);
1433 * pci_enable_device - Initialize device before it's used by a driver.
1434 * @dev: PCI device to be initialized
1436 * Initialize device before it's used by a driver. Ask low-level code
1437 * to enable I/O and memory. Wake up the device if it was suspended.
1438 * Beware, this function can fail.
1440 * Note we don't actually enable the device many times if we call
1441 * this function repeatedly (we just increment the count).
1443 int pci_enable_device(struct pci_dev *dev)
1445 return pci_enable_device_flags(dev, IORESOURCE_MEM | IORESOURCE_IO);
1447 EXPORT_SYMBOL(pci_enable_device);
1450 * Managed PCI resources. This manages device on/off, intx/msi/msix
1451 * on/off and BAR regions. pci_dev itself records msi/msix status, so
1452 * there's no need to track it separately. pci_devres is initialized
1453 * when a device is enabled using managed PCI device enable interface.
1456 unsigned int enabled:1;
1457 unsigned int pinned:1;
1458 unsigned int orig_intx:1;
1459 unsigned int restore_intx:1;
1463 static void pcim_release(struct device *gendev, void *res)
1465 struct pci_dev *dev = to_pci_dev(gendev);
1466 struct pci_devres *this = res;
1469 if (dev->msi_enabled)
1470 pci_disable_msi(dev);
1471 if (dev->msix_enabled)
1472 pci_disable_msix(dev);
1474 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++)
1475 if (this->region_mask & (1 << i))
1476 pci_release_region(dev, i);
1478 if (this->restore_intx)
1479 pci_intx(dev, this->orig_intx);
1481 if (this->enabled && !this->pinned)
1482 pci_disable_device(dev);
1485 static struct pci_devres *get_pci_dr(struct pci_dev *pdev)
1487 struct pci_devres *dr, *new_dr;
1489 dr = devres_find(&pdev->dev, pcim_release, NULL, NULL);
1493 new_dr = devres_alloc(pcim_release, sizeof(*new_dr), GFP_KERNEL);
1496 return devres_get(&pdev->dev, new_dr, NULL, NULL);
1499 static struct pci_devres *find_pci_dr(struct pci_dev *pdev)
1501 if (pci_is_managed(pdev))
1502 return devres_find(&pdev->dev, pcim_release, NULL, NULL);
1507 * pcim_enable_device - Managed pci_enable_device()
1508 * @pdev: PCI device to be initialized
1510 * Managed pci_enable_device().
1512 int pcim_enable_device(struct pci_dev *pdev)
1514 struct pci_devres *dr;
1517 dr = get_pci_dr(pdev);
1523 rc = pci_enable_device(pdev);
1525 pdev->is_managed = 1;
1530 EXPORT_SYMBOL(pcim_enable_device);
1533 * pcim_pin_device - Pin managed PCI device
1534 * @pdev: PCI device to pin
1536 * Pin managed PCI device @pdev. Pinned device won't be disabled on
1537 * driver detach. @pdev must have been enabled with
1538 * pcim_enable_device().
1540 void pcim_pin_device(struct pci_dev *pdev)
1542 struct pci_devres *dr;
1544 dr = find_pci_dr(pdev);
1545 WARN_ON(!dr || !dr->enabled);
1549 EXPORT_SYMBOL(pcim_pin_device);
1552 * pcibios_add_device - provide arch specific hooks when adding device dev
1553 * @dev: the PCI device being added
1555 * Permits the platform to provide architecture specific functionality when
1556 * devices are added. This is the default implementation. Architecture
1557 * implementations can override this.
1559 int __weak pcibios_add_device(struct pci_dev *dev)
1565 * pcibios_release_device - provide arch specific hooks when releasing device dev
1566 * @dev: the PCI device being released
1568 * Permits the platform to provide architecture specific functionality when
1569 * devices are released. This is the default implementation. Architecture
1570 * implementations can override this.
1572 void __weak pcibios_release_device(struct pci_dev *dev) {}
1575 * pcibios_disable_device - disable arch specific PCI resources for device dev
1576 * @dev: the PCI device to disable
1578 * Disables architecture specific PCI resources for the device. This
1579 * is the default implementation. Architecture implementations can
1582 void __weak pcibios_disable_device(struct pci_dev *dev) {}
1585 * pcibios_penalize_isa_irq - penalize an ISA IRQ
1586 * @irq: ISA IRQ to penalize
1587 * @active: IRQ active or not
1589 * Permits the platform to provide architecture-specific functionality when
1590 * penalizing ISA IRQs. This is the default implementation. Architecture
1591 * implementations can override this.
1593 void __weak pcibios_penalize_isa_irq(int irq, int active) {}
1595 static void do_pci_disable_device(struct pci_dev *dev)
1599 pci_read_config_word(dev, PCI_COMMAND, &pci_command);
1600 if (pci_command & PCI_COMMAND_MASTER) {
1601 pci_command &= ~PCI_COMMAND_MASTER;
1602 pci_write_config_word(dev, PCI_COMMAND, pci_command);
1605 pcibios_disable_device(dev);
1609 * pci_disable_enabled_device - Disable device without updating enable_cnt
1610 * @dev: PCI device to disable
1612 * NOTE: This function is a backend of PCI power management routines and is
1613 * not supposed to be called drivers.
1615 void pci_disable_enabled_device(struct pci_dev *dev)
1617 if (pci_is_enabled(dev))
1618 do_pci_disable_device(dev);
1622 * pci_disable_device - Disable PCI device after use
1623 * @dev: PCI device to be disabled
1625 * Signal to the system that the PCI device is not in use by the system
1626 * anymore. This only involves disabling PCI bus-mastering, if active.
1628 * Note we don't actually disable the device until all callers of
1629 * pci_enable_device() have called pci_disable_device().
1631 void pci_disable_device(struct pci_dev *dev)
1633 struct pci_devres *dr;
1635 dr = find_pci_dr(dev);
1639 dev_WARN_ONCE(&dev->dev, atomic_read(&dev->enable_cnt) <= 0,
1640 "disabling already-disabled device");
1642 if (atomic_dec_return(&dev->enable_cnt) != 0)
1645 do_pci_disable_device(dev);
1647 dev->is_busmaster = 0;
1649 EXPORT_SYMBOL(pci_disable_device);
1652 * pcibios_set_pcie_reset_state - set reset state for device dev
1653 * @dev: the PCIe device reset
1654 * @state: Reset state to enter into
1657 * Sets the PCIe reset state for the device. This is the default
1658 * implementation. Architecture implementations can override this.
1660 int __weak pcibios_set_pcie_reset_state(struct pci_dev *dev,
1661 enum pcie_reset_state state)
1667 * pci_set_pcie_reset_state - set reset state for device dev
1668 * @dev: the PCIe device reset
1669 * @state: Reset state to enter into
1672 * Sets the PCI reset state for the device.
1674 int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state)
1676 return pcibios_set_pcie_reset_state(dev, state);
1678 EXPORT_SYMBOL_GPL(pci_set_pcie_reset_state);
1681 * pci_check_pme_status - Check if given device has generated PME.
1682 * @dev: Device to check.
1684 * Check the PME status of the device and if set, clear it and clear PME enable
1685 * (if set). Return 'true' if PME status and PME enable were both set or
1686 * 'false' otherwise.
1688 bool pci_check_pme_status(struct pci_dev *dev)
1697 pmcsr_pos = dev->pm_cap + PCI_PM_CTRL;
1698 pci_read_config_word(dev, pmcsr_pos, &pmcsr);
1699 if (!(pmcsr & PCI_PM_CTRL_PME_STATUS))
1702 /* Clear PME status. */
1703 pmcsr |= PCI_PM_CTRL_PME_STATUS;
1704 if (pmcsr & PCI_PM_CTRL_PME_ENABLE) {
1705 /* Disable PME to avoid interrupt flood. */
1706 pmcsr &= ~PCI_PM_CTRL_PME_ENABLE;
1710 pci_write_config_word(dev, pmcsr_pos, pmcsr);
1716 * pci_pme_wakeup - Wake up a PCI device if its PME Status bit is set.
1717 * @dev: Device to handle.
1718 * @pme_poll_reset: Whether or not to reset the device's pme_poll flag.
1720 * Check if @dev has generated PME and queue a resume request for it in that
1723 static int pci_pme_wakeup(struct pci_dev *dev, void *pme_poll_reset)
1725 if (pme_poll_reset && dev->pme_poll)
1726 dev->pme_poll = false;
1728 if (pci_check_pme_status(dev)) {
1729 pci_wakeup_event(dev);
1730 pm_request_resume(&dev->dev);
1736 * pci_pme_wakeup_bus - Walk given bus and wake up devices on it, if necessary.
1737 * @bus: Top bus of the subtree to walk.
1739 void pci_pme_wakeup_bus(struct pci_bus *bus)
1742 pci_walk_bus(bus, pci_pme_wakeup, (void *)true);
1747 * pci_pme_capable - check the capability of PCI device to generate PME#
1748 * @dev: PCI device to handle.
1749 * @state: PCI state from which device will issue PME#.
1751 bool pci_pme_capable(struct pci_dev *dev, pci_power_t state)
1756 return !!(dev->pme_support & (1 << state));
1758 EXPORT_SYMBOL(pci_pme_capable);
1760 static void pci_pme_list_scan(struct work_struct *work)
1762 struct pci_pme_device *pme_dev, *n;
1764 mutex_lock(&pci_pme_list_mutex);
1765 list_for_each_entry_safe(pme_dev, n, &pci_pme_list, list) {
1766 if (pme_dev->dev->pme_poll) {
1767 struct pci_dev *bridge;
1769 bridge = pme_dev->dev->bus->self;
1771 * If bridge is in low power state, the
1772 * configuration space of subordinate devices
1773 * may be not accessible
1775 if (bridge && bridge->current_state != PCI_D0)
1777 pci_pme_wakeup(pme_dev->dev, NULL);
1779 list_del(&pme_dev->list);
1783 if (!list_empty(&pci_pme_list))
1784 schedule_delayed_work(&pci_pme_work,
1785 msecs_to_jiffies(PME_TIMEOUT));
1786 mutex_unlock(&pci_pme_list_mutex);
1789 static void __pci_pme_active(struct pci_dev *dev, bool enable)
1793 if (!dev->pme_support)
1796 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
1797 /* Clear PME_Status by writing 1 to it and enable PME# */
1798 pmcsr |= PCI_PM_CTRL_PME_STATUS | PCI_PM_CTRL_PME_ENABLE;
1800 pmcsr &= ~PCI_PM_CTRL_PME_ENABLE;
1802 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr);
1806 * pci_pme_active - enable or disable PCI device's PME# function
1807 * @dev: PCI device to handle.
1808 * @enable: 'true' to enable PME# generation; 'false' to disable it.
1810 * The caller must verify that the device is capable of generating PME# before
1811 * calling this function with @enable equal to 'true'.
1813 void pci_pme_active(struct pci_dev *dev, bool enable)
1815 __pci_pme_active(dev, enable);
1818 * PCI (as opposed to PCIe) PME requires that the device have
1819 * its PME# line hooked up correctly. Not all hardware vendors
1820 * do this, so the PME never gets delivered and the device
1821 * remains asleep. The easiest way around this is to
1822 * periodically walk the list of suspended devices and check
1823 * whether any have their PME flag set. The assumption is that
1824 * we'll wake up often enough anyway that this won't be a huge
1825 * hit, and the power savings from the devices will still be a
1828 * Although PCIe uses in-band PME message instead of PME# line
1829 * to report PME, PME does not work for some PCIe devices in
1830 * reality. For example, there are devices that set their PME
1831 * status bits, but don't really bother to send a PME message;
1832 * there are PCI Express Root Ports that don't bother to
1833 * trigger interrupts when they receive PME messages from the
1834 * devices below. So PME poll is used for PCIe devices too.
1837 if (dev->pme_poll) {
1838 struct pci_pme_device *pme_dev;
1840 pme_dev = kmalloc(sizeof(struct pci_pme_device),
1843 dev_warn(&dev->dev, "can't enable PME#\n");
1847 mutex_lock(&pci_pme_list_mutex);
1848 list_add(&pme_dev->list, &pci_pme_list);
1849 if (list_is_singular(&pci_pme_list))
1850 schedule_delayed_work(&pci_pme_work,
1851 msecs_to_jiffies(PME_TIMEOUT));
1852 mutex_unlock(&pci_pme_list_mutex);
1854 mutex_lock(&pci_pme_list_mutex);
1855 list_for_each_entry(pme_dev, &pci_pme_list, list) {
1856 if (pme_dev->dev == dev) {
1857 list_del(&pme_dev->list);
1862 mutex_unlock(&pci_pme_list_mutex);
1866 dev_dbg(&dev->dev, "PME# %s\n", enable ? "enabled" : "disabled");
1868 EXPORT_SYMBOL(pci_pme_active);
1871 * __pci_enable_wake - enable PCI device as wakeup event source
1872 * @dev: PCI device affected
1873 * @state: PCI state from which device will issue wakeup events
1874 * @runtime: True if the events are to be generated at run time
1875 * @enable: True to enable event generation; false to disable
1877 * This enables the device as a wakeup event source, or disables it.
1878 * When such events involves platform-specific hooks, those hooks are
1879 * called automatically by this routine.
1881 * Devices with legacy power management (no standard PCI PM capabilities)
1882 * always require such platform hooks.
1885 * 0 is returned on success
1886 * -EINVAL is returned if device is not supposed to wake up the system
1887 * Error code depending on the platform is returned if both the platform and
1888 * the native mechanism fail to enable the generation of wake-up events
1890 int __pci_enable_wake(struct pci_dev *dev, pci_power_t state,
1891 bool runtime, bool enable)
1895 if (enable && !runtime && !device_may_wakeup(&dev->dev))
1898 /* Don't do the same thing twice in a row for one device. */
1899 if (!!enable == !!dev->wakeup_prepared)
1903 * According to "PCI System Architecture" 4th ed. by Tom Shanley & Don
1904 * Anderson we should be doing PME# wake enable followed by ACPI wake
1905 * enable. To disable wake-up we call the platform first, for symmetry.
1911 if (pci_pme_capable(dev, state))
1912 pci_pme_active(dev, true);
1915 error = runtime ? platform_pci_run_wake(dev, true) :
1916 platform_pci_sleep_wake(dev, true);
1920 dev->wakeup_prepared = true;
1923 platform_pci_run_wake(dev, false);
1925 platform_pci_sleep_wake(dev, false);
1926 pci_pme_active(dev, false);
1927 dev->wakeup_prepared = false;
1932 EXPORT_SYMBOL(__pci_enable_wake);
1935 * pci_wake_from_d3 - enable/disable device to wake up from D3_hot or D3_cold
1936 * @dev: PCI device to prepare
1937 * @enable: True to enable wake-up event generation; false to disable
1939 * Many drivers want the device to wake up the system from D3_hot or D3_cold
1940 * and this function allows them to set that up cleanly - pci_enable_wake()
1941 * should not be called twice in a row to enable wake-up due to PCI PM vs ACPI
1942 * ordering constraints.
1944 * This function only returns error code if the device is not capable of
1945 * generating PME# from both D3_hot and D3_cold, and the platform is unable to
1946 * enable wake-up power for it.
1948 int pci_wake_from_d3(struct pci_dev *dev, bool enable)
1950 return pci_pme_capable(dev, PCI_D3cold) ?
1951 pci_enable_wake(dev, PCI_D3cold, enable) :
1952 pci_enable_wake(dev, PCI_D3hot, enable);
1954 EXPORT_SYMBOL(pci_wake_from_d3);
1957 * pci_target_state - find an appropriate low power state for a given PCI dev
1960 * Use underlying platform code to find a supported low power state for @dev.
1961 * If the platform can't manage @dev, return the deepest state from which it
1962 * can generate wake events, based on any available PME info.
1964 static pci_power_t pci_target_state(struct pci_dev *dev)
1966 pci_power_t target_state = PCI_D3hot;
1968 if (platform_pci_power_manageable(dev)) {
1970 * Call the platform to choose the target state of the device
1971 * and enable wake-up from this state if supported.
1973 pci_power_t state = platform_pci_choose_state(dev);
1976 case PCI_POWER_ERROR:
1981 if (pci_no_d1d2(dev))
1984 target_state = state;
1986 } else if (!dev->pm_cap) {
1987 target_state = PCI_D0;
1988 } else if (device_may_wakeup(&dev->dev)) {
1990 * Find the deepest state from which the device can generate
1991 * wake-up events, make it the target state and enable device
1994 if (dev->pme_support) {
1996 && !(dev->pme_support & (1 << target_state)))
2001 return target_state;
2005 * pci_prepare_to_sleep - prepare PCI device for system-wide transition into a sleep state
2006 * @dev: Device to handle.
2008 * Choose the power state appropriate for the device depending on whether
2009 * it can wake up the system and/or is power manageable by the platform
2010 * (PCI_D3hot is the default) and put the device into that state.
2012 int pci_prepare_to_sleep(struct pci_dev *dev)
2014 pci_power_t target_state = pci_target_state(dev);
2017 if (target_state == PCI_POWER_ERROR)
2020 pci_enable_wake(dev, target_state, device_may_wakeup(&dev->dev));
2022 error = pci_set_power_state(dev, target_state);
2025 pci_enable_wake(dev, target_state, false);
2029 EXPORT_SYMBOL(pci_prepare_to_sleep);
2032 * pci_back_from_sleep - turn PCI device on during system-wide transition into working state
2033 * @dev: Device to handle.
2035 * Disable device's system wake-up capability and put it into D0.
2037 int pci_back_from_sleep(struct pci_dev *dev)
2039 pci_enable_wake(dev, PCI_D0, false);
2040 return pci_set_power_state(dev, PCI_D0);
2042 EXPORT_SYMBOL(pci_back_from_sleep);
2045 * pci_finish_runtime_suspend - Carry out PCI-specific part of runtime suspend.
2046 * @dev: PCI device being suspended.
2048 * Prepare @dev to generate wake-up events at run time and put it into a low
2051 int pci_finish_runtime_suspend(struct pci_dev *dev)
2053 pci_power_t target_state = pci_target_state(dev);
2056 if (target_state == PCI_POWER_ERROR)
2059 dev->runtime_d3cold = target_state == PCI_D3cold;
2061 __pci_enable_wake(dev, target_state, true, pci_dev_run_wake(dev));
2063 error = pci_set_power_state(dev, target_state);
2066 __pci_enable_wake(dev, target_state, true, false);
2067 dev->runtime_d3cold = false;
2074 * pci_dev_run_wake - Check if device can generate run-time wake-up events.
2075 * @dev: Device to check.
2077 * Return true if the device itself is capable of generating wake-up events
2078 * (through the platform or using the native PCIe PME) or if the device supports
2079 * PME and one of its upstream bridges can generate wake-up events.
2081 bool pci_dev_run_wake(struct pci_dev *dev)
2083 struct pci_bus *bus = dev->bus;
2085 if (device_run_wake(&dev->dev))
2088 if (!dev->pme_support)
2091 while (bus->parent) {
2092 struct pci_dev *bridge = bus->self;
2094 if (device_run_wake(&bridge->dev))
2100 /* We have reached the root bus. */
2102 return device_run_wake(bus->bridge);
2106 EXPORT_SYMBOL_GPL(pci_dev_run_wake);
2109 * pci_dev_keep_suspended - Check if the device can stay in the suspended state.
2110 * @pci_dev: Device to check.
2112 * Return 'true' if the device is runtime-suspended, it doesn't have to be
2113 * reconfigured due to wakeup settings difference between system and runtime
2114 * suspend and the current power state of it is suitable for the upcoming
2115 * (system) transition.
2117 * If the device is not configured for system wakeup, disable PME for it before
2118 * returning 'true' to prevent it from waking up the system unnecessarily.
2120 bool pci_dev_keep_suspended(struct pci_dev *pci_dev)
2122 struct device *dev = &pci_dev->dev;
2124 if (!pm_runtime_suspended(dev)
2125 || pci_target_state(pci_dev) != pci_dev->current_state
2126 || platform_pci_need_resume(pci_dev))
2130 * At this point the device is good to go unless it's been configured
2131 * to generate PME at the runtime suspend time, but it is not supposed
2132 * to wake up the system. In that case, simply disable PME for it
2133 * (it will have to be re-enabled on exit from system resume).
2135 * If the device's power state is D3cold and the platform check above
2136 * hasn't triggered, the device's configuration is suitable and we don't
2137 * need to manipulate it at all.
2139 spin_lock_irq(&dev->power.lock);
2141 if (pm_runtime_suspended(dev) && pci_dev->current_state < PCI_D3cold &&
2142 !device_may_wakeup(dev))
2143 __pci_pme_active(pci_dev, false);
2145 spin_unlock_irq(&dev->power.lock);
2150 * pci_dev_complete_resume - Finalize resume from system sleep for a device.
2151 * @pci_dev: Device to handle.
2153 * If the device is runtime suspended and wakeup-capable, enable PME for it as
2154 * it might have been disabled during the prepare phase of system suspend if
2155 * the device was not configured for system wakeup.
2157 void pci_dev_complete_resume(struct pci_dev *pci_dev)
2159 struct device *dev = &pci_dev->dev;
2161 if (!pci_dev_run_wake(pci_dev))
2164 spin_lock_irq(&dev->power.lock);
2166 if (pm_runtime_suspended(dev) && pci_dev->current_state < PCI_D3cold)
2167 __pci_pme_active(pci_dev, true);
2169 spin_unlock_irq(&dev->power.lock);
2172 void pci_config_pm_runtime_get(struct pci_dev *pdev)
2174 struct device *dev = &pdev->dev;
2175 struct device *parent = dev->parent;
2178 pm_runtime_get_sync(parent);
2179 pm_runtime_get_noresume(dev);
2181 * pdev->current_state is set to PCI_D3cold during suspending,
2182 * so wait until suspending completes
2184 pm_runtime_barrier(dev);
2186 * Only need to resume devices in D3cold, because config
2187 * registers are still accessible for devices suspended but
2190 if (pdev->current_state == PCI_D3cold)
2191 pm_runtime_resume(dev);
2194 void pci_config_pm_runtime_put(struct pci_dev *pdev)
2196 struct device *dev = &pdev->dev;
2197 struct device *parent = dev->parent;
2199 pm_runtime_put(dev);
2201 pm_runtime_put_sync(parent);
2205 * pci_bridge_d3_possible - Is it possible to put the bridge into D3
2206 * @bridge: Bridge to check
2208 * This function checks if it is possible to move the bridge to D3.
2209 * Currently we only allow D3 for recent enough PCIe ports.
2211 static bool pci_bridge_d3_possible(struct pci_dev *bridge)
2215 if (!pci_is_pcie(bridge))
2218 switch (pci_pcie_type(bridge)) {
2219 case PCI_EXP_TYPE_ROOT_PORT:
2220 case PCI_EXP_TYPE_UPSTREAM:
2221 case PCI_EXP_TYPE_DOWNSTREAM:
2222 if (pci_bridge_d3_disable)
2224 if (pci_bridge_d3_force)
2228 * It should be safe to put PCIe ports from 2015 or newer
2231 if (dmi_get_date(DMI_BIOS_DATE, &year, NULL, NULL) &&
2241 static int pci_dev_check_d3cold(struct pci_dev *dev, void *data)
2243 bool *d3cold_ok = data;
2247 * The device needs to be allowed to go D3cold and if it is wake
2248 * capable to do so from D3cold.
2250 no_d3cold = dev->no_d3cold || !dev->d3cold_allowed ||
2251 (device_may_wakeup(&dev->dev) && !pci_pme_capable(dev, PCI_D3cold)) ||
2252 !pci_power_manageable(dev);
2254 *d3cold_ok = !no_d3cold;
2260 * pci_bridge_d3_update - Update bridge D3 capabilities
2261 * @dev: PCI device which is changed
2262 * @remove: Is the device being removed
2264 * Update upstream bridge PM capabilities accordingly depending on if the
2265 * device PM configuration was changed or the device is being removed. The
2266 * change is also propagated upstream.
2268 static void pci_bridge_d3_update(struct pci_dev *dev, bool remove)
2270 struct pci_dev *bridge;
2271 bool d3cold_ok = true;
2273 bridge = pci_upstream_bridge(dev);
2274 if (!bridge || !pci_bridge_d3_possible(bridge))
2277 pci_dev_get(bridge);
2279 * If the device is removed we do not care about its D3cold
2283 pci_dev_check_d3cold(dev, &d3cold_ok);
2287 * We need to go through all children to find out if all of
2288 * them can still go to D3cold.
2290 pci_walk_bus(bridge->subordinate, pci_dev_check_d3cold,
2294 if (bridge->bridge_d3 != d3cold_ok) {
2295 bridge->bridge_d3 = d3cold_ok;
2296 /* Propagate change to upstream bridges */
2297 pci_bridge_d3_update(bridge, false);
2300 pci_dev_put(bridge);
2304 * pci_bridge_d3_device_changed - Update bridge D3 capabilities on change
2305 * @dev: PCI device that was changed
2307 * If a device is added or its PM configuration, such as is it allowed to
2308 * enter D3cold, is changed this function updates upstream bridge PM
2309 * capabilities accordingly.
2311 void pci_bridge_d3_device_changed(struct pci_dev *dev)
2313 pci_bridge_d3_update(dev, false);
2317 * pci_bridge_d3_device_removed - Update bridge D3 capabilities on remove
2318 * @dev: PCI device being removed
2320 * Function updates upstream bridge PM capabilities based on other devices
2321 * still left on the bus.
2323 void pci_bridge_d3_device_removed(struct pci_dev *dev)
2325 pci_bridge_d3_update(dev, true);
2329 * pci_d3cold_enable - Enable D3cold for device
2330 * @dev: PCI device to handle
2332 * This function can be used in drivers to enable D3cold from the device
2333 * they handle. It also updates upstream PCI bridge PM capabilities
2336 void pci_d3cold_enable(struct pci_dev *dev)
2338 if (dev->no_d3cold) {
2339 dev->no_d3cold = false;
2340 pci_bridge_d3_device_changed(dev);
2343 EXPORT_SYMBOL_GPL(pci_d3cold_enable);
2346 * pci_d3cold_disable - Disable D3cold for device
2347 * @dev: PCI device to handle
2349 * This function can be used in drivers to disable D3cold from the device
2350 * they handle. It also updates upstream PCI bridge PM capabilities
2353 void pci_d3cold_disable(struct pci_dev *dev)
2355 if (!dev->no_d3cold) {
2356 dev->no_d3cold = true;
2357 pci_bridge_d3_device_changed(dev);
2360 EXPORT_SYMBOL_GPL(pci_d3cold_disable);
2363 * pci_pm_init - Initialize PM functions of given PCI device
2364 * @dev: PCI device to handle.
2366 void pci_pm_init(struct pci_dev *dev)
2371 pm_runtime_forbid(&dev->dev);
2372 pm_runtime_set_active(&dev->dev);
2373 pm_runtime_enable(&dev->dev);
2374 device_enable_async_suspend(&dev->dev);
2375 dev->wakeup_prepared = false;
2378 dev->pme_support = 0;
2380 /* find PCI PM capability in list */
2381 pm = pci_find_capability(dev, PCI_CAP_ID_PM);
2384 /* Check device's ability to generate PME# */
2385 pci_read_config_word(dev, pm + PCI_PM_PMC, &pmc);
2387 if ((pmc & PCI_PM_CAP_VER_MASK) > 3) {
2388 dev_err(&dev->dev, "unsupported PM cap regs version (%u)\n",
2389 pmc & PCI_PM_CAP_VER_MASK);
2394 dev->d3_delay = PCI_PM_D3_WAIT;
2395 dev->d3cold_delay = PCI_PM_D3COLD_WAIT;
2396 dev->bridge_d3 = pci_bridge_d3_possible(dev);
2397 dev->d3cold_allowed = true;
2399 dev->d1_support = false;
2400 dev->d2_support = false;
2401 if (!pci_no_d1d2(dev)) {
2402 if (pmc & PCI_PM_CAP_D1)
2403 dev->d1_support = true;
2404 if (pmc & PCI_PM_CAP_D2)
2405 dev->d2_support = true;
2407 if (dev->d1_support || dev->d2_support)
2408 dev_printk(KERN_DEBUG, &dev->dev, "supports%s%s\n",
2409 dev->d1_support ? " D1" : "",
2410 dev->d2_support ? " D2" : "");
2413 pmc &= PCI_PM_CAP_PME_MASK;
2415 dev_printk(KERN_DEBUG, &dev->dev,
2416 "PME# supported from%s%s%s%s%s\n",
2417 (pmc & PCI_PM_CAP_PME_D0) ? " D0" : "",
2418 (pmc & PCI_PM_CAP_PME_D1) ? " D1" : "",
2419 (pmc & PCI_PM_CAP_PME_D2) ? " D2" : "",
2420 (pmc & PCI_PM_CAP_PME_D3) ? " D3hot" : "",
2421 (pmc & PCI_PM_CAP_PME_D3cold) ? " D3cold" : "");
2422 dev->pme_support = pmc >> PCI_PM_CAP_PME_SHIFT;
2423 dev->pme_poll = true;
2425 * Make device's PM flags reflect the wake-up capability, but
2426 * let the user space enable it to wake up the system as needed.
2428 device_set_wakeup_capable(&dev->dev, true);
2429 /* Disable the PME# generation functionality */
2430 pci_pme_active(dev, false);
2434 static unsigned long pci_ea_flags(struct pci_dev *dev, u8 prop)
2436 unsigned long flags = IORESOURCE_PCI_FIXED | IORESOURCE_PCI_EA_BEI;
2440 case PCI_EA_P_VF_MEM:
2441 flags |= IORESOURCE_MEM;
2443 case PCI_EA_P_MEM_PREFETCH:
2444 case PCI_EA_P_VF_MEM_PREFETCH:
2445 flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH;
2448 flags |= IORESOURCE_IO;
2457 static struct resource *pci_ea_get_resource(struct pci_dev *dev, u8 bei,
2460 if (bei <= PCI_EA_BEI_BAR5 && prop <= PCI_EA_P_IO)
2461 return &dev->resource[bei];
2462 #ifdef CONFIG_PCI_IOV
2463 else if (bei >= PCI_EA_BEI_VF_BAR0 && bei <= PCI_EA_BEI_VF_BAR5 &&
2464 (prop == PCI_EA_P_VF_MEM || prop == PCI_EA_P_VF_MEM_PREFETCH))
2465 return &dev->resource[PCI_IOV_RESOURCES +
2466 bei - PCI_EA_BEI_VF_BAR0];
2468 else if (bei == PCI_EA_BEI_ROM)
2469 return &dev->resource[PCI_ROM_RESOURCE];
2474 /* Read an Enhanced Allocation (EA) entry */
2475 static int pci_ea_read(struct pci_dev *dev, int offset)
2477 struct resource *res;
2478 int ent_size, ent_offset = offset;
2479 resource_size_t start, end;
2480 unsigned long flags;
2481 u32 dw0, bei, base, max_offset;
2483 bool support_64 = (sizeof(resource_size_t) >= 8);
2485 pci_read_config_dword(dev, ent_offset, &dw0);
2488 /* Entry size field indicates DWORDs after 1st */
2489 ent_size = ((dw0 & PCI_EA_ES) + 1) << 2;
2491 if (!(dw0 & PCI_EA_ENABLE)) /* Entry not enabled */
2494 bei = (dw0 & PCI_EA_BEI) >> 4;
2495 prop = (dw0 & PCI_EA_PP) >> 8;
2498 * If the Property is in the reserved range, try the Secondary
2501 if (prop > PCI_EA_P_BRIDGE_IO && prop < PCI_EA_P_MEM_RESERVED)
2502 prop = (dw0 & PCI_EA_SP) >> 16;
2503 if (prop > PCI_EA_P_BRIDGE_IO)
2506 res = pci_ea_get_resource(dev, bei, prop);
2508 dev_err(&dev->dev, "Unsupported EA entry BEI: %u\n", bei);
2512 flags = pci_ea_flags(dev, prop);
2514 dev_err(&dev->dev, "Unsupported EA properties: %#x\n", prop);
2519 pci_read_config_dword(dev, ent_offset, &base);
2520 start = (base & PCI_EA_FIELD_MASK);
2523 /* Read MaxOffset */
2524 pci_read_config_dword(dev, ent_offset, &max_offset);
2527 /* Read Base MSBs (if 64-bit entry) */
2528 if (base & PCI_EA_IS_64) {
2531 pci_read_config_dword(dev, ent_offset, &base_upper);
2534 flags |= IORESOURCE_MEM_64;
2536 /* entry starts above 32-bit boundary, can't use */
2537 if (!support_64 && base_upper)
2541 start |= ((u64)base_upper << 32);
2544 end = start + (max_offset | 0x03);
2546 /* Read MaxOffset MSBs (if 64-bit entry) */
2547 if (max_offset & PCI_EA_IS_64) {
2548 u32 max_offset_upper;
2550 pci_read_config_dword(dev, ent_offset, &max_offset_upper);
2553 flags |= IORESOURCE_MEM_64;
2555 /* entry too big, can't use */
2556 if (!support_64 && max_offset_upper)
2560 end += ((u64)max_offset_upper << 32);
2564 dev_err(&dev->dev, "EA Entry crosses address boundary\n");
2568 if (ent_size != ent_offset - offset) {
2570 "EA Entry Size (%d) does not match length read (%d)\n",
2571 ent_size, ent_offset - offset);
2575 res->name = pci_name(dev);
2580 if (bei <= PCI_EA_BEI_BAR5)
2581 dev_printk(KERN_DEBUG, &dev->dev, "BAR %d: %pR (from Enhanced Allocation, properties %#02x)\n",
2583 else if (bei == PCI_EA_BEI_ROM)
2584 dev_printk(KERN_DEBUG, &dev->dev, "ROM: %pR (from Enhanced Allocation, properties %#02x)\n",
2586 else if (bei >= PCI_EA_BEI_VF_BAR0 && bei <= PCI_EA_BEI_VF_BAR5)
2587 dev_printk(KERN_DEBUG, &dev->dev, "VF BAR %d: %pR (from Enhanced Allocation, properties %#02x)\n",
2588 bei - PCI_EA_BEI_VF_BAR0, res, prop);
2590 dev_printk(KERN_DEBUG, &dev->dev, "BEI %d res: %pR (from Enhanced Allocation, properties %#02x)\n",
2594 return offset + ent_size;
2597 /* Enhanced Allocation Initialization */
2598 void pci_ea_init(struct pci_dev *dev)
2605 /* find PCI EA capability in list */
2606 ea = pci_find_capability(dev, PCI_CAP_ID_EA);
2610 /* determine the number of entries */
2611 pci_bus_read_config_byte(dev->bus, dev->devfn, ea + PCI_EA_NUM_ENT,
2613 num_ent &= PCI_EA_NUM_ENT_MASK;
2615 offset = ea + PCI_EA_FIRST_ENT;
2617 /* Skip DWORD 2 for type 1 functions */
2618 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE)
2621 /* parse each EA entry */
2622 for (i = 0; i < num_ent; ++i)
2623 offset = pci_ea_read(dev, offset);
2626 static void pci_add_saved_cap(struct pci_dev *pci_dev,
2627 struct pci_cap_saved_state *new_cap)
2629 hlist_add_head(&new_cap->next, &pci_dev->saved_cap_space);
2633 * _pci_add_cap_save_buffer - allocate buffer for saving given
2634 * capability registers
2635 * @dev: the PCI device
2636 * @cap: the capability to allocate the buffer for
2637 * @extended: Standard or Extended capability ID
2638 * @size: requested size of the buffer
2640 static int _pci_add_cap_save_buffer(struct pci_dev *dev, u16 cap,
2641 bool extended, unsigned int size)
2644 struct pci_cap_saved_state *save_state;
2647 pos = pci_find_ext_capability(dev, cap);
2649 pos = pci_find_capability(dev, cap);
2654 save_state = kzalloc(sizeof(*save_state) + size, GFP_KERNEL);
2658 save_state->cap.cap_nr = cap;
2659 save_state->cap.cap_extended = extended;
2660 save_state->cap.size = size;
2661 pci_add_saved_cap(dev, save_state);
2666 int pci_add_cap_save_buffer(struct pci_dev *dev, char cap, unsigned int size)
2668 return _pci_add_cap_save_buffer(dev, cap, false, size);
2671 int pci_add_ext_cap_save_buffer(struct pci_dev *dev, u16 cap, unsigned int size)
2673 return _pci_add_cap_save_buffer(dev, cap, true, size);
2677 * pci_allocate_cap_save_buffers - allocate buffers for saving capabilities
2678 * @dev: the PCI device
2680 void pci_allocate_cap_save_buffers(struct pci_dev *dev)
2684 error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_EXP,
2685 PCI_EXP_SAVE_REGS * sizeof(u16));
2688 "unable to preallocate PCI Express save buffer\n");
2690 error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_PCIX, sizeof(u16));
2693 "unable to preallocate PCI-X save buffer\n");
2695 pci_allocate_vc_save_buffers(dev);
2698 void pci_free_cap_save_buffers(struct pci_dev *dev)
2700 struct pci_cap_saved_state *tmp;
2701 struct hlist_node *n;
2703 hlist_for_each_entry_safe(tmp, n, &dev->saved_cap_space, next)
2708 * pci_configure_ari - enable or disable ARI forwarding
2709 * @dev: the PCI device
2711 * If @dev and its upstream bridge both support ARI, enable ARI in the
2712 * bridge. Otherwise, disable ARI in the bridge.
2714 void pci_configure_ari(struct pci_dev *dev)
2717 struct pci_dev *bridge;
2719 if (pcie_ari_disabled || !pci_is_pcie(dev) || dev->devfn)
2722 bridge = dev->bus->self;
2726 pcie_capability_read_dword(bridge, PCI_EXP_DEVCAP2, &cap);
2727 if (!(cap & PCI_EXP_DEVCAP2_ARI))
2730 if (pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI)) {
2731 pcie_capability_set_word(bridge, PCI_EXP_DEVCTL2,
2732 PCI_EXP_DEVCTL2_ARI);
2733 bridge->ari_enabled = 1;
2735 pcie_capability_clear_word(bridge, PCI_EXP_DEVCTL2,
2736 PCI_EXP_DEVCTL2_ARI);
2737 bridge->ari_enabled = 0;
2741 static int pci_acs_enable;
2744 * pci_request_acs - ask for ACS to be enabled if supported
2746 void pci_request_acs(void)
2752 * pci_std_enable_acs - enable ACS on devices using standard ACS capabilites
2753 * @dev: the PCI device
2755 static void pci_std_enable_acs(struct pci_dev *dev)
2761 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ACS);
2765 pci_read_config_word(dev, pos + PCI_ACS_CAP, &cap);
2766 pci_read_config_word(dev, pos + PCI_ACS_CTRL, &ctrl);
2768 /* Source Validation */
2769 ctrl |= (cap & PCI_ACS_SV);
2771 /* P2P Request Redirect */
2772 ctrl |= (cap & PCI_ACS_RR);
2774 /* P2P Completion Redirect */
2775 ctrl |= (cap & PCI_ACS_CR);
2777 /* Upstream Forwarding */
2778 ctrl |= (cap & PCI_ACS_UF);
2780 pci_write_config_word(dev, pos + PCI_ACS_CTRL, ctrl);
2784 * pci_enable_acs - enable ACS if hardware support it
2785 * @dev: the PCI device
2787 void pci_enable_acs(struct pci_dev *dev)
2789 if (!pci_acs_enable)
2792 if (!pci_dev_specific_enable_acs(dev))
2795 pci_std_enable_acs(dev);
2798 static bool pci_acs_flags_enabled(struct pci_dev *pdev, u16 acs_flags)
2803 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ACS);
2808 * Except for egress control, capabilities are either required
2809 * or only required if controllable. Features missing from the
2810 * capability field can therefore be assumed as hard-wired enabled.
2812 pci_read_config_word(pdev, pos + PCI_ACS_CAP, &cap);
2813 acs_flags &= (cap | PCI_ACS_EC);
2815 pci_read_config_word(pdev, pos + PCI_ACS_CTRL, &ctrl);
2816 return (ctrl & acs_flags) == acs_flags;
2820 * pci_acs_enabled - test ACS against required flags for a given device
2821 * @pdev: device to test
2822 * @acs_flags: required PCI ACS flags
2824 * Return true if the device supports the provided flags. Automatically
2825 * filters out flags that are not implemented on multifunction devices.
2827 * Note that this interface checks the effective ACS capabilities of the
2828 * device rather than the actual capabilities. For instance, most single
2829 * function endpoints are not required to support ACS because they have no
2830 * opportunity for peer-to-peer access. We therefore return 'true'
2831 * regardless of whether the device exposes an ACS capability. This makes
2832 * it much easier for callers of this function to ignore the actual type
2833 * or topology of the device when testing ACS support.
2835 bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags)
2839 ret = pci_dev_specific_acs_enabled(pdev, acs_flags);
2844 * Conventional PCI and PCI-X devices never support ACS, either
2845 * effectively or actually. The shared bus topology implies that
2846 * any device on the bus can receive or snoop DMA.
2848 if (!pci_is_pcie(pdev))
2851 switch (pci_pcie_type(pdev)) {
2853 * PCI/X-to-PCIe bridges are not specifically mentioned by the spec,
2854 * but since their primary interface is PCI/X, we conservatively
2855 * handle them as we would a non-PCIe device.
2857 case PCI_EXP_TYPE_PCIE_BRIDGE:
2859 * PCIe 3.0, 6.12.1 excludes ACS on these devices. "ACS is never
2860 * applicable... must never implement an ACS Extended Capability...".
2861 * This seems arbitrary, but we take a conservative interpretation
2862 * of this statement.
2864 case PCI_EXP_TYPE_PCI_BRIDGE:
2865 case PCI_EXP_TYPE_RC_EC:
2868 * PCIe 3.0, 6.12.1.1 specifies that downstream and root ports should
2869 * implement ACS in order to indicate their peer-to-peer capabilities,
2870 * regardless of whether they are single- or multi-function devices.
2872 case PCI_EXP_TYPE_DOWNSTREAM:
2873 case PCI_EXP_TYPE_ROOT_PORT:
2874 return pci_acs_flags_enabled(pdev, acs_flags);
2876 * PCIe 3.0, 6.12.1.2 specifies ACS capabilities that should be
2877 * implemented by the remaining PCIe types to indicate peer-to-peer
2878 * capabilities, but only when they are part of a multifunction
2879 * device. The footnote for section 6.12 indicates the specific
2880 * PCIe types included here.
2882 case PCI_EXP_TYPE_ENDPOINT:
2883 case PCI_EXP_TYPE_UPSTREAM:
2884 case PCI_EXP_TYPE_LEG_END:
2885 case PCI_EXP_TYPE_RC_END:
2886 if (!pdev->multifunction)
2889 return pci_acs_flags_enabled(pdev, acs_flags);
2893 * PCIe 3.0, 6.12.1.3 specifies no ACS capabilities are applicable
2894 * to single function devices with the exception of downstream ports.
2900 * pci_acs_path_enable - test ACS flags from start to end in a hierarchy
2901 * @start: starting downstream device
2902 * @end: ending upstream device or NULL to search to the root bus
2903 * @acs_flags: required flags
2905 * Walk up a device tree from start to end testing PCI ACS support. If
2906 * any step along the way does not support the required flags, return false.
2908 bool pci_acs_path_enabled(struct pci_dev *start,
2909 struct pci_dev *end, u16 acs_flags)
2911 struct pci_dev *pdev, *parent = start;
2916 if (!pci_acs_enabled(pdev, acs_flags))
2919 if (pci_is_root_bus(pdev->bus))
2920 return (end == NULL);
2922 parent = pdev->bus->self;
2923 } while (pdev != end);
2929 * pci_swizzle_interrupt_pin - swizzle INTx for device behind bridge
2930 * @dev: the PCI device
2931 * @pin: the INTx pin (1=INTA, 2=INTB, 3=INTC, 4=INTD)
2933 * Perform INTx swizzling for a device behind one level of bridge. This is
2934 * required by section 9.1 of the PCI-to-PCI bridge specification for devices
2935 * behind bridges on add-in cards. For devices with ARI enabled, the slot
2936 * number is always 0 (see the Implementation Note in section 2.2.8.1 of
2937 * the PCI Express Base Specification, Revision 2.1)
2939 u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin)
2943 if (pci_ari_enabled(dev->bus))
2946 slot = PCI_SLOT(dev->devfn);
2948 return (((pin - 1) + slot) % 4) + 1;
2951 int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge)
2959 while (!pci_is_root_bus(dev->bus)) {
2960 pin = pci_swizzle_interrupt_pin(dev, pin);
2961 dev = dev->bus->self;
2968 * pci_common_swizzle - swizzle INTx all the way to root bridge
2969 * @dev: the PCI device
2970 * @pinp: pointer to the INTx pin value (1=INTA, 2=INTB, 3=INTD, 4=INTD)
2972 * Perform INTx swizzling for a device. This traverses through all PCI-to-PCI
2973 * bridges all the way up to a PCI root bus.
2975 u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp)
2979 while (!pci_is_root_bus(dev->bus)) {
2980 pin = pci_swizzle_interrupt_pin(dev, pin);
2981 dev = dev->bus->self;
2984 return PCI_SLOT(dev->devfn);
2986 EXPORT_SYMBOL_GPL(pci_common_swizzle);
2989 * pci_release_region - Release a PCI bar
2990 * @pdev: PCI device whose resources were previously reserved by pci_request_region
2991 * @bar: BAR to release
2993 * Releases the PCI I/O and memory resources previously reserved by a
2994 * successful call to pci_request_region. Call this function only
2995 * after all use of the PCI regions has ceased.
2997 void pci_release_region(struct pci_dev *pdev, int bar)
2999 struct pci_devres *dr;
3001 if (pci_resource_len(pdev, bar) == 0)
3003 if (pci_resource_flags(pdev, bar) & IORESOURCE_IO)
3004 release_region(pci_resource_start(pdev, bar),
3005 pci_resource_len(pdev, bar));
3006 else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM)
3007 release_mem_region(pci_resource_start(pdev, bar),
3008 pci_resource_len(pdev, bar));
3010 dr = find_pci_dr(pdev);
3012 dr->region_mask &= ~(1 << bar);
3014 EXPORT_SYMBOL(pci_release_region);
3017 * __pci_request_region - Reserved PCI I/O and memory resource
3018 * @pdev: PCI device whose resources are to be reserved
3019 * @bar: BAR to be reserved
3020 * @res_name: Name to be associated with resource.
3021 * @exclusive: whether the region access is exclusive or not
3023 * Mark the PCI region associated with PCI device @pdev BR @bar as
3024 * being reserved by owner @res_name. Do not access any
3025 * address inside the PCI regions unless this call returns
3028 * If @exclusive is set, then the region is marked so that userspace
3029 * is explicitly not allowed to map the resource via /dev/mem or
3030 * sysfs MMIO access.
3032 * Returns 0 on success, or %EBUSY on error. A warning
3033 * message is also printed on failure.
3035 static int __pci_request_region(struct pci_dev *pdev, int bar,
3036 const char *res_name, int exclusive)
3038 struct pci_devres *dr;
3040 if (pci_resource_len(pdev, bar) == 0)
3043 if (pci_resource_flags(pdev, bar) & IORESOURCE_IO) {
3044 if (!request_region(pci_resource_start(pdev, bar),
3045 pci_resource_len(pdev, bar), res_name))
3047 } else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) {
3048 if (!__request_mem_region(pci_resource_start(pdev, bar),
3049 pci_resource_len(pdev, bar), res_name,
3054 dr = find_pci_dr(pdev);
3056 dr->region_mask |= 1 << bar;
3061 dev_warn(&pdev->dev, "BAR %d: can't reserve %pR\n", bar,
3062 &pdev->resource[bar]);
3067 * pci_request_region - Reserve PCI I/O and memory resource
3068 * @pdev: PCI device whose resources are to be reserved
3069 * @bar: BAR to be reserved
3070 * @res_name: Name to be associated with resource
3072 * Mark the PCI region associated with PCI device @pdev BAR @bar as
3073 * being reserved by owner @res_name. Do not access any
3074 * address inside the PCI regions unless this call returns
3077 * Returns 0 on success, or %EBUSY on error. A warning
3078 * message is also printed on failure.
3080 int pci_request_region(struct pci_dev *pdev, int bar, const char *res_name)
3082 return __pci_request_region(pdev, bar, res_name, 0);
3084 EXPORT_SYMBOL(pci_request_region);
3087 * pci_request_region_exclusive - Reserved PCI I/O and memory resource
3088 * @pdev: PCI device whose resources are to be reserved
3089 * @bar: BAR to be reserved
3090 * @res_name: Name to be associated with resource.
3092 * Mark the PCI region associated with PCI device @pdev BR @bar as
3093 * being reserved by owner @res_name. Do not access any
3094 * address inside the PCI regions unless this call returns
3097 * Returns 0 on success, or %EBUSY on error. A warning
3098 * message is also printed on failure.
3100 * The key difference that _exclusive makes it that userspace is
3101 * explicitly not allowed to map the resource via /dev/mem or
3104 int pci_request_region_exclusive(struct pci_dev *pdev, int bar,
3105 const char *res_name)
3107 return __pci_request_region(pdev, bar, res_name, IORESOURCE_EXCLUSIVE);
3109 EXPORT_SYMBOL(pci_request_region_exclusive);
3112 * pci_release_selected_regions - Release selected PCI I/O and memory resources
3113 * @pdev: PCI device whose resources were previously reserved
3114 * @bars: Bitmask of BARs to be released
3116 * Release selected PCI I/O and memory resources previously reserved.
3117 * Call this function only after all use of the PCI regions has ceased.
3119 void pci_release_selected_regions(struct pci_dev *pdev, int bars)
3123 for (i = 0; i < 6; i++)
3124 if (bars & (1 << i))
3125 pci_release_region(pdev, i);
3127 EXPORT_SYMBOL(pci_release_selected_regions);
3129 static int __pci_request_selected_regions(struct pci_dev *pdev, int bars,
3130 const char *res_name, int excl)
3134 for (i = 0; i < 6; i++)
3135 if (bars & (1 << i))
3136 if (__pci_request_region(pdev, i, res_name, excl))
3142 if (bars & (1 << i))
3143 pci_release_region(pdev, i);
3150 * pci_request_selected_regions - Reserve selected PCI I/O and memory resources
3151 * @pdev: PCI device whose resources are to be reserved
3152 * @bars: Bitmask of BARs to be requested
3153 * @res_name: Name to be associated with resource
3155 int pci_request_selected_regions(struct pci_dev *pdev, int bars,
3156 const char *res_name)
3158 return __pci_request_selected_regions(pdev, bars, res_name, 0);
3160 EXPORT_SYMBOL(pci_request_selected_regions);
3162 int pci_request_selected_regions_exclusive(struct pci_dev *pdev, int bars,
3163 const char *res_name)
3165 return __pci_request_selected_regions(pdev, bars, res_name,
3166 IORESOURCE_EXCLUSIVE);
3168 EXPORT_SYMBOL(pci_request_selected_regions_exclusive);
3171 * pci_release_regions - Release reserved PCI I/O and memory resources
3172 * @pdev: PCI device whose resources were previously reserved by pci_request_regions
3174 * Releases all PCI I/O and memory resources previously reserved by a
3175 * successful call to pci_request_regions. Call this function only
3176 * after all use of the PCI regions has ceased.
3179 void pci_release_regions(struct pci_dev *pdev)
3181 pci_release_selected_regions(pdev, (1 << 6) - 1);
3183 EXPORT_SYMBOL(pci_release_regions);
3186 * pci_request_regions - Reserved PCI I/O and memory resources
3187 * @pdev: PCI device whose resources are to be reserved
3188 * @res_name: Name to be associated with resource.
3190 * Mark all PCI regions associated with PCI device @pdev as
3191 * being reserved by owner @res_name. Do not access any
3192 * address inside the PCI regions unless this call returns
3195 * Returns 0 on success, or %EBUSY on error. A warning
3196 * message is also printed on failure.
3198 int pci_request_regions(struct pci_dev *pdev, const char *res_name)
3200 return pci_request_selected_regions(pdev, ((1 << 6) - 1), res_name);
3202 EXPORT_SYMBOL(pci_request_regions);
3205 * pci_request_regions_exclusive - Reserved PCI I/O and memory resources
3206 * @pdev: PCI device whose resources are to be reserved
3207 * @res_name: Name to be associated with resource.
3209 * Mark all PCI regions associated with PCI device @pdev as
3210 * being reserved by owner @res_name. Do not access any
3211 * address inside the PCI regions unless this call returns
3214 * pci_request_regions_exclusive() will mark the region so that
3215 * /dev/mem and the sysfs MMIO access will not be allowed.
3217 * Returns 0 on success, or %EBUSY on error. A warning
3218 * message is also printed on failure.
3220 int pci_request_regions_exclusive(struct pci_dev *pdev, const char *res_name)
3222 return pci_request_selected_regions_exclusive(pdev,
3223 ((1 << 6) - 1), res_name);
3225 EXPORT_SYMBOL(pci_request_regions_exclusive);
3229 struct list_head list;
3231 resource_size_t size;
3234 static LIST_HEAD(io_range_list);
3235 static DEFINE_SPINLOCK(io_range_lock);
3239 * Record the PCI IO range (expressed as CPU physical address + size).
3240 * Return a negative value if an error has occured, zero otherwise
3242 int __weak pci_register_io_range(phys_addr_t addr, resource_size_t size)
3247 struct io_range *range;
3248 resource_size_t allocated_size = 0;
3250 /* check if the range hasn't been previously recorded */
3251 spin_lock(&io_range_lock);
3252 list_for_each_entry(range, &io_range_list, list) {
3253 if (addr >= range->start && addr + size <= range->start + size) {
3254 /* range already registered, bail out */
3257 allocated_size += range->size;
3260 /* range not registed yet, check for available space */
3261 if (allocated_size + size - 1 > IO_SPACE_LIMIT) {
3262 /* if it's too big check if 64K space can be reserved */
3263 if (allocated_size + SZ_64K - 1 > IO_SPACE_LIMIT) {
3269 pr_warn("Requested IO range too big, new size set to 64K\n");
3272 /* add the range to the list */
3273 range = kzalloc(sizeof(*range), GFP_ATOMIC);
3279 range->start = addr;
3282 list_add_tail(&range->list, &io_range_list);
3285 spin_unlock(&io_range_lock);
3291 phys_addr_t pci_pio_to_address(unsigned long pio)
3293 phys_addr_t address = (phys_addr_t)OF_BAD_ADDR;
3296 struct io_range *range;
3297 resource_size_t allocated_size = 0;
3299 if (pio > IO_SPACE_LIMIT)
3302 spin_lock(&io_range_lock);
3303 list_for_each_entry(range, &io_range_list, list) {
3304 if (pio >= allocated_size && pio < allocated_size + range->size) {
3305 address = range->start + pio - allocated_size;
3308 allocated_size += range->size;
3310 spin_unlock(&io_range_lock);
3316 unsigned long __weak pci_address_to_pio(phys_addr_t address)
3319 struct io_range *res;
3320 resource_size_t offset = 0;
3321 unsigned long addr = -1;
3323 spin_lock(&io_range_lock);
3324 list_for_each_entry(res, &io_range_list, list) {
3325 if (address >= res->start && address < res->start + res->size) {
3326 addr = address - res->start + offset;
3329 offset += res->size;
3331 spin_unlock(&io_range_lock);
3335 if (address > IO_SPACE_LIMIT)
3336 return (unsigned long)-1;
3338 return (unsigned long) address;
3343 * pci_remap_iospace - Remap the memory mapped I/O space
3344 * @res: Resource describing the I/O space
3345 * @phys_addr: physical address of range to be mapped
3347 * Remap the memory mapped I/O space described by the @res
3348 * and the CPU physical address @phys_addr into virtual address space.
3349 * Only architectures that have memory mapped IO functions defined
3350 * (and the PCI_IOBASE value defined) should call this function.
3352 int __weak pci_remap_iospace(const struct resource *res, phys_addr_t phys_addr)
3354 #if defined(PCI_IOBASE) && defined(CONFIG_MMU)
3355 unsigned long vaddr = (unsigned long)PCI_IOBASE + res->start;
3357 if (!(res->flags & IORESOURCE_IO))
3360 if (res->end > IO_SPACE_LIMIT)
3363 return ioremap_page_range(vaddr, vaddr + resource_size(res), phys_addr,
3364 pgprot_device(PAGE_KERNEL));
3366 /* this architecture does not have memory mapped I/O space,
3367 so this function should never be called */
3368 WARN_ONCE(1, "This architecture does not support memory mapped I/O\n");
3374 * pci_unmap_iospace - Unmap the memory mapped I/O space
3375 * @res: resource to be unmapped
3377 * Unmap the CPU virtual address @res from virtual address space.
3378 * Only architectures that have memory mapped IO functions defined
3379 * (and the PCI_IOBASE value defined) should call this function.
3381 void pci_unmap_iospace(struct resource *res)
3383 #if defined(PCI_IOBASE) && defined(CONFIG_MMU)
3384 unsigned long vaddr = (unsigned long)PCI_IOBASE + res->start;
3386 unmap_kernel_range(vaddr, resource_size(res));
3390 static void __pci_set_master(struct pci_dev *dev, bool enable)
3394 pci_read_config_word(dev, PCI_COMMAND, &old_cmd);
3396 cmd = old_cmd | PCI_COMMAND_MASTER;
3398 cmd = old_cmd & ~PCI_COMMAND_MASTER;
3399 if (cmd != old_cmd) {
3400 dev_dbg(&dev->dev, "%s bus mastering\n",
3401 enable ? "enabling" : "disabling");
3402 pci_write_config_word(dev, PCI_COMMAND, cmd);
3404 dev->is_busmaster = enable;
3408 * pcibios_setup - process "pci=" kernel boot arguments
3409 * @str: string used to pass in "pci=" kernel boot arguments
3411 * Process kernel boot arguments. This is the default implementation.
3412 * Architecture specific implementations can override this as necessary.
3414 char * __weak __init pcibios_setup(char *str)
3420 * pcibios_set_master - enable PCI bus-mastering for device dev
3421 * @dev: the PCI device to enable
3423 * Enables PCI bus-mastering for the device. This is the default
3424 * implementation. Architecture specific implementations can override
3425 * this if necessary.
3427 void __weak pcibios_set_master(struct pci_dev *dev)
3431 /* The latency timer doesn't apply to PCIe (either Type 0 or Type 1) */
3432 if (pci_is_pcie(dev))
3435 pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat);
3437 lat = (64 <= pcibios_max_latency) ? 64 : pcibios_max_latency;
3438 else if (lat > pcibios_max_latency)
3439 lat = pcibios_max_latency;
3443 pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat);
3447 * pci_set_master - enables bus-mastering for device dev
3448 * @dev: the PCI device to enable
3450 * Enables bus-mastering on the device and calls pcibios_set_master()
3451 * to do the needed arch specific settings.
3453 void pci_set_master(struct pci_dev *dev)
3455 __pci_set_master(dev, true);
3456 pcibios_set_master(dev);
3458 EXPORT_SYMBOL(pci_set_master);
3461 * pci_clear_master - disables bus-mastering for device dev
3462 * @dev: the PCI device to disable
3464 void pci_clear_master(struct pci_dev *dev)
3466 __pci_set_master(dev, false);
3468 EXPORT_SYMBOL(pci_clear_master);
3471 * pci_set_cacheline_size - ensure the CACHE_LINE_SIZE register is programmed
3472 * @dev: the PCI device for which MWI is to be enabled
3474 * Helper function for pci_set_mwi.
3475 * Originally copied from drivers/net/acenic.c.
3476 * Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>.
3478 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
3480 int pci_set_cacheline_size(struct pci_dev *dev)
3484 if (!pci_cache_line_size)
3487 /* Validate current setting: the PCI_CACHE_LINE_SIZE must be
3488 equal to or multiple of the right value. */
3489 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
3490 if (cacheline_size >= pci_cache_line_size &&
3491 (cacheline_size % pci_cache_line_size) == 0)
3494 /* Write the correct value. */
3495 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, pci_cache_line_size);
3497 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
3498 if (cacheline_size == pci_cache_line_size)
3501 dev_printk(KERN_DEBUG, &dev->dev, "cache line size of %d is not supported\n",
3502 pci_cache_line_size << 2);
3506 EXPORT_SYMBOL_GPL(pci_set_cacheline_size);
3509 * pci_set_mwi - enables memory-write-invalidate PCI transaction
3510 * @dev: the PCI device for which MWI is enabled
3512 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
3514 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
3516 int pci_set_mwi(struct pci_dev *dev)
3518 #ifdef PCI_DISABLE_MWI
3524 rc = pci_set_cacheline_size(dev);
3528 pci_read_config_word(dev, PCI_COMMAND, &cmd);
3529 if (!(cmd & PCI_COMMAND_INVALIDATE)) {
3530 dev_dbg(&dev->dev, "enabling Mem-Wr-Inval\n");
3531 cmd |= PCI_COMMAND_INVALIDATE;
3532 pci_write_config_word(dev, PCI_COMMAND, cmd);
3537 EXPORT_SYMBOL(pci_set_mwi);
3540 * pci_try_set_mwi - enables memory-write-invalidate PCI transaction
3541 * @dev: the PCI device for which MWI is enabled
3543 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
3544 * Callers are not required to check the return value.
3546 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
3548 int pci_try_set_mwi(struct pci_dev *dev)
3550 #ifdef PCI_DISABLE_MWI
3553 return pci_set_mwi(dev);
3556 EXPORT_SYMBOL(pci_try_set_mwi);
3559 * pci_clear_mwi - disables Memory-Write-Invalidate for device dev
3560 * @dev: the PCI device to disable
3562 * Disables PCI Memory-Write-Invalidate transaction on the device
3564 void pci_clear_mwi(struct pci_dev *dev)
3566 #ifndef PCI_DISABLE_MWI
3569 pci_read_config_word(dev, PCI_COMMAND, &cmd);
3570 if (cmd & PCI_COMMAND_INVALIDATE) {
3571 cmd &= ~PCI_COMMAND_INVALIDATE;
3572 pci_write_config_word(dev, PCI_COMMAND, cmd);
3576 EXPORT_SYMBOL(pci_clear_mwi);
3579 * pci_intx - enables/disables PCI INTx for device dev
3580 * @pdev: the PCI device to operate on
3581 * @enable: boolean: whether to enable or disable PCI INTx
3583 * Enables/disables PCI INTx for device dev
3585 void pci_intx(struct pci_dev *pdev, int enable)
3587 u16 pci_command, new;
3589 pci_read_config_word(pdev, PCI_COMMAND, &pci_command);
3592 new = pci_command & ~PCI_COMMAND_INTX_DISABLE;
3594 new = pci_command | PCI_COMMAND_INTX_DISABLE;
3596 if (new != pci_command) {
3597 struct pci_devres *dr;
3599 pci_write_config_word(pdev, PCI_COMMAND, new);
3601 dr = find_pci_dr(pdev);
3602 if (dr && !dr->restore_intx) {
3603 dr->restore_intx = 1;
3604 dr->orig_intx = !enable;
3608 EXPORT_SYMBOL_GPL(pci_intx);
3611 * pci_intx_mask_supported - probe for INTx masking support
3612 * @dev: the PCI device to operate on
3614 * Check if the device dev support INTx masking via the config space
3617 bool pci_intx_mask_supported(struct pci_dev *dev)
3619 bool mask_supported = false;
3622 if (dev->broken_intx_masking)
3625 pci_cfg_access_lock(dev);
3627 pci_read_config_word(dev, PCI_COMMAND, &orig);
3628 pci_write_config_word(dev, PCI_COMMAND,
3629 orig ^ PCI_COMMAND_INTX_DISABLE);
3630 pci_read_config_word(dev, PCI_COMMAND, &new);
3633 * There's no way to protect against hardware bugs or detect them
3634 * reliably, but as long as we know what the value should be, let's
3635 * go ahead and check it.
3637 if ((new ^ orig) & ~PCI_COMMAND_INTX_DISABLE) {
3638 dev_err(&dev->dev, "Command register changed from 0x%x to 0x%x: driver or hardware bug?\n",
3640 } else if ((new ^ orig) & PCI_COMMAND_INTX_DISABLE) {
3641 mask_supported = true;
3642 pci_write_config_word(dev, PCI_COMMAND, orig);
3645 pci_cfg_access_unlock(dev);
3646 return mask_supported;
3648 EXPORT_SYMBOL_GPL(pci_intx_mask_supported);
3650 static bool pci_check_and_set_intx_mask(struct pci_dev *dev, bool mask)
3652 struct pci_bus *bus = dev->bus;
3653 bool mask_updated = true;
3654 u32 cmd_status_dword;
3655 u16 origcmd, newcmd;
3656 unsigned long flags;
3660 * We do a single dword read to retrieve both command and status.
3661 * Document assumptions that make this possible.
3663 BUILD_BUG_ON(PCI_COMMAND % 4);
3664 BUILD_BUG_ON(PCI_COMMAND + 2 != PCI_STATUS);
3666 raw_spin_lock_irqsave(&pci_lock, flags);
3668 bus->ops->read(bus, dev->devfn, PCI_COMMAND, 4, &cmd_status_dword);
3670 irq_pending = (cmd_status_dword >> 16) & PCI_STATUS_INTERRUPT;
3673 * Check interrupt status register to see whether our device
3674 * triggered the interrupt (when masking) or the next IRQ is
3675 * already pending (when unmasking).
3677 if (mask != irq_pending) {
3678 mask_updated = false;
3682 origcmd = cmd_status_dword;
3683 newcmd = origcmd & ~PCI_COMMAND_INTX_DISABLE;
3685 newcmd |= PCI_COMMAND_INTX_DISABLE;
3686 if (newcmd != origcmd)
3687 bus->ops->write(bus, dev->devfn, PCI_COMMAND, 2, newcmd);
3690 raw_spin_unlock_irqrestore(&pci_lock, flags);
3692 return mask_updated;
3696 * pci_check_and_mask_intx - mask INTx on pending interrupt
3697 * @dev: the PCI device to operate on
3699 * Check if the device dev has its INTx line asserted, mask it and
3700 * return true in that case. False is returned if not interrupt was
3703 bool pci_check_and_mask_intx(struct pci_dev *dev)
3705 return pci_check_and_set_intx_mask(dev, true);
3707 EXPORT_SYMBOL_GPL(pci_check_and_mask_intx);
3710 * pci_check_and_unmask_intx - unmask INTx if no interrupt is pending
3711 * @dev: the PCI device to operate on
3713 * Check if the device dev has its INTx line asserted, unmask it if not
3714 * and return true. False is returned and the mask remains active if
3715 * there was still an interrupt pending.
3717 bool pci_check_and_unmask_intx(struct pci_dev *dev)
3719 return pci_check_and_set_intx_mask(dev, false);
3721 EXPORT_SYMBOL_GPL(pci_check_and_unmask_intx);
3724 * pci_wait_for_pending_transaction - waits for pending transaction
3725 * @dev: the PCI device to operate on
3727 * Return 0 if transaction is pending 1 otherwise.
3729 int pci_wait_for_pending_transaction(struct pci_dev *dev)
3731 if (!pci_is_pcie(dev))
3734 return pci_wait_for_pending(dev, pci_pcie_cap(dev) + PCI_EXP_DEVSTA,
3735 PCI_EXP_DEVSTA_TRPND);
3737 EXPORT_SYMBOL(pci_wait_for_pending_transaction);
3740 * We should only need to wait 100ms after FLR, but some devices take longer.
3741 * Wait for up to 1000ms for config space to return something other than -1.
3742 * Intel IGD requires this when an LCD panel is attached. We read the 2nd
3743 * dword because VFs don't implement the 1st dword.
3745 static void pci_flr_wait(struct pci_dev *dev)
3752 pci_read_config_dword(dev, PCI_COMMAND, &id);
3753 } while (i++ < 10 && id == ~0);
3756 dev_warn(&dev->dev, "Failed to return from FLR\n");
3758 dev_info(&dev->dev, "Required additional %dms to return from FLR\n",
3762 static int pcie_flr(struct pci_dev *dev, int probe)
3766 pcie_capability_read_dword(dev, PCI_EXP_DEVCAP, &cap);
3767 if (!(cap & PCI_EXP_DEVCAP_FLR))
3773 if (!pci_wait_for_pending_transaction(dev))
3774 dev_err(&dev->dev, "timed out waiting for pending transaction; performing function level reset anyway\n");
3776 pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_BCR_FLR);
3781 static int pci_af_flr(struct pci_dev *dev, int probe)
3786 pos = pci_find_capability(dev, PCI_CAP_ID_AF);
3790 pci_read_config_byte(dev, pos + PCI_AF_CAP, &cap);
3791 if (!(cap & PCI_AF_CAP_TP) || !(cap & PCI_AF_CAP_FLR))
3798 * Wait for Transaction Pending bit to clear. A word-aligned test
3799 * is used, so we use the conrol offset rather than status and shift
3800 * the test bit to match.
3802 if (!pci_wait_for_pending(dev, pos + PCI_AF_CTRL,
3803 PCI_AF_STATUS_TP << 8))
3804 dev_err(&dev->dev, "timed out waiting for pending transaction; performing AF function level reset anyway\n");
3806 pci_write_config_byte(dev, pos + PCI_AF_CTRL, PCI_AF_CTRL_FLR);
3812 * pci_pm_reset - Put device into PCI_D3 and back into PCI_D0.
3813 * @dev: Device to reset.
3814 * @probe: If set, only check if the device can be reset this way.
3816 * If @dev supports native PCI PM and its PCI_PM_CTRL_NO_SOFT_RESET flag is
3817 * unset, it will be reinitialized internally when going from PCI_D3hot to
3818 * PCI_D0. If that's the case and the device is not in a low-power state
3819 * already, force it into PCI_D3hot and back to PCI_D0, causing it to be reset.
3821 * NOTE: This causes the caller to sleep for twice the device power transition
3822 * cooldown period, which for the D0->D3hot and D3hot->D0 transitions is 10 ms
3823 * by default (i.e. unless the @dev's d3_delay field has a different value).
3824 * Moreover, only devices in D0 can be reset by this function.
3826 static int pci_pm_reset(struct pci_dev *dev, int probe)
3830 if (!dev->pm_cap || dev->dev_flags & PCI_DEV_FLAGS_NO_PM_RESET)
3833 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &csr);
3834 if (csr & PCI_PM_CTRL_NO_SOFT_RESET)
3840 if (dev->current_state != PCI_D0)
3843 csr &= ~PCI_PM_CTRL_STATE_MASK;
3845 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr);
3846 pci_dev_d3_sleep(dev);
3848 csr &= ~PCI_PM_CTRL_STATE_MASK;
3850 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr);
3851 pci_dev_d3_sleep(dev);
3856 void pci_reset_secondary_bus(struct pci_dev *dev)
3860 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &ctrl);
3861 ctrl |= PCI_BRIDGE_CTL_BUS_RESET;
3862 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, ctrl);
3864 * PCI spec v3.0 7.6.4.2 requires minimum Trst of 1ms. Double
3865 * this to 2ms to ensure that we meet the minimum requirement.
3869 ctrl &= ~PCI_BRIDGE_CTL_BUS_RESET;
3870 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, ctrl);
3873 * Trhfa for conventional PCI is 2^25 clock cycles.
3874 * Assuming a minimum 33MHz clock this results in a 1s
3875 * delay before we can consider subordinate devices to
3876 * be re-initialized. PCIe has some ways to shorten this,
3877 * but we don't make use of them yet.
3882 void __weak pcibios_reset_secondary_bus(struct pci_dev *dev)
3884 pci_reset_secondary_bus(dev);
3888 * pci_reset_bridge_secondary_bus - Reset the secondary bus on a PCI bridge.
3889 * @dev: Bridge device
3891 * Use the bridge control register to assert reset on the secondary bus.
3892 * Devices on the secondary bus are left in power-on state.
3894 void pci_reset_bridge_secondary_bus(struct pci_dev *dev)
3896 pcibios_reset_secondary_bus(dev);
3898 EXPORT_SYMBOL_GPL(pci_reset_bridge_secondary_bus);
3900 static int pci_parent_bus_reset(struct pci_dev *dev, int probe)
3902 struct pci_dev *pdev;
3904 if (pci_is_root_bus(dev->bus) || dev->subordinate ||
3905 !dev->bus->self || dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET)
3908 list_for_each_entry(pdev, &dev->bus->devices, bus_list)
3915 pci_reset_bridge_secondary_bus(dev->bus->self);
3920 static int pci_reset_hotplug_slot(struct hotplug_slot *hotplug, int probe)
3924 if (!hotplug || !try_module_get(hotplug->ops->owner))
3927 if (hotplug->ops->reset_slot)
3928 rc = hotplug->ops->reset_slot(hotplug, probe);
3930 module_put(hotplug->ops->owner);
3935 static int pci_dev_reset_slot_function(struct pci_dev *dev, int probe)
3937 struct pci_dev *pdev;
3939 if (dev->subordinate || !dev->slot ||
3940 dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET)
3943 list_for_each_entry(pdev, &dev->bus->devices, bus_list)
3944 if (pdev != dev && pdev->slot == dev->slot)
3947 return pci_reset_hotplug_slot(dev->slot->hotplug, probe);
3950 static int __pci_dev_reset(struct pci_dev *dev, int probe)
3956 rc = pci_dev_specific_reset(dev, probe);
3960 rc = pcie_flr(dev, probe);
3964 rc = pci_af_flr(dev, probe);
3968 rc = pci_pm_reset(dev, probe);
3972 rc = pci_dev_reset_slot_function(dev, probe);
3976 rc = pci_parent_bus_reset(dev, probe);
3981 static void pci_dev_lock(struct pci_dev *dev)
3983 pci_cfg_access_lock(dev);
3984 /* block PM suspend, driver probe, etc. */
3985 device_lock(&dev->dev);
3988 /* Return 1 on successful lock, 0 on contention */
3989 static int pci_dev_trylock(struct pci_dev *dev)
3991 if (pci_cfg_access_trylock(dev)) {
3992 if (device_trylock(&dev->dev))
3994 pci_cfg_access_unlock(dev);
4000 static void pci_dev_unlock(struct pci_dev *dev)
4002 device_unlock(&dev->dev);
4003 pci_cfg_access_unlock(dev);
4007 * pci_reset_notify - notify device driver of reset
4008 * @dev: device to be notified of reset
4009 * @prepare: 'true' if device is about to be reset; 'false' if reset attempt
4012 * Must be called prior to device access being disabled and after device
4013 * access is restored.
4015 static void pci_reset_notify(struct pci_dev *dev, bool prepare)
4017 const struct pci_error_handlers *err_handler =
4018 dev->driver ? dev->driver->err_handler : NULL;
4019 if (err_handler && err_handler->reset_notify)
4020 err_handler->reset_notify(dev, prepare);
4023 static void pci_dev_save_and_disable(struct pci_dev *dev)
4025 pci_reset_notify(dev, true);
4028 * Wake-up device prior to save. PM registers default to D0 after
4029 * reset and a simple register restore doesn't reliably return
4030 * to a non-D0 state anyway.
4032 pci_set_power_state(dev, PCI_D0);
4034 pci_save_state(dev);
4036 * Disable the device by clearing the Command register, except for
4037 * INTx-disable which is set. This not only disables MMIO and I/O port
4038 * BARs, but also prevents the device from being Bus Master, preventing
4039 * DMA from the device including MSI/MSI-X interrupts. For PCI 2.3
4040 * compliant devices, INTx-disable prevents legacy interrupts.
4042 pci_write_config_word(dev, PCI_COMMAND, PCI_COMMAND_INTX_DISABLE);
4045 static void pci_dev_restore(struct pci_dev *dev)
4047 pci_restore_state(dev);
4048 pci_reset_notify(dev, false);
4051 static int pci_dev_reset(struct pci_dev *dev, int probe)
4058 rc = __pci_dev_reset(dev, probe);
4061 pci_dev_unlock(dev);
4067 * __pci_reset_function - reset a PCI device function
4068 * @dev: PCI device to reset
4070 * Some devices allow an individual function to be reset without affecting
4071 * other functions in the same device. The PCI device must be responsive
4072 * to PCI config space in order to use this function.
4074 * The device function is presumed to be unused when this function is called.
4075 * Resetting the device will make the contents of PCI configuration space
4076 * random, so any caller of this must be prepared to reinitialise the
4077 * device including MSI, bus mastering, BARs, decoding IO and memory spaces,
4080 * Returns 0 if the device function was successfully reset or negative if the
4081 * device doesn't support resetting a single function.
4083 int __pci_reset_function(struct pci_dev *dev)
4085 return pci_dev_reset(dev, 0);
4087 EXPORT_SYMBOL_GPL(__pci_reset_function);
4090 * __pci_reset_function_locked - reset a PCI device function while holding
4091 * the @dev mutex lock.
4092 * @dev: PCI device to reset
4094 * Some devices allow an individual function to be reset without affecting
4095 * other functions in the same device. The PCI device must be responsive
4096 * to PCI config space in order to use this function.
4098 * The device function is presumed to be unused and the caller is holding
4099 * the device mutex lock when this function is called.
4100 * Resetting the device will make the contents of PCI configuration space
4101 * random, so any caller of this must be prepared to reinitialise the
4102 * device including MSI, bus mastering, BARs, decoding IO and memory spaces,
4105 * Returns 0 if the device function was successfully reset or negative if the
4106 * device doesn't support resetting a single function.
4108 int __pci_reset_function_locked(struct pci_dev *dev)
4110 return __pci_dev_reset(dev, 0);
4112 EXPORT_SYMBOL_GPL(__pci_reset_function_locked);
4115 * pci_probe_reset_function - check whether the device can be safely reset
4116 * @dev: PCI device to reset
4118 * Some devices allow an individual function to be reset without affecting
4119 * other functions in the same device. The PCI device must be responsive
4120 * to PCI config space in order to use this function.
4122 * Returns 0 if the device function can be reset or negative if the
4123 * device doesn't support resetting a single function.
4125 int pci_probe_reset_function(struct pci_dev *dev)
4127 return pci_dev_reset(dev, 1);
4131 * pci_reset_function - quiesce and reset a PCI device function
4132 * @dev: PCI device to reset
4134 * Some devices allow an individual function to be reset without affecting
4135 * other functions in the same device. The PCI device must be responsive
4136 * to PCI config space in order to use this function.
4138 * This function does not just reset the PCI portion of a device, but
4139 * clears all the state associated with the device. This function differs
4140 * from __pci_reset_function in that it saves and restores device state
4143 * Returns 0 if the device function was successfully reset or negative if the
4144 * device doesn't support resetting a single function.
4146 int pci_reset_function(struct pci_dev *dev)
4150 rc = pci_dev_reset(dev, 1);
4154 pci_dev_save_and_disable(dev);
4156 rc = pci_dev_reset(dev, 0);
4158 pci_dev_restore(dev);
4162 EXPORT_SYMBOL_GPL(pci_reset_function);
4165 * pci_try_reset_function - quiesce and reset a PCI device function
4166 * @dev: PCI device to reset
4168 * Same as above, except return -EAGAIN if unable to lock device.
4170 int pci_try_reset_function(struct pci_dev *dev)
4174 rc = pci_dev_reset(dev, 1);
4178 pci_dev_save_and_disable(dev);
4180 if (pci_dev_trylock(dev)) {
4181 rc = __pci_dev_reset(dev, 0);
4182 pci_dev_unlock(dev);
4186 pci_dev_restore(dev);
4190 EXPORT_SYMBOL_GPL(pci_try_reset_function);
4192 /* Do any devices on or below this bus prevent a bus reset? */
4193 static bool pci_bus_resetable(struct pci_bus *bus)
4195 struct pci_dev *dev;
4197 list_for_each_entry(dev, &bus->devices, bus_list) {
4198 if (dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET ||
4199 (dev->subordinate && !pci_bus_resetable(dev->subordinate)))
4206 /* Lock devices from the top of the tree down */
4207 static void pci_bus_lock(struct pci_bus *bus)
4209 struct pci_dev *dev;
4211 list_for_each_entry(dev, &bus->devices, bus_list) {
4213 if (dev->subordinate)
4214 pci_bus_lock(dev->subordinate);
4218 /* Unlock devices from the bottom of the tree up */
4219 static void pci_bus_unlock(struct pci_bus *bus)
4221 struct pci_dev *dev;
4223 list_for_each_entry(dev, &bus->devices, bus_list) {
4224 if (dev->subordinate)
4225 pci_bus_unlock(dev->subordinate);
4226 pci_dev_unlock(dev);
4230 /* Return 1 on successful lock, 0 on contention */
4231 static int pci_bus_trylock(struct pci_bus *bus)
4233 struct pci_dev *dev;
4235 list_for_each_entry(dev, &bus->devices, bus_list) {
4236 if (!pci_dev_trylock(dev))
4238 if (dev->subordinate) {
4239 if (!pci_bus_trylock(dev->subordinate)) {
4240 pci_dev_unlock(dev);
4248 list_for_each_entry_continue_reverse(dev, &bus->devices, bus_list) {
4249 if (dev->subordinate)
4250 pci_bus_unlock(dev->subordinate);
4251 pci_dev_unlock(dev);
4256 /* Do any devices on or below this slot prevent a bus reset? */
4257 static bool pci_slot_resetable(struct pci_slot *slot)
4259 struct pci_dev *dev;
4261 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
4262 if (!dev->slot || dev->slot != slot)
4264 if (dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET ||
4265 (dev->subordinate && !pci_bus_resetable(dev->subordinate)))
4272 /* Lock devices from the top of the tree down */
4273 static void pci_slot_lock(struct pci_slot *slot)
4275 struct pci_dev *dev;
4277 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
4278 if (!dev->slot || dev->slot != slot)
4281 if (dev->subordinate)
4282 pci_bus_lock(dev->subordinate);
4286 /* Unlock devices from the bottom of the tree up */
4287 static void pci_slot_unlock(struct pci_slot *slot)
4289 struct pci_dev *dev;
4291 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
4292 if (!dev->slot || dev->slot != slot)
4294 if (dev->subordinate)
4295 pci_bus_unlock(dev->subordinate);
4296 pci_dev_unlock(dev);
4300 /* Return 1 on successful lock, 0 on contention */
4301 static int pci_slot_trylock(struct pci_slot *slot)
4303 struct pci_dev *dev;
4305 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
4306 if (!dev->slot || dev->slot != slot)
4308 if (!pci_dev_trylock(dev))
4310 if (dev->subordinate) {
4311 if (!pci_bus_trylock(dev->subordinate)) {
4312 pci_dev_unlock(dev);
4320 list_for_each_entry_continue_reverse(dev,
4321 &slot->bus->devices, bus_list) {
4322 if (!dev->slot || dev->slot != slot)
4324 if (dev->subordinate)
4325 pci_bus_unlock(dev->subordinate);
4326 pci_dev_unlock(dev);
4331 /* Save and disable devices from the top of the tree down */
4332 static void pci_bus_save_and_disable(struct pci_bus *bus)
4334 struct pci_dev *dev;
4336 list_for_each_entry(dev, &bus->devices, bus_list) {
4337 pci_dev_save_and_disable(dev);
4338 if (dev->subordinate)
4339 pci_bus_save_and_disable(dev->subordinate);
4344 * Restore devices from top of the tree down - parent bridges need to be
4345 * restored before we can get to subordinate devices.
4347 static void pci_bus_restore(struct pci_bus *bus)
4349 struct pci_dev *dev;
4351 list_for_each_entry(dev, &bus->devices, bus_list) {
4352 pci_dev_restore(dev);
4353 if (dev->subordinate)
4354 pci_bus_restore(dev->subordinate);
4358 /* Save and disable devices from the top of the tree down */
4359 static void pci_slot_save_and_disable(struct pci_slot *slot)
4361 struct pci_dev *dev;
4363 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
4364 if (!dev->slot || dev->slot != slot)
4366 pci_dev_save_and_disable(dev);
4367 if (dev->subordinate)
4368 pci_bus_save_and_disable(dev->subordinate);
4373 * Restore devices from top of the tree down - parent bridges need to be
4374 * restored before we can get to subordinate devices.
4376 static void pci_slot_restore(struct pci_slot *slot)
4378 struct pci_dev *dev;
4380 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
4381 if (!dev->slot || dev->slot != slot)
4383 pci_dev_restore(dev);
4384 if (dev->subordinate)
4385 pci_bus_restore(dev->subordinate);
4389 static int pci_slot_reset(struct pci_slot *slot, int probe)
4393 if (!slot || !pci_slot_resetable(slot))
4397 pci_slot_lock(slot);
4401 rc = pci_reset_hotplug_slot(slot->hotplug, probe);
4404 pci_slot_unlock(slot);
4410 * pci_probe_reset_slot - probe whether a PCI slot can be reset
4411 * @slot: PCI slot to probe
4413 * Return 0 if slot can be reset, negative if a slot reset is not supported.
4415 int pci_probe_reset_slot(struct pci_slot *slot)
4417 return pci_slot_reset(slot, 1);
4419 EXPORT_SYMBOL_GPL(pci_probe_reset_slot);
4422 * pci_reset_slot - reset a PCI slot
4423 * @slot: PCI slot to reset
4425 * A PCI bus may host multiple slots, each slot may support a reset mechanism
4426 * independent of other slots. For instance, some slots may support slot power
4427 * control. In the case of a 1:1 bus to slot architecture, this function may
4428 * wrap the bus reset to avoid spurious slot related events such as hotplug.
4429 * Generally a slot reset should be attempted before a bus reset. All of the
4430 * function of the slot and any subordinate buses behind the slot are reset
4431 * through this function. PCI config space of all devices in the slot and
4432 * behind the slot is saved before and restored after reset.
4434 * Return 0 on success, non-zero on error.
4436 int pci_reset_slot(struct pci_slot *slot)
4440 rc = pci_slot_reset(slot, 1);
4444 pci_slot_save_and_disable(slot);
4446 rc = pci_slot_reset(slot, 0);
4448 pci_slot_restore(slot);
4452 EXPORT_SYMBOL_GPL(pci_reset_slot);
4455 * pci_try_reset_slot - Try to reset a PCI slot
4456 * @slot: PCI slot to reset
4458 * Same as above except return -EAGAIN if the slot cannot be locked
4460 int pci_try_reset_slot(struct pci_slot *slot)
4464 rc = pci_slot_reset(slot, 1);
4468 pci_slot_save_and_disable(slot);
4470 if (pci_slot_trylock(slot)) {
4472 rc = pci_reset_hotplug_slot(slot->hotplug, 0);
4473 pci_slot_unlock(slot);
4477 pci_slot_restore(slot);
4481 EXPORT_SYMBOL_GPL(pci_try_reset_slot);
4483 static int pci_bus_reset(struct pci_bus *bus, int probe)
4485 if (!bus->self || !pci_bus_resetable(bus))
4495 pci_reset_bridge_secondary_bus(bus->self);
4497 pci_bus_unlock(bus);
4503 * pci_probe_reset_bus - probe whether a PCI bus can be reset
4504 * @bus: PCI bus to probe
4506 * Return 0 if bus can be reset, negative if a bus reset is not supported.
4508 int pci_probe_reset_bus(struct pci_bus *bus)
4510 return pci_bus_reset(bus, 1);
4512 EXPORT_SYMBOL_GPL(pci_probe_reset_bus);
4515 * pci_reset_bus - reset a PCI bus
4516 * @bus: top level PCI bus to reset
4518 * Do a bus reset on the given bus and any subordinate buses, saving
4519 * and restoring state of all devices.
4521 * Return 0 on success, non-zero on error.
4523 int pci_reset_bus(struct pci_bus *bus)
4527 rc = pci_bus_reset(bus, 1);
4531 pci_bus_save_and_disable(bus);
4533 rc = pci_bus_reset(bus, 0);
4535 pci_bus_restore(bus);
4539 EXPORT_SYMBOL_GPL(pci_reset_bus);
4542 * pci_try_reset_bus - Try to reset a PCI bus
4543 * @bus: top level PCI bus to reset
4545 * Same as above except return -EAGAIN if the bus cannot be locked
4547 int pci_try_reset_bus(struct pci_bus *bus)
4551 rc = pci_bus_reset(bus, 1);
4555 pci_bus_save_and_disable(bus);
4557 if (pci_bus_trylock(bus)) {
4559 pci_reset_bridge_secondary_bus(bus->self);
4560 pci_bus_unlock(bus);
4564 pci_bus_restore(bus);
4568 EXPORT_SYMBOL_GPL(pci_try_reset_bus);
4571 * pcix_get_max_mmrbc - get PCI-X maximum designed memory read byte count
4572 * @dev: PCI device to query
4574 * Returns mmrbc: maximum designed memory read count in bytes
4575 * or appropriate error value.
4577 int pcix_get_max_mmrbc(struct pci_dev *dev)
4582 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
4586 if (pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat))
4589 return 512 << ((stat & PCI_X_STATUS_MAX_READ) >> 21);
4591 EXPORT_SYMBOL(pcix_get_max_mmrbc);
4594 * pcix_get_mmrbc - get PCI-X maximum memory read byte count
4595 * @dev: PCI device to query
4597 * Returns mmrbc: maximum memory read count in bytes
4598 * or appropriate error value.
4600 int pcix_get_mmrbc(struct pci_dev *dev)
4605 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
4609 if (pci_read_config_word(dev, cap + PCI_X_CMD, &cmd))
4612 return 512 << ((cmd & PCI_X_CMD_MAX_READ) >> 2);
4614 EXPORT_SYMBOL(pcix_get_mmrbc);
4617 * pcix_set_mmrbc - set PCI-X maximum memory read byte count
4618 * @dev: PCI device to query
4619 * @mmrbc: maximum memory read count in bytes
4620 * valid values are 512, 1024, 2048, 4096
4622 * If possible sets maximum memory read byte count, some bridges have erratas
4623 * that prevent this.
4625 int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc)
4631 if (mmrbc < 512 || mmrbc > 4096 || !is_power_of_2(mmrbc))
4634 v = ffs(mmrbc) - 10;
4636 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
4640 if (pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat))
4643 if (v > (stat & PCI_X_STATUS_MAX_READ) >> 21)
4646 if (pci_read_config_word(dev, cap + PCI_X_CMD, &cmd))
4649 o = (cmd & PCI_X_CMD_MAX_READ) >> 2;
4651 if (v > o && (dev->bus->bus_flags & PCI_BUS_FLAGS_NO_MMRBC))
4654 cmd &= ~PCI_X_CMD_MAX_READ;
4656 if (pci_write_config_word(dev, cap + PCI_X_CMD, cmd))
4661 EXPORT_SYMBOL(pcix_set_mmrbc);
4664 * pcie_get_readrq - get PCI Express read request size
4665 * @dev: PCI device to query
4667 * Returns maximum memory read request in bytes
4668 * or appropriate error value.
4670 int pcie_get_readrq(struct pci_dev *dev)
4674 pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl);
4676 return 128 << ((ctl & PCI_EXP_DEVCTL_READRQ) >> 12);
4678 EXPORT_SYMBOL(pcie_get_readrq);
4681 * pcie_set_readrq - set PCI Express maximum memory read request
4682 * @dev: PCI device to query
4683 * @rq: maximum memory read count in bytes
4684 * valid values are 128, 256, 512, 1024, 2048, 4096
4686 * If possible sets maximum memory read request in bytes
4688 int pcie_set_readrq(struct pci_dev *dev, int rq)
4692 if (rq < 128 || rq > 4096 || !is_power_of_2(rq))
4696 * If using the "performance" PCIe config, we clamp the
4697 * read rq size to the max packet size to prevent the
4698 * host bridge generating requests larger than we can
4701 if (pcie_bus_config == PCIE_BUS_PERFORMANCE) {
4702 int mps = pcie_get_mps(dev);
4708 v = (ffs(rq) - 8) << 12;
4710 return pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL,
4711 PCI_EXP_DEVCTL_READRQ, v);
4713 EXPORT_SYMBOL(pcie_set_readrq);
4716 * pcie_get_mps - get PCI Express maximum payload size
4717 * @dev: PCI device to query
4719 * Returns maximum payload size in bytes
4721 int pcie_get_mps(struct pci_dev *dev)
4725 pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl);
4727 return 128 << ((ctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5);
4729 EXPORT_SYMBOL(pcie_get_mps);
4732 * pcie_set_mps - set PCI Express maximum payload size
4733 * @dev: PCI device to query
4734 * @mps: maximum payload size in bytes
4735 * valid values are 128, 256, 512, 1024, 2048, 4096
4737 * If possible sets maximum payload size
4739 int pcie_set_mps(struct pci_dev *dev, int mps)
4743 if (mps < 128 || mps > 4096 || !is_power_of_2(mps))
4747 if (v > dev->pcie_mpss)
4751 return pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL,
4752 PCI_EXP_DEVCTL_PAYLOAD, v);
4754 EXPORT_SYMBOL(pcie_set_mps);
4757 * pcie_get_minimum_link - determine minimum link settings of a PCI device
4758 * @dev: PCI device to query
4759 * @speed: storage for minimum speed
4760 * @width: storage for minimum width
4762 * This function will walk up the PCI device chain and determine the minimum
4763 * link width and speed of the device.
4765 int pcie_get_minimum_link(struct pci_dev *dev, enum pci_bus_speed *speed,
4766 enum pcie_link_width *width)
4770 *speed = PCI_SPEED_UNKNOWN;
4771 *width = PCIE_LNK_WIDTH_UNKNOWN;
4775 enum pci_bus_speed next_speed;
4776 enum pcie_link_width next_width;
4778 ret = pcie_capability_read_word(dev, PCI_EXP_LNKSTA, &lnksta);
4782 next_speed = pcie_link_speed[lnksta & PCI_EXP_LNKSTA_CLS];
4783 next_width = (lnksta & PCI_EXP_LNKSTA_NLW) >>
4784 PCI_EXP_LNKSTA_NLW_SHIFT;
4786 if (next_speed < *speed)
4787 *speed = next_speed;
4789 if (next_width < *width)
4790 *width = next_width;
4792 dev = dev->bus->self;
4797 EXPORT_SYMBOL(pcie_get_minimum_link);
4800 * pci_select_bars - Make BAR mask from the type of resource
4801 * @dev: the PCI device for which BAR mask is made
4802 * @flags: resource type mask to be selected
4804 * This helper routine makes bar mask from the type of resource.
4806 int pci_select_bars(struct pci_dev *dev, unsigned long flags)
4809 for (i = 0; i < PCI_NUM_RESOURCES; i++)
4810 if (pci_resource_flags(dev, i) & flags)
4814 EXPORT_SYMBOL(pci_select_bars);
4817 * pci_resource_bar - get position of the BAR associated with a resource
4818 * @dev: the PCI device
4819 * @resno: the resource number
4820 * @type: the BAR type to be filled in
4822 * Returns BAR position in config space, or 0 if the BAR is invalid.
4824 int pci_resource_bar(struct pci_dev *dev, int resno, enum pci_bar_type *type)
4828 if (resno < PCI_ROM_RESOURCE) {
4829 *type = pci_bar_unknown;
4830 return PCI_BASE_ADDRESS_0 + 4 * resno;
4831 } else if (resno == PCI_ROM_RESOURCE) {
4832 *type = pci_bar_mem32;
4833 return dev->rom_base_reg;
4834 } else if (resno < PCI_BRIDGE_RESOURCES) {
4835 /* device specific resource */
4836 *type = pci_bar_unknown;
4837 reg = pci_iov_resource_bar(dev, resno);
4842 dev_err(&dev->dev, "BAR %d: invalid resource\n", resno);
4846 /* Some architectures require additional programming to enable VGA */
4847 static arch_set_vga_state_t arch_set_vga_state;
4849 void __init pci_register_set_vga_state(arch_set_vga_state_t func)
4851 arch_set_vga_state = func; /* NULL disables */
4854 static int pci_set_vga_state_arch(struct pci_dev *dev, bool decode,
4855 unsigned int command_bits, u32 flags)
4857 if (arch_set_vga_state)
4858 return arch_set_vga_state(dev, decode, command_bits,
4864 * pci_set_vga_state - set VGA decode state on device and parents if requested
4865 * @dev: the PCI device
4866 * @decode: true = enable decoding, false = disable decoding
4867 * @command_bits: PCI_COMMAND_IO and/or PCI_COMMAND_MEMORY
4868 * @flags: traverse ancestors and change bridges
4869 * CHANGE_BRIDGE_ONLY / CHANGE_BRIDGE
4871 int pci_set_vga_state(struct pci_dev *dev, bool decode,
4872 unsigned int command_bits, u32 flags)
4874 struct pci_bus *bus;
4875 struct pci_dev *bridge;
4879 WARN_ON((flags & PCI_VGA_STATE_CHANGE_DECODES) && (command_bits & ~(PCI_COMMAND_IO|PCI_COMMAND_MEMORY)));
4881 /* ARCH specific VGA enables */
4882 rc = pci_set_vga_state_arch(dev, decode, command_bits, flags);
4886 if (flags & PCI_VGA_STATE_CHANGE_DECODES) {
4887 pci_read_config_word(dev, PCI_COMMAND, &cmd);
4889 cmd |= command_bits;
4891 cmd &= ~command_bits;
4892 pci_write_config_word(dev, PCI_COMMAND, cmd);
4895 if (!(flags & PCI_VGA_STATE_CHANGE_BRIDGE))
4902 pci_read_config_word(bridge, PCI_BRIDGE_CONTROL,
4905 cmd |= PCI_BRIDGE_CTL_VGA;
4907 cmd &= ~PCI_BRIDGE_CTL_VGA;
4908 pci_write_config_word(bridge, PCI_BRIDGE_CONTROL,
4917 * pci_add_dma_alias - Add a DMA devfn alias for a device
4918 * @dev: the PCI device for which alias is added
4919 * @devfn: alias slot and function
4921 * This helper encodes 8-bit devfn as bit number in dma_alias_mask.
4922 * It should be called early, preferably as PCI fixup header quirk.
4924 void pci_add_dma_alias(struct pci_dev *dev, u8 devfn)
4926 if (!dev->dma_alias_mask)
4927 dev->dma_alias_mask = kcalloc(BITS_TO_LONGS(U8_MAX),
4928 sizeof(long), GFP_KERNEL);
4929 if (!dev->dma_alias_mask) {
4930 dev_warn(&dev->dev, "Unable to allocate DMA alias mask\n");
4934 set_bit(devfn, dev->dma_alias_mask);
4935 dev_info(&dev->dev, "Enabling fixed DMA alias to %02x.%d\n",
4936 PCI_SLOT(devfn), PCI_FUNC(devfn));
4939 bool pci_devs_are_dma_aliases(struct pci_dev *dev1, struct pci_dev *dev2)
4941 return (dev1->dma_alias_mask &&
4942 test_bit(dev2->devfn, dev1->dma_alias_mask)) ||
4943 (dev2->dma_alias_mask &&
4944 test_bit(dev1->devfn, dev2->dma_alias_mask));
4947 bool pci_device_is_present(struct pci_dev *pdev)
4951 return pci_bus_read_dev_vendor_id(pdev->bus, pdev->devfn, &v, 0);
4953 EXPORT_SYMBOL_GPL(pci_device_is_present);
4955 void pci_ignore_hotplug(struct pci_dev *dev)
4957 struct pci_dev *bridge = dev->bus->self;
4959 dev->ignore_hotplug = 1;
4960 /* Propagate the "ignore hotplug" setting to the parent bridge. */
4962 bridge->ignore_hotplug = 1;
4964 EXPORT_SYMBOL_GPL(pci_ignore_hotplug);
4966 #define RESOURCE_ALIGNMENT_PARAM_SIZE COMMAND_LINE_SIZE
4967 static char resource_alignment_param[RESOURCE_ALIGNMENT_PARAM_SIZE] = {0};
4968 static DEFINE_SPINLOCK(resource_alignment_lock);
4971 * pci_specified_resource_alignment - get resource alignment specified by user.
4972 * @dev: the PCI device to get
4974 * RETURNS: Resource alignment if it is specified.
4975 * Zero if it is not specified.
4977 static resource_size_t pci_specified_resource_alignment(struct pci_dev *dev)
4979 int seg, bus, slot, func, align_order, count;
4980 unsigned short vendor, device, subsystem_vendor, subsystem_device;
4981 resource_size_t align = 0;
4984 spin_lock(&resource_alignment_lock);
4985 p = resource_alignment_param;
4988 if (sscanf(p, "%d%n", &align_order, &count) == 1 &&
4994 if (strncmp(p, "pci:", 4) == 0) {
4995 /* PCI vendor/device (subvendor/subdevice) ids are specified */
4997 if (sscanf(p, "%hx:%hx:%hx:%hx%n",
4998 &vendor, &device, &subsystem_vendor, &subsystem_device, &count) != 4) {
4999 if (sscanf(p, "%hx:%hx%n", &vendor, &device, &count) != 2) {
5000 printk(KERN_ERR "PCI: Can't parse resource_alignment parameter: pci:%s\n",
5004 subsystem_vendor = subsystem_device = 0;
5007 if ((!vendor || (vendor == dev->vendor)) &&
5008 (!device || (device == dev->device)) &&
5009 (!subsystem_vendor || (subsystem_vendor == dev->subsystem_vendor)) &&
5010 (!subsystem_device || (subsystem_device == dev->subsystem_device))) {
5011 if (align_order == -1)
5014 align = 1 << align_order;
5020 if (sscanf(p, "%x:%x:%x.%x%n",
5021 &seg, &bus, &slot, &func, &count) != 4) {
5023 if (sscanf(p, "%x:%x.%x%n",
5024 &bus, &slot, &func, &count) != 3) {
5025 /* Invalid format */
5026 printk(KERN_ERR "PCI: Can't parse resource_alignment parameter: %s\n",
5032 if (seg == pci_domain_nr(dev->bus) &&
5033 bus == dev->bus->number &&
5034 slot == PCI_SLOT(dev->devfn) &&
5035 func == PCI_FUNC(dev->devfn)) {
5036 if (align_order == -1)
5039 align = 1 << align_order;
5044 if (*p != ';' && *p != ',') {
5045 /* End of param or invalid format */
5050 spin_unlock(&resource_alignment_lock);
5055 * This function disables memory decoding and releases memory resources
5056 * of the device specified by kernel's boot parameter 'pci=resource_alignment='.
5057 * It also rounds up size to specified alignment.
5058 * Later on, the kernel will assign page-aligned memory resource back
5061 void pci_reassigndev_resource_alignment(struct pci_dev *dev)
5065 resource_size_t align, size;
5068 /* check if specified PCI is target device to reassign */
5069 align = pci_specified_resource_alignment(dev);
5073 if (dev->hdr_type == PCI_HEADER_TYPE_NORMAL &&
5074 (dev->class >> 8) == PCI_CLASS_BRIDGE_HOST) {
5076 "Can't reassign resources to host bridge.\n");
5081 "Disabling memory decoding and releasing memory resources.\n");
5082 pci_read_config_word(dev, PCI_COMMAND, &command);
5083 command &= ~PCI_COMMAND_MEMORY;
5084 pci_write_config_word(dev, PCI_COMMAND, command);
5086 for (i = 0; i < PCI_BRIDGE_RESOURCES; i++) {
5087 r = &dev->resource[i];
5088 if (!(r->flags & IORESOURCE_MEM))
5090 size = resource_size(r);
5094 "Rounding up size of resource #%d to %#llx.\n",
5095 i, (unsigned long long)size);
5097 r->flags |= IORESOURCE_UNSET;
5101 /* Need to disable bridge's resource window,
5102 * to enable the kernel to reassign new resource
5105 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE &&
5106 (dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
5107 for (i = PCI_BRIDGE_RESOURCES; i < PCI_NUM_RESOURCES; i++) {
5108 r = &dev->resource[i];
5109 if (!(r->flags & IORESOURCE_MEM))
5111 r->flags |= IORESOURCE_UNSET;
5112 r->end = resource_size(r) - 1;
5115 pci_disable_bridge_window(dev);
5119 static ssize_t pci_set_resource_alignment_param(const char *buf, size_t count)
5121 if (count > RESOURCE_ALIGNMENT_PARAM_SIZE - 1)
5122 count = RESOURCE_ALIGNMENT_PARAM_SIZE - 1;
5123 spin_lock(&resource_alignment_lock);
5124 strncpy(resource_alignment_param, buf, count);
5125 resource_alignment_param[count] = '\0';
5126 spin_unlock(&resource_alignment_lock);
5130 static ssize_t pci_get_resource_alignment_param(char *buf, size_t size)
5133 spin_lock(&resource_alignment_lock);
5134 count = snprintf(buf, size, "%s", resource_alignment_param);
5135 spin_unlock(&resource_alignment_lock);
5139 static ssize_t pci_resource_alignment_show(struct bus_type *bus, char *buf)
5141 return pci_get_resource_alignment_param(buf, PAGE_SIZE);
5144 static ssize_t pci_resource_alignment_store(struct bus_type *bus,
5145 const char *buf, size_t count)
5147 return pci_set_resource_alignment_param(buf, count);
5150 static BUS_ATTR(resource_alignment, 0644, pci_resource_alignment_show,
5151 pci_resource_alignment_store);
5153 static int __init pci_resource_alignment_sysfs_init(void)
5155 return bus_create_file(&pci_bus_type,
5156 &bus_attr_resource_alignment);
5158 late_initcall(pci_resource_alignment_sysfs_init);
5160 static void pci_no_domains(void)
5162 #ifdef CONFIG_PCI_DOMAINS
5163 pci_domains_supported = 0;
5167 #ifdef CONFIG_PCI_DOMAINS
5168 static atomic_t __domain_nr = ATOMIC_INIT(-1);
5170 int pci_get_new_domain_nr(void)
5172 return atomic_inc_return(&__domain_nr);
5175 #ifdef CONFIG_PCI_DOMAINS_GENERIC
5176 static int of_pci_bus_find_domain_nr(struct device *parent)
5178 static int use_dt_domains = -1;
5182 domain = of_get_pci_domain_nr(parent->of_node);
5184 * Check DT domain and use_dt_domains values.
5186 * If DT domain property is valid (domain >= 0) and
5187 * use_dt_domains != 0, the DT assignment is valid since this means
5188 * we have not previously allocated a domain number by using
5189 * pci_get_new_domain_nr(); we should also update use_dt_domains to
5190 * 1, to indicate that we have just assigned a domain number from
5193 * If DT domain property value is not valid (ie domain < 0), and we
5194 * have not previously assigned a domain number from DT
5195 * (use_dt_domains != 1) we should assign a domain number by
5198 * pci_get_new_domain_nr()
5200 * API and update the use_dt_domains value to keep track of method we
5201 * are using to assign domain numbers (use_dt_domains = 0).
5203 * All other combinations imply we have a platform that is trying
5204 * to mix domain numbers obtained from DT and pci_get_new_domain_nr(),
5205 * which is a recipe for domain mishandling and it is prevented by
5206 * invalidating the domain value (domain = -1) and printing a
5207 * corresponding error.
5209 if (domain >= 0 && use_dt_domains) {
5211 } else if (domain < 0 && use_dt_domains != 1) {
5213 domain = pci_get_new_domain_nr();
5215 dev_err(parent, "Node %s has inconsistent \"linux,pci-domain\" property in DT\n",
5216 parent->of_node->full_name);
5223 int pci_bus_find_domain_nr(struct pci_bus *bus, struct device *parent)
5225 return acpi_disabled ? of_pci_bus_find_domain_nr(parent) :
5226 acpi_pci_bus_find_domain_nr(bus);
5232 * pci_ext_cfg_avail - can we access extended PCI config space?
5234 * Returns 1 if we can access PCI extended config space (offsets
5235 * greater than 0xff). This is the default implementation. Architecture
5236 * implementations can override this.
5238 int __weak pci_ext_cfg_avail(void)
5243 void __weak pci_fixup_cardbus(struct pci_bus *bus)
5246 EXPORT_SYMBOL(pci_fixup_cardbus);
5248 static int __init pci_setup(char *str)
5251 char *k = strchr(str, ',');
5254 if (*str && (str = pcibios_setup(str)) && *str) {
5255 if (!strcmp(str, "nomsi")) {
5257 } else if (!strcmp(str, "noaer")) {
5259 } else if (!strncmp(str, "realloc=", 8)) {
5260 pci_realloc_get_opt(str + 8);
5261 } else if (!strncmp(str, "realloc", 7)) {
5262 pci_realloc_get_opt("on");
5263 } else if (!strcmp(str, "nodomains")) {
5265 } else if (!strncmp(str, "noari", 5)) {
5266 pcie_ari_disabled = true;
5267 } else if (!strncmp(str, "cbiosize=", 9)) {
5268 pci_cardbus_io_size = memparse(str + 9, &str);
5269 } else if (!strncmp(str, "cbmemsize=", 10)) {
5270 pci_cardbus_mem_size = memparse(str + 10, &str);
5271 } else if (!strncmp(str, "resource_alignment=", 19)) {
5272 pci_set_resource_alignment_param(str + 19,
5274 } else if (!strncmp(str, "ecrc=", 5)) {
5275 pcie_ecrc_get_policy(str + 5);
5276 } else if (!strncmp(str, "hpiosize=", 9)) {
5277 pci_hotplug_io_size = memparse(str + 9, &str);
5278 } else if (!strncmp(str, "hpmemsize=", 10)) {
5279 pci_hotplug_mem_size = memparse(str + 10, &str);
5280 } else if (!strncmp(str, "hpbussize=", 10)) {
5281 pci_hotplug_bus_size =
5282 simple_strtoul(str + 10, &str, 0);
5283 if (pci_hotplug_bus_size > 0xff)
5284 pci_hotplug_bus_size = DEFAULT_HOTPLUG_BUS_SIZE;
5285 } else if (!strncmp(str, "pcie_bus_tune_off", 17)) {
5286 pcie_bus_config = PCIE_BUS_TUNE_OFF;
5287 } else if (!strncmp(str, "pcie_bus_safe", 13)) {
5288 pcie_bus_config = PCIE_BUS_SAFE;
5289 } else if (!strncmp(str, "pcie_bus_perf", 13)) {
5290 pcie_bus_config = PCIE_BUS_PERFORMANCE;
5291 } else if (!strncmp(str, "pcie_bus_peer2peer", 18)) {
5292 pcie_bus_config = PCIE_BUS_PEER2PEER;
5293 } else if (!strncmp(str, "pcie_scan_all", 13)) {
5294 pci_add_flags(PCI_SCAN_ALL_PCIE_DEVS);
5296 printk(KERN_ERR "PCI: Unknown option `%s'\n",
5304 early_param("pci", pci_setup);