2 * PCI Bus Services, see include/linux/pci.h for further explanation.
4 * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter,
7 * Copyright 1997 -- 2000 Martin Mares <mj@ucw.cz>
10 #include <linux/acpi.h>
11 #include <linux/kernel.h>
12 #include <linux/delay.h>
13 #include <linux/dmi.h>
14 #include <linux/init.h>
16 #include <linux/of_pci.h>
17 #include <linux/pci.h>
19 #include <linux/slab.h>
20 #include <linux/module.h>
21 #include <linux/spinlock.h>
22 #include <linux/string.h>
23 #include <linux/log2.h>
24 #include <linux/pci-aspm.h>
25 #include <linux/pm_wakeup.h>
26 #include <linux/interrupt.h>
27 #include <linux/device.h>
28 #include <linux/pm_runtime.h>
29 #include <linux/pci_hotplug.h>
30 #include <linux/vmalloc.h>
31 #include <asm/setup.h>
33 #include <linux/aer.h>
36 const char *pci_power_names[] = {
37 "error", "D0", "D1", "D2", "D3hot", "D3cold", "unknown",
39 EXPORT_SYMBOL_GPL(pci_power_names);
41 int isa_dma_bridge_buggy;
42 EXPORT_SYMBOL(isa_dma_bridge_buggy);
45 EXPORT_SYMBOL(pci_pci_problems);
47 unsigned int pci_pm_d3_delay;
49 static void pci_pme_list_scan(struct work_struct *work);
51 static LIST_HEAD(pci_pme_list);
52 static DEFINE_MUTEX(pci_pme_list_mutex);
53 static DECLARE_DELAYED_WORK(pci_pme_work, pci_pme_list_scan);
55 struct pci_pme_device {
56 struct list_head list;
60 #define PME_TIMEOUT 1000 /* How long between PME checks */
62 static void pci_dev_d3_sleep(struct pci_dev *dev)
64 unsigned int delay = dev->d3_delay;
66 if (delay < pci_pm_d3_delay)
67 delay = pci_pm_d3_delay;
72 #ifdef CONFIG_PCI_DOMAINS
73 int pci_domains_supported = 1;
76 #define DEFAULT_CARDBUS_IO_SIZE (256)
77 #define DEFAULT_CARDBUS_MEM_SIZE (64*1024*1024)
78 /* pci=cbmemsize=nnM,cbiosize=nn can override this */
79 unsigned long pci_cardbus_io_size = DEFAULT_CARDBUS_IO_SIZE;
80 unsigned long pci_cardbus_mem_size = DEFAULT_CARDBUS_MEM_SIZE;
82 #define DEFAULT_HOTPLUG_IO_SIZE (256)
83 #define DEFAULT_HOTPLUG_MEM_SIZE (2*1024*1024)
84 /* pci=hpmemsize=nnM,hpiosize=nn can override this */
85 unsigned long pci_hotplug_io_size = DEFAULT_HOTPLUG_IO_SIZE;
86 unsigned long pci_hotplug_mem_size = DEFAULT_HOTPLUG_MEM_SIZE;
88 #define DEFAULT_HOTPLUG_BUS_SIZE 1
89 unsigned long pci_hotplug_bus_size = DEFAULT_HOTPLUG_BUS_SIZE;
91 enum pcie_bus_config_types pcie_bus_config = PCIE_BUS_DEFAULT;
94 * The default CLS is used if arch didn't set CLS explicitly and not
95 * all pci devices agree on the same value. Arch can override either
96 * the dfl or actual value as it sees fit. Don't forget this is
97 * measured in 32-bit words, not bytes.
99 u8 pci_dfl_cache_line_size = L1_CACHE_BYTES >> 2;
100 u8 pci_cache_line_size;
103 * If we set up a device for bus mastering, we need to check the latency
104 * timer as certain BIOSes forget to set it properly.
106 unsigned int pcibios_max_latency = 255;
108 /* If set, the PCIe ARI capability will not be used. */
109 static bool pcie_ari_disabled;
111 /* Disable bridge_d3 for all PCIe ports */
112 static bool pci_bridge_d3_disable;
113 /* Force bridge_d3 for all PCIe ports */
114 static bool pci_bridge_d3_force;
116 static int __init pcie_port_pm_setup(char *str)
118 if (!strcmp(str, "off"))
119 pci_bridge_d3_disable = true;
120 else if (!strcmp(str, "force"))
121 pci_bridge_d3_force = true;
124 __setup("pcie_port_pm=", pcie_port_pm_setup);
127 * pci_bus_max_busnr - returns maximum PCI bus number of given bus' children
128 * @bus: pointer to PCI bus structure to search
130 * Given a PCI bus, returns the highest PCI bus number present in the set
131 * including the given PCI bus and its list of child PCI buses.
133 unsigned char pci_bus_max_busnr(struct pci_bus *bus)
136 unsigned char max, n;
138 max = bus->busn_res.end;
139 list_for_each_entry(tmp, &bus->children, node) {
140 n = pci_bus_max_busnr(tmp);
146 EXPORT_SYMBOL_GPL(pci_bus_max_busnr);
148 #ifdef CONFIG_HAS_IOMEM
149 void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar)
151 struct resource *res = &pdev->resource[bar];
154 * Make sure the BAR is actually a memory resource, not an IO resource
156 if (res->flags & IORESOURCE_UNSET || !(res->flags & IORESOURCE_MEM)) {
157 dev_warn(&pdev->dev, "can't ioremap BAR %d: %pR\n", bar, res);
160 return ioremap_nocache(res->start, resource_size(res));
162 EXPORT_SYMBOL_GPL(pci_ioremap_bar);
164 void __iomem *pci_ioremap_wc_bar(struct pci_dev *pdev, int bar)
167 * Make sure the BAR is actually a memory resource, not an IO resource
169 if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) {
173 return ioremap_wc(pci_resource_start(pdev, bar),
174 pci_resource_len(pdev, bar));
176 EXPORT_SYMBOL_GPL(pci_ioremap_wc_bar);
180 static int __pci_find_next_cap_ttl(struct pci_bus *bus, unsigned int devfn,
181 u8 pos, int cap, int *ttl)
186 pci_bus_read_config_byte(bus, devfn, pos, &pos);
192 pci_bus_read_config_word(bus, devfn, pos, &ent);
204 static int __pci_find_next_cap(struct pci_bus *bus, unsigned int devfn,
207 int ttl = PCI_FIND_CAP_TTL;
209 return __pci_find_next_cap_ttl(bus, devfn, pos, cap, &ttl);
212 int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap)
214 return __pci_find_next_cap(dev->bus, dev->devfn,
215 pos + PCI_CAP_LIST_NEXT, cap);
217 EXPORT_SYMBOL_GPL(pci_find_next_capability);
219 static int __pci_bus_find_cap_start(struct pci_bus *bus,
220 unsigned int devfn, u8 hdr_type)
224 pci_bus_read_config_word(bus, devfn, PCI_STATUS, &status);
225 if (!(status & PCI_STATUS_CAP_LIST))
229 case PCI_HEADER_TYPE_NORMAL:
230 case PCI_HEADER_TYPE_BRIDGE:
231 return PCI_CAPABILITY_LIST;
232 case PCI_HEADER_TYPE_CARDBUS:
233 return PCI_CB_CAPABILITY_LIST;
240 * pci_find_capability - query for devices' capabilities
241 * @dev: PCI device to query
242 * @cap: capability code
244 * Tell if a device supports a given PCI capability.
245 * Returns the address of the requested capability structure within the
246 * device's PCI configuration space or 0 in case the device does not
247 * support it. Possible values for @cap:
249 * %PCI_CAP_ID_PM Power Management
250 * %PCI_CAP_ID_AGP Accelerated Graphics Port
251 * %PCI_CAP_ID_VPD Vital Product Data
252 * %PCI_CAP_ID_SLOTID Slot Identification
253 * %PCI_CAP_ID_MSI Message Signalled Interrupts
254 * %PCI_CAP_ID_CHSWP CompactPCI HotSwap
255 * %PCI_CAP_ID_PCIX PCI-X
256 * %PCI_CAP_ID_EXP PCI Express
258 int pci_find_capability(struct pci_dev *dev, int cap)
262 pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type);
264 pos = __pci_find_next_cap(dev->bus, dev->devfn, pos, cap);
268 EXPORT_SYMBOL(pci_find_capability);
271 * pci_bus_find_capability - query for devices' capabilities
272 * @bus: the PCI bus to query
273 * @devfn: PCI device to query
274 * @cap: capability code
276 * Like pci_find_capability() but works for pci devices that do not have a
277 * pci_dev structure set up yet.
279 * Returns the address of the requested capability structure within the
280 * device's PCI configuration space or 0 in case the device does not
283 int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap)
288 pci_bus_read_config_byte(bus, devfn, PCI_HEADER_TYPE, &hdr_type);
290 pos = __pci_bus_find_cap_start(bus, devfn, hdr_type & 0x7f);
292 pos = __pci_find_next_cap(bus, devfn, pos, cap);
296 EXPORT_SYMBOL(pci_bus_find_capability);
299 * pci_find_next_ext_capability - Find an extended capability
300 * @dev: PCI device to query
301 * @start: address at which to start looking (0 to start at beginning of list)
302 * @cap: capability code
304 * Returns the address of the next matching extended capability structure
305 * within the device's PCI configuration space or 0 if the device does
306 * not support it. Some capabilities can occur several times, e.g., the
307 * vendor-specific capability, and this provides a way to find them all.
309 int pci_find_next_ext_capability(struct pci_dev *dev, int start, int cap)
313 int pos = PCI_CFG_SPACE_SIZE;
315 /* minimum 8 bytes per capability */
316 ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8;
318 if (dev->cfg_size <= PCI_CFG_SPACE_SIZE)
324 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
328 * If we have no capabilities, this is indicated by cap ID,
329 * cap version and next pointer all being 0.
335 if (PCI_EXT_CAP_ID(header) == cap && pos != start)
338 pos = PCI_EXT_CAP_NEXT(header);
339 if (pos < PCI_CFG_SPACE_SIZE)
342 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
348 EXPORT_SYMBOL_GPL(pci_find_next_ext_capability);
351 * pci_find_ext_capability - Find an extended capability
352 * @dev: PCI device to query
353 * @cap: capability code
355 * Returns the address of the requested extended capability structure
356 * within the device's PCI configuration space or 0 if the device does
357 * not support it. Possible values for @cap:
359 * %PCI_EXT_CAP_ID_ERR Advanced Error Reporting
360 * %PCI_EXT_CAP_ID_VC Virtual Channel
361 * %PCI_EXT_CAP_ID_DSN Device Serial Number
362 * %PCI_EXT_CAP_ID_PWR Power Budgeting
364 int pci_find_ext_capability(struct pci_dev *dev, int cap)
366 return pci_find_next_ext_capability(dev, 0, cap);
368 EXPORT_SYMBOL_GPL(pci_find_ext_capability);
370 static int __pci_find_next_ht_cap(struct pci_dev *dev, int pos, int ht_cap)
372 int rc, ttl = PCI_FIND_CAP_TTL;
375 if (ht_cap == HT_CAPTYPE_SLAVE || ht_cap == HT_CAPTYPE_HOST)
376 mask = HT_3BIT_CAP_MASK;
378 mask = HT_5BIT_CAP_MASK;
380 pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn, pos,
381 PCI_CAP_ID_HT, &ttl);
383 rc = pci_read_config_byte(dev, pos + 3, &cap);
384 if (rc != PCIBIOS_SUCCESSFUL)
387 if ((cap & mask) == ht_cap)
390 pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn,
391 pos + PCI_CAP_LIST_NEXT,
392 PCI_CAP_ID_HT, &ttl);
398 * pci_find_next_ht_capability - query a device's Hypertransport capabilities
399 * @dev: PCI device to query
400 * @pos: Position from which to continue searching
401 * @ht_cap: Hypertransport capability code
403 * To be used in conjunction with pci_find_ht_capability() to search for
404 * all capabilities matching @ht_cap. @pos should always be a value returned
405 * from pci_find_ht_capability().
407 * NB. To be 100% safe against broken PCI devices, the caller should take
408 * steps to avoid an infinite loop.
410 int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap)
412 return __pci_find_next_ht_cap(dev, pos + PCI_CAP_LIST_NEXT, ht_cap);
414 EXPORT_SYMBOL_GPL(pci_find_next_ht_capability);
417 * pci_find_ht_capability - query a device's Hypertransport capabilities
418 * @dev: PCI device to query
419 * @ht_cap: Hypertransport capability code
421 * Tell if a device supports a given Hypertransport capability.
422 * Returns an address within the device's PCI configuration space
423 * or 0 in case the device does not support the request capability.
424 * The address points to the PCI capability, of type PCI_CAP_ID_HT,
425 * which has a Hypertransport capability matching @ht_cap.
427 int pci_find_ht_capability(struct pci_dev *dev, int ht_cap)
431 pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type);
433 pos = __pci_find_next_ht_cap(dev, pos, ht_cap);
437 EXPORT_SYMBOL_GPL(pci_find_ht_capability);
440 * pci_find_parent_resource - return resource region of parent bus of given region
441 * @dev: PCI device structure contains resources to be searched
442 * @res: child resource record for which parent is sought
444 * For given resource region of given device, return the resource
445 * region of parent bus the given region is contained in.
447 struct resource *pci_find_parent_resource(const struct pci_dev *dev,
448 struct resource *res)
450 const struct pci_bus *bus = dev->bus;
454 pci_bus_for_each_resource(bus, r, i) {
457 if (res->start && resource_contains(r, res)) {
460 * If the window is prefetchable but the BAR is
461 * not, the allocator made a mistake.
463 if (r->flags & IORESOURCE_PREFETCH &&
464 !(res->flags & IORESOURCE_PREFETCH))
468 * If we're below a transparent bridge, there may
469 * be both a positively-decoded aperture and a
470 * subtractively-decoded region that contain the BAR.
471 * We want the positively-decoded one, so this depends
472 * on pci_bus_for_each_resource() giving us those
480 EXPORT_SYMBOL(pci_find_parent_resource);
483 * pci_find_pcie_root_port - return PCIe Root Port
484 * @dev: PCI device to query
486 * Traverse up the parent chain and return the PCIe Root Port PCI Device
487 * for a given PCI Device.
489 struct pci_dev *pci_find_pcie_root_port(struct pci_dev *dev)
491 struct pci_dev *bridge, *highest_pcie_bridge = NULL;
493 bridge = pci_upstream_bridge(dev);
494 while (bridge && pci_is_pcie(bridge)) {
495 highest_pcie_bridge = bridge;
496 bridge = pci_upstream_bridge(bridge);
499 if (pci_pcie_type(highest_pcie_bridge) != PCI_EXP_TYPE_ROOT_PORT)
502 return highest_pcie_bridge;
504 EXPORT_SYMBOL(pci_find_pcie_root_port);
507 * pci_wait_for_pending - wait for @mask bit(s) to clear in status word @pos
508 * @dev: the PCI device to operate on
509 * @pos: config space offset of status word
510 * @mask: mask of bit(s) to care about in status word
512 * Return 1 when mask bit(s) in status word clear, 0 otherwise.
514 int pci_wait_for_pending(struct pci_dev *dev, int pos, u16 mask)
518 /* Wait for Transaction Pending bit clean */
519 for (i = 0; i < 4; i++) {
522 msleep((1 << (i - 1)) * 100);
524 pci_read_config_word(dev, pos, &status);
525 if (!(status & mask))
533 * pci_restore_bars - restore a device's BAR values (e.g. after wake-up)
534 * @dev: PCI device to have its BARs restored
536 * Restore the BAR values for a given device, so as to make it
537 * accessible by its driver.
539 static void pci_restore_bars(struct pci_dev *dev)
543 /* Per SR-IOV spec 3.4.1.11, VF BARs are RO zero */
547 for (i = 0; i < PCI_BRIDGE_RESOURCES; i++)
548 pci_update_resource(dev, i);
551 static const struct pci_platform_pm_ops *pci_platform_pm;
553 int pci_set_platform_pm(const struct pci_platform_pm_ops *ops)
555 if (!ops->is_manageable || !ops->set_state || !ops->get_state ||
556 !ops->choose_state || !ops->sleep_wake || !ops->run_wake ||
559 pci_platform_pm = ops;
563 static inline bool platform_pci_power_manageable(struct pci_dev *dev)
565 return pci_platform_pm ? pci_platform_pm->is_manageable(dev) : false;
568 static inline int platform_pci_set_power_state(struct pci_dev *dev,
571 return pci_platform_pm ? pci_platform_pm->set_state(dev, t) : -ENOSYS;
574 static inline pci_power_t platform_pci_get_power_state(struct pci_dev *dev)
576 return pci_platform_pm ? pci_platform_pm->get_state(dev) : PCI_UNKNOWN;
579 static inline pci_power_t platform_pci_choose_state(struct pci_dev *dev)
581 return pci_platform_pm ?
582 pci_platform_pm->choose_state(dev) : PCI_POWER_ERROR;
585 static inline int platform_pci_sleep_wake(struct pci_dev *dev, bool enable)
587 return pci_platform_pm ?
588 pci_platform_pm->sleep_wake(dev, enable) : -ENODEV;
591 static inline int platform_pci_run_wake(struct pci_dev *dev, bool enable)
593 return pci_platform_pm ?
594 pci_platform_pm->run_wake(dev, enable) : -ENODEV;
597 static inline bool platform_pci_need_resume(struct pci_dev *dev)
599 return pci_platform_pm ? pci_platform_pm->need_resume(dev) : false;
603 * pci_raw_set_power_state - Use PCI PM registers to set the power state of
605 * @dev: PCI device to handle.
606 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into.
609 * -EINVAL if the requested state is invalid.
610 * -EIO if device does not support PCI PM or its PM capabilities register has a
611 * wrong version, or device doesn't support the requested state.
612 * 0 if device already is in the requested state.
613 * 0 if device's power state has been successfully changed.
615 static int pci_raw_set_power_state(struct pci_dev *dev, pci_power_t state)
618 bool need_restore = false;
620 /* Check if we're already there */
621 if (dev->current_state == state)
627 if (state < PCI_D0 || state > PCI_D3hot)
630 /* Validate current state:
631 * Can enter D0 from any state, but if we can only go deeper
632 * to sleep if we're already in a low power state
634 if (state != PCI_D0 && dev->current_state <= PCI_D3cold
635 && dev->current_state > state) {
636 dev_err(&dev->dev, "invalid power transition (from state %d to %d)\n",
637 dev->current_state, state);
641 /* check if this device supports the desired state */
642 if ((state == PCI_D1 && !dev->d1_support)
643 || (state == PCI_D2 && !dev->d2_support))
646 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
648 /* If we're (effectively) in D3, force entire word to 0.
649 * This doesn't affect PME_Status, disables PME_En, and
650 * sets PowerState to 0.
652 switch (dev->current_state) {
656 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
661 case PCI_UNKNOWN: /* Boot-up */
662 if ((pmcsr & PCI_PM_CTRL_STATE_MASK) == PCI_D3hot
663 && !(pmcsr & PCI_PM_CTRL_NO_SOFT_RESET))
665 /* Fall-through: force to D0 */
671 /* enter specified state */
672 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr);
674 /* Mandatory power management transition delays */
675 /* see PCI PM 1.1 5.6.1 table 18 */
676 if (state == PCI_D3hot || dev->current_state == PCI_D3hot)
677 pci_dev_d3_sleep(dev);
678 else if (state == PCI_D2 || dev->current_state == PCI_D2)
679 udelay(PCI_PM_D2_DELAY);
681 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
682 dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK);
683 if (dev->current_state != state && printk_ratelimit())
684 dev_info(&dev->dev, "Refused to change power state, currently in D%d\n",
688 * According to section 5.4.1 of the "PCI BUS POWER MANAGEMENT
689 * INTERFACE SPECIFICATION, REV. 1.2", a device transitioning
690 * from D3hot to D0 _may_ perform an internal reset, thereby
691 * going to "D0 Uninitialized" rather than "D0 Initialized".
692 * For example, at least some versions of the 3c905B and the
693 * 3c556B exhibit this behaviour.
695 * At least some laptop BIOSen (e.g. the Thinkpad T21) leave
696 * devices in a D3hot state at boot. Consequently, we need to
697 * restore at least the BARs so that the device will be
698 * accessible to its driver.
701 pci_restore_bars(dev);
704 pcie_aspm_pm_state_change(dev->bus->self);
710 * pci_update_current_state - Read PCI power state of given device from its
711 * PCI PM registers and cache it
712 * @dev: PCI device to handle.
713 * @state: State to cache in case the device doesn't have the PM capability
715 void pci_update_current_state(struct pci_dev *dev, pci_power_t state)
721 * Configuration space is not accessible for device in
722 * D3cold, so just keep or set D3cold for safety
724 if (dev->current_state == PCI_D3cold)
726 if (state == PCI_D3cold) {
727 dev->current_state = PCI_D3cold;
730 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
731 dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK);
733 dev->current_state = state;
738 * pci_power_up - Put the given device into D0 forcibly
739 * @dev: PCI device to power up
741 void pci_power_up(struct pci_dev *dev)
743 if (platform_pci_power_manageable(dev))
744 platform_pci_set_power_state(dev, PCI_D0);
746 pci_raw_set_power_state(dev, PCI_D0);
747 pci_update_current_state(dev, PCI_D0);
751 * pci_platform_power_transition - Use platform to change device power state
752 * @dev: PCI device to handle.
753 * @state: State to put the device into.
755 static int pci_platform_power_transition(struct pci_dev *dev, pci_power_t state)
759 if (platform_pci_power_manageable(dev)) {
760 error = platform_pci_set_power_state(dev, state);
762 pci_update_current_state(dev, state);
766 if (error && !dev->pm_cap) /* Fall back to PCI_D0 */
767 dev->current_state = PCI_D0;
773 * pci_wakeup - Wake up a PCI device
774 * @pci_dev: Device to handle.
775 * @ign: ignored parameter
777 static int pci_wakeup(struct pci_dev *pci_dev, void *ign)
779 pci_wakeup_event(pci_dev);
780 pm_request_resume(&pci_dev->dev);
785 * pci_wakeup_bus - Walk given bus and wake up devices on it
786 * @bus: Top bus of the subtree to walk.
788 static void pci_wakeup_bus(struct pci_bus *bus)
791 pci_walk_bus(bus, pci_wakeup, NULL);
795 * __pci_start_power_transition - Start power transition of a PCI device
796 * @dev: PCI device to handle.
797 * @state: State to put the device into.
799 static void __pci_start_power_transition(struct pci_dev *dev, pci_power_t state)
801 if (state == PCI_D0) {
802 pci_platform_power_transition(dev, PCI_D0);
804 * Mandatory power management transition delays, see
805 * PCI Express Base Specification Revision 2.0 Section
806 * 6.6.1: Conventional Reset. Do not delay for
807 * devices powered on/off by corresponding bridge,
808 * because have already delayed for the bridge.
810 if (dev->runtime_d3cold) {
811 msleep(dev->d3cold_delay);
813 * When powering on a bridge from D3cold, the
814 * whole hierarchy may be powered on into
815 * D0uninitialized state, resume them to give
816 * them a chance to suspend again
818 pci_wakeup_bus(dev->subordinate);
824 * __pci_dev_set_current_state - Set current state of a PCI device
825 * @dev: Device to handle
826 * @data: pointer to state to be set
828 static int __pci_dev_set_current_state(struct pci_dev *dev, void *data)
830 pci_power_t state = *(pci_power_t *)data;
832 dev->current_state = state;
837 * __pci_bus_set_current_state - Walk given bus and set current state of devices
838 * @bus: Top bus of the subtree to walk.
839 * @state: state to be set
841 static void __pci_bus_set_current_state(struct pci_bus *bus, pci_power_t state)
844 pci_walk_bus(bus, __pci_dev_set_current_state, &state);
848 * __pci_complete_power_transition - Complete power transition of a PCI device
849 * @dev: PCI device to handle.
850 * @state: State to put the device into.
852 * This function should not be called directly by device drivers.
854 int __pci_complete_power_transition(struct pci_dev *dev, pci_power_t state)
860 ret = pci_platform_power_transition(dev, state);
861 /* Power off the bridge may power off the whole hierarchy */
862 if (!ret && state == PCI_D3cold)
863 __pci_bus_set_current_state(dev->subordinate, PCI_D3cold);
866 EXPORT_SYMBOL_GPL(__pci_complete_power_transition);
869 * pci_set_power_state - Set the power state of a PCI device
870 * @dev: PCI device to handle.
871 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into.
873 * Transition a device to a new power state, using the platform firmware and/or
874 * the device's PCI PM registers.
877 * -EINVAL if the requested state is invalid.
878 * -EIO if device does not support PCI PM or its PM capabilities register has a
879 * wrong version, or device doesn't support the requested state.
880 * 0 if device already is in the requested state.
881 * 0 if device's power state has been successfully changed.
883 int pci_set_power_state(struct pci_dev *dev, pci_power_t state)
887 /* bound the state we're entering */
888 if (state > PCI_D3cold)
890 else if (state < PCI_D0)
892 else if ((state == PCI_D1 || state == PCI_D2) && pci_no_d1d2(dev))
894 * If the device or the parent bridge do not support PCI PM,
895 * ignore the request if we're doing anything other than putting
896 * it into D0 (which would only happen on boot).
900 /* Check if we're already there */
901 if (dev->current_state == state)
904 __pci_start_power_transition(dev, state);
906 /* This device is quirked not to be put into D3, so
907 don't put it in D3 */
908 if (state >= PCI_D3hot && (dev->dev_flags & PCI_DEV_FLAGS_NO_D3))
912 * To put device in D3cold, we put device into D3hot in native
913 * way, then put device into D3cold with platform ops
915 error = pci_raw_set_power_state(dev, state > PCI_D3hot ?
918 if (!__pci_complete_power_transition(dev, state))
923 EXPORT_SYMBOL(pci_set_power_state);
926 * pci_choose_state - Choose the power state of a PCI device
927 * @dev: PCI device to be suspended
928 * @state: target sleep state for the whole system. This is the value
929 * that is passed to suspend() function.
931 * Returns PCI power state suitable for given device and given system
935 pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state)
942 ret = platform_pci_choose_state(dev);
943 if (ret != PCI_POWER_ERROR)
946 switch (state.event) {
949 case PM_EVENT_FREEZE:
950 case PM_EVENT_PRETHAW:
951 /* REVISIT both freeze and pre-thaw "should" use D0 */
952 case PM_EVENT_SUSPEND:
953 case PM_EVENT_HIBERNATE:
956 dev_info(&dev->dev, "unrecognized suspend event %d\n",
962 EXPORT_SYMBOL(pci_choose_state);
964 #define PCI_EXP_SAVE_REGS 7
966 static struct pci_cap_saved_state *_pci_find_saved_cap(struct pci_dev *pci_dev,
967 u16 cap, bool extended)
969 struct pci_cap_saved_state *tmp;
971 hlist_for_each_entry(tmp, &pci_dev->saved_cap_space, next) {
972 if (tmp->cap.cap_extended == extended && tmp->cap.cap_nr == cap)
978 struct pci_cap_saved_state *pci_find_saved_cap(struct pci_dev *dev, char cap)
980 return _pci_find_saved_cap(dev, cap, false);
983 struct pci_cap_saved_state *pci_find_saved_ext_cap(struct pci_dev *dev, u16 cap)
985 return _pci_find_saved_cap(dev, cap, true);
988 static int pci_save_pcie_state(struct pci_dev *dev)
991 struct pci_cap_saved_state *save_state;
994 if (!pci_is_pcie(dev))
997 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP);
999 dev_err(&dev->dev, "buffer not found in %s\n", __func__);
1003 cap = (u16 *)&save_state->cap.data[0];
1004 pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &cap[i++]);
1005 pcie_capability_read_word(dev, PCI_EXP_LNKCTL, &cap[i++]);
1006 pcie_capability_read_word(dev, PCI_EXP_SLTCTL, &cap[i++]);
1007 pcie_capability_read_word(dev, PCI_EXP_RTCTL, &cap[i++]);
1008 pcie_capability_read_word(dev, PCI_EXP_DEVCTL2, &cap[i++]);
1009 pcie_capability_read_word(dev, PCI_EXP_LNKCTL2, &cap[i++]);
1010 pcie_capability_read_word(dev, PCI_EXP_SLTCTL2, &cap[i++]);
1015 static void pci_restore_pcie_state(struct pci_dev *dev)
1018 struct pci_cap_saved_state *save_state;
1021 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP);
1025 cap = (u16 *)&save_state->cap.data[0];
1026 pcie_capability_write_word(dev, PCI_EXP_DEVCTL, cap[i++]);
1027 pcie_capability_write_word(dev, PCI_EXP_LNKCTL, cap[i++]);
1028 pcie_capability_write_word(dev, PCI_EXP_SLTCTL, cap[i++]);
1029 pcie_capability_write_word(dev, PCI_EXP_RTCTL, cap[i++]);
1030 pcie_capability_write_word(dev, PCI_EXP_DEVCTL2, cap[i++]);
1031 pcie_capability_write_word(dev, PCI_EXP_LNKCTL2, cap[i++]);
1032 pcie_capability_write_word(dev, PCI_EXP_SLTCTL2, cap[i++]);
1036 static int pci_save_pcix_state(struct pci_dev *dev)
1039 struct pci_cap_saved_state *save_state;
1041 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
1045 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX);
1047 dev_err(&dev->dev, "buffer not found in %s\n", __func__);
1051 pci_read_config_word(dev, pos + PCI_X_CMD,
1052 (u16 *)save_state->cap.data);
1057 static void pci_restore_pcix_state(struct pci_dev *dev)
1060 struct pci_cap_saved_state *save_state;
1063 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX);
1064 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
1065 if (!save_state || !pos)
1067 cap = (u16 *)&save_state->cap.data[0];
1069 pci_write_config_word(dev, pos + PCI_X_CMD, cap[i++]);
1074 * pci_save_state - save the PCI configuration space of a device before suspending
1075 * @dev: - PCI device that we're dealing with
1077 int pci_save_state(struct pci_dev *dev)
1080 /* XXX: 100% dword access ok here? */
1081 for (i = 0; i < 16; i++)
1082 pci_read_config_dword(dev, i * 4, &dev->saved_config_space[i]);
1083 dev->state_saved = true;
1085 i = pci_save_pcie_state(dev);
1089 i = pci_save_pcix_state(dev);
1093 return pci_save_vc_state(dev);
1095 EXPORT_SYMBOL(pci_save_state);
1097 static void pci_restore_config_dword(struct pci_dev *pdev, int offset,
1098 u32 saved_val, int retry)
1102 pci_read_config_dword(pdev, offset, &val);
1103 if (val == saved_val)
1107 dev_dbg(&pdev->dev, "restoring config space at offset %#x (was %#x, writing %#x)\n",
1108 offset, val, saved_val);
1109 pci_write_config_dword(pdev, offset, saved_val);
1113 pci_read_config_dword(pdev, offset, &val);
1114 if (val == saved_val)
1121 static void pci_restore_config_space_range(struct pci_dev *pdev,
1122 int start, int end, int retry)
1126 for (index = end; index >= start; index--)
1127 pci_restore_config_dword(pdev, 4 * index,
1128 pdev->saved_config_space[index],
1132 static void pci_restore_config_space(struct pci_dev *pdev)
1134 if (pdev->hdr_type == PCI_HEADER_TYPE_NORMAL) {
1135 pci_restore_config_space_range(pdev, 10, 15, 0);
1136 /* Restore BARs before the command register. */
1137 pci_restore_config_space_range(pdev, 4, 9, 10);
1138 pci_restore_config_space_range(pdev, 0, 3, 0);
1140 pci_restore_config_space_range(pdev, 0, 15, 0);
1145 * pci_restore_state - Restore the saved state of a PCI device
1146 * @dev: - PCI device that we're dealing with
1148 void pci_restore_state(struct pci_dev *dev)
1150 if (!dev->state_saved)
1153 /* PCI Express register must be restored first */
1154 pci_restore_pcie_state(dev);
1155 pci_restore_ats_state(dev);
1156 pci_restore_vc_state(dev);
1158 pci_cleanup_aer_error_status_regs(dev);
1160 pci_restore_config_space(dev);
1162 pci_restore_pcix_state(dev);
1163 pci_restore_msi_state(dev);
1165 /* Restore ACS and IOV configuration state */
1166 pci_enable_acs(dev);
1167 pci_restore_iov_state(dev);
1169 dev->state_saved = false;
1171 EXPORT_SYMBOL(pci_restore_state);
1173 struct pci_saved_state {
1174 u32 config_space[16];
1175 struct pci_cap_saved_data cap[0];
1179 * pci_store_saved_state - Allocate and return an opaque struct containing
1180 * the device saved state.
1181 * @dev: PCI device that we're dealing with
1183 * Return NULL if no state or error.
1185 struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev)
1187 struct pci_saved_state *state;
1188 struct pci_cap_saved_state *tmp;
1189 struct pci_cap_saved_data *cap;
1192 if (!dev->state_saved)
1195 size = sizeof(*state) + sizeof(struct pci_cap_saved_data);
1197 hlist_for_each_entry(tmp, &dev->saved_cap_space, next)
1198 size += sizeof(struct pci_cap_saved_data) + tmp->cap.size;
1200 state = kzalloc(size, GFP_KERNEL);
1204 memcpy(state->config_space, dev->saved_config_space,
1205 sizeof(state->config_space));
1208 hlist_for_each_entry(tmp, &dev->saved_cap_space, next) {
1209 size_t len = sizeof(struct pci_cap_saved_data) + tmp->cap.size;
1210 memcpy(cap, &tmp->cap, len);
1211 cap = (struct pci_cap_saved_data *)((u8 *)cap + len);
1213 /* Empty cap_save terminates list */
1217 EXPORT_SYMBOL_GPL(pci_store_saved_state);
1220 * pci_load_saved_state - Reload the provided save state into struct pci_dev.
1221 * @dev: PCI device that we're dealing with
1222 * @state: Saved state returned from pci_store_saved_state()
1224 int pci_load_saved_state(struct pci_dev *dev,
1225 struct pci_saved_state *state)
1227 struct pci_cap_saved_data *cap;
1229 dev->state_saved = false;
1234 memcpy(dev->saved_config_space, state->config_space,
1235 sizeof(state->config_space));
1239 struct pci_cap_saved_state *tmp;
1241 tmp = _pci_find_saved_cap(dev, cap->cap_nr, cap->cap_extended);
1242 if (!tmp || tmp->cap.size != cap->size)
1245 memcpy(tmp->cap.data, cap->data, tmp->cap.size);
1246 cap = (struct pci_cap_saved_data *)((u8 *)cap +
1247 sizeof(struct pci_cap_saved_data) + cap->size);
1250 dev->state_saved = true;
1253 EXPORT_SYMBOL_GPL(pci_load_saved_state);
1256 * pci_load_and_free_saved_state - Reload the save state pointed to by state,
1257 * and free the memory allocated for it.
1258 * @dev: PCI device that we're dealing with
1259 * @state: Pointer to saved state returned from pci_store_saved_state()
1261 int pci_load_and_free_saved_state(struct pci_dev *dev,
1262 struct pci_saved_state **state)
1264 int ret = pci_load_saved_state(dev, *state);
1269 EXPORT_SYMBOL_GPL(pci_load_and_free_saved_state);
1271 int __weak pcibios_enable_device(struct pci_dev *dev, int bars)
1273 return pci_enable_resources(dev, bars);
1276 static int do_pci_enable_device(struct pci_dev *dev, int bars)
1279 struct pci_dev *bridge;
1283 err = pci_set_power_state(dev, PCI_D0);
1284 if (err < 0 && err != -EIO)
1287 bridge = pci_upstream_bridge(dev);
1289 pcie_aspm_powersave_config_link(bridge);
1291 err = pcibios_enable_device(dev, bars);
1294 pci_fixup_device(pci_fixup_enable, dev);
1296 if (dev->msi_enabled || dev->msix_enabled)
1299 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin);
1301 pci_read_config_word(dev, PCI_COMMAND, &cmd);
1302 if (cmd & PCI_COMMAND_INTX_DISABLE)
1303 pci_write_config_word(dev, PCI_COMMAND,
1304 cmd & ~PCI_COMMAND_INTX_DISABLE);
1311 * pci_reenable_device - Resume abandoned device
1312 * @dev: PCI device to be resumed
1314 * Note this function is a backend of pci_default_resume and is not supposed
1315 * to be called by normal code, write proper resume handler and use it instead.
1317 int pci_reenable_device(struct pci_dev *dev)
1319 if (pci_is_enabled(dev))
1320 return do_pci_enable_device(dev, (1 << PCI_NUM_RESOURCES) - 1);
1323 EXPORT_SYMBOL(pci_reenable_device);
1325 static void pci_enable_bridge(struct pci_dev *dev)
1327 struct pci_dev *bridge;
1330 bridge = pci_upstream_bridge(dev);
1332 pci_enable_bridge(bridge);
1334 if (pci_is_enabled(dev)) {
1335 if (!dev->is_busmaster)
1336 pci_set_master(dev);
1340 retval = pci_enable_device(dev);
1342 dev_err(&dev->dev, "Error enabling bridge (%d), continuing\n",
1344 pci_set_master(dev);
1347 static int pci_enable_device_flags(struct pci_dev *dev, unsigned long flags)
1349 struct pci_dev *bridge;
1354 * Power state could be unknown at this point, either due to a fresh
1355 * boot or a device removal call. So get the current power state
1356 * so that things like MSI message writing will behave as expected
1357 * (e.g. if the device really is in D0 at enable time).
1361 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
1362 dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK);
1365 if (atomic_inc_return(&dev->enable_cnt) > 1)
1366 return 0; /* already enabled */
1368 bridge = pci_upstream_bridge(dev);
1370 pci_enable_bridge(bridge);
1372 /* only skip sriov related */
1373 for (i = 0; i <= PCI_ROM_RESOURCE; i++)
1374 if (dev->resource[i].flags & flags)
1376 for (i = PCI_BRIDGE_RESOURCES; i < DEVICE_COUNT_RESOURCE; i++)
1377 if (dev->resource[i].flags & flags)
1380 err = do_pci_enable_device(dev, bars);
1382 atomic_dec(&dev->enable_cnt);
1387 * pci_enable_device_io - Initialize a device for use with IO space
1388 * @dev: PCI device to be initialized
1390 * Initialize device before it's used by a driver. Ask low-level code
1391 * to enable I/O resources. Wake up the device if it was suspended.
1392 * Beware, this function can fail.
1394 int pci_enable_device_io(struct pci_dev *dev)
1396 return pci_enable_device_flags(dev, IORESOURCE_IO);
1398 EXPORT_SYMBOL(pci_enable_device_io);
1401 * pci_enable_device_mem - Initialize a device for use with Memory space
1402 * @dev: PCI device to be initialized
1404 * Initialize device before it's used by a driver. Ask low-level code
1405 * to enable Memory resources. Wake up the device if it was suspended.
1406 * Beware, this function can fail.
1408 int pci_enable_device_mem(struct pci_dev *dev)
1410 return pci_enable_device_flags(dev, IORESOURCE_MEM);
1412 EXPORT_SYMBOL(pci_enable_device_mem);
1415 * pci_enable_device - Initialize device before it's used by a driver.
1416 * @dev: PCI device to be initialized
1418 * Initialize device before it's used by a driver. Ask low-level code
1419 * to enable I/O and memory. Wake up the device if it was suspended.
1420 * Beware, this function can fail.
1422 * Note we don't actually enable the device many times if we call
1423 * this function repeatedly (we just increment the count).
1425 int pci_enable_device(struct pci_dev *dev)
1427 return pci_enable_device_flags(dev, IORESOURCE_MEM | IORESOURCE_IO);
1429 EXPORT_SYMBOL(pci_enable_device);
1432 * Managed PCI resources. This manages device on/off, intx/msi/msix
1433 * on/off and BAR regions. pci_dev itself records msi/msix status, so
1434 * there's no need to track it separately. pci_devres is initialized
1435 * when a device is enabled using managed PCI device enable interface.
1438 unsigned int enabled:1;
1439 unsigned int pinned:1;
1440 unsigned int orig_intx:1;
1441 unsigned int restore_intx:1;
1445 static void pcim_release(struct device *gendev, void *res)
1447 struct pci_dev *dev = to_pci_dev(gendev);
1448 struct pci_devres *this = res;
1451 if (dev->msi_enabled)
1452 pci_disable_msi(dev);
1453 if (dev->msix_enabled)
1454 pci_disable_msix(dev);
1456 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++)
1457 if (this->region_mask & (1 << i))
1458 pci_release_region(dev, i);
1460 if (this->restore_intx)
1461 pci_intx(dev, this->orig_intx);
1463 if (this->enabled && !this->pinned)
1464 pci_disable_device(dev);
1467 static struct pci_devres *get_pci_dr(struct pci_dev *pdev)
1469 struct pci_devres *dr, *new_dr;
1471 dr = devres_find(&pdev->dev, pcim_release, NULL, NULL);
1475 new_dr = devres_alloc(pcim_release, sizeof(*new_dr), GFP_KERNEL);
1478 return devres_get(&pdev->dev, new_dr, NULL, NULL);
1481 static struct pci_devres *find_pci_dr(struct pci_dev *pdev)
1483 if (pci_is_managed(pdev))
1484 return devres_find(&pdev->dev, pcim_release, NULL, NULL);
1489 * pcim_enable_device - Managed pci_enable_device()
1490 * @pdev: PCI device to be initialized
1492 * Managed pci_enable_device().
1494 int pcim_enable_device(struct pci_dev *pdev)
1496 struct pci_devres *dr;
1499 dr = get_pci_dr(pdev);
1505 rc = pci_enable_device(pdev);
1507 pdev->is_managed = 1;
1512 EXPORT_SYMBOL(pcim_enable_device);
1515 * pcim_pin_device - Pin managed PCI device
1516 * @pdev: PCI device to pin
1518 * Pin managed PCI device @pdev. Pinned device won't be disabled on
1519 * driver detach. @pdev must have been enabled with
1520 * pcim_enable_device().
1522 void pcim_pin_device(struct pci_dev *pdev)
1524 struct pci_devres *dr;
1526 dr = find_pci_dr(pdev);
1527 WARN_ON(!dr || !dr->enabled);
1531 EXPORT_SYMBOL(pcim_pin_device);
1534 * pcibios_add_device - provide arch specific hooks when adding device dev
1535 * @dev: the PCI device being added
1537 * Permits the platform to provide architecture specific functionality when
1538 * devices are added. This is the default implementation. Architecture
1539 * implementations can override this.
1541 int __weak pcibios_add_device(struct pci_dev *dev)
1547 * pcibios_release_device - provide arch specific hooks when releasing device dev
1548 * @dev: the PCI device being released
1550 * Permits the platform to provide architecture specific functionality when
1551 * devices are released. This is the default implementation. Architecture
1552 * implementations can override this.
1554 void __weak pcibios_release_device(struct pci_dev *dev) {}
1557 * pcibios_disable_device - disable arch specific PCI resources for device dev
1558 * @dev: the PCI device to disable
1560 * Disables architecture specific PCI resources for the device. This
1561 * is the default implementation. Architecture implementations can
1564 void __weak pcibios_disable_device(struct pci_dev *dev) {}
1567 * pcibios_penalize_isa_irq - penalize an ISA IRQ
1568 * @irq: ISA IRQ to penalize
1569 * @active: IRQ active or not
1571 * Permits the platform to provide architecture-specific functionality when
1572 * penalizing ISA IRQs. This is the default implementation. Architecture
1573 * implementations can override this.
1575 void __weak pcibios_penalize_isa_irq(int irq, int active) {}
1577 static void do_pci_disable_device(struct pci_dev *dev)
1581 pci_read_config_word(dev, PCI_COMMAND, &pci_command);
1582 if (pci_command & PCI_COMMAND_MASTER) {
1583 pci_command &= ~PCI_COMMAND_MASTER;
1584 pci_write_config_word(dev, PCI_COMMAND, pci_command);
1587 pcibios_disable_device(dev);
1591 * pci_disable_enabled_device - Disable device without updating enable_cnt
1592 * @dev: PCI device to disable
1594 * NOTE: This function is a backend of PCI power management routines and is
1595 * not supposed to be called drivers.
1597 void pci_disable_enabled_device(struct pci_dev *dev)
1599 if (pci_is_enabled(dev))
1600 do_pci_disable_device(dev);
1604 * pci_disable_device - Disable PCI device after use
1605 * @dev: PCI device to be disabled
1607 * Signal to the system that the PCI device is not in use by the system
1608 * anymore. This only involves disabling PCI bus-mastering, if active.
1610 * Note we don't actually disable the device until all callers of
1611 * pci_enable_device() have called pci_disable_device().
1613 void pci_disable_device(struct pci_dev *dev)
1615 struct pci_devres *dr;
1617 dr = find_pci_dr(dev);
1621 dev_WARN_ONCE(&dev->dev, atomic_read(&dev->enable_cnt) <= 0,
1622 "disabling already-disabled device");
1624 if (atomic_dec_return(&dev->enable_cnt) != 0)
1627 do_pci_disable_device(dev);
1629 dev->is_busmaster = 0;
1631 EXPORT_SYMBOL(pci_disable_device);
1634 * pcibios_set_pcie_reset_state - set reset state for device dev
1635 * @dev: the PCIe device reset
1636 * @state: Reset state to enter into
1639 * Sets the PCIe reset state for the device. This is the default
1640 * implementation. Architecture implementations can override this.
1642 int __weak pcibios_set_pcie_reset_state(struct pci_dev *dev,
1643 enum pcie_reset_state state)
1649 * pci_set_pcie_reset_state - set reset state for device dev
1650 * @dev: the PCIe device reset
1651 * @state: Reset state to enter into
1654 * Sets the PCI reset state for the device.
1656 int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state)
1658 return pcibios_set_pcie_reset_state(dev, state);
1660 EXPORT_SYMBOL_GPL(pci_set_pcie_reset_state);
1663 * pci_check_pme_status - Check if given device has generated PME.
1664 * @dev: Device to check.
1666 * Check the PME status of the device and if set, clear it and clear PME enable
1667 * (if set). Return 'true' if PME status and PME enable were both set or
1668 * 'false' otherwise.
1670 bool pci_check_pme_status(struct pci_dev *dev)
1679 pmcsr_pos = dev->pm_cap + PCI_PM_CTRL;
1680 pci_read_config_word(dev, pmcsr_pos, &pmcsr);
1681 if (!(pmcsr & PCI_PM_CTRL_PME_STATUS))
1684 /* Clear PME status. */
1685 pmcsr |= PCI_PM_CTRL_PME_STATUS;
1686 if (pmcsr & PCI_PM_CTRL_PME_ENABLE) {
1687 /* Disable PME to avoid interrupt flood. */
1688 pmcsr &= ~PCI_PM_CTRL_PME_ENABLE;
1692 pci_write_config_word(dev, pmcsr_pos, pmcsr);
1698 * pci_pme_wakeup - Wake up a PCI device if its PME Status bit is set.
1699 * @dev: Device to handle.
1700 * @pme_poll_reset: Whether or not to reset the device's pme_poll flag.
1702 * Check if @dev has generated PME and queue a resume request for it in that
1705 static int pci_pme_wakeup(struct pci_dev *dev, void *pme_poll_reset)
1707 if (pme_poll_reset && dev->pme_poll)
1708 dev->pme_poll = false;
1710 if (pci_check_pme_status(dev)) {
1711 pci_wakeup_event(dev);
1712 pm_request_resume(&dev->dev);
1718 * pci_pme_wakeup_bus - Walk given bus and wake up devices on it, if necessary.
1719 * @bus: Top bus of the subtree to walk.
1721 void pci_pme_wakeup_bus(struct pci_bus *bus)
1724 pci_walk_bus(bus, pci_pme_wakeup, (void *)true);
1729 * pci_pme_capable - check the capability of PCI device to generate PME#
1730 * @dev: PCI device to handle.
1731 * @state: PCI state from which device will issue PME#.
1733 bool pci_pme_capable(struct pci_dev *dev, pci_power_t state)
1738 return !!(dev->pme_support & (1 << state));
1740 EXPORT_SYMBOL(pci_pme_capable);
1742 static void pci_pme_list_scan(struct work_struct *work)
1744 struct pci_pme_device *pme_dev, *n;
1746 mutex_lock(&pci_pme_list_mutex);
1747 list_for_each_entry_safe(pme_dev, n, &pci_pme_list, list) {
1748 if (pme_dev->dev->pme_poll) {
1749 struct pci_dev *bridge;
1751 bridge = pme_dev->dev->bus->self;
1753 * If bridge is in low power state, the
1754 * configuration space of subordinate devices
1755 * may be not accessible
1757 if (bridge && bridge->current_state != PCI_D0)
1759 pci_pme_wakeup(pme_dev->dev, NULL);
1761 list_del(&pme_dev->list);
1765 if (!list_empty(&pci_pme_list))
1766 schedule_delayed_work(&pci_pme_work,
1767 msecs_to_jiffies(PME_TIMEOUT));
1768 mutex_unlock(&pci_pme_list_mutex);
1771 static void __pci_pme_active(struct pci_dev *dev, bool enable)
1775 if (!dev->pme_support)
1778 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
1779 /* Clear PME_Status by writing 1 to it and enable PME# */
1780 pmcsr |= PCI_PM_CTRL_PME_STATUS | PCI_PM_CTRL_PME_ENABLE;
1782 pmcsr &= ~PCI_PM_CTRL_PME_ENABLE;
1784 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr);
1788 * pci_pme_active - enable or disable PCI device's PME# function
1789 * @dev: PCI device to handle.
1790 * @enable: 'true' to enable PME# generation; 'false' to disable it.
1792 * The caller must verify that the device is capable of generating PME# before
1793 * calling this function with @enable equal to 'true'.
1795 void pci_pme_active(struct pci_dev *dev, bool enable)
1797 __pci_pme_active(dev, enable);
1800 * PCI (as opposed to PCIe) PME requires that the device have
1801 * its PME# line hooked up correctly. Not all hardware vendors
1802 * do this, so the PME never gets delivered and the device
1803 * remains asleep. The easiest way around this is to
1804 * periodically walk the list of suspended devices and check
1805 * whether any have their PME flag set. The assumption is that
1806 * we'll wake up often enough anyway that this won't be a huge
1807 * hit, and the power savings from the devices will still be a
1810 * Although PCIe uses in-band PME message instead of PME# line
1811 * to report PME, PME does not work for some PCIe devices in
1812 * reality. For example, there are devices that set their PME
1813 * status bits, but don't really bother to send a PME message;
1814 * there are PCI Express Root Ports that don't bother to
1815 * trigger interrupts when they receive PME messages from the
1816 * devices below. So PME poll is used for PCIe devices too.
1819 if (dev->pme_poll) {
1820 struct pci_pme_device *pme_dev;
1822 pme_dev = kmalloc(sizeof(struct pci_pme_device),
1825 dev_warn(&dev->dev, "can't enable PME#\n");
1829 mutex_lock(&pci_pme_list_mutex);
1830 list_add(&pme_dev->list, &pci_pme_list);
1831 if (list_is_singular(&pci_pme_list))
1832 schedule_delayed_work(&pci_pme_work,
1833 msecs_to_jiffies(PME_TIMEOUT));
1834 mutex_unlock(&pci_pme_list_mutex);
1836 mutex_lock(&pci_pme_list_mutex);
1837 list_for_each_entry(pme_dev, &pci_pme_list, list) {
1838 if (pme_dev->dev == dev) {
1839 list_del(&pme_dev->list);
1844 mutex_unlock(&pci_pme_list_mutex);
1848 dev_dbg(&dev->dev, "PME# %s\n", enable ? "enabled" : "disabled");
1850 EXPORT_SYMBOL(pci_pme_active);
1853 * __pci_enable_wake - enable PCI device as wakeup event source
1854 * @dev: PCI device affected
1855 * @state: PCI state from which device will issue wakeup events
1856 * @runtime: True if the events are to be generated at run time
1857 * @enable: True to enable event generation; false to disable
1859 * This enables the device as a wakeup event source, or disables it.
1860 * When such events involves platform-specific hooks, those hooks are
1861 * called automatically by this routine.
1863 * Devices with legacy power management (no standard PCI PM capabilities)
1864 * always require such platform hooks.
1867 * 0 is returned on success
1868 * -EINVAL is returned if device is not supposed to wake up the system
1869 * Error code depending on the platform is returned if both the platform and
1870 * the native mechanism fail to enable the generation of wake-up events
1872 int __pci_enable_wake(struct pci_dev *dev, pci_power_t state,
1873 bool runtime, bool enable)
1877 if (enable && !runtime && !device_may_wakeup(&dev->dev))
1880 /* Don't do the same thing twice in a row for one device. */
1881 if (!!enable == !!dev->wakeup_prepared)
1885 * According to "PCI System Architecture" 4th ed. by Tom Shanley & Don
1886 * Anderson we should be doing PME# wake enable followed by ACPI wake
1887 * enable. To disable wake-up we call the platform first, for symmetry.
1893 if (pci_pme_capable(dev, state))
1894 pci_pme_active(dev, true);
1897 error = runtime ? platform_pci_run_wake(dev, true) :
1898 platform_pci_sleep_wake(dev, true);
1902 dev->wakeup_prepared = true;
1905 platform_pci_run_wake(dev, false);
1907 platform_pci_sleep_wake(dev, false);
1908 pci_pme_active(dev, false);
1909 dev->wakeup_prepared = false;
1914 EXPORT_SYMBOL(__pci_enable_wake);
1917 * pci_wake_from_d3 - enable/disable device to wake up from D3_hot or D3_cold
1918 * @dev: PCI device to prepare
1919 * @enable: True to enable wake-up event generation; false to disable
1921 * Many drivers want the device to wake up the system from D3_hot or D3_cold
1922 * and this function allows them to set that up cleanly - pci_enable_wake()
1923 * should not be called twice in a row to enable wake-up due to PCI PM vs ACPI
1924 * ordering constraints.
1926 * This function only returns error code if the device is not capable of
1927 * generating PME# from both D3_hot and D3_cold, and the platform is unable to
1928 * enable wake-up power for it.
1930 int pci_wake_from_d3(struct pci_dev *dev, bool enable)
1932 return pci_pme_capable(dev, PCI_D3cold) ?
1933 pci_enable_wake(dev, PCI_D3cold, enable) :
1934 pci_enable_wake(dev, PCI_D3hot, enable);
1936 EXPORT_SYMBOL(pci_wake_from_d3);
1939 * pci_target_state - find an appropriate low power state for a given PCI dev
1942 * Use underlying platform code to find a supported low power state for @dev.
1943 * If the platform can't manage @dev, return the deepest state from which it
1944 * can generate wake events, based on any available PME info.
1946 static pci_power_t pci_target_state(struct pci_dev *dev)
1948 pci_power_t target_state = PCI_D3hot;
1950 if (platform_pci_power_manageable(dev)) {
1952 * Call the platform to choose the target state of the device
1953 * and enable wake-up from this state if supported.
1955 pci_power_t state = platform_pci_choose_state(dev);
1958 case PCI_POWER_ERROR:
1963 if (pci_no_d1d2(dev))
1966 target_state = state;
1969 return target_state;
1973 target_state = PCI_D0;
1976 * If the device is in D3cold even though it's not power-manageable by
1977 * the platform, it may have been powered down by non-standard means.
1978 * Best to let it slumber.
1980 if (dev->current_state == PCI_D3cold)
1981 target_state = PCI_D3cold;
1983 if (device_may_wakeup(&dev->dev)) {
1985 * Find the deepest state from which the device can generate
1986 * wake-up events, make it the target state and enable device
1989 if (dev->pme_support) {
1991 && !(dev->pme_support & (1 << target_state)))
1996 return target_state;
2000 * pci_prepare_to_sleep - prepare PCI device for system-wide transition into a sleep state
2001 * @dev: Device to handle.
2003 * Choose the power state appropriate for the device depending on whether
2004 * it can wake up the system and/or is power manageable by the platform
2005 * (PCI_D3hot is the default) and put the device into that state.
2007 int pci_prepare_to_sleep(struct pci_dev *dev)
2009 pci_power_t target_state = pci_target_state(dev);
2012 if (target_state == PCI_POWER_ERROR)
2015 pci_enable_wake(dev, target_state, device_may_wakeup(&dev->dev));
2017 error = pci_set_power_state(dev, target_state);
2020 pci_enable_wake(dev, target_state, false);
2024 EXPORT_SYMBOL(pci_prepare_to_sleep);
2027 * pci_back_from_sleep - turn PCI device on during system-wide transition into working state
2028 * @dev: Device to handle.
2030 * Disable device's system wake-up capability and put it into D0.
2032 int pci_back_from_sleep(struct pci_dev *dev)
2034 pci_enable_wake(dev, PCI_D0, false);
2035 return pci_set_power_state(dev, PCI_D0);
2037 EXPORT_SYMBOL(pci_back_from_sleep);
2040 * pci_finish_runtime_suspend - Carry out PCI-specific part of runtime suspend.
2041 * @dev: PCI device being suspended.
2043 * Prepare @dev to generate wake-up events at run time and put it into a low
2046 int pci_finish_runtime_suspend(struct pci_dev *dev)
2048 pci_power_t target_state = pci_target_state(dev);
2051 if (target_state == PCI_POWER_ERROR)
2054 dev->runtime_d3cold = target_state == PCI_D3cold;
2056 __pci_enable_wake(dev, target_state, true, pci_dev_run_wake(dev));
2058 error = pci_set_power_state(dev, target_state);
2061 __pci_enable_wake(dev, target_state, true, false);
2062 dev->runtime_d3cold = false;
2069 * pci_dev_run_wake - Check if device can generate run-time wake-up events.
2070 * @dev: Device to check.
2072 * Return true if the device itself is capable of generating wake-up events
2073 * (through the platform or using the native PCIe PME) or if the device supports
2074 * PME and one of its upstream bridges can generate wake-up events.
2076 bool pci_dev_run_wake(struct pci_dev *dev)
2078 struct pci_bus *bus = dev->bus;
2080 if (device_run_wake(&dev->dev))
2083 if (!dev->pme_support)
2086 while (bus->parent) {
2087 struct pci_dev *bridge = bus->self;
2089 if (device_run_wake(&bridge->dev))
2095 /* We have reached the root bus. */
2097 return device_run_wake(bus->bridge);
2101 EXPORT_SYMBOL_GPL(pci_dev_run_wake);
2104 * pci_dev_keep_suspended - Check if the device can stay in the suspended state.
2105 * @pci_dev: Device to check.
2107 * Return 'true' if the device is runtime-suspended, it doesn't have to be
2108 * reconfigured due to wakeup settings difference between system and runtime
2109 * suspend and the current power state of it is suitable for the upcoming
2110 * (system) transition.
2112 * If the device is not configured for system wakeup, disable PME for it before
2113 * returning 'true' to prevent it from waking up the system unnecessarily.
2115 bool pci_dev_keep_suspended(struct pci_dev *pci_dev)
2117 struct device *dev = &pci_dev->dev;
2119 if (!pm_runtime_suspended(dev)
2120 || pci_target_state(pci_dev) != pci_dev->current_state
2121 || platform_pci_need_resume(pci_dev))
2125 * At this point the device is good to go unless it's been configured
2126 * to generate PME at the runtime suspend time, but it is not supposed
2127 * to wake up the system. In that case, simply disable PME for it
2128 * (it will have to be re-enabled on exit from system resume).
2130 * If the device's power state is D3cold and the platform check above
2131 * hasn't triggered, the device's configuration is suitable and we don't
2132 * need to manipulate it at all.
2134 spin_lock_irq(&dev->power.lock);
2136 if (pm_runtime_suspended(dev) && pci_dev->current_state < PCI_D3cold &&
2137 !device_may_wakeup(dev))
2138 __pci_pme_active(pci_dev, false);
2140 spin_unlock_irq(&dev->power.lock);
2145 * pci_dev_complete_resume - Finalize resume from system sleep for a device.
2146 * @pci_dev: Device to handle.
2148 * If the device is runtime suspended and wakeup-capable, enable PME for it as
2149 * it might have been disabled during the prepare phase of system suspend if
2150 * the device was not configured for system wakeup.
2152 void pci_dev_complete_resume(struct pci_dev *pci_dev)
2154 struct device *dev = &pci_dev->dev;
2156 if (!pci_dev_run_wake(pci_dev))
2159 spin_lock_irq(&dev->power.lock);
2161 if (pm_runtime_suspended(dev) && pci_dev->current_state < PCI_D3cold)
2162 __pci_pme_active(pci_dev, true);
2164 spin_unlock_irq(&dev->power.lock);
2167 void pci_config_pm_runtime_get(struct pci_dev *pdev)
2169 struct device *dev = &pdev->dev;
2170 struct device *parent = dev->parent;
2173 pm_runtime_get_sync(parent);
2174 pm_runtime_get_noresume(dev);
2176 * pdev->current_state is set to PCI_D3cold during suspending,
2177 * so wait until suspending completes
2179 pm_runtime_barrier(dev);
2181 * Only need to resume devices in D3cold, because config
2182 * registers are still accessible for devices suspended but
2185 if (pdev->current_state == PCI_D3cold)
2186 pm_runtime_resume(dev);
2189 void pci_config_pm_runtime_put(struct pci_dev *pdev)
2191 struct device *dev = &pdev->dev;
2192 struct device *parent = dev->parent;
2194 pm_runtime_put(dev);
2196 pm_runtime_put_sync(parent);
2200 * pci_bridge_d3_possible - Is it possible to put the bridge into D3
2201 * @bridge: Bridge to check
2203 * This function checks if it is possible to move the bridge to D3.
2204 * Currently we only allow D3 for recent enough PCIe ports.
2206 static bool pci_bridge_d3_possible(struct pci_dev *bridge)
2210 if (!pci_is_pcie(bridge))
2213 switch (pci_pcie_type(bridge)) {
2214 case PCI_EXP_TYPE_ROOT_PORT:
2215 case PCI_EXP_TYPE_UPSTREAM:
2216 case PCI_EXP_TYPE_DOWNSTREAM:
2217 if (pci_bridge_d3_disable)
2219 if (pci_bridge_d3_force)
2223 * It should be safe to put PCIe ports from 2015 or newer
2226 if (dmi_get_date(DMI_BIOS_DATE, &year, NULL, NULL) &&
2236 static int pci_dev_check_d3cold(struct pci_dev *dev, void *data)
2238 bool *d3cold_ok = data;
2242 * The device needs to be allowed to go D3cold and if it is wake
2243 * capable to do so from D3cold.
2245 no_d3cold = dev->no_d3cold || !dev->d3cold_allowed ||
2246 (device_may_wakeup(&dev->dev) && !pci_pme_capable(dev, PCI_D3cold)) ||
2247 !pci_power_manageable(dev);
2249 *d3cold_ok = !no_d3cold;
2255 * pci_bridge_d3_update - Update bridge D3 capabilities
2256 * @dev: PCI device which is changed
2257 * @remove: Is the device being removed
2259 * Update upstream bridge PM capabilities accordingly depending on if the
2260 * device PM configuration was changed or the device is being removed. The
2261 * change is also propagated upstream.
2263 static void pci_bridge_d3_update(struct pci_dev *dev, bool remove)
2265 struct pci_dev *bridge;
2266 bool d3cold_ok = true;
2268 bridge = pci_upstream_bridge(dev);
2269 if (!bridge || !pci_bridge_d3_possible(bridge))
2272 pci_dev_get(bridge);
2274 * If the device is removed we do not care about its D3cold
2278 pci_dev_check_d3cold(dev, &d3cold_ok);
2282 * We need to go through all children to find out if all of
2283 * them can still go to D3cold.
2285 pci_walk_bus(bridge->subordinate, pci_dev_check_d3cold,
2289 if (bridge->bridge_d3 != d3cold_ok) {
2290 bridge->bridge_d3 = d3cold_ok;
2291 /* Propagate change to upstream bridges */
2292 pci_bridge_d3_update(bridge, false);
2295 pci_dev_put(bridge);
2299 * pci_bridge_d3_device_changed - Update bridge D3 capabilities on change
2300 * @dev: PCI device that was changed
2302 * If a device is added or its PM configuration, such as is it allowed to
2303 * enter D3cold, is changed this function updates upstream bridge PM
2304 * capabilities accordingly.
2306 void pci_bridge_d3_device_changed(struct pci_dev *dev)
2308 pci_bridge_d3_update(dev, false);
2312 * pci_bridge_d3_device_removed - Update bridge D3 capabilities on remove
2313 * @dev: PCI device being removed
2315 * Function updates upstream bridge PM capabilities based on other devices
2316 * still left on the bus.
2318 void pci_bridge_d3_device_removed(struct pci_dev *dev)
2320 pci_bridge_d3_update(dev, true);
2324 * pci_d3cold_enable - Enable D3cold for device
2325 * @dev: PCI device to handle
2327 * This function can be used in drivers to enable D3cold from the device
2328 * they handle. It also updates upstream PCI bridge PM capabilities
2331 void pci_d3cold_enable(struct pci_dev *dev)
2333 if (dev->no_d3cold) {
2334 dev->no_d3cold = false;
2335 pci_bridge_d3_device_changed(dev);
2338 EXPORT_SYMBOL_GPL(pci_d3cold_enable);
2341 * pci_d3cold_disable - Disable D3cold for device
2342 * @dev: PCI device to handle
2344 * This function can be used in drivers to disable D3cold from the device
2345 * they handle. It also updates upstream PCI bridge PM capabilities
2348 void pci_d3cold_disable(struct pci_dev *dev)
2350 if (!dev->no_d3cold) {
2351 dev->no_d3cold = true;
2352 pci_bridge_d3_device_changed(dev);
2355 EXPORT_SYMBOL_GPL(pci_d3cold_disable);
2358 * pci_pm_init - Initialize PM functions of given PCI device
2359 * @dev: PCI device to handle.
2361 void pci_pm_init(struct pci_dev *dev)
2366 pm_runtime_forbid(&dev->dev);
2367 pm_runtime_set_active(&dev->dev);
2368 pm_runtime_enable(&dev->dev);
2369 device_enable_async_suspend(&dev->dev);
2370 dev->wakeup_prepared = false;
2373 dev->pme_support = 0;
2375 /* find PCI PM capability in list */
2376 pm = pci_find_capability(dev, PCI_CAP_ID_PM);
2379 /* Check device's ability to generate PME# */
2380 pci_read_config_word(dev, pm + PCI_PM_PMC, &pmc);
2382 if ((pmc & PCI_PM_CAP_VER_MASK) > 3) {
2383 dev_err(&dev->dev, "unsupported PM cap regs version (%u)\n",
2384 pmc & PCI_PM_CAP_VER_MASK);
2389 dev->d3_delay = PCI_PM_D3_WAIT;
2390 dev->d3cold_delay = PCI_PM_D3COLD_WAIT;
2391 dev->bridge_d3 = pci_bridge_d3_possible(dev);
2392 dev->d3cold_allowed = true;
2394 dev->d1_support = false;
2395 dev->d2_support = false;
2396 if (!pci_no_d1d2(dev)) {
2397 if (pmc & PCI_PM_CAP_D1)
2398 dev->d1_support = true;
2399 if (pmc & PCI_PM_CAP_D2)
2400 dev->d2_support = true;
2402 if (dev->d1_support || dev->d2_support)
2403 dev_printk(KERN_DEBUG, &dev->dev, "supports%s%s\n",
2404 dev->d1_support ? " D1" : "",
2405 dev->d2_support ? " D2" : "");
2408 pmc &= PCI_PM_CAP_PME_MASK;
2410 dev_printk(KERN_DEBUG, &dev->dev,
2411 "PME# supported from%s%s%s%s%s\n",
2412 (pmc & PCI_PM_CAP_PME_D0) ? " D0" : "",
2413 (pmc & PCI_PM_CAP_PME_D1) ? " D1" : "",
2414 (pmc & PCI_PM_CAP_PME_D2) ? " D2" : "",
2415 (pmc & PCI_PM_CAP_PME_D3) ? " D3hot" : "",
2416 (pmc & PCI_PM_CAP_PME_D3cold) ? " D3cold" : "");
2417 dev->pme_support = pmc >> PCI_PM_CAP_PME_SHIFT;
2418 dev->pme_poll = true;
2420 * Make device's PM flags reflect the wake-up capability, but
2421 * let the user space enable it to wake up the system as needed.
2423 device_set_wakeup_capable(&dev->dev, true);
2424 /* Disable the PME# generation functionality */
2425 pci_pme_active(dev, false);
2429 static unsigned long pci_ea_flags(struct pci_dev *dev, u8 prop)
2431 unsigned long flags = IORESOURCE_PCI_FIXED | IORESOURCE_PCI_EA_BEI;
2435 case PCI_EA_P_VF_MEM:
2436 flags |= IORESOURCE_MEM;
2438 case PCI_EA_P_MEM_PREFETCH:
2439 case PCI_EA_P_VF_MEM_PREFETCH:
2440 flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH;
2443 flags |= IORESOURCE_IO;
2452 static struct resource *pci_ea_get_resource(struct pci_dev *dev, u8 bei,
2455 if (bei <= PCI_EA_BEI_BAR5 && prop <= PCI_EA_P_IO)
2456 return &dev->resource[bei];
2457 #ifdef CONFIG_PCI_IOV
2458 else if (bei >= PCI_EA_BEI_VF_BAR0 && bei <= PCI_EA_BEI_VF_BAR5 &&
2459 (prop == PCI_EA_P_VF_MEM || prop == PCI_EA_P_VF_MEM_PREFETCH))
2460 return &dev->resource[PCI_IOV_RESOURCES +
2461 bei - PCI_EA_BEI_VF_BAR0];
2463 else if (bei == PCI_EA_BEI_ROM)
2464 return &dev->resource[PCI_ROM_RESOURCE];
2469 /* Read an Enhanced Allocation (EA) entry */
2470 static int pci_ea_read(struct pci_dev *dev, int offset)
2472 struct resource *res;
2473 int ent_size, ent_offset = offset;
2474 resource_size_t start, end;
2475 unsigned long flags;
2476 u32 dw0, bei, base, max_offset;
2478 bool support_64 = (sizeof(resource_size_t) >= 8);
2480 pci_read_config_dword(dev, ent_offset, &dw0);
2483 /* Entry size field indicates DWORDs after 1st */
2484 ent_size = ((dw0 & PCI_EA_ES) + 1) << 2;
2486 if (!(dw0 & PCI_EA_ENABLE)) /* Entry not enabled */
2489 bei = (dw0 & PCI_EA_BEI) >> 4;
2490 prop = (dw0 & PCI_EA_PP) >> 8;
2493 * If the Property is in the reserved range, try the Secondary
2496 if (prop > PCI_EA_P_BRIDGE_IO && prop < PCI_EA_P_MEM_RESERVED)
2497 prop = (dw0 & PCI_EA_SP) >> 16;
2498 if (prop > PCI_EA_P_BRIDGE_IO)
2501 res = pci_ea_get_resource(dev, bei, prop);
2503 dev_err(&dev->dev, "Unsupported EA entry BEI: %u\n", bei);
2507 flags = pci_ea_flags(dev, prop);
2509 dev_err(&dev->dev, "Unsupported EA properties: %#x\n", prop);
2514 pci_read_config_dword(dev, ent_offset, &base);
2515 start = (base & PCI_EA_FIELD_MASK);
2518 /* Read MaxOffset */
2519 pci_read_config_dword(dev, ent_offset, &max_offset);
2522 /* Read Base MSBs (if 64-bit entry) */
2523 if (base & PCI_EA_IS_64) {
2526 pci_read_config_dword(dev, ent_offset, &base_upper);
2529 flags |= IORESOURCE_MEM_64;
2531 /* entry starts above 32-bit boundary, can't use */
2532 if (!support_64 && base_upper)
2536 start |= ((u64)base_upper << 32);
2539 end = start + (max_offset | 0x03);
2541 /* Read MaxOffset MSBs (if 64-bit entry) */
2542 if (max_offset & PCI_EA_IS_64) {
2543 u32 max_offset_upper;
2545 pci_read_config_dword(dev, ent_offset, &max_offset_upper);
2548 flags |= IORESOURCE_MEM_64;
2550 /* entry too big, can't use */
2551 if (!support_64 && max_offset_upper)
2555 end += ((u64)max_offset_upper << 32);
2559 dev_err(&dev->dev, "EA Entry crosses address boundary\n");
2563 if (ent_size != ent_offset - offset) {
2565 "EA Entry Size (%d) does not match length read (%d)\n",
2566 ent_size, ent_offset - offset);
2570 res->name = pci_name(dev);
2575 if (bei <= PCI_EA_BEI_BAR5)
2576 dev_printk(KERN_DEBUG, &dev->dev, "BAR %d: %pR (from Enhanced Allocation, properties %#02x)\n",
2578 else if (bei == PCI_EA_BEI_ROM)
2579 dev_printk(KERN_DEBUG, &dev->dev, "ROM: %pR (from Enhanced Allocation, properties %#02x)\n",
2581 else if (bei >= PCI_EA_BEI_VF_BAR0 && bei <= PCI_EA_BEI_VF_BAR5)
2582 dev_printk(KERN_DEBUG, &dev->dev, "VF BAR %d: %pR (from Enhanced Allocation, properties %#02x)\n",
2583 bei - PCI_EA_BEI_VF_BAR0, res, prop);
2585 dev_printk(KERN_DEBUG, &dev->dev, "BEI %d res: %pR (from Enhanced Allocation, properties %#02x)\n",
2589 return offset + ent_size;
2592 /* Enhanced Allocation Initialization */
2593 void pci_ea_init(struct pci_dev *dev)
2600 /* find PCI EA capability in list */
2601 ea = pci_find_capability(dev, PCI_CAP_ID_EA);
2605 /* determine the number of entries */
2606 pci_bus_read_config_byte(dev->bus, dev->devfn, ea + PCI_EA_NUM_ENT,
2608 num_ent &= PCI_EA_NUM_ENT_MASK;
2610 offset = ea + PCI_EA_FIRST_ENT;
2612 /* Skip DWORD 2 for type 1 functions */
2613 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE)
2616 /* parse each EA entry */
2617 for (i = 0; i < num_ent; ++i)
2618 offset = pci_ea_read(dev, offset);
2621 static void pci_add_saved_cap(struct pci_dev *pci_dev,
2622 struct pci_cap_saved_state *new_cap)
2624 hlist_add_head(&new_cap->next, &pci_dev->saved_cap_space);
2628 * _pci_add_cap_save_buffer - allocate buffer for saving given
2629 * capability registers
2630 * @dev: the PCI device
2631 * @cap: the capability to allocate the buffer for
2632 * @extended: Standard or Extended capability ID
2633 * @size: requested size of the buffer
2635 static int _pci_add_cap_save_buffer(struct pci_dev *dev, u16 cap,
2636 bool extended, unsigned int size)
2639 struct pci_cap_saved_state *save_state;
2642 pos = pci_find_ext_capability(dev, cap);
2644 pos = pci_find_capability(dev, cap);
2649 save_state = kzalloc(sizeof(*save_state) + size, GFP_KERNEL);
2653 save_state->cap.cap_nr = cap;
2654 save_state->cap.cap_extended = extended;
2655 save_state->cap.size = size;
2656 pci_add_saved_cap(dev, save_state);
2661 int pci_add_cap_save_buffer(struct pci_dev *dev, char cap, unsigned int size)
2663 return _pci_add_cap_save_buffer(dev, cap, false, size);
2666 int pci_add_ext_cap_save_buffer(struct pci_dev *dev, u16 cap, unsigned int size)
2668 return _pci_add_cap_save_buffer(dev, cap, true, size);
2672 * pci_allocate_cap_save_buffers - allocate buffers for saving capabilities
2673 * @dev: the PCI device
2675 void pci_allocate_cap_save_buffers(struct pci_dev *dev)
2679 error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_EXP,
2680 PCI_EXP_SAVE_REGS * sizeof(u16));
2683 "unable to preallocate PCI Express save buffer\n");
2685 error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_PCIX, sizeof(u16));
2688 "unable to preallocate PCI-X save buffer\n");
2690 pci_allocate_vc_save_buffers(dev);
2693 void pci_free_cap_save_buffers(struct pci_dev *dev)
2695 struct pci_cap_saved_state *tmp;
2696 struct hlist_node *n;
2698 hlist_for_each_entry_safe(tmp, n, &dev->saved_cap_space, next)
2703 * pci_configure_ari - enable or disable ARI forwarding
2704 * @dev: the PCI device
2706 * If @dev and its upstream bridge both support ARI, enable ARI in the
2707 * bridge. Otherwise, disable ARI in the bridge.
2709 void pci_configure_ari(struct pci_dev *dev)
2712 struct pci_dev *bridge;
2714 if (pcie_ari_disabled || !pci_is_pcie(dev) || dev->devfn)
2717 bridge = dev->bus->self;
2721 pcie_capability_read_dword(bridge, PCI_EXP_DEVCAP2, &cap);
2722 if (!(cap & PCI_EXP_DEVCAP2_ARI))
2725 if (pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI)) {
2726 pcie_capability_set_word(bridge, PCI_EXP_DEVCTL2,
2727 PCI_EXP_DEVCTL2_ARI);
2728 bridge->ari_enabled = 1;
2730 pcie_capability_clear_word(bridge, PCI_EXP_DEVCTL2,
2731 PCI_EXP_DEVCTL2_ARI);
2732 bridge->ari_enabled = 0;
2736 static int pci_acs_enable;
2739 * pci_request_acs - ask for ACS to be enabled if supported
2741 void pci_request_acs(void)
2747 * pci_std_enable_acs - enable ACS on devices using standard ACS capabilites
2748 * @dev: the PCI device
2750 static void pci_std_enable_acs(struct pci_dev *dev)
2756 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ACS);
2760 pci_read_config_word(dev, pos + PCI_ACS_CAP, &cap);
2761 pci_read_config_word(dev, pos + PCI_ACS_CTRL, &ctrl);
2763 /* Source Validation */
2764 ctrl |= (cap & PCI_ACS_SV);
2766 /* P2P Request Redirect */
2767 ctrl |= (cap & PCI_ACS_RR);
2769 /* P2P Completion Redirect */
2770 ctrl |= (cap & PCI_ACS_CR);
2772 /* Upstream Forwarding */
2773 ctrl |= (cap & PCI_ACS_UF);
2775 pci_write_config_word(dev, pos + PCI_ACS_CTRL, ctrl);
2779 * pci_enable_acs - enable ACS if hardware support it
2780 * @dev: the PCI device
2782 void pci_enable_acs(struct pci_dev *dev)
2784 if (!pci_acs_enable)
2787 if (!pci_dev_specific_enable_acs(dev))
2790 pci_std_enable_acs(dev);
2793 static bool pci_acs_flags_enabled(struct pci_dev *pdev, u16 acs_flags)
2798 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ACS);
2803 * Except for egress control, capabilities are either required
2804 * or only required if controllable. Features missing from the
2805 * capability field can therefore be assumed as hard-wired enabled.
2807 pci_read_config_word(pdev, pos + PCI_ACS_CAP, &cap);
2808 acs_flags &= (cap | PCI_ACS_EC);
2810 pci_read_config_word(pdev, pos + PCI_ACS_CTRL, &ctrl);
2811 return (ctrl & acs_flags) == acs_flags;
2815 * pci_acs_enabled - test ACS against required flags for a given device
2816 * @pdev: device to test
2817 * @acs_flags: required PCI ACS flags
2819 * Return true if the device supports the provided flags. Automatically
2820 * filters out flags that are not implemented on multifunction devices.
2822 * Note that this interface checks the effective ACS capabilities of the
2823 * device rather than the actual capabilities. For instance, most single
2824 * function endpoints are not required to support ACS because they have no
2825 * opportunity for peer-to-peer access. We therefore return 'true'
2826 * regardless of whether the device exposes an ACS capability. This makes
2827 * it much easier for callers of this function to ignore the actual type
2828 * or topology of the device when testing ACS support.
2830 bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags)
2834 ret = pci_dev_specific_acs_enabled(pdev, acs_flags);
2839 * Conventional PCI and PCI-X devices never support ACS, either
2840 * effectively or actually. The shared bus topology implies that
2841 * any device on the bus can receive or snoop DMA.
2843 if (!pci_is_pcie(pdev))
2846 switch (pci_pcie_type(pdev)) {
2848 * PCI/X-to-PCIe bridges are not specifically mentioned by the spec,
2849 * but since their primary interface is PCI/X, we conservatively
2850 * handle them as we would a non-PCIe device.
2852 case PCI_EXP_TYPE_PCIE_BRIDGE:
2854 * PCIe 3.0, 6.12.1 excludes ACS on these devices. "ACS is never
2855 * applicable... must never implement an ACS Extended Capability...".
2856 * This seems arbitrary, but we take a conservative interpretation
2857 * of this statement.
2859 case PCI_EXP_TYPE_PCI_BRIDGE:
2860 case PCI_EXP_TYPE_RC_EC:
2863 * PCIe 3.0, 6.12.1.1 specifies that downstream and root ports should
2864 * implement ACS in order to indicate their peer-to-peer capabilities,
2865 * regardless of whether they are single- or multi-function devices.
2867 case PCI_EXP_TYPE_DOWNSTREAM:
2868 case PCI_EXP_TYPE_ROOT_PORT:
2869 return pci_acs_flags_enabled(pdev, acs_flags);
2871 * PCIe 3.0, 6.12.1.2 specifies ACS capabilities that should be
2872 * implemented by the remaining PCIe types to indicate peer-to-peer
2873 * capabilities, but only when they are part of a multifunction
2874 * device. The footnote for section 6.12 indicates the specific
2875 * PCIe types included here.
2877 case PCI_EXP_TYPE_ENDPOINT:
2878 case PCI_EXP_TYPE_UPSTREAM:
2879 case PCI_EXP_TYPE_LEG_END:
2880 case PCI_EXP_TYPE_RC_END:
2881 if (!pdev->multifunction)
2884 return pci_acs_flags_enabled(pdev, acs_flags);
2888 * PCIe 3.0, 6.12.1.3 specifies no ACS capabilities are applicable
2889 * to single function devices with the exception of downstream ports.
2895 * pci_acs_path_enable - test ACS flags from start to end in a hierarchy
2896 * @start: starting downstream device
2897 * @end: ending upstream device or NULL to search to the root bus
2898 * @acs_flags: required flags
2900 * Walk up a device tree from start to end testing PCI ACS support. If
2901 * any step along the way does not support the required flags, return false.
2903 bool pci_acs_path_enabled(struct pci_dev *start,
2904 struct pci_dev *end, u16 acs_flags)
2906 struct pci_dev *pdev, *parent = start;
2911 if (!pci_acs_enabled(pdev, acs_flags))
2914 if (pci_is_root_bus(pdev->bus))
2915 return (end == NULL);
2917 parent = pdev->bus->self;
2918 } while (pdev != end);
2924 * pci_swizzle_interrupt_pin - swizzle INTx for device behind bridge
2925 * @dev: the PCI device
2926 * @pin: the INTx pin (1=INTA, 2=INTB, 3=INTC, 4=INTD)
2928 * Perform INTx swizzling for a device behind one level of bridge. This is
2929 * required by section 9.1 of the PCI-to-PCI bridge specification for devices
2930 * behind bridges on add-in cards. For devices with ARI enabled, the slot
2931 * number is always 0 (see the Implementation Note in section 2.2.8.1 of
2932 * the PCI Express Base Specification, Revision 2.1)
2934 u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin)
2938 if (pci_ari_enabled(dev->bus))
2941 slot = PCI_SLOT(dev->devfn);
2943 return (((pin - 1) + slot) % 4) + 1;
2946 int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge)
2954 while (!pci_is_root_bus(dev->bus)) {
2955 pin = pci_swizzle_interrupt_pin(dev, pin);
2956 dev = dev->bus->self;
2963 * pci_common_swizzle - swizzle INTx all the way to root bridge
2964 * @dev: the PCI device
2965 * @pinp: pointer to the INTx pin value (1=INTA, 2=INTB, 3=INTD, 4=INTD)
2967 * Perform INTx swizzling for a device. This traverses through all PCI-to-PCI
2968 * bridges all the way up to a PCI root bus.
2970 u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp)
2974 while (!pci_is_root_bus(dev->bus)) {
2975 pin = pci_swizzle_interrupt_pin(dev, pin);
2976 dev = dev->bus->self;
2979 return PCI_SLOT(dev->devfn);
2981 EXPORT_SYMBOL_GPL(pci_common_swizzle);
2984 * pci_release_region - Release a PCI bar
2985 * @pdev: PCI device whose resources were previously reserved by pci_request_region
2986 * @bar: BAR to release
2988 * Releases the PCI I/O and memory resources previously reserved by a
2989 * successful call to pci_request_region. Call this function only
2990 * after all use of the PCI regions has ceased.
2992 void pci_release_region(struct pci_dev *pdev, int bar)
2994 struct pci_devres *dr;
2996 if (pci_resource_len(pdev, bar) == 0)
2998 if (pci_resource_flags(pdev, bar) & IORESOURCE_IO)
2999 release_region(pci_resource_start(pdev, bar),
3000 pci_resource_len(pdev, bar));
3001 else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM)
3002 release_mem_region(pci_resource_start(pdev, bar),
3003 pci_resource_len(pdev, bar));
3005 dr = find_pci_dr(pdev);
3007 dr->region_mask &= ~(1 << bar);
3009 EXPORT_SYMBOL(pci_release_region);
3012 * __pci_request_region - Reserved PCI I/O and memory resource
3013 * @pdev: PCI device whose resources are to be reserved
3014 * @bar: BAR to be reserved
3015 * @res_name: Name to be associated with resource.
3016 * @exclusive: whether the region access is exclusive or not
3018 * Mark the PCI region associated with PCI device @pdev BR @bar as
3019 * being reserved by owner @res_name. Do not access any
3020 * address inside the PCI regions unless this call returns
3023 * If @exclusive is set, then the region is marked so that userspace
3024 * is explicitly not allowed to map the resource via /dev/mem or
3025 * sysfs MMIO access.
3027 * Returns 0 on success, or %EBUSY on error. A warning
3028 * message is also printed on failure.
3030 static int __pci_request_region(struct pci_dev *pdev, int bar,
3031 const char *res_name, int exclusive)
3033 struct pci_devres *dr;
3035 if (pci_resource_len(pdev, bar) == 0)
3038 if (pci_resource_flags(pdev, bar) & IORESOURCE_IO) {
3039 if (!request_region(pci_resource_start(pdev, bar),
3040 pci_resource_len(pdev, bar), res_name))
3042 } else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) {
3043 if (!__request_mem_region(pci_resource_start(pdev, bar),
3044 pci_resource_len(pdev, bar), res_name,
3049 dr = find_pci_dr(pdev);
3051 dr->region_mask |= 1 << bar;
3056 dev_warn(&pdev->dev, "BAR %d: can't reserve %pR\n", bar,
3057 &pdev->resource[bar]);
3062 * pci_request_region - Reserve PCI I/O and memory resource
3063 * @pdev: PCI device whose resources are to be reserved
3064 * @bar: BAR to be reserved
3065 * @res_name: Name to be associated with resource
3067 * Mark the PCI region associated with PCI device @pdev BAR @bar as
3068 * being reserved by owner @res_name. Do not access any
3069 * address inside the PCI regions unless this call returns
3072 * Returns 0 on success, or %EBUSY on error. A warning
3073 * message is also printed on failure.
3075 int pci_request_region(struct pci_dev *pdev, int bar, const char *res_name)
3077 return __pci_request_region(pdev, bar, res_name, 0);
3079 EXPORT_SYMBOL(pci_request_region);
3082 * pci_request_region_exclusive - Reserved PCI I/O and memory resource
3083 * @pdev: PCI device whose resources are to be reserved
3084 * @bar: BAR to be reserved
3085 * @res_name: Name to be associated with resource.
3087 * Mark the PCI region associated with PCI device @pdev BR @bar as
3088 * being reserved by owner @res_name. Do not access any
3089 * address inside the PCI regions unless this call returns
3092 * Returns 0 on success, or %EBUSY on error. A warning
3093 * message is also printed on failure.
3095 * The key difference that _exclusive makes it that userspace is
3096 * explicitly not allowed to map the resource via /dev/mem or
3099 int pci_request_region_exclusive(struct pci_dev *pdev, int bar,
3100 const char *res_name)
3102 return __pci_request_region(pdev, bar, res_name, IORESOURCE_EXCLUSIVE);
3104 EXPORT_SYMBOL(pci_request_region_exclusive);
3107 * pci_release_selected_regions - Release selected PCI I/O and memory resources
3108 * @pdev: PCI device whose resources were previously reserved
3109 * @bars: Bitmask of BARs to be released
3111 * Release selected PCI I/O and memory resources previously reserved.
3112 * Call this function only after all use of the PCI regions has ceased.
3114 void pci_release_selected_regions(struct pci_dev *pdev, int bars)
3118 for (i = 0; i < 6; i++)
3119 if (bars & (1 << i))
3120 pci_release_region(pdev, i);
3122 EXPORT_SYMBOL(pci_release_selected_regions);
3124 static int __pci_request_selected_regions(struct pci_dev *pdev, int bars,
3125 const char *res_name, int excl)
3129 for (i = 0; i < 6; i++)
3130 if (bars & (1 << i))
3131 if (__pci_request_region(pdev, i, res_name, excl))
3137 if (bars & (1 << i))
3138 pci_release_region(pdev, i);
3145 * pci_request_selected_regions - Reserve selected PCI I/O and memory resources
3146 * @pdev: PCI device whose resources are to be reserved
3147 * @bars: Bitmask of BARs to be requested
3148 * @res_name: Name to be associated with resource
3150 int pci_request_selected_regions(struct pci_dev *pdev, int bars,
3151 const char *res_name)
3153 return __pci_request_selected_regions(pdev, bars, res_name, 0);
3155 EXPORT_SYMBOL(pci_request_selected_regions);
3157 int pci_request_selected_regions_exclusive(struct pci_dev *pdev, int bars,
3158 const char *res_name)
3160 return __pci_request_selected_regions(pdev, bars, res_name,
3161 IORESOURCE_EXCLUSIVE);
3163 EXPORT_SYMBOL(pci_request_selected_regions_exclusive);
3166 * pci_release_regions - Release reserved PCI I/O and memory resources
3167 * @pdev: PCI device whose resources were previously reserved by pci_request_regions
3169 * Releases all PCI I/O and memory resources previously reserved by a
3170 * successful call to pci_request_regions. Call this function only
3171 * after all use of the PCI regions has ceased.
3174 void pci_release_regions(struct pci_dev *pdev)
3176 pci_release_selected_regions(pdev, (1 << 6) - 1);
3178 EXPORT_SYMBOL(pci_release_regions);
3181 * pci_request_regions - Reserved PCI I/O and memory resources
3182 * @pdev: PCI device whose resources are to be reserved
3183 * @res_name: Name to be associated with resource.
3185 * Mark all PCI regions associated with PCI device @pdev as
3186 * being reserved by owner @res_name. Do not access any
3187 * address inside the PCI regions unless this call returns
3190 * Returns 0 on success, or %EBUSY on error. A warning
3191 * message is also printed on failure.
3193 int pci_request_regions(struct pci_dev *pdev, const char *res_name)
3195 return pci_request_selected_regions(pdev, ((1 << 6) - 1), res_name);
3197 EXPORT_SYMBOL(pci_request_regions);
3200 * pci_request_regions_exclusive - Reserved PCI I/O and memory resources
3201 * @pdev: PCI device whose resources are to be reserved
3202 * @res_name: Name to be associated with resource.
3204 * Mark all PCI regions associated with PCI device @pdev as
3205 * being reserved by owner @res_name. Do not access any
3206 * address inside the PCI regions unless this call returns
3209 * pci_request_regions_exclusive() will mark the region so that
3210 * /dev/mem and the sysfs MMIO access will not be allowed.
3212 * Returns 0 on success, or %EBUSY on error. A warning
3213 * message is also printed on failure.
3215 int pci_request_regions_exclusive(struct pci_dev *pdev, const char *res_name)
3217 return pci_request_selected_regions_exclusive(pdev,
3218 ((1 << 6) - 1), res_name);
3220 EXPORT_SYMBOL(pci_request_regions_exclusive);
3224 struct list_head list;
3226 resource_size_t size;
3229 static LIST_HEAD(io_range_list);
3230 static DEFINE_SPINLOCK(io_range_lock);
3234 * Record the PCI IO range (expressed as CPU physical address + size).
3235 * Return a negative value if an error has occured, zero otherwise
3237 int __weak pci_register_io_range(phys_addr_t addr, resource_size_t size)
3242 struct io_range *range;
3243 resource_size_t allocated_size = 0;
3245 /* check if the range hasn't been previously recorded */
3246 spin_lock(&io_range_lock);
3247 list_for_each_entry(range, &io_range_list, list) {
3248 if (addr >= range->start && addr + size <= range->start + size) {
3249 /* range already registered, bail out */
3252 allocated_size += range->size;
3255 /* range not registed yet, check for available space */
3256 if (allocated_size + size - 1 > IO_SPACE_LIMIT) {
3257 /* if it's too big check if 64K space can be reserved */
3258 if (allocated_size + SZ_64K - 1 > IO_SPACE_LIMIT) {
3264 pr_warn("Requested IO range too big, new size set to 64K\n");
3267 /* add the range to the list */
3268 range = kzalloc(sizeof(*range), GFP_ATOMIC);
3274 range->start = addr;
3277 list_add_tail(&range->list, &io_range_list);
3280 spin_unlock(&io_range_lock);
3286 phys_addr_t pci_pio_to_address(unsigned long pio)
3288 phys_addr_t address = (phys_addr_t)OF_BAD_ADDR;
3291 struct io_range *range;
3292 resource_size_t allocated_size = 0;
3294 if (pio > IO_SPACE_LIMIT)
3297 spin_lock(&io_range_lock);
3298 list_for_each_entry(range, &io_range_list, list) {
3299 if (pio >= allocated_size && pio < allocated_size + range->size) {
3300 address = range->start + pio - allocated_size;
3303 allocated_size += range->size;
3305 spin_unlock(&io_range_lock);
3311 unsigned long __weak pci_address_to_pio(phys_addr_t address)
3314 struct io_range *res;
3315 resource_size_t offset = 0;
3316 unsigned long addr = -1;
3318 spin_lock(&io_range_lock);
3319 list_for_each_entry(res, &io_range_list, list) {
3320 if (address >= res->start && address < res->start + res->size) {
3321 addr = address - res->start + offset;
3324 offset += res->size;
3326 spin_unlock(&io_range_lock);
3330 if (address > IO_SPACE_LIMIT)
3331 return (unsigned long)-1;
3333 return (unsigned long) address;
3338 * pci_remap_iospace - Remap the memory mapped I/O space
3339 * @res: Resource describing the I/O space
3340 * @phys_addr: physical address of range to be mapped
3342 * Remap the memory mapped I/O space described by the @res
3343 * and the CPU physical address @phys_addr into virtual address space.
3344 * Only architectures that have memory mapped IO functions defined
3345 * (and the PCI_IOBASE value defined) should call this function.
3347 int __weak pci_remap_iospace(const struct resource *res, phys_addr_t phys_addr)
3349 #if defined(PCI_IOBASE) && defined(CONFIG_MMU)
3350 unsigned long vaddr = (unsigned long)PCI_IOBASE + res->start;
3352 if (!(res->flags & IORESOURCE_IO))
3355 if (res->end > IO_SPACE_LIMIT)
3358 return ioremap_page_range(vaddr, vaddr + resource_size(res), phys_addr,
3359 pgprot_device(PAGE_KERNEL));
3361 /* this architecture does not have memory mapped I/O space,
3362 so this function should never be called */
3363 WARN_ONCE(1, "This architecture does not support memory mapped I/O\n");
3369 * pci_unmap_iospace - Unmap the memory mapped I/O space
3370 * @res: resource to be unmapped
3372 * Unmap the CPU virtual address @res from virtual address space.
3373 * Only architectures that have memory mapped IO functions defined
3374 * (and the PCI_IOBASE value defined) should call this function.
3376 void pci_unmap_iospace(struct resource *res)
3378 #if defined(PCI_IOBASE) && defined(CONFIG_MMU)
3379 unsigned long vaddr = (unsigned long)PCI_IOBASE + res->start;
3381 unmap_kernel_range(vaddr, resource_size(res));
3385 static void __pci_set_master(struct pci_dev *dev, bool enable)
3389 pci_read_config_word(dev, PCI_COMMAND, &old_cmd);
3391 cmd = old_cmd | PCI_COMMAND_MASTER;
3393 cmd = old_cmd & ~PCI_COMMAND_MASTER;
3394 if (cmd != old_cmd) {
3395 dev_dbg(&dev->dev, "%s bus mastering\n",
3396 enable ? "enabling" : "disabling");
3397 pci_write_config_word(dev, PCI_COMMAND, cmd);
3399 dev->is_busmaster = enable;
3403 * pcibios_setup - process "pci=" kernel boot arguments
3404 * @str: string used to pass in "pci=" kernel boot arguments
3406 * Process kernel boot arguments. This is the default implementation.
3407 * Architecture specific implementations can override this as necessary.
3409 char * __weak __init pcibios_setup(char *str)
3415 * pcibios_set_master - enable PCI bus-mastering for device dev
3416 * @dev: the PCI device to enable
3418 * Enables PCI bus-mastering for the device. This is the default
3419 * implementation. Architecture specific implementations can override
3420 * this if necessary.
3422 void __weak pcibios_set_master(struct pci_dev *dev)
3426 /* The latency timer doesn't apply to PCIe (either Type 0 or Type 1) */
3427 if (pci_is_pcie(dev))
3430 pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat);
3432 lat = (64 <= pcibios_max_latency) ? 64 : pcibios_max_latency;
3433 else if (lat > pcibios_max_latency)
3434 lat = pcibios_max_latency;
3438 pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat);
3442 * pci_set_master - enables bus-mastering for device dev
3443 * @dev: the PCI device to enable
3445 * Enables bus-mastering on the device and calls pcibios_set_master()
3446 * to do the needed arch specific settings.
3448 void pci_set_master(struct pci_dev *dev)
3450 __pci_set_master(dev, true);
3451 pcibios_set_master(dev);
3453 EXPORT_SYMBOL(pci_set_master);
3456 * pci_clear_master - disables bus-mastering for device dev
3457 * @dev: the PCI device to disable
3459 void pci_clear_master(struct pci_dev *dev)
3461 __pci_set_master(dev, false);
3463 EXPORT_SYMBOL(pci_clear_master);
3466 * pci_set_cacheline_size - ensure the CACHE_LINE_SIZE register is programmed
3467 * @dev: the PCI device for which MWI is to be enabled
3469 * Helper function for pci_set_mwi.
3470 * Originally copied from drivers/net/acenic.c.
3471 * Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>.
3473 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
3475 int pci_set_cacheline_size(struct pci_dev *dev)
3479 if (!pci_cache_line_size)
3482 /* Validate current setting: the PCI_CACHE_LINE_SIZE must be
3483 equal to or multiple of the right value. */
3484 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
3485 if (cacheline_size >= pci_cache_line_size &&
3486 (cacheline_size % pci_cache_line_size) == 0)
3489 /* Write the correct value. */
3490 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, pci_cache_line_size);
3492 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
3493 if (cacheline_size == pci_cache_line_size)
3496 dev_printk(KERN_DEBUG, &dev->dev, "cache line size of %d is not supported\n",
3497 pci_cache_line_size << 2);
3501 EXPORT_SYMBOL_GPL(pci_set_cacheline_size);
3504 * pci_set_mwi - enables memory-write-invalidate PCI transaction
3505 * @dev: the PCI device for which MWI is enabled
3507 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
3509 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
3511 int pci_set_mwi(struct pci_dev *dev)
3513 #ifdef PCI_DISABLE_MWI
3519 rc = pci_set_cacheline_size(dev);
3523 pci_read_config_word(dev, PCI_COMMAND, &cmd);
3524 if (!(cmd & PCI_COMMAND_INVALIDATE)) {
3525 dev_dbg(&dev->dev, "enabling Mem-Wr-Inval\n");
3526 cmd |= PCI_COMMAND_INVALIDATE;
3527 pci_write_config_word(dev, PCI_COMMAND, cmd);
3532 EXPORT_SYMBOL(pci_set_mwi);
3535 * pci_try_set_mwi - enables memory-write-invalidate PCI transaction
3536 * @dev: the PCI device for which MWI is enabled
3538 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
3539 * Callers are not required to check the return value.
3541 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
3543 int pci_try_set_mwi(struct pci_dev *dev)
3545 #ifdef PCI_DISABLE_MWI
3548 return pci_set_mwi(dev);
3551 EXPORT_SYMBOL(pci_try_set_mwi);
3554 * pci_clear_mwi - disables Memory-Write-Invalidate for device dev
3555 * @dev: the PCI device to disable
3557 * Disables PCI Memory-Write-Invalidate transaction on the device
3559 void pci_clear_mwi(struct pci_dev *dev)
3561 #ifndef PCI_DISABLE_MWI
3564 pci_read_config_word(dev, PCI_COMMAND, &cmd);
3565 if (cmd & PCI_COMMAND_INVALIDATE) {
3566 cmd &= ~PCI_COMMAND_INVALIDATE;
3567 pci_write_config_word(dev, PCI_COMMAND, cmd);
3571 EXPORT_SYMBOL(pci_clear_mwi);
3574 * pci_intx - enables/disables PCI INTx for device dev
3575 * @pdev: the PCI device to operate on
3576 * @enable: boolean: whether to enable or disable PCI INTx
3578 * Enables/disables PCI INTx for device dev
3580 void pci_intx(struct pci_dev *pdev, int enable)
3582 u16 pci_command, new;
3584 pci_read_config_word(pdev, PCI_COMMAND, &pci_command);
3587 new = pci_command & ~PCI_COMMAND_INTX_DISABLE;
3589 new = pci_command | PCI_COMMAND_INTX_DISABLE;
3591 if (new != pci_command) {
3592 struct pci_devres *dr;
3594 pci_write_config_word(pdev, PCI_COMMAND, new);
3596 dr = find_pci_dr(pdev);
3597 if (dr && !dr->restore_intx) {
3598 dr->restore_intx = 1;
3599 dr->orig_intx = !enable;
3603 EXPORT_SYMBOL_GPL(pci_intx);
3606 * pci_intx_mask_supported - probe for INTx masking support
3607 * @dev: the PCI device to operate on
3609 * Check if the device dev support INTx masking via the config space
3612 bool pci_intx_mask_supported(struct pci_dev *dev)
3614 bool mask_supported = false;
3617 if (dev->broken_intx_masking)
3620 pci_cfg_access_lock(dev);
3622 pci_read_config_word(dev, PCI_COMMAND, &orig);
3623 pci_write_config_word(dev, PCI_COMMAND,
3624 orig ^ PCI_COMMAND_INTX_DISABLE);
3625 pci_read_config_word(dev, PCI_COMMAND, &new);
3628 * There's no way to protect against hardware bugs or detect them
3629 * reliably, but as long as we know what the value should be, let's
3630 * go ahead and check it.
3632 if ((new ^ orig) & ~PCI_COMMAND_INTX_DISABLE) {
3633 dev_err(&dev->dev, "Command register changed from 0x%x to 0x%x: driver or hardware bug?\n",
3635 } else if ((new ^ orig) & PCI_COMMAND_INTX_DISABLE) {
3636 mask_supported = true;
3637 pci_write_config_word(dev, PCI_COMMAND, orig);
3640 pci_cfg_access_unlock(dev);
3641 return mask_supported;
3643 EXPORT_SYMBOL_GPL(pci_intx_mask_supported);
3645 static bool pci_check_and_set_intx_mask(struct pci_dev *dev, bool mask)
3647 struct pci_bus *bus = dev->bus;
3648 bool mask_updated = true;
3649 u32 cmd_status_dword;
3650 u16 origcmd, newcmd;
3651 unsigned long flags;
3655 * We do a single dword read to retrieve both command and status.
3656 * Document assumptions that make this possible.
3658 BUILD_BUG_ON(PCI_COMMAND % 4);
3659 BUILD_BUG_ON(PCI_COMMAND + 2 != PCI_STATUS);
3661 raw_spin_lock_irqsave(&pci_lock, flags);
3663 bus->ops->read(bus, dev->devfn, PCI_COMMAND, 4, &cmd_status_dword);
3665 irq_pending = (cmd_status_dword >> 16) & PCI_STATUS_INTERRUPT;
3668 * Check interrupt status register to see whether our device
3669 * triggered the interrupt (when masking) or the next IRQ is
3670 * already pending (when unmasking).
3672 if (mask != irq_pending) {
3673 mask_updated = false;
3677 origcmd = cmd_status_dword;
3678 newcmd = origcmd & ~PCI_COMMAND_INTX_DISABLE;
3680 newcmd |= PCI_COMMAND_INTX_DISABLE;
3681 if (newcmd != origcmd)
3682 bus->ops->write(bus, dev->devfn, PCI_COMMAND, 2, newcmd);
3685 raw_spin_unlock_irqrestore(&pci_lock, flags);
3687 return mask_updated;
3691 * pci_check_and_mask_intx - mask INTx on pending interrupt
3692 * @dev: the PCI device to operate on
3694 * Check if the device dev has its INTx line asserted, mask it and
3695 * return true in that case. False is returned if not interrupt was
3698 bool pci_check_and_mask_intx(struct pci_dev *dev)
3700 return pci_check_and_set_intx_mask(dev, true);
3702 EXPORT_SYMBOL_GPL(pci_check_and_mask_intx);
3705 * pci_check_and_unmask_intx - unmask INTx if no interrupt is pending
3706 * @dev: the PCI device to operate on
3708 * Check if the device dev has its INTx line asserted, unmask it if not
3709 * and return true. False is returned and the mask remains active if
3710 * there was still an interrupt pending.
3712 bool pci_check_and_unmask_intx(struct pci_dev *dev)
3714 return pci_check_and_set_intx_mask(dev, false);
3716 EXPORT_SYMBOL_GPL(pci_check_and_unmask_intx);
3719 * pci_wait_for_pending_transaction - waits for pending transaction
3720 * @dev: the PCI device to operate on
3722 * Return 0 if transaction is pending 1 otherwise.
3724 int pci_wait_for_pending_transaction(struct pci_dev *dev)
3726 if (!pci_is_pcie(dev))
3729 return pci_wait_for_pending(dev, pci_pcie_cap(dev) + PCI_EXP_DEVSTA,
3730 PCI_EXP_DEVSTA_TRPND);
3732 EXPORT_SYMBOL(pci_wait_for_pending_transaction);
3735 * We should only need to wait 100ms after FLR, but some devices take longer.
3736 * Wait for up to 1000ms for config space to return something other than -1.
3737 * Intel IGD requires this when an LCD panel is attached. We read the 2nd
3738 * dword because VFs don't implement the 1st dword.
3740 static void pci_flr_wait(struct pci_dev *dev)
3747 pci_read_config_dword(dev, PCI_COMMAND, &id);
3748 } while (i++ < 10 && id == ~0);
3751 dev_warn(&dev->dev, "Failed to return from FLR\n");
3753 dev_info(&dev->dev, "Required additional %dms to return from FLR\n",
3757 static int pcie_flr(struct pci_dev *dev, int probe)
3761 pcie_capability_read_dword(dev, PCI_EXP_DEVCAP, &cap);
3762 if (!(cap & PCI_EXP_DEVCAP_FLR))
3768 if (!pci_wait_for_pending_transaction(dev))
3769 dev_err(&dev->dev, "timed out waiting for pending transaction; performing function level reset anyway\n");
3771 pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_BCR_FLR);
3776 static int pci_af_flr(struct pci_dev *dev, int probe)
3781 pos = pci_find_capability(dev, PCI_CAP_ID_AF);
3785 pci_read_config_byte(dev, pos + PCI_AF_CAP, &cap);
3786 if (!(cap & PCI_AF_CAP_TP) || !(cap & PCI_AF_CAP_FLR))
3793 * Wait for Transaction Pending bit to clear. A word-aligned test
3794 * is used, so we use the conrol offset rather than status and shift
3795 * the test bit to match.
3797 if (!pci_wait_for_pending(dev, pos + PCI_AF_CTRL,
3798 PCI_AF_STATUS_TP << 8))
3799 dev_err(&dev->dev, "timed out waiting for pending transaction; performing AF function level reset anyway\n");
3801 pci_write_config_byte(dev, pos + PCI_AF_CTRL, PCI_AF_CTRL_FLR);
3807 * pci_pm_reset - Put device into PCI_D3 and back into PCI_D0.
3808 * @dev: Device to reset.
3809 * @probe: If set, only check if the device can be reset this way.
3811 * If @dev supports native PCI PM and its PCI_PM_CTRL_NO_SOFT_RESET flag is
3812 * unset, it will be reinitialized internally when going from PCI_D3hot to
3813 * PCI_D0. If that's the case and the device is not in a low-power state
3814 * already, force it into PCI_D3hot and back to PCI_D0, causing it to be reset.
3816 * NOTE: This causes the caller to sleep for twice the device power transition
3817 * cooldown period, which for the D0->D3hot and D3hot->D0 transitions is 10 ms
3818 * by default (i.e. unless the @dev's d3_delay field has a different value).
3819 * Moreover, only devices in D0 can be reset by this function.
3821 static int pci_pm_reset(struct pci_dev *dev, int probe)
3825 if (!dev->pm_cap || dev->dev_flags & PCI_DEV_FLAGS_NO_PM_RESET)
3828 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &csr);
3829 if (csr & PCI_PM_CTRL_NO_SOFT_RESET)
3835 if (dev->current_state != PCI_D0)
3838 csr &= ~PCI_PM_CTRL_STATE_MASK;
3840 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr);
3841 pci_dev_d3_sleep(dev);
3843 csr &= ~PCI_PM_CTRL_STATE_MASK;
3845 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr);
3846 pci_dev_d3_sleep(dev);
3851 void pci_reset_secondary_bus(struct pci_dev *dev)
3855 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &ctrl);
3856 ctrl |= PCI_BRIDGE_CTL_BUS_RESET;
3857 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, ctrl);
3859 * PCI spec v3.0 7.6.4.2 requires minimum Trst of 1ms. Double
3860 * this to 2ms to ensure that we meet the minimum requirement.
3864 ctrl &= ~PCI_BRIDGE_CTL_BUS_RESET;
3865 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, ctrl);
3868 * Trhfa for conventional PCI is 2^25 clock cycles.
3869 * Assuming a minimum 33MHz clock this results in a 1s
3870 * delay before we can consider subordinate devices to
3871 * be re-initialized. PCIe has some ways to shorten this,
3872 * but we don't make use of them yet.
3877 void __weak pcibios_reset_secondary_bus(struct pci_dev *dev)
3879 pci_reset_secondary_bus(dev);
3883 * pci_reset_bridge_secondary_bus - Reset the secondary bus on a PCI bridge.
3884 * @dev: Bridge device
3886 * Use the bridge control register to assert reset on the secondary bus.
3887 * Devices on the secondary bus are left in power-on state.
3889 void pci_reset_bridge_secondary_bus(struct pci_dev *dev)
3891 pcibios_reset_secondary_bus(dev);
3893 EXPORT_SYMBOL_GPL(pci_reset_bridge_secondary_bus);
3895 static int pci_parent_bus_reset(struct pci_dev *dev, int probe)
3897 struct pci_dev *pdev;
3899 if (pci_is_root_bus(dev->bus) || dev->subordinate ||
3900 !dev->bus->self || dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET)
3903 list_for_each_entry(pdev, &dev->bus->devices, bus_list)
3910 pci_reset_bridge_secondary_bus(dev->bus->self);
3915 static int pci_reset_hotplug_slot(struct hotplug_slot *hotplug, int probe)
3919 if (!hotplug || !try_module_get(hotplug->ops->owner))
3922 if (hotplug->ops->reset_slot)
3923 rc = hotplug->ops->reset_slot(hotplug, probe);
3925 module_put(hotplug->ops->owner);
3930 static int pci_dev_reset_slot_function(struct pci_dev *dev, int probe)
3932 struct pci_dev *pdev;
3934 if (dev->subordinate || !dev->slot ||
3935 dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET)
3938 list_for_each_entry(pdev, &dev->bus->devices, bus_list)
3939 if (pdev != dev && pdev->slot == dev->slot)
3942 return pci_reset_hotplug_slot(dev->slot->hotplug, probe);
3945 static int __pci_dev_reset(struct pci_dev *dev, int probe)
3951 rc = pci_dev_specific_reset(dev, probe);
3955 rc = pcie_flr(dev, probe);
3959 rc = pci_af_flr(dev, probe);
3963 rc = pci_pm_reset(dev, probe);
3967 rc = pci_dev_reset_slot_function(dev, probe);
3971 rc = pci_parent_bus_reset(dev, probe);
3976 static void pci_dev_lock(struct pci_dev *dev)
3978 pci_cfg_access_lock(dev);
3979 /* block PM suspend, driver probe, etc. */
3980 device_lock(&dev->dev);
3983 /* Return 1 on successful lock, 0 on contention */
3984 static int pci_dev_trylock(struct pci_dev *dev)
3986 if (pci_cfg_access_trylock(dev)) {
3987 if (device_trylock(&dev->dev))
3989 pci_cfg_access_unlock(dev);
3995 static void pci_dev_unlock(struct pci_dev *dev)
3997 device_unlock(&dev->dev);
3998 pci_cfg_access_unlock(dev);
4002 * pci_reset_notify - notify device driver of reset
4003 * @dev: device to be notified of reset
4004 * @prepare: 'true' if device is about to be reset; 'false' if reset attempt
4007 * Must be called prior to device access being disabled and after device
4008 * access is restored.
4010 static void pci_reset_notify(struct pci_dev *dev, bool prepare)
4012 const struct pci_error_handlers *err_handler =
4013 dev->driver ? dev->driver->err_handler : NULL;
4014 if (err_handler && err_handler->reset_notify)
4015 err_handler->reset_notify(dev, prepare);
4018 static void pci_dev_save_and_disable(struct pci_dev *dev)
4020 pci_reset_notify(dev, true);
4023 * Wake-up device prior to save. PM registers default to D0 after
4024 * reset and a simple register restore doesn't reliably return
4025 * to a non-D0 state anyway.
4027 pci_set_power_state(dev, PCI_D0);
4029 pci_save_state(dev);
4031 * Disable the device by clearing the Command register, except for
4032 * INTx-disable which is set. This not only disables MMIO and I/O port
4033 * BARs, but also prevents the device from being Bus Master, preventing
4034 * DMA from the device including MSI/MSI-X interrupts. For PCI 2.3
4035 * compliant devices, INTx-disable prevents legacy interrupts.
4037 pci_write_config_word(dev, PCI_COMMAND, PCI_COMMAND_INTX_DISABLE);
4040 static void pci_dev_restore(struct pci_dev *dev)
4042 pci_restore_state(dev);
4043 pci_reset_notify(dev, false);
4046 static int pci_dev_reset(struct pci_dev *dev, int probe)
4053 rc = __pci_dev_reset(dev, probe);
4056 pci_dev_unlock(dev);
4062 * __pci_reset_function - reset a PCI device function
4063 * @dev: PCI device to reset
4065 * Some devices allow an individual function to be reset without affecting
4066 * other functions in the same device. The PCI device must be responsive
4067 * to PCI config space in order to use this function.
4069 * The device function is presumed to be unused when this function is called.
4070 * Resetting the device will make the contents of PCI configuration space
4071 * random, so any caller of this must be prepared to reinitialise the
4072 * device including MSI, bus mastering, BARs, decoding IO and memory spaces,
4075 * Returns 0 if the device function was successfully reset or negative if the
4076 * device doesn't support resetting a single function.
4078 int __pci_reset_function(struct pci_dev *dev)
4080 return pci_dev_reset(dev, 0);
4082 EXPORT_SYMBOL_GPL(__pci_reset_function);
4085 * __pci_reset_function_locked - reset a PCI device function while holding
4086 * the @dev mutex lock.
4087 * @dev: PCI device to reset
4089 * Some devices allow an individual function to be reset without affecting
4090 * other functions in the same device. The PCI device must be responsive
4091 * to PCI config space in order to use this function.
4093 * The device function is presumed to be unused and the caller is holding
4094 * the device mutex lock when this function is called.
4095 * Resetting the device will make the contents of PCI configuration space
4096 * random, so any caller of this must be prepared to reinitialise the
4097 * device including MSI, bus mastering, BARs, decoding IO and memory spaces,
4100 * Returns 0 if the device function was successfully reset or negative if the
4101 * device doesn't support resetting a single function.
4103 int __pci_reset_function_locked(struct pci_dev *dev)
4105 return __pci_dev_reset(dev, 0);
4107 EXPORT_SYMBOL_GPL(__pci_reset_function_locked);
4110 * pci_probe_reset_function - check whether the device can be safely reset
4111 * @dev: PCI device to reset
4113 * Some devices allow an individual function to be reset without affecting
4114 * other functions in the same device. The PCI device must be responsive
4115 * to PCI config space in order to use this function.
4117 * Returns 0 if the device function can be reset or negative if the
4118 * device doesn't support resetting a single function.
4120 int pci_probe_reset_function(struct pci_dev *dev)
4122 return pci_dev_reset(dev, 1);
4126 * pci_reset_function - quiesce and reset a PCI device function
4127 * @dev: PCI device to reset
4129 * Some devices allow an individual function to be reset without affecting
4130 * other functions in the same device. The PCI device must be responsive
4131 * to PCI config space in order to use this function.
4133 * This function does not just reset the PCI portion of a device, but
4134 * clears all the state associated with the device. This function differs
4135 * from __pci_reset_function in that it saves and restores device state
4138 * Returns 0 if the device function was successfully reset or negative if the
4139 * device doesn't support resetting a single function.
4141 int pci_reset_function(struct pci_dev *dev)
4145 rc = pci_dev_reset(dev, 1);
4149 pci_dev_save_and_disable(dev);
4151 rc = pci_dev_reset(dev, 0);
4153 pci_dev_restore(dev);
4157 EXPORT_SYMBOL_GPL(pci_reset_function);
4160 * pci_try_reset_function - quiesce and reset a PCI device function
4161 * @dev: PCI device to reset
4163 * Same as above, except return -EAGAIN if unable to lock device.
4165 int pci_try_reset_function(struct pci_dev *dev)
4169 rc = pci_dev_reset(dev, 1);
4173 pci_dev_save_and_disable(dev);
4175 if (pci_dev_trylock(dev)) {
4176 rc = __pci_dev_reset(dev, 0);
4177 pci_dev_unlock(dev);
4181 pci_dev_restore(dev);
4185 EXPORT_SYMBOL_GPL(pci_try_reset_function);
4187 /* Do any devices on or below this bus prevent a bus reset? */
4188 static bool pci_bus_resetable(struct pci_bus *bus)
4190 struct pci_dev *dev;
4192 list_for_each_entry(dev, &bus->devices, bus_list) {
4193 if (dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET ||
4194 (dev->subordinate && !pci_bus_resetable(dev->subordinate)))
4201 /* Lock devices from the top of the tree down */
4202 static void pci_bus_lock(struct pci_bus *bus)
4204 struct pci_dev *dev;
4206 list_for_each_entry(dev, &bus->devices, bus_list) {
4208 if (dev->subordinate)
4209 pci_bus_lock(dev->subordinate);
4213 /* Unlock devices from the bottom of the tree up */
4214 static void pci_bus_unlock(struct pci_bus *bus)
4216 struct pci_dev *dev;
4218 list_for_each_entry(dev, &bus->devices, bus_list) {
4219 if (dev->subordinate)
4220 pci_bus_unlock(dev->subordinate);
4221 pci_dev_unlock(dev);
4225 /* Return 1 on successful lock, 0 on contention */
4226 static int pci_bus_trylock(struct pci_bus *bus)
4228 struct pci_dev *dev;
4230 list_for_each_entry(dev, &bus->devices, bus_list) {
4231 if (!pci_dev_trylock(dev))
4233 if (dev->subordinate) {
4234 if (!pci_bus_trylock(dev->subordinate)) {
4235 pci_dev_unlock(dev);
4243 list_for_each_entry_continue_reverse(dev, &bus->devices, bus_list) {
4244 if (dev->subordinate)
4245 pci_bus_unlock(dev->subordinate);
4246 pci_dev_unlock(dev);
4251 /* Do any devices on or below this slot prevent a bus reset? */
4252 static bool pci_slot_resetable(struct pci_slot *slot)
4254 struct pci_dev *dev;
4256 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
4257 if (!dev->slot || dev->slot != slot)
4259 if (dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET ||
4260 (dev->subordinate && !pci_bus_resetable(dev->subordinate)))
4267 /* Lock devices from the top of the tree down */
4268 static void pci_slot_lock(struct pci_slot *slot)
4270 struct pci_dev *dev;
4272 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
4273 if (!dev->slot || dev->slot != slot)
4276 if (dev->subordinate)
4277 pci_bus_lock(dev->subordinate);
4281 /* Unlock devices from the bottom of the tree up */
4282 static void pci_slot_unlock(struct pci_slot *slot)
4284 struct pci_dev *dev;
4286 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
4287 if (!dev->slot || dev->slot != slot)
4289 if (dev->subordinate)
4290 pci_bus_unlock(dev->subordinate);
4291 pci_dev_unlock(dev);
4295 /* Return 1 on successful lock, 0 on contention */
4296 static int pci_slot_trylock(struct pci_slot *slot)
4298 struct pci_dev *dev;
4300 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
4301 if (!dev->slot || dev->slot != slot)
4303 if (!pci_dev_trylock(dev))
4305 if (dev->subordinate) {
4306 if (!pci_bus_trylock(dev->subordinate)) {
4307 pci_dev_unlock(dev);
4315 list_for_each_entry_continue_reverse(dev,
4316 &slot->bus->devices, bus_list) {
4317 if (!dev->slot || dev->slot != slot)
4319 if (dev->subordinate)
4320 pci_bus_unlock(dev->subordinate);
4321 pci_dev_unlock(dev);
4326 /* Save and disable devices from the top of the tree down */
4327 static void pci_bus_save_and_disable(struct pci_bus *bus)
4329 struct pci_dev *dev;
4331 list_for_each_entry(dev, &bus->devices, bus_list) {
4332 pci_dev_save_and_disable(dev);
4333 if (dev->subordinate)
4334 pci_bus_save_and_disable(dev->subordinate);
4339 * Restore devices from top of the tree down - parent bridges need to be
4340 * restored before we can get to subordinate devices.
4342 static void pci_bus_restore(struct pci_bus *bus)
4344 struct pci_dev *dev;
4346 list_for_each_entry(dev, &bus->devices, bus_list) {
4347 pci_dev_restore(dev);
4348 if (dev->subordinate)
4349 pci_bus_restore(dev->subordinate);
4353 /* Save and disable devices from the top of the tree down */
4354 static void pci_slot_save_and_disable(struct pci_slot *slot)
4356 struct pci_dev *dev;
4358 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
4359 if (!dev->slot || dev->slot != slot)
4361 pci_dev_save_and_disable(dev);
4362 if (dev->subordinate)
4363 pci_bus_save_and_disable(dev->subordinate);
4368 * Restore devices from top of the tree down - parent bridges need to be
4369 * restored before we can get to subordinate devices.
4371 static void pci_slot_restore(struct pci_slot *slot)
4373 struct pci_dev *dev;
4375 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
4376 if (!dev->slot || dev->slot != slot)
4378 pci_dev_restore(dev);
4379 if (dev->subordinate)
4380 pci_bus_restore(dev->subordinate);
4384 static int pci_slot_reset(struct pci_slot *slot, int probe)
4388 if (!slot || !pci_slot_resetable(slot))
4392 pci_slot_lock(slot);
4396 rc = pci_reset_hotplug_slot(slot->hotplug, probe);
4399 pci_slot_unlock(slot);
4405 * pci_probe_reset_slot - probe whether a PCI slot can be reset
4406 * @slot: PCI slot to probe
4408 * Return 0 if slot can be reset, negative if a slot reset is not supported.
4410 int pci_probe_reset_slot(struct pci_slot *slot)
4412 return pci_slot_reset(slot, 1);
4414 EXPORT_SYMBOL_GPL(pci_probe_reset_slot);
4417 * pci_reset_slot - reset a PCI slot
4418 * @slot: PCI slot to reset
4420 * A PCI bus may host multiple slots, each slot may support a reset mechanism
4421 * independent of other slots. For instance, some slots may support slot power
4422 * control. In the case of a 1:1 bus to slot architecture, this function may
4423 * wrap the bus reset to avoid spurious slot related events such as hotplug.
4424 * Generally a slot reset should be attempted before a bus reset. All of the
4425 * function of the slot and any subordinate buses behind the slot are reset
4426 * through this function. PCI config space of all devices in the slot and
4427 * behind the slot is saved before and restored after reset.
4429 * Return 0 on success, non-zero on error.
4431 int pci_reset_slot(struct pci_slot *slot)
4435 rc = pci_slot_reset(slot, 1);
4439 pci_slot_save_and_disable(slot);
4441 rc = pci_slot_reset(slot, 0);
4443 pci_slot_restore(slot);
4447 EXPORT_SYMBOL_GPL(pci_reset_slot);
4450 * pci_try_reset_slot - Try to reset a PCI slot
4451 * @slot: PCI slot to reset
4453 * Same as above except return -EAGAIN if the slot cannot be locked
4455 int pci_try_reset_slot(struct pci_slot *slot)
4459 rc = pci_slot_reset(slot, 1);
4463 pci_slot_save_and_disable(slot);
4465 if (pci_slot_trylock(slot)) {
4467 rc = pci_reset_hotplug_slot(slot->hotplug, 0);
4468 pci_slot_unlock(slot);
4472 pci_slot_restore(slot);
4476 EXPORT_SYMBOL_GPL(pci_try_reset_slot);
4478 static int pci_bus_reset(struct pci_bus *bus, int probe)
4480 if (!bus->self || !pci_bus_resetable(bus))
4490 pci_reset_bridge_secondary_bus(bus->self);
4492 pci_bus_unlock(bus);
4498 * pci_probe_reset_bus - probe whether a PCI bus can be reset
4499 * @bus: PCI bus to probe
4501 * Return 0 if bus can be reset, negative if a bus reset is not supported.
4503 int pci_probe_reset_bus(struct pci_bus *bus)
4505 return pci_bus_reset(bus, 1);
4507 EXPORT_SYMBOL_GPL(pci_probe_reset_bus);
4510 * pci_reset_bus - reset a PCI bus
4511 * @bus: top level PCI bus to reset
4513 * Do a bus reset on the given bus and any subordinate buses, saving
4514 * and restoring state of all devices.
4516 * Return 0 on success, non-zero on error.
4518 int pci_reset_bus(struct pci_bus *bus)
4522 rc = pci_bus_reset(bus, 1);
4526 pci_bus_save_and_disable(bus);
4528 rc = pci_bus_reset(bus, 0);
4530 pci_bus_restore(bus);
4534 EXPORT_SYMBOL_GPL(pci_reset_bus);
4537 * pci_try_reset_bus - Try to reset a PCI bus
4538 * @bus: top level PCI bus to reset
4540 * Same as above except return -EAGAIN if the bus cannot be locked
4542 int pci_try_reset_bus(struct pci_bus *bus)
4546 rc = pci_bus_reset(bus, 1);
4550 pci_bus_save_and_disable(bus);
4552 if (pci_bus_trylock(bus)) {
4554 pci_reset_bridge_secondary_bus(bus->self);
4555 pci_bus_unlock(bus);
4559 pci_bus_restore(bus);
4563 EXPORT_SYMBOL_GPL(pci_try_reset_bus);
4566 * pcix_get_max_mmrbc - get PCI-X maximum designed memory read byte count
4567 * @dev: PCI device to query
4569 * Returns mmrbc: maximum designed memory read count in bytes
4570 * or appropriate error value.
4572 int pcix_get_max_mmrbc(struct pci_dev *dev)
4577 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
4581 if (pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat))
4584 return 512 << ((stat & PCI_X_STATUS_MAX_READ) >> 21);
4586 EXPORT_SYMBOL(pcix_get_max_mmrbc);
4589 * pcix_get_mmrbc - get PCI-X maximum memory read byte count
4590 * @dev: PCI device to query
4592 * Returns mmrbc: maximum memory read count in bytes
4593 * or appropriate error value.
4595 int pcix_get_mmrbc(struct pci_dev *dev)
4600 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
4604 if (pci_read_config_word(dev, cap + PCI_X_CMD, &cmd))
4607 return 512 << ((cmd & PCI_X_CMD_MAX_READ) >> 2);
4609 EXPORT_SYMBOL(pcix_get_mmrbc);
4612 * pcix_set_mmrbc - set PCI-X maximum memory read byte count
4613 * @dev: PCI device to query
4614 * @mmrbc: maximum memory read count in bytes
4615 * valid values are 512, 1024, 2048, 4096
4617 * If possible sets maximum memory read byte count, some bridges have erratas
4618 * that prevent this.
4620 int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc)
4626 if (mmrbc < 512 || mmrbc > 4096 || !is_power_of_2(mmrbc))
4629 v = ffs(mmrbc) - 10;
4631 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
4635 if (pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat))
4638 if (v > (stat & PCI_X_STATUS_MAX_READ) >> 21)
4641 if (pci_read_config_word(dev, cap + PCI_X_CMD, &cmd))
4644 o = (cmd & PCI_X_CMD_MAX_READ) >> 2;
4646 if (v > o && (dev->bus->bus_flags & PCI_BUS_FLAGS_NO_MMRBC))
4649 cmd &= ~PCI_X_CMD_MAX_READ;
4651 if (pci_write_config_word(dev, cap + PCI_X_CMD, cmd))
4656 EXPORT_SYMBOL(pcix_set_mmrbc);
4659 * pcie_get_readrq - get PCI Express read request size
4660 * @dev: PCI device to query
4662 * Returns maximum memory read request in bytes
4663 * or appropriate error value.
4665 int pcie_get_readrq(struct pci_dev *dev)
4669 pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl);
4671 return 128 << ((ctl & PCI_EXP_DEVCTL_READRQ) >> 12);
4673 EXPORT_SYMBOL(pcie_get_readrq);
4676 * pcie_set_readrq - set PCI Express maximum memory read request
4677 * @dev: PCI device to query
4678 * @rq: maximum memory read count in bytes
4679 * valid values are 128, 256, 512, 1024, 2048, 4096
4681 * If possible sets maximum memory read request in bytes
4683 int pcie_set_readrq(struct pci_dev *dev, int rq)
4687 if (rq < 128 || rq > 4096 || !is_power_of_2(rq))
4691 * If using the "performance" PCIe config, we clamp the
4692 * read rq size to the max packet size to prevent the
4693 * host bridge generating requests larger than we can
4696 if (pcie_bus_config == PCIE_BUS_PERFORMANCE) {
4697 int mps = pcie_get_mps(dev);
4703 v = (ffs(rq) - 8) << 12;
4705 return pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL,
4706 PCI_EXP_DEVCTL_READRQ, v);
4708 EXPORT_SYMBOL(pcie_set_readrq);
4711 * pcie_get_mps - get PCI Express maximum payload size
4712 * @dev: PCI device to query
4714 * Returns maximum payload size in bytes
4716 int pcie_get_mps(struct pci_dev *dev)
4720 pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl);
4722 return 128 << ((ctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5);
4724 EXPORT_SYMBOL(pcie_get_mps);
4727 * pcie_set_mps - set PCI Express maximum payload size
4728 * @dev: PCI device to query
4729 * @mps: maximum payload size in bytes
4730 * valid values are 128, 256, 512, 1024, 2048, 4096
4732 * If possible sets maximum payload size
4734 int pcie_set_mps(struct pci_dev *dev, int mps)
4738 if (mps < 128 || mps > 4096 || !is_power_of_2(mps))
4742 if (v > dev->pcie_mpss)
4746 return pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL,
4747 PCI_EXP_DEVCTL_PAYLOAD, v);
4749 EXPORT_SYMBOL(pcie_set_mps);
4752 * pcie_get_minimum_link - determine minimum link settings of a PCI device
4753 * @dev: PCI device to query
4754 * @speed: storage for minimum speed
4755 * @width: storage for minimum width
4757 * This function will walk up the PCI device chain and determine the minimum
4758 * link width and speed of the device.
4760 int pcie_get_minimum_link(struct pci_dev *dev, enum pci_bus_speed *speed,
4761 enum pcie_link_width *width)
4765 *speed = PCI_SPEED_UNKNOWN;
4766 *width = PCIE_LNK_WIDTH_UNKNOWN;
4770 enum pci_bus_speed next_speed;
4771 enum pcie_link_width next_width;
4773 ret = pcie_capability_read_word(dev, PCI_EXP_LNKSTA, &lnksta);
4777 next_speed = pcie_link_speed[lnksta & PCI_EXP_LNKSTA_CLS];
4778 next_width = (lnksta & PCI_EXP_LNKSTA_NLW) >>
4779 PCI_EXP_LNKSTA_NLW_SHIFT;
4781 if (next_speed < *speed)
4782 *speed = next_speed;
4784 if (next_width < *width)
4785 *width = next_width;
4787 dev = dev->bus->self;
4792 EXPORT_SYMBOL(pcie_get_minimum_link);
4795 * pci_select_bars - Make BAR mask from the type of resource
4796 * @dev: the PCI device for which BAR mask is made
4797 * @flags: resource type mask to be selected
4799 * This helper routine makes bar mask from the type of resource.
4801 int pci_select_bars(struct pci_dev *dev, unsigned long flags)
4804 for (i = 0; i < PCI_NUM_RESOURCES; i++)
4805 if (pci_resource_flags(dev, i) & flags)
4809 EXPORT_SYMBOL(pci_select_bars);
4812 * pci_resource_bar - get position of the BAR associated with a resource
4813 * @dev: the PCI device
4814 * @resno: the resource number
4815 * @type: the BAR type to be filled in
4817 * Returns BAR position in config space, or 0 if the BAR is invalid.
4819 int pci_resource_bar(struct pci_dev *dev, int resno, enum pci_bar_type *type)
4823 if (resno < PCI_ROM_RESOURCE) {
4824 *type = pci_bar_unknown;
4825 return PCI_BASE_ADDRESS_0 + 4 * resno;
4826 } else if (resno == PCI_ROM_RESOURCE) {
4827 *type = pci_bar_mem32;
4828 return dev->rom_base_reg;
4829 } else if (resno < PCI_BRIDGE_RESOURCES) {
4830 /* device specific resource */
4831 *type = pci_bar_unknown;
4832 reg = pci_iov_resource_bar(dev, resno);
4837 dev_err(&dev->dev, "BAR %d: invalid resource\n", resno);
4841 /* Some architectures require additional programming to enable VGA */
4842 static arch_set_vga_state_t arch_set_vga_state;
4844 void __init pci_register_set_vga_state(arch_set_vga_state_t func)
4846 arch_set_vga_state = func; /* NULL disables */
4849 static int pci_set_vga_state_arch(struct pci_dev *dev, bool decode,
4850 unsigned int command_bits, u32 flags)
4852 if (arch_set_vga_state)
4853 return arch_set_vga_state(dev, decode, command_bits,
4859 * pci_set_vga_state - set VGA decode state on device and parents if requested
4860 * @dev: the PCI device
4861 * @decode: true = enable decoding, false = disable decoding
4862 * @command_bits: PCI_COMMAND_IO and/or PCI_COMMAND_MEMORY
4863 * @flags: traverse ancestors and change bridges
4864 * CHANGE_BRIDGE_ONLY / CHANGE_BRIDGE
4866 int pci_set_vga_state(struct pci_dev *dev, bool decode,
4867 unsigned int command_bits, u32 flags)
4869 struct pci_bus *bus;
4870 struct pci_dev *bridge;
4874 WARN_ON((flags & PCI_VGA_STATE_CHANGE_DECODES) && (command_bits & ~(PCI_COMMAND_IO|PCI_COMMAND_MEMORY)));
4876 /* ARCH specific VGA enables */
4877 rc = pci_set_vga_state_arch(dev, decode, command_bits, flags);
4881 if (flags & PCI_VGA_STATE_CHANGE_DECODES) {
4882 pci_read_config_word(dev, PCI_COMMAND, &cmd);
4884 cmd |= command_bits;
4886 cmd &= ~command_bits;
4887 pci_write_config_word(dev, PCI_COMMAND, cmd);
4890 if (!(flags & PCI_VGA_STATE_CHANGE_BRIDGE))
4897 pci_read_config_word(bridge, PCI_BRIDGE_CONTROL,
4900 cmd |= PCI_BRIDGE_CTL_VGA;
4902 cmd &= ~PCI_BRIDGE_CTL_VGA;
4903 pci_write_config_word(bridge, PCI_BRIDGE_CONTROL,
4912 * pci_add_dma_alias - Add a DMA devfn alias for a device
4913 * @dev: the PCI device for which alias is added
4914 * @devfn: alias slot and function
4916 * This helper encodes 8-bit devfn as bit number in dma_alias_mask.
4917 * It should be called early, preferably as PCI fixup header quirk.
4919 void pci_add_dma_alias(struct pci_dev *dev, u8 devfn)
4921 if (!dev->dma_alias_mask)
4922 dev->dma_alias_mask = kcalloc(BITS_TO_LONGS(U8_MAX),
4923 sizeof(long), GFP_KERNEL);
4924 if (!dev->dma_alias_mask) {
4925 dev_warn(&dev->dev, "Unable to allocate DMA alias mask\n");
4929 set_bit(devfn, dev->dma_alias_mask);
4930 dev_info(&dev->dev, "Enabling fixed DMA alias to %02x.%d\n",
4931 PCI_SLOT(devfn), PCI_FUNC(devfn));
4934 bool pci_devs_are_dma_aliases(struct pci_dev *dev1, struct pci_dev *dev2)
4936 return (dev1->dma_alias_mask &&
4937 test_bit(dev2->devfn, dev1->dma_alias_mask)) ||
4938 (dev2->dma_alias_mask &&
4939 test_bit(dev1->devfn, dev2->dma_alias_mask));
4942 bool pci_device_is_present(struct pci_dev *pdev)
4946 return pci_bus_read_dev_vendor_id(pdev->bus, pdev->devfn, &v, 0);
4948 EXPORT_SYMBOL_GPL(pci_device_is_present);
4950 void pci_ignore_hotplug(struct pci_dev *dev)
4952 struct pci_dev *bridge = dev->bus->self;
4954 dev->ignore_hotplug = 1;
4955 /* Propagate the "ignore hotplug" setting to the parent bridge. */
4957 bridge->ignore_hotplug = 1;
4959 EXPORT_SYMBOL_GPL(pci_ignore_hotplug);
4961 #define RESOURCE_ALIGNMENT_PARAM_SIZE COMMAND_LINE_SIZE
4962 static char resource_alignment_param[RESOURCE_ALIGNMENT_PARAM_SIZE] = {0};
4963 static DEFINE_SPINLOCK(resource_alignment_lock);
4966 * pci_specified_resource_alignment - get resource alignment specified by user.
4967 * @dev: the PCI device to get
4969 * RETURNS: Resource alignment if it is specified.
4970 * Zero if it is not specified.
4972 static resource_size_t pci_specified_resource_alignment(struct pci_dev *dev)
4974 int seg, bus, slot, func, align_order, count;
4975 unsigned short vendor, device, subsystem_vendor, subsystem_device;
4976 resource_size_t align = 0;
4979 spin_lock(&resource_alignment_lock);
4980 p = resource_alignment_param;
4983 if (sscanf(p, "%d%n", &align_order, &count) == 1 &&
4989 if (strncmp(p, "pci:", 4) == 0) {
4990 /* PCI vendor/device (subvendor/subdevice) ids are specified */
4992 if (sscanf(p, "%hx:%hx:%hx:%hx%n",
4993 &vendor, &device, &subsystem_vendor, &subsystem_device, &count) != 4) {
4994 if (sscanf(p, "%hx:%hx%n", &vendor, &device, &count) != 2) {
4995 printk(KERN_ERR "PCI: Can't parse resource_alignment parameter: pci:%s\n",
4999 subsystem_vendor = subsystem_device = 0;
5002 if ((!vendor || (vendor == dev->vendor)) &&
5003 (!device || (device == dev->device)) &&
5004 (!subsystem_vendor || (subsystem_vendor == dev->subsystem_vendor)) &&
5005 (!subsystem_device || (subsystem_device == dev->subsystem_device))) {
5006 if (align_order == -1)
5009 align = 1 << align_order;
5015 if (sscanf(p, "%x:%x:%x.%x%n",
5016 &seg, &bus, &slot, &func, &count) != 4) {
5018 if (sscanf(p, "%x:%x.%x%n",
5019 &bus, &slot, &func, &count) != 3) {
5020 /* Invalid format */
5021 printk(KERN_ERR "PCI: Can't parse resource_alignment parameter: %s\n",
5027 if (seg == pci_domain_nr(dev->bus) &&
5028 bus == dev->bus->number &&
5029 slot == PCI_SLOT(dev->devfn) &&
5030 func == PCI_FUNC(dev->devfn)) {
5031 if (align_order == -1)
5034 align = 1 << align_order;
5039 if (*p != ';' && *p != ',') {
5040 /* End of param or invalid format */
5045 spin_unlock(&resource_alignment_lock);
5050 * This function disables memory decoding and releases memory resources
5051 * of the device specified by kernel's boot parameter 'pci=resource_alignment='.
5052 * It also rounds up size to specified alignment.
5053 * Later on, the kernel will assign page-aligned memory resource back
5056 void pci_reassigndev_resource_alignment(struct pci_dev *dev)
5060 resource_size_t align, size;
5063 /* check if specified PCI is target device to reassign */
5064 align = pci_specified_resource_alignment(dev);
5068 if (dev->hdr_type == PCI_HEADER_TYPE_NORMAL &&
5069 (dev->class >> 8) == PCI_CLASS_BRIDGE_HOST) {
5071 "Can't reassign resources to host bridge.\n");
5076 "Disabling memory decoding and releasing memory resources.\n");
5077 pci_read_config_word(dev, PCI_COMMAND, &command);
5078 command &= ~PCI_COMMAND_MEMORY;
5079 pci_write_config_word(dev, PCI_COMMAND, command);
5081 for (i = 0; i < PCI_BRIDGE_RESOURCES; i++) {
5082 r = &dev->resource[i];
5083 if (!(r->flags & IORESOURCE_MEM))
5085 size = resource_size(r);
5089 "Rounding up size of resource #%d to %#llx.\n",
5090 i, (unsigned long long)size);
5092 r->flags |= IORESOURCE_UNSET;
5096 /* Need to disable bridge's resource window,
5097 * to enable the kernel to reassign new resource
5100 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE &&
5101 (dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
5102 for (i = PCI_BRIDGE_RESOURCES; i < PCI_NUM_RESOURCES; i++) {
5103 r = &dev->resource[i];
5104 if (!(r->flags & IORESOURCE_MEM))
5106 r->flags |= IORESOURCE_UNSET;
5107 r->end = resource_size(r) - 1;
5110 pci_disable_bridge_window(dev);
5114 static ssize_t pci_set_resource_alignment_param(const char *buf, size_t count)
5116 if (count > RESOURCE_ALIGNMENT_PARAM_SIZE - 1)
5117 count = RESOURCE_ALIGNMENT_PARAM_SIZE - 1;
5118 spin_lock(&resource_alignment_lock);
5119 strncpy(resource_alignment_param, buf, count);
5120 resource_alignment_param[count] = '\0';
5121 spin_unlock(&resource_alignment_lock);
5125 static ssize_t pci_get_resource_alignment_param(char *buf, size_t size)
5128 spin_lock(&resource_alignment_lock);
5129 count = snprintf(buf, size, "%s", resource_alignment_param);
5130 spin_unlock(&resource_alignment_lock);
5134 static ssize_t pci_resource_alignment_show(struct bus_type *bus, char *buf)
5136 return pci_get_resource_alignment_param(buf, PAGE_SIZE);
5139 static ssize_t pci_resource_alignment_store(struct bus_type *bus,
5140 const char *buf, size_t count)
5142 return pci_set_resource_alignment_param(buf, count);
5145 static BUS_ATTR(resource_alignment, 0644, pci_resource_alignment_show,
5146 pci_resource_alignment_store);
5148 static int __init pci_resource_alignment_sysfs_init(void)
5150 return bus_create_file(&pci_bus_type,
5151 &bus_attr_resource_alignment);
5153 late_initcall(pci_resource_alignment_sysfs_init);
5155 static void pci_no_domains(void)
5157 #ifdef CONFIG_PCI_DOMAINS
5158 pci_domains_supported = 0;
5162 #ifdef CONFIG_PCI_DOMAINS
5163 static atomic_t __domain_nr = ATOMIC_INIT(-1);
5165 int pci_get_new_domain_nr(void)
5167 return atomic_inc_return(&__domain_nr);
5170 #ifdef CONFIG_PCI_DOMAINS_GENERIC
5171 static int of_pci_bus_find_domain_nr(struct device *parent)
5173 static int use_dt_domains = -1;
5177 domain = of_get_pci_domain_nr(parent->of_node);
5179 * Check DT domain and use_dt_domains values.
5181 * If DT domain property is valid (domain >= 0) and
5182 * use_dt_domains != 0, the DT assignment is valid since this means
5183 * we have not previously allocated a domain number by using
5184 * pci_get_new_domain_nr(); we should also update use_dt_domains to
5185 * 1, to indicate that we have just assigned a domain number from
5188 * If DT domain property value is not valid (ie domain < 0), and we
5189 * have not previously assigned a domain number from DT
5190 * (use_dt_domains != 1) we should assign a domain number by
5193 * pci_get_new_domain_nr()
5195 * API and update the use_dt_domains value to keep track of method we
5196 * are using to assign domain numbers (use_dt_domains = 0).
5198 * All other combinations imply we have a platform that is trying
5199 * to mix domain numbers obtained from DT and pci_get_new_domain_nr(),
5200 * which is a recipe for domain mishandling and it is prevented by
5201 * invalidating the domain value (domain = -1) and printing a
5202 * corresponding error.
5204 if (domain >= 0 && use_dt_domains) {
5206 } else if (domain < 0 && use_dt_domains != 1) {
5208 domain = pci_get_new_domain_nr();
5210 dev_err(parent, "Node %s has inconsistent \"linux,pci-domain\" property in DT\n",
5211 parent->of_node->full_name);
5218 int pci_bus_find_domain_nr(struct pci_bus *bus, struct device *parent)
5220 return acpi_disabled ? of_pci_bus_find_domain_nr(parent) :
5221 acpi_pci_bus_find_domain_nr(bus);
5227 * pci_ext_cfg_avail - can we access extended PCI config space?
5229 * Returns 1 if we can access PCI extended config space (offsets
5230 * greater than 0xff). This is the default implementation. Architecture
5231 * implementations can override this.
5233 int __weak pci_ext_cfg_avail(void)
5238 void __weak pci_fixup_cardbus(struct pci_bus *bus)
5241 EXPORT_SYMBOL(pci_fixup_cardbus);
5243 static int __init pci_setup(char *str)
5246 char *k = strchr(str, ',');
5249 if (*str && (str = pcibios_setup(str)) && *str) {
5250 if (!strcmp(str, "nomsi")) {
5252 } else if (!strcmp(str, "noaer")) {
5254 } else if (!strncmp(str, "realloc=", 8)) {
5255 pci_realloc_get_opt(str + 8);
5256 } else if (!strncmp(str, "realloc", 7)) {
5257 pci_realloc_get_opt("on");
5258 } else if (!strcmp(str, "nodomains")) {
5260 } else if (!strncmp(str, "noari", 5)) {
5261 pcie_ari_disabled = true;
5262 } else if (!strncmp(str, "cbiosize=", 9)) {
5263 pci_cardbus_io_size = memparse(str + 9, &str);
5264 } else if (!strncmp(str, "cbmemsize=", 10)) {
5265 pci_cardbus_mem_size = memparse(str + 10, &str);
5266 } else if (!strncmp(str, "resource_alignment=", 19)) {
5267 pci_set_resource_alignment_param(str + 19,
5269 } else if (!strncmp(str, "ecrc=", 5)) {
5270 pcie_ecrc_get_policy(str + 5);
5271 } else if (!strncmp(str, "hpiosize=", 9)) {
5272 pci_hotplug_io_size = memparse(str + 9, &str);
5273 } else if (!strncmp(str, "hpmemsize=", 10)) {
5274 pci_hotplug_mem_size = memparse(str + 10, &str);
5275 } else if (!strncmp(str, "hpbussize=", 10)) {
5276 pci_hotplug_bus_size =
5277 simple_strtoul(str + 10, &str, 0);
5278 if (pci_hotplug_bus_size > 0xff)
5279 pci_hotplug_bus_size = DEFAULT_HOTPLUG_BUS_SIZE;
5280 } else if (!strncmp(str, "pcie_bus_tune_off", 17)) {
5281 pcie_bus_config = PCIE_BUS_TUNE_OFF;
5282 } else if (!strncmp(str, "pcie_bus_safe", 13)) {
5283 pcie_bus_config = PCIE_BUS_SAFE;
5284 } else if (!strncmp(str, "pcie_bus_perf", 13)) {
5285 pcie_bus_config = PCIE_BUS_PERFORMANCE;
5286 } else if (!strncmp(str, "pcie_bus_peer2peer", 18)) {
5287 pcie_bus_config = PCIE_BUS_PEER2PEER;
5288 } else if (!strncmp(str, "pcie_scan_all", 13)) {
5289 pci_add_flags(PCI_SCAN_ALL_PCIE_DEVS);
5291 printk(KERN_ERR "PCI: Unknown option `%s'\n",
5299 early_param("pci", pci_setup);