drivers/phy/phy-twl4030-usb.c

   1 /*
   2  * twl4030_usb - TWL4030 USB transceiver, talking to OMAP OTG controller
   3  *
   4  * Copyright (C) 2004-2007 Texas Instruments
   5  * Copyright (C) 2008 Nokia Corporation
   6  * Contact: Felipe Balbi <felipe.balbi@nokia.com>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  21  *
  22  * Current status:
  23  *      - HS USB ULPI mode works.
  24  *      - 3-pin mode support may be added in future.
  25  */
  26
  27 #include <linux/module.h>
  28 #include <linux/init.h>
  29 #include <linux/interrupt.h>
  30 #include <linux/platform_device.h>
  31 #include <linux/workqueue.h>
  32 #include <linux/io.h>
  33 #include <linux/delay.h>
  34 #include <linux/usb/otg.h>
  35 #include <linux/phy/phy.h>
  36 #include <linux/pm_runtime.h>
  37 #include <linux/usb/musb.h>
  38 #include <linux/usb/ulpi.h>
  39 #include <linux/i2c/twl.h>
  40 #include <linux/regulator/consumer.h>
  41 #include <linux/err.h>
  42 #include <linux/slab.h>
  43
  44 /* Register defines */
  45
  46 #define MCPC_CTRL                       0x30
  47 #define MCPC_CTRL_RTSOL                 (1 << 7)
  48 #define MCPC_CTRL_EXTSWR                (1 << 6)
  49 #define MCPC_CTRL_EXTSWC                (1 << 5)
  50 #define MCPC_CTRL_VOICESW               (1 << 4)
  51 #define MCPC_CTRL_OUT64K                (1 << 3)
  52 #define MCPC_CTRL_RTSCTSSW              (1 << 2)
  53 #define MCPC_CTRL_HS_UART               (1 << 0)
  54
  55 #define MCPC_IO_CTRL                    0x33
  56 #define MCPC_IO_CTRL_MICBIASEN          (1 << 5)
  57 #define MCPC_IO_CTRL_CTS_NPU            (1 << 4)
  58 #define MCPC_IO_CTRL_RXD_PU             (1 << 3)
  59 #define MCPC_IO_CTRL_TXDTYP             (1 << 2)
  60 #define MCPC_IO_CTRL_CTSTYP             (1 << 1)
  61 #define MCPC_IO_CTRL_RTSTYP             (1 << 0)
  62
  63 #define MCPC_CTRL2                      0x36
  64 #define MCPC_CTRL2_MCPC_CK_EN           (1 << 0)
  65
  66 #define OTHER_FUNC_CTRL                 0x80
  67 #define OTHER_FUNC_CTRL_BDIS_ACON_EN    (1 << 4)
  68 #define OTHER_FUNC_CTRL_FIVEWIRE_MODE   (1 << 2)
  69
  70 #define OTHER_IFC_CTRL                  0x83
  71 #define OTHER_IFC_CTRL_OE_INT_EN        (1 << 6)
  72 #define OTHER_IFC_CTRL_CEA2011_MODE     (1 << 5)
  73 #define OTHER_IFC_CTRL_FSLSSERIALMODE_4PIN      (1 << 4)
  74 #define OTHER_IFC_CTRL_HIZ_ULPI_60MHZ_OUT       (1 << 3)
  75 #define OTHER_IFC_CTRL_HIZ_ULPI         (1 << 2)
  76 #define OTHER_IFC_CTRL_ALT_INT_REROUTE  (1 << 0)
  77
  78 #define OTHER_INT_EN_RISE               0x86
  79 #define OTHER_INT_EN_FALL               0x89
  80 #define OTHER_INT_STS                   0x8C
  81 #define OTHER_INT_LATCH                 0x8D
  82 #define OTHER_INT_VB_SESS_VLD           (1 << 7)
  83 #define OTHER_INT_DM_HI                 (1 << 6) /* not valid for "latch" reg */
  84 #define OTHER_INT_DP_HI                 (1 << 5) /* not valid for "latch" reg */
  85 #define OTHER_INT_BDIS_ACON             (1 << 3) /* not valid for "fall" regs */
  86 #define OTHER_INT_MANU                  (1 << 1)
  87 #define OTHER_INT_ABNORMAL_STRESS       (1 << 0)
  88
  89 #define ID_STATUS                       0x96
  90 #define ID_RES_FLOAT                    (1 << 4)
  91 #define ID_RES_440K                     (1 << 3)
  92 #define ID_RES_200K                     (1 << 2)
  93 #define ID_RES_102K                     (1 << 1)
  94 #define ID_RES_GND                      (1 << 0)
  95
  96 #define POWER_CTRL                      0xAC
  97 #define POWER_CTRL_OTG_ENAB             (1 << 5)
  98
  99 #define OTHER_IFC_CTRL2                 0xAF
 100 #define OTHER_IFC_CTRL2_ULPI_STP_LOW    (1 << 4)
 101 #define OTHER_IFC_CTRL2_ULPI_TXEN_POL   (1 << 3)
 102 #define OTHER_IFC_CTRL2_ULPI_4PIN_2430  (1 << 2)
 103 #define OTHER_IFC_CTRL2_USB_INT_OUTSEL_MASK     (3 << 0) /* bits 0 and 1 */
 104 #define OTHER_IFC_CTRL2_USB_INT_OUTSEL_INT1N    (0 << 0)
 105 #define OTHER_IFC_CTRL2_USB_INT_OUTSEL_INT2N    (1 << 0)
 106
 107 #define REG_CTRL_EN                     0xB2
 108 #define REG_CTRL_ERROR                  0xB5
 109 #define ULPI_I2C_CONFLICT_INTEN         (1 << 0)
 110
 111 #define OTHER_FUNC_CTRL2                0xB8
 112 #define OTHER_FUNC_CTRL2_VBAT_TIMER_EN  (1 << 0)
 113
 114 /* following registers do not have separate _clr and _set registers */
 115 #define VBUS_DEBOUNCE                   0xC0
 116 #define ID_DEBOUNCE                     0xC1
 117 #define VBAT_TIMER                      0xD3
 118 #define PHY_PWR_CTRL                    0xFD
 119 #define PHY_PWR_PHYPWD                  (1 << 0)
 120 #define PHY_CLK_CTRL                    0xFE
 121 #define PHY_CLK_CTRL_CLOCKGATING_EN     (1 << 2)
 122 #define PHY_CLK_CTRL_CLK32K_EN          (1 << 1)
 123 #define REQ_PHY_DPLL_CLK                (1 << 0)
 124 #define PHY_CLK_CTRL_STS                0xFF
 125 #define PHY_DPLL_CLK                    (1 << 0)
 126
 127 /* In module TWL_MODULE_PM_MASTER */
 128 #define STS_HW_CONDITIONS               0x0F
 129
 130 /* In module TWL_MODULE_PM_RECEIVER */
 131 #define VUSB_DEDICATED1                 0x7D
 132 #define VUSB_DEDICATED2                 0x7E
 133 #define VUSB1V5_DEV_GRP                 0x71
 134 #define VUSB1V5_TYPE                    0x72
 135 #define VUSB1V5_REMAP                   0x73
 136 #define VUSB1V8_DEV_GRP                 0x74
 137 #define VUSB1V8_TYPE                    0x75
 138 #define VUSB1V8_REMAP                   0x76
 139 #define VUSB3V1_DEV_GRP                 0x77
 140 #define VUSB3V1_TYPE                    0x78
 141 #define VUSB3V1_REMAP                   0x79
 142
 143 /* In module TWL4030_MODULE_INTBR */
 144 #define PMBR1                           0x0D
 145 #define GPIO_USB_4PIN_ULPI_2430C        (3 << 0)
 146
 147 /*
 148  * If VBUS is valid or ID is ground, then we know a
 149  * cable is present and we need to be runtime-enabled
 150  */
 151 static inline bool cable_present(enum musb_vbus_id_status stat)
 152 {
 153         return stat == MUSB_VBUS_VALID ||
 154                 stat == MUSB_ID_GROUND;
 155 }
 156
 157 struct twl4030_usb {
 158         struct usb_phy          phy;
 159         struct device           *dev;
 160
 161         /* TWL4030 internal USB regulator supplies */
 162         struct regulator        *usb1v5;
 163         struct regulator        *usb1v8;
 164         struct regulator        *usb3v1;
 165
 166         /* for vbus reporting with irqs disabled */
 167         struct mutex            lock;
 168
 169         /* pin configuration */
 170         enum twl4030_usb_mode   usb_mode;
 171
 172         int                     irq;
 173         enum musb_vbus_id_status linkstat;
 174         bool                    vbus_supplied;
 175         bool                    musb_mailbox_pending;
 176
 177         struct delayed_work     id_workaround_work;
 178 };
 179
 180 /* internal define on top of container_of */
 181 #define phy_to_twl(x)           container_of((x), struct twl4030_usb, phy)
 182
 183 /*-------------------------------------------------------------------------*/
 184
 185 static int twl4030_i2c_write_u8_verify(struct twl4030_usb *twl,
 186                 u8 module, u8 data, u8 address)
 187 {
 188         u8 check;
 189
 190         if ((twl_i2c_write_u8(module, data, address) >= 0) &&
 191             (twl_i2c_read_u8(module, &check, address) >= 0) &&
 192                                                 (check == data))
 193                 return 0;
 194         dev_dbg(twl->dev, "Write%d[%d,0x%x] wrote %02x but read %02x\n",
 195                         1, module, address, check, data);
 196
 197         /* Failed once: Try again */
 198         if ((twl_i2c_write_u8(module, data, address) >= 0) &&
 199             (twl_i2c_read_u8(module, &check, address) >= 0) &&
 200                                                 (check == data))
 201                 return 0;
 202         dev_dbg(twl->dev, "Write%d[%d,0x%x] wrote %02x but read %02x\n",
 203                         2, module, address, check, data);
 204
 205         /* Failed again: Return error */
 206         return -EBUSY;
 207 }
 208
 209 #define twl4030_usb_write_verify(twl, address, data)    \
 210         twl4030_i2c_write_u8_verify(twl, TWL_MODULE_USB, (data), (address))
 211
 212 static inline int twl4030_usb_write(struct twl4030_usb *twl,
 213                 u8 address, u8 data)
 214 {
 215         int ret = 0;
 216
 217         ret = twl_i2c_write_u8(TWL_MODULE_USB, data, address);
 218         if (ret < 0)
 219                 dev_dbg(twl->dev,
 220                         "TWL4030:USB:Write[0x%x] Error %d\n", address, ret);
 221         return ret;
 222 }
 223
 224 static inline int twl4030_readb(struct twl4030_usb *twl, u8 module, u8 address)
 225 {
 226         u8 data;
 227         int ret = 0;
 228
 229         ret = twl_i2c_read_u8(module, &data, address);
 230         if (ret >= 0)
 231                 ret = data;
 232         else
 233                 dev_dbg(twl->dev,
 234                         "TWL4030:readb[0x%x,0x%x] Error %d\n",
 235                                         module, address, ret);
 236
 237         return ret;
 238 }
 239
 240 static inline int twl4030_usb_read(struct twl4030_usb *twl, u8 address)
 241 {
 242         return twl4030_readb(twl, TWL_MODULE_USB, address);
 243 }
 244
 245 /*-------------------------------------------------------------------------*/
 246
 247 static inline int
 248 twl4030_usb_set_bits(struct twl4030_usb *twl, u8 reg, u8 bits)
 249 {
 250         return twl4030_usb_write(twl, ULPI_SET(reg), bits);
 251 }
 252
 253 static inline int
 254 twl4030_usb_clear_bits(struct twl4030_usb *twl, u8 reg, u8 bits)
 255 {
 256         return twl4030_usb_write(twl, ULPI_CLR(reg), bits);
 257 }
 258
 259 /*-------------------------------------------------------------------------*/
 260
 261 static bool twl4030_is_driving_vbus(struct twl4030_usb *twl)
 262 {
 263         int ret;
 264
 265         ret = twl4030_usb_read(twl, PHY_CLK_CTRL_STS);
 266         if (ret < 0 || !(ret & PHY_DPLL_CLK))
 267                 /*
 268                  * if clocks are off, registers are not updated,
 269                  * but we can assume we don't drive VBUS in this case
 270                  */
 271                 return false;
 272
 273         ret = twl4030_usb_read(twl, ULPI_OTG_CTRL);
 274         if (ret < 0)
 275                 return false;
 276
 277         return (ret & (ULPI_OTG_DRVVBUS | ULPI_OTG_CHRGVBUS)) ? true : false;
 278 }
 279
 280 static enum musb_vbus_id_status
 281         twl4030_usb_linkstat(struct twl4030_usb *twl)
 282 {
 283         int     status;
 284         enum musb_vbus_id_status linkstat = MUSB_UNKNOWN;
 285
 286         twl->vbus_supplied = false;
 287
 288         /*
 289          * For ID/VBUS sensing, see manual section 15.4.8 ...
 290          * except when using only battery backup power, two
 291          * comparators produce VBUS_PRES and ID_PRES signals,
 292          * which don't match docs elsewhere.  But ... BIT(7)
 293          * and BIT(2) of STS_HW_CONDITIONS, respectively, do
 294          * seem to match up.  If either is true the USB_PRES
 295          * signal is active, the OTG module is activated, and
 296          * its interrupt may be raised (may wake the system).
 297          */
 298         status = twl4030_readb(twl, TWL_MODULE_PM_MASTER, STS_HW_CONDITIONS);
 299         if (status < 0)
 300                 dev_err(twl->dev, "USB link status err %d\n", status);
 301         else if (status & (BIT(7) | BIT(2))) {
 302                 if (status & BIT(7)) {
 303                         if (twl4030_is_driving_vbus(twl))
 304                                 status &= ~BIT(7);
 305                         else
 306                                 twl->vbus_supplied = true;
 307                 }
 308
 309                 if (status & BIT(2))
 310                         linkstat = MUSB_ID_GROUND;
 311                 else if (status & BIT(7))
 312                         linkstat = MUSB_VBUS_VALID;
 313                 else
 314                         linkstat = MUSB_VBUS_OFF;
 315         } else {
 316                 if (twl->linkstat != MUSB_UNKNOWN)
 317                         linkstat = MUSB_VBUS_OFF;
 318         }
 319
 320         dev_dbg(twl->dev, "HW_CONDITIONS 0x%02x/%d; link %d\n",
 321                         status, status, linkstat);
 322
 323         /* REVISIT this assumes host and peripheral controllers
 324          * are registered, and that both are active...
 325          */
 326
 327         return linkstat;
 328 }
 329
 330 static void twl4030_usb_set_mode(struct twl4030_usb *twl, int mode)
 331 {
 332         twl->usb_mode = mode;
 333
 334         switch (mode) {
 335         case T2_USB_MODE_ULPI:
 336                 twl4030_usb_clear_bits(twl, ULPI_IFC_CTRL,
 337                                         ULPI_IFC_CTRL_CARKITMODE);
 338                 twl4030_usb_set_bits(twl, POWER_CTRL, POWER_CTRL_OTG_ENAB);
 339                 twl4030_usb_clear_bits(twl, ULPI_FUNC_CTRL,
 340                                         ULPI_FUNC_CTRL_XCVRSEL_MASK |
 341                                         ULPI_FUNC_CTRL_OPMODE_MASK);
 342                 break;
 343         case -1:
 344                 /* FIXME: power on defaults */
 345                 break;
 346         default:
 347                 dev_err(twl->dev, "unsupported T2 transceiver mode %d\n",
 348                                 mode);
 349                 break;
 350         }
 351 }
 352
 353 static void twl4030_i2c_access(struct twl4030_usb *twl, int on)
 354 {
 355         unsigned long timeout;
 356         int val = twl4030_usb_read(twl, PHY_CLK_CTRL);
 357
 358         if (val >= 0) {
 359                 if (on) {
 360                         /* enable DPLL to access PHY registers over I2C */
 361                         val |= REQ_PHY_DPLL_CLK;
 362                         WARN_ON(twl4030_usb_write_verify(twl, PHY_CLK_CTRL,
 363                                                 (u8)val) < 0);
 364
 365                         timeout = jiffies + HZ;
 366                         while (!(twl4030_usb_read(twl, PHY_CLK_CTRL_STS) &
 367                                                         PHY_DPLL_CLK)
 368                                 && time_before(jiffies, timeout))
 369                                         udelay(10);
 370                         if (!(twl4030_usb_read(twl, PHY_CLK_CTRL_STS) &
 371                                                         PHY_DPLL_CLK))
 372                                 dev_err(twl->dev, "Timeout setting T2 HSUSB "
 373                                                 "PHY DPLL clock\n");
 374                 } else {
 375                         /* let ULPI control the DPLL clock */
 376                         val &= ~REQ_PHY_DPLL_CLK;
 377                         WARN_ON(twl4030_usb_write_verify(twl, PHY_CLK_CTRL,
 378                                                 (u8)val) < 0);
 379                 }
 380         }
 381 }
 382
 383 static void __twl4030_phy_power(struct twl4030_usb *twl, int on)
 384 {
 385         u8 pwr = twl4030_usb_read(twl, PHY_PWR_CTRL);
 386
 387         if (on)
 388                 pwr &= ~PHY_PWR_PHYPWD;
 389         else
 390                 pwr |= PHY_PWR_PHYPWD;
 391
 392         WARN_ON(twl4030_usb_write_verify(twl, PHY_PWR_CTRL, pwr) < 0);
 393 }
 394
 395 static int __maybe_unused twl4030_usb_runtime_suspend(struct device *dev)
 396 {
 397         struct twl4030_usb *twl = dev_get_drvdata(dev);
 398
 399         dev_dbg(twl->dev, "%s\n", __func__);
 400
 401         __twl4030_phy_power(twl, 0);
 402         regulator_disable(twl->usb1v5);
 403         regulator_disable(twl->usb1v8);
 404         regulator_disable(twl->usb3v1);
 405
 406         return 0;
 407 }
 408
 409 static int __maybe_unused twl4030_usb_runtime_resume(struct device *dev)
 410 {
 411         struct twl4030_usb *twl = dev_get_drvdata(dev);
 412         int res;
 413
 414         dev_dbg(twl->dev, "%s\n", __func__);
 415
 416         res = regulator_enable(twl->usb3v1);
 417         if (res)
 418                 dev_err(twl->dev, "Failed to enable usb3v1\n");
 419
 420         res = regulator_enable(twl->usb1v8);
 421         if (res)
 422                 dev_err(twl->dev, "Failed to enable usb1v8\n");
 423
 424         /*
 425          * Disabling usb3v1 regulator (= writing 0 to VUSB3V1_DEV_GRP
 426          * in twl4030) resets the VUSB_DEDICATED2 register. This reset
 427          * enables VUSB3V1_SLEEP bit that remaps usb3v1 ACTIVE state to
 428          * SLEEP. We work around this by clearing the bit after usv3v1
 429          * is re-activated. This ensures that VUSB3V1 is really active.
 430          */
 431         twl_i2c_write_u8(TWL_MODULE_PM_RECEIVER, 0, VUSB_DEDICATED2);
 432
 433         res = regulator_enable(twl->usb1v5);
 434         if (res)
 435                 dev_err(twl->dev, "Failed to enable usb1v5\n");
 436
 437         __twl4030_phy_power(twl, 1);
 438         twl4030_usb_write(twl, PHY_CLK_CTRL,
 439                           twl4030_usb_read(twl, PHY_CLK_CTRL) |
 440                           (PHY_CLK_CTRL_CLOCKGATING_EN |
 441                            PHY_CLK_CTRL_CLK32K_EN));
 442
 443         return 0;
 444 }
 445
 446 static int twl4030_phy_power_off(struct phy *phy)
 447 {
 448         struct twl4030_usb *twl = phy_get_drvdata(phy);
 449
 450         dev_dbg(twl->dev, "%s\n", __func__);
 451         pm_runtime_mark_last_busy(twl->dev);
 452         pm_runtime_put_autosuspend(twl->dev);
 453
 454         return 0;
 455 }
 456
 457 static int twl4030_phy_power_on(struct phy *phy)
 458 {
 459         struct twl4030_usb *twl = phy_get_drvdata(phy);
 460
 461         dev_dbg(twl->dev, "%s\n", __func__);
 462         pm_runtime_get_sync(twl->dev);
 463         twl4030_i2c_access(twl, 1);
 464         twl4030_usb_set_mode(twl, twl->usb_mode);
 465         if (twl->usb_mode == T2_USB_MODE_ULPI)
 466                 twl4030_i2c_access(twl, 0);
 467         twl->linkstat = MUSB_UNKNOWN;
 468         schedule_delayed_work(&twl->id_workaround_work, HZ);
 469
 470         return 0;
 471 }
 472
 473 static int twl4030_usb_ldo_init(struct twl4030_usb *twl)
 474 {
 475         /* Enable writing to power configuration registers */
 476         twl_i2c_write_u8(TWL_MODULE_PM_MASTER, TWL4030_PM_MASTER_KEY_CFG1,
 477                          TWL4030_PM_MASTER_PROTECT_KEY);
 478
 479         twl_i2c_write_u8(TWL_MODULE_PM_MASTER, TWL4030_PM_MASTER_KEY_CFG2,
 480                          TWL4030_PM_MASTER_PROTECT_KEY);
 481
 482         /* Keep VUSB3V1 LDO in sleep state until VBUS/ID change detected*/
 483         /*twl_i2c_write_u8(TWL_MODULE_PM_RECEIVER, 0, VUSB_DEDICATED2);*/
 484
 485         /* input to VUSB3V1 LDO is from VBAT, not VBUS */
 486         twl_i2c_write_u8(TWL_MODULE_PM_RECEIVER, 0x14, VUSB_DEDICATED1);
 487
 488         /* Initialize 3.1V regulator */
 489         twl_i2c_write_u8(TWL_MODULE_PM_RECEIVER, 0, VUSB3V1_DEV_GRP);
 490
 491         twl->usb3v1 = devm_regulator_get(twl->dev, "usb3v1");
 492         if (IS_ERR(twl->usb3v1))
 493                 return -ENODEV;
 494
 495         twl_i2c_write_u8(TWL_MODULE_PM_RECEIVER, 0, VUSB3V1_TYPE);
 496
 497         /* Initialize 1.5V regulator */
 498         twl_i2c_write_u8(TWL_MODULE_PM_RECEIVER, 0, VUSB1V5_DEV_GRP);
 499
 500         twl->usb1v5 = devm_regulator_get(twl->dev, "usb1v5");
 501         if (IS_ERR(twl->usb1v5))
 502                 return -ENODEV;
 503
 504         twl_i2c_write_u8(TWL_MODULE_PM_RECEIVER, 0, VUSB1V5_TYPE);
 505
 506         /* Initialize 1.8V regulator */
 507         twl_i2c_write_u8(TWL_MODULE_PM_RECEIVER, 0, VUSB1V8_DEV_GRP);
 508
 509         twl->usb1v8 = devm_regulator_get(twl->dev, "usb1v8");
 510         if (IS_ERR(twl->usb1v8))
 511                 return -ENODEV;
 512
 513         twl_i2c_write_u8(TWL_MODULE_PM_RECEIVER, 0, VUSB1V8_TYPE);
 514
 515         /* disable access to power configuration registers */
 516         twl_i2c_write_u8(TWL_MODULE_PM_MASTER, 0,
 517                          TWL4030_PM_MASTER_PROTECT_KEY);
 518
 519         return 0;
 520 }
 521
 522 static ssize_t twl4030_usb_vbus_show(struct device *dev,
 523                 struct device_attribute *attr, char *buf)
 524 {
 525         struct twl4030_usb *twl = dev_get_drvdata(dev);
 526         int ret = -EINVAL;
 527
 528         mutex_lock(&twl->lock);
 529         ret = sprintf(buf, "%s\n",
 530                         twl->vbus_supplied ? "on" : "off");
 531         mutex_unlock(&twl->lock);
 532
 533         return ret;
 534 }
 535 static DEVICE_ATTR(vbus, 0444, twl4030_usb_vbus_show, NULL);
 536
 537 static irqreturn_t twl4030_usb_irq(int irq, void *_twl)
 538 {
 539         struct twl4030_usb *twl = _twl;
 540         enum musb_vbus_id_status status;
 541         bool status_changed = false;
 542         int err;
 543
 544         status = twl4030_usb_linkstat(twl);
 545
 546         mutex_lock(&twl->lock);
 547         if (status >= 0 && status != twl->linkstat) {
 548                 status_changed =
 549                         cable_present(twl->linkstat) !=
 550                         cable_present(status);
 551                 twl->linkstat = status;
 552         }
 553         mutex_unlock(&twl->lock);
 554
 555         if (status_changed) {
 556                 /* FIXME add a set_power() method so that B-devices can
 557                  * configure the charger appropriately.  It's not always
 558                  * correct to consume VBUS power, and how much current to
 559                  * consume is a function of the USB configuration chosen
 560                  * by the host.
 561                  *
 562                  * REVISIT usb_gadget_vbus_connect(...) as needed, ditto
 563                  * its disconnect() sibling, when changing to/from the
 564                  * USB_LINK_VBUS state.  musb_hdrc won't care until it
 565                  * starts to handle softconnect right.
 566                  */
 567                 if (cable_present(status)) {
 568                         pm_runtime_get_sync(twl->dev);
 569                 } else {
 570                         pm_runtime_mark_last_busy(twl->dev);
 571                         pm_runtime_put_autosuspend(twl->dev);
 572                 }
 573                 twl->musb_mailbox_pending = true;
 574         }
 575         if (twl->musb_mailbox_pending) {
 576                 err = musb_mailbox(status);
 577                 if (!err)
 578                         twl->musb_mailbox_pending = false;
 579         }
 580
 581         /* don't schedule during sleep - irq works right then */
 582         if (status == MUSB_ID_GROUND && pm_runtime_active(twl->dev)) {
 583                 cancel_delayed_work(&twl->id_workaround_work);
 584                 schedule_delayed_work(&twl->id_workaround_work, HZ);
 585         }
 586
 587         if (irq)
 588                 sysfs_notify(&twl->dev->kobj, NULL, "vbus");
 589
 590         return IRQ_HANDLED;
 591 }
 592
 593 static void twl4030_id_workaround_work(struct work_struct *work)
 594 {
 595         struct twl4030_usb *twl = container_of(work, struct twl4030_usb,
 596                 id_workaround_work.work);
 597
 598         twl4030_usb_irq(0, twl);
 599 }
 600
 601 static int twl4030_phy_init(struct phy *phy)
 602 {
 603         struct twl4030_usb *twl = phy_get_drvdata(phy);
 604
 605         pm_runtime_get_sync(twl->dev);
 606         twl->linkstat = MUSB_UNKNOWN;
 607         schedule_delayed_work(&twl->id_workaround_work, HZ);
 608         pm_runtime_mark_last_busy(twl->dev);
 609         pm_runtime_put_autosuspend(twl->dev);
 610
 611         return 0;
 612 }
 613
 614 static int twl4030_set_peripheral(struct usb_otg *otg,
 615                                         struct usb_gadget *gadget)
 616 {
 617         if (!otg)
 618                 return -ENODEV;
 619
 620         otg->gadget = gadget;
 621         if (!gadget)
 622                 otg->state = OTG_STATE_UNDEFINED;
 623
 624         return 0;
 625 }
 626
 627 static int twl4030_set_host(struct usb_otg *otg, struct usb_bus *host)
 628 {
 629         if (!otg)
 630                 return -ENODEV;
 631
 632         otg->host = host;
 633         if (!host)
 634                 otg->state = OTG_STATE_UNDEFINED;
 635
 636         return 0;
 637 }
 638
 639 static const struct phy_ops ops = {
 640         .init           = twl4030_phy_init,
 641         .power_on       = twl4030_phy_power_on,
 642         .power_off      = twl4030_phy_power_off,
 643         .owner          = THIS_MODULE,
 644 };
 645
 646 static const struct dev_pm_ops twl4030_usb_pm_ops = {
 647         SET_RUNTIME_PM_OPS(twl4030_usb_runtime_suspend,
 648                            twl4030_usb_runtime_resume, NULL)
 649 };
 650
 651 static int twl4030_usb_probe(struct platform_device *pdev)
 652 {
 653         struct twl4030_usb_data *pdata = dev_get_platdata(&pdev->dev);
 654         struct twl4030_usb      *twl;
 655         struct phy              *phy;
 656         int                     status, err;
 657         struct usb_otg          *otg;
 658         struct device_node      *np = pdev->dev.of_node;
 659         struct phy_provider     *phy_provider;
 660
 661         twl = devm_kzalloc(&pdev->dev, sizeof(*twl), GFP_KERNEL);
 662         if (!twl)
 663                 return -ENOMEM;
 664
 665         if (np)
 666                 of_property_read_u32(np, "usb_mode",
 667                                 (enum twl4030_usb_mode *)&twl->usb_mode);
 668         else if (pdata) {
 669                 twl->usb_mode = pdata->usb_mode;
 670         } else {
 671                 dev_err(&pdev->dev, "twl4030 initialized without pdata\n");
 672                 return -EINVAL;
 673         }
 674
 675         otg = devm_kzalloc(&pdev->dev, sizeof(*otg), GFP_KERNEL);
 676         if (!otg)
 677                 return -ENOMEM;
 678
 679         twl->dev                = &pdev->dev;
 680         twl->irq                = platform_get_irq(pdev, 0);
 681         twl->vbus_supplied      = false;
 682         twl->linkstat           = MUSB_UNKNOWN;
 683         twl->musb_mailbox_pending = false;
 684
 685         twl->phy.dev            = twl->dev;
 686         twl->phy.label          = "twl4030";
 687         twl->phy.otg            = otg;
 688         twl->phy.type           = USB_PHY_TYPE_USB2;
 689
 690         otg->usb_phy            = &twl->phy;
 691         otg->set_host           = twl4030_set_host;
 692         otg->set_peripheral     = twl4030_set_peripheral;
 693
 694         phy = devm_phy_create(twl->dev, NULL, &ops);
 695         if (IS_ERR(phy)) {
 696                 dev_dbg(&pdev->dev, "Failed to create PHY\n");
 697                 return PTR_ERR(phy);
 698         }
 699
 700         phy_set_drvdata(phy, twl);
 701
 702         phy_provider = devm_of_phy_provider_register(twl->dev,
 703                 of_phy_simple_xlate);
 704         if (IS_ERR(phy_provider))
 705                 return PTR_ERR(phy_provider);
 706
 707         /* init mutex for workqueue */
 708         mutex_init(&twl->lock);
 709
 710         INIT_DELAYED_WORK(&twl->id_workaround_work, twl4030_id_workaround_work);
 711
 712         err = twl4030_usb_ldo_init(twl);
 713         if (err) {
 714                 dev_err(&pdev->dev, "ldo init failed\n");
 715                 return err;
 716         }
 717         usb_add_phy_dev(&twl->phy);
 718
 719         platform_set_drvdata(pdev, twl);
 720         if (device_create_file(&pdev->dev, &dev_attr_vbus))
 721                 dev_warn(&pdev->dev, "could not create sysfs file\n");
 722
 723         ATOMIC_INIT_NOTIFIER_HEAD(&twl->phy.notifier);
 724
 725         pm_runtime_use_autosuspend(&pdev->dev);
 726         pm_runtime_set_autosuspend_delay(&pdev->dev, 2000);
 727         pm_runtime_enable(&pdev->dev);
 728         pm_runtime_get_sync(&pdev->dev);
 729
 730         /* Our job is to use irqs and status from the power module
 731          * to keep the transceiver disabled when nothing's connected.
 732          *
 733          * FIXME we actually shouldn't start enabling it until the
 734          * USB controller drivers have said they're ready, by calling
 735          * set_host() and/or set_peripheral() ... OTG_capable boards
 736          * need both handles, otherwise just one suffices.
 737          */
 738         status = devm_request_threaded_irq(twl->dev, twl->irq, NULL,
 739                         twl4030_usb_irq, IRQF_TRIGGER_FALLING |
 740                         IRQF_TRIGGER_RISING | IRQF_ONESHOT, "twl4030_usb", twl);
 741         if (status < 0) {
 742                 dev_dbg(&pdev->dev, "can't get IRQ %d, err %d\n",
 743                         twl->irq, status);
 744                 return status;
 745         }
 746
 747         if (pdata)
 748                 err = phy_create_lookup(phy, "usb", "musb-hdrc.0");
 749         if (err)
 750                 return err;
 751
 752         pm_runtime_mark_last_busy(&pdev->dev);
 753         pm_runtime_put_autosuspend(twl->dev);
 754
 755         dev_info(&pdev->dev, "Initialized TWL4030 USB module\n");
 756         return 0;
 757 }
 758
 759 static int twl4030_usb_remove(struct platform_device *pdev)
 760 {
 761         struct twl4030_usb *twl = platform_get_drvdata(pdev);
 762         int val;
 763
 764         usb_remove_phy(&twl->phy);
 765         pm_runtime_get_sync(twl->dev);
 766         cancel_delayed_work(&twl->id_workaround_work);
 767         device_remove_file(twl->dev, &dev_attr_vbus);
 768
 769         /* set transceiver mode to power on defaults */
 770         twl4030_usb_set_mode(twl, -1);
 771
 772         /* idle ulpi before powering off */
 773         if (cable_present(twl->linkstat))
 774                 pm_runtime_put_noidle(twl->dev);
 775         pm_runtime_mark_last_busy(twl->dev);
 776         pm_runtime_dont_use_autosuspend(&pdev->dev);
 777         pm_runtime_put_sync(twl->dev);
 778         pm_runtime_disable(twl->dev);
 779
 780         /* autogate 60MHz ULPI clock,
 781          * clear dpll clock request for i2c access,
 782          * disable 32KHz
 783          */
 784         val = twl4030_usb_read(twl, PHY_CLK_CTRL);
 785         if (val >= 0) {
 786                 val |= PHY_CLK_CTRL_CLOCKGATING_EN;
 787                 val &= ~(PHY_CLK_CTRL_CLK32K_EN | REQ_PHY_DPLL_CLK);
 788                 twl4030_usb_write(twl, PHY_CLK_CTRL, (u8)val);
 789         }
 790
 791         /* disable complete OTG block */
 792         twl4030_usb_clear_bits(twl, POWER_CTRL, POWER_CTRL_OTG_ENAB);
 793
 794         return 0;
 795 }
 796
 797 #ifdef CONFIG_OF
 798 static const struct of_device_id twl4030_usb_id_table[] = {
 799         { .compatible = "ti,twl4030-usb" },
 800         {}
 801 };
 802 MODULE_DEVICE_TABLE(of, twl4030_usb_id_table);
 803 #endif
 804
 805 static struct platform_driver twl4030_usb_driver = {
 806         .probe          = twl4030_usb_probe,
 807         .remove         = twl4030_usb_remove,
 808         .driver         = {
 809                 .name   = "twl4030_usb",
 810                 .pm     = &twl4030_usb_pm_ops,
 811                 .of_match_table = of_match_ptr(twl4030_usb_id_table),
 812         },
 813 };
 814
 815 static int __init twl4030_usb_init(void)
 816 {
 817         return platform_driver_register(&twl4030_usb_driver);
 818 }
 819 subsys_initcall(twl4030_usb_init);
 820
 821 static void __exit twl4030_usb_exit(void)
 822 {
 823         platform_driver_unregister(&twl4030_usb_driver);
 824 }
 825 module_exit(twl4030_usb_exit);
 826
 827 MODULE_ALIAS("platform:twl4030_usb");
 828 MODULE_AUTHOR("Texas Instruments, Inc, Nokia Corporation");
 829 MODULE_DESCRIPTION("TWL4030 USB transceiver driver");
 830 MODULE_LICENSE("GPL");