2 * Copyright (C) 2014-2015 Broadcom Corporation
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License as
6 * published by the Free Software Foundation version 2.
8 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
9 * kind, whether express or implied; without even the implied warranty
10 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
13 * This file contains the Broadcom Iproc GPIO driver that supports 3
14 * GPIO controllers on Iproc including the ASIU GPIO controller, the
15 * chipCommonG GPIO controller, and the always-on GPIO controller. Basic
16 * PINCONF such as bias pull up/down, and drive strength are also supported
19 * It provides the functionality where pins from the GPIO can be
20 * individually muxed to GPIO function, if individual pad
21 * configuration is supported, through the interaction with respective
22 * SoCs IOMUX controller.
25 #include <linux/kernel.h>
26 #include <linux/slab.h>
27 #include <linux/interrupt.h>
29 #include <linux/gpio/driver.h>
30 #include <linux/ioport.h>
31 #include <linux/of_device.h>
32 #include <linux/of_irq.h>
33 #include <linux/pinctrl/pinctrl.h>
34 #include <linux/pinctrl/pinconf.h>
35 #include <linux/pinctrl/pinconf-generic.h>
37 #include "../pinctrl-utils.h"
39 #define IPROC_GPIO_DATA_IN_OFFSET 0x00
40 #define IPROC_GPIO_DATA_OUT_OFFSET 0x04
41 #define IPROC_GPIO_OUT_EN_OFFSET 0x08
42 #define IPROC_GPIO_INT_TYPE_OFFSET 0x0c
43 #define IPROC_GPIO_INT_DE_OFFSET 0x10
44 #define IPROC_GPIO_INT_EDGE_OFFSET 0x14
45 #define IPROC_GPIO_INT_MSK_OFFSET 0x18
46 #define IPROC_GPIO_INT_STAT_OFFSET 0x1c
47 #define IPROC_GPIO_INT_MSTAT_OFFSET 0x20
48 #define IPROC_GPIO_INT_CLR_OFFSET 0x24
49 #define IPROC_GPIO_PAD_RES_OFFSET 0x34
50 #define IPROC_GPIO_RES_EN_OFFSET 0x38
52 /* drive strength control for ASIU GPIO */
53 #define IPROC_GPIO_ASIU_DRV0_CTRL_OFFSET 0x58
55 /* drive strength control for CCM/CRMU (AON) GPIO */
56 #define IPROC_GPIO_DRV0_CTRL_OFFSET 0x00
58 #define GPIO_BANK_SIZE 0x200
59 #define NGPIOS_PER_BANK 32
60 #define GPIO_BANK(pin) ((pin) / NGPIOS_PER_BANK)
62 #define IPROC_GPIO_REG(pin, reg) (GPIO_BANK(pin) * GPIO_BANK_SIZE + (reg))
63 #define IPROC_GPIO_SHIFT(pin) ((pin) % NGPIOS_PER_BANK)
65 #define GPIO_DRV_STRENGTH_BIT_SHIFT 20
66 #define GPIO_DRV_STRENGTH_BITS 3
67 #define GPIO_DRV_STRENGTH_BIT_MASK ((1 << GPIO_DRV_STRENGTH_BITS) - 1)
72 * @dev: pointer to device
73 * @base: I/O register base for Iproc GPIO controller
74 * @io_ctrl: I/O register base for certain type of Iproc GPIO controller that
75 * has the PINCONF support implemented outside of the GPIO block
76 * @lock: lock to protect access to I/O registers
78 * @num_banks: number of GPIO banks, each bank supports up to 32 GPIOs
79 * @pinmux_is_supported: flag to indicate this GPIO controller contains pins
80 * that can be individually muxed to GPIO
81 * @pctl: pointer to pinctrl_dev
82 * @pctldesc: pinctrl descriptor
88 void __iomem *io_ctrl;
95 bool pinmux_is_supported;
97 struct pinctrl_dev *pctl;
98 struct pinctrl_desc pctldesc;
102 * Mapping from PINCONF pins to GPIO pins is 1-to-1
104 static inline unsigned iproc_pin_to_gpio(unsigned pin)
110 * iproc_set_bit - set or clear one bit (corresponding to the GPIO pin) in a
111 * Iproc GPIO register
113 * @iproc_gpio: Iproc GPIO device
114 * @reg: register offset
118 static inline void iproc_set_bit(struct iproc_gpio *chip, unsigned int reg,
119 unsigned gpio, bool set)
121 unsigned int offset = IPROC_GPIO_REG(gpio, reg);
122 unsigned int shift = IPROC_GPIO_SHIFT(gpio);
125 val = readl(chip->base + offset);
130 writel(val, chip->base + offset);
133 static inline bool iproc_get_bit(struct iproc_gpio *chip, unsigned int reg,
136 unsigned int offset = IPROC_GPIO_REG(gpio, reg);
137 unsigned int shift = IPROC_GPIO_SHIFT(gpio);
139 return !!(readl(chip->base + offset) & BIT(shift));
142 static void iproc_gpio_irq_handler(struct irq_desc *desc)
144 struct gpio_chip *gc = irq_desc_get_handler_data(desc);
145 struct iproc_gpio *chip = gpiochip_get_data(gc);
146 struct irq_chip *irq_chip = irq_desc_get_chip(desc);
149 chained_irq_enter(irq_chip, desc);
151 /* go through the entire GPIO banks and handle all interrupts */
152 for (i = 0; i < chip->num_banks; i++) {
153 unsigned long val = readl(chip->base + (i * GPIO_BANK_SIZE) +
154 IPROC_GPIO_INT_MSTAT_OFFSET);
156 for_each_set_bit(bit, &val, NGPIOS_PER_BANK) {
157 unsigned pin = NGPIOS_PER_BANK * i + bit;
158 int child_irq = irq_find_mapping(gc->irqdomain, pin);
161 * Clear the interrupt before invoking the
162 * handler, so we do not leave any window
164 writel(BIT(bit), chip->base + (i * GPIO_BANK_SIZE) +
165 IPROC_GPIO_INT_CLR_OFFSET);
167 generic_handle_irq(child_irq);
171 chained_irq_exit(irq_chip, desc);
175 static void iproc_gpio_irq_ack(struct irq_data *d)
177 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
178 struct iproc_gpio *chip = gpiochip_get_data(gc);
179 unsigned gpio = d->hwirq;
180 unsigned int offset = IPROC_GPIO_REG(gpio,
181 IPROC_GPIO_INT_CLR_OFFSET);
182 unsigned int shift = IPROC_GPIO_SHIFT(gpio);
183 u32 val = BIT(shift);
185 writel(val, chip->base + offset);
189 * iproc_gpio_irq_set_mask - mask/unmask a GPIO interrupt
192 * @unmask: mask/unmask GPIO interrupt
194 static void iproc_gpio_irq_set_mask(struct irq_data *d, bool unmask)
196 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
197 struct iproc_gpio *chip = gpiochip_get_data(gc);
198 unsigned gpio = d->hwirq;
200 iproc_set_bit(chip, IPROC_GPIO_INT_MSK_OFFSET, gpio, unmask);
203 static void iproc_gpio_irq_mask(struct irq_data *d)
205 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
206 struct iproc_gpio *chip = gpiochip_get_data(gc);
209 spin_lock_irqsave(&chip->lock, flags);
210 iproc_gpio_irq_set_mask(d, false);
211 spin_unlock_irqrestore(&chip->lock, flags);
214 static void iproc_gpio_irq_unmask(struct irq_data *d)
216 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
217 struct iproc_gpio *chip = gpiochip_get_data(gc);
220 spin_lock_irqsave(&chip->lock, flags);
221 iproc_gpio_irq_set_mask(d, true);
222 spin_unlock_irqrestore(&chip->lock, flags);
225 static int iproc_gpio_irq_set_type(struct irq_data *d, unsigned int type)
227 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
228 struct iproc_gpio *chip = gpiochip_get_data(gc);
229 unsigned gpio = d->hwirq;
230 bool level_triggered = false;
231 bool dual_edge = false;
232 bool rising_or_high = false;
235 switch (type & IRQ_TYPE_SENSE_MASK) {
236 case IRQ_TYPE_EDGE_RISING:
237 rising_or_high = true;
240 case IRQ_TYPE_EDGE_FALLING:
243 case IRQ_TYPE_EDGE_BOTH:
247 case IRQ_TYPE_LEVEL_HIGH:
248 level_triggered = true;
249 rising_or_high = true;
252 case IRQ_TYPE_LEVEL_LOW:
253 level_triggered = true;
257 dev_err(chip->dev, "invalid GPIO IRQ type 0x%x\n",
262 spin_lock_irqsave(&chip->lock, flags);
263 iproc_set_bit(chip, IPROC_GPIO_INT_TYPE_OFFSET, gpio,
265 iproc_set_bit(chip, IPROC_GPIO_INT_DE_OFFSET, gpio, dual_edge);
266 iproc_set_bit(chip, IPROC_GPIO_INT_EDGE_OFFSET, gpio,
268 spin_unlock_irqrestore(&chip->lock, flags);
271 "gpio:%u level_triggered:%d dual_edge:%d rising_or_high:%d\n",
272 gpio, level_triggered, dual_edge, rising_or_high);
277 static struct irq_chip iproc_gpio_irq_chip = {
278 .name = "bcm-iproc-gpio",
279 .irq_ack = iproc_gpio_irq_ack,
280 .irq_mask = iproc_gpio_irq_mask,
281 .irq_unmask = iproc_gpio_irq_unmask,
282 .irq_set_type = iproc_gpio_irq_set_type,
286 * Request the Iproc IOMUX pinmux controller to mux individual pins to GPIO
288 static int iproc_gpio_request(struct gpio_chip *gc, unsigned offset)
290 struct iproc_gpio *chip = gpiochip_get_data(gc);
291 unsigned gpio = gc->base + offset;
293 /* not all Iproc GPIO pins can be muxed individually */
294 if (!chip->pinmux_is_supported)
297 return pinctrl_request_gpio(gpio);
300 static void iproc_gpio_free(struct gpio_chip *gc, unsigned offset)
302 struct iproc_gpio *chip = gpiochip_get_data(gc);
303 unsigned gpio = gc->base + offset;
305 if (!chip->pinmux_is_supported)
308 pinctrl_free_gpio(gpio);
311 static int iproc_gpio_direction_input(struct gpio_chip *gc, unsigned gpio)
313 struct iproc_gpio *chip = gpiochip_get_data(gc);
316 spin_lock_irqsave(&chip->lock, flags);
317 iproc_set_bit(chip, IPROC_GPIO_OUT_EN_OFFSET, gpio, false);
318 spin_unlock_irqrestore(&chip->lock, flags);
320 dev_dbg(chip->dev, "gpio:%u set input\n", gpio);
325 static int iproc_gpio_direction_output(struct gpio_chip *gc, unsigned gpio,
328 struct iproc_gpio *chip = gpiochip_get_data(gc);
331 spin_lock_irqsave(&chip->lock, flags);
332 iproc_set_bit(chip, IPROC_GPIO_OUT_EN_OFFSET, gpio, true);
333 iproc_set_bit(chip, IPROC_GPIO_DATA_OUT_OFFSET, gpio, !!(val));
334 spin_unlock_irqrestore(&chip->lock, flags);
336 dev_dbg(chip->dev, "gpio:%u set output, value:%d\n", gpio, val);
341 static void iproc_gpio_set(struct gpio_chip *gc, unsigned gpio, int val)
343 struct iproc_gpio *chip = gpiochip_get_data(gc);
346 spin_lock_irqsave(&chip->lock, flags);
347 iproc_set_bit(chip, IPROC_GPIO_DATA_OUT_OFFSET, gpio, !!(val));
348 spin_unlock_irqrestore(&chip->lock, flags);
350 dev_dbg(chip->dev, "gpio:%u set, value:%d\n", gpio, val);
353 static int iproc_gpio_get(struct gpio_chip *gc, unsigned gpio)
355 struct iproc_gpio *chip = gpiochip_get_data(gc);
356 unsigned int offset = IPROC_GPIO_REG(gpio,
357 IPROC_GPIO_DATA_IN_OFFSET);
358 unsigned int shift = IPROC_GPIO_SHIFT(gpio);
360 return !!(readl(chip->base + offset) & BIT(shift));
363 static int iproc_get_groups_count(struct pinctrl_dev *pctldev)
369 * Only one group: "gpio_grp", since this local pinctrl device only performs
370 * GPIO specific PINCONF configurations
372 static const char *iproc_get_group_name(struct pinctrl_dev *pctldev,
378 static const struct pinctrl_ops iproc_pctrl_ops = {
379 .get_groups_count = iproc_get_groups_count,
380 .get_group_name = iproc_get_group_name,
381 .dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
382 .dt_free_map = pinctrl_utils_free_map,
385 static int iproc_gpio_set_pull(struct iproc_gpio *chip, unsigned gpio,
386 bool disable, bool pull_up)
390 spin_lock_irqsave(&chip->lock, flags);
393 iproc_set_bit(chip, IPROC_GPIO_RES_EN_OFFSET, gpio, false);
395 iproc_set_bit(chip, IPROC_GPIO_PAD_RES_OFFSET, gpio,
397 iproc_set_bit(chip, IPROC_GPIO_RES_EN_OFFSET, gpio, true);
400 spin_unlock_irqrestore(&chip->lock, flags);
402 dev_dbg(chip->dev, "gpio:%u set pullup:%d\n", gpio, pull_up);
407 static void iproc_gpio_get_pull(struct iproc_gpio *chip, unsigned gpio,
408 bool *disable, bool *pull_up)
412 spin_lock_irqsave(&chip->lock, flags);
413 *disable = !iproc_get_bit(chip, IPROC_GPIO_RES_EN_OFFSET, gpio);
414 *pull_up = iproc_get_bit(chip, IPROC_GPIO_PAD_RES_OFFSET, gpio);
415 spin_unlock_irqrestore(&chip->lock, flags);
418 static int iproc_gpio_set_strength(struct iproc_gpio *chip, unsigned gpio,
422 unsigned int i, offset, shift;
426 /* make sure drive strength is supported */
427 if (strength < 2 || strength > 16 || (strength % 2))
431 base = chip->io_ctrl;
432 offset = IPROC_GPIO_DRV0_CTRL_OFFSET;
435 offset = IPROC_GPIO_REG(gpio,
436 IPROC_GPIO_ASIU_DRV0_CTRL_OFFSET);
439 shift = IPROC_GPIO_SHIFT(gpio);
441 dev_dbg(chip->dev, "gpio:%u set drive strength:%d mA\n", gpio,
444 spin_lock_irqsave(&chip->lock, flags);
445 strength = (strength / 2) - 1;
446 for (i = 0; i < GPIO_DRV_STRENGTH_BITS; i++) {
447 val = readl(base + offset);
449 val |= ((strength >> i) & 0x1) << shift;
450 writel(val, base + offset);
453 spin_unlock_irqrestore(&chip->lock, flags);
458 static int iproc_gpio_get_strength(struct iproc_gpio *chip, unsigned gpio,
462 unsigned int i, offset, shift;
467 base = chip->io_ctrl;
468 offset = IPROC_GPIO_DRV0_CTRL_OFFSET;
471 offset = IPROC_GPIO_REG(gpio,
472 IPROC_GPIO_ASIU_DRV0_CTRL_OFFSET);
475 shift = IPROC_GPIO_SHIFT(gpio);
477 spin_lock_irqsave(&chip->lock, flags);
479 for (i = 0; i < GPIO_DRV_STRENGTH_BITS; i++) {
480 val = readl(base + offset) & BIT(shift);
482 *strength += (val << i);
487 *strength = (*strength + 1) * 2;
488 spin_unlock_irqrestore(&chip->lock, flags);
493 static int iproc_pin_config_get(struct pinctrl_dev *pctldev, unsigned pin,
494 unsigned long *config)
496 struct iproc_gpio *chip = pinctrl_dev_get_drvdata(pctldev);
497 enum pin_config_param param = pinconf_to_config_param(*config);
498 unsigned gpio = iproc_pin_to_gpio(pin);
500 bool disable, pull_up;
504 case PIN_CONFIG_BIAS_DISABLE:
505 iproc_gpio_get_pull(chip, gpio, &disable, &pull_up);
511 case PIN_CONFIG_BIAS_PULL_UP:
512 iproc_gpio_get_pull(chip, gpio, &disable, &pull_up);
513 if (!disable && pull_up)
518 case PIN_CONFIG_BIAS_PULL_DOWN:
519 iproc_gpio_get_pull(chip, gpio, &disable, &pull_up);
520 if (!disable && !pull_up)
525 case PIN_CONFIG_DRIVE_STRENGTH:
526 ret = iproc_gpio_get_strength(chip, gpio, &arg);
529 *config = pinconf_to_config_packed(param, arg);
540 static int iproc_pin_config_set(struct pinctrl_dev *pctldev, unsigned pin,
541 unsigned long *configs, unsigned num_configs)
543 struct iproc_gpio *chip = pinctrl_dev_get_drvdata(pctldev);
544 enum pin_config_param param;
546 unsigned i, gpio = iproc_pin_to_gpio(pin);
549 for (i = 0; i < num_configs; i++) {
550 param = pinconf_to_config_param(configs[i]);
551 arg = pinconf_to_config_argument(configs[i]);
554 case PIN_CONFIG_BIAS_DISABLE:
555 ret = iproc_gpio_set_pull(chip, gpio, true, false);
560 case PIN_CONFIG_BIAS_PULL_UP:
561 ret = iproc_gpio_set_pull(chip, gpio, false, true);
566 case PIN_CONFIG_BIAS_PULL_DOWN:
567 ret = iproc_gpio_set_pull(chip, gpio, false, false);
572 case PIN_CONFIG_DRIVE_STRENGTH:
573 ret = iproc_gpio_set_strength(chip, gpio, arg);
579 dev_err(chip->dev, "invalid configuration\n");
582 } /* for each config */
588 static const struct pinconf_ops iproc_pconf_ops = {
590 .pin_config_get = iproc_pin_config_get,
591 .pin_config_set = iproc_pin_config_set,
595 * Iproc GPIO controller supports some PINCONF related configurations such as
596 * pull up, pull down, and drive strength, when the pin is configured to GPIO
598 * Here a local pinctrl device is created with simple 1-to-1 pin mapping to the
601 static int iproc_gpio_register_pinconf(struct iproc_gpio *chip)
603 struct pinctrl_desc *pctldesc = &chip->pctldesc;
604 struct pinctrl_pin_desc *pins;
605 struct gpio_chip *gc = &chip->gc;
608 pins = devm_kcalloc(chip->dev, gc->ngpio, sizeof(*pins), GFP_KERNEL);
612 for (i = 0; i < gc->ngpio; i++) {
614 pins[i].name = devm_kasprintf(chip->dev, GFP_KERNEL,
620 pctldesc->name = dev_name(chip->dev);
621 pctldesc->pctlops = &iproc_pctrl_ops;
622 pctldesc->pins = pins;
623 pctldesc->npins = gc->ngpio;
624 pctldesc->confops = &iproc_pconf_ops;
626 chip->pctl = devm_pinctrl_register(chip->dev, pctldesc, chip);
627 if (IS_ERR(chip->pctl)) {
628 dev_err(chip->dev, "unable to register pinctrl device\n");
629 return PTR_ERR(chip->pctl);
635 static const struct of_device_id iproc_gpio_of_match[] = {
636 { .compatible = "brcm,cygnus-ccm-gpio" },
637 { .compatible = "brcm,cygnus-asiu-gpio" },
638 { .compatible = "brcm,cygnus-crmu-gpio" },
639 { .compatible = "brcm,iproc-gpio" },
643 static int iproc_gpio_probe(struct platform_device *pdev)
645 struct device *dev = &pdev->dev;
646 struct resource *res;
647 struct iproc_gpio *chip;
648 struct gpio_chip *gc;
652 chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
657 platform_set_drvdata(pdev, chip);
659 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
660 chip->base = devm_ioremap_resource(dev, res);
661 if (IS_ERR(chip->base)) {
662 dev_err(dev, "unable to map I/O memory\n");
663 return PTR_ERR(chip->base);
666 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
668 chip->io_ctrl = devm_ioremap_resource(dev, res);
669 if (IS_ERR(chip->io_ctrl)) {
670 dev_err(dev, "unable to map I/O memory\n");
671 return PTR_ERR(chip->io_ctrl);
675 if (of_property_read_u32(dev->of_node, "ngpios", &ngpios)) {
676 dev_err(&pdev->dev, "missing ngpios DT property\n");
680 spin_lock_init(&chip->lock);
685 chip->num_banks = (ngpios + NGPIOS_PER_BANK - 1) / NGPIOS_PER_BANK;
686 gc->label = dev_name(dev);
688 gc->of_node = dev->of_node;
689 gc->request = iproc_gpio_request;
690 gc->free = iproc_gpio_free;
691 gc->direction_input = iproc_gpio_direction_input;
692 gc->direction_output = iproc_gpio_direction_output;
693 gc->set = iproc_gpio_set;
694 gc->get = iproc_gpio_get;
696 chip->pinmux_is_supported = of_property_read_bool(dev->of_node,
699 ret = gpiochip_add_data(gc, chip);
701 dev_err(dev, "unable to add GPIO chip\n");
705 ret = iproc_gpio_register_pinconf(chip);
707 dev_err(dev, "unable to register pinconf\n");
708 goto err_rm_gpiochip;
711 /* optional GPIO interrupt support */
712 irq = platform_get_irq(pdev, 0);
714 ret = gpiochip_irqchip_add(gc, &iproc_gpio_irq_chip, 0,
715 handle_simple_irq, IRQ_TYPE_NONE);
717 dev_err(dev, "no GPIO irqchip\n");
718 goto err_rm_gpiochip;
721 gpiochip_set_chained_irqchip(gc, &iproc_gpio_irq_chip, irq,
722 iproc_gpio_irq_handler);
733 static struct platform_driver iproc_gpio_driver = {
735 .name = "iproc-gpio",
736 .of_match_table = iproc_gpio_of_match,
738 .probe = iproc_gpio_probe,
741 static int __init iproc_gpio_init(void)
743 return platform_driver_probe(&iproc_gpio_driver, iproc_gpio_probe);
745 arch_initcall_sync(iproc_gpio_init);