2 * Cherryview/Braswell pinctrl driver
4 * Copyright (C) 2014, Intel Corporation
5 * Author: Mika Westerberg <mika.westerberg@linux.intel.com>
7 * This driver is based on the original Cherryview GPIO driver by
8 * Ning Li <ning.li@intel.com>
9 * Alan Cox <alan@linux.intel.com>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
16 #include <linux/kernel.h>
17 #include <linux/module.h>
18 #include <linux/init.h>
19 #include <linux/types.h>
20 #include <linux/gpio.h>
21 #include <linux/gpio/driver.h>
22 #include <linux/acpi.h>
23 #include <linux/pinctrl/pinctrl.h>
24 #include <linux/pinctrl/pinmux.h>
25 #include <linux/pinctrl/pinconf.h>
26 #include <linux/pinctrl/pinconf-generic.h>
27 #include <linux/platform_device.h>
29 #define CHV_INTSTAT 0x300
30 #define CHV_INTMASK 0x380
32 #define FAMILY_PAD_REGS_OFF 0x4400
33 #define FAMILY_PAD_REGS_SIZE 0x400
34 #define MAX_FAMILY_PAD_GPIO_NO 15
35 #define GPIO_REGS_SIZE 8
37 #define CHV_PADCTRL0 0x000
38 #define CHV_PADCTRL0_INTSEL_SHIFT 28
39 #define CHV_PADCTRL0_INTSEL_MASK (0xf << CHV_PADCTRL0_INTSEL_SHIFT)
40 #define CHV_PADCTRL0_TERM_UP BIT(23)
41 #define CHV_PADCTRL0_TERM_SHIFT 20
42 #define CHV_PADCTRL0_TERM_MASK (7 << CHV_PADCTRL0_TERM_SHIFT)
43 #define CHV_PADCTRL0_TERM_20K 1
44 #define CHV_PADCTRL0_TERM_5K 2
45 #define CHV_PADCTRL0_TERM_1K 4
46 #define CHV_PADCTRL0_PMODE_SHIFT 16
47 #define CHV_PADCTRL0_PMODE_MASK (0xf << CHV_PADCTRL0_PMODE_SHIFT)
48 #define CHV_PADCTRL0_GPIOEN BIT(15)
49 #define CHV_PADCTRL0_GPIOCFG_SHIFT 8
50 #define CHV_PADCTRL0_GPIOCFG_MASK (7 << CHV_PADCTRL0_GPIOCFG_SHIFT)
51 #define CHV_PADCTRL0_GPIOCFG_GPIO 0
52 #define CHV_PADCTRL0_GPIOCFG_GPO 1
53 #define CHV_PADCTRL0_GPIOCFG_GPI 2
54 #define CHV_PADCTRL0_GPIOCFG_HIZ 3
55 #define CHV_PADCTRL0_GPIOTXSTATE BIT(1)
56 #define CHV_PADCTRL0_GPIORXSTATE BIT(0)
58 #define CHV_PADCTRL1 0x004
59 #define CHV_PADCTRL1_CFGLOCK BIT(31)
60 #define CHV_PADCTRL1_INVRXTX_SHIFT 4
61 #define CHV_PADCTRL1_INVRXTX_MASK (0xf << CHV_PADCTRL1_INVRXTX_SHIFT)
62 #define CHV_PADCTRL1_INVRXTX_TXENABLE (2 << CHV_PADCTRL1_INVRXTX_SHIFT)
63 #define CHV_PADCTRL1_ODEN BIT(3)
64 #define CHV_PADCTRL1_INVRXTX_RXDATA (4 << CHV_PADCTRL1_INVRXTX_SHIFT)
65 #define CHV_PADCTRL1_INTWAKECFG_MASK 7
66 #define CHV_PADCTRL1_INTWAKECFG_FALLING 1
67 #define CHV_PADCTRL1_INTWAKECFG_RISING 2
68 #define CHV_PADCTRL1_INTWAKECFG_BOTH 3
69 #define CHV_PADCTRL1_INTWAKECFG_LEVEL 4
72 * struct chv_alternate_function - A per group or per pin alternate function
73 * @pin: Pin number (only used in per pin configs)
74 * @mode: Mode the pin should be set in
75 * @invert_oe: Invert OE for this pin
77 struct chv_alternate_function {
84 * struct chv_pincgroup - describes a CHV pin group
85 * @name: Name of the group
86 * @pins: An array of pins in this group
87 * @npins: Number of pins in this group
88 * @altfunc: Alternate function applied to all pins in this group
89 * @overrides: Alternate function override per pin or %NULL if not used
90 * @noverrides: Number of per pin alternate function overrides if
97 struct chv_alternate_function altfunc;
98 const struct chv_alternate_function *overrides;
103 * struct chv_function - A CHV pinmux function
104 * @name: Name of the function
105 * @groups: An array of groups for this function
106 * @ngroups: Number of groups in @groups
108 struct chv_function {
110 const char * const *groups;
115 * struct chv_gpio_pinrange - A range of pins that can be used as GPIOs
116 * @base: Start pin number
117 * @npins: Number of pins in this range
119 struct chv_gpio_pinrange {
125 * struct chv_community - A community specific configuration
126 * @uid: ACPI _UID used to match the community
127 * @pins: All pins in this community
128 * @npins: Number of pins
129 * @groups: All groups in this community
130 * @ngroups: Number of groups
131 * @functions: All functions in this community
132 * @nfunctions: Number of functions
133 * @ngpios: Number of GPIOs in this community
134 * @gpio_ranges: An array of GPIO ranges in this community
135 * @ngpio_ranges: Number of GPIO ranges
136 * @ngpios: Total number of GPIOs in this community
138 struct chv_community {
140 const struct pinctrl_pin_desc *pins;
142 const struct chv_pingroup *groups;
144 const struct chv_function *functions;
146 const struct chv_gpio_pinrange *gpio_ranges;
151 struct chv_pin_context {
157 * struct chv_pinctrl - CHV pinctrl private structure
158 * @dev: Pointer to the parent device
159 * @pctldesc: Pin controller description
160 * @pctldev: Pointer to the pin controller device
161 * @chip: GPIO chip in this pin controller
162 * @regs: MMIO registers
163 * @intr_lines: Stores mapping between 16 HW interrupt wires and GPIO
164 * offset (in GPIO number space)
165 * @community: Community this pinctrl instance represents
167 * The first group in @groups is expected to contain all pins that can be
172 struct pinctrl_desc pctldesc;
173 struct pinctrl_dev *pctldev;
174 struct gpio_chip chip;
176 unsigned intr_lines[16];
177 const struct chv_community *community;
179 struct chv_pin_context *saved_pin_context;
182 #define ALTERNATE_FUNCTION(p, m, i) \
189 #define PIN_GROUP(n, p, m, i) \
193 .npins = ARRAY_SIZE((p)), \
194 .altfunc.mode = (m), \
195 .altfunc.invert_oe = (i), \
198 #define PIN_GROUP_WITH_OVERRIDE(n, p, m, i, o) \
202 .npins = ARRAY_SIZE((p)), \
203 .altfunc.mode = (m), \
204 .altfunc.invert_oe = (i), \
206 .noverrides = ARRAY_SIZE((o)), \
209 #define FUNCTION(n, g) \
213 .ngroups = ARRAY_SIZE((g)), \
216 #define GPIO_PINRANGE(start, end) \
219 .npins = (end) - (start) + 1, \
222 static const struct pinctrl_pin_desc southwest_pins[] = {
223 PINCTRL_PIN(0, "FST_SPI_D2"),
224 PINCTRL_PIN(1, "FST_SPI_D0"),
225 PINCTRL_PIN(2, "FST_SPI_CLK"),
226 PINCTRL_PIN(3, "FST_SPI_D3"),
227 PINCTRL_PIN(4, "FST_SPI_CS1_B"),
228 PINCTRL_PIN(5, "FST_SPI_D1"),
229 PINCTRL_PIN(6, "FST_SPI_CS0_B"),
230 PINCTRL_PIN(7, "FST_SPI_CS2_B"),
232 PINCTRL_PIN(15, "UART1_RTS_B"),
233 PINCTRL_PIN(16, "UART1_RXD"),
234 PINCTRL_PIN(17, "UART2_RXD"),
235 PINCTRL_PIN(18, "UART1_CTS_B"),
236 PINCTRL_PIN(19, "UART2_RTS_B"),
237 PINCTRL_PIN(20, "UART1_TXD"),
238 PINCTRL_PIN(21, "UART2_TXD"),
239 PINCTRL_PIN(22, "UART2_CTS_B"),
241 PINCTRL_PIN(30, "MF_HDA_CLK"),
242 PINCTRL_PIN(31, "MF_HDA_RSTB"),
243 PINCTRL_PIN(32, "MF_HDA_SDIO"),
244 PINCTRL_PIN(33, "MF_HDA_SDO"),
245 PINCTRL_PIN(34, "MF_HDA_DOCKRSTB"),
246 PINCTRL_PIN(35, "MF_HDA_SYNC"),
247 PINCTRL_PIN(36, "MF_HDA_SDI1"),
248 PINCTRL_PIN(37, "MF_HDA_DOCKENB"),
250 PINCTRL_PIN(45, "I2C5_SDA"),
251 PINCTRL_PIN(46, "I2C4_SDA"),
252 PINCTRL_PIN(47, "I2C6_SDA"),
253 PINCTRL_PIN(48, "I2C5_SCL"),
254 PINCTRL_PIN(49, "I2C_NFC_SDA"),
255 PINCTRL_PIN(50, "I2C4_SCL"),
256 PINCTRL_PIN(51, "I2C6_SCL"),
257 PINCTRL_PIN(52, "I2C_NFC_SCL"),
259 PINCTRL_PIN(60, "I2C1_SDA"),
260 PINCTRL_PIN(61, "I2C0_SDA"),
261 PINCTRL_PIN(62, "I2C2_SDA"),
262 PINCTRL_PIN(63, "I2C1_SCL"),
263 PINCTRL_PIN(64, "I2C3_SDA"),
264 PINCTRL_PIN(65, "I2C0_SCL"),
265 PINCTRL_PIN(66, "I2C2_SCL"),
266 PINCTRL_PIN(67, "I2C3_SCL"),
268 PINCTRL_PIN(75, "SATA_GP0"),
269 PINCTRL_PIN(76, "SATA_GP1"),
270 PINCTRL_PIN(77, "SATA_LEDN"),
271 PINCTRL_PIN(78, "SATA_GP2"),
272 PINCTRL_PIN(79, "MF_SMB_ALERTB"),
273 PINCTRL_PIN(80, "SATA_GP3"),
274 PINCTRL_PIN(81, "MF_SMB_CLK"),
275 PINCTRL_PIN(82, "MF_SMB_DATA"),
277 PINCTRL_PIN(90, "PCIE_CLKREQ0B"),
278 PINCTRL_PIN(91, "PCIE_CLKREQ1B"),
279 PINCTRL_PIN(92, "GP_SSP_2_CLK"),
280 PINCTRL_PIN(93, "PCIE_CLKREQ2B"),
281 PINCTRL_PIN(94, "GP_SSP_2_RXD"),
282 PINCTRL_PIN(95, "PCIE_CLKREQ3B"),
283 PINCTRL_PIN(96, "GP_SSP_2_FS"),
284 PINCTRL_PIN(97, "GP_SSP_2_TXD"),
287 static const unsigned southwest_fspi_pins[] = { 0, 1, 2, 3, 4, 5, 6, 7 };
288 static const unsigned southwest_uart0_pins[] = { 16, 20 };
289 static const unsigned southwest_uart1_pins[] = { 15, 16, 18, 20 };
290 static const unsigned southwest_uart2_pins[] = { 17, 19, 21, 22 };
291 static const unsigned southwest_i2c0_pins[] = { 61, 65 };
292 static const unsigned southwest_hda_pins[] = { 30, 31, 32, 33, 34, 35, 36, 37 };
293 static const unsigned southwest_lpe_pins[] = {
294 30, 31, 32, 33, 34, 35, 36, 37, 92, 94, 96, 97,
296 static const unsigned southwest_i2c1_pins[] = { 60, 63 };
297 static const unsigned southwest_i2c2_pins[] = { 62, 66 };
298 static const unsigned southwest_i2c3_pins[] = { 64, 67 };
299 static const unsigned southwest_i2c4_pins[] = { 46, 50 };
300 static const unsigned southwest_i2c5_pins[] = { 45, 48 };
301 static const unsigned southwest_i2c6_pins[] = { 47, 51 };
302 static const unsigned southwest_i2c_nfc_pins[] = { 49, 52 };
303 static const unsigned southwest_smbus_pins[] = { 79, 81, 82 };
304 static const unsigned southwest_spi3_pins[] = { 76, 79, 80, 81, 82 };
306 /* LPE I2S TXD pins need to have invert_oe set */
307 static const struct chv_alternate_function southwest_lpe_altfuncs[] = {
308 ALTERNATE_FUNCTION(30, 1, true),
309 ALTERNATE_FUNCTION(34, 1, true),
310 ALTERNATE_FUNCTION(97, 1, true),
314 * Two spi3 chipselects are available in different mode than the main spi3
315 * functionality, which is using mode 1.
317 static const struct chv_alternate_function southwest_spi3_altfuncs[] = {
318 ALTERNATE_FUNCTION(76, 3, false),
319 ALTERNATE_FUNCTION(80, 3, false),
322 static const struct chv_pingroup southwest_groups[] = {
323 PIN_GROUP("uart0_grp", southwest_uart0_pins, 2, false),
324 PIN_GROUP("uart1_grp", southwest_uart1_pins, 1, false),
325 PIN_GROUP("uart2_grp", southwest_uart2_pins, 1, false),
326 PIN_GROUP("hda_grp", southwest_hda_pins, 2, false),
327 PIN_GROUP("i2c0_grp", southwest_i2c0_pins, 1, true),
328 PIN_GROUP("i2c1_grp", southwest_i2c1_pins, 1, true),
329 PIN_GROUP("i2c2_grp", southwest_i2c2_pins, 1, true),
330 PIN_GROUP("i2c3_grp", southwest_i2c3_pins, 1, true),
331 PIN_GROUP("i2c4_grp", southwest_i2c4_pins, 1, true),
332 PIN_GROUP("i2c5_grp", southwest_i2c5_pins, 1, true),
333 PIN_GROUP("i2c6_grp", southwest_i2c6_pins, 1, true),
334 PIN_GROUP("i2c_nfc_grp", southwest_i2c_nfc_pins, 2, true),
336 PIN_GROUP_WITH_OVERRIDE("lpe_grp", southwest_lpe_pins, 1, false,
337 southwest_lpe_altfuncs),
338 PIN_GROUP_WITH_OVERRIDE("spi3_grp", southwest_spi3_pins, 2, false,
339 southwest_spi3_altfuncs),
342 static const char * const southwest_uart0_groups[] = { "uart0_grp" };
343 static const char * const southwest_uart1_groups[] = { "uart1_grp" };
344 static const char * const southwest_uart2_groups[] = { "uart2_grp" };
345 static const char * const southwest_hda_groups[] = { "hda_grp" };
346 static const char * const southwest_lpe_groups[] = { "lpe_grp" };
347 static const char * const southwest_i2c0_groups[] = { "i2c0_grp" };
348 static const char * const southwest_i2c1_groups[] = { "i2c1_grp" };
349 static const char * const southwest_i2c2_groups[] = { "i2c2_grp" };
350 static const char * const southwest_i2c3_groups[] = { "i2c3_grp" };
351 static const char * const southwest_i2c4_groups[] = { "i2c4_grp" };
352 static const char * const southwest_i2c5_groups[] = { "i2c5_grp" };
353 static const char * const southwest_i2c6_groups[] = { "i2c6_grp" };
354 static const char * const southwest_i2c_nfc_groups[] = { "i2c_nfc_grp" };
355 static const char * const southwest_spi3_groups[] = { "spi3_grp" };
358 * Only do pinmuxing for certain LPSS devices for now. Rest of the pins are
359 * enabled only as GPIOs.
361 static const struct chv_function southwest_functions[] = {
362 FUNCTION("uart0", southwest_uart0_groups),
363 FUNCTION("uart1", southwest_uart1_groups),
364 FUNCTION("uart2", southwest_uart2_groups),
365 FUNCTION("hda", southwest_hda_groups),
366 FUNCTION("lpe", southwest_lpe_groups),
367 FUNCTION("i2c0", southwest_i2c0_groups),
368 FUNCTION("i2c1", southwest_i2c1_groups),
369 FUNCTION("i2c2", southwest_i2c2_groups),
370 FUNCTION("i2c3", southwest_i2c3_groups),
371 FUNCTION("i2c4", southwest_i2c4_groups),
372 FUNCTION("i2c5", southwest_i2c5_groups),
373 FUNCTION("i2c6", southwest_i2c6_groups),
374 FUNCTION("i2c_nfc", southwest_i2c_nfc_groups),
375 FUNCTION("spi3", southwest_spi3_groups),
378 static const struct chv_gpio_pinrange southwest_gpio_ranges[] = {
380 GPIO_PINRANGE(15, 22),
381 GPIO_PINRANGE(30, 37),
382 GPIO_PINRANGE(45, 52),
383 GPIO_PINRANGE(60, 67),
384 GPIO_PINRANGE(75, 82),
385 GPIO_PINRANGE(90, 97),
388 static const struct chv_community southwest_community = {
390 .pins = southwest_pins,
391 .npins = ARRAY_SIZE(southwest_pins),
392 .groups = southwest_groups,
393 .ngroups = ARRAY_SIZE(southwest_groups),
394 .functions = southwest_functions,
395 .nfunctions = ARRAY_SIZE(southwest_functions),
396 .gpio_ranges = southwest_gpio_ranges,
397 .ngpio_ranges = ARRAY_SIZE(southwest_gpio_ranges),
398 .ngpios = ARRAY_SIZE(southwest_pins),
401 static const struct pinctrl_pin_desc north_pins[] = {
402 PINCTRL_PIN(0, "GPIO_DFX_0"),
403 PINCTRL_PIN(1, "GPIO_DFX_3"),
404 PINCTRL_PIN(2, "GPIO_DFX_7"),
405 PINCTRL_PIN(3, "GPIO_DFX_1"),
406 PINCTRL_PIN(4, "GPIO_DFX_5"),
407 PINCTRL_PIN(5, "GPIO_DFX_4"),
408 PINCTRL_PIN(6, "GPIO_DFX_8"),
409 PINCTRL_PIN(7, "GPIO_DFX_2"),
410 PINCTRL_PIN(8, "GPIO_DFX_6"),
412 PINCTRL_PIN(15, "GPIO_SUS0"),
413 PINCTRL_PIN(16, "SEC_GPIO_SUS10"),
414 PINCTRL_PIN(17, "GPIO_SUS3"),
415 PINCTRL_PIN(18, "GPIO_SUS7"),
416 PINCTRL_PIN(19, "GPIO_SUS1"),
417 PINCTRL_PIN(20, "GPIO_SUS5"),
418 PINCTRL_PIN(21, "SEC_GPIO_SUS11"),
419 PINCTRL_PIN(22, "GPIO_SUS4"),
420 PINCTRL_PIN(23, "SEC_GPIO_SUS8"),
421 PINCTRL_PIN(24, "GPIO_SUS2"),
422 PINCTRL_PIN(25, "GPIO_SUS6"),
423 PINCTRL_PIN(26, "CX_PREQ_B"),
424 PINCTRL_PIN(27, "SEC_GPIO_SUS9"),
426 PINCTRL_PIN(30, "TRST_B"),
427 PINCTRL_PIN(31, "TCK"),
428 PINCTRL_PIN(32, "PROCHOT_B"),
429 PINCTRL_PIN(33, "SVIDO_DATA"),
430 PINCTRL_PIN(34, "TMS"),
431 PINCTRL_PIN(35, "CX_PRDY_B_2"),
432 PINCTRL_PIN(36, "TDO_2"),
433 PINCTRL_PIN(37, "CX_PRDY_B"),
434 PINCTRL_PIN(38, "SVIDO_ALERT_B"),
435 PINCTRL_PIN(39, "TDO"),
436 PINCTRL_PIN(40, "SVIDO_CLK"),
437 PINCTRL_PIN(41, "TDI"),
439 PINCTRL_PIN(45, "GP_CAMERASB_05"),
440 PINCTRL_PIN(46, "GP_CAMERASB_02"),
441 PINCTRL_PIN(47, "GP_CAMERASB_08"),
442 PINCTRL_PIN(48, "GP_CAMERASB_00"),
443 PINCTRL_PIN(49, "GP_CAMERASB_06"),
444 PINCTRL_PIN(50, "GP_CAMERASB_10"),
445 PINCTRL_PIN(51, "GP_CAMERASB_03"),
446 PINCTRL_PIN(52, "GP_CAMERASB_09"),
447 PINCTRL_PIN(53, "GP_CAMERASB_01"),
448 PINCTRL_PIN(54, "GP_CAMERASB_07"),
449 PINCTRL_PIN(55, "GP_CAMERASB_11"),
450 PINCTRL_PIN(56, "GP_CAMERASB_04"),
452 PINCTRL_PIN(60, "PANEL0_BKLTEN"),
453 PINCTRL_PIN(61, "HV_DDI0_HPD"),
454 PINCTRL_PIN(62, "HV_DDI2_DDC_SDA"),
455 PINCTRL_PIN(63, "PANEL1_BKLTCTL"),
456 PINCTRL_PIN(64, "HV_DDI1_HPD"),
457 PINCTRL_PIN(65, "PANEL0_BKLTCTL"),
458 PINCTRL_PIN(66, "HV_DDI0_DDC_SDA"),
459 PINCTRL_PIN(67, "HV_DDI2_DDC_SCL"),
460 PINCTRL_PIN(68, "HV_DDI2_HPD"),
461 PINCTRL_PIN(69, "PANEL1_VDDEN"),
462 PINCTRL_PIN(70, "PANEL1_BKLTEN"),
463 PINCTRL_PIN(71, "HV_DDI0_DDC_SCL"),
464 PINCTRL_PIN(72, "PANEL0_VDDEN"),
467 static const struct chv_gpio_pinrange north_gpio_ranges[] = {
469 GPIO_PINRANGE(15, 27),
470 GPIO_PINRANGE(30, 41),
471 GPIO_PINRANGE(45, 56),
472 GPIO_PINRANGE(60, 72),
475 static const struct chv_community north_community = {
478 .npins = ARRAY_SIZE(north_pins),
479 .gpio_ranges = north_gpio_ranges,
480 .ngpio_ranges = ARRAY_SIZE(north_gpio_ranges),
481 .ngpios = ARRAY_SIZE(north_pins),
484 static const struct pinctrl_pin_desc east_pins[] = {
485 PINCTRL_PIN(0, "PMU_SLP_S3_B"),
486 PINCTRL_PIN(1, "PMU_BATLOW_B"),
487 PINCTRL_PIN(2, "SUS_STAT_B"),
488 PINCTRL_PIN(3, "PMU_SLP_S0IX_B"),
489 PINCTRL_PIN(4, "PMU_AC_PRESENT"),
490 PINCTRL_PIN(5, "PMU_PLTRST_B"),
491 PINCTRL_PIN(6, "PMU_SUSCLK"),
492 PINCTRL_PIN(7, "PMU_SLP_LAN_B"),
493 PINCTRL_PIN(8, "PMU_PWRBTN_B"),
494 PINCTRL_PIN(9, "PMU_SLP_S4_B"),
495 PINCTRL_PIN(10, "PMU_WAKE_B"),
496 PINCTRL_PIN(11, "PMU_WAKE_LAN_B"),
498 PINCTRL_PIN(15, "MF_ISH_GPIO_3"),
499 PINCTRL_PIN(16, "MF_ISH_GPIO_7"),
500 PINCTRL_PIN(17, "MF_ISH_I2C1_SCL"),
501 PINCTRL_PIN(18, "MF_ISH_GPIO_1"),
502 PINCTRL_PIN(19, "MF_ISH_GPIO_5"),
503 PINCTRL_PIN(20, "MF_ISH_GPIO_9"),
504 PINCTRL_PIN(21, "MF_ISH_GPIO_0"),
505 PINCTRL_PIN(22, "MF_ISH_GPIO_4"),
506 PINCTRL_PIN(23, "MF_ISH_GPIO_8"),
507 PINCTRL_PIN(24, "MF_ISH_GPIO_2"),
508 PINCTRL_PIN(25, "MF_ISH_GPIO_6"),
509 PINCTRL_PIN(26, "MF_ISH_I2C1_SDA"),
512 static const struct chv_gpio_pinrange east_gpio_ranges[] = {
513 GPIO_PINRANGE(0, 11),
514 GPIO_PINRANGE(15, 26),
517 static const struct chv_community east_community = {
520 .npins = ARRAY_SIZE(east_pins),
521 .gpio_ranges = east_gpio_ranges,
522 .ngpio_ranges = ARRAY_SIZE(east_gpio_ranges),
523 .ngpios = ARRAY_SIZE(east_pins),
526 static const struct pinctrl_pin_desc southeast_pins[] = {
527 PINCTRL_PIN(0, "MF_PLT_CLK0"),
528 PINCTRL_PIN(1, "PWM1"),
529 PINCTRL_PIN(2, "MF_PLT_CLK1"),
530 PINCTRL_PIN(3, "MF_PLT_CLK4"),
531 PINCTRL_PIN(4, "MF_PLT_CLK3"),
532 PINCTRL_PIN(5, "PWM0"),
533 PINCTRL_PIN(6, "MF_PLT_CLK5"),
534 PINCTRL_PIN(7, "MF_PLT_CLK2"),
536 PINCTRL_PIN(15, "SDMMC2_D3_CD_B"),
537 PINCTRL_PIN(16, "SDMMC1_CLK"),
538 PINCTRL_PIN(17, "SDMMC1_D0"),
539 PINCTRL_PIN(18, "SDMMC2_D1"),
540 PINCTRL_PIN(19, "SDMMC2_CLK"),
541 PINCTRL_PIN(20, "SDMMC1_D2"),
542 PINCTRL_PIN(21, "SDMMC2_D2"),
543 PINCTRL_PIN(22, "SDMMC2_CMD"),
544 PINCTRL_PIN(23, "SDMMC1_CMD"),
545 PINCTRL_PIN(24, "SDMMC1_D1"),
546 PINCTRL_PIN(25, "SDMMC2_D0"),
547 PINCTRL_PIN(26, "SDMMC1_D3_CD_B"),
549 PINCTRL_PIN(30, "SDMMC3_D1"),
550 PINCTRL_PIN(31, "SDMMC3_CLK"),
551 PINCTRL_PIN(32, "SDMMC3_D3"),
552 PINCTRL_PIN(33, "SDMMC3_D2"),
553 PINCTRL_PIN(34, "SDMMC3_CMD"),
554 PINCTRL_PIN(35, "SDMMC3_D0"),
556 PINCTRL_PIN(45, "MF_LPC_AD2"),
557 PINCTRL_PIN(46, "LPC_CLKRUNB"),
558 PINCTRL_PIN(47, "MF_LPC_AD0"),
559 PINCTRL_PIN(48, "LPC_FRAMEB"),
560 PINCTRL_PIN(49, "MF_LPC_CLKOUT1"),
561 PINCTRL_PIN(50, "MF_LPC_AD3"),
562 PINCTRL_PIN(51, "MF_LPC_CLKOUT0"),
563 PINCTRL_PIN(52, "MF_LPC_AD1"),
565 PINCTRL_PIN(60, "SPI1_MISO"),
566 PINCTRL_PIN(61, "SPI1_CSO_B"),
567 PINCTRL_PIN(62, "SPI1_CLK"),
568 PINCTRL_PIN(63, "MMC1_D6"),
569 PINCTRL_PIN(64, "SPI1_MOSI"),
570 PINCTRL_PIN(65, "MMC1_D5"),
571 PINCTRL_PIN(66, "SPI1_CS1_B"),
572 PINCTRL_PIN(67, "MMC1_D4_SD_WE"),
573 PINCTRL_PIN(68, "MMC1_D7"),
574 PINCTRL_PIN(69, "MMC1_RCLK"),
576 PINCTRL_PIN(75, "USB_OC1_B"),
577 PINCTRL_PIN(76, "PMU_RESETBUTTON_B"),
578 PINCTRL_PIN(77, "GPIO_ALERT"),
579 PINCTRL_PIN(78, "SDMMC3_PWR_EN_B"),
580 PINCTRL_PIN(79, "ILB_SERIRQ"),
581 PINCTRL_PIN(80, "USB_OC0_B"),
582 PINCTRL_PIN(81, "SDMMC3_CD_B"),
583 PINCTRL_PIN(82, "SPKR"),
584 PINCTRL_PIN(83, "SUSPWRDNACK"),
585 PINCTRL_PIN(84, "SPARE_PIN"),
586 PINCTRL_PIN(85, "SDMMC3_1P8_EN"),
589 static const unsigned southeast_pwm0_pins[] = { 5 };
590 static const unsigned southeast_pwm1_pins[] = { 1 };
591 static const unsigned southeast_sdmmc1_pins[] = {
592 16, 17, 20, 23, 24, 26, 63, 65, 67, 68, 69,
594 static const unsigned southeast_sdmmc2_pins[] = { 15, 18, 19, 21, 22, 25 };
595 static const unsigned southeast_sdmmc3_pins[] = {
596 30, 31, 32, 33, 34, 35, 78, 81, 85,
598 static const unsigned southeast_spi1_pins[] = { 60, 61, 62, 64, 66 };
599 static const unsigned southeast_spi2_pins[] = { 2, 3, 4, 6, 7 };
601 static const struct chv_pingroup southeast_groups[] = {
602 PIN_GROUP("pwm0_grp", southeast_pwm0_pins, 1, false),
603 PIN_GROUP("pwm1_grp", southeast_pwm1_pins, 1, false),
604 PIN_GROUP("sdmmc1_grp", southeast_sdmmc1_pins, 1, false),
605 PIN_GROUP("sdmmc2_grp", southeast_sdmmc2_pins, 1, false),
606 PIN_GROUP("sdmmc3_grp", southeast_sdmmc3_pins, 1, false),
607 PIN_GROUP("spi1_grp", southeast_spi1_pins, 1, false),
608 PIN_GROUP("spi2_grp", southeast_spi2_pins, 4, false),
611 static const char * const southeast_pwm0_groups[] = { "pwm0_grp" };
612 static const char * const southeast_pwm1_groups[] = { "pwm1_grp" };
613 static const char * const southeast_sdmmc1_groups[] = { "sdmmc1_grp" };
614 static const char * const southeast_sdmmc2_groups[] = { "sdmmc2_grp" };
615 static const char * const southeast_sdmmc3_groups[] = { "sdmmc3_grp" };
616 static const char * const southeast_spi1_groups[] = { "spi1_grp" };
617 static const char * const southeast_spi2_groups[] = { "spi2_grp" };
619 static const struct chv_function southeast_functions[] = {
620 FUNCTION("pwm0", southeast_pwm0_groups),
621 FUNCTION("pwm1", southeast_pwm1_groups),
622 FUNCTION("sdmmc1", southeast_sdmmc1_groups),
623 FUNCTION("sdmmc2", southeast_sdmmc2_groups),
624 FUNCTION("sdmmc3", southeast_sdmmc3_groups),
625 FUNCTION("spi1", southeast_spi1_groups),
626 FUNCTION("spi2", southeast_spi2_groups),
629 static const struct chv_gpio_pinrange southeast_gpio_ranges[] = {
631 GPIO_PINRANGE(15, 26),
632 GPIO_PINRANGE(30, 35),
633 GPIO_PINRANGE(45, 52),
634 GPIO_PINRANGE(60, 69),
635 GPIO_PINRANGE(75, 85),
638 static const struct chv_community southeast_community = {
640 .pins = southeast_pins,
641 .npins = ARRAY_SIZE(southeast_pins),
642 .groups = southeast_groups,
643 .ngroups = ARRAY_SIZE(southeast_groups),
644 .functions = southeast_functions,
645 .nfunctions = ARRAY_SIZE(southeast_functions),
646 .gpio_ranges = southeast_gpio_ranges,
647 .ngpio_ranges = ARRAY_SIZE(southeast_gpio_ranges),
648 .ngpios = ARRAY_SIZE(southeast_pins),
651 static const struct chv_community *chv_communities[] = {
652 &southwest_community,
655 &southeast_community,
659 * Lock to serialize register accesses
661 * Due to a silicon issue, a shared lock must be used to prevent
662 * concurrent accesses across the 4 GPIO controllers.
664 * See Intel Atom Z8000 Processor Series Specification Update (Rev. 005),
665 * errata #CHT34, for further information.
667 static DEFINE_RAW_SPINLOCK(chv_lock);
669 static void __iomem *chv_padreg(struct chv_pinctrl *pctrl, unsigned offset,
672 unsigned family_no = offset / MAX_FAMILY_PAD_GPIO_NO;
673 unsigned pad_no = offset % MAX_FAMILY_PAD_GPIO_NO;
675 offset = FAMILY_PAD_REGS_OFF + FAMILY_PAD_REGS_SIZE * family_no +
676 GPIO_REGS_SIZE * pad_no;
678 return pctrl->regs + offset + reg;
681 static void chv_writel(u32 value, void __iomem *reg)
684 /* simple readback to confirm the bus transferring done */
688 /* When Pad Cfg is locked, driver can only change GPIOTXState or GPIORXState */
689 static bool chv_pad_locked(struct chv_pinctrl *pctrl, unsigned offset)
693 reg = chv_padreg(pctrl, offset, CHV_PADCTRL1);
694 return readl(reg) & CHV_PADCTRL1_CFGLOCK;
697 static int chv_get_groups_count(struct pinctrl_dev *pctldev)
699 struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
701 return pctrl->community->ngroups;
704 static const char *chv_get_group_name(struct pinctrl_dev *pctldev,
707 struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
709 return pctrl->community->groups[group].name;
712 static int chv_get_group_pins(struct pinctrl_dev *pctldev, unsigned group,
713 const unsigned **pins, unsigned *npins)
715 struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
717 *pins = pctrl->community->groups[group].pins;
718 *npins = pctrl->community->groups[group].npins;
722 static void chv_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
725 struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
730 raw_spin_lock_irqsave(&chv_lock, flags);
732 ctrl0 = readl(chv_padreg(pctrl, offset, CHV_PADCTRL0));
733 ctrl1 = readl(chv_padreg(pctrl, offset, CHV_PADCTRL1));
734 locked = chv_pad_locked(pctrl, offset);
736 raw_spin_unlock_irqrestore(&chv_lock, flags);
738 if (ctrl0 & CHV_PADCTRL0_GPIOEN) {
739 seq_puts(s, "GPIO ");
743 mode = ctrl0 & CHV_PADCTRL0_PMODE_MASK;
744 mode >>= CHV_PADCTRL0_PMODE_SHIFT;
746 seq_printf(s, "mode %d ", mode);
749 seq_printf(s, "ctrl0 0x%08x ctrl1 0x%08x", ctrl0, ctrl1);
752 seq_puts(s, " [LOCKED]");
755 static const struct pinctrl_ops chv_pinctrl_ops = {
756 .get_groups_count = chv_get_groups_count,
757 .get_group_name = chv_get_group_name,
758 .get_group_pins = chv_get_group_pins,
759 .pin_dbg_show = chv_pin_dbg_show,
762 static int chv_get_functions_count(struct pinctrl_dev *pctldev)
764 struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
766 return pctrl->community->nfunctions;
769 static const char *chv_get_function_name(struct pinctrl_dev *pctldev,
772 struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
774 return pctrl->community->functions[function].name;
777 static int chv_get_function_groups(struct pinctrl_dev *pctldev,
779 const char * const **groups,
780 unsigned * const ngroups)
782 struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
784 *groups = pctrl->community->functions[function].groups;
785 *ngroups = pctrl->community->functions[function].ngroups;
789 static int chv_pinmux_set_mux(struct pinctrl_dev *pctldev, unsigned function,
792 struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
793 const struct chv_pingroup *grp;
797 grp = &pctrl->community->groups[group];
799 raw_spin_lock_irqsave(&chv_lock, flags);
801 /* Check first that the pad is not locked */
802 for (i = 0; i < grp->npins; i++) {
803 if (chv_pad_locked(pctrl, grp->pins[i])) {
804 dev_warn(pctrl->dev, "unable to set mode for locked pin %u\n",
806 raw_spin_unlock_irqrestore(&chv_lock, flags);
811 for (i = 0; i < grp->npins; i++) {
812 const struct chv_alternate_function *altfunc = &grp->altfunc;
813 int pin = grp->pins[i];
817 /* Check if there is pin-specific config */
818 if (grp->overrides) {
821 for (j = 0; j < grp->noverrides; j++) {
822 if (grp->overrides[j].pin == pin) {
823 altfunc = &grp->overrides[j];
829 reg = chv_padreg(pctrl, pin, CHV_PADCTRL0);
831 /* Disable GPIO mode */
832 value &= ~CHV_PADCTRL0_GPIOEN;
833 /* Set to desired mode */
834 value &= ~CHV_PADCTRL0_PMODE_MASK;
835 value |= altfunc->mode << CHV_PADCTRL0_PMODE_SHIFT;
836 chv_writel(value, reg);
838 /* Update for invert_oe */
839 reg = chv_padreg(pctrl, pin, CHV_PADCTRL1);
840 value = readl(reg) & ~CHV_PADCTRL1_INVRXTX_MASK;
841 if (altfunc->invert_oe)
842 value |= CHV_PADCTRL1_INVRXTX_TXENABLE;
843 chv_writel(value, reg);
845 dev_dbg(pctrl->dev, "configured pin %u mode %u OE %sinverted\n",
846 pin, altfunc->mode, altfunc->invert_oe ? "" : "not ");
849 raw_spin_unlock_irqrestore(&chv_lock, flags);
854 static int chv_gpio_request_enable(struct pinctrl_dev *pctldev,
855 struct pinctrl_gpio_range *range,
858 struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
863 raw_spin_lock_irqsave(&chv_lock, flags);
865 if (chv_pad_locked(pctrl, offset)) {
866 value = readl(chv_padreg(pctrl, offset, CHV_PADCTRL0));
867 if (!(value & CHV_PADCTRL0_GPIOEN)) {
868 /* Locked so cannot enable */
869 raw_spin_unlock_irqrestore(&chv_lock, flags);
875 /* Reset the interrupt mapping */
876 for (i = 0; i < ARRAY_SIZE(pctrl->intr_lines); i++) {
877 if (pctrl->intr_lines[i] == offset) {
878 pctrl->intr_lines[i] = 0;
883 /* Disable interrupt generation */
884 reg = chv_padreg(pctrl, offset, CHV_PADCTRL1);
886 value &= ~CHV_PADCTRL1_INTWAKECFG_MASK;
887 value &= ~CHV_PADCTRL1_INVRXTX_MASK;
888 chv_writel(value, reg);
890 reg = chv_padreg(pctrl, offset, CHV_PADCTRL0);
894 * If the pin is in HiZ mode (both TX and RX buffers are
895 * disabled) we turn it to be input now.
897 if ((value & CHV_PADCTRL0_GPIOCFG_MASK) ==
898 (CHV_PADCTRL0_GPIOCFG_HIZ << CHV_PADCTRL0_GPIOCFG_SHIFT)) {
899 value &= ~CHV_PADCTRL0_GPIOCFG_MASK;
900 value |= CHV_PADCTRL0_GPIOCFG_GPI <<
901 CHV_PADCTRL0_GPIOCFG_SHIFT;
904 /* Switch to a GPIO mode */
905 value |= CHV_PADCTRL0_GPIOEN;
906 chv_writel(value, reg);
909 raw_spin_unlock_irqrestore(&chv_lock, flags);
914 static void chv_gpio_disable_free(struct pinctrl_dev *pctldev,
915 struct pinctrl_gpio_range *range,
918 struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
923 raw_spin_lock_irqsave(&chv_lock, flags);
925 reg = chv_padreg(pctrl, offset, CHV_PADCTRL0);
926 value = readl(reg) & ~CHV_PADCTRL0_GPIOEN;
927 chv_writel(value, reg);
929 raw_spin_unlock_irqrestore(&chv_lock, flags);
932 static int chv_gpio_set_direction(struct pinctrl_dev *pctldev,
933 struct pinctrl_gpio_range *range,
934 unsigned offset, bool input)
936 struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
937 void __iomem *reg = chv_padreg(pctrl, offset, CHV_PADCTRL0);
941 raw_spin_lock_irqsave(&chv_lock, flags);
943 ctrl0 = readl(reg) & ~CHV_PADCTRL0_GPIOCFG_MASK;
945 ctrl0 |= CHV_PADCTRL0_GPIOCFG_GPI << CHV_PADCTRL0_GPIOCFG_SHIFT;
947 ctrl0 |= CHV_PADCTRL0_GPIOCFG_GPO << CHV_PADCTRL0_GPIOCFG_SHIFT;
948 chv_writel(ctrl0, reg);
950 raw_spin_unlock_irqrestore(&chv_lock, flags);
955 static const struct pinmux_ops chv_pinmux_ops = {
956 .get_functions_count = chv_get_functions_count,
957 .get_function_name = chv_get_function_name,
958 .get_function_groups = chv_get_function_groups,
959 .set_mux = chv_pinmux_set_mux,
960 .gpio_request_enable = chv_gpio_request_enable,
961 .gpio_disable_free = chv_gpio_disable_free,
962 .gpio_set_direction = chv_gpio_set_direction,
965 static int chv_config_get(struct pinctrl_dev *pctldev, unsigned pin,
966 unsigned long *config)
968 struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
969 enum pin_config_param param = pinconf_to_config_param(*config);
975 raw_spin_lock_irqsave(&chv_lock, flags);
976 ctrl0 = readl(chv_padreg(pctrl, pin, CHV_PADCTRL0));
977 ctrl1 = readl(chv_padreg(pctrl, pin, CHV_PADCTRL1));
978 raw_spin_unlock_irqrestore(&chv_lock, flags);
980 term = (ctrl0 & CHV_PADCTRL0_TERM_MASK) >> CHV_PADCTRL0_TERM_SHIFT;
983 case PIN_CONFIG_BIAS_DISABLE:
988 case PIN_CONFIG_BIAS_PULL_UP:
989 if (!(ctrl0 & CHV_PADCTRL0_TERM_UP))
993 case CHV_PADCTRL0_TERM_20K:
996 case CHV_PADCTRL0_TERM_5K:
999 case CHV_PADCTRL0_TERM_1K:
1006 case PIN_CONFIG_BIAS_PULL_DOWN:
1007 if (!term || (ctrl0 & CHV_PADCTRL0_TERM_UP))
1011 case CHV_PADCTRL0_TERM_20K:
1014 case CHV_PADCTRL0_TERM_5K:
1021 case PIN_CONFIG_DRIVE_OPEN_DRAIN:
1022 if (!(ctrl1 & CHV_PADCTRL1_ODEN))
1026 case PIN_CONFIG_BIAS_HIGH_IMPEDANCE: {
1029 cfg = ctrl0 & CHV_PADCTRL0_GPIOCFG_MASK;
1030 cfg >>= CHV_PADCTRL0_GPIOCFG_SHIFT;
1031 if (cfg != CHV_PADCTRL0_GPIOCFG_HIZ)
1041 *config = pinconf_to_config_packed(param, arg);
1045 static int chv_config_set_pull(struct chv_pinctrl *pctrl, unsigned pin,
1046 enum pin_config_param param, u16 arg)
1048 void __iomem *reg = chv_padreg(pctrl, pin, CHV_PADCTRL0);
1049 unsigned long flags;
1052 raw_spin_lock_irqsave(&chv_lock, flags);
1056 case PIN_CONFIG_BIAS_DISABLE:
1057 ctrl0 &= ~(CHV_PADCTRL0_TERM_MASK | CHV_PADCTRL0_TERM_UP);
1060 case PIN_CONFIG_BIAS_PULL_UP:
1061 ctrl0 &= ~(CHV_PADCTRL0_TERM_MASK | CHV_PADCTRL0_TERM_UP);
1065 /* For 1k there is only pull up */
1066 pull = CHV_PADCTRL0_TERM_1K << CHV_PADCTRL0_TERM_SHIFT;
1069 pull = CHV_PADCTRL0_TERM_5K << CHV_PADCTRL0_TERM_SHIFT;
1072 pull = CHV_PADCTRL0_TERM_20K << CHV_PADCTRL0_TERM_SHIFT;
1075 raw_spin_unlock_irqrestore(&chv_lock, flags);
1079 ctrl0 |= CHV_PADCTRL0_TERM_UP | pull;
1082 case PIN_CONFIG_BIAS_PULL_DOWN:
1083 ctrl0 &= ~(CHV_PADCTRL0_TERM_MASK | CHV_PADCTRL0_TERM_UP);
1087 pull = CHV_PADCTRL0_TERM_5K << CHV_PADCTRL0_TERM_SHIFT;
1090 pull = CHV_PADCTRL0_TERM_20K << CHV_PADCTRL0_TERM_SHIFT;
1093 raw_spin_unlock_irqrestore(&chv_lock, flags);
1101 raw_spin_unlock_irqrestore(&chv_lock, flags);
1105 chv_writel(ctrl0, reg);
1106 raw_spin_unlock_irqrestore(&chv_lock, flags);
1111 static int chv_config_set_oden(struct chv_pinctrl *pctrl, unsigned int pin,
1114 void __iomem *reg = chv_padreg(pctrl, pin, CHV_PADCTRL1);
1115 unsigned long flags;
1118 raw_spin_lock_irqsave(&chv_lock, flags);
1122 ctrl1 |= CHV_PADCTRL1_ODEN;
1124 ctrl1 &= ~CHV_PADCTRL1_ODEN;
1126 chv_writel(ctrl1, reg);
1127 raw_spin_unlock_irqrestore(&chv_lock, flags);
1132 static int chv_config_set(struct pinctrl_dev *pctldev, unsigned pin,
1133 unsigned long *configs, unsigned nconfigs)
1135 struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
1136 enum pin_config_param param;
1140 if (chv_pad_locked(pctrl, pin))
1143 for (i = 0; i < nconfigs; i++) {
1144 param = pinconf_to_config_param(configs[i]);
1145 arg = pinconf_to_config_argument(configs[i]);
1148 case PIN_CONFIG_BIAS_DISABLE:
1149 case PIN_CONFIG_BIAS_PULL_UP:
1150 case PIN_CONFIG_BIAS_PULL_DOWN:
1151 ret = chv_config_set_pull(pctrl, pin, param, arg);
1156 case PIN_CONFIG_DRIVE_PUSH_PULL:
1157 ret = chv_config_set_oden(pctrl, pin, false);
1162 case PIN_CONFIG_DRIVE_OPEN_DRAIN:
1163 ret = chv_config_set_oden(pctrl, pin, true);
1172 dev_dbg(pctrl->dev, "pin %d set config %d arg %u\n", pin,
1179 static int chv_config_group_get(struct pinctrl_dev *pctldev,
1181 unsigned long *config)
1183 const unsigned int *pins;
1187 ret = chv_get_group_pins(pctldev, group, &pins, &npins);
1191 ret = chv_config_get(pctldev, pins[0], config);
1198 static int chv_config_group_set(struct pinctrl_dev *pctldev,
1199 unsigned int group, unsigned long *configs,
1200 unsigned int num_configs)
1202 const unsigned int *pins;
1206 ret = chv_get_group_pins(pctldev, group, &pins, &npins);
1210 for (i = 0; i < npins; i++) {
1211 ret = chv_config_set(pctldev, pins[i], configs, num_configs);
1219 static const struct pinconf_ops chv_pinconf_ops = {
1221 .pin_config_set = chv_config_set,
1222 .pin_config_get = chv_config_get,
1223 .pin_config_group_get = chv_config_group_get,
1224 .pin_config_group_set = chv_config_group_set,
1227 static struct pinctrl_desc chv_pinctrl_desc = {
1228 .pctlops = &chv_pinctrl_ops,
1229 .pmxops = &chv_pinmux_ops,
1230 .confops = &chv_pinconf_ops,
1231 .owner = THIS_MODULE,
1234 static unsigned chv_gpio_offset_to_pin(struct chv_pinctrl *pctrl,
1237 return pctrl->community->pins[offset].number;
1240 static int chv_gpio_get(struct gpio_chip *chip, unsigned offset)
1242 struct chv_pinctrl *pctrl = gpiochip_get_data(chip);
1243 int pin = chv_gpio_offset_to_pin(pctrl, offset);
1244 unsigned long flags;
1247 raw_spin_lock_irqsave(&chv_lock, flags);
1248 ctrl0 = readl(chv_padreg(pctrl, pin, CHV_PADCTRL0));
1249 raw_spin_unlock_irqrestore(&chv_lock, flags);
1251 cfg = ctrl0 & CHV_PADCTRL0_GPIOCFG_MASK;
1252 cfg >>= CHV_PADCTRL0_GPIOCFG_SHIFT;
1254 if (cfg == CHV_PADCTRL0_GPIOCFG_GPO)
1255 return !!(ctrl0 & CHV_PADCTRL0_GPIOTXSTATE);
1256 return !!(ctrl0 & CHV_PADCTRL0_GPIORXSTATE);
1259 static void chv_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
1261 struct chv_pinctrl *pctrl = gpiochip_get_data(chip);
1262 unsigned pin = chv_gpio_offset_to_pin(pctrl, offset);
1263 unsigned long flags;
1267 raw_spin_lock_irqsave(&chv_lock, flags);
1269 reg = chv_padreg(pctrl, pin, CHV_PADCTRL0);
1273 ctrl0 |= CHV_PADCTRL0_GPIOTXSTATE;
1275 ctrl0 &= ~CHV_PADCTRL0_GPIOTXSTATE;
1277 chv_writel(ctrl0, reg);
1279 raw_spin_unlock_irqrestore(&chv_lock, flags);
1282 static int chv_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
1284 struct chv_pinctrl *pctrl = gpiochip_get_data(chip);
1285 unsigned pin = chv_gpio_offset_to_pin(pctrl, offset);
1286 u32 ctrl0, direction;
1287 unsigned long flags;
1289 raw_spin_lock_irqsave(&chv_lock, flags);
1290 ctrl0 = readl(chv_padreg(pctrl, pin, CHV_PADCTRL0));
1291 raw_spin_unlock_irqrestore(&chv_lock, flags);
1293 direction = ctrl0 & CHV_PADCTRL0_GPIOCFG_MASK;
1294 direction >>= CHV_PADCTRL0_GPIOCFG_SHIFT;
1296 return direction != CHV_PADCTRL0_GPIOCFG_GPO;
1299 static int chv_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
1301 return pinctrl_gpio_direction_input(chip->base + offset);
1304 static int chv_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
1307 chv_gpio_set(chip, offset, value);
1308 return pinctrl_gpio_direction_output(chip->base + offset);
1311 static const struct gpio_chip chv_gpio_chip = {
1312 .owner = THIS_MODULE,
1313 .request = gpiochip_generic_request,
1314 .free = gpiochip_generic_free,
1315 .get_direction = chv_gpio_get_direction,
1316 .direction_input = chv_gpio_direction_input,
1317 .direction_output = chv_gpio_direction_output,
1318 .get = chv_gpio_get,
1319 .set = chv_gpio_set,
1322 static void chv_gpio_irq_ack(struct irq_data *d)
1324 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1325 struct chv_pinctrl *pctrl = gpiochip_get_data(gc);
1326 int pin = chv_gpio_offset_to_pin(pctrl, irqd_to_hwirq(d));
1329 raw_spin_lock(&chv_lock);
1331 intr_line = readl(chv_padreg(pctrl, pin, CHV_PADCTRL0));
1332 intr_line &= CHV_PADCTRL0_INTSEL_MASK;
1333 intr_line >>= CHV_PADCTRL0_INTSEL_SHIFT;
1334 chv_writel(BIT(intr_line), pctrl->regs + CHV_INTSTAT);
1336 raw_spin_unlock(&chv_lock);
1339 static void chv_gpio_irq_mask_unmask(struct irq_data *d, bool mask)
1341 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1342 struct chv_pinctrl *pctrl = gpiochip_get_data(gc);
1343 int pin = chv_gpio_offset_to_pin(pctrl, irqd_to_hwirq(d));
1344 u32 value, intr_line;
1345 unsigned long flags;
1347 raw_spin_lock_irqsave(&chv_lock, flags);
1349 intr_line = readl(chv_padreg(pctrl, pin, CHV_PADCTRL0));
1350 intr_line &= CHV_PADCTRL0_INTSEL_MASK;
1351 intr_line >>= CHV_PADCTRL0_INTSEL_SHIFT;
1353 value = readl(pctrl->regs + CHV_INTMASK);
1355 value &= ~BIT(intr_line);
1357 value |= BIT(intr_line);
1358 chv_writel(value, pctrl->regs + CHV_INTMASK);
1360 raw_spin_unlock_irqrestore(&chv_lock, flags);
1363 static void chv_gpio_irq_mask(struct irq_data *d)
1365 chv_gpio_irq_mask_unmask(d, true);
1368 static void chv_gpio_irq_unmask(struct irq_data *d)
1370 chv_gpio_irq_mask_unmask(d, false);
1373 static unsigned chv_gpio_irq_startup(struct irq_data *d)
1376 * Check if the interrupt has been requested with 0 as triggering
1377 * type. In that case it is assumed that the current values
1378 * programmed to the hardware are used (e.g BIOS configured
1381 * In that case ->irq_set_type() will never be called so we need to
1382 * read back the values from hardware now, set correct flow handler
1383 * and update mappings before the interrupt is being used.
1385 if (irqd_get_trigger_type(d) == IRQ_TYPE_NONE) {
1386 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1387 struct chv_pinctrl *pctrl = gpiochip_get_data(gc);
1388 unsigned offset = irqd_to_hwirq(d);
1389 int pin = chv_gpio_offset_to_pin(pctrl, offset);
1390 irq_flow_handler_t handler;
1391 unsigned long flags;
1394 raw_spin_lock_irqsave(&chv_lock, flags);
1395 intsel = readl(chv_padreg(pctrl, pin, CHV_PADCTRL0));
1396 intsel &= CHV_PADCTRL0_INTSEL_MASK;
1397 intsel >>= CHV_PADCTRL0_INTSEL_SHIFT;
1399 value = readl(chv_padreg(pctrl, pin, CHV_PADCTRL1));
1400 if (value & CHV_PADCTRL1_INTWAKECFG_LEVEL)
1401 handler = handle_level_irq;
1403 handler = handle_edge_irq;
1405 if (!pctrl->intr_lines[intsel]) {
1406 irq_set_handler_locked(d, handler);
1407 pctrl->intr_lines[intsel] = offset;
1409 raw_spin_unlock_irqrestore(&chv_lock, flags);
1412 chv_gpio_irq_unmask(d);
1416 static int chv_gpio_irq_type(struct irq_data *d, unsigned type)
1418 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1419 struct chv_pinctrl *pctrl = gpiochip_get_data(gc);
1420 unsigned offset = irqd_to_hwirq(d);
1421 int pin = chv_gpio_offset_to_pin(pctrl, offset);
1422 unsigned long flags;
1425 raw_spin_lock_irqsave(&chv_lock, flags);
1428 * Pins which can be used as shared interrupt are configured in
1429 * BIOS. Driver trusts BIOS configurations and assigns different
1430 * handler according to the irq type.
1432 * Driver needs to save the mapping between each pin and
1433 * its interrupt line.
1434 * 1. If the pin cfg is locked in BIOS:
1435 * Trust BIOS has programmed IntWakeCfg bits correctly,
1436 * driver just needs to save the mapping.
1437 * 2. If the pin cfg is not locked in BIOS:
1438 * Driver programs the IntWakeCfg bits and save the mapping.
1440 if (!chv_pad_locked(pctrl, pin)) {
1441 void __iomem *reg = chv_padreg(pctrl, pin, CHV_PADCTRL1);
1444 value &= ~CHV_PADCTRL1_INTWAKECFG_MASK;
1445 value &= ~CHV_PADCTRL1_INVRXTX_MASK;
1447 if (type & IRQ_TYPE_EDGE_BOTH) {
1448 if ((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH)
1449 value |= CHV_PADCTRL1_INTWAKECFG_BOTH;
1450 else if (type & IRQ_TYPE_EDGE_RISING)
1451 value |= CHV_PADCTRL1_INTWAKECFG_RISING;
1452 else if (type & IRQ_TYPE_EDGE_FALLING)
1453 value |= CHV_PADCTRL1_INTWAKECFG_FALLING;
1454 } else if (type & IRQ_TYPE_LEVEL_MASK) {
1455 value |= CHV_PADCTRL1_INTWAKECFG_LEVEL;
1456 if (type & IRQ_TYPE_LEVEL_LOW)
1457 value |= CHV_PADCTRL1_INVRXTX_RXDATA;
1460 chv_writel(value, reg);
1463 value = readl(chv_padreg(pctrl, pin, CHV_PADCTRL0));
1464 value &= CHV_PADCTRL0_INTSEL_MASK;
1465 value >>= CHV_PADCTRL0_INTSEL_SHIFT;
1467 pctrl->intr_lines[value] = offset;
1469 if (type & IRQ_TYPE_EDGE_BOTH)
1470 irq_set_handler_locked(d, handle_edge_irq);
1471 else if (type & IRQ_TYPE_LEVEL_MASK)
1472 irq_set_handler_locked(d, handle_level_irq);
1474 raw_spin_unlock_irqrestore(&chv_lock, flags);
1479 static struct irq_chip chv_gpio_irqchip = {
1481 .irq_startup = chv_gpio_irq_startup,
1482 .irq_ack = chv_gpio_irq_ack,
1483 .irq_mask = chv_gpio_irq_mask,
1484 .irq_unmask = chv_gpio_irq_unmask,
1485 .irq_set_type = chv_gpio_irq_type,
1486 .flags = IRQCHIP_SKIP_SET_WAKE,
1489 static void chv_gpio_irq_handler(struct irq_desc *desc)
1491 struct gpio_chip *gc = irq_desc_get_handler_data(desc);
1492 struct chv_pinctrl *pctrl = gpiochip_get_data(gc);
1493 struct irq_chip *chip = irq_desc_get_chip(desc);
1494 unsigned long pending;
1497 chained_irq_enter(chip, desc);
1499 pending = readl(pctrl->regs + CHV_INTSTAT);
1500 for_each_set_bit(intr_line, &pending, 16) {
1501 unsigned irq, offset;
1503 offset = pctrl->intr_lines[intr_line];
1504 irq = irq_find_mapping(gc->irqdomain, offset);
1505 generic_handle_irq(irq);
1508 chained_irq_exit(chip, desc);
1511 static int chv_gpio_probe(struct chv_pinctrl *pctrl, int irq)
1513 const struct chv_gpio_pinrange *range;
1514 struct gpio_chip *chip = &pctrl->chip;
1517 *chip = chv_gpio_chip;
1519 chip->ngpio = pctrl->community->ngpios;
1520 chip->label = dev_name(pctrl->dev);
1521 chip->parent = pctrl->dev;
1524 ret = gpiochip_add_data(chip, pctrl);
1526 dev_err(pctrl->dev, "Failed to register gpiochip\n");
1530 for (i = 0, offset = 0; i < pctrl->community->ngpio_ranges; i++) {
1531 range = &pctrl->community->gpio_ranges[i];
1532 ret = gpiochip_add_pin_range(chip, dev_name(pctrl->dev), offset,
1533 range->base, range->npins);
1535 dev_err(pctrl->dev, "failed to add GPIO pin range\n");
1539 offset += range->npins;
1542 /* Mask and clear all interrupts */
1543 chv_writel(0, pctrl->regs + CHV_INTMASK);
1544 chv_writel(0xffff, pctrl->regs + CHV_INTSTAT);
1546 ret = gpiochip_irqchip_add(chip, &chv_gpio_irqchip, 0,
1547 handle_simple_irq, IRQ_TYPE_NONE);
1549 dev_err(pctrl->dev, "failed to add IRQ chip\n");
1553 gpiochip_set_chained_irqchip(chip, &chv_gpio_irqchip, irq,
1554 chv_gpio_irq_handler);
1558 gpiochip_remove(chip);
1563 static int chv_pinctrl_probe(struct platform_device *pdev)
1565 struct chv_pinctrl *pctrl;
1566 struct acpi_device *adev;
1567 struct resource *res;
1570 adev = ACPI_COMPANION(&pdev->dev);
1574 pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL);
1578 for (i = 0; i < ARRAY_SIZE(chv_communities); i++)
1579 if (!strcmp(adev->pnp.unique_id, chv_communities[i]->uid)) {
1580 pctrl->community = chv_communities[i];
1583 if (i == ARRAY_SIZE(chv_communities))
1586 pctrl->dev = &pdev->dev;
1588 #ifdef CONFIG_PM_SLEEP
1589 pctrl->saved_pin_context = devm_kcalloc(pctrl->dev,
1590 pctrl->community->npins, sizeof(*pctrl->saved_pin_context),
1592 if (!pctrl->saved_pin_context)
1596 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1597 pctrl->regs = devm_ioremap_resource(&pdev->dev, res);
1598 if (IS_ERR(pctrl->regs))
1599 return PTR_ERR(pctrl->regs);
1601 irq = platform_get_irq(pdev, 0);
1603 dev_err(&pdev->dev, "failed to get interrupt number\n");
1607 pctrl->pctldesc = chv_pinctrl_desc;
1608 pctrl->pctldesc.name = dev_name(&pdev->dev);
1609 pctrl->pctldesc.pins = pctrl->community->pins;
1610 pctrl->pctldesc.npins = pctrl->community->npins;
1612 pctrl->pctldev = devm_pinctrl_register(&pdev->dev, &pctrl->pctldesc,
1614 if (IS_ERR(pctrl->pctldev)) {
1615 dev_err(&pdev->dev, "failed to register pinctrl driver\n");
1616 return PTR_ERR(pctrl->pctldev);
1619 ret = chv_gpio_probe(pctrl, irq);
1623 platform_set_drvdata(pdev, pctrl);
1628 static int chv_pinctrl_remove(struct platform_device *pdev)
1630 struct chv_pinctrl *pctrl = platform_get_drvdata(pdev);
1632 gpiochip_remove(&pctrl->chip);
1637 #ifdef CONFIG_PM_SLEEP
1638 static int chv_pinctrl_suspend(struct device *dev)
1640 struct platform_device *pdev = to_platform_device(dev);
1641 struct chv_pinctrl *pctrl = platform_get_drvdata(pdev);
1644 pctrl->saved_intmask = readl(pctrl->regs + CHV_INTMASK);
1646 for (i = 0; i < pctrl->community->npins; i++) {
1647 const struct pinctrl_pin_desc *desc;
1648 struct chv_pin_context *ctx;
1651 desc = &pctrl->community->pins[i];
1652 if (chv_pad_locked(pctrl, desc->number))
1655 ctx = &pctrl->saved_pin_context[i];
1657 reg = chv_padreg(pctrl, desc->number, CHV_PADCTRL0);
1658 ctx->padctrl0 = readl(reg) & ~CHV_PADCTRL0_GPIORXSTATE;
1660 reg = chv_padreg(pctrl, desc->number, CHV_PADCTRL1);
1661 ctx->padctrl1 = readl(reg);
1667 static int chv_pinctrl_resume(struct device *dev)
1669 struct platform_device *pdev = to_platform_device(dev);
1670 struct chv_pinctrl *pctrl = platform_get_drvdata(pdev);
1674 * Mask all interrupts before restoring per-pin configuration
1675 * registers because we don't know in which state BIOS left them
1676 * upon exiting suspend.
1678 chv_writel(0, pctrl->regs + CHV_INTMASK);
1680 for (i = 0; i < pctrl->community->npins; i++) {
1681 const struct pinctrl_pin_desc *desc;
1682 const struct chv_pin_context *ctx;
1686 desc = &pctrl->community->pins[i];
1687 if (chv_pad_locked(pctrl, desc->number))
1690 ctx = &pctrl->saved_pin_context[i];
1692 /* Only restore if our saved state differs from the current */
1693 reg = chv_padreg(pctrl, desc->number, CHV_PADCTRL0);
1694 val = readl(reg) & ~CHV_PADCTRL0_GPIORXSTATE;
1695 if (ctx->padctrl0 != val) {
1696 chv_writel(ctx->padctrl0, reg);
1697 dev_dbg(pctrl->dev, "restored pin %2u ctrl0 0x%08x\n",
1698 desc->number, readl(reg));
1701 reg = chv_padreg(pctrl, desc->number, CHV_PADCTRL1);
1703 if (ctx->padctrl1 != val) {
1704 chv_writel(ctx->padctrl1, reg);
1705 dev_dbg(pctrl->dev, "restored pin %2u ctrl1 0x%08x\n",
1706 desc->number, readl(reg));
1711 * Now that all pins are restored to known state, we can restore
1712 * the interrupt mask register as well.
1714 chv_writel(0xffff, pctrl->regs + CHV_INTSTAT);
1715 chv_writel(pctrl->saved_intmask, pctrl->regs + CHV_INTMASK);
1721 static const struct dev_pm_ops chv_pinctrl_pm_ops = {
1722 SET_LATE_SYSTEM_SLEEP_PM_OPS(chv_pinctrl_suspend, chv_pinctrl_resume)
1725 static const struct acpi_device_id chv_pinctrl_acpi_match[] = {
1729 MODULE_DEVICE_TABLE(acpi, chv_pinctrl_acpi_match);
1731 static struct platform_driver chv_pinctrl_driver = {
1732 .probe = chv_pinctrl_probe,
1733 .remove = chv_pinctrl_remove,
1735 .name = "cherryview-pinctrl",
1736 .pm = &chv_pinctrl_pm_ops,
1737 .acpi_match_table = chv_pinctrl_acpi_match,
1741 static int __init chv_pinctrl_init(void)
1743 return platform_driver_register(&chv_pinctrl_driver);
1745 subsys_initcall(chv_pinctrl_init);
1747 static void __exit chv_pinctrl_exit(void)
1749 platform_driver_unregister(&chv_pinctrl_driver);
1751 module_exit(chv_pinctrl_exit);
1753 MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>");
1754 MODULE_DESCRIPTION("Intel Cherryview/Braswell pinctrl driver");
1755 MODULE_LICENSE("GPL v2");