drivers/pinctrl/pinctrl-rockchip.c

   1 /*
   2  * Pinctrl driver for Rockchip SoCs
   3  *
   4  * Copyright (c) 2013 MundoReader S.L.
   5  * Author: Heiko Stuebner <heiko@sntech.de>
   6  *
   7  * With some ideas taken from pinctrl-samsung:
   8  * Copyright (c) 2012 Samsung Electronics Co., Ltd.
   9  *              http://www.samsung.com
  10  * Copyright (c) 2012 Linaro Ltd
  11  *              http://www.linaro.org
  12  *
  13  * and pinctrl-at91:
  14  * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
  15  *
  16  * This program is free software; you can redistribute it and/or modify
  17  * it under the terms of the GNU General Public License version 2 as published
  18  * by the Free Software Foundation.
  19  *
  20  * This program is distributed in the hope that it will be useful,
  21  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  22  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  23  * GNU General Public License for more details.
  24  */
  25
  26 #include <linux/module.h>
  27 #include <linux/platform_device.h>
  28 #include <linux/io.h>
  29 #include <linux/bitops.h>
  30 #include <linux/gpio.h>
  31 #include <linux/of_address.h>
  32 #include <linux/of_irq.h>
  33 #include <linux/pinctrl/machine.h>
  34 #include <linux/pinctrl/pinconf.h>
  35 #include <linux/pinctrl/pinctrl.h>
  36 #include <linux/pinctrl/pinmux.h>
  37 #include <linux/pinctrl/pinconf-generic.h>
  38 #include <linux/irqchip/chained_irq.h>
  39 #include <linux/clk.h>
  40 #include <dt-bindings/pinctrl/rockchip.h>
  41
  42 #include "core.h"
  43 #include "pinconf.h"
  44
  45 /* GPIO control registers */
  46 #define GPIO_SWPORT_DR          0x00
  47 #define GPIO_SWPORT_DDR         0x04
  48 #define GPIO_INTEN              0x30
  49 #define GPIO_INTMASK            0x34
  50 #define GPIO_INTTYPE_LEVEL      0x38
  51 #define GPIO_INT_POLARITY       0x3c
  52 #define GPIO_INT_STATUS         0x40
  53 #define GPIO_INT_RAWSTATUS      0x44
  54 #define GPIO_DEBOUNCE           0x48
  55 #define GPIO_PORTS_EOI          0x4c
  56 #define GPIO_EXT_PORT           0x50
  57 #define GPIO_LS_SYNC            0x60
  58
  59 enum rockchip_pinctrl_type {
  60         RK2928,
  61         RK3066B,
  62         RK3188,
  63 };
  64
  65 enum rockchip_pin_bank_type {
  66         COMMON_BANK,
  67         RK3188_BANK0,
  68 };
  69
  70 /**
  71  * @reg_base: register base of the gpio bank
  72  * @reg_pull: optional separate register for additional pull settings
  73  * @clk: clock of the gpio bank
  74  * @irq: interrupt of the gpio bank
  75  * @pin_base: first pin number
  76  * @nr_pins: number of pins in this bank
  77  * @name: name of the bank
  78  * @bank_num: number of the bank, to account for holes
  79  * @valid: are all necessary informations present
  80  * @of_node: dt node of this bank
  81  * @drvdata: common pinctrl basedata
  82  * @domain: irqdomain of the gpio bank
  83  * @gpio_chip: gpiolib chip
  84  * @grange: gpio range
  85  * @slock: spinlock for the gpio bank
  86  */
  87 struct rockchip_pin_bank {
  88         void __iomem                    *reg_base;
  89         void __iomem                    *reg_pull;
  90         struct clk                      *clk;
  91         int                             irq;
  92         u32                             pin_base;
  93         u8                              nr_pins;
  94         char                            *name;
  95         u8                              bank_num;
  96         enum rockchip_pin_bank_type     bank_type;
  97         bool                            valid;
  98         struct device_node              *of_node;
  99         struct rockchip_pinctrl         *drvdata;
 100         struct irq_domain               *domain;
 101         struct gpio_chip                gpio_chip;
 102         struct pinctrl_gpio_range       grange;
 103         spinlock_t                      slock;
 104         u32                             toggle_edge_mode;
 105 };
 106
 107 #define PIN_BANK(id, pins, label)                       \
 108         {                                               \
 109                 .bank_num       = id,                   \
 110                 .nr_pins        = pins,                 \
 111                 .name           = label,                \
 112         }
 113
 114 /**
 115  */
 116 struct rockchip_pin_ctrl {
 117         struct rockchip_pin_bank        *pin_banks;
 118         u32                             nr_banks;
 119         u32                             nr_pins;
 120         char                            *label;
 121         enum rockchip_pinctrl_type      type;
 122         int                             mux_offset;
 123         void    (*pull_calc_reg)(struct rockchip_pin_bank *bank, int pin_num,
 124                                  void __iomem **reg, u8 *bit);
 125 };
 126
 127 struct rockchip_pin_config {
 128         unsigned int            func;
 129         unsigned long           *configs;
 130         unsigned int            nconfigs;
 131 };
 132
 133 /**
 134  * struct rockchip_pin_group: represent group of pins of a pinmux function.
 135  * @name: name of the pin group, used to lookup the group.
 136  * @pins: the pins included in this group.
 137  * @npins: number of pins included in this group.
 138  * @func: the mux function number to be programmed when selected.
 139  * @configs: the config values to be set for each pin
 140  * @nconfigs: number of configs for each pin
 141  */
 142 struct rockchip_pin_group {
 143         const char                      *name;
 144         unsigned int                    npins;
 145         unsigned int                    *pins;
 146         struct rockchip_pin_config      *data;
 147 };
 148
 149 /**
 150  * struct rockchip_pmx_func: represent a pin function.
 151  * @name: name of the pin function, used to lookup the function.
 152  * @groups: one or more names of pin groups that provide this function.
 153  * @num_groups: number of groups included in @groups.
 154  */
 155 struct rockchip_pmx_func {
 156         const char              *name;
 157         const char              **groups;
 158         u8                      ngroups;
 159 };
 160
 161 struct rockchip_pinctrl {
 162         void __iomem                    *reg_base;
 163         void __iomem                    *reg_pull;
 164         struct device                   *dev;
 165         struct rockchip_pin_ctrl        *ctrl;
 166         struct pinctrl_desc             pctl;
 167         struct pinctrl_dev              *pctl_dev;
 168         struct rockchip_pin_group       *groups;
 169         unsigned int                    ngroups;
 170         struct rockchip_pmx_func        *functions;
 171         unsigned int                    nfunctions;
 172 };
 173
 174 static inline struct rockchip_pin_bank *gc_to_pin_bank(struct gpio_chip *gc)
 175 {
 176         return container_of(gc, struct rockchip_pin_bank, gpio_chip);
 177 }
 178
 179 static const inline struct rockchip_pin_group *pinctrl_name_to_group(
 180                                         const struct rockchip_pinctrl *info,
 181                                         const char *name)
 182 {
 183         int i;
 184
 185         for (i = 0; i < info->ngroups; i++) {
 186                 if (!strcmp(info->groups[i].name, name))
 187                         return &info->groups[i];
 188         }
 189
 190         return NULL;
 191 }
 192
 193 /*
 194  * given a pin number that is local to a pin controller, find out the pin bank
 195  * and the register base of the pin bank.
 196  */
 197 static struct rockchip_pin_bank *pin_to_bank(struct rockchip_pinctrl *info,
 198                                                                 unsigned pin)
 199 {
 200         struct rockchip_pin_bank *b = info->ctrl->pin_banks;
 201
 202         while (pin >= (b->pin_base + b->nr_pins))
 203                 b++;
 204
 205         return b;
 206 }
 207
 208 static struct rockchip_pin_bank *bank_num_to_bank(
 209                                         struct rockchip_pinctrl *info,
 210                                         unsigned num)
 211 {
 212         struct rockchip_pin_bank *b = info->ctrl->pin_banks;
 213         int i;
 214
 215         for (i = 0; i < info->ctrl->nr_banks; i++, b++) {
 216                 if (b->bank_num == num)
 217                         return b;
 218         }
 219
 220         return ERR_PTR(-EINVAL);
 221 }
 222
 223 /*
 224  * Pinctrl_ops handling
 225  */
 226
 227 static int rockchip_get_groups_count(struct pinctrl_dev *pctldev)
 228 {
 229         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 230
 231         return info->ngroups;
 232 }
 233
 234 static const char *rockchip_get_group_name(struct pinctrl_dev *pctldev,
 235                                                         unsigned selector)
 236 {
 237         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 238
 239         return info->groups[selector].name;
 240 }
 241
 242 static int rockchip_get_group_pins(struct pinctrl_dev *pctldev,
 243                                       unsigned selector, const unsigned **pins,
 244                                       unsigned *npins)
 245 {
 246         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 247
 248         if (selector >= info->ngroups)
 249                 return -EINVAL;
 250
 251         *pins = info->groups[selector].pins;
 252         *npins = info->groups[selector].npins;
 253
 254         return 0;
 255 }
 256
 257 static int rockchip_dt_node_to_map(struct pinctrl_dev *pctldev,
 258                                  struct device_node *np,
 259                                  struct pinctrl_map **map, unsigned *num_maps)
 260 {
 261         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 262         const struct rockchip_pin_group *grp;
 263         struct pinctrl_map *new_map;
 264         struct device_node *parent;
 265         int map_num = 1;
 266         int i;
 267
 268         /*
 269          * first find the group of this node and check if we need to create
 270          * config maps for pins
 271          */
 272         grp = pinctrl_name_to_group(info, np->name);
 273         if (!grp) {
 274                 dev_err(info->dev, "unable to find group for node %s\n",
 275                         np->name);
 276                 return -EINVAL;
 277         }
 278
 279         map_num += grp->npins;
 280         new_map = devm_kzalloc(pctldev->dev, sizeof(*new_map) * map_num,
 281                                                                 GFP_KERNEL);
 282         if (!new_map)
 283                 return -ENOMEM;
 284
 285         *map = new_map;
 286         *num_maps = map_num;
 287
 288         /* create mux map */
 289         parent = of_get_parent(np);
 290         if (!parent) {
 291                 devm_kfree(pctldev->dev, new_map);
 292                 return -EINVAL;
 293         }
 294         new_map[0].type = PIN_MAP_TYPE_MUX_GROUP;
 295         new_map[0].data.mux.function = parent->name;
 296         new_map[0].data.mux.group = np->name;
 297         of_node_put(parent);
 298
 299         /* create config map */
 300         new_map++;
 301         for (i = 0; i < grp->npins; i++) {
 302                 new_map[i].type = PIN_MAP_TYPE_CONFIGS_PIN;
 303                 new_map[i].data.configs.group_or_pin =
 304                                 pin_get_name(pctldev, grp->pins[i]);
 305                 new_map[i].data.configs.configs = grp->data[i].configs;
 306                 new_map[i].data.configs.num_configs = grp->data[i].nconfigs;
 307         }
 308
 309         dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n",
 310                 (*map)->data.mux.function, (*map)->data.mux.group, map_num);
 311
 312         return 0;
 313 }
 314
 315 static void rockchip_dt_free_map(struct pinctrl_dev *pctldev,
 316                                     struct pinctrl_map *map, unsigned num_maps)
 317 {
 318 }
 319
 320 static const struct pinctrl_ops rockchip_pctrl_ops = {
 321         .get_groups_count       = rockchip_get_groups_count,
 322         .get_group_name         = rockchip_get_group_name,
 323         .get_group_pins         = rockchip_get_group_pins,
 324         .dt_node_to_map         = rockchip_dt_node_to_map,
 325         .dt_free_map            = rockchip_dt_free_map,
 326 };
 327
 328 /*
 329  * Hardware access
 330  */
 331
 332 /*
 333  * Set a new mux function for a pin.
 334  *
 335  * The register is divided into the upper and lower 16 bit. When changing
 336  * a value, the previous register value is not read and changed. Instead
 337  * it seems the changed bits are marked in the upper 16 bit, while the
 338  * changed value gets set in the same offset in the lower 16 bit.
 339  * All pin settings seem to be 2 bit wide in both the upper and lower
 340  * parts.
 341  * @bank: pin bank to change
 342  * @pin: pin to change
 343  * @mux: new mux function to set
 344  */
 345 static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
 346 {
 347         struct rockchip_pinctrl *info = bank->drvdata;
 348         void __iomem *reg = info->reg_base + info->ctrl->mux_offset;
 349         unsigned long flags;
 350         u8 bit;
 351         u32 data;
 352
 353         /*
 354          * The first 16 pins of rk3188_bank0 are always gpios and do not have
 355          * a mux register at all.
 356          */
 357         if (bank->bank_type == RK3188_BANK0 && pin < 16) {
 358                 if (mux != RK_FUNC_GPIO) {
 359                         dev_err(info->dev,
 360                                 "pin %d only supports a gpio mux\n", pin);
 361                         return -ENOTSUPP;
 362                 } else {
 363                         return 0;
 364                 }
 365         }
 366
 367         dev_dbg(info->dev, "setting mux of GPIO%d-%d to %d\n",
 368                                                 bank->bank_num, pin, mux);
 369
 370         /* get basic quadrupel of mux registers and the correct reg inside */
 371         reg += bank->bank_num * 0x10;
 372         reg += (pin / 8) * 4;
 373         bit = (pin % 8) * 2;
 374
 375         spin_lock_irqsave(&bank->slock, flags);
 376
 377         data = (3 << (bit + 16));
 378         data |= (mux & 3) << bit;
 379         writel(data, reg);
 380
 381         spin_unlock_irqrestore(&bank->slock, flags);
 382
 383         return 0;
 384 }
 385
 386 #define RK2928_PULL_OFFSET              0x118
 387 #define RK2928_PULL_PINS_PER_REG        16
 388 #define RK2928_PULL_BANK_STRIDE         8
 389
 390 static void rk2928_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
 391                                     int pin_num, void __iomem **reg, u8 *bit)
 392 {
 393         struct rockchip_pinctrl *info = bank->drvdata;
 394
 395         *reg = info->reg_base + RK2928_PULL_OFFSET;
 396         *reg += bank->bank_num * RK2928_PULL_BANK_STRIDE;
 397         *reg += (pin_num / RK2928_PULL_PINS_PER_REG) * 4;
 398
 399         *bit = pin_num % RK2928_PULL_PINS_PER_REG;
 400 };
 401
 402 #define RK3188_PULL_BITS_PER_PIN        2
 403 #define RK3188_PULL_PINS_PER_REG        8
 404 #define RK3188_PULL_BANK_STRIDE         16
 405
 406 static void rk3188_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
 407                                     int pin_num, void __iomem **reg, u8 *bit)
 408 {
 409         struct rockchip_pinctrl *info = bank->drvdata;
 410
 411         /* The first 12 pins of the first bank are located elsewhere */
 412         if (bank->bank_type == RK3188_BANK0 && pin_num < 12) {
 413                 *reg = bank->reg_pull +
 414                                 ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
 415                 *bit = pin_num % RK3188_PULL_PINS_PER_REG;
 416                 *bit *= RK3188_PULL_BITS_PER_PIN;
 417         } else {
 418                 *reg = info->reg_pull - 4;
 419                 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
 420                 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
 421
 422                 /*
 423                  * The bits in these registers have an inverse ordering
 424                  * with the lowest pin being in bits 15:14 and the highest
 425                  * pin in bits 1:0
 426                  */
 427                 *bit = 7 - (pin_num % RK3188_PULL_PINS_PER_REG);
 428                 *bit *= RK3188_PULL_BITS_PER_PIN;
 429         }
 430 }
 431
 432 static int rockchip_get_pull(struct rockchip_pin_bank *bank, int pin_num)
 433 {
 434         struct rockchip_pinctrl *info = bank->drvdata;
 435         struct rockchip_pin_ctrl *ctrl = info->ctrl;
 436         void __iomem *reg;
 437         u8 bit;
 438         u32 data;
 439
 440         /* rk3066b does support any pulls */
 441         if (ctrl->type == RK3066B)
 442                 return PIN_CONFIG_BIAS_DISABLE;
 443
 444         ctrl->pull_calc_reg(bank, pin_num, &reg, &bit);
 445
 446         switch (ctrl->type) {
 447         case RK2928:
 448                 return !(readl_relaxed(reg) & BIT(bit))
 449                                 ? PIN_CONFIG_BIAS_PULL_PIN_DEFAULT
 450                                 : PIN_CONFIG_BIAS_DISABLE;
 451         case RK3188:
 452                 data = readl_relaxed(reg) >> bit;
 453                 data &= (1 << RK3188_PULL_BITS_PER_PIN) - 1;
 454
 455                 switch (data) {
 456                 case 0:
 457                         return PIN_CONFIG_BIAS_DISABLE;
 458                 case 1:
 459                         return PIN_CONFIG_BIAS_PULL_UP;
 460                 case 2:
 461                         return PIN_CONFIG_BIAS_PULL_DOWN;
 462                 case 3:
 463                         return PIN_CONFIG_BIAS_BUS_HOLD;
 464                 }
 465
 466                 dev_err(info->dev, "unknown pull setting\n");
 467                 return -EIO;
 468         default:
 469                 dev_err(info->dev, "unsupported pinctrl type\n");
 470                 return -EINVAL;
 471         };
 472 }
 473
 474 static int rockchip_set_pull(struct rockchip_pin_bank *bank,
 475                                         int pin_num, int pull)
 476 {
 477         struct rockchip_pinctrl *info = bank->drvdata;
 478         struct rockchip_pin_ctrl *ctrl = info->ctrl;
 479         void __iomem *reg;
 480         unsigned long flags;
 481         u8 bit;
 482         u32 data;
 483
 484         dev_dbg(info->dev, "setting pull of GPIO%d-%d to %d\n",
 485                  bank->bank_num, pin_num, pull);
 486
 487         /* rk3066b does support any pulls */
 488         if (ctrl->type == RK3066B)
 489                 return pull ? -EINVAL : 0;
 490
 491         ctrl->pull_calc_reg(bank, pin_num, &reg, &bit);
 492
 493         switch (ctrl->type) {
 494         case RK2928:
 495                 spin_lock_irqsave(&bank->slock, flags);
 496
 497                 data = BIT(bit + 16);
 498                 if (pull == PIN_CONFIG_BIAS_DISABLE)
 499                         data |= BIT(bit);
 500                 writel(data, reg);
 501
 502                 spin_unlock_irqrestore(&bank->slock, flags);
 503                 break;
 504         case RK3188:
 505                 spin_lock_irqsave(&bank->slock, flags);
 506
 507                 /* enable the write to the equivalent lower bits */
 508                 data = ((1 << RK3188_PULL_BITS_PER_PIN) - 1) << (bit + 16);
 509
 510                 switch (pull) {
 511                 case PIN_CONFIG_BIAS_DISABLE:
 512                         break;
 513                 case PIN_CONFIG_BIAS_PULL_UP:
 514                         data |= (1 << bit);
 515                         break;
 516                 case PIN_CONFIG_BIAS_PULL_DOWN:
 517                         data |= (2 << bit);
 518                         break;
 519                 case PIN_CONFIG_BIAS_BUS_HOLD:
 520                         data |= (3 << bit);
 521                         break;
 522                 default:
 523                         spin_unlock_irqrestore(&bank->slock, flags);
 524                         dev_err(info->dev, "unsupported pull setting %d\n",
 525                                 pull);
 526                         return -EINVAL;
 527                 }
 528
 529                 writel(data, reg);
 530
 531                 spin_unlock_irqrestore(&bank->slock, flags);
 532                 break;
 533         default:
 534                 dev_err(info->dev, "unsupported pinctrl type\n");
 535                 return -EINVAL;
 536         }
 537
 538         return 0;
 539 }
 540
 541 /*
 542  * Pinmux_ops handling
 543  */
 544
 545 static int rockchip_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
 546 {
 547         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 548
 549         return info->nfunctions;
 550 }
 551
 552 static const char *rockchip_pmx_get_func_name(struct pinctrl_dev *pctldev,
 553                                           unsigned selector)
 554 {
 555         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 556
 557         return info->functions[selector].name;
 558 }
 559
 560 static int rockchip_pmx_get_groups(struct pinctrl_dev *pctldev,
 561                                 unsigned selector, const char * const **groups,
 562                                 unsigned * const num_groups)
 563 {
 564         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 565
 566         *groups = info->functions[selector].groups;
 567         *num_groups = info->functions[selector].ngroups;
 568
 569         return 0;
 570 }
 571
 572 static int rockchip_pmx_enable(struct pinctrl_dev *pctldev, unsigned selector,
 573                                                             unsigned group)
 574 {
 575         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 576         const unsigned int *pins = info->groups[group].pins;
 577         const struct rockchip_pin_config *data = info->groups[group].data;
 578         struct rockchip_pin_bank *bank;
 579         int cnt, ret = 0;
 580
 581         dev_dbg(info->dev, "enable function %s group %s\n",
 582                 info->functions[selector].name, info->groups[group].name);
 583
 584         /*
 585          * for each pin in the pin group selected, program the correspoding pin
 586          * pin function number in the config register.
 587          */
 588         for (cnt = 0; cnt < info->groups[group].npins; cnt++) {
 589                 bank = pin_to_bank(info, pins[cnt]);
 590                 ret = rockchip_set_mux(bank, pins[cnt] - bank->pin_base,
 591                                        data[cnt].func);
 592                 if (ret)
 593                         break;
 594         }
 595
 596         if (ret) {
 597                 /* revert the already done pin settings */
 598                 for (cnt--; cnt >= 0; cnt--)
 599                         rockchip_set_mux(bank, pins[cnt] - bank->pin_base, 0);
 600
 601                 return ret;
 602         }
 603
 604         return 0;
 605 }
 606
 607 static void rockchip_pmx_disable(struct pinctrl_dev *pctldev,
 608                                         unsigned selector, unsigned group)
 609 {
 610         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 611         const unsigned int *pins = info->groups[group].pins;
 612         struct rockchip_pin_bank *bank;
 613         int cnt;
 614
 615         dev_dbg(info->dev, "disable function %s group %s\n",
 616                 info->functions[selector].name, info->groups[group].name);
 617
 618         for (cnt = 0; cnt < info->groups[group].npins; cnt++) {
 619                 bank = pin_to_bank(info, pins[cnt]);
 620                 rockchip_set_mux(bank, pins[cnt] - bank->pin_base, 0);
 621         }
 622 }
 623
 624 /*
 625  * The calls to gpio_direction_output() and gpio_direction_input()
 626  * leads to this function call (via the pinctrl_gpio_direction_{input|output}()
 627  * function called from the gpiolib interface).
 628  */
 629 static int rockchip_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
 630                                               struct pinctrl_gpio_range *range,
 631                                               unsigned offset, bool input)
 632 {
 633         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 634         struct rockchip_pin_bank *bank;
 635         struct gpio_chip *chip;
 636         int pin, ret;
 637         u32 data;
 638
 639         chip = range->gc;
 640         bank = gc_to_pin_bank(chip);
 641         pin = offset - chip->base;
 642
 643         dev_dbg(info->dev, "gpio_direction for pin %u as %s-%d to %s\n",
 644                  offset, range->name, pin, input ? "input" : "output");
 645
 646         ret = rockchip_set_mux(bank, pin, RK_FUNC_GPIO);
 647         if (ret < 0)
 648                 return ret;
 649
 650         data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR);
 651         /* set bit to 1 for output, 0 for input */
 652         if (!input)
 653                 data |= BIT(pin);
 654         else
 655                 data &= ~BIT(pin);
 656         writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR);
 657
 658         return 0;
 659 }
 660
 661 static const struct pinmux_ops rockchip_pmx_ops = {
 662         .get_functions_count    = rockchip_pmx_get_funcs_count,
 663         .get_function_name      = rockchip_pmx_get_func_name,
 664         .get_function_groups    = rockchip_pmx_get_groups,
 665         .enable                 = rockchip_pmx_enable,
 666         .disable                = rockchip_pmx_disable,
 667         .gpio_set_direction     = rockchip_pmx_gpio_set_direction,
 668 };
 669
 670 /*
 671  * Pinconf_ops handling
 672  */
 673
 674 static bool rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl *ctrl,
 675                                         enum pin_config_param pull)
 676 {
 677         switch (ctrl->type) {
 678         case RK2928:
 679                 return (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT ||
 680                                         pull == PIN_CONFIG_BIAS_DISABLE);
 681         case RK3066B:
 682                 return pull ? false : true;
 683         case RK3188:
 684                 return (pull != PIN_CONFIG_BIAS_PULL_PIN_DEFAULT);
 685         }
 686
 687         return false;
 688 }
 689
 690 /* set the pin config settings for a specified pin */
 691 static int rockchip_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
 692                                 unsigned long *configs, unsigned num_configs)
 693 {
 694         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 695         struct rockchip_pin_bank *bank = pin_to_bank(info, pin);
 696         enum pin_config_param param;
 697         u16 arg;
 698         int i;
 699         int rc;
 700
 701         for (i = 0; i < num_configs; i++) {
 702                 param = pinconf_to_config_param(configs[i]);
 703                 arg = pinconf_to_config_argument(configs[i]);
 704
 705                 switch (param) {
 706                 case PIN_CONFIG_BIAS_DISABLE:
 707                         rc =  rockchip_set_pull(bank, pin - bank->pin_base,
 708                                 param);
 709                         if (rc)
 710                                 return rc;
 711                         break;
 712                 case PIN_CONFIG_BIAS_PULL_UP:
 713                 case PIN_CONFIG_BIAS_PULL_DOWN:
 714                 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
 715                 case PIN_CONFIG_BIAS_BUS_HOLD:
 716                         if (!rockchip_pinconf_pull_valid(info->ctrl, param))
 717                                 return -ENOTSUPP;
 718
 719                         if (!arg)
 720                                 return -EINVAL;
 721
 722                         rc = rockchip_set_pull(bank, pin - bank->pin_base,
 723                                 param);
 724                         if (rc)
 725                                 return rc;
 726                         break;
 727                 default:
 728                         return -ENOTSUPP;
 729                         break;
 730                 }
 731         } /* for each config */
 732
 733         return 0;
 734 }
 735
 736 /* get the pin config settings for a specified pin */
 737 static int rockchip_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin,
 738                                                         unsigned long *config)
 739 {
 740         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 741         struct rockchip_pin_bank *bank = pin_to_bank(info, pin);
 742         enum pin_config_param param = pinconf_to_config_param(*config);
 743
 744         switch (param) {
 745         case PIN_CONFIG_BIAS_DISABLE:
 746                 if (rockchip_get_pull(bank, pin - bank->pin_base) != param)
 747                         return -EINVAL;
 748
 749                 *config = 0;
 750                 break;
 751         case PIN_CONFIG_BIAS_PULL_UP:
 752         case PIN_CONFIG_BIAS_PULL_DOWN:
 753         case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
 754         case PIN_CONFIG_BIAS_BUS_HOLD:
 755                 if (!rockchip_pinconf_pull_valid(info->ctrl, param))
 756                         return -ENOTSUPP;
 757
 758                 if (rockchip_get_pull(bank, pin - bank->pin_base) != param)
 759                         return -EINVAL;
 760
 761                 *config = 1;
 762                 break;
 763         default:
 764                 return -ENOTSUPP;
 765                 break;
 766         }
 767
 768         return 0;
 769 }
 770
 771 static const struct pinconf_ops rockchip_pinconf_ops = {
 772         .pin_config_get                 = rockchip_pinconf_get,
 773         .pin_config_set                 = rockchip_pinconf_set,
 774 };
 775
 776 static const struct of_device_id rockchip_bank_match[] = {
 777         { .compatible = "rockchip,gpio-bank" },
 778         { .compatible = "rockchip,rk3188-gpio-bank0" },
 779         {},
 780 };
 781
 782 static void rockchip_pinctrl_child_count(struct rockchip_pinctrl *info,
 783                                                 struct device_node *np)
 784 {
 785         struct device_node *child;
 786
 787         for_each_child_of_node(np, child) {
 788                 if (of_match_node(rockchip_bank_match, child))
 789                         continue;
 790
 791                 info->nfunctions++;
 792                 info->ngroups += of_get_child_count(child);
 793         }
 794 }
 795
 796 static int rockchip_pinctrl_parse_groups(struct device_node *np,
 797                                               struct rockchip_pin_group *grp,
 798                                               struct rockchip_pinctrl *info,
 799                                               u32 index)
 800 {
 801         struct rockchip_pin_bank *bank;
 802         int size;
 803         const __be32 *list;
 804         int num;
 805         int i, j;
 806         int ret;
 807
 808         dev_dbg(info->dev, "group(%d): %s\n", index, np->name);
 809
 810         /* Initialise group */
 811         grp->name = np->name;
 812
 813         /*
 814          * the binding format is rockchip,pins = <bank pin mux CONFIG>,
 815          * do sanity check and calculate pins number
 816          */
 817         list = of_get_property(np, "rockchip,pins", &size);
 818         /* we do not check return since it's safe node passed down */
 819         size /= sizeof(*list);
 820         if (!size || size % 4) {
 821                 dev_err(info->dev, "wrong pins number or pins and configs should be by 4\n");
 822                 return -EINVAL;
 823         }
 824
 825         grp->npins = size / 4;
 826
 827         grp->pins = devm_kzalloc(info->dev, grp->npins * sizeof(unsigned int),
 828                                                 GFP_KERNEL);
 829         grp->data = devm_kzalloc(info->dev, grp->npins *
 830                                           sizeof(struct rockchip_pin_config),
 831                                         GFP_KERNEL);
 832         if (!grp->pins || !grp->data)
 833                 return -ENOMEM;
 834
 835         for (i = 0, j = 0; i < size; i += 4, j++) {
 836                 const __be32 *phandle;
 837                 struct device_node *np_config;
 838
 839                 num = be32_to_cpu(*list++);
 840                 bank = bank_num_to_bank(info, num);
 841                 if (IS_ERR(bank))
 842                         return PTR_ERR(bank);
 843
 844                 grp->pins[j] = bank->pin_base + be32_to_cpu(*list++);
 845                 grp->data[j].func = be32_to_cpu(*list++);
 846
 847                 phandle = list++;
 848                 if (!phandle)
 849                         return -EINVAL;
 850
 851                 np_config = of_find_node_by_phandle(be32_to_cpup(phandle));
 852                 ret = pinconf_generic_parse_dt_config(np_config,
 853                                 &grp->data[j].configs, &grp->data[j].nconfigs);
 854                 if (ret)
 855                         return ret;
 856         }
 857
 858         return 0;
 859 }
 860
 861 static int rockchip_pinctrl_parse_functions(struct device_node *np,
 862                                                 struct rockchip_pinctrl *info,
 863                                                 u32 index)
 864 {
 865         struct device_node *child;
 866         struct rockchip_pmx_func *func;
 867         struct rockchip_pin_group *grp;
 868         int ret;
 869         static u32 grp_index;
 870         u32 i = 0;
 871
 872         dev_dbg(info->dev, "parse function(%d): %s\n", index, np->name);
 873
 874         func = &info->functions[index];
 875
 876         /* Initialise function */
 877         func->name = np->name;
 878         func->ngroups = of_get_child_count(np);
 879         if (func->ngroups <= 0)
 880                 return 0;
 881
 882         func->groups = devm_kzalloc(info->dev,
 883                         func->ngroups * sizeof(char *), GFP_KERNEL);
 884         if (!func->groups)
 885                 return -ENOMEM;
 886
 887         for_each_child_of_node(np, child) {
 888                 func->groups[i] = child->name;
 889                 grp = &info->groups[grp_index++];
 890                 ret = rockchip_pinctrl_parse_groups(child, grp, info, i++);
 891                 if (ret)
 892                         return ret;
 893         }
 894
 895         return 0;
 896 }
 897
 898 static int rockchip_pinctrl_parse_dt(struct platform_device *pdev,
 899                                               struct rockchip_pinctrl *info)
 900 {
 901         struct device *dev = &pdev->dev;
 902         struct device_node *np = dev->of_node;
 903         struct device_node *child;
 904         int ret;
 905         int i;
 906
 907         rockchip_pinctrl_child_count(info, np);
 908
 909         dev_dbg(&pdev->dev, "nfunctions = %d\n", info->nfunctions);
 910         dev_dbg(&pdev->dev, "ngroups = %d\n", info->ngroups);
 911
 912         info->functions = devm_kzalloc(dev, info->nfunctions *
 913                                               sizeof(struct rockchip_pmx_func),
 914                                               GFP_KERNEL);
 915         if (!info->functions) {
 916                 dev_err(dev, "failed to allocate memory for function list\n");
 917                 return -EINVAL;
 918         }
 919
 920         info->groups = devm_kzalloc(dev, info->ngroups *
 921                                             sizeof(struct rockchip_pin_group),
 922                                             GFP_KERNEL);
 923         if (!info->groups) {
 924                 dev_err(dev, "failed allocate memory for ping group list\n");
 925                 return -EINVAL;
 926         }
 927
 928         i = 0;
 929
 930         for_each_child_of_node(np, child) {
 931                 if (of_match_node(rockchip_bank_match, child))
 932                         continue;
 933
 934                 ret = rockchip_pinctrl_parse_functions(child, info, i++);
 935                 if (ret) {
 936                         dev_err(&pdev->dev, "failed to parse function\n");
 937                         return ret;
 938                 }
 939         }
 940
 941         return 0;
 942 }
 943
 944 static int rockchip_pinctrl_register(struct platform_device *pdev,
 945                                         struct rockchip_pinctrl *info)
 946 {
 947         struct pinctrl_desc *ctrldesc = &info->pctl;
 948         struct pinctrl_pin_desc *pindesc, *pdesc;
 949         struct rockchip_pin_bank *pin_bank;
 950         int pin, bank, ret;
 951         int k;
 952
 953         ctrldesc->name = "rockchip-pinctrl";
 954         ctrldesc->owner = THIS_MODULE;
 955         ctrldesc->pctlops = &rockchip_pctrl_ops;
 956         ctrldesc->pmxops = &rockchip_pmx_ops;
 957         ctrldesc->confops = &rockchip_pinconf_ops;
 958
 959         pindesc = devm_kzalloc(&pdev->dev, sizeof(*pindesc) *
 960                         info->ctrl->nr_pins, GFP_KERNEL);
 961         if (!pindesc) {
 962                 dev_err(&pdev->dev, "mem alloc for pin descriptors failed\n");
 963                 return -ENOMEM;
 964         }
 965         ctrldesc->pins = pindesc;
 966         ctrldesc->npins = info->ctrl->nr_pins;
 967
 968         pdesc = pindesc;
 969         for (bank = 0 , k = 0; bank < info->ctrl->nr_banks; bank++) {
 970                 pin_bank = &info->ctrl->pin_banks[bank];
 971                 for (pin = 0; pin < pin_bank->nr_pins; pin++, k++) {
 972                         pdesc->number = k;
 973                         pdesc->name = kasprintf(GFP_KERNEL, "%s-%d",
 974                                                 pin_bank->name, pin);
 975                         pdesc++;
 976                 }
 977         }
 978
 979         info->pctl_dev = pinctrl_register(ctrldesc, &pdev->dev, info);
 980         if (!info->pctl_dev) {
 981                 dev_err(&pdev->dev, "could not register pinctrl driver\n");
 982                 return -EINVAL;
 983         }
 984
 985         for (bank = 0; bank < info->ctrl->nr_banks; ++bank) {
 986                 pin_bank = &info->ctrl->pin_banks[bank];
 987                 pin_bank->grange.name = pin_bank->name;
 988                 pin_bank->grange.id = bank;
 989                 pin_bank->grange.pin_base = pin_bank->pin_base;
 990                 pin_bank->grange.base = pin_bank->gpio_chip.base;
 991                 pin_bank->grange.npins = pin_bank->gpio_chip.ngpio;
 992                 pin_bank->grange.gc = &pin_bank->gpio_chip;
 993                 pinctrl_add_gpio_range(info->pctl_dev, &pin_bank->grange);
 994         }
 995
 996         ret = rockchip_pinctrl_parse_dt(pdev, info);
 997         if (ret) {
 998                 pinctrl_unregister(info->pctl_dev);
 999                 return ret;
1000         }
1001
1002         return 0;
1003 }
1004
1005 /*
1006  * GPIO handling
1007  */
1008
1009 static int rockchip_gpio_request(struct gpio_chip *chip, unsigned offset)
1010 {
1011         return pinctrl_request_gpio(chip->base + offset);
1012 }
1013
1014 static void rockchip_gpio_free(struct gpio_chip *chip, unsigned offset)
1015 {
1016         pinctrl_free_gpio(chip->base + offset);
1017 }
1018
1019 static void rockchip_gpio_set(struct gpio_chip *gc, unsigned offset, int value)
1020 {
1021         struct rockchip_pin_bank *bank = gc_to_pin_bank(gc);
1022         void __iomem *reg = bank->reg_base + GPIO_SWPORT_DR;
1023         unsigned long flags;
1024         u32 data;
1025
1026         spin_lock_irqsave(&bank->slock, flags);
1027
1028         data = readl(reg);
1029         data &= ~BIT(offset);
1030         if (value)
1031                 data |= BIT(offset);
1032         writel(data, reg);
1033
1034         spin_unlock_irqrestore(&bank->slock, flags);
1035 }
1036
1037 /*
1038  * Returns the level of the pin for input direction and setting of the DR
1039  * register for output gpios.
1040  */
1041 static int rockchip_gpio_get(struct gpio_chip *gc, unsigned offset)
1042 {
1043         struct rockchip_pin_bank *bank = gc_to_pin_bank(gc);
1044         u32 data;
1045
1046         data = readl(bank->reg_base + GPIO_EXT_PORT);
1047         data >>= offset;
1048         data &= 1;
1049         return data;
1050 }
1051
1052 /*
1053  * gpiolib gpio_direction_input callback function. The setting of the pin
1054  * mux function as 'gpio input' will be handled by the pinctrl susbsystem
1055  * interface.
1056  */
1057 static int rockchip_gpio_direction_input(struct gpio_chip *gc, unsigned offset)
1058 {
1059         return pinctrl_gpio_direction_input(gc->base + offset);
1060 }
1061
1062 /*
1063  * gpiolib gpio_direction_output callback function. The setting of the pin
1064  * mux function as 'gpio output' will be handled by the pinctrl susbsystem
1065  * interface.
1066  */
1067 static int rockchip_gpio_direction_output(struct gpio_chip *gc,
1068                                           unsigned offset, int value)
1069 {
1070         rockchip_gpio_set(gc, offset, value);
1071         return pinctrl_gpio_direction_output(gc->base + offset);
1072 }
1073
1074 /*
1075  * gpiolib gpio_to_irq callback function. Creates a mapping between a GPIO pin
1076  * and a virtual IRQ, if not already present.
1077  */
1078 static int rockchip_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
1079 {
1080         struct rockchip_pin_bank *bank = gc_to_pin_bank(gc);
1081         unsigned int virq;
1082
1083         if (!bank->domain)
1084                 return -ENXIO;
1085
1086         virq = irq_create_mapping(bank->domain, offset);
1087
1088         return (virq) ? : -ENXIO;
1089 }
1090
1091 static const struct gpio_chip rockchip_gpiolib_chip = {
1092         .request = rockchip_gpio_request,
1093         .free = rockchip_gpio_free,
1094         .set = rockchip_gpio_set,
1095         .get = rockchip_gpio_get,
1096         .direction_input = rockchip_gpio_direction_input,
1097         .direction_output = rockchip_gpio_direction_output,
1098         .to_irq = rockchip_gpio_to_irq,
1099         .owner = THIS_MODULE,
1100 };
1101
1102 /*
1103  * Interrupt handling
1104  */
1105
1106 static void rockchip_irq_demux(unsigned int irq, struct irq_desc *desc)
1107 {
1108         struct irq_chip *chip = irq_get_chip(irq);
1109         struct rockchip_pin_bank *bank = irq_get_handler_data(irq);
1110         u32 polarity = 0, data = 0;
1111         u32 pend;
1112         bool edge_changed = false;
1113
1114         dev_dbg(bank->drvdata->dev, "got irq for bank %s\n", bank->name);
1115
1116         chained_irq_enter(chip, desc);
1117
1118         pend = readl_relaxed(bank->reg_base + GPIO_INT_STATUS);
1119
1120         if (bank->toggle_edge_mode) {
1121                 polarity = readl_relaxed(bank->reg_base +
1122                                          GPIO_INT_POLARITY);
1123                 data = readl_relaxed(bank->reg_base + GPIO_EXT_PORT);
1124         }
1125
1126         while (pend) {
1127                 unsigned int virq;
1128
1129                 irq = __ffs(pend);
1130                 pend &= ~BIT(irq);
1131                 virq = irq_linear_revmap(bank->domain, irq);
1132
1133                 if (!virq) {
1134                         dev_err(bank->drvdata->dev, "unmapped irq %d\n", irq);
1135                         continue;
1136                 }
1137
1138                 dev_dbg(bank->drvdata->dev, "handling irq %d\n", irq);
1139
1140                 /*
1141                  * Triggering IRQ on both rising and falling edge
1142                  * needs manual intervention.
1143                  */
1144                 if (bank->toggle_edge_mode & BIT(irq)) {
1145                         if (data & BIT(irq))
1146                                 polarity &= ~BIT(irq);
1147                         else
1148                                 polarity |= BIT(irq);
1149
1150                         edge_changed = true;
1151                 }
1152
1153                 generic_handle_irq(virq);
1154         }
1155
1156         if (bank->toggle_edge_mode && edge_changed) {
1157                 /* Interrupt params should only be set with ints disabled */
1158                 data = readl_relaxed(bank->reg_base + GPIO_INTEN);
1159                 writel_relaxed(0, bank->reg_base + GPIO_INTEN);
1160                 writel(polarity, bank->reg_base + GPIO_INT_POLARITY);
1161                 writel(data, bank->reg_base + GPIO_INTEN);
1162         }
1163
1164         chained_irq_exit(chip, desc);
1165 }
1166
1167 static int rockchip_irq_set_type(struct irq_data *d, unsigned int type)
1168 {
1169         struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
1170         struct rockchip_pin_bank *bank = gc->private;
1171         u32 mask = BIT(d->hwirq);
1172         u32 polarity;
1173         u32 level;
1174         u32 data;
1175         int ret;
1176
1177         /* make sure the pin is configured as gpio input */
1178         ret = rockchip_set_mux(bank, d->hwirq, RK_FUNC_GPIO);
1179         if (ret < 0)
1180                 return ret;
1181
1182         data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR);
1183         data &= ~mask;
1184         writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR);
1185
1186         if (type & IRQ_TYPE_EDGE_BOTH)
1187                 __irq_set_handler_locked(d->irq, handle_edge_irq);
1188         else
1189                 __irq_set_handler_locked(d->irq, handle_level_irq);
1190
1191         irq_gc_lock(gc);
1192
1193         level = readl_relaxed(gc->reg_base + GPIO_INTTYPE_LEVEL);
1194         polarity = readl_relaxed(gc->reg_base + GPIO_INT_POLARITY);
1195
1196         switch (type) {
1197         case IRQ_TYPE_EDGE_BOTH:
1198                 bank->toggle_edge_mode |= mask;
1199                 level |= mask;
1200
1201                 /*
1202                  * Determine gpio state. If 1 next interrupt should be falling
1203                  * otherwise rising.
1204                  */
1205                 data = readl(bank->reg_base + GPIO_EXT_PORT);
1206                 if (data & mask)
1207                         polarity &= ~mask;
1208                 else
1209                         polarity |= mask;
1210                 break;
1211         case IRQ_TYPE_EDGE_RISING:
1212                 bank->toggle_edge_mode &= ~mask;
1213                 level |= mask;
1214                 polarity |= mask;
1215                 break;
1216         case IRQ_TYPE_EDGE_FALLING:
1217                 bank->toggle_edge_mode &= ~mask;
1218                 level |= mask;
1219                 polarity &= ~mask;
1220                 break;
1221         case IRQ_TYPE_LEVEL_HIGH:
1222                 bank->toggle_edge_mode &= ~mask;
1223                 level &= ~mask;
1224                 polarity |= mask;
1225                 break;
1226         case IRQ_TYPE_LEVEL_LOW:
1227                 bank->toggle_edge_mode &= ~mask;
1228                 level &= ~mask;
1229                 polarity &= ~mask;
1230                 break;
1231         default:
1232                 irq_gc_unlock(gc);
1233                 return -EINVAL;
1234         }
1235
1236         writel_relaxed(level, gc->reg_base + GPIO_INTTYPE_LEVEL);
1237         writel_relaxed(polarity, gc->reg_base + GPIO_INT_POLARITY);
1238
1239         irq_gc_unlock(gc);
1240
1241         return 0;
1242 }
1243
1244 static int rockchip_interrupts_register(struct platform_device *pdev,
1245                                                 struct rockchip_pinctrl *info)
1246 {
1247         struct rockchip_pin_ctrl *ctrl = info->ctrl;
1248         struct rockchip_pin_bank *bank = ctrl->pin_banks;
1249         unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
1250         struct irq_chip_generic *gc;
1251         int ret;
1252         int i;
1253
1254         for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
1255                 if (!bank->valid) {
1256                         dev_warn(&pdev->dev, "bank %s is not valid\n",
1257                                  bank->name);
1258                         continue;
1259                 }
1260
1261                 bank->domain = irq_domain_add_linear(bank->of_node, 32,
1262                                                 &irq_generic_chip_ops, NULL);
1263                 if (!bank->domain) {
1264                         dev_warn(&pdev->dev, "could not initialize irq domain for bank %s\n",
1265                                  bank->name);
1266                         continue;
1267                 }
1268
1269                 ret = irq_alloc_domain_generic_chips(bank->domain, 32, 1,
1270                                          "rockchip_gpio_irq", handle_level_irq,
1271                                          clr, 0, IRQ_GC_INIT_MASK_CACHE);
1272                 if (ret) {
1273                         dev_err(&pdev->dev, "could not alloc generic chips for bank %s\n",
1274                                 bank->name);
1275                         irq_domain_remove(bank->domain);
1276                         continue;
1277                 }
1278
1279                 gc = irq_get_domain_generic_chip(bank->domain, 0);
1280                 gc->reg_base = bank->reg_base;
1281                 gc->private = bank;
1282                 gc->chip_types[0].regs.mask = GPIO_INTEN;
1283                 gc->chip_types[0].regs.ack = GPIO_PORTS_EOI;
1284                 gc->chip_types[0].chip.irq_ack = irq_gc_ack_set_bit;
1285                 gc->chip_types[0].chip.irq_mask = irq_gc_mask_clr_bit;
1286                 gc->chip_types[0].chip.irq_unmask = irq_gc_mask_set_bit;
1287                 gc->chip_types[0].chip.irq_set_wake = irq_gc_set_wake;
1288                 gc->chip_types[0].chip.irq_set_type = rockchip_irq_set_type;
1289
1290                 irq_set_handler_data(bank->irq, bank);
1291                 irq_set_chained_handler(bank->irq, rockchip_irq_demux);
1292         }
1293
1294         return 0;
1295 }
1296
1297 static int rockchip_gpiolib_register(struct platform_device *pdev,
1298                                                 struct rockchip_pinctrl *info)
1299 {
1300         struct rockchip_pin_ctrl *ctrl = info->ctrl;
1301         struct rockchip_pin_bank *bank = ctrl->pin_banks;
1302         struct gpio_chip *gc;
1303         int ret;
1304         int i;
1305
1306         for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
1307                 if (!bank->valid) {
1308                         dev_warn(&pdev->dev, "bank %s is not valid\n",
1309                                  bank->name);
1310                         continue;
1311                 }
1312
1313                 bank->gpio_chip = rockchip_gpiolib_chip;
1314
1315                 gc = &bank->gpio_chip;
1316                 gc->base = bank->pin_base;
1317                 gc->ngpio = bank->nr_pins;
1318                 gc->dev = &pdev->dev;
1319                 gc->of_node = bank->of_node;
1320                 gc->label = bank->name;
1321
1322                 ret = gpiochip_add(gc);
1323                 if (ret) {
1324                         dev_err(&pdev->dev, "failed to register gpio_chip %s, error code: %d\n",
1325                                                         gc->label, ret);
1326                         goto fail;
1327                 }
1328         }
1329
1330         rockchip_interrupts_register(pdev, info);
1331
1332         return 0;
1333
1334 fail:
1335         for (--i, --bank; i >= 0; --i, --bank) {
1336                 if (!bank->valid)
1337                         continue;
1338
1339                 if (gpiochip_remove(&bank->gpio_chip))
1340                         dev_err(&pdev->dev, "gpio chip %s remove failed\n",
1341                                                         bank->gpio_chip.label);
1342         }
1343         return ret;
1344 }
1345
1346 static int rockchip_gpiolib_unregister(struct platform_device *pdev,
1347                                                 struct rockchip_pinctrl *info)
1348 {
1349         struct rockchip_pin_ctrl *ctrl = info->ctrl;
1350         struct rockchip_pin_bank *bank = ctrl->pin_banks;
1351         int ret = 0;
1352         int i;
1353
1354         for (i = 0; !ret && i < ctrl->nr_banks; ++i, ++bank) {
1355                 if (!bank->valid)
1356                         continue;
1357
1358                 ret = gpiochip_remove(&bank->gpio_chip);
1359         }
1360
1361         if (ret)
1362                 dev_err(&pdev->dev, "gpio chip remove failed\n");
1363
1364         return ret;
1365 }
1366
1367 static int rockchip_get_bank_data(struct rockchip_pin_bank *bank,
1368                                   struct device *dev)
1369 {
1370         struct resource res;
1371
1372         if (of_address_to_resource(bank->of_node, 0, &res)) {
1373                 dev_err(dev, "cannot find IO resource for bank\n");
1374                 return -ENOENT;
1375         }
1376
1377         bank->reg_base = devm_ioremap_resource(dev, &res);
1378         if (IS_ERR(bank->reg_base))
1379                 return PTR_ERR(bank->reg_base);
1380
1381         /*
1382          * special case, where parts of the pull setting-registers are
1383          * part of the PMU register space
1384          */
1385         if (of_device_is_compatible(bank->of_node,
1386                                     "rockchip,rk3188-gpio-bank0")) {
1387                 bank->bank_type = RK3188_BANK0;
1388
1389                 if (of_address_to_resource(bank->of_node, 1, &res)) {
1390                         dev_err(dev, "cannot find IO resource for bank\n");
1391                         return -ENOENT;
1392                 }
1393
1394                 bank->reg_pull = devm_ioremap_resource(dev, &res);
1395                 if (IS_ERR(bank->reg_pull))
1396                         return PTR_ERR(bank->reg_pull);
1397         } else {
1398                 bank->bank_type = COMMON_BANK;
1399         }
1400
1401         bank->irq = irq_of_parse_and_map(bank->of_node, 0);
1402
1403         bank->clk = of_clk_get(bank->of_node, 0);
1404         if (IS_ERR(bank->clk))
1405                 return PTR_ERR(bank->clk);
1406
1407         return clk_prepare_enable(bank->clk);
1408 }
1409
1410 static const struct of_device_id rockchip_pinctrl_dt_match[];
1411
1412 /* retrieve the soc specific data */
1413 static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data(
1414                                                 struct rockchip_pinctrl *d,
1415                                                 struct platform_device *pdev)
1416 {
1417         const struct of_device_id *match;
1418         struct device_node *node = pdev->dev.of_node;
1419         struct device_node *np;
1420         struct rockchip_pin_ctrl *ctrl;
1421         struct rockchip_pin_bank *bank;
1422         int i;
1423
1424         match = of_match_node(rockchip_pinctrl_dt_match, node);
1425         ctrl = (struct rockchip_pin_ctrl *)match->data;
1426
1427         for_each_child_of_node(node, np) {
1428                 if (!of_find_property(np, "gpio-controller", NULL))
1429                         continue;
1430
1431                 bank = ctrl->pin_banks;
1432                 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
1433                         if (!strcmp(bank->name, np->name)) {
1434                                 bank->of_node = np;
1435
1436                                 if (!rockchip_get_bank_data(bank, &pdev->dev))
1437                                         bank->valid = true;
1438
1439                                 break;
1440                         }
1441                 }
1442         }
1443
1444         bank = ctrl->pin_banks;
1445         for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
1446                 spin_lock_init(&bank->slock);
1447                 bank->drvdata = d;
1448                 bank->pin_base = ctrl->nr_pins;
1449                 ctrl->nr_pins += bank->nr_pins;
1450         }
1451
1452         return ctrl;
1453 }
1454
1455 static int rockchip_pinctrl_probe(struct platform_device *pdev)
1456 {
1457         struct rockchip_pinctrl *info;
1458         struct device *dev = &pdev->dev;
1459         struct rockchip_pin_ctrl *ctrl;
1460         struct resource *res;
1461         int ret;
1462
1463         if (!dev->of_node) {
1464                 dev_err(dev, "device tree node not found\n");
1465                 return -ENODEV;
1466         }
1467
1468         info = devm_kzalloc(dev, sizeof(struct rockchip_pinctrl), GFP_KERNEL);
1469         if (!info)
1470                 return -ENOMEM;
1471
1472         ctrl = rockchip_pinctrl_get_soc_data(info, pdev);
1473         if (!ctrl) {
1474                 dev_err(dev, "driver data not available\n");
1475                 return -EINVAL;
1476         }
1477         info->ctrl = ctrl;
1478         info->dev = dev;
1479
1480         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1481         info->reg_base = devm_ioremap_resource(&pdev->dev, res);
1482         if (IS_ERR(info->reg_base))
1483                 return PTR_ERR(info->reg_base);
1484
1485         /* The RK3188 has its pull registers in a separate place */
1486         if (ctrl->type == RK3188) {
1487                 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1488                 info->reg_pull = devm_ioremap_resource(&pdev->dev, res);
1489                 if (IS_ERR(info->reg_pull))
1490                         return PTR_ERR(info->reg_pull);
1491         }
1492
1493         ret = rockchip_gpiolib_register(pdev, info);
1494         if (ret)
1495                 return ret;
1496
1497         ret = rockchip_pinctrl_register(pdev, info);
1498         if (ret) {
1499                 rockchip_gpiolib_unregister(pdev, info);
1500                 return ret;
1501         }
1502
1503         platform_set_drvdata(pdev, info);
1504
1505         return 0;
1506 }
1507
1508 static struct rockchip_pin_bank rk2928_pin_banks[] = {
1509         PIN_BANK(0, 32, "gpio0"),
1510         PIN_BANK(1, 32, "gpio1"),
1511         PIN_BANK(2, 32, "gpio2"),
1512         PIN_BANK(3, 32, "gpio3"),
1513 };
1514
1515 static struct rockchip_pin_ctrl rk2928_pin_ctrl = {
1516                 .pin_banks              = rk2928_pin_banks,
1517                 .nr_banks               = ARRAY_SIZE(rk2928_pin_banks),
1518                 .label                  = "RK2928-GPIO",
1519                 .type                   = RK2928,
1520                 .mux_offset             = 0xa8,
1521                 .pull_calc_reg          = rk2928_calc_pull_reg_and_bit,
1522 };
1523
1524 static struct rockchip_pin_bank rk3066a_pin_banks[] = {
1525         PIN_BANK(0, 32, "gpio0"),
1526         PIN_BANK(1, 32, "gpio1"),
1527         PIN_BANK(2, 32, "gpio2"),
1528         PIN_BANK(3, 32, "gpio3"),
1529         PIN_BANK(4, 32, "gpio4"),
1530         PIN_BANK(6, 16, "gpio6"),
1531 };
1532
1533 static struct rockchip_pin_ctrl rk3066a_pin_ctrl = {
1534                 .pin_banks              = rk3066a_pin_banks,
1535                 .nr_banks               = ARRAY_SIZE(rk3066a_pin_banks),
1536                 .label                  = "RK3066a-GPIO",
1537                 .type                   = RK2928,
1538                 .mux_offset             = 0xa8,
1539                 .pull_calc_reg          = rk2928_calc_pull_reg_and_bit,
1540 };
1541
1542 static struct rockchip_pin_bank rk3066b_pin_banks[] = {
1543         PIN_BANK(0, 32, "gpio0"),
1544         PIN_BANK(1, 32, "gpio1"),
1545         PIN_BANK(2, 32, "gpio2"),
1546         PIN_BANK(3, 32, "gpio3"),
1547 };
1548
1549 static struct rockchip_pin_ctrl rk3066b_pin_ctrl = {
1550                 .pin_banks      = rk3066b_pin_banks,
1551                 .nr_banks       = ARRAY_SIZE(rk3066b_pin_banks),
1552                 .label          = "RK3066b-GPIO",
1553                 .type           = RK3066B,
1554                 .mux_offset     = 0x60,
1555 };
1556
1557 static struct rockchip_pin_bank rk3188_pin_banks[] = {
1558         PIN_BANK(0, 32, "gpio0"),
1559         PIN_BANK(1, 32, "gpio1"),
1560         PIN_BANK(2, 32, "gpio2"),
1561         PIN_BANK(3, 32, "gpio3"),
1562 };
1563
1564 static struct rockchip_pin_ctrl rk3188_pin_ctrl = {
1565                 .pin_banks              = rk3188_pin_banks,
1566                 .nr_banks               = ARRAY_SIZE(rk3188_pin_banks),
1567                 .label                  = "RK3188-GPIO",
1568                 .type                   = RK3188,
1569                 .mux_offset             = 0x60,
1570                 .pull_calc_reg          = rk3188_calc_pull_reg_and_bit,
1571 };
1572
1573 static const struct of_device_id rockchip_pinctrl_dt_match[] = {
1574         { .compatible = "rockchip,rk2928-pinctrl",
1575                 .data = (void *)&rk2928_pin_ctrl },
1576         { .compatible = "rockchip,rk3066a-pinctrl",
1577                 .data = (void *)&rk3066a_pin_ctrl },
1578         { .compatible = "rockchip,rk3066b-pinctrl",
1579                 .data = (void *)&rk3066b_pin_ctrl },
1580         { .compatible = "rockchip,rk3188-pinctrl",
1581                 .data = (void *)&rk3188_pin_ctrl },
1582         {},
1583 };
1584 MODULE_DEVICE_TABLE(of, rockchip_pinctrl_dt_match);
1585
1586 static struct platform_driver rockchip_pinctrl_driver = {
1587         .probe          = rockchip_pinctrl_probe,
1588         .driver = {
1589                 .name   = "rockchip-pinctrl",
1590                 .owner  = THIS_MODULE,
1591                 .of_match_table = rockchip_pinctrl_dt_match,
1592         },
1593 };
1594
1595 static int __init rockchip_pinctrl_drv_register(void)
1596 {
1597         return platform_driver_register(&rockchip_pinctrl_driver);
1598 }
1599 postcore_initcall(rockchip_pinctrl_drv_register);
1600
1601 MODULE_AUTHOR("Heiko Stuebner <heiko@sntech.de>");
1602 MODULE_DESCRIPTION("Rockchip pinctrl driver");
1603 MODULE_LICENSE("GPL v2");