drivers/pinctrl/pinctrl-single.c

   1 /*
   2  * Generic device tree based pinctrl driver for one register per pin
   3  * type pinmux controllers
   4  *
   5  * Copyright (C) 2012 Texas Instruments, Inc.
   6  *
   7  * This file is licensed under the terms of the GNU General Public
   8  * License version 2. This program is licensed "as is" without any
   9  * warranty of any kind, whether express or implied.
  10  */
  11
  12 #include <linux/init.h>
  13 #include <linux/module.h>
  14 #include <linux/io.h>
  15 #include <linux/slab.h>
  16 #include <linux/err.h>
  17 #include <linux/list.h>
  18 #include <linux/interrupt.h>
  19
  20 #include <linux/irqchip/chained_irq.h>
  21
  22 #include <linux/of.h>
  23 #include <linux/of_device.h>
  24 #include <linux/of_address.h>
  25 #include <linux/of_irq.h>
  26
  27 #include <linux/pinctrl/pinctrl.h>
  28 #include <linux/pinctrl/pinmux.h>
  29 #include <linux/pinctrl/pinconf-generic.h>
  30
  31 #include <linux/platform_data/pinctrl-single.h>
  32
  33 #include "core.h"
  34 #include "pinconf.h"
  35
  36 #define DRIVER_NAME                     "pinctrl-single"
  37 #define PCS_MUX_PINS_NAME               "pinctrl-single,pins"
  38 #define PCS_MUX_BITS_NAME               "pinctrl-single,bits"
  39 #define PCS_REG_NAME_LEN                ((sizeof(unsigned long) * 2) + 3)
  40 #define PCS_OFF_DISABLED                ~0U
  41
  42 /**
  43  * struct pcs_pingroup - pingroups for a function
  44  * @np:         pingroup device node pointer
  45  * @name:       pingroup name
  46  * @gpins:      array of the pins in the group
  47  * @ngpins:     number of pins in the group
  48  * @node:       list node
  49  */
  50 struct pcs_pingroup {
  51         struct device_node *np;
  52         const char *name;
  53         int *gpins;
  54         int ngpins;
  55         struct list_head node;
  56 };
  57
  58 /**
  59  * struct pcs_func_vals - mux function register offset and value pair
  60  * @reg:        register virtual address
  61  * @val:        register value
  62  */
  63 struct pcs_func_vals {
  64         void __iomem *reg;
  65         unsigned val;
  66         unsigned mask;
  67 };
  68
  69 /**
  70  * struct pcs_conf_vals - pinconf parameter, pinconf register offset
  71  * and value, enable, disable, mask
  72  * @param:      config parameter
  73  * @val:        user input bits in the pinconf register
  74  * @enable:     enable bits in the pinconf register
  75  * @disable:    disable bits in the pinconf register
  76  * @mask:       mask bits in the register value
  77  */
  78 struct pcs_conf_vals {
  79         enum pin_config_param param;
  80         unsigned val;
  81         unsigned enable;
  82         unsigned disable;
  83         unsigned mask;
  84 };
  85
  86 /**
  87  * struct pcs_conf_type - pinconf property name, pinconf param pair
  88  * @name:       property name in DTS file
  89  * @param:      config parameter
  90  */
  91 struct pcs_conf_type {
  92         const char *name;
  93         enum pin_config_param param;
  94 };
  95
  96 /**
  97  * struct pcs_function - pinctrl function
  98  * @name:       pinctrl function name
  99  * @vals:       register and vals array
 100  * @nvals:      number of entries in vals array
 101  * @pgnames:    array of pingroup names the function uses
 102  * @npgnames:   number of pingroup names the function uses
 103  * @node:       list node
 104  */
 105 struct pcs_function {
 106         const char *name;
 107         struct pcs_func_vals *vals;
 108         unsigned nvals;
 109         const char **pgnames;
 110         int npgnames;
 111         struct pcs_conf_vals *conf;
 112         int nconfs;
 113         struct list_head node;
 114 };
 115
 116 /**
 117  * struct pcs_gpiofunc_range - pin ranges with same mux value of gpio function
 118  * @offset:     offset base of pins
 119  * @npins:      number pins with the same mux value of gpio function
 120  * @gpiofunc:   mux value of gpio function
 121  * @node:       list node
 122  */
 123 struct pcs_gpiofunc_range {
 124         unsigned offset;
 125         unsigned npins;
 126         unsigned gpiofunc;
 127         struct list_head node;
 128 };
 129
 130 /**
 131  * struct pcs_data - wrapper for data needed by pinctrl framework
 132  * @pa:         pindesc array
 133  * @cur:        index to current element
 134  *
 135  * REVISIT: We should be able to drop this eventually by adding
 136  * support for registering pins individually in the pinctrl
 137  * framework for those drivers that don't need a static array.
 138  */
 139 struct pcs_data {
 140         struct pinctrl_pin_desc *pa;
 141         int cur;
 142 };
 143
 144 /**
 145  * struct pcs_name - register name for a pin
 146  * @name:       name of the pinctrl register
 147  *
 148  * REVISIT: We may want to make names optional in the pinctrl
 149  * framework as some drivers may not care about pin names to
 150  * avoid kernel bloat. The pin names can be deciphered by user
 151  * space tools using debugfs based on the register address and
 152  * SoC packaging information.
 153  */
 154 struct pcs_name {
 155         char name[PCS_REG_NAME_LEN];
 156 };
 157
 158 /**
 159  * struct pcs_soc_data - SoC specific settings
 160  * @flags:      initial SoC specific PCS_FEAT_xxx values
 161  * @irq:        optional interrupt for the controller
 162  * @irq_enable_mask:    optional SoC specific interrupt enable mask
 163  * @irq_status_mask:    optional SoC specific interrupt status mask
 164  * @rearm:      optional SoC specific wake-up rearm function
 165  */
 166 struct pcs_soc_data {
 167         unsigned flags;
 168         int irq;
 169         unsigned irq_enable_mask;
 170         unsigned irq_status_mask;
 171         void (*rearm)(void);
 172 };
 173
 174 /**
 175  * struct pcs_device - pinctrl device instance
 176  * @res:        resources
 177  * @base:       virtual address of the controller
 178  * @size:       size of the ioremapped area
 179  * @dev:        device entry
 180  * @pctl:       pin controller device
 181  * @flags:      mask of PCS_FEAT_xxx values
 182  * @lock:       spinlock for register access
 183  * @mutex:      mutex protecting the lists
 184  * @width:      bits per mux register
 185  * @fmask:      function register mask
 186  * @fshift:     function register shift
 187  * @foff:       value to turn mux off
 188  * @fmax:       max number of functions in fmask
 189  * @bits_per_pin:number of bits per pin
 190  * @names:      array of register names for pins
 191  * @pins:       physical pins on the SoC
 192  * @pgtree:     pingroup index radix tree
 193  * @ftree:      function index radix tree
 194  * @pingroups:  list of pingroups
 195  * @functions:  list of functions
 196  * @gpiofuncs:  list of gpio functions
 197  * @irqs:       list of interrupt registers
 198  * @chip:       chip container for this instance
 199  * @domain:     IRQ domain for this instance
 200  * @ngroups:    number of pingroups
 201  * @nfuncs:     number of functions
 202  * @desc:       pin controller descriptor
 203  * @read:       register read function to use
 204  * @write:      register write function to use
 205  */
 206 struct pcs_device {
 207         struct resource *res;
 208         void __iomem *base;
 209         unsigned size;
 210         struct device *dev;
 211         struct pinctrl_dev *pctl;
 212         unsigned flags;
 213 #define PCS_QUIRK_SHARED_IRQ    (1 << 2)
 214 #define PCS_FEAT_IRQ            (1 << 1)
 215 #define PCS_FEAT_PINCONF        (1 << 0)
 216         struct pcs_soc_data socdata;
 217         raw_spinlock_t lock;
 218         struct mutex mutex;
 219         unsigned width;
 220         unsigned fmask;
 221         unsigned fshift;
 222         unsigned foff;
 223         unsigned fmax;
 224         bool bits_per_mux;
 225         unsigned bits_per_pin;
 226         struct pcs_name *names;
 227         struct pcs_data pins;
 228         struct radix_tree_root pgtree;
 229         struct radix_tree_root ftree;
 230         struct list_head pingroups;
 231         struct list_head functions;
 232         struct list_head gpiofuncs;
 233         struct list_head irqs;
 234         struct irq_chip chip;
 235         struct irq_domain *domain;
 236         unsigned ngroups;
 237         unsigned nfuncs;
 238         struct pinctrl_desc desc;
 239         unsigned (*read)(void __iomem *reg);
 240         void (*write)(unsigned val, void __iomem *reg);
 241 };
 242
 243 #define PCS_QUIRK_HAS_SHARED_IRQ        (pcs->flags & PCS_QUIRK_SHARED_IRQ)
 244 #define PCS_HAS_IRQ             (pcs->flags & PCS_FEAT_IRQ)
 245 #define PCS_HAS_PINCONF         (pcs->flags & PCS_FEAT_PINCONF)
 246
 247 static int pcs_pinconf_get(struct pinctrl_dev *pctldev, unsigned pin,
 248                            unsigned long *config);
 249 static int pcs_pinconf_set(struct pinctrl_dev *pctldev, unsigned pin,
 250                            unsigned long *configs, unsigned num_configs);
 251
 252 static enum pin_config_param pcs_bias[] = {
 253         PIN_CONFIG_BIAS_PULL_DOWN,
 254         PIN_CONFIG_BIAS_PULL_UP,
 255 };
 256
 257 /*
 258  * REVISIT: Reads and writes could eventually use regmap or something
 259  * generic. But at least on omaps, some mux registers are performance
 260  * critical as they may need to be remuxed every time before and after
 261  * idle. Adding tests for register access width for every read and
 262  * write like regmap is doing is not desired, and caching the registers
 263  * does not help in this case.
 264  */
 265
 266 static unsigned __maybe_unused pcs_readb(void __iomem *reg)
 267 {
 268         return readb(reg);
 269 }
 270
 271 static unsigned __maybe_unused pcs_readw(void __iomem *reg)
 272 {
 273         return readw(reg);
 274 }
 275
 276 static unsigned __maybe_unused pcs_readl(void __iomem *reg)
 277 {
 278         return readl(reg);
 279 }
 280
 281 static void __maybe_unused pcs_writeb(unsigned val, void __iomem *reg)
 282 {
 283         writeb(val, reg);
 284 }
 285
 286 static void __maybe_unused pcs_writew(unsigned val, void __iomem *reg)
 287 {
 288         writew(val, reg);
 289 }
 290
 291 static void __maybe_unused pcs_writel(unsigned val, void __iomem *reg)
 292 {
 293         writel(val, reg);
 294 }
 295
 296 static int pcs_get_groups_count(struct pinctrl_dev *pctldev)
 297 {
 298         struct pcs_device *pcs;
 299
 300         pcs = pinctrl_dev_get_drvdata(pctldev);
 301
 302         return pcs->ngroups;
 303 }
 304
 305 static const char *pcs_get_group_name(struct pinctrl_dev *pctldev,
 306                                         unsigned gselector)
 307 {
 308         struct pcs_device *pcs;
 309         struct pcs_pingroup *group;
 310
 311         pcs = pinctrl_dev_get_drvdata(pctldev);
 312         group = radix_tree_lookup(&pcs->pgtree, gselector);
 313         if (!group) {
 314                 dev_err(pcs->dev, "%s could not find pingroup%i\n",
 315                         __func__, gselector);
 316                 return NULL;
 317         }
 318
 319         return group->name;
 320 }
 321
 322 static int pcs_get_group_pins(struct pinctrl_dev *pctldev,
 323                                         unsigned gselector,
 324                                         const unsigned **pins,
 325                                         unsigned *npins)
 326 {
 327         struct pcs_device *pcs;
 328         struct pcs_pingroup *group;
 329
 330         pcs = pinctrl_dev_get_drvdata(pctldev);
 331         group = radix_tree_lookup(&pcs->pgtree, gselector);
 332         if (!group) {
 333                 dev_err(pcs->dev, "%s could not find pingroup%i\n",
 334                         __func__, gselector);
 335                 return -EINVAL;
 336         }
 337
 338         *pins = group->gpins;
 339         *npins = group->ngpins;
 340
 341         return 0;
 342 }
 343
 344 static void pcs_pin_dbg_show(struct pinctrl_dev *pctldev,
 345                                         struct seq_file *s,
 346                                         unsigned pin)
 347 {
 348         struct pcs_device *pcs;
 349         unsigned val, mux_bytes;
 350
 351         pcs = pinctrl_dev_get_drvdata(pctldev);
 352
 353         mux_bytes = pcs->width / BITS_PER_BYTE;
 354         val = pcs->read(pcs->base + pin * mux_bytes);
 355
 356         seq_printf(s, "%08x %s " , val, DRIVER_NAME);
 357 }
 358
 359 static void pcs_dt_free_map(struct pinctrl_dev *pctldev,
 360                                 struct pinctrl_map *map, unsigned num_maps)
 361 {
 362         struct pcs_device *pcs;
 363
 364         pcs = pinctrl_dev_get_drvdata(pctldev);
 365         devm_kfree(pcs->dev, map);
 366 }
 367
 368 static int pcs_dt_node_to_map(struct pinctrl_dev *pctldev,
 369                                 struct device_node *np_config,
 370                                 struct pinctrl_map **map, unsigned *num_maps);
 371
 372 static const struct pinctrl_ops pcs_pinctrl_ops = {
 373         .get_groups_count = pcs_get_groups_count,
 374         .get_group_name = pcs_get_group_name,
 375         .get_group_pins = pcs_get_group_pins,
 376         .pin_dbg_show = pcs_pin_dbg_show,
 377         .dt_node_to_map = pcs_dt_node_to_map,
 378         .dt_free_map = pcs_dt_free_map,
 379 };
 380
 381 static int pcs_get_functions_count(struct pinctrl_dev *pctldev)
 382 {
 383         struct pcs_device *pcs;
 384
 385         pcs = pinctrl_dev_get_drvdata(pctldev);
 386
 387         return pcs->nfuncs;
 388 }
 389
 390 static const char *pcs_get_function_name(struct pinctrl_dev *pctldev,
 391                                                 unsigned fselector)
 392 {
 393         struct pcs_device *pcs;
 394         struct pcs_function *func;
 395
 396         pcs = pinctrl_dev_get_drvdata(pctldev);
 397         func = radix_tree_lookup(&pcs->ftree, fselector);
 398         if (!func) {
 399                 dev_err(pcs->dev, "%s could not find function%i\n",
 400                         __func__, fselector);
 401                 return NULL;
 402         }
 403
 404         return func->name;
 405 }
 406
 407 static int pcs_get_function_groups(struct pinctrl_dev *pctldev,
 408                                         unsigned fselector,
 409                                         const char * const **groups,
 410                                         unsigned * const ngroups)
 411 {
 412         struct pcs_device *pcs;
 413         struct pcs_function *func;
 414
 415         pcs = pinctrl_dev_get_drvdata(pctldev);
 416         func = radix_tree_lookup(&pcs->ftree, fselector);
 417         if (!func) {
 418                 dev_err(pcs->dev, "%s could not find function%i\n",
 419                         __func__, fselector);
 420                 return -EINVAL;
 421         }
 422         *groups = func->pgnames;
 423         *ngroups = func->npgnames;
 424
 425         return 0;
 426 }
 427
 428 static int pcs_get_function(struct pinctrl_dev *pctldev, unsigned pin,
 429                             struct pcs_function **func)
 430 {
 431         struct pcs_device *pcs = pinctrl_dev_get_drvdata(pctldev);
 432         struct pin_desc *pdesc = pin_desc_get(pctldev, pin);
 433         const struct pinctrl_setting_mux *setting;
 434         unsigned fselector;
 435
 436         /* If pin is not described in DTS & enabled, mux_setting is NULL. */
 437         setting = pdesc->mux_setting;
 438         if (!setting)
 439                 return -ENOTSUPP;
 440         fselector = setting->func;
 441         *func = radix_tree_lookup(&pcs->ftree, fselector);
 442         if (!(*func)) {
 443                 dev_err(pcs->dev, "%s could not find function%i\n",
 444                         __func__, fselector);
 445                 return -ENOTSUPP;
 446         }
 447         return 0;
 448 }
 449
 450 static int pcs_enable(struct pinctrl_dev *pctldev, unsigned fselector,
 451         unsigned group)
 452 {
 453         struct pcs_device *pcs;
 454         struct pcs_function *func;
 455         int i;
 456
 457         pcs = pinctrl_dev_get_drvdata(pctldev);
 458         /* If function mask is null, needn't enable it. */
 459         if (!pcs->fmask)
 460                 return 0;
 461         func = radix_tree_lookup(&pcs->ftree, fselector);
 462         if (!func)
 463                 return -EINVAL;
 464
 465         dev_dbg(pcs->dev, "enabling %s function%i\n",
 466                 func->name, fselector);
 467
 468         for (i = 0; i < func->nvals; i++) {
 469                 struct pcs_func_vals *vals;
 470                 unsigned long flags;
 471                 unsigned val, mask;
 472
 473                 vals = &func->vals[i];
 474                 raw_spin_lock_irqsave(&pcs->lock, flags);
 475                 val = pcs->read(vals->reg);
 476
 477                 if (pcs->bits_per_mux)
 478                         mask = vals->mask;
 479                 else
 480                         mask = pcs->fmask;
 481
 482                 val &= ~mask;
 483                 val |= (vals->val & mask);
 484                 pcs->write(val, vals->reg);
 485                 raw_spin_unlock_irqrestore(&pcs->lock, flags);
 486         }
 487
 488         return 0;
 489 }
 490
 491 static void pcs_disable(struct pinctrl_dev *pctldev, unsigned fselector,
 492                                         unsigned group)
 493 {
 494         struct pcs_device *pcs;
 495         struct pcs_function *func;
 496         int i;
 497
 498         pcs = pinctrl_dev_get_drvdata(pctldev);
 499         /* If function mask is null, needn't disable it. */
 500         if (!pcs->fmask)
 501                 return;
 502
 503         func = radix_tree_lookup(&pcs->ftree, fselector);
 504         if (!func) {
 505                 dev_err(pcs->dev, "%s could not find function%i\n",
 506                         __func__, fselector);
 507                 return;
 508         }
 509
 510         /*
 511          * Ignore disable if function-off is not specified. Some hardware
 512          * does not have clearly defined disable function. For pin specific
 513          * off modes, you can use alternate named states as described in
 514          * pinctrl-bindings.txt.
 515          */
 516         if (pcs->foff == PCS_OFF_DISABLED) {
 517                 dev_dbg(pcs->dev, "ignoring disable for %s function%i\n",
 518                         func->name, fselector);
 519                 return;
 520         }
 521
 522         dev_dbg(pcs->dev, "disabling function%i %s\n",
 523                 fselector, func->name);
 524
 525         for (i = 0; i < func->nvals; i++) {
 526                 struct pcs_func_vals *vals;
 527                 unsigned long flags;
 528                 unsigned val;
 529
 530                 vals = &func->vals[i];
 531                 raw_spin_lock_irqsave(&pcs->lock, flags);
 532                 val = pcs->read(vals->reg);
 533                 val &= ~pcs->fmask;
 534                 val |= pcs->foff << pcs->fshift;
 535                 pcs->write(val, vals->reg);
 536                 raw_spin_unlock_irqrestore(&pcs->lock, flags);
 537         }
 538 }
 539
 540 static int pcs_request_gpio(struct pinctrl_dev *pctldev,
 541                             struct pinctrl_gpio_range *range, unsigned pin)
 542 {
 543         struct pcs_device *pcs = pinctrl_dev_get_drvdata(pctldev);
 544         struct pcs_gpiofunc_range *frange = NULL;
 545         struct list_head *pos, *tmp;
 546         int mux_bytes = 0;
 547         unsigned data;
 548
 549         /* If function mask is null, return directly. */
 550         if (!pcs->fmask)
 551                 return -ENOTSUPP;
 552
 553         list_for_each_safe(pos, tmp, &pcs->gpiofuncs) {
 554                 frange = list_entry(pos, struct pcs_gpiofunc_range, node);
 555                 if (pin >= frange->offset + frange->npins
 556                         || pin < frange->offset)
 557                         continue;
 558                 mux_bytes = pcs->width / BITS_PER_BYTE;
 559                 data = pcs->read(pcs->base + pin * mux_bytes) & ~pcs->fmask;
 560                 data |= frange->gpiofunc;
 561                 pcs->write(data, pcs->base + pin * mux_bytes);
 562                 break;
 563         }
 564         return 0;
 565 }
 566
 567 static const struct pinmux_ops pcs_pinmux_ops = {
 568         .get_functions_count = pcs_get_functions_count,
 569         .get_function_name = pcs_get_function_name,
 570         .get_function_groups = pcs_get_function_groups,
 571         .enable = pcs_enable,
 572         .disable = pcs_disable,
 573         .gpio_request_enable = pcs_request_gpio,
 574 };
 575
 576 /* Clear BIAS value */
 577 static void pcs_pinconf_clear_bias(struct pinctrl_dev *pctldev, unsigned pin)
 578 {
 579         unsigned long config;
 580         int i;
 581         for (i = 0; i < ARRAY_SIZE(pcs_bias); i++) {
 582                 config = pinconf_to_config_packed(pcs_bias[i], 0);
 583                 pcs_pinconf_set(pctldev, pin, &config, 1);
 584         }
 585 }
 586
 587 /*
 588  * Check whether PIN_CONFIG_BIAS_DISABLE is valid.
 589  * It's depend on that PULL_DOWN & PULL_UP configs are all invalid.
 590  */
 591 static bool pcs_pinconf_bias_disable(struct pinctrl_dev *pctldev, unsigned pin)
 592 {
 593         unsigned long config;
 594         int i;
 595
 596         for (i = 0; i < ARRAY_SIZE(pcs_bias); i++) {
 597                 config = pinconf_to_config_packed(pcs_bias[i], 0);
 598                 if (!pcs_pinconf_get(pctldev, pin, &config))
 599                         goto out;
 600         }
 601         return true;
 602 out:
 603         return false;
 604 }
 605
 606 static int pcs_pinconf_get(struct pinctrl_dev *pctldev,
 607                                 unsigned pin, unsigned long *config)
 608 {
 609         struct pcs_device *pcs = pinctrl_dev_get_drvdata(pctldev);
 610         struct pcs_function *func;
 611         enum pin_config_param param;
 612         unsigned offset = 0, data = 0, i, j, ret;
 613
 614         ret = pcs_get_function(pctldev, pin, &func);
 615         if (ret)
 616                 return ret;
 617
 618         for (i = 0; i < func->nconfs; i++) {
 619                 param = pinconf_to_config_param(*config);
 620                 if (param == PIN_CONFIG_BIAS_DISABLE) {
 621                         if (pcs_pinconf_bias_disable(pctldev, pin)) {
 622                                 *config = 0;
 623                                 return 0;
 624                         } else {
 625                                 return -ENOTSUPP;
 626                         }
 627                 } else if (param != func->conf[i].param) {
 628                         continue;
 629                 }
 630
 631                 offset = pin * (pcs->width / BITS_PER_BYTE);
 632                 data = pcs->read(pcs->base + offset) & func->conf[i].mask;
 633                 switch (func->conf[i].param) {
 634                 /* 4 parameters */
 635                 case PIN_CONFIG_BIAS_PULL_DOWN:
 636                 case PIN_CONFIG_BIAS_PULL_UP:
 637                 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
 638                         if ((data != func->conf[i].enable) ||
 639                             (data == func->conf[i].disable))
 640                                 return -ENOTSUPP;
 641                         *config = 0;
 642                         break;
 643                 /* 2 parameters */
 644                 case PIN_CONFIG_INPUT_SCHMITT:
 645                         for (j = 0; j < func->nconfs; j++) {
 646                                 switch (func->conf[j].param) {
 647                                 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
 648                                         if (data != func->conf[j].enable)
 649                                                 return -ENOTSUPP;
 650                                         break;
 651                                 default:
 652                                         break;
 653                                 }
 654                         }
 655                         *config = data;
 656                         break;
 657                 case PIN_CONFIG_DRIVE_STRENGTH:
 658                 case PIN_CONFIG_SLEW_RATE:
 659                 default:
 660                         *config = data;
 661                         break;
 662                 }
 663                 return 0;
 664         }
 665         return -ENOTSUPP;
 666 }
 667
 668 static int pcs_pinconf_set(struct pinctrl_dev *pctldev,
 669                                 unsigned pin, unsigned long *configs,
 670                                 unsigned num_configs)
 671 {
 672         struct pcs_device *pcs = pinctrl_dev_get_drvdata(pctldev);
 673         struct pcs_function *func;
 674         unsigned offset = 0, shift = 0, i, data, ret;
 675         u16 arg;
 676         int j;
 677
 678         ret = pcs_get_function(pctldev, pin, &func);
 679         if (ret)
 680                 return ret;
 681
 682         for (j = 0; j < num_configs; j++) {
 683                 for (i = 0; i < func->nconfs; i++) {
 684                         if (pinconf_to_config_param(configs[j])
 685                                 != func->conf[i].param)
 686                                 continue;
 687
 688                         offset = pin * (pcs->width / BITS_PER_BYTE);
 689                         data = pcs->read(pcs->base + offset);
 690                         arg = pinconf_to_config_argument(configs[j]);
 691                         switch (func->conf[i].param) {
 692                         /* 2 parameters */
 693                         case PIN_CONFIG_INPUT_SCHMITT:
 694                         case PIN_CONFIG_DRIVE_STRENGTH:
 695                         case PIN_CONFIG_SLEW_RATE:
 696                                 shift = ffs(func->conf[i].mask) - 1;
 697                                 data &= ~func->conf[i].mask;
 698                                 data |= (arg << shift) & func->conf[i].mask;
 699                                 break;
 700                         /* 4 parameters */
 701                         case PIN_CONFIG_BIAS_DISABLE:
 702                                 pcs_pinconf_clear_bias(pctldev, pin);
 703                                 break;
 704                         case PIN_CONFIG_BIAS_PULL_DOWN:
 705                         case PIN_CONFIG_BIAS_PULL_UP:
 706                                 if (arg)
 707                                         pcs_pinconf_clear_bias(pctldev, pin);
 708                                 /* fall through */
 709                         case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
 710                                 data &= ~func->conf[i].mask;
 711                                 if (arg)
 712                                         data |= func->conf[i].enable;
 713                                 else
 714                                         data |= func->conf[i].disable;
 715                                 break;
 716                         default:
 717                                 return -ENOTSUPP;
 718                         }
 719                         pcs->write(data, pcs->base + offset);
 720
 721                         break;
 722                 }
 723                 if (i >= func->nconfs)
 724                         return -ENOTSUPP;
 725         } /* for each config */
 726
 727         return 0;
 728 }
 729
 730 static int pcs_pinconf_group_get(struct pinctrl_dev *pctldev,
 731                                 unsigned group, unsigned long *config)
 732 {
 733         const unsigned *pins;
 734         unsigned npins, old = 0;
 735         int i, ret;
 736
 737         ret = pcs_get_group_pins(pctldev, group, &pins, &npins);
 738         if (ret)
 739                 return ret;
 740         for (i = 0; i < npins; i++) {
 741                 if (pcs_pinconf_get(pctldev, pins[i], config))
 742                         return -ENOTSUPP;
 743                 /* configs do not match between two pins */
 744                 if (i && (old != *config))
 745                         return -ENOTSUPP;
 746                 old = *config;
 747         }
 748         return 0;
 749 }
 750
 751 static int pcs_pinconf_group_set(struct pinctrl_dev *pctldev,
 752                                 unsigned group, unsigned long *configs,
 753                                 unsigned num_configs)
 754 {
 755         const unsigned *pins;
 756         unsigned npins;
 757         int i, ret;
 758
 759         ret = pcs_get_group_pins(pctldev, group, &pins, &npins);
 760         if (ret)
 761                 return ret;
 762         for (i = 0; i < npins; i++) {
 763                 if (pcs_pinconf_set(pctldev, pins[i], configs, num_configs))
 764                         return -ENOTSUPP;
 765         }
 766         return 0;
 767 }
 768
 769 static void pcs_pinconf_dbg_show(struct pinctrl_dev *pctldev,
 770                                 struct seq_file *s, unsigned pin)
 771 {
 772 }
 773
 774 static void pcs_pinconf_group_dbg_show(struct pinctrl_dev *pctldev,
 775                                 struct seq_file *s, unsigned selector)
 776 {
 777 }
 778
 779 static void pcs_pinconf_config_dbg_show(struct pinctrl_dev *pctldev,
 780                                         struct seq_file *s,
 781                                         unsigned long config)
 782 {
 783         pinconf_generic_dump_config(pctldev, s, config);
 784 }
 785
 786 static const struct pinconf_ops pcs_pinconf_ops = {
 787         .pin_config_get = pcs_pinconf_get,
 788         .pin_config_set = pcs_pinconf_set,
 789         .pin_config_group_get = pcs_pinconf_group_get,
 790         .pin_config_group_set = pcs_pinconf_group_set,
 791         .pin_config_dbg_show = pcs_pinconf_dbg_show,
 792         .pin_config_group_dbg_show = pcs_pinconf_group_dbg_show,
 793         .pin_config_config_dbg_show = pcs_pinconf_config_dbg_show,
 794         .is_generic = true,
 795 };
 796
 797 /**
 798  * pcs_add_pin() - add a pin to the static per controller pin array
 799  * @pcs: pcs driver instance
 800  * @offset: register offset from base
 801  */
 802 static int pcs_add_pin(struct pcs_device *pcs, unsigned offset,
 803                 unsigned pin_pos)
 804 {
 805         struct pinctrl_pin_desc *pin;
 806         struct pcs_name *pn;
 807         int i;
 808
 809         i = pcs->pins.cur;
 810         if (i >= pcs->desc.npins) {
 811                 dev_err(pcs->dev, "too many pins, max %i\n",
 812                         pcs->desc.npins);
 813                 return -ENOMEM;
 814         }
 815
 816         pin = &pcs->pins.pa[i];
 817         pn = &pcs->names[i];
 818         sprintf(pn->name, "%lx.%d",
 819                 (unsigned long)pcs->res->start + offset, pin_pos);
 820         pin->name = pn->name;
 821         pin->number = i;
 822         pcs->pins.cur++;
 823
 824         return i;
 825 }
 826
 827 /**
 828  * pcs_allocate_pin_table() - adds all the pins for the pinctrl driver
 829  * @pcs: pcs driver instance
 830  *
 831  * In case of errors, resources are freed in pcs_free_resources.
 832  *
 833  * If your hardware needs holes in the address space, then just set
 834  * up multiple driver instances.
 835  */
 836 static int pcs_allocate_pin_table(struct pcs_device *pcs)
 837 {
 838         int mux_bytes, nr_pins, i;
 839         int num_pins_in_register = 0;
 840
 841         mux_bytes = pcs->width / BITS_PER_BYTE;
 842
 843         if (pcs->bits_per_mux) {
 844                 pcs->bits_per_pin = fls(pcs->fmask);
 845                 nr_pins = (pcs->size * BITS_PER_BYTE) / pcs->bits_per_pin;
 846                 num_pins_in_register = pcs->width / pcs->bits_per_pin;
 847         } else {
 848                 nr_pins = pcs->size / mux_bytes;
 849         }
 850
 851         dev_dbg(pcs->dev, "allocating %i pins\n", nr_pins);
 852         pcs->pins.pa = devm_kzalloc(pcs->dev,
 853                                 sizeof(*pcs->pins.pa) * nr_pins,
 854                                 GFP_KERNEL);
 855         if (!pcs->pins.pa)
 856                 return -ENOMEM;
 857
 858         pcs->names = devm_kzalloc(pcs->dev,
 859                                 sizeof(struct pcs_name) * nr_pins,
 860                                 GFP_KERNEL);
 861         if (!pcs->names)
 862                 return -ENOMEM;
 863
 864         pcs->desc.pins = pcs->pins.pa;
 865         pcs->desc.npins = nr_pins;
 866
 867         for (i = 0; i < pcs->desc.npins; i++) {
 868                 unsigned offset;
 869                 int res;
 870                 int byte_num;
 871                 int pin_pos = 0;
 872
 873                 if (pcs->bits_per_mux) {
 874                         byte_num = (pcs->bits_per_pin * i) / BITS_PER_BYTE;
 875                         offset = (byte_num / mux_bytes) * mux_bytes;
 876                         pin_pos = i % num_pins_in_register;
 877                 } else {
 878                         offset = i * mux_bytes;
 879                 }
 880                 res = pcs_add_pin(pcs, offset, pin_pos);
 881                 if (res < 0) {
 882                         dev_err(pcs->dev, "error adding pins: %i\n", res);
 883                         return res;
 884                 }
 885         }
 886
 887         return 0;
 888 }
 889
 890 /**
 891  * pcs_add_function() - adds a new function to the function list
 892  * @pcs: pcs driver instance
 893  * @np: device node of the mux entry
 894  * @name: name of the function
 895  * @vals: array of mux register value pairs used by the function
 896  * @nvals: number of mux register value pairs
 897  * @pgnames: array of pingroup names for the function
 898  * @npgnames: number of pingroup names
 899  */
 900 static struct pcs_function *pcs_add_function(struct pcs_device *pcs,
 901                                         struct device_node *np,
 902                                         const char *name,
 903                                         struct pcs_func_vals *vals,
 904                                         unsigned nvals,
 905                                         const char **pgnames,
 906                                         unsigned npgnames)
 907 {
 908         struct pcs_function *function;
 909
 910         function = devm_kzalloc(pcs->dev, sizeof(*function), GFP_KERNEL);
 911         if (!function)
 912                 return NULL;
 913
 914         function->name = name;
 915         function->vals = vals;
 916         function->nvals = nvals;
 917         function->pgnames = pgnames;
 918         function->npgnames = npgnames;
 919
 920         mutex_lock(&pcs->mutex);
 921         list_add_tail(&function->node, &pcs->functions);
 922         radix_tree_insert(&pcs->ftree, pcs->nfuncs, function);
 923         pcs->nfuncs++;
 924         mutex_unlock(&pcs->mutex);
 925
 926         return function;
 927 }
 928
 929 static void pcs_remove_function(struct pcs_device *pcs,
 930                                 struct pcs_function *function)
 931 {
 932         int i;
 933
 934         mutex_lock(&pcs->mutex);
 935         for (i = 0; i < pcs->nfuncs; i++) {
 936                 struct pcs_function *found;
 937
 938                 found = radix_tree_lookup(&pcs->ftree, i);
 939                 if (found == function)
 940                         radix_tree_delete(&pcs->ftree, i);
 941         }
 942         list_del(&function->node);
 943         mutex_unlock(&pcs->mutex);
 944 }
 945
 946 /**
 947  * pcs_add_pingroup() - add a pingroup to the pingroup list
 948  * @pcs: pcs driver instance
 949  * @np: device node of the mux entry
 950  * @name: name of the pingroup
 951  * @gpins: array of the pins that belong to the group
 952  * @ngpins: number of pins in the group
 953  */
 954 static int pcs_add_pingroup(struct pcs_device *pcs,
 955                                         struct device_node *np,
 956                                         const char *name,
 957                                         int *gpins,
 958                                         int ngpins)
 959 {
 960         struct pcs_pingroup *pingroup;
 961
 962         pingroup = devm_kzalloc(pcs->dev, sizeof(*pingroup), GFP_KERNEL);
 963         if (!pingroup)
 964                 return -ENOMEM;
 965
 966         pingroup->name = name;
 967         pingroup->np = np;
 968         pingroup->gpins = gpins;
 969         pingroup->ngpins = ngpins;
 970
 971         mutex_lock(&pcs->mutex);
 972         list_add_tail(&pingroup->node, &pcs->pingroups);
 973         radix_tree_insert(&pcs->pgtree, pcs->ngroups, pingroup);
 974         pcs->ngroups++;
 975         mutex_unlock(&pcs->mutex);
 976
 977         return 0;
 978 }
 979
 980 /**
 981  * pcs_get_pin_by_offset() - get a pin index based on the register offset
 982  * @pcs: pcs driver instance
 983  * @offset: register offset from the base
 984  *
 985  * Note that this is OK as long as the pins are in a static array.
 986  */
 987 static int pcs_get_pin_by_offset(struct pcs_device *pcs, unsigned offset)
 988 {
 989         unsigned index;
 990
 991         if (offset >= pcs->size) {
 992                 dev_err(pcs->dev, "mux offset out of range: 0x%x (0x%x)\n",
 993                         offset, pcs->size);
 994                 return -EINVAL;
 995         }
 996
 997         if (pcs->bits_per_mux)
 998                 index = (offset * BITS_PER_BYTE) / pcs->bits_per_pin;
 999         else
1000                 index = offset / (pcs->width / BITS_PER_BYTE);
1001
1002         return index;
1003 }
1004
1005 /*
1006  * check whether data matches enable bits or disable bits
1007  * Return value: 1 for matching enable bits, 0 for matching disable bits,
1008  *               and negative value for matching failure.
1009  */
1010 static int pcs_config_match(unsigned data, unsigned enable, unsigned disable)
1011 {
1012         int ret = -EINVAL;
1013
1014         if (data == enable)
1015                 ret = 1;
1016         else if (data == disable)
1017                 ret = 0;
1018         return ret;
1019 }
1020
1021 static void add_config(struct pcs_conf_vals **conf, enum pin_config_param param,
1022                        unsigned value, unsigned enable, unsigned disable,
1023                        unsigned mask)
1024 {
1025         (*conf)->param = param;
1026         (*conf)->val = value;
1027         (*conf)->enable = enable;
1028         (*conf)->disable = disable;
1029         (*conf)->mask = mask;
1030         (*conf)++;
1031 }
1032
1033 static void add_setting(unsigned long **setting, enum pin_config_param param,
1034                         unsigned arg)
1035 {
1036         **setting = pinconf_to_config_packed(param, arg);
1037         (*setting)++;
1038 }
1039
1040 /* add pinconf setting with 2 parameters */
1041 static void pcs_add_conf2(struct pcs_device *pcs, struct device_node *np,
1042                           const char *name, enum pin_config_param param,
1043                           struct pcs_conf_vals **conf, unsigned long **settings)
1044 {
1045         unsigned value[2], shift;
1046         int ret;
1047
1048         ret = of_property_read_u32_array(np, name, value, 2);
1049         if (ret)
1050                 return;
1051         /* set value & mask */
1052         value[0] &= value[1];
1053         shift = ffs(value[1]) - 1;
1054         /* skip enable & disable */
1055         add_config(conf, param, value[0], 0, 0, value[1]);
1056         add_setting(settings, param, value[0] >> shift);
1057 }
1058
1059 /* add pinconf setting with 4 parameters */
1060 static void pcs_add_conf4(struct pcs_device *pcs, struct device_node *np,
1061                           const char *name, enum pin_config_param param,
1062                           struct pcs_conf_vals **conf, unsigned long **settings)
1063 {
1064         unsigned value[4];
1065         int ret;
1066
1067         /* value to set, enable, disable, mask */
1068         ret = of_property_read_u32_array(np, name, value, 4);
1069         if (ret)
1070                 return;
1071         if (!value[3]) {
1072                 dev_err(pcs->dev, "mask field of the property can't be 0\n");
1073                 return;
1074         }
1075         value[0] &= value[3];
1076         value[1] &= value[3];
1077         value[2] &= value[3];
1078         ret = pcs_config_match(value[0], value[1], value[2]);
1079         if (ret < 0)
1080                 dev_dbg(pcs->dev, "failed to match enable or disable bits\n");
1081         add_config(conf, param, value[0], value[1], value[2], value[3]);
1082         add_setting(settings, param, ret);
1083 }
1084
1085 static int pcs_parse_pinconf(struct pcs_device *pcs, struct device_node *np,
1086                              struct pcs_function *func,
1087                              struct pinctrl_map **map)
1088
1089 {
1090         struct pinctrl_map *m = *map;
1091         int i = 0, nconfs = 0;
1092         unsigned long *settings = NULL, *s = NULL;
1093         struct pcs_conf_vals *conf = NULL;
1094         struct pcs_conf_type prop2[] = {
1095                 { "pinctrl-single,drive-strength", PIN_CONFIG_DRIVE_STRENGTH, },
1096                 { "pinctrl-single,slew-rate", PIN_CONFIG_SLEW_RATE, },
1097                 { "pinctrl-single,input-schmitt", PIN_CONFIG_INPUT_SCHMITT, },
1098         };
1099         struct pcs_conf_type prop4[] = {
1100                 { "pinctrl-single,bias-pullup", PIN_CONFIG_BIAS_PULL_UP, },
1101                 { "pinctrl-single,bias-pulldown", PIN_CONFIG_BIAS_PULL_DOWN, },
1102                 { "pinctrl-single,input-schmitt-enable",
1103                         PIN_CONFIG_INPUT_SCHMITT_ENABLE, },
1104         };
1105
1106         /* If pinconf isn't supported, don't parse properties in below. */
1107         if (!PCS_HAS_PINCONF)
1108                 return 0;
1109
1110         /* cacluate how much properties are supported in current node */
1111         for (i = 0; i < ARRAY_SIZE(prop2); i++) {
1112                 if (of_find_property(np, prop2[i].name, NULL))
1113                         nconfs++;
1114         }
1115         for (i = 0; i < ARRAY_SIZE(prop4); i++) {
1116                 if (of_find_property(np, prop4[i].name, NULL))
1117                         nconfs++;
1118         }
1119         if (!nconfs)
1120                 return 0;
1121
1122         func->conf = devm_kzalloc(pcs->dev,
1123                                   sizeof(struct pcs_conf_vals) * nconfs,
1124                                   GFP_KERNEL);
1125         if (!func->conf)
1126                 return -ENOMEM;
1127         func->nconfs = nconfs;
1128         conf = &(func->conf[0]);
1129         m++;
1130         settings = devm_kzalloc(pcs->dev, sizeof(unsigned long) * nconfs,
1131                                 GFP_KERNEL);
1132         if (!settings)
1133                 return -ENOMEM;
1134         s = &settings[0];
1135
1136         for (i = 0; i < ARRAY_SIZE(prop2); i++)
1137                 pcs_add_conf2(pcs, np, prop2[i].name, prop2[i].param,
1138                               &conf, &s);
1139         for (i = 0; i < ARRAY_SIZE(prop4); i++)
1140                 pcs_add_conf4(pcs, np, prop4[i].name, prop4[i].param,
1141                               &conf, &s);
1142         m->type = PIN_MAP_TYPE_CONFIGS_GROUP;
1143         m->data.configs.group_or_pin = np->name;
1144         m->data.configs.configs = settings;
1145         m->data.configs.num_configs = nconfs;
1146         return 0;
1147 }
1148
1149 static void pcs_free_pingroups(struct pcs_device *pcs);
1150
1151 /**
1152  * smux_parse_one_pinctrl_entry() - parses a device tree mux entry
1153  * @pcs: pinctrl driver instance
1154  * @np: device node of the mux entry
1155  * @map: map entry
1156  * @num_maps: number of map
1157  * @pgnames: pingroup names
1158  *
1159  * Note that this binding currently supports only sets of one register + value.
1160  *
1161  * Also note that this driver tries to avoid understanding pin and function
1162  * names because of the extra bloat they would cause especially in the case of
1163  * a large number of pins. This driver just sets what is specified for the board
1164  * in the .dts file. Further user space debugging tools can be developed to
1165  * decipher the pin and function names using debugfs.
1166  *
1167  * If you are concerned about the boot time, set up the static pins in
1168  * the bootloader, and only set up selected pins as device tree entries.
1169  */
1170 static int pcs_parse_one_pinctrl_entry(struct pcs_device *pcs,
1171                                                 struct device_node *np,
1172                                                 struct pinctrl_map **map,
1173                                                 unsigned *num_maps,
1174                                                 const char **pgnames)
1175 {
1176         struct pcs_func_vals *vals;
1177         const __be32 *mux;
1178         int size, rows, *pins, index = 0, found = 0, res = -ENOMEM;
1179         struct pcs_function *function;
1180
1181         mux = of_get_property(np, PCS_MUX_PINS_NAME, &size);
1182         if ((!mux) || (size < sizeof(*mux) * 2)) {
1183                 dev_err(pcs->dev, "bad data for mux %s\n",
1184                         np->name);
1185                 return -EINVAL;
1186         }
1187
1188         size /= sizeof(*mux);   /* Number of elements in array */
1189         rows = size / 2;
1190
1191         vals = devm_kzalloc(pcs->dev, sizeof(*vals) * rows, GFP_KERNEL);
1192         if (!vals)
1193                 return -ENOMEM;
1194
1195         pins = devm_kzalloc(pcs->dev, sizeof(*pins) * rows, GFP_KERNEL);
1196         if (!pins)
1197                 goto free_vals;
1198
1199         while (index < size) {
1200                 unsigned offset, val;
1201                 int pin;
1202
1203                 offset = be32_to_cpup(mux + index++);
1204                 val = be32_to_cpup(mux + index++);
1205                 vals[found].reg = pcs->base + offset;
1206                 vals[found].val = val;
1207
1208                 pin = pcs_get_pin_by_offset(pcs, offset);
1209                 if (pin < 0) {
1210                         dev_err(pcs->dev,
1211                                 "could not add functions for %s %ux\n",
1212                                 np->name, offset);
1213                         break;
1214                 }
1215                 pins[found++] = pin;
1216         }
1217
1218         pgnames[0] = np->name;
1219         function = pcs_add_function(pcs, np, np->name, vals, found, pgnames, 1);
1220         if (!function)
1221                 goto free_pins;
1222
1223         res = pcs_add_pingroup(pcs, np, np->name, pins, found);
1224         if (res < 0)
1225                 goto free_function;
1226
1227         (*map)->type = PIN_MAP_TYPE_MUX_GROUP;
1228         (*map)->data.mux.group = np->name;
1229         (*map)->data.mux.function = np->name;
1230
1231         if (PCS_HAS_PINCONF) {
1232                 res = pcs_parse_pinconf(pcs, np, function, map);
1233                 if (res)
1234                         goto free_pingroups;
1235                 *num_maps = 2;
1236         } else {
1237                 *num_maps = 1;
1238         }
1239         return 0;
1240
1241 free_pingroups:
1242         pcs_free_pingroups(pcs);
1243         *num_maps = 1;
1244 free_function:
1245         pcs_remove_function(pcs, function);
1246
1247 free_pins:
1248         devm_kfree(pcs->dev, pins);
1249
1250 free_vals:
1251         devm_kfree(pcs->dev, vals);
1252
1253         return res;
1254 }
1255
1256 #define PARAMS_FOR_BITS_PER_MUX 3
1257
1258 static int pcs_parse_bits_in_pinctrl_entry(struct pcs_device *pcs,
1259                                                 struct device_node *np,
1260                                                 struct pinctrl_map **map,
1261                                                 unsigned *num_maps,
1262                                                 const char **pgnames)
1263 {
1264         struct pcs_func_vals *vals;
1265         const __be32 *mux;
1266         int size, rows, *pins, index = 0, found = 0, res = -ENOMEM;
1267         int npins_in_row;
1268         struct pcs_function *function;
1269
1270         mux = of_get_property(np, PCS_MUX_BITS_NAME, &size);
1271
1272         if (!mux) {
1273                 dev_err(pcs->dev, "no valid property for %s\n", np->name);
1274                 return -EINVAL;
1275         }
1276
1277         if (size < (sizeof(*mux) * PARAMS_FOR_BITS_PER_MUX)) {
1278                 dev_err(pcs->dev, "bad data for %s\n", np->name);
1279                 return -EINVAL;
1280         }
1281
1282         /* Number of elements in array */
1283         size /= sizeof(*mux);
1284
1285         rows = size / PARAMS_FOR_BITS_PER_MUX;
1286         npins_in_row = pcs->width / pcs->bits_per_pin;
1287
1288         vals = devm_kzalloc(pcs->dev, sizeof(*vals) * rows * npins_in_row,
1289                         GFP_KERNEL);
1290         if (!vals)
1291                 return -ENOMEM;
1292
1293         pins = devm_kzalloc(pcs->dev, sizeof(*pins) * rows * npins_in_row,
1294                         GFP_KERNEL);
1295         if (!pins)
1296                 goto free_vals;
1297
1298         while (index < size) {
1299                 unsigned offset, val;
1300                 unsigned mask, bit_pos, val_pos, mask_pos, submask;
1301                 unsigned pin_num_from_lsb;
1302                 int pin;
1303
1304                 offset = be32_to_cpup(mux + index++);
1305                 val = be32_to_cpup(mux + index++);
1306                 mask = be32_to_cpup(mux + index++);
1307
1308                 /* Parse pins in each row from LSB */
1309                 while (mask) {
1310                         bit_pos = ffs(mask);
1311                         pin_num_from_lsb = bit_pos / pcs->bits_per_pin;
1312                         mask_pos = ((pcs->fmask) << (bit_pos - 1));
1313                         val_pos = val & mask_pos;
1314                         submask = mask & mask_pos;
1315                         mask &= ~mask_pos;
1316
1317                         if (submask != mask_pos) {
1318                                 dev_warn(pcs->dev,
1319                                                 "Invalid submask 0x%x for %s at 0x%x\n",
1320                                                 submask, np->name, offset);
1321                                 continue;
1322                         }
1323
1324                         vals[found].mask = submask;
1325                         vals[found].reg = pcs->base + offset;
1326                         vals[found].val = val_pos;
1327
1328                         pin = pcs_get_pin_by_offset(pcs, offset);
1329                         if (pin < 0) {
1330                                 dev_err(pcs->dev,
1331                                         "could not add functions for %s %ux\n",
1332                                         np->name, offset);
1333                                 break;
1334                         }
1335                         pins[found++] = pin + pin_num_from_lsb;
1336                 }
1337         }
1338
1339         pgnames[0] = np->name;
1340         function = pcs_add_function(pcs, np, np->name, vals, found, pgnames, 1);
1341         if (!function)
1342                 goto free_pins;
1343
1344         res = pcs_add_pingroup(pcs, np, np->name, pins, found);
1345         if (res < 0)
1346                 goto free_function;
1347
1348         (*map)->type = PIN_MAP_TYPE_MUX_GROUP;
1349         (*map)->data.mux.group = np->name;
1350         (*map)->data.mux.function = np->name;
1351
1352         if (PCS_HAS_PINCONF) {
1353                 dev_err(pcs->dev, "pinconf not supported\n");
1354                 goto free_pingroups;
1355         }
1356
1357         *num_maps = 1;
1358         return 0;
1359
1360 free_pingroups:
1361         pcs_free_pingroups(pcs);
1362         *num_maps = 1;
1363 free_function:
1364         pcs_remove_function(pcs, function);
1365
1366 free_pins:
1367         devm_kfree(pcs->dev, pins);
1368
1369 free_vals:
1370         devm_kfree(pcs->dev, vals);
1371
1372         return res;
1373 }
1374 /**
1375  * pcs_dt_node_to_map() - allocates and parses pinctrl maps
1376  * @pctldev: pinctrl instance
1377  * @np_config: device tree pinmux entry
1378  * @map: array of map entries
1379  * @num_maps: number of maps
1380  */
1381 static int pcs_dt_node_to_map(struct pinctrl_dev *pctldev,
1382                                 struct device_node *np_config,
1383                                 struct pinctrl_map **map, unsigned *num_maps)
1384 {
1385         struct pcs_device *pcs;
1386         const char **pgnames;
1387         int ret;
1388
1389         pcs = pinctrl_dev_get_drvdata(pctldev);
1390
1391         /* create 2 maps. One is for pinmux, and the other is for pinconf. */
1392         *map = devm_kzalloc(pcs->dev, sizeof(**map) * 2, GFP_KERNEL);
1393         if (!*map)
1394                 return -ENOMEM;
1395
1396         *num_maps = 0;
1397
1398         pgnames = devm_kzalloc(pcs->dev, sizeof(*pgnames), GFP_KERNEL);
1399         if (!pgnames) {
1400                 ret = -ENOMEM;
1401                 goto free_map;
1402         }
1403
1404         if (pcs->bits_per_mux) {
1405                 ret = pcs_parse_bits_in_pinctrl_entry(pcs, np_config, map,
1406                                 num_maps, pgnames);
1407                 if (ret < 0) {
1408                         dev_err(pcs->dev, "no pins entries for %s\n",
1409                                 np_config->name);
1410                         goto free_pgnames;
1411                 }
1412         } else {
1413                 ret = pcs_parse_one_pinctrl_entry(pcs, np_config, map,
1414                                 num_maps, pgnames);
1415                 if (ret < 0) {
1416                         dev_err(pcs->dev, "no pins entries for %s\n",
1417                                 np_config->name);
1418                         goto free_pgnames;
1419                 }
1420         }
1421
1422         return 0;
1423
1424 free_pgnames:
1425         devm_kfree(pcs->dev, pgnames);
1426 free_map:
1427         devm_kfree(pcs->dev, *map);
1428
1429         return ret;
1430 }
1431
1432 /**
1433  * pcs_free_funcs() - free memory used by functions
1434  * @pcs: pcs driver instance
1435  */
1436 static void pcs_free_funcs(struct pcs_device *pcs)
1437 {
1438         struct list_head *pos, *tmp;
1439         int i;
1440
1441         mutex_lock(&pcs->mutex);
1442         for (i = 0; i < pcs->nfuncs; i++) {
1443                 struct pcs_function *func;
1444
1445                 func = radix_tree_lookup(&pcs->ftree, i);
1446                 if (!func)
1447                         continue;
1448                 radix_tree_delete(&pcs->ftree, i);
1449         }
1450         list_for_each_safe(pos, tmp, &pcs->functions) {
1451                 struct pcs_function *function;
1452
1453                 function = list_entry(pos, struct pcs_function, node);
1454                 list_del(&function->node);
1455         }
1456         mutex_unlock(&pcs->mutex);
1457 }
1458
1459 /**
1460  * pcs_free_pingroups() - free memory used by pingroups
1461  * @pcs: pcs driver instance
1462  */
1463 static void pcs_free_pingroups(struct pcs_device *pcs)
1464 {
1465         struct list_head *pos, *tmp;
1466         int i;
1467
1468         mutex_lock(&pcs->mutex);
1469         for (i = 0; i < pcs->ngroups; i++) {
1470                 struct pcs_pingroup *pingroup;
1471
1472                 pingroup = radix_tree_lookup(&pcs->pgtree, i);
1473                 if (!pingroup)
1474                         continue;
1475                 radix_tree_delete(&pcs->pgtree, i);
1476         }
1477         list_for_each_safe(pos, tmp, &pcs->pingroups) {
1478                 struct pcs_pingroup *pingroup;
1479
1480                 pingroup = list_entry(pos, struct pcs_pingroup, node);
1481                 list_del(&pingroup->node);
1482         }
1483         mutex_unlock(&pcs->mutex);
1484 }
1485
1486 /**
1487  * pcs_irq_free() - free interrupt
1488  * @pcs: pcs driver instance
1489  */
1490 static void pcs_irq_free(struct pcs_device *pcs)
1491 {
1492         struct pcs_soc_data *pcs_soc = &pcs->socdata;
1493
1494         if (pcs_soc->irq < 0)
1495                 return;
1496
1497         if (pcs->domain)
1498                 irq_domain_remove(pcs->domain);
1499
1500         if (PCS_QUIRK_HAS_SHARED_IRQ)
1501                 free_irq(pcs_soc->irq, pcs_soc);
1502         else
1503                 irq_set_chained_handler(pcs_soc->irq, NULL);
1504 }
1505
1506 /**
1507  * pcs_free_resources() - free memory used by this driver
1508  * @pcs: pcs driver instance
1509  */
1510 static void pcs_free_resources(struct pcs_device *pcs)
1511 {
1512         pcs_irq_free(pcs);
1513
1514         if (pcs->pctl)
1515                 pinctrl_unregister(pcs->pctl);
1516
1517         pcs_free_funcs(pcs);
1518         pcs_free_pingroups(pcs);
1519 }
1520
1521 #define PCS_GET_PROP_U32(name, reg, err)                                \
1522         do {                                                            \
1523                 ret = of_property_read_u32(np, name, reg);              \
1524                 if (ret) {                                              \
1525                         dev_err(pcs->dev, err);                         \
1526                         return ret;                                     \
1527                 }                                                       \
1528         } while (0);
1529
1530 static struct of_device_id pcs_of_match[];
1531
1532 static int pcs_add_gpio_func(struct device_node *node, struct pcs_device *pcs)
1533 {
1534         const char *propname = "pinctrl-single,gpio-range";
1535         const char *cellname = "#pinctrl-single,gpio-range-cells";
1536         struct of_phandle_args gpiospec;
1537         struct pcs_gpiofunc_range *range;
1538         int ret, i;
1539
1540         for (i = 0; ; i++) {
1541                 ret = of_parse_phandle_with_args(node, propname, cellname,
1542                                                  i, &gpiospec);
1543                 /* Do not treat it as error. Only treat it as end condition. */
1544                 if (ret) {
1545                         ret = 0;
1546                         break;
1547                 }
1548                 range = devm_kzalloc(pcs->dev, sizeof(*range), GFP_KERNEL);
1549                 if (!range) {
1550                         ret = -ENOMEM;
1551                         break;
1552                 }
1553                 range->offset = gpiospec.args[0];
1554                 range->npins = gpiospec.args[1];
1555                 range->gpiofunc = gpiospec.args[2];
1556                 mutex_lock(&pcs->mutex);
1557                 list_add_tail(&range->node, &pcs->gpiofuncs);
1558                 mutex_unlock(&pcs->mutex);
1559         }
1560         return ret;
1561 }
1562 /**
1563  * @reg:        virtual address of interrupt register
1564  * @hwirq:      hardware irq number
1565  * @irq:        virtual irq number
1566  * @node:       list node
1567  */
1568 struct pcs_interrupt {
1569         void __iomem *reg;
1570         irq_hw_number_t hwirq;
1571         unsigned int irq;
1572         struct list_head node;
1573 };
1574
1575 /**
1576  * pcs_irq_set() - enables or disables an interrupt
1577  *
1578  * Note that this currently assumes one interrupt per pinctrl
1579  * register that is typically used for wake-up events.
1580  */
1581 static inline void pcs_irq_set(struct pcs_soc_data *pcs_soc,
1582                                int irq, const bool enable)
1583 {
1584         struct pcs_device *pcs;
1585         struct list_head *pos;
1586         unsigned mask;
1587
1588         pcs = container_of(pcs_soc, struct pcs_device, socdata);
1589         list_for_each(pos, &pcs->irqs) {
1590                 struct pcs_interrupt *pcswi;
1591                 unsigned soc_mask;
1592
1593                 pcswi = list_entry(pos, struct pcs_interrupt, node);
1594                 if (irq != pcswi->irq)
1595                         continue;
1596
1597                 soc_mask = pcs_soc->irq_enable_mask;
1598                 raw_spin_lock(&pcs->lock);
1599                 mask = pcs->read(pcswi->reg);
1600                 if (enable)
1601                         mask |= soc_mask;
1602                 else
1603                         mask &= ~soc_mask;
1604                 pcs->write(mask, pcswi->reg);
1605                 raw_spin_unlock(&pcs->lock);
1606         }
1607
1608         if (pcs_soc->rearm)
1609                 pcs_soc->rearm();
1610 }
1611
1612 /**
1613  * pcs_irq_mask() - mask pinctrl interrupt
1614  * @d: interrupt data
1615  */
1616 static void pcs_irq_mask(struct irq_data *d)
1617 {
1618         struct pcs_soc_data *pcs_soc = irq_data_get_irq_chip_data(d);
1619
1620         pcs_irq_set(pcs_soc, d->irq, false);
1621 }
1622
1623 /**
1624  * pcs_irq_unmask() - unmask pinctrl interrupt
1625  * @d: interrupt data
1626  */
1627 static void pcs_irq_unmask(struct irq_data *d)
1628 {
1629         struct pcs_soc_data *pcs_soc = irq_data_get_irq_chip_data(d);
1630
1631         pcs_irq_set(pcs_soc, d->irq, true);
1632 }
1633
1634 /**
1635  * pcs_irq_set_wake() - toggle the suspend and resume wake up
1636  * @d: interrupt data
1637  * @state: wake-up state
1638  *
1639  * Note that this should be called only for suspend and resume.
1640  * For runtime PM, the wake-up events should be enabled by default.
1641  */
1642 static int pcs_irq_set_wake(struct irq_data *d, unsigned int state)
1643 {
1644         if (state)
1645                 pcs_irq_unmask(d);
1646         else
1647                 pcs_irq_mask(d);
1648
1649         return 0;
1650 }
1651
1652 /**
1653  * pcs_irq_handle() - common interrupt handler
1654  * @pcs_irq: interrupt data
1655  *
1656  * Note that this currently assumes we have one interrupt bit per
1657  * mux register. This interrupt is typically used for wake-up events.
1658  * For more complex interrupts different handlers can be specified.
1659  */
1660 static int pcs_irq_handle(struct pcs_soc_data *pcs_soc)
1661 {
1662         struct pcs_device *pcs;
1663         struct list_head *pos;
1664         int count = 0;
1665
1666         pcs = container_of(pcs_soc, struct pcs_device, socdata);
1667         list_for_each(pos, &pcs->irqs) {
1668                 struct pcs_interrupt *pcswi;
1669                 unsigned mask;
1670
1671                 pcswi = list_entry(pos, struct pcs_interrupt, node);
1672                 raw_spin_lock(&pcs->lock);
1673                 mask = pcs->read(pcswi->reg);
1674                 raw_spin_unlock(&pcs->lock);
1675                 if (mask & pcs_soc->irq_status_mask) {
1676                         generic_handle_irq(irq_find_mapping(pcs->domain,
1677                                                             pcswi->hwirq));
1678                         count++;
1679                 }
1680         }
1681
1682         return count;
1683 }
1684
1685 /**
1686  * pcs_irq_handler() - handler for the shared interrupt case
1687  * @irq: interrupt
1688  * @d: data
1689  *
1690  * Use this for cases where multiple instances of
1691  * pinctrl-single share a single interrupt like on omaps.
1692  */
1693 static irqreturn_t pcs_irq_handler(int irq, void *d)
1694 {
1695         struct pcs_soc_data *pcs_soc = d;
1696
1697         return pcs_irq_handle(pcs_soc) ? IRQ_HANDLED : IRQ_NONE;
1698 }
1699
1700 /**
1701  * pcs_irq_handle() - handler for the dedicated chained interrupt case
1702  * @irq: interrupt
1703  * @desc: interrupt descriptor
1704  *
1705  * Use this if you have a separate interrupt for each
1706  * pinctrl-single instance.
1707  */
1708 static void pcs_irq_chain_handler(unsigned int irq, struct irq_desc *desc)
1709 {
1710         struct pcs_soc_data *pcs_soc = irq_desc_get_handler_data(desc);
1711         struct irq_chip *chip;
1712         int res;
1713
1714         chip = irq_get_chip(irq);
1715         chained_irq_enter(chip, desc);
1716         res = pcs_irq_handle(pcs_soc);
1717         /* REVISIT: export and add handle_bad_irq(irq, desc)? */
1718         chained_irq_exit(chip, desc);
1719
1720         return;
1721 }
1722
1723 static int pcs_irqdomain_map(struct irq_domain *d, unsigned int irq,
1724                              irq_hw_number_t hwirq)
1725 {
1726         struct pcs_soc_data *pcs_soc = d->host_data;
1727         struct pcs_device *pcs;
1728         struct pcs_interrupt *pcswi;
1729
1730         pcs = container_of(pcs_soc, struct pcs_device, socdata);
1731         pcswi = devm_kzalloc(pcs->dev, sizeof(*pcswi), GFP_KERNEL);
1732         if (!pcswi)
1733                 return -ENOMEM;
1734
1735         pcswi->reg = pcs->base + hwirq;
1736         pcswi->hwirq = hwirq;
1737         pcswi->irq = irq;
1738
1739         mutex_lock(&pcs->mutex);
1740         list_add_tail(&pcswi->node, &pcs->irqs);
1741         mutex_unlock(&pcs->mutex);
1742
1743         irq_set_chip_data(irq, pcs_soc);
1744         irq_set_chip_and_handler(irq, &pcs->chip,
1745                                  handle_level_irq);
1746
1747 #ifdef CONFIG_ARM
1748         set_irq_flags(irq, IRQF_VALID);
1749 #else
1750         irq_set_noprobe(irq);
1751 #endif
1752
1753         return 0;
1754 }
1755
1756 static struct irq_domain_ops pcs_irqdomain_ops = {
1757         .map = pcs_irqdomain_map,
1758         .xlate = irq_domain_xlate_onecell,
1759 };
1760
1761 /**
1762  * pcs_irq_init_chained_handler() - set up a chained interrupt handler
1763  * @pcs: pcs driver instance
1764  * @np: device node pointer
1765  */
1766 static int pcs_irq_init_chained_handler(struct pcs_device *pcs,
1767                                         struct device_node *np)
1768 {
1769         struct pcs_soc_data *pcs_soc = &pcs->socdata;
1770         const char *name = "pinctrl";
1771         int num_irqs;
1772
1773         if (!pcs_soc->irq_enable_mask ||
1774             !pcs_soc->irq_status_mask) {
1775                 pcs_soc->irq = -1;
1776                 return -EINVAL;
1777         }
1778
1779         INIT_LIST_HEAD(&pcs->irqs);
1780         pcs->chip.name = name;
1781         pcs->chip.irq_ack = pcs_irq_mask;
1782         pcs->chip.irq_mask = pcs_irq_mask;
1783         pcs->chip.irq_unmask = pcs_irq_unmask;
1784         pcs->chip.irq_set_wake = pcs_irq_set_wake;
1785
1786         if (PCS_QUIRK_HAS_SHARED_IRQ) {
1787                 int res;
1788
1789                 res = request_irq(pcs_soc->irq, pcs_irq_handler,
1790                                   IRQF_SHARED | IRQF_NO_SUSPEND,
1791                                   name, pcs_soc);
1792                 if (res) {
1793                         pcs_soc->irq = -1;
1794                         return res;
1795                 }
1796         } else {
1797                 irq_set_handler_data(pcs_soc->irq, pcs_soc);
1798                 irq_set_chained_handler(pcs_soc->irq,
1799                                         pcs_irq_chain_handler);
1800         }
1801
1802         /*
1803          * We can use the register offset as the hardirq
1804          * number as irq_domain_add_simple maps them lazily.
1805          * This way we can easily support more than one
1806          * interrupt per function if needed.
1807          */
1808         num_irqs = pcs->size;
1809
1810         pcs->domain = irq_domain_add_simple(np, num_irqs, 0,
1811                                             &pcs_irqdomain_ops,
1812                                             pcs_soc);
1813         if (!pcs->domain) {
1814                 irq_set_chained_handler(pcs_soc->irq, NULL);
1815                 return -EINVAL;
1816         }
1817
1818         return 0;
1819 }
1820
1821 #ifdef CONFIG_PM
1822 static int pinctrl_single_suspend(struct platform_device *pdev,
1823                                         pm_message_t state)
1824 {
1825         struct pcs_device *pcs;
1826
1827         pcs = platform_get_drvdata(pdev);
1828         if (!pcs)
1829                 return -EINVAL;
1830
1831         return pinctrl_force_sleep(pcs->pctl);
1832 }
1833
1834 static int pinctrl_single_resume(struct platform_device *pdev)
1835 {
1836         struct pcs_device *pcs;
1837
1838         pcs = platform_get_drvdata(pdev);
1839         if (!pcs)
1840                 return -EINVAL;
1841
1842         return pinctrl_force_default(pcs->pctl);
1843 }
1844 #endif
1845
1846 static int pcs_probe(struct platform_device *pdev)
1847 {
1848         struct device_node *np = pdev->dev.of_node;
1849         const struct of_device_id *match;
1850         struct pcs_pdata *pdata;
1851         struct resource *res;
1852         struct pcs_device *pcs;
1853         const struct pcs_soc_data *soc;
1854         int ret;
1855
1856         match = of_match_device(pcs_of_match, &pdev->dev);
1857         if (!match)
1858                 return -EINVAL;
1859
1860         pcs = devm_kzalloc(&pdev->dev, sizeof(*pcs), GFP_KERNEL);
1861         if (!pcs) {
1862                 dev_err(&pdev->dev, "could not allocate\n");
1863                 return -ENOMEM;
1864         }
1865         pcs->dev = &pdev->dev;
1866         raw_spin_lock_init(&pcs->lock);
1867         mutex_init(&pcs->mutex);
1868         INIT_LIST_HEAD(&pcs->pingroups);
1869         INIT_LIST_HEAD(&pcs->functions);
1870         INIT_LIST_HEAD(&pcs->gpiofuncs);
1871         soc = match->data;
1872         pcs->flags = soc->flags;
1873         memcpy(&pcs->socdata, soc, sizeof(*soc));
1874
1875         PCS_GET_PROP_U32("pinctrl-single,register-width", &pcs->width,
1876                          "register width not specified\n");
1877
1878         ret = of_property_read_u32(np, "pinctrl-single,function-mask",
1879                                    &pcs->fmask);
1880         if (!ret) {
1881                 pcs->fshift = ffs(pcs->fmask) - 1;
1882                 pcs->fmax = pcs->fmask >> pcs->fshift;
1883         } else {
1884                 /* If mask property doesn't exist, function mux is invalid. */
1885                 pcs->fmask = 0;
1886                 pcs->fshift = 0;
1887                 pcs->fmax = 0;
1888         }
1889
1890         ret = of_property_read_u32(np, "pinctrl-single,function-off",
1891                                         &pcs->foff);
1892         if (ret)
1893                 pcs->foff = PCS_OFF_DISABLED;
1894
1895         pcs->bits_per_mux = of_property_read_bool(np,
1896                                                   "pinctrl-single,bit-per-mux");
1897
1898         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1899         if (!res) {
1900                 dev_err(pcs->dev, "could not get resource\n");
1901                 return -ENODEV;
1902         }
1903
1904         pcs->res = devm_request_mem_region(pcs->dev, res->start,
1905                         resource_size(res), DRIVER_NAME);
1906         if (!pcs->res) {
1907                 dev_err(pcs->dev, "could not get mem_region\n");
1908                 return -EBUSY;
1909         }
1910
1911         pcs->size = resource_size(pcs->res);
1912         pcs->base = devm_ioremap(pcs->dev, pcs->res->start, pcs->size);
1913         if (!pcs->base) {
1914                 dev_err(pcs->dev, "could not ioremap\n");
1915                 return -ENODEV;
1916         }
1917
1918         INIT_RADIX_TREE(&pcs->pgtree, GFP_KERNEL);
1919         INIT_RADIX_TREE(&pcs->ftree, GFP_KERNEL);
1920         platform_set_drvdata(pdev, pcs);
1921
1922         switch (pcs->width) {
1923         case 8:
1924                 pcs->read = pcs_readb;
1925                 pcs->write = pcs_writeb;
1926                 break;
1927         case 16:
1928                 pcs->read = pcs_readw;
1929                 pcs->write = pcs_writew;
1930                 break;
1931         case 32:
1932                 pcs->read = pcs_readl;
1933                 pcs->write = pcs_writel;
1934                 break;
1935         default:
1936                 break;
1937         }
1938
1939         pcs->desc.name = DRIVER_NAME;
1940         pcs->desc.pctlops = &pcs_pinctrl_ops;
1941         pcs->desc.pmxops = &pcs_pinmux_ops;
1942         if (PCS_HAS_PINCONF)
1943                 pcs->desc.confops = &pcs_pinconf_ops;
1944         pcs->desc.owner = THIS_MODULE;
1945
1946         ret = pcs_allocate_pin_table(pcs);
1947         if (ret < 0)
1948                 goto free;
1949
1950         pcs->pctl = pinctrl_register(&pcs->desc, pcs->dev, pcs);
1951         if (!pcs->pctl) {
1952                 dev_err(pcs->dev, "could not register single pinctrl driver\n");
1953                 ret = -EINVAL;
1954                 goto free;
1955         }
1956
1957         ret = pcs_add_gpio_func(np, pcs);
1958         if (ret < 0)
1959                 goto free;
1960
1961         pcs->socdata.irq = irq_of_parse_and_map(np, 0);
1962         if (pcs->socdata.irq)
1963                 pcs->flags |= PCS_FEAT_IRQ;
1964
1965         /* We still need auxdata for some omaps for PRM interrupts */
1966         pdata = dev_get_platdata(&pdev->dev);
1967         if (pdata) {
1968                 if (pdata->rearm)
1969                         pcs->socdata.rearm = pdata->rearm;
1970                 if (pdata->irq) {
1971                         pcs->socdata.irq = pdata->irq;
1972                         pcs->flags |= PCS_FEAT_IRQ;
1973                 }
1974         }
1975
1976         if (PCS_HAS_IRQ) {
1977                 ret = pcs_irq_init_chained_handler(pcs, np);
1978                 if (ret < 0)
1979                         dev_warn(pcs->dev, "initialized with no interrupts\n");
1980         }
1981
1982         dev_info(pcs->dev, "%i pins at pa %p size %u\n",
1983                  pcs->desc.npins, pcs->base, pcs->size);
1984
1985         return 0;
1986
1987 free:
1988         pcs_free_resources(pcs);
1989
1990         return ret;
1991 }
1992
1993 static int pcs_remove(struct platform_device *pdev)
1994 {
1995         struct pcs_device *pcs = platform_get_drvdata(pdev);
1996
1997         if (!pcs)
1998                 return 0;
1999
2000         pcs_free_resources(pcs);
2001
2002         return 0;
2003 }
2004
2005 static const struct pcs_soc_data pinctrl_single_omap_wkup = {
2006         .flags = PCS_QUIRK_SHARED_IRQ,
2007         .irq_enable_mask = (1 << 14),   /* OMAP_WAKEUP_EN */
2008         .irq_status_mask = (1 << 15),   /* OMAP_WAKEUP_EVENT */
2009 };
2010
2011 static const struct pcs_soc_data pinctrl_single = {
2012 };
2013
2014 static const struct pcs_soc_data pinconf_single = {
2015         .flags = PCS_FEAT_PINCONF,
2016 };
2017
2018 static struct of_device_id pcs_of_match[] = {
2019         { .compatible = "ti,omap3-padconf", .data = &pinctrl_single_omap_wkup },
2020         { .compatible = "ti,omap4-padconf", .data = &pinctrl_single_omap_wkup },
2021         { .compatible = "ti,omap5-padconf", .data = &pinctrl_single_omap_wkup },
2022         { .compatible = "pinctrl-single", .data = &pinctrl_single },
2023         { .compatible = "pinconf-single", .data = &pinconf_single },
2024         { },
2025 };
2026 MODULE_DEVICE_TABLE(of, pcs_of_match);
2027
2028 static struct platform_driver pcs_driver = {
2029         .probe          = pcs_probe,
2030         .remove         = pcs_remove,
2031         .driver = {
2032                 .owner          = THIS_MODULE,
2033                 .name           = DRIVER_NAME,
2034                 .of_match_table = pcs_of_match,
2035         },
2036 #ifdef CONFIG_PM
2037         .suspend = pinctrl_single_suspend,
2038         .resume = pinctrl_single_resume,
2039 #endif
2040 };
2041
2042 module_platform_driver(pcs_driver);
2043
2044 MODULE_AUTHOR("Tony Lindgren <tony@atomide.com>");
2045 MODULE_DESCRIPTION("One-register-per-pin type device tree based pinctrl driver");
2046 MODULE_LICENSE("GPL v2");