drivers/pinctrl/sirf/pinctrl-atlas6.c

   1 /*
   2  * pinctrl pads, groups, functions for CSR SiRFatlasVI
   3  *
   4  * Copyright (c) 2011 - 2014 Cambridge Silicon Radio Limited, a CSR plc group
   5  * company.
   6  *
   7  * Licensed under GPLv2 or later.
   8  */
   9
  10 #include <linux/pinctrl/pinctrl.h>
  11 #include <linux/bitops.h>
  12
  13 #include "pinctrl-sirf.h"
  14
  15 /*
  16  * pad list for the pinmux subsystem
  17  * refer to atlasVI_io_table_v0.93.xls
  18  */
  19 static const struct pinctrl_pin_desc sirfsoc_pads[] = {
  20         PINCTRL_PIN(0, "gpio0-0"),
  21         PINCTRL_PIN(1, "gpio0-1"),
  22         PINCTRL_PIN(2, "gpio0-2"),
  23         PINCTRL_PIN(3, "gpio0-3"),
  24         PINCTRL_PIN(4, "pwm0"),
  25         PINCTRL_PIN(5, "pwm1"),
  26         PINCTRL_PIN(6, "pwm2"),
  27         PINCTRL_PIN(7, "pwm3"),
  28         PINCTRL_PIN(8, "warm_rst_b"),
  29         PINCTRL_PIN(9, "odo_0"),
  30         PINCTRL_PIN(10, "odo_1"),
  31         PINCTRL_PIN(11, "dr_dir"),
  32         PINCTRL_PIN(12, "rts_0"),
  33         PINCTRL_PIN(13, "scl_1"),
  34         PINCTRL_PIN(14, "ntrst"),
  35         PINCTRL_PIN(15, "sda_1"),
  36         PINCTRL_PIN(16, "x_ldd[16]"),
  37         PINCTRL_PIN(17, "x_ldd[17]"),
  38         PINCTRL_PIN(18, "x_ldd[18]"),
  39         PINCTRL_PIN(19, "x_ldd[19]"),
  40         PINCTRL_PIN(20, "x_ldd[20]"),
  41         PINCTRL_PIN(21, "x_ldd[21]"),
  42         PINCTRL_PIN(22, "x_ldd[22]"),
  43         PINCTRL_PIN(23, "x_ldd[23]"),
  44         PINCTRL_PIN(24, "gps_sgn"),
  45         PINCTRL_PIN(25, "gps_mag"),
  46         PINCTRL_PIN(26, "gps_clk"),
  47         PINCTRL_PIN(27, "sd_cd_b_2"),
  48         PINCTRL_PIN(28, "sd_vcc_on_2"),
  49         PINCTRL_PIN(29, "sd_wp_b_2"),
  50         PINCTRL_PIN(30, "sd_clk_3"),
  51         PINCTRL_PIN(31, "sd_cmd_3"),
  52
  53         PINCTRL_PIN(32, "x_sd_dat_3[0]"),
  54         PINCTRL_PIN(33, "x_sd_dat_3[1]"),
  55         PINCTRL_PIN(34, "x_sd_dat_3[2]"),
  56         PINCTRL_PIN(35, "x_sd_dat_3[3]"),
  57         PINCTRL_PIN(36, "usb_clk"),
  58         PINCTRL_PIN(37, "usb_dir"),
  59         PINCTRL_PIN(38, "usb_nxt"),
  60         PINCTRL_PIN(39, "usb_stp"),
  61         PINCTRL_PIN(40, "usb_dat[7]"),
  62         PINCTRL_PIN(41, "usb_dat[6]"),
  63         PINCTRL_PIN(42, "x_cko_1"),
  64         PINCTRL_PIN(43, "spi_clk_1"),
  65         PINCTRL_PIN(44, "spi_dout_1"),
  66         PINCTRL_PIN(45, "spi_din_1"),
  67         PINCTRL_PIN(46, "spi_en_1"),
  68         PINCTRL_PIN(47, "x_txd_1"),
  69         PINCTRL_PIN(48, "x_txd_2"),
  70         PINCTRL_PIN(49, "x_rxd_1"),
  71         PINCTRL_PIN(50, "x_rxd_2"),
  72         PINCTRL_PIN(51, "x_usclk_0"),
  73         PINCTRL_PIN(52, "x_utxd_0"),
  74         PINCTRL_PIN(53, "x_urxd_0"),
  75         PINCTRL_PIN(54, "x_utfs_0"),
  76         PINCTRL_PIN(55, "x_urfs_0"),
  77         PINCTRL_PIN(56, "usb_dat5"),
  78         PINCTRL_PIN(57, "usb_dat4"),
  79         PINCTRL_PIN(58, "usb_dat3"),
  80         PINCTRL_PIN(59, "usb_dat2"),
  81         PINCTRL_PIN(60, "usb_dat1"),
  82         PINCTRL_PIN(61, "usb_dat0"),
  83         PINCTRL_PIN(62, "x_ldd[14]"),
  84         PINCTRL_PIN(63, "x_ldd[15]"),
  85
  86         PINCTRL_PIN(64, "x_gps_gpio"),
  87         PINCTRL_PIN(65, "x_ldd[13]"),
  88         PINCTRL_PIN(66, "x_df_we_b"),
  89         PINCTRL_PIN(67, "x_df_re_b"),
  90         PINCTRL_PIN(68, "x_txd_0"),
  91         PINCTRL_PIN(69, "x_rxd_0"),
  92         PINCTRL_PIN(70, "x_l_lck"),
  93         PINCTRL_PIN(71, "x_l_fck"),
  94         PINCTRL_PIN(72, "x_l_de"),
  95         PINCTRL_PIN(73, "x_ldd[0]"),
  96         PINCTRL_PIN(74, "x_ldd[1]"),
  97         PINCTRL_PIN(75, "x_ldd[2]"),
  98         PINCTRL_PIN(76, "x_ldd[3]"),
  99         PINCTRL_PIN(77, "x_ldd[4]"),
 100         PINCTRL_PIN(78, "x_cko_0"),
 101         PINCTRL_PIN(79, "x_ldd[5]"),
 102         PINCTRL_PIN(80, "x_ldd[6]"),
 103         PINCTRL_PIN(81, "x_ldd[7]"),
 104         PINCTRL_PIN(82, "x_ldd[8]"),
 105         PINCTRL_PIN(83, "x_ldd[9]"),
 106         PINCTRL_PIN(84, "x_ldd[10]"),
 107         PINCTRL_PIN(85, "x_ldd[11]"),
 108         PINCTRL_PIN(86, "x_ldd[12]"),
 109         PINCTRL_PIN(87, "x_vip_vsync"),
 110         PINCTRL_PIN(88, "x_vip_hsync"),
 111         PINCTRL_PIN(89, "x_vip_pxclk"),
 112         PINCTRL_PIN(90, "x_sda_0"),
 113         PINCTRL_PIN(91, "x_scl_0"),
 114         PINCTRL_PIN(92, "x_df_ry_by"),
 115         PINCTRL_PIN(93, "x_df_cs_b[1]"),
 116         PINCTRL_PIN(94, "x_df_cs_b[0]"),
 117         PINCTRL_PIN(95, "x_l_pclk"),
 118
 119         PINCTRL_PIN(96, "x_df_dqs"),
 120         PINCTRL_PIN(97, "x_df_wp_b"),
 121         PINCTRL_PIN(98, "ac97_sync"),
 122         PINCTRL_PIN(99, "ac97_bit_clk "),
 123         PINCTRL_PIN(100, "ac97_dout"),
 124         PINCTRL_PIN(101, "ac97_din"),
 125         PINCTRL_PIN(102, "x_rtc_io"),
 126
 127         PINCTRL_PIN(103, "x_usb1_dp"),
 128         PINCTRL_PIN(104, "x_usb1_dn"),
 129 };
 130
 131 static const struct sirfsoc_muxmask lcd_16bits_sirfsoc_muxmask[] = {
 132         {
 133                 .group = 1,
 134                 .mask = BIT(30) | BIT(31),
 135         }, {
 136                 .group = 2,
 137                 .mask = BIT(1) | BIT(6) | BIT(7) | BIT(8) | BIT(9) | BIT(10) | BIT(11) |
 138                         BIT(12) | BIT(13) | BIT(15) | BIT(16) | BIT(17) | BIT(18) | BIT(19) |
 139                         BIT(20) | BIT(21) | BIT(22) | BIT(31),
 140         },
 141 };
 142
 143 static const struct sirfsoc_padmux lcd_16bits_padmux = {
 144         .muxmask_counts = ARRAY_SIZE(lcd_16bits_sirfsoc_muxmask),
 145         .muxmask = lcd_16bits_sirfsoc_muxmask,
 146         .ctrlreg = SIRFSOC_RSC_PIN_MUX,
 147         .funcmask = BIT(4),
 148         .funcval = 0,
 149 };
 150
 151 static const unsigned lcd_16bits_pins[] = { 62, 63, 65, 70, 71, 72, 73, 74, 75, 76, 77, 79, 80, 81, 82, 83,
 152         84, 85, 86, 95 };
 153
 154 static const struct sirfsoc_muxmask lcd_18bits_muxmask[] = {
 155         {
 156                 .group = 2,
 157                 .mask = BIT(1) | BIT(6) | BIT(7) | BIT(8) | BIT(9) | BIT(10) | BIT(11) |
 158                         BIT(12) | BIT(13) | BIT(15) | BIT(16) | BIT(17) | BIT(18) | BIT(19) |
 159                         BIT(20) | BIT(21) | BIT(22) | BIT(31),
 160         }, {
 161                 .group = 1,
 162                 .mask = BIT(30) | BIT(31),
 163         }, {
 164                 .group = 0,
 165                 .mask = BIT(16) | BIT(17),
 166         },
 167 };
 168
 169 static const struct sirfsoc_padmux lcd_18bits_padmux = {
 170         .muxmask_counts = ARRAY_SIZE(lcd_18bits_muxmask),
 171         .muxmask = lcd_18bits_muxmask,
 172         .ctrlreg = SIRFSOC_RSC_PIN_MUX,
 173         .funcmask = BIT(4) | BIT(15),
 174         .funcval = 0,
 175 };
 176
 177 static const unsigned lcd_18bits_pins[] = { 16, 17, 62, 63, 65, 70, 71, 72, 73, 74, 75, 76, 77, 79, 80, 81, 82, 83,
 178         84, 85, 86, 95 };
 179
 180 static const struct sirfsoc_muxmask lcd_24bits_muxmask[] = {
 181         {
 182                 .group = 2,
 183                 .mask = BIT(1) | BIT(6) | BIT(7) | BIT(8) | BIT(9) | BIT(10) | BIT(11) |
 184                         BIT(12) | BIT(13) | BIT(15) | BIT(16) | BIT(17) | BIT(18) | BIT(19) |
 185                         BIT(20) | BIT(21) | BIT(22) | BIT(31),
 186         }, {
 187                 .group = 1,
 188                 .mask = BIT(30) | BIT(31),
 189         }, {
 190                 .group = 0,
 191                 .mask = BIT(16) | BIT(17) | BIT(18) | BIT(19) | BIT(20) | BIT(21) | BIT(22) | BIT(23),
 192         },
 193 };
 194
 195 static const struct sirfsoc_padmux lcd_24bits_padmux = {
 196         .muxmask_counts = ARRAY_SIZE(lcd_24bits_muxmask),
 197         .muxmask = lcd_24bits_muxmask,
 198         .ctrlreg = SIRFSOC_RSC_PIN_MUX,
 199         .funcmask = BIT(4) | BIT(15),
 200         .funcval = 0,
 201 };
 202
 203 static const unsigned lcd_24bits_pins[] = { 16, 17, 18, 19, 20, 21, 22, 23, 62, 63, 65, 70, 71, 72, 73, 74, 75, 76, 77, 79,
 204         80, 81, 82, 83, 84, 85, 86, 95};
 205
 206 static const struct sirfsoc_muxmask lcdrom_muxmask[] = {
 207         {
 208                 .group = 2,
 209                 .mask = BIT(1) | BIT(6) | BIT(7) | BIT(8) | BIT(9) | BIT(10) | BIT(11) |
 210                         BIT(12) | BIT(13) | BIT(15) | BIT(16) | BIT(17) | BIT(18) | BIT(19) |
 211                         BIT(20) | BIT(21) | BIT(22) | BIT(31),
 212         }, {
 213                 .group = 1,
 214                 .mask = BIT(30) | BIT(31),
 215         }, {
 216                 .group = 0,
 217                 .mask = BIT(8),
 218         },
 219 };
 220
 221 static const struct sirfsoc_padmux lcdrom_padmux = {
 222         .muxmask_counts = ARRAY_SIZE(lcdrom_muxmask),
 223         .muxmask = lcdrom_muxmask,
 224         .ctrlreg = SIRFSOC_RSC_PIN_MUX,
 225         .funcmask = BIT(4),
 226         .funcval = BIT(4),
 227 };
 228
 229 static const unsigned lcdrom_pins[] = { 8, 62, 63, 65, 70, 71, 72, 73, 74, 75, 76, 77, 79, 80, 81, 82, 83,
 230         84, 85, 86, 95};
 231
 232 static const struct sirfsoc_muxmask uart0_muxmask[] = {
 233         {
 234                 .group = 0,
 235                 .mask = BIT(12),
 236         }, {
 237                 .group = 1,
 238                 .mask = BIT(23),
 239         }, {
 240                 .group = 2,
 241                 .mask = BIT(4) | BIT(5),
 242         },
 243 };
 244
 245 static const struct sirfsoc_padmux uart0_padmux = {
 246         .muxmask_counts = ARRAY_SIZE(uart0_muxmask),
 247         .muxmask = uart0_muxmask,
 248         .ctrlreg = SIRFSOC_RSC_PIN_MUX,
 249         .funcmask = BIT(9),
 250         .funcval = BIT(9),
 251 };
 252
 253 static const unsigned uart0_pins[] = { 12, 55, 68, 69 };
 254
 255 static const struct sirfsoc_muxmask uart0_nostreamctrl_muxmask[] = {
 256         {
 257                 .group = 2,
 258                 .mask = BIT(4) | BIT(5),
 259         },
 260 };
 261
 262 static const struct sirfsoc_padmux uart0_nostreamctrl_padmux = {
 263         .muxmask_counts = ARRAY_SIZE(uart0_nostreamctrl_muxmask),
 264         .muxmask = uart0_nostreamctrl_muxmask,
 265 };
 266
 267 static const unsigned uart0_nostreamctrl_pins[] = { 68, 69 };
 268
 269 static const struct sirfsoc_muxmask uart1_muxmask[] = {
 270         {
 271                 .group = 1,
 272                 .mask = BIT(15) | BIT(17),
 273         },
 274 };
 275
 276 static const struct sirfsoc_padmux uart1_padmux = {
 277         .muxmask_counts = ARRAY_SIZE(uart1_muxmask),
 278         .muxmask = uart1_muxmask,
 279 };
 280
 281 static const unsigned uart1_pins[] = { 47, 49 };
 282
 283 static const struct sirfsoc_muxmask uart2_muxmask[] = {
 284         {
 285                 .group = 0,
 286                 .mask = BIT(10) | BIT(14),
 287         }, {
 288                 .group = 1,
 289                 .mask = BIT(16) | BIT(18),
 290         },
 291 };
 292
 293 static const struct sirfsoc_padmux uart2_padmux = {
 294         .muxmask_counts = ARRAY_SIZE(uart2_muxmask),
 295         .muxmask = uart2_muxmask,
 296         .ctrlreg = SIRFSOC_RSC_PIN_MUX,
 297         .funcmask = BIT(10),
 298         .funcval = BIT(10),
 299 };
 300
 301 static const unsigned uart2_pins[] = { 10, 14, 48, 50 };
 302
 303 static const struct sirfsoc_muxmask uart2_nostreamctrl_muxmask[] = {
 304         {
 305                 .group = 1,
 306                 .mask = BIT(16) | BIT(18),
 307         },
 308 };
 309
 310 static const struct sirfsoc_padmux uart2_nostreamctrl_padmux = {
 311         .muxmask_counts = ARRAY_SIZE(uart2_nostreamctrl_muxmask),
 312         .muxmask = uart2_nostreamctrl_muxmask,
 313 };
 314
 315 static const unsigned uart2_nostreamctrl_pins[] = { 48, 50 };
 316
 317 static const struct sirfsoc_muxmask sdmmc3_muxmask[] = {
 318         {
 319                 .group = 0,
 320                 .mask = BIT(30) | BIT(31),
 321         }, {
 322                 .group = 1,
 323                 .mask = BIT(0) | BIT(1) | BIT(2) | BIT(3),
 324         },
 325 };
 326
 327 static const struct sirfsoc_padmux sdmmc3_padmux = {
 328         .muxmask_counts = ARRAY_SIZE(sdmmc3_muxmask),
 329         .muxmask = sdmmc3_muxmask,
 330         .ctrlreg = SIRFSOC_RSC_PIN_MUX,
 331         .funcmask = BIT(7),
 332         .funcval = 0,
 333 };
 334
 335 static const unsigned sdmmc3_pins[] = { 30, 31, 32, 33, 34, 35 };
 336
 337 static const struct sirfsoc_muxmask spi0_muxmask[] = {
 338         {
 339                 .group = 0,
 340                 .mask = BIT(30),
 341         }, {
 342                 .group = 1,
 343                 .mask = BIT(0) | BIT(2) | BIT(3),
 344         },
 345 };
 346
 347 static const struct sirfsoc_padmux spi0_padmux = {
 348         .muxmask_counts = ARRAY_SIZE(spi0_muxmask),
 349         .muxmask = spi0_muxmask,
 350         .ctrlreg = SIRFSOC_RSC_PIN_MUX,
 351         .funcmask = BIT(7),
 352         .funcval = BIT(7),
 353 };
 354
 355 static const unsigned spi0_pins[] = { 30, 32, 34, 35 };
 356
 357 static const struct sirfsoc_muxmask cko1_muxmask[] = {
 358         {
 359                 .group = 1,
 360                 .mask = BIT(10),
 361         },
 362 };
 363
 364 static const struct sirfsoc_padmux cko1_padmux = {
 365         .muxmask_counts = ARRAY_SIZE(cko1_muxmask),
 366         .muxmask = cko1_muxmask,
 367         .ctrlreg = SIRFSOC_RSC_PIN_MUX,
 368         .funcmask = BIT(3),
 369         .funcval = 0,
 370 };
 371
 372 static const unsigned cko1_pins[] = { 42 };
 373
 374 static const struct sirfsoc_muxmask i2s_muxmask[] = {
 375         {
 376                 .group = 1,
 377                 .mask = BIT(10),
 378         }, {
 379                 .group = 3,
 380                 .mask = BIT(2) | BIT(3) | BIT(4) | BIT(5),
 381         },
 382 };
 383
 384 static const struct sirfsoc_padmux i2s_padmux = {
 385         .muxmask_counts = ARRAY_SIZE(i2s_muxmask),
 386         .muxmask = i2s_muxmask,
 387         .ctrlreg = SIRFSOC_RSC_PIN_MUX,
 388         .funcmask = BIT(3),
 389         .funcval = BIT(3),
 390 };
 391
 392 static const unsigned i2s_pins[] = { 42, 98, 99, 100, 101 };
 393
 394 static const struct sirfsoc_muxmask i2s_no_din_muxmask[] = {
 395         {
 396                 .group = 1,
 397                 .mask = BIT(10),
 398         }, {
 399                 .group = 3,
 400                 .mask = BIT(2) | BIT(3) | BIT(4),
 401         },
 402 };
 403
 404 static const struct sirfsoc_padmux i2s_no_din_padmux = {
 405         .muxmask_counts = ARRAY_SIZE(i2s_no_din_muxmask),
 406         .muxmask = i2s_no_din_muxmask,
 407         .ctrlreg = SIRFSOC_RSC_PIN_MUX,
 408         .funcmask = BIT(3),
 409         .funcval = BIT(3),
 410 };
 411
 412 static const unsigned i2s_no_din_pins[] = { 42, 98, 99, 100 };
 413
 414 static const struct sirfsoc_muxmask i2s_6chn_muxmask[] = {
 415         {
 416                 .group = 1,
 417                 .mask = BIT(10) | BIT(20) | BIT(23),
 418         }, {
 419                 .group = 3,
 420                 .mask = BIT(2) | BIT(3) | BIT(4) | BIT(5),
 421         },
 422 };
 423
 424 static const struct sirfsoc_padmux i2s_6chn_padmux = {
 425         .muxmask_counts = ARRAY_SIZE(i2s_6chn_muxmask),
 426         .muxmask = i2s_6chn_muxmask,
 427         .ctrlreg = SIRFSOC_RSC_PIN_MUX,
 428         .funcmask = BIT(1) | BIT(3) | BIT(9),
 429         .funcval = BIT(1) | BIT(3) | BIT(9),
 430 };
 431
 432 static const unsigned i2s_6chn_pins[] = { 42, 52, 55, 98, 99, 100, 101 };
 433
 434 static const struct sirfsoc_muxmask ac97_muxmask[] = {
 435         {
 436                 .group = 3,
 437                 .mask = BIT(2) | BIT(3) | BIT(4) | BIT(5),
 438         },
 439 };
 440
 441 static const struct sirfsoc_padmux ac97_padmux = {
 442         .muxmask_counts = ARRAY_SIZE(ac97_muxmask),
 443         .muxmask = ac97_muxmask,
 444 };
 445
 446 static const unsigned ac97_pins[] = { 98, 99, 100, 101 };
 447
 448 static const struct sirfsoc_muxmask spi1_muxmask[] = {
 449         {
 450                 .group = 1,
 451                 .mask = BIT(11) | BIT(12) | BIT(13) | BIT(14),
 452         },
 453 };
 454
 455 static const struct sirfsoc_padmux spi1_padmux = {
 456         .muxmask_counts = ARRAY_SIZE(spi1_muxmask),
 457         .muxmask = spi1_muxmask,
 458         .ctrlreg = SIRFSOC_RSC_PIN_MUX,
 459         .funcmask = BIT(16),
 460         .funcval = 0,
 461 };
 462
 463 static const unsigned spi1_pins[] = { 43, 44, 45, 46 };
 464
 465 static const struct sirfsoc_muxmask sdmmc1_muxmask[] = {
 466         {
 467                 .group = 2,
 468                 .mask = BIT(2) | BIT(3),
 469         },
 470 };
 471
 472 static const struct sirfsoc_padmux sdmmc1_padmux = {
 473         .muxmask_counts = ARRAY_SIZE(sdmmc1_muxmask),
 474         .muxmask = sdmmc1_muxmask,
 475         .ctrlreg = SIRFSOC_RSC_PIN_MUX,
 476         .funcmask = BIT(5),
 477         .funcval = BIT(5),
 478 };
 479
 480 static const unsigned sdmmc1_pins[] = { 66, 67 };
 481
 482 static const struct sirfsoc_muxmask gps_muxmask[] = {
 483         {
 484                 .group = 0,
 485                 .mask = BIT(24) | BIT(25) | BIT(26),
 486         },
 487 };
 488
 489 static const struct sirfsoc_padmux gps_padmux = {
 490         .muxmask_counts = ARRAY_SIZE(gps_muxmask),
 491         .muxmask = gps_muxmask,
 492         .ctrlreg = SIRFSOC_RSC_PIN_MUX,
 493         .funcmask = BIT(13),
 494         .funcval = 0,
 495 };
 496
 497 static const unsigned gps_pins[] = { 24, 25, 26 };
 498
 499 static const struct sirfsoc_muxmask sdmmc5_muxmask[] = {
 500         {
 501                 .group = 0,
 502                 .mask = BIT(24) | BIT(25) | BIT(26),
 503         },
 504 };
 505
 506 static const struct sirfsoc_padmux sdmmc5_padmux = {
 507         .muxmask_counts = ARRAY_SIZE(sdmmc5_muxmask),
 508         .muxmask = sdmmc5_muxmask,
 509         .ctrlreg = SIRFSOC_RSC_PIN_MUX,
 510         .funcmask = BIT(13),
 511         .funcval = BIT(13),
 512 };
 513
 514 static const unsigned sdmmc5_pins[] = { 24, 25, 26 };
 515
 516 static const struct sirfsoc_muxmask usp0_muxmask[] = {
 517         {
 518                 .group = 1,
 519                 .mask = BIT(19) | BIT(20) | BIT(21) | BIT(22) | BIT(23),
 520         },
 521 };
 522
 523 static const struct sirfsoc_padmux usp0_padmux = {
 524         .muxmask_counts = ARRAY_SIZE(usp0_muxmask),
 525         .muxmask = usp0_muxmask,
 526         .ctrlreg = SIRFSOC_RSC_PIN_MUX,
 527         .funcmask = BIT(1) | BIT(2) | BIT(9),
 528         .funcval = 0,
 529 };
 530
 531 static const unsigned usp0_pins[] = { 51, 52, 53, 54, 55 };
 532
 533 static const struct sirfsoc_muxmask usp0_only_utfs_muxmask[] = {
 534         {
 535                 .group = 1,
 536                 .mask = BIT(19) | BIT(20) | BIT(21) | BIT(22),
 537         },
 538 };
 539
 540 static const struct sirfsoc_padmux usp0_only_utfs_padmux = {
 541         .muxmask_counts = ARRAY_SIZE(usp0_only_utfs_muxmask),
 542         .muxmask = usp0_only_utfs_muxmask,
 543         .ctrlreg = SIRFSOC_RSC_PIN_MUX,
 544         .funcmask = BIT(1) | BIT(2) | BIT(6),
 545         .funcval = 0,
 546 };
 547
 548 static const unsigned usp0_only_utfs_pins[] = { 51, 52, 53, 54 };
 549
 550 static const struct sirfsoc_muxmask usp0_only_urfs_muxmask[] = {
 551         {
 552                 .group = 1,
 553                 .mask = BIT(19) | BIT(20) | BIT(21) | BIT(23),
 554         },
 555 };
 556
 557 static const struct sirfsoc_padmux usp0_only_urfs_padmux = {
 558         .muxmask_counts = ARRAY_SIZE(usp0_only_urfs_muxmask),
 559         .muxmask = usp0_only_urfs_muxmask,
 560         .ctrlreg = SIRFSOC_RSC_PIN_MUX,
 561         .funcmask = BIT(1) | BIT(2) | BIT(9),
 562         .funcval = 0,
 563 };
 564
 565 static const unsigned usp0_only_urfs_pins[] = { 51, 52, 53, 55 };
 566
 567 static const struct sirfsoc_muxmask usp0_uart_nostreamctrl_muxmask[] = {
 568         {
 569                 .group = 1,
 570                 .mask = BIT(20) | BIT(21),
 571         },
 572 };
 573
 574 static const struct sirfsoc_padmux usp0_uart_nostreamctrl_padmux = {
 575         .muxmask_counts = ARRAY_SIZE(usp0_uart_nostreamctrl_muxmask),
 576         .muxmask = usp0_uart_nostreamctrl_muxmask,
 577 };
 578
 579 static const unsigned usp0_uart_nostreamctrl_pins[] = { 52, 53 };
 580 static const struct sirfsoc_muxmask usp1_muxmask[] = {
 581         {
 582                 .group = 0,
 583                 .mask = BIT(15),
 584         }, {
 585                 .group = 1,
 586                 .mask = BIT(11) | BIT(12) | BIT(13) | BIT(14),
 587         },
 588 };
 589
 590 static const struct sirfsoc_padmux usp1_padmux = {
 591         .muxmask_counts = ARRAY_SIZE(usp1_muxmask),
 592         .muxmask = usp1_muxmask,
 593         .ctrlreg = SIRFSOC_RSC_PIN_MUX,
 594         .funcmask = BIT(16),
 595         .funcval = BIT(16),
 596 };
 597
 598 static const unsigned usp1_pins[] = { 15, 43, 44, 45, 46 };
 599
 600 static const struct sirfsoc_muxmask usp1_uart_nostreamctrl_muxmask[] = {
 601         {
 602                 .group = 1,
 603                 .mask = BIT(12) | BIT(13),
 604         },
 605 };
 606
 607 static const struct sirfsoc_padmux usp1_uart_nostreamctrl_padmux = {
 608         .muxmask_counts = ARRAY_SIZE(usp1_uart_nostreamctrl_muxmask),
 609         .muxmask = usp1_uart_nostreamctrl_muxmask,
 610         .ctrlreg = SIRFSOC_RSC_PIN_MUX,
 611         .funcmask = BIT(16),
 612         .funcval = BIT(16),
 613 };
 614
 615 static const unsigned usp1_uart_nostreamctrl_pins[] = { 44, 45 };
 616
 617 static const struct sirfsoc_muxmask nand_muxmask[] = {
 618         {
 619                 .group = 2,
 620                 .mask = BIT(2) | BIT(3) | BIT(28) | BIT(29) | BIT(30),
 621         }, {
 622                 .group = 3,
 623                 .mask = BIT(0) | BIT(1),
 624         },
 625 };
 626
 627 static const struct sirfsoc_padmux nand_padmux = {
 628         .muxmask_counts = ARRAY_SIZE(nand_muxmask),
 629         .muxmask = nand_muxmask,
 630         .ctrlreg = SIRFSOC_RSC_PIN_MUX,
 631         .funcmask = BIT(5) | BIT(19),
 632         .funcval = 0,
 633 };
 634
 635 static const unsigned nand_pins[] = { 66, 67, 92, 93, 94, 96, 97 };
 636
 637 static const struct sirfsoc_muxmask sdmmc0_muxmask[] = {
 638         {
 639                 .group = 3,
 640                 .mask = BIT(1),
 641         },
 642 };
 643
 644 static const struct sirfsoc_padmux sdmmc0_padmux = {
 645         .muxmask_counts = ARRAY_SIZE(sdmmc0_muxmask),
 646         .muxmask = sdmmc0_muxmask,
 647         .ctrlreg = SIRFSOC_RSC_PIN_MUX,
 648         .funcmask = BIT(5) | BIT(19),
 649         .funcval = BIT(19),
 650 };
 651
 652 static const unsigned sdmmc0_pins[] = { 97 };
 653
 654 static const struct sirfsoc_muxmask sdmmc2_muxmask[] = {
 655         {
 656                 .group = 0,
 657                 .mask = BIT(27) | BIT(28) | BIT(29),
 658         },
 659 };
 660
 661 static const struct sirfsoc_padmux sdmmc2_padmux = {
 662         .muxmask_counts = ARRAY_SIZE(sdmmc2_muxmask),
 663         .muxmask = sdmmc2_muxmask,
 664         .ctrlreg = SIRFSOC_RSC_PIN_MUX,
 665         .funcmask = BIT(11),
 666         .funcval = 0,
 667 };
 668
 669 static const unsigned sdmmc2_pins[] = { 27, 28, 29 };
 670
 671 static const struct sirfsoc_muxmask sdmmc2_nowp_muxmask[] = {
 672         {
 673                 .group = 0,
 674                 .mask = BIT(27) | BIT(28),
 675         },
 676 };
 677
 678 static const struct sirfsoc_padmux sdmmc2_nowp_padmux = {
 679         .muxmask_counts = ARRAY_SIZE(sdmmc2_nowp_muxmask),
 680         .muxmask = sdmmc2_nowp_muxmask,
 681         .ctrlreg = SIRFSOC_RSC_PIN_MUX,
 682         .funcmask = BIT(11),
 683         .funcval = 0,
 684 };
 685
 686 static const unsigned sdmmc2_nowp_pins[] = { 27, 28 };
 687
 688 static const struct sirfsoc_muxmask cko0_muxmask[] = {
 689         {
 690                 .group = 2,
 691                 .mask = BIT(14),
 692         },
 693 };
 694
 695 static const struct sirfsoc_padmux cko0_padmux = {
 696         .muxmask_counts = ARRAY_SIZE(cko0_muxmask),
 697         .muxmask = cko0_muxmask,
 698 };
 699
 700 static const unsigned cko0_pins[] = { 78 };
 701
 702 static const struct sirfsoc_muxmask vip_muxmask[] = {
 703         {
 704                 .group = 1,
 705                 .mask = BIT(4) | BIT(5) | BIT(6) | BIT(8) | BIT(9)
 706                         | BIT(24) | BIT(25) | BIT(26) | BIT(27) | BIT(28) |
 707                         BIT(29),
 708         },
 709 };
 710
 711 static const struct sirfsoc_padmux vip_padmux = {
 712         .muxmask_counts = ARRAY_SIZE(vip_muxmask),
 713         .muxmask = vip_muxmask,
 714         .ctrlreg = SIRFSOC_RSC_PIN_MUX,
 715         .funcmask = BIT(18),
 716         .funcval = BIT(18),
 717 };
 718
 719 static const unsigned vip_pins[] = { 36, 37, 38, 40, 41, 56, 57, 58, 59, 60, 61 };
 720
 721 static const struct sirfsoc_muxmask vip_noupli_muxmask[] = {
 722         {
 723                 .group = 0,
 724                 .mask = BIT(16) | BIT(17) | BIT(18) | BIT(19) | BIT(20)
 725                         | BIT(21) | BIT(22) | BIT(23),
 726         }, {
 727                 .group = 2,
 728                 .mask = BIT(23) | BIT(24) | BIT(25),
 729         },
 730 };
 731
 732 static const struct sirfsoc_padmux vip_noupli_padmux = {
 733         .muxmask_counts = ARRAY_SIZE(vip_noupli_muxmask),
 734         .muxmask = vip_noupli_muxmask,
 735         .ctrlreg = SIRFSOC_RSC_PIN_MUX,
 736         .funcmask = BIT(15),
 737         .funcval = BIT(15),
 738 };
 739
 740 static const unsigned vip_noupli_pins[] = { 16, 17, 18, 19, 20, 21, 22, 23, 87, 88, 89 };
 741
 742 static const struct sirfsoc_muxmask i2c0_muxmask[] = {
 743         {
 744                 .group = 2,
 745                 .mask = BIT(26) | BIT(27),
 746         },
 747 };
 748
 749 static const struct sirfsoc_padmux i2c0_padmux = {
 750         .muxmask_counts = ARRAY_SIZE(i2c0_muxmask),
 751         .muxmask = i2c0_muxmask,
 752 };
 753
 754 static const unsigned i2c0_pins[] = { 90, 91 };
 755
 756 static const struct sirfsoc_muxmask i2c1_muxmask[] = {
 757         {
 758                 .group = 0,
 759                 .mask = BIT(13) | BIT(15),
 760         },
 761 };
 762
 763 static const struct sirfsoc_padmux i2c1_padmux = {
 764         .muxmask_counts = ARRAY_SIZE(i2c1_muxmask),
 765         .muxmask = i2c1_muxmask,
 766         .ctrlreg = SIRFSOC_RSC_PIN_MUX,
 767         .funcmask = BIT(16),
 768         .funcval = 0,
 769 };
 770
 771 static const unsigned i2c1_pins[] = { 13, 15 };
 772
 773 static const struct sirfsoc_muxmask pwm0_muxmask[] = {
 774         {
 775                 .group = 0,
 776                 .mask = BIT(4),
 777         },
 778 };
 779
 780 static const struct sirfsoc_padmux pwm0_padmux = {
 781         .muxmask_counts = ARRAY_SIZE(pwm0_muxmask),
 782         .muxmask = pwm0_muxmask,
 783         .ctrlreg = SIRFSOC_RSC_PIN_MUX,
 784         .funcmask = BIT(12),
 785         .funcval = 0,
 786 };
 787
 788 static const unsigned pwm0_pins[] = { 4 };
 789
 790 static const struct sirfsoc_muxmask pwm1_muxmask[] = {
 791         {
 792                 .group = 0,
 793                 .mask = BIT(5),
 794         },
 795 };
 796
 797 static const struct sirfsoc_padmux pwm1_padmux = {
 798         .muxmask_counts = ARRAY_SIZE(pwm1_muxmask),
 799         .muxmask = pwm1_muxmask,
 800 };
 801
 802 static const unsigned pwm1_pins[] = { 5 };
 803
 804 static const struct sirfsoc_muxmask pwm2_muxmask[] = {
 805         {
 806                 .group = 0,
 807                 .mask = BIT(6),
 808         },
 809 };
 810
 811 static const struct sirfsoc_padmux pwm2_padmux = {
 812         .muxmask_counts = ARRAY_SIZE(pwm2_muxmask),
 813         .muxmask = pwm2_muxmask,
 814 };
 815
 816 static const unsigned pwm2_pins[] = { 6 };
 817
 818 static const struct sirfsoc_muxmask pwm3_muxmask[] = {
 819         {
 820                 .group = 0,
 821                 .mask = BIT(7),
 822         },
 823 };
 824
 825 static const struct sirfsoc_padmux pwm3_padmux = {
 826         .muxmask_counts = ARRAY_SIZE(pwm3_muxmask),
 827         .muxmask = pwm3_muxmask,
 828 };
 829
 830 static const unsigned pwm3_pins[] = { 7 };
 831
 832 static const struct sirfsoc_muxmask pwm4_muxmask[] = {
 833         {
 834                 .group = 2,
 835                 .mask = BIT(14),
 836         },
 837 };
 838
 839 static const struct sirfsoc_padmux pwm4_padmux = {
 840         .muxmask_counts = ARRAY_SIZE(pwm4_muxmask),
 841         .muxmask = pwm4_muxmask,
 842 };
 843
 844 static const unsigned pwm4_pins[] = { 78 };
 845
 846 static const struct sirfsoc_muxmask warm_rst_muxmask[] = {
 847         {
 848                 .group = 0,
 849                 .mask = BIT(8),
 850         },
 851 };
 852
 853 static const struct sirfsoc_padmux warm_rst_padmux = {
 854         .muxmask_counts = ARRAY_SIZE(warm_rst_muxmask),
 855         .muxmask = warm_rst_muxmask,
 856         .ctrlreg = SIRFSOC_RSC_PIN_MUX,
 857         .funcmask = BIT(4),
 858         .funcval = 0,
 859 };
 860
 861 static const unsigned warm_rst_pins[] = { 8 };
 862
 863 static const struct sirfsoc_muxmask usb0_upli_drvbus_muxmask[] = {
 864         {
 865                 .group = 1,
 866                 .mask = BIT(4) | BIT(5) | BIT(6) | BIT(7) | BIT(8)
 867                         | BIT(9) | BIT(24) | BIT(25) | BIT(26) |
 868                         BIT(27) | BIT(28) | BIT(29),
 869         },
 870 };
 871 static const struct sirfsoc_padmux usb0_upli_drvbus_padmux = {
 872         .muxmask_counts = ARRAY_SIZE(usb0_upli_drvbus_muxmask),
 873         .muxmask = usb0_upli_drvbus_muxmask,
 874         .ctrlreg = SIRFSOC_RSC_PIN_MUX,
 875         .funcmask = BIT(18),
 876         .funcval = 0,
 877 };
 878
 879 static const unsigned usb0_upli_drvbus_pins[] = { 36, 37, 38, 39, 40, 41, 56, 57, 58, 59, 60, 61 };
 880
 881 static const struct sirfsoc_muxmask usb1_utmi_drvbus_muxmask[] = {
 882         {
 883                 .group = 0,
 884                 .mask = BIT(28),
 885         },
 886 };
 887
 888 static const struct sirfsoc_padmux usb1_utmi_drvbus_padmux = {
 889         .muxmask_counts = ARRAY_SIZE(usb1_utmi_drvbus_muxmask),
 890         .muxmask = usb1_utmi_drvbus_muxmask,
 891         .ctrlreg = SIRFSOC_RSC_PIN_MUX,
 892         .funcmask = BIT(11),
 893         .funcval = BIT(11), /* refer to PAD_UTMI_DRVVBUS1_ENABLE */
 894 };
 895
 896 static const unsigned usb1_utmi_drvbus_pins[] = { 28 };
 897
 898 static const struct sirfsoc_padmux usb1_dp_dn_padmux = {
 899         .muxmask_counts = 0,
 900         .ctrlreg = SIRFSOC_RSC_USB_UART_SHARE,
 901         .funcmask = BIT(2),
 902         .funcval = BIT(2),
 903 };
 904
 905 static const unsigned usb1_dp_dn_pins[] = { 103, 104 };
 906
 907 static const struct sirfsoc_padmux uart1_route_io_usb1_padmux = {
 908         .muxmask_counts = 0,
 909         .ctrlreg = SIRFSOC_RSC_USB_UART_SHARE,
 910         .funcmask = BIT(2),
 911         .funcval = 0,
 912 };
 913
 914 static const unsigned uart1_route_io_usb1_pins[] = { 103, 104 };
 915
 916 static const struct sirfsoc_muxmask pulse_count_muxmask[] = {
 917         {
 918                 .group = 0,
 919                 .mask = BIT(9) | BIT(10) | BIT(11),
 920         },
 921 };
 922
 923 static const struct sirfsoc_padmux pulse_count_padmux = {
 924         .muxmask_counts = ARRAY_SIZE(pulse_count_muxmask),
 925         .muxmask = pulse_count_muxmask,
 926 };
 927
 928 static const unsigned pulse_count_pins[] = { 9, 10, 11 };
 929
 930 static const struct sirfsoc_pin_group sirfsoc_pin_groups[] = {
 931         SIRFSOC_PIN_GROUP("lcd_16bitsgrp", lcd_16bits_pins),
 932         SIRFSOC_PIN_GROUP("lcd_18bitsgrp", lcd_18bits_pins),
 933         SIRFSOC_PIN_GROUP("lcd_24bitsgrp", lcd_24bits_pins),
 934         SIRFSOC_PIN_GROUP("lcdrom_grp", lcdrom_pins),
 935         SIRFSOC_PIN_GROUP("uart0grp", uart0_pins),
 936         SIRFSOC_PIN_GROUP("uart0_nostreamctrlgrp", uart0_nostreamctrl_pins),
 937         SIRFSOC_PIN_GROUP("uart1grp", uart1_pins),
 938         SIRFSOC_PIN_GROUP("uart2grp", uart2_pins),
 939         SIRFSOC_PIN_GROUP("uart2_nostreamctrlgrp", uart2_nostreamctrl_pins),
 940         SIRFSOC_PIN_GROUP("usp0grp", usp0_pins),
 941         SIRFSOC_PIN_GROUP("usp0_uart_nostreamctrl_grp",
 942                                         usp0_uart_nostreamctrl_pins),
 943         SIRFSOC_PIN_GROUP("usp0_only_utfs_grp", usp0_only_utfs_pins),
 944         SIRFSOC_PIN_GROUP("usp0_only_urfs_grp", usp0_only_urfs_pins),
 945         SIRFSOC_PIN_GROUP("usp1grp", usp1_pins),
 946         SIRFSOC_PIN_GROUP("usp1_uart_nostreamctrl_grp",
 947                                         usp1_uart_nostreamctrl_pins),
 948         SIRFSOC_PIN_GROUP("i2c0grp", i2c0_pins),
 949         SIRFSOC_PIN_GROUP("i2c1grp", i2c1_pins),
 950         SIRFSOC_PIN_GROUP("pwm0grp", pwm0_pins),
 951         SIRFSOC_PIN_GROUP("pwm1grp", pwm1_pins),
 952         SIRFSOC_PIN_GROUP("pwm2grp", pwm2_pins),
 953         SIRFSOC_PIN_GROUP("pwm3grp", pwm3_pins),
 954         SIRFSOC_PIN_GROUP("pwm4grp", pwm4_pins),
 955         SIRFSOC_PIN_GROUP("vipgrp", vip_pins),
 956         SIRFSOC_PIN_GROUP("vip_noupligrp", vip_noupli_pins),
 957         SIRFSOC_PIN_GROUP("warm_rstgrp", warm_rst_pins),
 958         SIRFSOC_PIN_GROUP("cko0grp", cko0_pins),
 959         SIRFSOC_PIN_GROUP("cko1grp", cko1_pins),
 960         SIRFSOC_PIN_GROUP("sdmmc0grp", sdmmc0_pins),
 961         SIRFSOC_PIN_GROUP("sdmmc1grp", sdmmc1_pins),
 962         SIRFSOC_PIN_GROUP("sdmmc2grp", sdmmc2_pins),
 963         SIRFSOC_PIN_GROUP("sdmmc2_nowpgrp", sdmmc2_nowp_pins),
 964         SIRFSOC_PIN_GROUP("sdmmc3grp", sdmmc3_pins),
 965         SIRFSOC_PIN_GROUP("sdmmc5grp", sdmmc5_pins),
 966         SIRFSOC_PIN_GROUP("usb0_upli_drvbusgrp", usb0_upli_drvbus_pins),
 967         SIRFSOC_PIN_GROUP("usb1_utmi_drvbusgrp", usb1_utmi_drvbus_pins),
 968         SIRFSOC_PIN_GROUP("usb1_dp_dngrp", usb1_dp_dn_pins),
 969         SIRFSOC_PIN_GROUP("uart1_route_io_usb1grp", uart1_route_io_usb1_pins),
 970         SIRFSOC_PIN_GROUP("pulse_countgrp", pulse_count_pins),
 971         SIRFSOC_PIN_GROUP("i2sgrp", i2s_pins),
 972         SIRFSOC_PIN_GROUP("i2s_no_dingrp", i2s_no_din_pins),
 973         SIRFSOC_PIN_GROUP("i2s_6chngrp", i2s_6chn_pins),
 974         SIRFSOC_PIN_GROUP("ac97grp", ac97_pins),
 975         SIRFSOC_PIN_GROUP("nandgrp", nand_pins),
 976         SIRFSOC_PIN_GROUP("spi0grp", spi0_pins),
 977         SIRFSOC_PIN_GROUP("spi1grp", spi1_pins),
 978         SIRFSOC_PIN_GROUP("gpsgrp", gps_pins),
 979 };
 980
 981 static const char * const lcd_16bitsgrp[] = { "lcd_16bitsgrp" };
 982 static const char * const lcd_18bitsgrp[] = { "lcd_18bitsgrp" };
 983 static const char * const lcd_24bitsgrp[] = { "lcd_24bitsgrp" };
 984 static const char * const lcdromgrp[] = { "lcdromgrp" };
 985 static const char * const uart0grp[] = { "uart0grp" };
 986 static const char * const uart0_nostreamctrlgrp[] = { "uart0_nostreamctrlgrp" };
 987 static const char * const uart1grp[] = { "uart1grp" };
 988 static const char * const uart2grp[] = { "uart2grp" };
 989 static const char * const uart2_nostreamctrlgrp[] = { "uart2_nostreamctrlgrp" };
 990 static const char * const usp0_uart_nostreamctrl_grp[] = {
 991                                         "usp0_uart_nostreamctrl_grp" };
 992 static const char * const usp0grp[] = { "usp0grp" };
 993 static const char * const usp0_only_utfs_grp[] = { "usp0_only_utfs_grp" };
 994 static const char * const usp0_only_urfs_grp[] = { "usp0_only_urfs_grp" };
 995
 996 static const char * const usp1grp[] = { "usp1grp" };
 997 static const char * const usp1_uart_nostreamctrl_grp[] = {
 998                                         "usp1_uart_nostreamctrl_grp" };
 999 static const char * const i2c0grp[] = { "i2c0grp" };
1000 static const char * const i2c1grp[] = { "i2c1grp" };
1001 static const char * const pwm0grp[] = { "pwm0grp" };
1002 static const char * const pwm1grp[] = { "pwm1grp" };
1003 static const char * const pwm2grp[] = { "pwm2grp" };
1004 static const char * const pwm3grp[] = { "pwm3grp" };
1005 static const char * const pwm4grp[] = { "pwm4grp" };
1006 static const char * const vipgrp[] = { "vipgrp" };
1007 static const char * const vip_noupligrp[] = { "vip_noupligrp" };
1008 static const char * const warm_rstgrp[] = { "warm_rstgrp" };
1009 static const char * const cko0grp[] = { "cko0grp" };
1010 static const char * const cko1grp[] = { "cko1grp" };
1011 static const char * const sdmmc0grp[] = { "sdmmc0grp" };
1012 static const char * const sdmmc1grp[] = { "sdmmc1grp" };
1013 static const char * const sdmmc2grp[] = { "sdmmc2grp" };
1014 static const char * const sdmmc3grp[] = { "sdmmc3grp" };
1015 static const char * const sdmmc5grp[] = { "sdmmc5grp" };
1016 static const char * const sdmmc2_nowpgrp[] = { "sdmmc2_nowpgrp" };
1017 static const char * const usb0_upli_drvbusgrp[] = { "usb0_upli_drvbusgrp" };
1018 static const char * const usb1_utmi_drvbusgrp[] = { "usb1_utmi_drvbusgrp" };
1019 static const char * const usb1_dp_dngrp[] = { "usb1_dp_dngrp" };
1020 static const char * const uart1_route_io_usb1grp[] = { "uart1_route_io_usb1grp" };
1021 static const char * const pulse_countgrp[] = { "pulse_countgrp" };
1022 static const char * const i2sgrp[] = { "i2sgrp" };
1023 static const char * const i2s_no_dingrp[] = { "i2s_no_dingrp" };
1024 static const char * const i2s_6chngrp[] = { "i2s_6chngrp" };
1025 static const char * const ac97grp[] = { "ac97grp" };
1026 static const char * const nandgrp[] = { "nandgrp" };
1027 static const char * const spi0grp[] = { "spi0grp" };
1028 static const char * const spi1grp[] = { "spi1grp" };
1029 static const char * const gpsgrp[] = { "gpsgrp" };
1030
1031 static const struct sirfsoc_pmx_func sirfsoc_pmx_functions[] = {
1032         SIRFSOC_PMX_FUNCTION("lcd_16bits", lcd_16bitsgrp, lcd_16bits_padmux),
1033         SIRFSOC_PMX_FUNCTION("lcd_18bits", lcd_18bitsgrp, lcd_18bits_padmux),
1034         SIRFSOC_PMX_FUNCTION("lcd_24bits", lcd_24bitsgrp, lcd_24bits_padmux),
1035         SIRFSOC_PMX_FUNCTION("lcdrom", lcdromgrp, lcdrom_padmux),
1036         SIRFSOC_PMX_FUNCTION("uart0", uart0grp, uart0_padmux),
1037         SIRFSOC_PMX_FUNCTION("uart0_nostreamctrl", uart0_nostreamctrlgrp,
1038                                                 uart0_nostreamctrl_padmux),
1039         SIRFSOC_PMX_FUNCTION("uart1", uart1grp, uart1_padmux),
1040         SIRFSOC_PMX_FUNCTION("uart2", uart2grp, uart2_padmux),
1041         SIRFSOC_PMX_FUNCTION("uart2_nostreamctrl", uart2_nostreamctrlgrp, uart2_nostreamctrl_padmux),
1042         SIRFSOC_PMX_FUNCTION("usp0", usp0grp, usp0_padmux),
1043         SIRFSOC_PMX_FUNCTION("usp0_uart_nostreamctrl",
1044                                                 usp0_uart_nostreamctrl_grp,
1045                                                 usp0_uart_nostreamctrl_padmux),
1046         SIRFSOC_PMX_FUNCTION("usp0_only_utfs", usp0_only_utfs_grp,
1047                                                 usp0_only_utfs_padmux),
1048         SIRFSOC_PMX_FUNCTION("usp0_only_urfs", usp0_only_urfs_grp,
1049                                                 usp0_only_urfs_padmux),
1050         SIRFSOC_PMX_FUNCTION("usp1", usp1grp, usp1_padmux),
1051         SIRFSOC_PMX_FUNCTION("usp1_uart_nostreamctrl",
1052                                                 usp1_uart_nostreamctrl_grp,
1053                                                 usp1_uart_nostreamctrl_padmux),
1054         SIRFSOC_PMX_FUNCTION("i2c0", i2c0grp, i2c0_padmux),
1055         SIRFSOC_PMX_FUNCTION("i2c1", i2c1grp, i2c1_padmux),
1056         SIRFSOC_PMX_FUNCTION("pwm0", pwm0grp, pwm0_padmux),
1057         SIRFSOC_PMX_FUNCTION("pwm1", pwm1grp, pwm1_padmux),
1058         SIRFSOC_PMX_FUNCTION("pwm2", pwm2grp, pwm2_padmux),
1059         SIRFSOC_PMX_FUNCTION("pwm3", pwm3grp, pwm3_padmux),
1060         SIRFSOC_PMX_FUNCTION("pwm4", pwm4grp, pwm4_padmux),
1061         SIRFSOC_PMX_FUNCTION("vip", vipgrp, vip_padmux),
1062         SIRFSOC_PMX_FUNCTION("vip_noupli", vip_noupligrp, vip_noupli_padmux),
1063         SIRFSOC_PMX_FUNCTION("warm_rst", warm_rstgrp, warm_rst_padmux),
1064         SIRFSOC_PMX_FUNCTION("cko0", cko0grp, cko0_padmux),
1065         SIRFSOC_PMX_FUNCTION("cko1", cko1grp, cko1_padmux),
1066         SIRFSOC_PMX_FUNCTION("sdmmc0", sdmmc0grp, sdmmc0_padmux),
1067         SIRFSOC_PMX_FUNCTION("sdmmc1", sdmmc1grp, sdmmc1_padmux),
1068         SIRFSOC_PMX_FUNCTION("sdmmc2", sdmmc2grp, sdmmc2_padmux),
1069         SIRFSOC_PMX_FUNCTION("sdmmc3", sdmmc3grp, sdmmc3_padmux),
1070         SIRFSOC_PMX_FUNCTION("sdmmc5", sdmmc5grp, sdmmc5_padmux),
1071         SIRFSOC_PMX_FUNCTION("sdmmc2_nowp", sdmmc2_nowpgrp, sdmmc2_nowp_padmux),
1072         SIRFSOC_PMX_FUNCTION("usb0_upli_drvbus", usb0_upli_drvbusgrp, usb0_upli_drvbus_padmux),
1073         SIRFSOC_PMX_FUNCTION("usb1_utmi_drvbus", usb1_utmi_drvbusgrp, usb1_utmi_drvbus_padmux),
1074         SIRFSOC_PMX_FUNCTION("usb1_dp_dn", usb1_dp_dngrp, usb1_dp_dn_padmux),
1075         SIRFSOC_PMX_FUNCTION("uart1_route_io_usb1", uart1_route_io_usb1grp, uart1_route_io_usb1_padmux),
1076         SIRFSOC_PMX_FUNCTION("pulse_count", pulse_countgrp, pulse_count_padmux),
1077         SIRFSOC_PMX_FUNCTION("i2s", i2sgrp, i2s_padmux),
1078         SIRFSOC_PMX_FUNCTION("i2s_no_din", i2s_no_dingrp, i2s_no_din_padmux),
1079         SIRFSOC_PMX_FUNCTION("i2s_6chn", i2s_6chngrp, i2s_6chn_padmux),
1080         SIRFSOC_PMX_FUNCTION("ac97", ac97grp, ac97_padmux),
1081         SIRFSOC_PMX_FUNCTION("nand", nandgrp, nand_padmux),
1082         SIRFSOC_PMX_FUNCTION("spi0", spi0grp, spi0_padmux),
1083         SIRFSOC_PMX_FUNCTION("spi1", spi1grp, spi1_padmux),
1084         SIRFSOC_PMX_FUNCTION("gps", gpsgrp, gps_padmux),
1085 };
1086
1087 struct sirfsoc_pinctrl_data atlas6_pinctrl_data = {
1088         (struct pinctrl_pin_desc *)sirfsoc_pads,
1089         ARRAY_SIZE(sirfsoc_pads),
1090         (struct sirfsoc_pin_group *)sirfsoc_pin_groups,
1091         ARRAY_SIZE(sirfsoc_pin_groups),
1092         (struct sirfsoc_pmx_func *)sirfsoc_pmx_functions,
1093         ARRAY_SIZE(sirfsoc_pmx_functions),
1094 };
1095