drivers/pinctrl/sirf/pinctrl-prima2.c

   1 /*
   2  * pinctrl pads, groups, functions for CSR SiRFprimaII
   3  *
   4  * Copyright (c) 2011 - 2014 Cambridge Silicon Radio Limited, a CSR plc group
   5  * company.
   6  *
   7  * Licensed under GPLv2 or later.
   8  */
   9
  10 #include <linux/pinctrl/pinctrl.h>
  11 #include <linux/bitops.h>
  12
  13 #include "pinctrl-sirf.h"
  14
  15 /*
  16  * pad list for the pinmux subsystem
  17  * refer to CS-131858-DC-6A.xls
  18  */
  19 static const struct pinctrl_pin_desc sirfsoc_pads[] = {
  20         PINCTRL_PIN(0, "gpio0-0"),
  21         PINCTRL_PIN(1, "gpio0-1"),
  22         PINCTRL_PIN(2, "gpio0-2"),
  23         PINCTRL_PIN(3, "gpio0-3"),
  24         PINCTRL_PIN(4, "pwm0"),
  25         PINCTRL_PIN(5, "pwm1"),
  26         PINCTRL_PIN(6, "pwm2"),
  27         PINCTRL_PIN(7, "pwm3"),
  28         PINCTRL_PIN(8, "warm_rst_b"),
  29         PINCTRL_PIN(9, "odo_0"),
  30         PINCTRL_PIN(10, "odo_1"),
  31         PINCTRL_PIN(11, "dr_dir"),
  32         PINCTRL_PIN(12, "viprom_fa"),
  33         PINCTRL_PIN(13, "scl_1"),
  34         PINCTRL_PIN(14, "ntrst"),
  35         PINCTRL_PIN(15, "sda_1"),
  36         PINCTRL_PIN(16, "x_ldd[16]"),
  37         PINCTRL_PIN(17, "x_ldd[17]"),
  38         PINCTRL_PIN(18, "x_ldd[18]"),
  39         PINCTRL_PIN(19, "x_ldd[19]"),
  40         PINCTRL_PIN(20, "x_ldd[20]"),
  41         PINCTRL_PIN(21, "x_ldd[21]"),
  42         PINCTRL_PIN(22, "x_ldd[22]"),
  43         PINCTRL_PIN(23, "x_ldd[23], lcdrom_frdy"),
  44         PINCTRL_PIN(24, "gps_sgn"),
  45         PINCTRL_PIN(25, "gps_mag"),
  46         PINCTRL_PIN(26, "gps_clk"),
  47         PINCTRL_PIN(27, "sd_cd_b_1"),
  48         PINCTRL_PIN(28, "sd_vcc_on_1"),
  49         PINCTRL_PIN(29, "sd_wp_b_1"),
  50         PINCTRL_PIN(30, "sd_clk_3"),
  51         PINCTRL_PIN(31, "sd_cmd_3"),
  52
  53         PINCTRL_PIN(32, "x_sd_dat_3[0]"),
  54         PINCTRL_PIN(33, "x_sd_dat_3[1]"),
  55         PINCTRL_PIN(34, "x_sd_dat_3[2]"),
  56         PINCTRL_PIN(35, "x_sd_dat_3[3]"),
  57         PINCTRL_PIN(36, "x_sd_clk_4"),
  58         PINCTRL_PIN(37, "x_sd_cmd_4"),
  59         PINCTRL_PIN(38, "x_sd_dat_4[0]"),
  60         PINCTRL_PIN(39, "x_sd_dat_4[1]"),
  61         PINCTRL_PIN(40, "x_sd_dat_4[2]"),
  62         PINCTRL_PIN(41, "x_sd_dat_4[3]"),
  63         PINCTRL_PIN(42, "x_cko_1"),
  64         PINCTRL_PIN(43, "x_ac97_bit_clk"),
  65         PINCTRL_PIN(44, "x_ac97_dout"),
  66         PINCTRL_PIN(45, "x_ac97_din"),
  67         PINCTRL_PIN(46, "x_ac97_sync"),
  68         PINCTRL_PIN(47, "x_txd_1"),
  69         PINCTRL_PIN(48, "x_txd_2"),
  70         PINCTRL_PIN(49, "x_rxd_1"),
  71         PINCTRL_PIN(50, "x_rxd_2"),
  72         PINCTRL_PIN(51, "x_usclk_0"),
  73         PINCTRL_PIN(52, "x_utxd_0"),
  74         PINCTRL_PIN(53, "x_urxd_0"),
  75         PINCTRL_PIN(54, "x_utfs_0"),
  76         PINCTRL_PIN(55, "x_urfs_0"),
  77         PINCTRL_PIN(56, "x_usclk_1"),
  78         PINCTRL_PIN(57, "x_utxd_1"),
  79         PINCTRL_PIN(58, "x_urxd_1"),
  80         PINCTRL_PIN(59, "x_utfs_1"),
  81         PINCTRL_PIN(60, "x_urfs_1"),
  82         PINCTRL_PIN(61, "x_usclk_2"),
  83         PINCTRL_PIN(62, "x_utxd_2"),
  84         PINCTRL_PIN(63, "x_urxd_2"),
  85
  86         PINCTRL_PIN(64, "x_utfs_2"),
  87         PINCTRL_PIN(65, "x_urfs_2"),
  88         PINCTRL_PIN(66, "x_df_we_b"),
  89         PINCTRL_PIN(67, "x_df_re_b"),
  90         PINCTRL_PIN(68, "x_txd_0"),
  91         PINCTRL_PIN(69, "x_rxd_0"),
  92         PINCTRL_PIN(78, "x_cko_0"),
  93         PINCTRL_PIN(79, "x_vip_pxd[7]"),
  94         PINCTRL_PIN(80, "x_vip_pxd[6]"),
  95         PINCTRL_PIN(81, "x_vip_pxd[5]"),
  96         PINCTRL_PIN(82, "x_vip_pxd[4]"),
  97         PINCTRL_PIN(83, "x_vip_pxd[3]"),
  98         PINCTRL_PIN(84, "x_vip_pxd[2]"),
  99         PINCTRL_PIN(85, "x_vip_pxd[1]"),
 100         PINCTRL_PIN(86, "x_vip_pxd[0]"),
 101         PINCTRL_PIN(87, "x_vip_vsync"),
 102         PINCTRL_PIN(88, "x_vip_hsync"),
 103         PINCTRL_PIN(89, "x_vip_pxclk"),
 104         PINCTRL_PIN(90, "x_sda_0"),
 105         PINCTRL_PIN(91, "x_scl_0"),
 106         PINCTRL_PIN(92, "x_df_ry_by"),
 107         PINCTRL_PIN(93, "x_df_cs_b[1]"),
 108         PINCTRL_PIN(94, "x_df_cs_b[0]"),
 109         PINCTRL_PIN(95, "x_l_pclk"),
 110
 111         PINCTRL_PIN(96, "x_l_lck"),
 112         PINCTRL_PIN(97, "x_l_fck"),
 113         PINCTRL_PIN(98, "x_l_de"),
 114         PINCTRL_PIN(99, "x_ldd[0]"),
 115         PINCTRL_PIN(100, "x_ldd[1]"),
 116         PINCTRL_PIN(101, "x_ldd[2]"),
 117         PINCTRL_PIN(102, "x_ldd[3]"),
 118         PINCTRL_PIN(103, "x_ldd[4]"),
 119         PINCTRL_PIN(104, "x_ldd[5]"),
 120         PINCTRL_PIN(105, "x_ldd[6]"),
 121         PINCTRL_PIN(106, "x_ldd[7]"),
 122         PINCTRL_PIN(107, "x_ldd[8]"),
 123         PINCTRL_PIN(108, "x_ldd[9]"),
 124         PINCTRL_PIN(109, "x_ldd[10]"),
 125         PINCTRL_PIN(110, "x_ldd[11]"),
 126         PINCTRL_PIN(111, "x_ldd[12]"),
 127         PINCTRL_PIN(112, "x_ldd[13]"),
 128         PINCTRL_PIN(113, "x_ldd[14]"),
 129         PINCTRL_PIN(114, "x_ldd[15]"),
 130
 131         PINCTRL_PIN(115, "x_usb1_dp"),
 132         PINCTRL_PIN(116, "x_usb1_dn"),
 133 };
 134
 135 static const struct sirfsoc_muxmask lcd_16bits_sirfsoc_muxmask[] = {
 136         {
 137                 .group = 3,
 138                 .mask = BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) | BIT(6) | BIT(7) | BIT(8) |
 139                         BIT(9) | BIT(10) | BIT(11) | BIT(12) | BIT(13) | BIT(14) | BIT(15) | BIT(16) |
 140                         BIT(17) | BIT(18),
 141         }, {
 142                 .group = 2,
 143                 .mask = BIT(31),
 144         },
 145 };
 146
 147 static const struct sirfsoc_padmux lcd_16bits_padmux = {
 148         .muxmask_counts = ARRAY_SIZE(lcd_16bits_sirfsoc_muxmask),
 149         .muxmask = lcd_16bits_sirfsoc_muxmask,
 150         .ctrlreg = SIRFSOC_RSC_PIN_MUX,
 151         .funcmask = BIT(4),
 152         .funcval = 0,
 153 };
 154
 155 static const unsigned lcd_16bits_pins[] = { 95, 96, 97, 98, 99, 100, 101, 102, 103, 104,
 156         105, 106, 107, 108, 109, 110, 111, 112, 113, 114 };
 157
 158 static const struct sirfsoc_muxmask lcd_18bits_muxmask[] = {
 159         {
 160                 .group = 3,
 161                 .mask = BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) | BIT(6) | BIT(7) | BIT(8) |
 162                         BIT(9) | BIT(10) | BIT(11) | BIT(12) | BIT(13) | BIT(14) | BIT(15) | BIT(16) |
 163                         BIT(17) | BIT(18),
 164         }, {
 165                 .group = 2,
 166                 .mask = BIT(31),
 167         }, {
 168                 .group = 0,
 169                 .mask = BIT(16) | BIT(17),
 170         },
 171 };
 172
 173 static const struct sirfsoc_padmux lcd_18bits_padmux = {
 174         .muxmask_counts = ARRAY_SIZE(lcd_18bits_muxmask),
 175         .muxmask = lcd_18bits_muxmask,
 176         .ctrlreg = SIRFSOC_RSC_PIN_MUX,
 177         .funcmask = BIT(4),
 178         .funcval = 0,
 179 };
 180
 181 static const unsigned lcd_18bits_pins[] = { 16, 17, 95, 96, 97, 98, 99, 100, 101, 102, 103, 104,
 182         105, 106, 107, 108, 109, 110, 111, 112, 113, 114};
 183
 184 static const struct sirfsoc_muxmask lcd_24bits_muxmask[] = {
 185         {
 186                 .group = 3,
 187                 .mask = BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) | BIT(6) | BIT(7) | BIT(8) |
 188                         BIT(9) | BIT(10) | BIT(11) | BIT(12) | BIT(13) | BIT(14) | BIT(15) | BIT(16) |
 189                         BIT(17) | BIT(18),
 190         }, {
 191                 .group = 2,
 192                 .mask = BIT(31),
 193         }, {
 194                 .group = 0,
 195                 .mask = BIT(16) | BIT(17) | BIT(18) | BIT(19) | BIT(20) | BIT(21) | BIT(22) | BIT(23),
 196         },
 197 };
 198
 199 static const struct sirfsoc_padmux lcd_24bits_padmux = {
 200         .muxmask_counts = ARRAY_SIZE(lcd_24bits_muxmask),
 201         .muxmask = lcd_24bits_muxmask,
 202         .ctrlreg = SIRFSOC_RSC_PIN_MUX,
 203         .funcmask = BIT(4),
 204         .funcval = 0,
 205 };
 206
 207 static const unsigned lcd_24bits_pins[] = { 16, 17, 18, 19, 20, 21, 22, 23, 95, 96, 97, 98, 99, 100, 101, 102, 103, 104,
 208         105, 106, 107, 108, 109, 110, 111, 112, 113, 114 };
 209
 210 static const struct sirfsoc_muxmask lcdrom_muxmask[] = {
 211         {
 212                 .group = 3,
 213                 .mask = BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) | BIT(6) | BIT(7) | BIT(8) |
 214                         BIT(9) | BIT(10) | BIT(11) | BIT(12) | BIT(13) | BIT(14) | BIT(15) | BIT(16) |
 215                         BIT(17) | BIT(18),
 216         }, {
 217                 .group = 2,
 218                 .mask = BIT(31),
 219         }, {
 220                 .group = 0,
 221                 .mask = BIT(23),
 222         },
 223 };
 224
 225 static const struct sirfsoc_padmux lcdrom_padmux = {
 226         .muxmask_counts = ARRAY_SIZE(lcdrom_muxmask),
 227         .muxmask = lcdrom_muxmask,
 228         .ctrlreg = SIRFSOC_RSC_PIN_MUX,
 229         .funcmask = BIT(4),
 230         .funcval = BIT(4),
 231 };
 232
 233 static const unsigned lcdrom_pins[] = { 23, 95, 96, 97, 98, 99, 100, 101, 102, 103, 104,
 234         105, 106, 107, 108, 109, 110, 111, 112, 113, 114 };
 235
 236 static const struct sirfsoc_muxmask uart0_muxmask[] = {
 237         {
 238                 .group = 2,
 239                 .mask = BIT(4) | BIT(5),
 240         }, {
 241                 .group = 1,
 242                 .mask = BIT(23) | BIT(28),
 243         },
 244 };
 245
 246 static const struct sirfsoc_padmux uart0_padmux = {
 247         .muxmask_counts = ARRAY_SIZE(uart0_muxmask),
 248         .muxmask = uart0_muxmask,
 249         .ctrlreg = SIRFSOC_RSC_PIN_MUX,
 250         .funcmask = BIT(9),
 251         .funcval = BIT(9),
 252 };
 253
 254 static const unsigned uart0_pins[] = { 55, 60, 68, 69 };
 255
 256 static const struct sirfsoc_muxmask uart0_nostreamctrl_muxmask[] = {
 257         {
 258                 .group = 2,
 259                 .mask = BIT(4) | BIT(5),
 260         },
 261 };
 262
 263 static const struct sirfsoc_padmux uart0_nostreamctrl_padmux = {
 264         .muxmask_counts = ARRAY_SIZE(uart0_nostreamctrl_muxmask),
 265         .muxmask = uart0_nostreamctrl_muxmask,
 266 };
 267
 268 static const unsigned uart0_nostreamctrl_pins[] = { 68, 69 };
 269
 270 static const struct sirfsoc_muxmask uart1_muxmask[] = {
 271         {
 272                 .group = 1,
 273                 .mask = BIT(15) | BIT(17),
 274         },
 275 };
 276
 277 static const struct sirfsoc_padmux uart1_padmux = {
 278         .muxmask_counts = ARRAY_SIZE(uart1_muxmask),
 279         .muxmask = uart1_muxmask,
 280 };
 281
 282 static const unsigned uart1_pins[] = { 47, 49 };
 283
 284 static const struct sirfsoc_muxmask uart2_muxmask[] = {
 285         {
 286                 .group = 1,
 287                 .mask = BIT(16) | BIT(18) | BIT(24) | BIT(27),
 288         },
 289 };
 290
 291 static const struct sirfsoc_padmux uart2_padmux = {
 292         .muxmask_counts = ARRAY_SIZE(uart2_muxmask),
 293         .muxmask = uart2_muxmask,
 294         .ctrlreg = SIRFSOC_RSC_PIN_MUX,
 295         .funcmask = BIT(10),
 296         .funcval = BIT(10),
 297 };
 298
 299 static const unsigned uart2_pins[] = { 48, 50, 56, 59 };
 300
 301 static const struct sirfsoc_muxmask uart2_nostreamctrl_muxmask[] = {
 302         {
 303                 .group = 1,
 304                 .mask = BIT(16) | BIT(18),
 305         },
 306 };
 307
 308 static const struct sirfsoc_padmux uart2_nostreamctrl_padmux = {
 309         .muxmask_counts = ARRAY_SIZE(uart2_nostreamctrl_muxmask),
 310         .muxmask = uart2_nostreamctrl_muxmask,
 311 };
 312
 313 static const unsigned uart2_nostreamctrl_pins[] = { 48, 50 };
 314
 315 static const struct sirfsoc_muxmask sdmmc3_muxmask[] = {
 316         {
 317                 .group = 0,
 318                 .mask = BIT(30) | BIT(31),
 319         }, {
 320                 .group = 1,
 321                 .mask = BIT(0) | BIT(1) | BIT(2) | BIT(3),
 322         },
 323 };
 324
 325 static const struct sirfsoc_padmux sdmmc3_padmux = {
 326         .muxmask_counts = ARRAY_SIZE(sdmmc3_muxmask),
 327         .muxmask = sdmmc3_muxmask,
 328         .ctrlreg = SIRFSOC_RSC_PIN_MUX,
 329         .funcmask = BIT(7),
 330         .funcval = 0,
 331 };
 332
 333 static const unsigned sdmmc3_pins[] = { 30, 31, 32, 33, 34, 35 };
 334
 335 static const struct sirfsoc_muxmask spi0_muxmask[] = {
 336         {
 337                 .group = 1,
 338                 .mask = BIT(0) | BIT(1) | BIT(2) | BIT(3),
 339         },
 340 };
 341
 342 static const struct sirfsoc_padmux spi0_padmux = {
 343         .muxmask_counts = ARRAY_SIZE(spi0_muxmask),
 344         .muxmask = spi0_muxmask,
 345         .ctrlreg = SIRFSOC_RSC_PIN_MUX,
 346         .funcmask = BIT(7),
 347         .funcval = BIT(7),
 348 };
 349
 350 static const unsigned spi0_pins[] = { 32, 33, 34, 35 };
 351
 352 static const struct sirfsoc_muxmask sdmmc4_muxmask[] = {
 353         {
 354                 .group = 1,
 355                 .mask = BIT(4) | BIT(5) | BIT(6) | BIT(7) | BIT(8) | BIT(9),
 356         },
 357 };
 358
 359 static const struct sirfsoc_padmux sdmmc4_padmux = {
 360         .muxmask_counts = ARRAY_SIZE(sdmmc4_muxmask),
 361         .muxmask = sdmmc4_muxmask,
 362 };
 363
 364 static const unsigned sdmmc4_pins[] = { 36, 37, 38, 39, 40, 41 };
 365
 366 static const struct sirfsoc_muxmask cko1_muxmask[] = {
 367         {
 368                 .group = 1,
 369                 .mask = BIT(10),
 370         },
 371 };
 372
 373 static const struct sirfsoc_padmux cko1_padmux = {
 374         .muxmask_counts = ARRAY_SIZE(cko1_muxmask),
 375         .muxmask = cko1_muxmask,
 376         .ctrlreg = SIRFSOC_RSC_PIN_MUX,
 377         .funcmask = BIT(3),
 378         .funcval = 0,
 379 };
 380
 381 static const unsigned cko1_pins[] = { 42 };
 382
 383 static const struct sirfsoc_muxmask i2s_muxmask[] = {
 384         {
 385                 .group = 1,
 386                 .mask =
 387                         BIT(10) | BIT(11) | BIT(12) | BIT(13) | BIT(14) | BIT(19)
 388                                 | BIT(23) | BIT(28),
 389         },
 390 };
 391
 392 static const struct sirfsoc_padmux i2s_padmux = {
 393         .muxmask_counts = ARRAY_SIZE(i2s_muxmask),
 394         .muxmask = i2s_muxmask,
 395         .ctrlreg = SIRFSOC_RSC_PIN_MUX,
 396         .funcmask = BIT(3) | BIT(9),
 397         .funcval = BIT(3),
 398 };
 399
 400 static const unsigned i2s_pins[] = { 42, 43, 44, 45, 46, 51, 55, 60 };
 401
 402 static const struct sirfsoc_muxmask ac97_muxmask[] = {
 403         {
 404                 .group = 1,
 405                 .mask = BIT(11) | BIT(12) | BIT(13) | BIT(14),
 406         },
 407 };
 408
 409 static const struct sirfsoc_padmux ac97_padmux = {
 410         .muxmask_counts = ARRAY_SIZE(ac97_muxmask),
 411         .muxmask = ac97_muxmask,
 412         .ctrlreg = SIRFSOC_RSC_PIN_MUX,
 413         .funcmask = BIT(8),
 414         .funcval = 0,
 415 };
 416
 417 static const unsigned ac97_pins[] = { 43, 44, 45, 46 };
 418
 419 static const struct sirfsoc_muxmask spi1_muxmask[] = {
 420         {
 421                 .group = 1,
 422                 .mask = BIT(11) | BIT(12) | BIT(13) | BIT(14),
 423         },
 424 };
 425
 426 static const struct sirfsoc_padmux spi1_padmux = {
 427         .muxmask_counts = ARRAY_SIZE(spi1_muxmask),
 428         .muxmask = spi1_muxmask,
 429         .ctrlreg = SIRFSOC_RSC_PIN_MUX,
 430         .funcmask = BIT(8),
 431         .funcval = BIT(8),
 432 };
 433
 434 static const unsigned spi1_pins[] = { 43, 44, 45, 46 };
 435
 436 static const struct sirfsoc_muxmask sdmmc1_muxmask[] = {
 437         {
 438                 .group = 0,
 439                 .mask = BIT(27) | BIT(28) | BIT(29),
 440         },
 441 };
 442
 443 static const struct sirfsoc_padmux sdmmc1_padmux = {
 444         .muxmask_counts = ARRAY_SIZE(sdmmc1_muxmask),
 445         .muxmask = sdmmc1_muxmask,
 446 };
 447
 448 static const unsigned sdmmc1_pins[] = { 27, 28, 29 };
 449
 450 static const struct sirfsoc_muxmask gps_muxmask[] = {
 451         {
 452                 .group = 0,
 453                 .mask = BIT(24) | BIT(25) | BIT(26),
 454         },
 455 };
 456
 457 static const struct sirfsoc_padmux gps_padmux = {
 458         .muxmask_counts = ARRAY_SIZE(gps_muxmask),
 459         .muxmask = gps_muxmask,
 460         .ctrlreg = SIRFSOC_RSC_PIN_MUX,
 461         .funcmask = BIT(12) | BIT(13) | BIT(14),
 462         .funcval = BIT(12),
 463 };
 464
 465 static const unsigned gps_pins[] = { 24, 25, 26 };
 466
 467 static const struct sirfsoc_muxmask sdmmc5_muxmask[] = {
 468         {
 469                 .group = 0,
 470                 .mask = BIT(24) | BIT(25) | BIT(26),
 471         },
 472 };
 473
 474 static const struct sirfsoc_padmux sdmmc5_padmux = {
 475         .muxmask_counts = ARRAY_SIZE(sdmmc5_muxmask),
 476         .muxmask = sdmmc5_muxmask,
 477         .ctrlreg = SIRFSOC_RSC_PIN_MUX,
 478         .funcmask = BIT(13) | BIT(14),
 479         .funcval = BIT(13) | BIT(14),
 480 };
 481
 482 static const unsigned sdmmc5_pins[] = { 24, 25, 26 };
 483
 484 static const struct sirfsoc_muxmask usp0_muxmask[] = {
 485         {
 486                 .group = 1,
 487                 .mask = BIT(19) | BIT(20) | BIT(21) | BIT(22) | BIT(23),
 488         },
 489 };
 490
 491 static const struct sirfsoc_padmux usp0_padmux = {
 492         .muxmask_counts = ARRAY_SIZE(usp0_muxmask),
 493         .muxmask = usp0_muxmask,
 494         .ctrlreg = SIRFSOC_RSC_PIN_MUX,
 495         .funcmask = BIT(1) | BIT(2) | BIT(6) | BIT(9),
 496         .funcval = 0,
 497 };
 498
 499 static const unsigned usp0_pins[] = { 51, 52, 53, 54, 55 };
 500
 501 static const struct sirfsoc_muxmask usp0_only_utfs_muxmask[] = {
 502         {
 503                 .group = 1,
 504                 .mask = BIT(19) | BIT(20) | BIT(21) | BIT(22),
 505         },
 506 };
 507
 508 static const struct sirfsoc_padmux usp0_only_utfs_padmux = {
 509         .muxmask_counts = ARRAY_SIZE(usp0_only_utfs_muxmask),
 510         .muxmask = usp0_only_utfs_muxmask,
 511         .ctrlreg = SIRFSOC_RSC_PIN_MUX,
 512         .funcmask = BIT(1) | BIT(2) | BIT(6),
 513         .funcval = 0,
 514 };
 515
 516 static const unsigned usp0_only_utfs_pins[] = { 51, 52, 53, 54 };
 517
 518 static const struct sirfsoc_muxmask usp0_only_urfs_muxmask[] = {
 519         {
 520                 .group = 1,
 521                 .mask = BIT(19) | BIT(20) | BIT(21) | BIT(23),
 522         },
 523 };
 524
 525 static const struct sirfsoc_padmux usp0_only_urfs_padmux = {
 526         .muxmask_counts = ARRAY_SIZE(usp0_only_urfs_muxmask),
 527         .muxmask = usp0_only_urfs_muxmask,
 528         .ctrlreg = SIRFSOC_RSC_PIN_MUX,
 529         .funcmask = BIT(1) | BIT(2) | BIT(9),
 530         .funcval = 0,
 531 };
 532
 533 static const unsigned usp0_only_urfs_pins[] = { 51, 52, 53, 55 };
 534
 535 static const struct sirfsoc_muxmask usp0_uart_nostreamctrl_muxmask[] = {
 536         {
 537                 .group = 1,
 538                 .mask = BIT(20) | BIT(21),
 539         },
 540 };
 541
 542 static const struct sirfsoc_padmux usp0_uart_nostreamctrl_padmux = {
 543         .muxmask_counts = ARRAY_SIZE(usp0_uart_nostreamctrl_muxmask),
 544         .muxmask = usp0_uart_nostreamctrl_muxmask,
 545 };
 546
 547 static const unsigned usp0_uart_nostreamctrl_pins[] = { 52, 53 };
 548
 549 static const struct sirfsoc_muxmask usp1_muxmask[] = {
 550         {
 551                 .group = 1,
 552                 .mask = BIT(24) | BIT(25) | BIT(26) | BIT(27) | BIT(28),
 553         },
 554 };
 555
 556 static const struct sirfsoc_padmux usp1_padmux = {
 557         .muxmask_counts = ARRAY_SIZE(usp1_muxmask),
 558         .muxmask = usp1_muxmask,
 559         .ctrlreg = SIRFSOC_RSC_PIN_MUX,
 560         .funcmask = BIT(1) | BIT(9) | BIT(10) | BIT(11),
 561         .funcval = 0,
 562 };
 563
 564 static const unsigned usp1_pins[] = { 56, 57, 58, 59, 60 };
 565
 566 static const struct sirfsoc_muxmask usp1_uart_nostreamctrl_muxmask[] = {
 567         {
 568                 .group = 1,
 569                 .mask = BIT(25) | BIT(26),
 570         },
 571 };
 572
 573 static const struct sirfsoc_padmux usp1_uart_nostreamctrl_padmux = {
 574         .muxmask_counts = ARRAY_SIZE(usp1_uart_nostreamctrl_muxmask),
 575         .muxmask = usp1_uart_nostreamctrl_muxmask,
 576 };
 577
 578 static const unsigned usp1_uart_nostreamctrl_pins[] = { 57, 58 };
 579
 580 static const struct sirfsoc_muxmask usp2_muxmask[] = {
 581         {
 582                 .group = 1,
 583                 .mask = BIT(29) | BIT(30) | BIT(31),
 584         }, {
 585                 .group = 2,
 586                 .mask = BIT(0) | BIT(1),
 587         },
 588 };
 589
 590 static const struct sirfsoc_padmux usp2_padmux = {
 591         .muxmask_counts = ARRAY_SIZE(usp2_muxmask),
 592         .muxmask = usp2_muxmask,
 593         .ctrlreg = SIRFSOC_RSC_PIN_MUX,
 594         .funcmask = BIT(13) | BIT(14),
 595         .funcval = 0,
 596 };
 597
 598 static const unsigned usp2_pins[] = { 61, 62, 63, 64, 65 };
 599
 600 static const struct sirfsoc_muxmask usp2_uart_nostreamctrl_muxmask[] = {
 601         {
 602                 .group = 1,
 603                 .mask = BIT(30) | BIT(31),
 604         },
 605 };
 606
 607 static const struct sirfsoc_padmux usp2_uart_nostreamctrl_padmux = {
 608         .muxmask_counts = ARRAY_SIZE(usp2_uart_nostreamctrl_muxmask),
 609         .muxmask = usp2_uart_nostreamctrl_muxmask,
 610 };
 611
 612 static const unsigned usp2_uart_nostreamctrl_pins[] = { 62, 63 };
 613
 614 static const struct sirfsoc_muxmask nand_muxmask[] = {
 615         {
 616                 .group = 2,
 617                 .mask = BIT(2) | BIT(3) | BIT(28) | BIT(29) | BIT(30),
 618         },
 619 };
 620
 621 static const struct sirfsoc_padmux nand_padmux = {
 622         .muxmask_counts = ARRAY_SIZE(nand_muxmask),
 623         .muxmask = nand_muxmask,
 624         .ctrlreg = SIRFSOC_RSC_PIN_MUX,
 625         .funcmask = BIT(5),
 626         .funcval = 0,
 627 };
 628
 629 static const unsigned nand_pins[] = { 64, 65, 92, 93, 94 };
 630
 631 static const struct sirfsoc_padmux sdmmc0_padmux = {
 632         .muxmask_counts = 0,
 633         .ctrlreg = SIRFSOC_RSC_PIN_MUX,
 634         .funcmask = BIT(5),
 635         .funcval = 0,
 636 };
 637
 638 static const unsigned sdmmc0_pins[] = { };
 639
 640 static const struct sirfsoc_muxmask sdmmc2_muxmask[] = {
 641         {
 642                 .group = 2,
 643                 .mask = BIT(2) | BIT(3),
 644         },
 645 };
 646
 647 static const struct sirfsoc_padmux sdmmc2_padmux = {
 648         .muxmask_counts = ARRAY_SIZE(sdmmc2_muxmask),
 649         .muxmask = sdmmc2_muxmask,
 650         .ctrlreg = SIRFSOC_RSC_PIN_MUX,
 651         .funcmask = BIT(5),
 652         .funcval = BIT(5),
 653 };
 654
 655 static const unsigned sdmmc2_pins[] = { 66, 67 };
 656
 657 static const struct sirfsoc_muxmask cko0_muxmask[] = {
 658         {
 659                 .group = 2,
 660                 .mask = BIT(14),
 661         },
 662 };
 663
 664 static const struct sirfsoc_padmux cko0_padmux = {
 665         .muxmask_counts = ARRAY_SIZE(cko0_muxmask),
 666         .muxmask = cko0_muxmask,
 667 };
 668
 669 static const unsigned cko0_pins[] = { 78 };
 670
 671 static const struct sirfsoc_muxmask vip_muxmask[] = {
 672         {
 673                 .group = 2,
 674                 .mask = BIT(15) | BIT(16) | BIT(17) | BIT(18) | BIT(19)
 675                         | BIT(20) | BIT(21) | BIT(22) | BIT(23) | BIT(24) |
 676                         BIT(25),
 677         },
 678 };
 679
 680 static const struct sirfsoc_padmux vip_padmux = {
 681         .muxmask_counts = ARRAY_SIZE(vip_muxmask),
 682         .muxmask = vip_muxmask,
 683         .ctrlreg = SIRFSOC_RSC_PIN_MUX,
 684         .funcmask = BIT(0),
 685         .funcval = 0,
 686 };
 687
 688 static const unsigned vip_pins[] = { 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89 };
 689
 690 static const struct sirfsoc_muxmask i2c0_muxmask[] = {
 691         {
 692                 .group = 2,
 693                 .mask = BIT(26) | BIT(27),
 694         },
 695 };
 696
 697 static const struct sirfsoc_padmux i2c0_padmux = {
 698         .muxmask_counts = ARRAY_SIZE(i2c0_muxmask),
 699         .muxmask = i2c0_muxmask,
 700 };
 701
 702 static const unsigned i2c0_pins[] = { 90, 91 };
 703
 704 static const struct sirfsoc_muxmask i2c1_muxmask[] = {
 705         {
 706                 .group = 0,
 707                 .mask = BIT(13) | BIT(15),
 708         },
 709 };
 710
 711 static const struct sirfsoc_padmux i2c1_padmux = {
 712         .muxmask_counts = ARRAY_SIZE(i2c1_muxmask),
 713         .muxmask = i2c1_muxmask,
 714 };
 715
 716 static const unsigned i2c1_pins[] = { 13, 15 };
 717
 718 static const struct sirfsoc_muxmask viprom_muxmask[] = {
 719         {
 720                 .group = 2,
 721                 .mask = BIT(15) | BIT(16) | BIT(17) | BIT(18) | BIT(19)
 722                         | BIT(20) | BIT(21) | BIT(22) | BIT(23) | BIT(24) |
 723                         BIT(25),
 724         }, {
 725                 .group = 0,
 726                 .mask = BIT(12),
 727         },
 728 };
 729
 730 static const struct sirfsoc_padmux viprom_padmux = {
 731         .muxmask_counts = ARRAY_SIZE(viprom_muxmask),
 732         .muxmask = viprom_muxmask,
 733         .ctrlreg = SIRFSOC_RSC_PIN_MUX,
 734         .funcmask = BIT(0),
 735         .funcval = BIT(0),
 736 };
 737
 738 static const unsigned viprom_pins[] = { 12, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89 };
 739
 740 static const struct sirfsoc_muxmask pwm0_muxmask[] = {
 741         {
 742                 .group = 0,
 743                 .mask = BIT(4),
 744         },
 745 };
 746
 747 static const struct sirfsoc_padmux pwm0_padmux = {
 748         .muxmask_counts = ARRAY_SIZE(pwm0_muxmask),
 749         .muxmask = pwm0_muxmask,
 750         .ctrlreg = SIRFSOC_RSC_PIN_MUX,
 751         .funcmask = BIT(12),
 752         .funcval = 0,
 753 };
 754
 755 static const unsigned pwm0_pins[] = { 4 };
 756
 757 static const struct sirfsoc_muxmask pwm1_muxmask[] = {
 758         {
 759                 .group = 0,
 760                 .mask = BIT(5),
 761         },
 762 };
 763
 764 static const struct sirfsoc_padmux pwm1_padmux = {
 765         .muxmask_counts = ARRAY_SIZE(pwm1_muxmask),
 766         .muxmask = pwm1_muxmask,
 767 };
 768
 769 static const unsigned pwm1_pins[] = { 5 };
 770
 771 static const struct sirfsoc_muxmask pwm2_muxmask[] = {
 772         {
 773                 .group = 0,
 774                 .mask = BIT(6),
 775         },
 776 };
 777
 778 static const struct sirfsoc_padmux pwm2_padmux = {
 779         .muxmask_counts = ARRAY_SIZE(pwm2_muxmask),
 780         .muxmask = pwm2_muxmask,
 781 };
 782
 783 static const unsigned pwm2_pins[] = { 6 };
 784
 785 static const struct sirfsoc_muxmask pwm3_muxmask[] = {
 786         {
 787                 .group = 0,
 788                 .mask = BIT(7),
 789         },
 790 };
 791
 792 static const struct sirfsoc_padmux pwm3_padmux = {
 793         .muxmask_counts = ARRAY_SIZE(pwm3_muxmask),
 794         .muxmask = pwm3_muxmask,
 795 };
 796
 797 static const unsigned pwm3_pins[] = { 7 };
 798
 799 static const struct sirfsoc_muxmask warm_rst_muxmask[] = {
 800         {
 801                 .group = 0,
 802                 .mask = BIT(8),
 803         },
 804 };
 805
 806 static const struct sirfsoc_padmux warm_rst_padmux = {
 807         .muxmask_counts = ARRAY_SIZE(warm_rst_muxmask),
 808         .muxmask = warm_rst_muxmask,
 809 };
 810
 811 static const unsigned warm_rst_pins[] = { 8 };
 812
 813 static const struct sirfsoc_muxmask usb0_utmi_drvbus_muxmask[] = {
 814         {
 815                 .group = 1,
 816                 .mask = BIT(22),
 817         },
 818 };
 819 static const struct sirfsoc_padmux usb0_utmi_drvbus_padmux = {
 820         .muxmask_counts = ARRAY_SIZE(usb0_utmi_drvbus_muxmask),
 821         .muxmask = usb0_utmi_drvbus_muxmask,
 822         .ctrlreg = SIRFSOC_RSC_PIN_MUX,
 823         .funcmask = BIT(6),
 824         .funcval = BIT(6), /* refer to PAD_UTMI_DRVVBUS0_ENABLE */
 825 };
 826
 827 static const unsigned usb0_utmi_drvbus_pins[] = { 54 };
 828
 829 static const struct sirfsoc_muxmask usb1_utmi_drvbus_muxmask[] = {
 830         {
 831                 .group = 1,
 832                 .mask = BIT(27),
 833         },
 834 };
 835
 836 static const struct sirfsoc_padmux usb1_utmi_drvbus_padmux = {
 837         .muxmask_counts = ARRAY_SIZE(usb1_utmi_drvbus_muxmask),
 838         .muxmask = usb1_utmi_drvbus_muxmask,
 839         .ctrlreg = SIRFSOC_RSC_PIN_MUX,
 840         .funcmask = BIT(11),
 841         .funcval = BIT(11), /* refer to PAD_UTMI_DRVVBUS1_ENABLE */
 842 };
 843
 844 static const unsigned usb1_utmi_drvbus_pins[] = { 59 };
 845
 846 static const struct sirfsoc_padmux usb1_dp_dn_padmux = {
 847         .muxmask_counts = 0,
 848         .ctrlreg = SIRFSOC_RSC_USB_UART_SHARE,
 849         .funcmask = BIT(2),
 850         .funcval = BIT(2),
 851 };
 852
 853 static const unsigned usb1_dp_dn_pins[] = { 115, 116 };
 854
 855 static const struct sirfsoc_padmux uart1_route_io_usb1_padmux = {
 856         .muxmask_counts = 0,
 857         .ctrlreg = SIRFSOC_RSC_USB_UART_SHARE,
 858         .funcmask = BIT(2),
 859         .funcval = 0,
 860 };
 861
 862 static const unsigned uart1_route_io_usb1_pins[] = { 115, 116 };
 863
 864 static const struct sirfsoc_muxmask pulse_count_muxmask[] = {
 865         {
 866                 .group = 0,
 867                 .mask = BIT(9) | BIT(10) | BIT(11),
 868         },
 869 };
 870
 871 static const struct sirfsoc_padmux pulse_count_padmux = {
 872         .muxmask_counts = ARRAY_SIZE(pulse_count_muxmask),
 873         .muxmask = pulse_count_muxmask,
 874 };
 875
 876 static const unsigned pulse_count_pins[] = { 9, 10, 11 };
 877
 878 static const struct sirfsoc_pin_group sirfsoc_pin_groups[] = {
 879         SIRFSOC_PIN_GROUP("lcd_16bitsgrp", lcd_16bits_pins),
 880         SIRFSOC_PIN_GROUP("lcd_18bitsgrp", lcd_18bits_pins),
 881         SIRFSOC_PIN_GROUP("lcd_24bitsgrp", lcd_24bits_pins),
 882         SIRFSOC_PIN_GROUP("lcdrom_grp", lcdrom_pins),
 883         SIRFSOC_PIN_GROUP("uart0grp", uart0_pins),
 884         SIRFSOC_PIN_GROUP("uart0_nostreamctrlgrp", uart0_nostreamctrl_pins),
 885         SIRFSOC_PIN_GROUP("uart1grp", uart1_pins),
 886         SIRFSOC_PIN_GROUP("uart2grp", uart2_pins),
 887         SIRFSOC_PIN_GROUP("uart2_nostreamctrlgrp", uart2_nostreamctrl_pins),
 888         SIRFSOC_PIN_GROUP("usp0grp", usp0_pins),
 889         SIRFSOC_PIN_GROUP("usp0_uart_nostreamctrl_grp",
 890                                         usp0_uart_nostreamctrl_pins),
 891         SIRFSOC_PIN_GROUP("usp0_only_utfs_grp", usp0_only_utfs_pins),
 892         SIRFSOC_PIN_GROUP("usp0_only_urfs_grp", usp0_only_urfs_pins),
 893         SIRFSOC_PIN_GROUP("usp1grp", usp1_pins),
 894         SIRFSOC_PIN_GROUP("usp1_uart_nostreamctrl_grp",
 895                                         usp1_uart_nostreamctrl_pins),
 896         SIRFSOC_PIN_GROUP("usp2grp", usp2_pins),
 897         SIRFSOC_PIN_GROUP("usp2_uart_nostreamctrl_grp",
 898                                         usp2_uart_nostreamctrl_pins),
 899         SIRFSOC_PIN_GROUP("i2c0grp", i2c0_pins),
 900         SIRFSOC_PIN_GROUP("i2c1grp", i2c1_pins),
 901         SIRFSOC_PIN_GROUP("pwm0grp", pwm0_pins),
 902         SIRFSOC_PIN_GROUP("pwm1grp", pwm1_pins),
 903         SIRFSOC_PIN_GROUP("pwm2grp", pwm2_pins),
 904         SIRFSOC_PIN_GROUP("pwm3grp", pwm3_pins),
 905         SIRFSOC_PIN_GROUP("vipgrp", vip_pins),
 906         SIRFSOC_PIN_GROUP("vipromgrp", viprom_pins),
 907         SIRFSOC_PIN_GROUP("warm_rstgrp", warm_rst_pins),
 908         SIRFSOC_PIN_GROUP("cko0grp", cko0_pins),
 909         SIRFSOC_PIN_GROUP("cko1grp", cko1_pins),
 910         SIRFSOC_PIN_GROUP("sdmmc0grp", sdmmc0_pins),
 911         SIRFSOC_PIN_GROUP("sdmmc1grp", sdmmc1_pins),
 912         SIRFSOC_PIN_GROUP("sdmmc2grp", sdmmc2_pins),
 913         SIRFSOC_PIN_GROUP("sdmmc3grp", sdmmc3_pins),
 914         SIRFSOC_PIN_GROUP("sdmmc4grp", sdmmc4_pins),
 915         SIRFSOC_PIN_GROUP("sdmmc5grp", sdmmc5_pins),
 916         SIRFSOC_PIN_GROUP("usb0_utmi_drvbusgrp", usb0_utmi_drvbus_pins),
 917         SIRFSOC_PIN_GROUP("usb1_utmi_drvbusgrp", usb1_utmi_drvbus_pins),
 918         SIRFSOC_PIN_GROUP("usb1_dp_dngrp", usb1_dp_dn_pins),
 919         SIRFSOC_PIN_GROUP("uart1_route_io_usb1grp", uart1_route_io_usb1_pins),
 920         SIRFSOC_PIN_GROUP("pulse_countgrp", pulse_count_pins),
 921         SIRFSOC_PIN_GROUP("i2sgrp", i2s_pins),
 922         SIRFSOC_PIN_GROUP("ac97grp", ac97_pins),
 923         SIRFSOC_PIN_GROUP("nandgrp", nand_pins),
 924         SIRFSOC_PIN_GROUP("spi0grp", spi0_pins),
 925         SIRFSOC_PIN_GROUP("spi1grp", spi1_pins),
 926         SIRFSOC_PIN_GROUP("gpsgrp", gps_pins),
 927 };
 928
 929 static const char * const lcd_16bitsgrp[] = { "lcd_16bitsgrp" };
 930 static const char * const lcd_18bitsgrp[] = { "lcd_18bitsgrp" };
 931 static const char * const lcd_24bitsgrp[] = { "lcd_24bitsgrp" };
 932 static const char * const lcdromgrp[] = { "lcdromgrp" };
 933 static const char * const uart0grp[] = { "uart0grp" };
 934 static const char * const uart0_nostreamctrlgrp[] = { "uart0_nostreamctrlgrp" };
 935 static const char * const uart1grp[] = { "uart1grp" };
 936 static const char * const uart2grp[] = { "uart2grp" };
 937 static const char * const uart2_nostreamctrlgrp[] = { "uart2_nostreamctrlgrp" };
 938 static const char * const usp0grp[] = { "usp0grp" };
 939 static const char * const usp0_uart_nostreamctrl_grp[] =
 940                                         { "usp0_uart_nostreamctrl_grp" };
 941 static const char * const usp0_only_utfs_grp[] = { "usp0_only_utfs_grp" };
 942 static const char * const usp0_only_urfs_grp[] = { "usp0_only_urfs_grp" };
 943 static const char * const usp1grp[] = { "usp1grp" };
 944 static const char * const usp1_uart_nostreamctrl_grp[] =
 945                                         { "usp1_uart_nostreamctrl_grp" };
 946 static const char * const usp2grp[] = { "usp2grp" };
 947 static const char * const usp2_uart_nostreamctrl_grp[] =
 948                                         { "usp2_uart_nostreamctrl_grp" };
 949 static const char * const i2c0grp[] = { "i2c0grp" };
 950 static const char * const i2c1grp[] = { "i2c1grp" };
 951 static const char * const pwm0grp[] = { "pwm0grp" };
 952 static const char * const pwm1grp[] = { "pwm1grp" };
 953 static const char * const pwm2grp[] = { "pwm2grp" };
 954 static const char * const pwm3grp[] = { "pwm3grp" };
 955 static const char * const vipgrp[] = { "vipgrp" };
 956 static const char * const vipromgrp[] = { "vipromgrp" };
 957 static const char * const warm_rstgrp[] = { "warm_rstgrp" };
 958 static const char * const cko0grp[] = { "cko0grp" };
 959 static const char * const cko1grp[] = { "cko1grp" };
 960 static const char * const sdmmc0grp[] = { "sdmmc0grp" };
 961 static const char * const sdmmc1grp[] = { "sdmmc1grp" };
 962 static const char * const sdmmc2grp[] = { "sdmmc2grp" };
 963 static const char * const sdmmc3grp[] = { "sdmmc3grp" };
 964 static const char * const sdmmc4grp[] = { "sdmmc4grp" };
 965 static const char * const sdmmc5grp[] = { "sdmmc5grp" };
 966 static const char * const usb0_utmi_drvbusgrp[] = { "usb0_utmi_drvbusgrp" };
 967 static const char * const usb1_utmi_drvbusgrp[] = { "usb1_utmi_drvbusgrp" };
 968 static const char * const usb1_dp_dngrp[] = { "usb1_dp_dngrp" };
 969 static const char * const uart1_route_io_usb1grp[] = { "uart1_route_io_usb1grp" };
 970 static const char * const pulse_countgrp[] = { "pulse_countgrp" };
 971 static const char * const i2sgrp[] = { "i2sgrp" };
 972 static const char * const ac97grp[] = { "ac97grp" };
 973 static const char * const nandgrp[] = { "nandgrp" };
 974 static const char * const spi0grp[] = { "spi0grp" };
 975 static const char * const spi1grp[] = { "spi1grp" };
 976 static const char * const gpsgrp[] = { "gpsgrp" };
 977
 978 static const struct sirfsoc_pmx_func sirfsoc_pmx_functions[] = {
 979         SIRFSOC_PMX_FUNCTION("lcd_16bits", lcd_16bitsgrp, lcd_16bits_padmux),
 980         SIRFSOC_PMX_FUNCTION("lcd_18bits", lcd_18bitsgrp, lcd_18bits_padmux),
 981         SIRFSOC_PMX_FUNCTION("lcd_24bits", lcd_24bitsgrp, lcd_24bits_padmux),
 982         SIRFSOC_PMX_FUNCTION("lcdrom", lcdromgrp, lcdrom_padmux),
 983         SIRFSOC_PMX_FUNCTION("uart0", uart0grp, uart0_padmux),
 984         SIRFSOC_PMX_FUNCTION("uart0_nostreamctrl", uart0_nostreamctrlgrp, uart0_nostreamctrl_padmux),
 985         SIRFSOC_PMX_FUNCTION("uart1", uart1grp, uart1_padmux),
 986         SIRFSOC_PMX_FUNCTION("uart2", uart2grp, uart2_padmux),
 987         SIRFSOC_PMX_FUNCTION("uart2_nostreamctrl", uart2_nostreamctrlgrp, uart2_nostreamctrl_padmux),
 988         SIRFSOC_PMX_FUNCTION("usp0", usp0grp, usp0_padmux),
 989         SIRFSOC_PMX_FUNCTION("usp0_uart_nostreamctrl",
 990                 usp0_uart_nostreamctrl_grp, usp0_uart_nostreamctrl_padmux),
 991         SIRFSOC_PMX_FUNCTION("usp0_only_utfs", usp0_only_utfs_grp, usp0_only_utfs_padmux),
 992         SIRFSOC_PMX_FUNCTION("usp0_only_urfs", usp0_only_urfs_grp, usp0_only_urfs_padmux),
 993         SIRFSOC_PMX_FUNCTION("usp1", usp1grp, usp1_padmux),
 994         SIRFSOC_PMX_FUNCTION("usp1_uart_nostreamctrl",
 995                 usp1_uart_nostreamctrl_grp, usp1_uart_nostreamctrl_padmux),
 996         SIRFSOC_PMX_FUNCTION("usp2", usp2grp, usp2_padmux),
 997         SIRFSOC_PMX_FUNCTION("usp2_uart_nostreamctrl",
 998                 usp2_uart_nostreamctrl_grp, usp2_uart_nostreamctrl_padmux),
 999         SIRFSOC_PMX_FUNCTION("i2c0", i2c0grp, i2c0_padmux),
1000         SIRFSOC_PMX_FUNCTION("i2c1", i2c1grp, i2c1_padmux),
1001         SIRFSOC_PMX_FUNCTION("pwm0", pwm0grp, pwm0_padmux),
1002         SIRFSOC_PMX_FUNCTION("pwm1", pwm1grp, pwm1_padmux),
1003         SIRFSOC_PMX_FUNCTION("pwm2", pwm2grp, pwm2_padmux),
1004         SIRFSOC_PMX_FUNCTION("pwm3", pwm3grp, pwm3_padmux),
1005         SIRFSOC_PMX_FUNCTION("vip", vipgrp, vip_padmux),
1006         SIRFSOC_PMX_FUNCTION("viprom", vipromgrp, viprom_padmux),
1007         SIRFSOC_PMX_FUNCTION("warm_rst", warm_rstgrp, warm_rst_padmux),
1008         SIRFSOC_PMX_FUNCTION("cko0", cko0grp, cko0_padmux),
1009         SIRFSOC_PMX_FUNCTION("cko1", cko1grp, cko1_padmux),
1010         SIRFSOC_PMX_FUNCTION("sdmmc0", sdmmc0grp, sdmmc0_padmux),
1011         SIRFSOC_PMX_FUNCTION("sdmmc1", sdmmc1grp, sdmmc1_padmux),
1012         SIRFSOC_PMX_FUNCTION("sdmmc2", sdmmc2grp, sdmmc2_padmux),
1013         SIRFSOC_PMX_FUNCTION("sdmmc3", sdmmc3grp, sdmmc3_padmux),
1014         SIRFSOC_PMX_FUNCTION("sdmmc4", sdmmc4grp, sdmmc4_padmux),
1015         SIRFSOC_PMX_FUNCTION("sdmmc5", sdmmc5grp, sdmmc5_padmux),
1016         SIRFSOC_PMX_FUNCTION("usb0_utmi_drvbus", usb0_utmi_drvbusgrp, usb0_utmi_drvbus_padmux),
1017         SIRFSOC_PMX_FUNCTION("usb1_utmi_drvbus", usb1_utmi_drvbusgrp, usb1_utmi_drvbus_padmux),
1018         SIRFSOC_PMX_FUNCTION("usb1_dp_dn", usb1_dp_dngrp, usb1_dp_dn_padmux),
1019         SIRFSOC_PMX_FUNCTION("uart1_route_io_usb1", uart1_route_io_usb1grp, uart1_route_io_usb1_padmux),
1020         SIRFSOC_PMX_FUNCTION("pulse_count", pulse_countgrp, pulse_count_padmux),
1021         SIRFSOC_PMX_FUNCTION("i2s", i2sgrp, i2s_padmux),
1022         SIRFSOC_PMX_FUNCTION("ac97", ac97grp, ac97_padmux),
1023         SIRFSOC_PMX_FUNCTION("nand", nandgrp, nand_padmux),
1024         SIRFSOC_PMX_FUNCTION("spi0", spi0grp, spi0_padmux),
1025         SIRFSOC_PMX_FUNCTION("spi1", spi1grp, spi1_padmux),
1026         SIRFSOC_PMX_FUNCTION("gps", gpsgrp, gps_padmux),
1027 };
1028
1029 struct sirfsoc_pinctrl_data prima2_pinctrl_data = {
1030         (struct pinctrl_pin_desc *)sirfsoc_pads,
1031         ARRAY_SIZE(sirfsoc_pads),
1032         (struct sirfsoc_pin_group *)sirfsoc_pin_groups,
1033         ARRAY_SIZE(sirfsoc_pin_groups),
1034         (struct sirfsoc_pmx_func *)sirfsoc_pmx_functions,
1035         ARRAY_SIZE(sirfsoc_pmx_functions),
1036 };
1037