2 * pinmux driver for CSR SiRFprimaII
4 * Copyright (c) 2011 - 2014 Cambridge Silicon Radio Limited, a CSR plc group
7 * Licensed under GPLv2 or later.
10 #include <linux/init.h>
11 #include <linux/module.h>
12 #include <linux/irq.h>
13 #include <linux/platform_device.h>
15 #include <linux/slab.h>
16 #include <linux/err.h>
17 #include <linux/pinctrl/pinctrl.h>
18 #include <linux/pinctrl/pinmux.h>
19 #include <linux/pinctrl/consumer.h>
20 #include <linux/pinctrl/machine.h>
22 #include <linux/of_address.h>
23 #include <linux/of_device.h>
24 #include <linux/of_platform.h>
25 #include <linux/bitops.h>
26 #include <linux/gpio.h>
27 #include <linux/of_gpio.h>
29 #include "pinctrl-sirf.h"
31 #define DRIVER_NAME "pinmux-sirf"
33 struct sirfsoc_gpio_bank {
39 struct sirfsoc_gpio_chip {
40 struct of_mm_gpio_chip chip;
41 bool is_marco; /* for marco, some registers are different with prima2 */
42 struct sirfsoc_gpio_bank sgpio_bank[SIRFSOC_GPIO_NO_OF_BANKS];
45 static struct sirfsoc_gpio_chip sgpio_chip;
46 static DEFINE_SPINLOCK(sgpio_lock);
48 static struct sirfsoc_pin_group *sirfsoc_pin_groups;
49 static int sirfsoc_pingrp_cnt;
51 static int sirfsoc_get_groups_count(struct pinctrl_dev *pctldev)
53 return sirfsoc_pingrp_cnt;
56 static const char *sirfsoc_get_group_name(struct pinctrl_dev *pctldev,
59 return sirfsoc_pin_groups[selector].name;
62 static int sirfsoc_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector,
63 const unsigned **pins,
66 *pins = sirfsoc_pin_groups[selector].pins;
67 *num_pins = sirfsoc_pin_groups[selector].num_pins;
71 static void sirfsoc_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
74 seq_printf(s, " " DRIVER_NAME);
77 static int sirfsoc_dt_node_to_map(struct pinctrl_dev *pctldev,
78 struct device_node *np_config,
79 struct pinctrl_map **map, unsigned *num_maps)
81 struct sirfsoc_pmx *spmx = pinctrl_dev_get_drvdata(pctldev);
82 struct device_node *np;
83 struct property *prop;
84 const char *function, *group;
85 int ret, index = 0, count = 0;
87 /* calculate number of maps required */
88 for_each_child_of_node(np_config, np) {
89 ret = of_property_read_string(np, "sirf,function", &function);
93 ret = of_property_count_strings(np, "sirf,pins");
101 dev_err(spmx->dev, "No child nodes passed via DT\n");
105 *map = kzalloc(sizeof(**map) * count, GFP_KERNEL);
109 for_each_child_of_node(np_config, np) {
110 of_property_read_string(np, "sirf,function", &function);
111 of_property_for_each_string(np, "sirf,pins", prop, group) {
112 (*map)[index].type = PIN_MAP_TYPE_MUX_GROUP;
113 (*map)[index].data.mux.group = group;
114 (*map)[index].data.mux.function = function;
124 static void sirfsoc_dt_free_map(struct pinctrl_dev *pctldev,
125 struct pinctrl_map *map, unsigned num_maps)
130 static struct pinctrl_ops sirfsoc_pctrl_ops = {
131 .get_groups_count = sirfsoc_get_groups_count,
132 .get_group_name = sirfsoc_get_group_name,
133 .get_group_pins = sirfsoc_get_group_pins,
134 .pin_dbg_show = sirfsoc_pin_dbg_show,
135 .dt_node_to_map = sirfsoc_dt_node_to_map,
136 .dt_free_map = sirfsoc_dt_free_map,
139 static struct sirfsoc_pmx_func *sirfsoc_pmx_functions;
140 static int sirfsoc_pmxfunc_cnt;
142 static void sirfsoc_pinmux_endisable(struct sirfsoc_pmx *spmx, unsigned selector,
146 const struct sirfsoc_padmux *mux = sirfsoc_pmx_functions[selector].padmux;
147 const struct sirfsoc_muxmask *mask = mux->muxmask;
149 for (i = 0; i < mux->muxmask_counts; i++) {
151 if (!spmx->is_marco) {
152 muxval = readl(spmx->gpio_virtbase + SIRFSOC_GPIO_PAD_EN(mask[i].group));
154 muxval = muxval & ~mask[i].mask;
156 muxval = muxval | mask[i].mask;
157 writel(muxval, spmx->gpio_virtbase + SIRFSOC_GPIO_PAD_EN(mask[i].group));
160 writel(mask[i].mask, spmx->gpio_virtbase +
161 SIRFSOC_GPIO_PAD_EN_CLR(mask[i].group));
163 writel(mask[i].mask, spmx->gpio_virtbase +
164 SIRFSOC_GPIO_PAD_EN(mask[i].group));
168 if (mux->funcmask && enable) {
172 readl(spmx->rsc_virtbase + mux->ctrlreg);
174 (func_en_val & ~mux->funcmask) | (mux->funcval);
175 writel(func_en_val, spmx->rsc_virtbase + mux->ctrlreg);
179 static int sirfsoc_pinmux_enable(struct pinctrl_dev *pmxdev, unsigned selector,
182 struct sirfsoc_pmx *spmx;
184 spmx = pinctrl_dev_get_drvdata(pmxdev);
185 sirfsoc_pinmux_endisable(spmx, selector, true);
190 static void sirfsoc_pinmux_disable(struct pinctrl_dev *pmxdev, unsigned selector,
193 struct sirfsoc_pmx *spmx;
195 spmx = pinctrl_dev_get_drvdata(pmxdev);
196 sirfsoc_pinmux_endisable(spmx, selector, false);
199 static int sirfsoc_pinmux_get_funcs_count(struct pinctrl_dev *pmxdev)
201 return sirfsoc_pmxfunc_cnt;
204 static const char *sirfsoc_pinmux_get_func_name(struct pinctrl_dev *pctldev,
207 return sirfsoc_pmx_functions[selector].name;
210 static int sirfsoc_pinmux_get_groups(struct pinctrl_dev *pctldev, unsigned selector,
211 const char * const **groups,
212 unsigned * const num_groups)
214 *groups = sirfsoc_pmx_functions[selector].groups;
215 *num_groups = sirfsoc_pmx_functions[selector].num_groups;
219 static int sirfsoc_pinmux_request_gpio(struct pinctrl_dev *pmxdev,
220 struct pinctrl_gpio_range *range, unsigned offset)
222 struct sirfsoc_pmx *spmx;
224 int group = range->id;
228 spmx = pinctrl_dev_get_drvdata(pmxdev);
230 if (!spmx->is_marco) {
231 muxval = readl(spmx->gpio_virtbase + SIRFSOC_GPIO_PAD_EN(group));
232 muxval = muxval | (1 << (offset - range->pin_base));
233 writel(muxval, spmx->gpio_virtbase + SIRFSOC_GPIO_PAD_EN(group));
235 writel(1 << (offset - range->pin_base), spmx->gpio_virtbase +
236 SIRFSOC_GPIO_PAD_EN(group));
242 static struct pinmux_ops sirfsoc_pinmux_ops = {
243 .enable = sirfsoc_pinmux_enable,
244 .disable = sirfsoc_pinmux_disable,
245 .get_functions_count = sirfsoc_pinmux_get_funcs_count,
246 .get_function_name = sirfsoc_pinmux_get_func_name,
247 .get_function_groups = sirfsoc_pinmux_get_groups,
248 .gpio_request_enable = sirfsoc_pinmux_request_gpio,
251 static struct pinctrl_desc sirfsoc_pinmux_desc = {
253 .pctlops = &sirfsoc_pctrl_ops,
254 .pmxops = &sirfsoc_pinmux_ops,
255 .owner = THIS_MODULE,
259 * Todo: bind irq_chip to every pinctrl_gpio_range
261 static struct pinctrl_gpio_range sirfsoc_gpio_ranges = {
262 .name = "sirfsoc-gpio*",
266 .npins = SIRFSOC_GPIO_BANK_SIZE * SIRFSOC_GPIO_NO_OF_BANKS,
269 static void __iomem *sirfsoc_rsc_of_iomap(void)
271 const struct of_device_id rsc_ids[] = {
272 { .compatible = "sirf,prima2-rsc" },
273 { .compatible = "sirf,marco-rsc" },
276 struct device_node *np;
278 np = of_find_matching_node(NULL, rsc_ids);
280 panic("unable to find compatible rsc node in dtb\n");
282 return of_iomap(np, 0);
285 static int sirfsoc_gpio_of_xlate(struct gpio_chip *gc,
286 const struct of_phandle_args *gpiospec,
289 if (gpiospec->args[0] > SIRFSOC_GPIO_NO_OF_BANKS * SIRFSOC_GPIO_BANK_SIZE)
292 if (gc != &sgpio_chip.chip.gc)
296 *flags = gpiospec->args[1];
298 return gpiospec->args[0];
301 static const struct of_device_id pinmux_ids[] = {
302 { .compatible = "sirf,prima2-pinctrl", .data = &prima2_pinctrl_data, },
303 { .compatible = "sirf,atlas6-pinctrl", .data = &atlas6_pinctrl_data, },
304 { .compatible = "sirf,marco-pinctrl", .data = &prima2_pinctrl_data, },
308 static int sirfsoc_pinmux_probe(struct platform_device *pdev)
311 struct sirfsoc_pmx *spmx;
312 struct device_node *np = pdev->dev.of_node;
313 const struct sirfsoc_pinctrl_data *pdata;
315 /* Create state holders etc for this driver */
316 spmx = devm_kzalloc(&pdev->dev, sizeof(*spmx), GFP_KERNEL);
320 spmx->dev = &pdev->dev;
322 platform_set_drvdata(pdev, spmx);
324 spmx->gpio_virtbase = of_iomap(np, 0);
325 if (!spmx->gpio_virtbase) {
326 dev_err(&pdev->dev, "can't map gpio registers\n");
330 spmx->rsc_virtbase = sirfsoc_rsc_of_iomap();
331 if (!spmx->rsc_virtbase) {
333 dev_err(&pdev->dev, "can't map rsc registers\n");
334 goto out_no_rsc_remap;
337 if (of_device_is_compatible(np, "sirf,marco-pinctrl"))
340 pdata = of_match_node(pinmux_ids, np)->data;
341 sirfsoc_pin_groups = pdata->grps;
342 sirfsoc_pingrp_cnt = pdata->grps_cnt;
343 sirfsoc_pmx_functions = pdata->funcs;
344 sirfsoc_pmxfunc_cnt = pdata->funcs_cnt;
345 sirfsoc_pinmux_desc.pins = pdata->pads;
346 sirfsoc_pinmux_desc.npins = pdata->pads_cnt;
349 /* Now register the pin controller and all pins it handles */
350 spmx->pmx = pinctrl_register(&sirfsoc_pinmux_desc, &pdev->dev, spmx);
352 dev_err(&pdev->dev, "could not register SIRFSOC pinmux driver\n");
357 sirfsoc_gpio_ranges.gc = &sgpio_chip.chip.gc;
358 pinctrl_add_gpio_range(spmx->pmx, &sirfsoc_gpio_ranges);
360 dev_info(&pdev->dev, "initialized SIRFSOC pinmux driver\n");
365 iounmap(spmx->rsc_virtbase);
367 iounmap(spmx->gpio_virtbase);
371 #ifdef CONFIG_PM_SLEEP
372 static int sirfsoc_pinmux_suspend_noirq(struct device *dev)
375 struct sirfsoc_pmx *spmx = dev_get_drvdata(dev);
377 for (i = 0; i < SIRFSOC_GPIO_NO_OF_BANKS; i++) {
378 for (j = 0; j < SIRFSOC_GPIO_BANK_SIZE; j++) {
379 spmx->gpio_regs[i][j] = readl(spmx->gpio_virtbase +
380 SIRFSOC_GPIO_CTRL(i, j));
382 spmx->ints_regs[i] = readl(spmx->gpio_virtbase +
383 SIRFSOC_GPIO_INT_STATUS(i));
384 spmx->paden_regs[i] = readl(spmx->gpio_virtbase +
385 SIRFSOC_GPIO_PAD_EN(i));
387 spmx->dspen_regs = readl(spmx->gpio_virtbase + SIRFSOC_GPIO_DSP_EN0);
389 for (i = 0; i < 3; i++)
390 spmx->rsc_regs[i] = readl(spmx->rsc_virtbase + 4 * i);
395 static int sirfsoc_pinmux_resume_noirq(struct device *dev)
398 struct sirfsoc_pmx *spmx = dev_get_drvdata(dev);
400 for (i = 0; i < SIRFSOC_GPIO_NO_OF_BANKS; i++) {
401 for (j = 0; j < SIRFSOC_GPIO_BANK_SIZE; j++) {
402 writel(spmx->gpio_regs[i][j], spmx->gpio_virtbase +
403 SIRFSOC_GPIO_CTRL(i, j));
405 writel(spmx->ints_regs[i], spmx->gpio_virtbase +
406 SIRFSOC_GPIO_INT_STATUS(i));
407 writel(spmx->paden_regs[i], spmx->gpio_virtbase +
408 SIRFSOC_GPIO_PAD_EN(i));
410 writel(spmx->dspen_regs, spmx->gpio_virtbase + SIRFSOC_GPIO_DSP_EN0);
412 for (i = 0; i < 3; i++)
413 writel(spmx->rsc_regs[i], spmx->rsc_virtbase + 4 * i);
418 static const struct dev_pm_ops sirfsoc_pinmux_pm_ops = {
419 .suspend_noirq = sirfsoc_pinmux_suspend_noirq,
420 .resume_noirq = sirfsoc_pinmux_resume_noirq,
421 .freeze_noirq = sirfsoc_pinmux_suspend_noirq,
422 .restore_noirq = sirfsoc_pinmux_resume_noirq,
426 static struct platform_driver sirfsoc_pinmux_driver = {
429 .owner = THIS_MODULE,
430 .of_match_table = pinmux_ids,
431 #ifdef CONFIG_PM_SLEEP
432 .pm = &sirfsoc_pinmux_pm_ops,
435 .probe = sirfsoc_pinmux_probe,
438 static int __init sirfsoc_pinmux_init(void)
440 return platform_driver_register(&sirfsoc_pinmux_driver);
442 arch_initcall(sirfsoc_pinmux_init);
444 static inline struct sirfsoc_gpio_bank *sirfsoc_gpio_to_bank(unsigned int gpio)
446 return &sgpio_chip.sgpio_bank[gpio / SIRFSOC_GPIO_BANK_SIZE];
449 static inline int sirfsoc_gpio_to_bankoff(unsigned int gpio)
451 return gpio % SIRFSOC_GPIO_BANK_SIZE;
454 static void sirfsoc_gpio_irq_ack(struct irq_data *d)
456 struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(d->hwirq);
457 int idx = d->hwirq % SIRFSOC_GPIO_BANK_SIZE;
461 offset = SIRFSOC_GPIO_CTRL(bank->id, idx);
463 spin_lock_irqsave(&sgpio_lock, flags);
465 val = readl(sgpio_chip.chip.regs + offset);
467 writel(val, sgpio_chip.chip.regs + offset);
469 spin_unlock_irqrestore(&sgpio_lock, flags);
472 static void __sirfsoc_gpio_irq_mask(struct sirfsoc_gpio_bank *bank, int idx)
477 offset = SIRFSOC_GPIO_CTRL(bank->id, idx);
479 spin_lock_irqsave(&sgpio_lock, flags);
481 val = readl(sgpio_chip.chip.regs + offset);
482 val &= ~SIRFSOC_GPIO_CTL_INTR_EN_MASK;
483 val &= ~SIRFSOC_GPIO_CTL_INTR_STS_MASK;
484 writel(val, sgpio_chip.chip.regs + offset);
486 spin_unlock_irqrestore(&sgpio_lock, flags);
489 static void sirfsoc_gpio_irq_mask(struct irq_data *d)
491 struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(d->hwirq);
493 __sirfsoc_gpio_irq_mask(bank, d->hwirq % SIRFSOC_GPIO_BANK_SIZE);
496 static void sirfsoc_gpio_irq_unmask(struct irq_data *d)
498 struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(d->hwirq);
499 int idx = d->hwirq % SIRFSOC_GPIO_BANK_SIZE;
503 offset = SIRFSOC_GPIO_CTRL(bank->id, idx);
505 spin_lock_irqsave(&sgpio_lock, flags);
507 val = readl(sgpio_chip.chip.regs + offset);
508 val &= ~SIRFSOC_GPIO_CTL_INTR_STS_MASK;
509 val |= SIRFSOC_GPIO_CTL_INTR_EN_MASK;
510 writel(val, sgpio_chip.chip.regs + offset);
512 spin_unlock_irqrestore(&sgpio_lock, flags);
515 static int sirfsoc_gpio_irq_type(struct irq_data *d, unsigned type)
517 struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(d->hwirq);
518 int idx = d->hwirq % SIRFSOC_GPIO_BANK_SIZE;
522 offset = SIRFSOC_GPIO_CTRL(bank->id, idx);
524 spin_lock_irqsave(&sgpio_lock, flags);
526 val = readl(sgpio_chip.chip.regs + offset);
527 val &= ~(SIRFSOC_GPIO_CTL_INTR_STS_MASK | SIRFSOC_GPIO_CTL_OUT_EN_MASK);
532 case IRQ_TYPE_EDGE_RISING:
533 val |= SIRFSOC_GPIO_CTL_INTR_HIGH_MASK | SIRFSOC_GPIO_CTL_INTR_TYPE_MASK;
534 val &= ~SIRFSOC_GPIO_CTL_INTR_LOW_MASK;
536 case IRQ_TYPE_EDGE_FALLING:
537 val &= ~SIRFSOC_GPIO_CTL_INTR_HIGH_MASK;
538 val |= SIRFSOC_GPIO_CTL_INTR_LOW_MASK | SIRFSOC_GPIO_CTL_INTR_TYPE_MASK;
540 case IRQ_TYPE_EDGE_BOTH:
541 val |= SIRFSOC_GPIO_CTL_INTR_HIGH_MASK | SIRFSOC_GPIO_CTL_INTR_LOW_MASK |
542 SIRFSOC_GPIO_CTL_INTR_TYPE_MASK;
544 case IRQ_TYPE_LEVEL_LOW:
545 val &= ~(SIRFSOC_GPIO_CTL_INTR_HIGH_MASK | SIRFSOC_GPIO_CTL_INTR_TYPE_MASK);
546 val |= SIRFSOC_GPIO_CTL_INTR_LOW_MASK;
548 case IRQ_TYPE_LEVEL_HIGH:
549 val |= SIRFSOC_GPIO_CTL_INTR_HIGH_MASK;
550 val &= ~(SIRFSOC_GPIO_CTL_INTR_LOW_MASK | SIRFSOC_GPIO_CTL_INTR_TYPE_MASK);
554 writel(val, sgpio_chip.chip.regs + offset);
556 spin_unlock_irqrestore(&sgpio_lock, flags);
561 static struct irq_chip sirfsoc_irq_chip = {
562 .name = "sirf-gpio-irq",
563 .irq_ack = sirfsoc_gpio_irq_ack,
564 .irq_mask = sirfsoc_gpio_irq_mask,
565 .irq_unmask = sirfsoc_gpio_irq_unmask,
566 .irq_set_type = sirfsoc_gpio_irq_type,
569 static void sirfsoc_gpio_handle_irq(unsigned int irq, struct irq_desc *desc)
571 struct sirfsoc_gpio_bank *bank;
574 struct irq_chip *chip = irq_get_chip(irq);
577 for (i = 0; i < SIRFSOC_GPIO_NO_OF_BANKS; i++) {
578 bank = &sgpio_chip.sgpio_bank[i];
579 if (bank->parent_irq == irq)
582 BUG_ON(i == SIRFSOC_GPIO_NO_OF_BANKS);
584 chained_irq_enter(chip, desc);
586 status = readl(sgpio_chip.chip.regs + SIRFSOC_GPIO_INT_STATUS(bank->id));
589 "%s: gpio id %d status %#x no interrupt is flaged\n",
590 __func__, bank->id, status);
591 handle_bad_irq(irq, desc);
596 ctrl = readl(sgpio_chip.chip.regs + SIRFSOC_GPIO_CTRL(bank->id, idx));
599 * Here we must check whether the corresponding GPIO's interrupt
600 * has been enabled, otherwise just skip it
602 if ((status & 0x1) && (ctrl & SIRFSOC_GPIO_CTL_INTR_EN_MASK)) {
603 pr_debug("%s: gpio id %d idx %d happens\n",
604 __func__, bank->id, idx);
605 generic_handle_irq(irq_find_mapping(sgpio_chip.chip.gc.irqdomain, idx +
606 bank->id * SIRFSOC_GPIO_BANK_SIZE));
610 status = status >> 1;
613 chained_irq_exit(chip, desc);
616 static inline void sirfsoc_gpio_set_input(struct sirfsoc_gpio_bank *bank, unsigned ctrl_offset)
620 val = readl(sgpio_chip.chip.regs + ctrl_offset);
621 val &= ~SIRFSOC_GPIO_CTL_OUT_EN_MASK;
622 writel(val, sgpio_chip.chip.regs + ctrl_offset);
625 static int sirfsoc_gpio_request(struct gpio_chip *chip, unsigned offset)
627 struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(offset);
630 if (pinctrl_request_gpio(chip->base + offset))
633 spin_lock_irqsave(&bank->lock, flags);
637 * set direction as input and mask irq
639 sirfsoc_gpio_set_input(bank, SIRFSOC_GPIO_CTRL(bank->id, offset));
640 __sirfsoc_gpio_irq_mask(bank, offset);
642 spin_unlock_irqrestore(&bank->lock, flags);
647 static void sirfsoc_gpio_free(struct gpio_chip *chip, unsigned offset)
649 struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(offset);
652 spin_lock_irqsave(&bank->lock, flags);
654 __sirfsoc_gpio_irq_mask(bank, offset);
655 sirfsoc_gpio_set_input(bank, SIRFSOC_GPIO_CTRL(bank->id, offset));
657 spin_unlock_irqrestore(&bank->lock, flags);
659 pinctrl_free_gpio(chip->base + offset);
662 static int sirfsoc_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
664 struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(gpio);
665 int idx = sirfsoc_gpio_to_bankoff(gpio);
669 offset = SIRFSOC_GPIO_CTRL(bank->id, idx);
671 spin_lock_irqsave(&bank->lock, flags);
673 sirfsoc_gpio_set_input(bank, offset);
675 spin_unlock_irqrestore(&bank->lock, flags);
680 static inline void sirfsoc_gpio_set_output(struct sirfsoc_gpio_bank *bank, unsigned offset,
686 spin_lock_irqsave(&bank->lock, flags);
688 out_ctrl = readl(sgpio_chip.chip.regs + offset);
690 out_ctrl |= SIRFSOC_GPIO_CTL_DATAOUT_MASK;
692 out_ctrl &= ~SIRFSOC_GPIO_CTL_DATAOUT_MASK;
694 out_ctrl &= ~SIRFSOC_GPIO_CTL_INTR_EN_MASK;
695 out_ctrl |= SIRFSOC_GPIO_CTL_OUT_EN_MASK;
696 writel(out_ctrl, sgpio_chip.chip.regs + offset);
698 spin_unlock_irqrestore(&bank->lock, flags);
701 static int sirfsoc_gpio_direction_output(struct gpio_chip *chip, unsigned gpio, int value)
703 struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(gpio);
704 int idx = sirfsoc_gpio_to_bankoff(gpio);
708 offset = SIRFSOC_GPIO_CTRL(bank->id, idx);
710 spin_lock_irqsave(&sgpio_lock, flags);
712 sirfsoc_gpio_set_output(bank, offset, value);
714 spin_unlock_irqrestore(&sgpio_lock, flags);
719 static int sirfsoc_gpio_get_value(struct gpio_chip *chip, unsigned offset)
721 struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(offset);
725 spin_lock_irqsave(&bank->lock, flags);
727 val = readl(sgpio_chip.chip.regs + SIRFSOC_GPIO_CTRL(bank->id, offset));
729 spin_unlock_irqrestore(&bank->lock, flags);
731 return !!(val & SIRFSOC_GPIO_CTL_DATAIN_MASK);
734 static void sirfsoc_gpio_set_value(struct gpio_chip *chip, unsigned offset,
737 struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(offset);
741 spin_lock_irqsave(&bank->lock, flags);
743 ctrl = readl(sgpio_chip.chip.regs + SIRFSOC_GPIO_CTRL(bank->id, offset));
745 ctrl |= SIRFSOC_GPIO_CTL_DATAOUT_MASK;
747 ctrl &= ~SIRFSOC_GPIO_CTL_DATAOUT_MASK;
748 writel(ctrl, sgpio_chip.chip.regs + SIRFSOC_GPIO_CTRL(bank->id, offset));
750 spin_unlock_irqrestore(&bank->lock, flags);
753 static void sirfsoc_gpio_set_pullup(const u32 *pullups)
756 const unsigned long *p = (const unsigned long *)pullups;
758 for (i = 0; i < SIRFSOC_GPIO_NO_OF_BANKS; i++) {
759 for_each_set_bit(n, p + i, BITS_PER_LONG) {
760 u32 offset = SIRFSOC_GPIO_CTRL(i, n);
761 u32 val = readl(sgpio_chip.chip.regs + offset);
762 val |= SIRFSOC_GPIO_CTL_PULL_MASK;
763 val |= SIRFSOC_GPIO_CTL_PULL_HIGH;
764 writel(val, sgpio_chip.chip.regs + offset);
769 static void sirfsoc_gpio_set_pulldown(const u32 *pulldowns)
772 const unsigned long *p = (const unsigned long *)pulldowns;
774 for (i = 0; i < SIRFSOC_GPIO_NO_OF_BANKS; i++) {
775 for_each_set_bit(n, p + i, BITS_PER_LONG) {
776 u32 offset = SIRFSOC_GPIO_CTRL(i, n);
777 u32 val = readl(sgpio_chip.chip.regs + offset);
778 val |= SIRFSOC_GPIO_CTL_PULL_MASK;
779 val &= ~SIRFSOC_GPIO_CTL_PULL_HIGH;
780 writel(val, sgpio_chip.chip.regs + offset);
785 static int sirfsoc_gpio_probe(struct device_node *np)
788 struct sirfsoc_gpio_bank *bank;
790 struct platform_device *pdev;
791 bool is_marco = false;
793 u32 pullups[SIRFSOC_GPIO_NO_OF_BANKS], pulldowns[SIRFSOC_GPIO_NO_OF_BANKS];
795 pdev = of_find_device_by_node(np);
799 regs = of_iomap(np, 0);
803 if (of_device_is_compatible(np, "sirf,marco-pinctrl"))
806 sgpio_chip.chip.gc.request = sirfsoc_gpio_request;
807 sgpio_chip.chip.gc.free = sirfsoc_gpio_free;
808 sgpio_chip.chip.gc.direction_input = sirfsoc_gpio_direction_input;
809 sgpio_chip.chip.gc.get = sirfsoc_gpio_get_value;
810 sgpio_chip.chip.gc.direction_output = sirfsoc_gpio_direction_output;
811 sgpio_chip.chip.gc.set = sirfsoc_gpio_set_value;
812 sgpio_chip.chip.gc.base = 0;
813 sgpio_chip.chip.gc.ngpio = SIRFSOC_GPIO_BANK_SIZE * SIRFSOC_GPIO_NO_OF_BANKS;
814 sgpio_chip.chip.gc.label = kstrdup(np->full_name, GFP_KERNEL);
815 sgpio_chip.chip.gc.of_node = np;
816 sgpio_chip.chip.gc.of_xlate = sirfsoc_gpio_of_xlate;
817 sgpio_chip.chip.gc.of_gpio_n_cells = 2;
818 sgpio_chip.chip.gc.dev = &pdev->dev;
819 sgpio_chip.chip.regs = regs;
820 sgpio_chip.is_marco = is_marco;
822 err = gpiochip_add(&sgpio_chip.chip.gc);
824 dev_err(&pdev->dev, "%s: error in probe function with status %d\n",
829 err = gpiochip_irqchip_add(&sgpio_chip.chip.gc,
835 "could not connect irqchip to gpiochip\n");
839 for (i = 0; i < SIRFSOC_GPIO_NO_OF_BANKS; i++) {
840 bank = &sgpio_chip.sgpio_bank[i];
841 spin_lock_init(&bank->lock);
842 bank->parent_irq = platform_get_irq(pdev, i);
843 if (bank->parent_irq < 0) {
844 err = bank->parent_irq;
848 gpiochip_set_chained_irqchip(&sgpio_chip.chip.gc,
851 sirfsoc_gpio_handle_irq);
854 if (!of_property_read_u32_array(np, "sirf,pullups", pullups,
855 SIRFSOC_GPIO_NO_OF_BANKS))
856 sirfsoc_gpio_set_pullup(pullups);
858 if (!of_property_read_u32_array(np, "sirf,pulldowns", pulldowns,
859 SIRFSOC_GPIO_NO_OF_BANKS))
860 sirfsoc_gpio_set_pulldown(pulldowns);
869 static int __init sirfsoc_gpio_init(void)
872 struct device_node *np;
874 np = of_find_matching_node(NULL, pinmux_ids);
879 return sirfsoc_gpio_probe(np);
881 subsys_initcall(sirfsoc_gpio_init);
883 MODULE_AUTHOR("Rongjun Ying <rongjun.ying@csr.com>, "
884 "Yuping Luo <yuping.luo@csr.com>, "
885 "Barry Song <baohua.song@csr.com>");
886 MODULE_DESCRIPTION("SIRFSOC pin control driver");
887 MODULE_LICENSE("GPL");