drivers/pinctrl/sunxi/pinctrl-sunxi.c

   1 /*
   2  * Allwinner A1X SoCs pinctrl driver.
   3  *
   4  * Copyright (C) 2012 Maxime Ripard
   5  *
   6  * Maxime Ripard <maxime.ripard@free-electrons.com>
   7  *
   8  * This file is licensed under the terms of the GNU General Public
   9  * License version 2.  This program is licensed "as is" without any
  10  * warranty of any kind, whether express or implied.
  11  */
  12
  13 #include <linux/io.h>
  14 #include <linux/clk.h>
  15 #include <linux/gpio/driver.h>
  16 #include <linux/irqdomain.h>
  17 #include <linux/irqchip/chained_irq.h>
  18 #include <linux/export.h>
  19 #include <linux/of.h>
  20 #include <linux/of_address.h>
  21 #include <linux/of_device.h>
  22 #include <linux/of_irq.h>
  23 #include <linux/pinctrl/consumer.h>
  24 #include <linux/pinctrl/machine.h>
  25 #include <linux/pinctrl/pinctrl.h>
  26 #include <linux/pinctrl/pinconf-generic.h>
  27 #include <linux/pinctrl/pinmux.h>
  28 #include <linux/platform_device.h>
  29 #include <linux/slab.h>
  30
  31 #include "../core.h"
  32 #include "pinctrl-sunxi.h"
  33
  34 static struct irq_chip sunxi_pinctrl_edge_irq_chip;
  35 static struct irq_chip sunxi_pinctrl_level_irq_chip;
  36
  37 static struct sunxi_pinctrl_group *
  38 sunxi_pinctrl_find_group_by_name(struct sunxi_pinctrl *pctl, const char *group)
  39 {
  40         int i;
  41
  42         for (i = 0; i < pctl->ngroups; i++) {
  43                 struct sunxi_pinctrl_group *grp = pctl->groups + i;
  44
  45                 if (!strcmp(grp->name, group))
  46                         return grp;
  47         }
  48
  49         return NULL;
  50 }
  51
  52 static struct sunxi_pinctrl_function *
  53 sunxi_pinctrl_find_function_by_name(struct sunxi_pinctrl *pctl,
  54                                     const char *name)
  55 {
  56         struct sunxi_pinctrl_function *func = pctl->functions;
  57         int i;
  58
  59         for (i = 0; i < pctl->nfunctions; i++) {
  60                 if (!func[i].name)
  61                         break;
  62
  63                 if (!strcmp(func[i].name, name))
  64                         return func + i;
  65         }
  66
  67         return NULL;
  68 }
  69
  70 static struct sunxi_desc_function *
  71 sunxi_pinctrl_desc_find_function_by_name(struct sunxi_pinctrl *pctl,
  72                                          const char *pin_name,
  73                                          const char *func_name)
  74 {
  75         int i;
  76
  77         for (i = 0; i < pctl->desc->npins; i++) {
  78                 const struct sunxi_desc_pin *pin = pctl->desc->pins + i;
  79
  80                 if (!strcmp(pin->pin.name, pin_name)) {
  81                         struct sunxi_desc_function *func = pin->functions;
  82
  83                         while (func->name) {
  84                                 if (!strcmp(func->name, func_name))
  85                                         return func;
  86
  87                                 func++;
  88                         }
  89                 }
  90         }
  91
  92         return NULL;
  93 }
  94
  95 static struct sunxi_desc_function *
  96 sunxi_pinctrl_desc_find_function_by_pin(struct sunxi_pinctrl *pctl,
  97                                         const u16 pin_num,
  98                                         const char *func_name)
  99 {
 100         int i;
 101
 102         for (i = 0; i < pctl->desc->npins; i++) {
 103                 const struct sunxi_desc_pin *pin = pctl->desc->pins + i;
 104
 105                 if (pin->pin.number == pin_num) {
 106                         struct sunxi_desc_function *func = pin->functions;
 107
 108                         while (func->name) {
 109                                 if (!strcmp(func->name, func_name))
 110                                         return func;
 111
 112                                 func++;
 113                         }
 114                 }
 115         }
 116
 117         return NULL;
 118 }
 119
 120 static int sunxi_pctrl_get_groups_count(struct pinctrl_dev *pctldev)
 121 {
 122         struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
 123
 124         return pctl->ngroups;
 125 }
 126
 127 static const char *sunxi_pctrl_get_group_name(struct pinctrl_dev *pctldev,
 128                                               unsigned group)
 129 {
 130         struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
 131
 132         return pctl->groups[group].name;
 133 }
 134
 135 static int sunxi_pctrl_get_group_pins(struct pinctrl_dev *pctldev,
 136                                       unsigned group,
 137                                       const unsigned **pins,
 138                                       unsigned *num_pins)
 139 {
 140         struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
 141
 142         *pins = (unsigned *)&pctl->groups[group].pin;
 143         *num_pins = 1;
 144
 145         return 0;
 146 }
 147
 148 static int sunxi_pctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
 149                                       struct device_node *node,
 150                                       struct pinctrl_map **map,
 151                                       unsigned *num_maps)
 152 {
 153         struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
 154         unsigned long *pinconfig;
 155         struct property *prop;
 156         const char *function;
 157         const char *group;
 158         int ret, nmaps, i = 0;
 159         u32 val;
 160
 161         *map = NULL;
 162         *num_maps = 0;
 163
 164         ret = of_property_read_string(node, "allwinner,function", &function);
 165         if (ret) {
 166                 dev_err(pctl->dev,
 167                         "missing allwinner,function property in node %s\n",
 168                         node->name);
 169                 return -EINVAL;
 170         }
 171
 172         nmaps = of_property_count_strings(node, "allwinner,pins") * 2;
 173         if (nmaps < 0) {
 174                 dev_err(pctl->dev,
 175                         "missing allwinner,pins property in node %s\n",
 176                         node->name);
 177                 return -EINVAL;
 178         }
 179
 180         *map = kmalloc(nmaps * sizeof(struct pinctrl_map), GFP_KERNEL);
 181         if (!*map)
 182                 return -ENOMEM;
 183
 184         of_property_for_each_string(node, "allwinner,pins", prop, group) {
 185                 struct sunxi_pinctrl_group *grp =
 186                         sunxi_pinctrl_find_group_by_name(pctl, group);
 187                 int j = 0, configlen = 0;
 188
 189                 if (!grp) {
 190                         dev_err(pctl->dev, "unknown pin %s", group);
 191                         continue;
 192                 }
 193
 194                 if (!sunxi_pinctrl_desc_find_function_by_name(pctl,
 195                                                               grp->name,
 196                                                               function)) {
 197                         dev_err(pctl->dev, "unsupported function %s on pin %s",
 198                                 function, group);
 199                         continue;
 200                 }
 201
 202                 (*map)[i].type = PIN_MAP_TYPE_MUX_GROUP;
 203                 (*map)[i].data.mux.group = group;
 204                 (*map)[i].data.mux.function = function;
 205
 206                 i++;
 207
 208                 (*map)[i].type = PIN_MAP_TYPE_CONFIGS_GROUP;
 209                 (*map)[i].data.configs.group_or_pin = group;
 210
 211                 if (of_find_property(node, "allwinner,drive", NULL))
 212                         configlen++;
 213                 if (of_find_property(node, "allwinner,pull", NULL))
 214                         configlen++;
 215
 216                 pinconfig = kzalloc(configlen * sizeof(*pinconfig), GFP_KERNEL);
 217                 if (!pinconfig) {
 218                         kfree(*map);
 219                         return -ENOMEM;
 220                 }
 221
 222                 if (!of_property_read_u32(node, "allwinner,drive", &val)) {
 223                         u16 strength = (val + 1) * 10;
 224                         pinconfig[j++] =
 225                                 pinconf_to_config_packed(PIN_CONFIG_DRIVE_STRENGTH,
 226                                                          strength);
 227                 }
 228
 229                 if (!of_property_read_u32(node, "allwinner,pull", &val)) {
 230                         enum pin_config_param pull = PIN_CONFIG_END;
 231                         if (val == 1)
 232                                 pull = PIN_CONFIG_BIAS_PULL_UP;
 233                         else if (val == 2)
 234                                 pull = PIN_CONFIG_BIAS_PULL_DOWN;
 235                         pinconfig[j++] = pinconf_to_config_packed(pull, 0);
 236                 }
 237
 238                 (*map)[i].data.configs.configs = pinconfig;
 239                 (*map)[i].data.configs.num_configs = configlen;
 240
 241                 i++;
 242         }
 243
 244         *num_maps = nmaps;
 245
 246         return 0;
 247 }
 248
 249 static void sunxi_pctrl_dt_free_map(struct pinctrl_dev *pctldev,
 250                                     struct pinctrl_map *map,
 251                                     unsigned num_maps)
 252 {
 253         int i;
 254
 255         for (i = 0; i < num_maps; i++) {
 256                 if (map[i].type == PIN_MAP_TYPE_CONFIGS_GROUP)
 257                         kfree(map[i].data.configs.configs);
 258         }
 259
 260         kfree(map);
 261 }
 262
 263 static const struct pinctrl_ops sunxi_pctrl_ops = {
 264         .dt_node_to_map         = sunxi_pctrl_dt_node_to_map,
 265         .dt_free_map            = sunxi_pctrl_dt_free_map,
 266         .get_groups_count       = sunxi_pctrl_get_groups_count,
 267         .get_group_name         = sunxi_pctrl_get_group_name,
 268         .get_group_pins         = sunxi_pctrl_get_group_pins,
 269 };
 270
 271 static int sunxi_pconf_group_get(struct pinctrl_dev *pctldev,
 272                                  unsigned group,
 273                                  unsigned long *config)
 274 {
 275         struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
 276
 277         *config = pctl->groups[group].config;
 278
 279         return 0;
 280 }
 281
 282 static int sunxi_pconf_group_set(struct pinctrl_dev *pctldev,
 283                                  unsigned group,
 284                                  unsigned long *configs,
 285                                  unsigned num_configs)
 286 {
 287         struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
 288         struct sunxi_pinctrl_group *g = &pctl->groups[group];
 289         unsigned long flags;
 290         unsigned pin = g->pin - pctl->desc->pin_base;
 291         u32 val, mask;
 292         u16 strength;
 293         u8 dlevel;
 294         int i;
 295
 296         spin_lock_irqsave(&pctl->lock, flags);
 297
 298         for (i = 0; i < num_configs; i++) {
 299                 switch (pinconf_to_config_param(configs[i])) {
 300                 case PIN_CONFIG_DRIVE_STRENGTH:
 301                         strength = pinconf_to_config_argument(configs[i]);
 302                         if (strength > 40) {
 303                                 spin_unlock_irqrestore(&pctl->lock, flags);
 304                                 return -EINVAL;
 305                         }
 306                         /*
 307                          * We convert from mA to what the register expects:
 308                          *   0: 10mA
 309                          *   1: 20mA
 310                          *   2: 30mA
 311                          *   3: 40mA
 312                          */
 313                         dlevel = strength / 10 - 1;
 314                         val = readl(pctl->membase + sunxi_dlevel_reg(pin));
 315                         mask = DLEVEL_PINS_MASK << sunxi_dlevel_offset(pin);
 316                         writel((val & ~mask)
 317                                 | dlevel << sunxi_dlevel_offset(pin),
 318                                 pctl->membase + sunxi_dlevel_reg(pin));
 319                         break;
 320                 case PIN_CONFIG_BIAS_PULL_UP:
 321                         val = readl(pctl->membase + sunxi_pull_reg(pin));
 322                         mask = PULL_PINS_MASK << sunxi_pull_offset(pin);
 323                         writel((val & ~mask) | 1 << sunxi_pull_offset(pin),
 324                                 pctl->membase + sunxi_pull_reg(pin));
 325                         break;
 326                 case PIN_CONFIG_BIAS_PULL_DOWN:
 327                         val = readl(pctl->membase + sunxi_pull_reg(pin));
 328                         mask = PULL_PINS_MASK << sunxi_pull_offset(pin);
 329                         writel((val & ~mask) | 2 << sunxi_pull_offset(pin),
 330                                 pctl->membase + sunxi_pull_reg(pin));
 331                         break;
 332                 default:
 333                         break;
 334                 }
 335                 /* cache the config value */
 336                 g->config = configs[i];
 337         } /* for each config */
 338
 339         spin_unlock_irqrestore(&pctl->lock, flags);
 340
 341         return 0;
 342 }
 343
 344 static const struct pinconf_ops sunxi_pconf_ops = {
 345         .pin_config_group_get   = sunxi_pconf_group_get,
 346         .pin_config_group_set   = sunxi_pconf_group_set,
 347 };
 348
 349 static int sunxi_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev)
 350 {
 351         struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
 352
 353         return pctl->nfunctions;
 354 }
 355
 356 static const char *sunxi_pmx_get_func_name(struct pinctrl_dev *pctldev,
 357                                            unsigned function)
 358 {
 359         struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
 360
 361         return pctl->functions[function].name;
 362 }
 363
 364 static int sunxi_pmx_get_func_groups(struct pinctrl_dev *pctldev,
 365                                      unsigned function,
 366                                      const char * const **groups,
 367                                      unsigned * const num_groups)
 368 {
 369         struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
 370
 371         *groups = pctl->functions[function].groups;
 372         *num_groups = pctl->functions[function].ngroups;
 373
 374         return 0;
 375 }
 376
 377 static void sunxi_pmx_set(struct pinctrl_dev *pctldev,
 378                                  unsigned pin,
 379                                  u8 config)
 380 {
 381         struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
 382         unsigned long flags;
 383         u32 val, mask;
 384
 385         spin_lock_irqsave(&pctl->lock, flags);
 386
 387         pin -= pctl->desc->pin_base;
 388         val = readl(pctl->membase + sunxi_mux_reg(pin));
 389         mask = MUX_PINS_MASK << sunxi_mux_offset(pin);
 390         writel((val & ~mask) | config << sunxi_mux_offset(pin),
 391                 pctl->membase + sunxi_mux_reg(pin));
 392
 393         spin_unlock_irqrestore(&pctl->lock, flags);
 394 }
 395
 396 static int sunxi_pmx_set_mux(struct pinctrl_dev *pctldev,
 397                              unsigned function,
 398                              unsigned group)
 399 {
 400         struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
 401         struct sunxi_pinctrl_group *g = pctl->groups + group;
 402         struct sunxi_pinctrl_function *func = pctl->functions + function;
 403         struct sunxi_desc_function *desc =
 404                 sunxi_pinctrl_desc_find_function_by_name(pctl,
 405                                                          g->name,
 406                                                          func->name);
 407
 408         if (!desc)
 409                 return -EINVAL;
 410
 411         sunxi_pmx_set(pctldev, g->pin, desc->muxval);
 412
 413         return 0;
 414 }
 415
 416 static int
 417 sunxi_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
 418                         struct pinctrl_gpio_range *range,
 419                         unsigned offset,
 420                         bool input)
 421 {
 422         struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
 423         struct sunxi_desc_function *desc;
 424         const char *func;
 425
 426         if (input)
 427                 func = "gpio_in";
 428         else
 429                 func = "gpio_out";
 430
 431         desc = sunxi_pinctrl_desc_find_function_by_pin(pctl, offset, func);
 432         if (!desc)
 433                 return -EINVAL;
 434
 435         sunxi_pmx_set(pctldev, offset, desc->muxval);
 436
 437         return 0;
 438 }
 439
 440 static const struct pinmux_ops sunxi_pmx_ops = {
 441         .get_functions_count    = sunxi_pmx_get_funcs_cnt,
 442         .get_function_name      = sunxi_pmx_get_func_name,
 443         .get_function_groups    = sunxi_pmx_get_func_groups,
 444         .set_mux                = sunxi_pmx_set_mux,
 445         .gpio_set_direction     = sunxi_pmx_gpio_set_direction,
 446 };
 447
 448 static int sunxi_pinctrl_gpio_direction_input(struct gpio_chip *chip,
 449                                         unsigned offset)
 450 {
 451         return pinctrl_gpio_direction_input(chip->base + offset);
 452 }
 453
 454 static int sunxi_pinctrl_gpio_get(struct gpio_chip *chip, unsigned offset)
 455 {
 456         struct sunxi_pinctrl *pctl = gpiochip_get_data(chip);
 457         u32 reg = sunxi_data_reg(offset);
 458         u8 index = sunxi_data_offset(offset);
 459         bool set_mux = pctl->desc->irq_read_needs_mux &&
 460                 gpiochip_line_is_irq(chip, offset);
 461         u32 pin = offset + chip->base;
 462         u32 val;
 463
 464         if (set_mux)
 465                 sunxi_pmx_set(pctl->pctl_dev, pin, SUN4I_FUNC_INPUT);
 466
 467         val = (readl(pctl->membase + reg) >> index) & DATA_PINS_MASK;
 468
 469         if (set_mux)
 470                 sunxi_pmx_set(pctl->pctl_dev, pin, SUN4I_FUNC_IRQ);
 471
 472         return !!val;
 473 }
 474
 475 static void sunxi_pinctrl_gpio_set(struct gpio_chip *chip,
 476                                 unsigned offset, int value)
 477 {
 478         struct sunxi_pinctrl *pctl = gpiochip_get_data(chip);
 479         u32 reg = sunxi_data_reg(offset);
 480         u8 index = sunxi_data_offset(offset);
 481         unsigned long flags;
 482         u32 regval;
 483
 484         spin_lock_irqsave(&pctl->lock, flags);
 485
 486         regval = readl(pctl->membase + reg);
 487
 488         if (value)
 489                 regval |= BIT(index);
 490         else
 491                 regval &= ~(BIT(index));
 492
 493         writel(regval, pctl->membase + reg);
 494
 495         spin_unlock_irqrestore(&pctl->lock, flags);
 496 }
 497
 498 static int sunxi_pinctrl_gpio_direction_output(struct gpio_chip *chip,
 499                                         unsigned offset, int value)
 500 {
 501         sunxi_pinctrl_gpio_set(chip, offset, value);
 502         return pinctrl_gpio_direction_output(chip->base + offset);
 503 }
 504
 505 static int sunxi_pinctrl_gpio_of_xlate(struct gpio_chip *gc,
 506                                 const struct of_phandle_args *gpiospec,
 507                                 u32 *flags)
 508 {
 509         int pin, base;
 510
 511         base = PINS_PER_BANK * gpiospec->args[0];
 512         pin = base + gpiospec->args[1];
 513
 514         if (pin > gc->ngpio)
 515                 return -EINVAL;
 516
 517         if (flags)
 518                 *flags = gpiospec->args[2];
 519
 520         return pin;
 521 }
 522
 523 static int sunxi_pinctrl_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
 524 {
 525         struct sunxi_pinctrl *pctl = gpiochip_get_data(chip);
 526         struct sunxi_desc_function *desc;
 527         unsigned pinnum = pctl->desc->pin_base + offset;
 528         unsigned irqnum;
 529
 530         if (offset >= chip->ngpio)
 531                 return -ENXIO;
 532
 533         desc = sunxi_pinctrl_desc_find_function_by_pin(pctl, pinnum, "irq");
 534         if (!desc)
 535                 return -EINVAL;
 536
 537         irqnum = desc->irqbank * IRQ_PER_BANK + desc->irqnum;
 538
 539         dev_dbg(chip->parent, "%s: request IRQ for GPIO %d, return %d\n",
 540                 chip->label, offset + chip->base, irqnum);
 541
 542         return irq_find_mapping(pctl->domain, irqnum);
 543 }
 544
 545 static int sunxi_pinctrl_irq_request_resources(struct irq_data *d)
 546 {
 547         struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);
 548         struct sunxi_desc_function *func;
 549         int ret;
 550
 551         func = sunxi_pinctrl_desc_find_function_by_pin(pctl,
 552                                         pctl->irq_array[d->hwirq], "irq");
 553         if (!func)
 554                 return -EINVAL;
 555
 556         ret = gpiochip_lock_as_irq(pctl->chip,
 557                         pctl->irq_array[d->hwirq] - pctl->desc->pin_base);
 558         if (ret) {
 559                 dev_err(pctl->dev, "unable to lock HW IRQ %lu for IRQ\n",
 560                         irqd_to_hwirq(d));
 561                 return ret;
 562         }
 563
 564         /* Change muxing to INT mode */
 565         sunxi_pmx_set(pctl->pctl_dev, pctl->irq_array[d->hwirq], func->muxval);
 566
 567         return 0;
 568 }
 569
 570 static void sunxi_pinctrl_irq_release_resources(struct irq_data *d)
 571 {
 572         struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);
 573
 574         gpiochip_unlock_as_irq(pctl->chip,
 575                               pctl->irq_array[d->hwirq] - pctl->desc->pin_base);
 576 }
 577
 578 static int sunxi_pinctrl_irq_set_type(struct irq_data *d, unsigned int type)
 579 {
 580         struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);
 581         u32 reg = sunxi_irq_cfg_reg(d->hwirq, pctl->desc->irq_bank_base);
 582         u8 index = sunxi_irq_cfg_offset(d->hwirq);
 583         unsigned long flags;
 584         u32 regval;
 585         u8 mode;
 586
 587         switch (type) {
 588         case IRQ_TYPE_EDGE_RISING:
 589                 mode = IRQ_EDGE_RISING;
 590                 break;
 591         case IRQ_TYPE_EDGE_FALLING:
 592                 mode = IRQ_EDGE_FALLING;
 593                 break;
 594         case IRQ_TYPE_EDGE_BOTH:
 595                 mode = IRQ_EDGE_BOTH;
 596                 break;
 597         case IRQ_TYPE_LEVEL_HIGH:
 598                 mode = IRQ_LEVEL_HIGH;
 599                 break;
 600         case IRQ_TYPE_LEVEL_LOW:
 601                 mode = IRQ_LEVEL_LOW;
 602                 break;
 603         default:
 604                 return -EINVAL;
 605         }
 606
 607         spin_lock_irqsave(&pctl->lock, flags);
 608
 609         if (type & IRQ_TYPE_LEVEL_MASK)
 610                 irq_set_chip_handler_name_locked(d, &sunxi_pinctrl_level_irq_chip,
 611                                                  handle_fasteoi_irq, NULL);
 612         else
 613                 irq_set_chip_handler_name_locked(d, &sunxi_pinctrl_edge_irq_chip,
 614                                                  handle_edge_irq, NULL);
 615
 616         regval = readl(pctl->membase + reg);
 617         regval &= ~(IRQ_CFG_IRQ_MASK << index);
 618         writel(regval | (mode << index), pctl->membase + reg);
 619
 620         spin_unlock_irqrestore(&pctl->lock, flags);
 621
 622         return 0;
 623 }
 624
 625 static void sunxi_pinctrl_irq_ack(struct irq_data *d)
 626 {
 627         struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);
 628         u32 status_reg = sunxi_irq_status_reg(d->hwirq,
 629                                               pctl->desc->irq_bank_base);
 630         u8 status_idx = sunxi_irq_status_offset(d->hwirq);
 631
 632         /* Clear the IRQ */
 633         writel(1 << status_idx, pctl->membase + status_reg);
 634 }
 635
 636 static void sunxi_pinctrl_irq_mask(struct irq_data *d)
 637 {
 638         struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);
 639         u32 reg = sunxi_irq_ctrl_reg(d->hwirq, pctl->desc->irq_bank_base);
 640         u8 idx = sunxi_irq_ctrl_offset(d->hwirq);
 641         unsigned long flags;
 642         u32 val;
 643
 644         spin_lock_irqsave(&pctl->lock, flags);
 645
 646         /* Mask the IRQ */
 647         val = readl(pctl->membase + reg);
 648         writel(val & ~(1 << idx), pctl->membase + reg);
 649
 650         spin_unlock_irqrestore(&pctl->lock, flags);
 651 }
 652
 653 static void sunxi_pinctrl_irq_unmask(struct irq_data *d)
 654 {
 655         struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);
 656         u32 reg = sunxi_irq_ctrl_reg(d->hwirq, pctl->desc->irq_bank_base);
 657         u8 idx = sunxi_irq_ctrl_offset(d->hwirq);
 658         unsigned long flags;
 659         u32 val;
 660
 661         spin_lock_irqsave(&pctl->lock, flags);
 662
 663         /* Unmask the IRQ */
 664         val = readl(pctl->membase + reg);
 665         writel(val | (1 << idx), pctl->membase + reg);
 666
 667         spin_unlock_irqrestore(&pctl->lock, flags);
 668 }
 669
 670 static void sunxi_pinctrl_irq_ack_unmask(struct irq_data *d)
 671 {
 672         sunxi_pinctrl_irq_ack(d);
 673         sunxi_pinctrl_irq_unmask(d);
 674 }
 675
 676 static struct irq_chip sunxi_pinctrl_edge_irq_chip = {
 677         .name           = "sunxi_pio_edge",
 678         .irq_ack        = sunxi_pinctrl_irq_ack,
 679         .irq_mask       = sunxi_pinctrl_irq_mask,
 680         .irq_unmask     = sunxi_pinctrl_irq_unmask,
 681         .irq_request_resources = sunxi_pinctrl_irq_request_resources,
 682         .irq_release_resources = sunxi_pinctrl_irq_release_resources,
 683         .irq_set_type   = sunxi_pinctrl_irq_set_type,
 684         .flags          = IRQCHIP_SKIP_SET_WAKE,
 685 };
 686
 687 static struct irq_chip sunxi_pinctrl_level_irq_chip = {
 688         .name           = "sunxi_pio_level",
 689         .irq_eoi        = sunxi_pinctrl_irq_ack,
 690         .irq_mask       = sunxi_pinctrl_irq_mask,
 691         .irq_unmask     = sunxi_pinctrl_irq_unmask,
 692         /* Define irq_enable / disable to avoid spurious irqs for drivers
 693          * using these to suppress irqs while they clear the irq source */
 694         .irq_enable     = sunxi_pinctrl_irq_ack_unmask,
 695         .irq_disable    = sunxi_pinctrl_irq_mask,
 696         .irq_request_resources = sunxi_pinctrl_irq_request_resources,
 697         .irq_release_resources = sunxi_pinctrl_irq_release_resources,
 698         .irq_set_type   = sunxi_pinctrl_irq_set_type,
 699         .flags          = IRQCHIP_SKIP_SET_WAKE | IRQCHIP_EOI_THREADED |
 700                           IRQCHIP_EOI_IF_HANDLED,
 701 };
 702
 703 static int sunxi_pinctrl_irq_of_xlate(struct irq_domain *d,
 704                                       struct device_node *node,
 705                                       const u32 *intspec,
 706                                       unsigned int intsize,
 707                                       unsigned long *out_hwirq,
 708                                       unsigned int *out_type)
 709 {
 710         struct sunxi_pinctrl *pctl = d->host_data;
 711         struct sunxi_desc_function *desc;
 712         int pin, base;
 713
 714         if (intsize < 3)
 715                 return -EINVAL;
 716
 717         base = PINS_PER_BANK * intspec[0];
 718         pin = pctl->desc->pin_base + base + intspec[1];
 719
 720         desc = sunxi_pinctrl_desc_find_function_by_pin(pctl, pin, "irq");
 721         if (!desc)
 722                 return -EINVAL;
 723
 724         *out_hwirq = desc->irqbank * PINS_PER_BANK + desc->irqnum;
 725         *out_type = intspec[2];
 726
 727         return 0;
 728 }
 729
 730 static struct irq_domain_ops sunxi_pinctrl_irq_domain_ops = {
 731         .xlate          = sunxi_pinctrl_irq_of_xlate,
 732 };
 733
 734 static void sunxi_pinctrl_irq_handler(struct irq_desc *desc)
 735 {
 736         unsigned int irq = irq_desc_get_irq(desc);
 737         struct irq_chip *chip = irq_desc_get_chip(desc);
 738         struct sunxi_pinctrl *pctl = irq_desc_get_handler_data(desc);
 739         unsigned long bank, reg, val;
 740
 741         for (bank = 0; bank < pctl->desc->irq_banks; bank++)
 742                 if (irq == pctl->irq[bank])
 743                         break;
 744
 745         if (bank == pctl->desc->irq_banks)
 746                 return;
 747
 748         reg = sunxi_irq_status_reg_from_bank(bank, pctl->desc->irq_bank_base);
 749         val = readl(pctl->membase + reg);
 750
 751         if (val) {
 752                 int irqoffset;
 753
 754                 chained_irq_enter(chip, desc);
 755                 for_each_set_bit(irqoffset, &val, IRQ_PER_BANK) {
 756                         int pin_irq = irq_find_mapping(pctl->domain,
 757                                                        bank * IRQ_PER_BANK + irqoffset);
 758                         generic_handle_irq(pin_irq);
 759                 }
 760                 chained_irq_exit(chip, desc);
 761         }
 762 }
 763
 764 static int sunxi_pinctrl_add_function(struct sunxi_pinctrl *pctl,
 765                                         const char *name)
 766 {
 767         struct sunxi_pinctrl_function *func = pctl->functions;
 768
 769         while (func->name) {
 770                 /* function already there */
 771                 if (strcmp(func->name, name) == 0) {
 772                         func->ngroups++;
 773                         return -EEXIST;
 774                 }
 775                 func++;
 776         }
 777
 778         func->name = name;
 779         func->ngroups = 1;
 780
 781         pctl->nfunctions++;
 782
 783         return 0;
 784 }
 785
 786 static int sunxi_pinctrl_build_state(struct platform_device *pdev)
 787 {
 788         struct sunxi_pinctrl *pctl = platform_get_drvdata(pdev);
 789         int i;
 790
 791         pctl->ngroups = pctl->desc->npins;
 792
 793         /* Allocate groups */
 794         pctl->groups = devm_kzalloc(&pdev->dev,
 795                                     pctl->ngroups * sizeof(*pctl->groups),
 796                                     GFP_KERNEL);
 797         if (!pctl->groups)
 798                 return -ENOMEM;
 799
 800         for (i = 0; i < pctl->desc->npins; i++) {
 801                 const struct sunxi_desc_pin *pin = pctl->desc->pins + i;
 802                 struct sunxi_pinctrl_group *group = pctl->groups + i;
 803
 804                 group->name = pin->pin.name;
 805                 group->pin = pin->pin.number;
 806         }
 807
 808         /*
 809          * We suppose that we won't have any more functions than pins,
 810          * we'll reallocate that later anyway
 811          */
 812         pctl->functions = devm_kzalloc(&pdev->dev,
 813                                 pctl->desc->npins * sizeof(*pctl->functions),
 814                                 GFP_KERNEL);
 815         if (!pctl->functions)
 816                 return -ENOMEM;
 817
 818         /* Count functions and their associated groups */
 819         for (i = 0; i < pctl->desc->npins; i++) {
 820                 const struct sunxi_desc_pin *pin = pctl->desc->pins + i;
 821                 struct sunxi_desc_function *func = pin->functions;
 822
 823                 while (func->name) {
 824                         /* Create interrupt mapping while we're at it */
 825                         if (!strcmp(func->name, "irq")) {
 826                                 int irqnum = func->irqnum + func->irqbank * IRQ_PER_BANK;
 827                                 pctl->irq_array[irqnum] = pin->pin.number;
 828                         }
 829
 830                         sunxi_pinctrl_add_function(pctl, func->name);
 831                         func++;
 832                 }
 833         }
 834
 835         pctl->functions = krealloc(pctl->functions,
 836                                 pctl->nfunctions * sizeof(*pctl->functions),
 837                                 GFP_KERNEL);
 838
 839         for (i = 0; i < pctl->desc->npins; i++) {
 840                 const struct sunxi_desc_pin *pin = pctl->desc->pins + i;
 841                 struct sunxi_desc_function *func = pin->functions;
 842
 843                 while (func->name) {
 844                         struct sunxi_pinctrl_function *func_item;
 845                         const char **func_grp;
 846
 847                         func_item = sunxi_pinctrl_find_function_by_name(pctl,
 848                                                                         func->name);
 849                         if (!func_item)
 850                                 return -EINVAL;
 851
 852                         if (!func_item->groups) {
 853                                 func_item->groups =
 854                                         devm_kzalloc(&pdev->dev,
 855                                                      func_item->ngroups * sizeof(*func_item->groups),
 856                                                      GFP_KERNEL);
 857                                 if (!func_item->groups)
 858                                         return -ENOMEM;
 859                         }
 860
 861                         func_grp = func_item->groups;
 862                         while (*func_grp)
 863                                 func_grp++;
 864
 865                         *func_grp = pin->pin.name;
 866                         func++;
 867                 }
 868         }
 869
 870         return 0;
 871 }
 872
 873 int sunxi_pinctrl_init(struct platform_device *pdev,
 874                        const struct sunxi_pinctrl_desc *desc)
 875 {
 876         struct device_node *node = pdev->dev.of_node;
 877         struct pinctrl_desc *pctrl_desc;
 878         struct pinctrl_pin_desc *pins;
 879         struct sunxi_pinctrl *pctl;
 880         struct resource *res;
 881         int i, ret, last_pin;
 882         struct clk *clk;
 883
 884         pctl = devm_kzalloc(&pdev->dev, sizeof(*pctl), GFP_KERNEL);
 885         if (!pctl)
 886                 return -ENOMEM;
 887         platform_set_drvdata(pdev, pctl);
 888
 889         spin_lock_init(&pctl->lock);
 890
 891         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 892         pctl->membase = devm_ioremap_resource(&pdev->dev, res);
 893         if (IS_ERR(pctl->membase))
 894                 return PTR_ERR(pctl->membase);
 895
 896         pctl->dev = &pdev->dev;
 897         pctl->desc = desc;
 898
 899         pctl->irq_array = devm_kcalloc(&pdev->dev,
 900                                        IRQ_PER_BANK * pctl->desc->irq_banks,
 901                                        sizeof(*pctl->irq_array),
 902                                        GFP_KERNEL);
 903         if (!pctl->irq_array)
 904                 return -ENOMEM;
 905
 906         ret = sunxi_pinctrl_build_state(pdev);
 907         if (ret) {
 908                 dev_err(&pdev->dev, "dt probe failed: %d\n", ret);
 909                 return ret;
 910         }
 911
 912         pins = devm_kzalloc(&pdev->dev,
 913                             pctl->desc->npins * sizeof(*pins),
 914                             GFP_KERNEL);
 915         if (!pins)
 916                 return -ENOMEM;
 917
 918         for (i = 0; i < pctl->desc->npins; i++)
 919                 pins[i] = pctl->desc->pins[i].pin;
 920
 921         pctrl_desc = devm_kzalloc(&pdev->dev,
 922                                   sizeof(*pctrl_desc),
 923                                   GFP_KERNEL);
 924         if (!pctrl_desc)
 925                 return -ENOMEM;
 926
 927         pctrl_desc->name = dev_name(&pdev->dev);
 928         pctrl_desc->owner = THIS_MODULE;
 929         pctrl_desc->pins = pins;
 930         pctrl_desc->npins = pctl->desc->npins;
 931         pctrl_desc->confops = &sunxi_pconf_ops;
 932         pctrl_desc->pctlops = &sunxi_pctrl_ops;
 933         pctrl_desc->pmxops =  &sunxi_pmx_ops;
 934
 935         pctl->pctl_dev = devm_pinctrl_register(&pdev->dev, pctrl_desc, pctl);
 936         if (IS_ERR(pctl->pctl_dev)) {
 937                 dev_err(&pdev->dev, "couldn't register pinctrl driver\n");
 938                 return PTR_ERR(pctl->pctl_dev);
 939         }
 940
 941         pctl->chip = devm_kzalloc(&pdev->dev, sizeof(*pctl->chip), GFP_KERNEL);
 942         if (!pctl->chip)
 943                 return -ENOMEM;
 944
 945         last_pin = pctl->desc->pins[pctl->desc->npins - 1].pin.number;
 946         pctl->chip->owner = THIS_MODULE;
 947         pctl->chip->request = gpiochip_generic_request,
 948         pctl->chip->free = gpiochip_generic_free,
 949         pctl->chip->direction_input = sunxi_pinctrl_gpio_direction_input,
 950         pctl->chip->direction_output = sunxi_pinctrl_gpio_direction_output,
 951         pctl->chip->get = sunxi_pinctrl_gpio_get,
 952         pctl->chip->set = sunxi_pinctrl_gpio_set,
 953         pctl->chip->of_xlate = sunxi_pinctrl_gpio_of_xlate,
 954         pctl->chip->to_irq = sunxi_pinctrl_gpio_to_irq,
 955         pctl->chip->of_gpio_n_cells = 3,
 956         pctl->chip->can_sleep = false,
 957         pctl->chip->ngpio = round_up(last_pin, PINS_PER_BANK) -
 958                             pctl->desc->pin_base;
 959         pctl->chip->label = dev_name(&pdev->dev);
 960         pctl->chip->parent = &pdev->dev;
 961         pctl->chip->base = pctl->desc->pin_base;
 962
 963         ret = gpiochip_add_data(pctl->chip, pctl);
 964         if (ret)
 965                 return ret;
 966
 967         for (i = 0; i < pctl->desc->npins; i++) {
 968                 const struct sunxi_desc_pin *pin = pctl->desc->pins + i;
 969
 970                 ret = gpiochip_add_pin_range(pctl->chip, dev_name(&pdev->dev),
 971                                              pin->pin.number - pctl->desc->pin_base,
 972                                              pin->pin.number, 1);
 973                 if (ret)
 974                         goto gpiochip_error;
 975         }
 976
 977         clk = devm_clk_get(&pdev->dev, NULL);
 978         if (IS_ERR(clk)) {
 979                 ret = PTR_ERR(clk);
 980                 goto gpiochip_error;
 981         }
 982
 983         ret = clk_prepare_enable(clk);
 984         if (ret)
 985                 goto gpiochip_error;
 986
 987         pctl->irq = devm_kcalloc(&pdev->dev,
 988                                  pctl->desc->irq_banks,
 989                                  sizeof(*pctl->irq),
 990                                  GFP_KERNEL);
 991         if (!pctl->irq) {
 992                 ret = -ENOMEM;
 993                 goto clk_error;
 994         }
 995
 996         for (i = 0; i < pctl->desc->irq_banks; i++) {
 997                 pctl->irq[i] = platform_get_irq(pdev, i);
 998                 if (pctl->irq[i] < 0) {
 999                         ret = pctl->irq[i];
1000                         goto clk_error;
1001                 }
1002         }
1003
1004         pctl->domain = irq_domain_add_linear(node,
1005                                              pctl->desc->irq_banks * IRQ_PER_BANK,
1006                                              &sunxi_pinctrl_irq_domain_ops,
1007                                              pctl);
1008         if (!pctl->domain) {
1009                 dev_err(&pdev->dev, "Couldn't register IRQ domain\n");
1010                 ret = -ENOMEM;
1011                 goto clk_error;
1012         }
1013
1014         for (i = 0; i < (pctl->desc->irq_banks * IRQ_PER_BANK); i++) {
1015                 int irqno = irq_create_mapping(pctl->domain, i);
1016
1017                 irq_set_chip_and_handler(irqno, &sunxi_pinctrl_edge_irq_chip,
1018                                          handle_edge_irq);
1019                 irq_set_chip_data(irqno, pctl);
1020         }
1021
1022         for (i = 0; i < pctl->desc->irq_banks; i++) {
1023                 /* Mask and clear all IRQs before registering a handler */
1024                 writel(0, pctl->membase + sunxi_irq_ctrl_reg_from_bank(i,
1025                                                 pctl->desc->irq_bank_base));
1026                 writel(0xffffffff,
1027                        pctl->membase + sunxi_irq_status_reg_from_bank(i,
1028                                                 pctl->desc->irq_bank_base));
1029
1030                 irq_set_chained_handler_and_data(pctl->irq[i],
1031                                                  sunxi_pinctrl_irq_handler,
1032                                                  pctl);
1033         }
1034
1035         dev_info(&pdev->dev, "initialized sunXi PIO driver\n");
1036
1037         return 0;
1038
1039 clk_error:
1040         clk_disable_unprepare(clk);
1041 gpiochip_error:
1042         gpiochip_remove(pctl->chip);
1043         return ret;
1044 }