2 * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
15 #ifndef __PINCTRL_UNIPHIER_H__
16 #define __PINCTRL_UNIPHIER_H__
18 #include <linux/bug.h>
19 #include <linux/kernel.h>
20 #include <linux/types.h>
22 struct platform_device;
24 #define UNIPHIER_PINCTRL_PINMUX_BASE 0x0
25 #define UNIPHIER_PINCTRL_LOAD_PINMUX 0x700
26 #define UNIPHIER_PINCTRL_DRVCTRL_BASE 0x800
27 #define UNIPHIER_PINCTRL_DRV2CTRL_BASE 0x900
28 #define UNIPHIER_PINCTRL_DRV3CTRL_BASE 0x980
29 #define UNIPHIER_PINCTRL_PUPDCTRL_BASE 0xa00
30 #define UNIPHIER_PINCTRL_IECTRL 0xd00
32 /* input enable control register bit */
33 #define UNIPHIER_PIN_IECTRL_SHIFT 0
34 #define UNIPHIER_PIN_IECTRL_BITS 8
35 #define UNIPHIER_PIN_IECTRL_MASK ((1UL << (UNIPHIER_PIN_IECTRL_BITS)) \
38 /* drive strength control register number */
39 #define UNIPHIER_PIN_DRVCTRL_SHIFT ((UNIPHIER_PIN_IECTRL_SHIFT) + \
40 (UNIPHIER_PIN_IECTRL_BITS))
41 #define UNIPHIER_PIN_DRVCTRL_BITS 9
42 #define UNIPHIER_PIN_DRVCTRL_MASK ((1UL << (UNIPHIER_PIN_DRVCTRL_BITS)) \
45 /* drive control type */
46 #define UNIPHIER_PIN_DRV_TYPE_SHIFT ((UNIPHIER_PIN_DRVCTRL_SHIFT) + \
47 (UNIPHIER_PIN_DRVCTRL_BITS))
48 #define UNIPHIER_PIN_DRV_TYPE_BITS 3
49 #define UNIPHIER_PIN_DRV_TYPE_MASK ((1UL << (UNIPHIER_PIN_DRV_TYPE_BITS)) \
52 /* pull-up / pull-down register number */
53 #define UNIPHIER_PIN_PUPDCTRL_SHIFT ((UNIPHIER_PIN_DRV_TYPE_SHIFT) + \
54 (UNIPHIER_PIN_DRV_TYPE_BITS))
55 #define UNIPHIER_PIN_PUPDCTRL_BITS 9
56 #define UNIPHIER_PIN_PUPDCTRL_MASK ((1UL << (UNIPHIER_PIN_PUPDCTRL_BITS))\
59 /* direction of pull register */
60 #define UNIPHIER_PIN_PULL_DIR_SHIFT ((UNIPHIER_PIN_PUPDCTRL_SHIFT) + \
61 (UNIPHIER_PIN_PUPDCTRL_BITS))
62 #define UNIPHIER_PIN_PULL_DIR_BITS 3
63 #define UNIPHIER_PIN_PULL_DIR_MASK ((1UL << (UNIPHIER_PIN_PULL_DIR_BITS))\
66 #if UNIPHIER_PIN_PULL_DIR_SHIFT + UNIPHIER_PIN_PULL_DIR_BITS > BITS_PER_LONG
67 #error "unable to pack pin attributes."
70 #define UNIPHIER_PIN_IECTRL_NONE (UNIPHIER_PIN_IECTRL_MASK)
72 /* drive control type */
73 enum uniphier_pin_drv_type {
74 UNIPHIER_PIN_DRV_1BIT, /* 2 level control: 4/8 mA */
75 UNIPHIER_PIN_DRV_2BIT, /* 4 level control: 8/12/16/20 mA */
76 UNIPHIER_PIN_DRV_3BIT, /* 8 level control: 4/5/7/9/11/12/14/16 mA */
77 UNIPHIER_PIN_DRV_FIXED4, /* fixed to 4mA */
78 UNIPHIER_PIN_DRV_FIXED5, /* fixed to 5mA */
79 UNIPHIER_PIN_DRV_FIXED8, /* fixed to 8mA */
80 UNIPHIER_PIN_DRV_NONE, /* no support (input only pin) */
83 /* direction of pull register (no pin supports bi-directional pull biasing) */
84 enum uniphier_pin_pull_dir {
85 UNIPHIER_PIN_PULL_UP, /* pull-up or disabled */
86 UNIPHIER_PIN_PULL_DOWN, /* pull-down or disabled */
87 UNIPHIER_PIN_PULL_UP_FIXED, /* always pull-up */
88 UNIPHIER_PIN_PULL_DOWN_FIXED, /* always pull-down */
89 UNIPHIER_PIN_PULL_NONE, /* no pull register */
92 #define UNIPHIER_PIN_IECTRL(x) \
93 (((x) & (UNIPHIER_PIN_IECTRL_MASK)) << (UNIPHIER_PIN_IECTRL_SHIFT))
94 #define UNIPHIER_PIN_DRVCTRL(x) \
95 (((x) & (UNIPHIER_PIN_DRVCTRL_MASK)) << (UNIPHIER_PIN_DRVCTRL_SHIFT))
96 #define UNIPHIER_PIN_DRV_TYPE(x) \
97 (((x) & (UNIPHIER_PIN_DRV_TYPE_MASK)) << (UNIPHIER_PIN_DRV_TYPE_SHIFT))
98 #define UNIPHIER_PIN_PUPDCTRL(x) \
99 (((x) & (UNIPHIER_PIN_PUPDCTRL_MASK)) << (UNIPHIER_PIN_PUPDCTRL_SHIFT))
100 #define UNIPHIER_PIN_PULL_DIR(x) \
101 (((x) & (UNIPHIER_PIN_PULL_DIR_MASK)) << (UNIPHIER_PIN_PULL_DIR_SHIFT))
103 #define UNIPHIER_PIN_ATTR_PACKED(iectrl, drvctrl, drv_type, pupdctrl, pull_dir)\
104 (UNIPHIER_PIN_IECTRL(iectrl) | \
105 UNIPHIER_PIN_DRVCTRL(drvctrl) | \
106 UNIPHIER_PIN_DRV_TYPE(drv_type) | \
107 UNIPHIER_PIN_PUPDCTRL(pupdctrl) | \
108 UNIPHIER_PIN_PULL_DIR(pull_dir))
110 static inline unsigned int uniphier_pin_get_iectrl(void *drv_data)
112 return ((unsigned long)drv_data >> UNIPHIER_PIN_IECTRL_SHIFT) &
113 UNIPHIER_PIN_IECTRL_MASK;
116 static inline unsigned int uniphier_pin_get_drvctrl(void *drv_data)
118 return ((unsigned long)drv_data >> UNIPHIER_PIN_DRVCTRL_SHIFT) &
119 UNIPHIER_PIN_DRVCTRL_MASK;
122 static inline unsigned int uniphier_pin_get_drv_type(void *drv_data)
124 return ((unsigned long)drv_data >> UNIPHIER_PIN_DRV_TYPE_SHIFT) &
125 UNIPHIER_PIN_DRV_TYPE_MASK;
128 static inline unsigned int uniphier_pin_get_pupdctrl(void *drv_data)
130 return ((unsigned long)drv_data >> UNIPHIER_PIN_PUPDCTRL_SHIFT) &
131 UNIPHIER_PIN_PUPDCTRL_MASK;
134 static inline unsigned int uniphier_pin_get_pull_dir(void *drv_data)
136 return ((unsigned long)drv_data >> UNIPHIER_PIN_PULL_DIR_SHIFT) &
137 UNIPHIER_PIN_PULL_DIR_MASK;
140 enum uniphier_pinmux_gpio_range_type {
141 UNIPHIER_PINMUX_GPIO_RANGE_PORT,
142 UNIPHIER_PINMUX_GPIO_RANGE_IRQ,
143 UNIPHIER_PINMUX_GPIO_RANGE_NONE,
146 struct uniphier_pinctrl_group {
148 const unsigned *pins;
150 const unsigned *muxvals;
151 enum uniphier_pinmux_gpio_range_type range_type;
154 struct uniphier_pinmux_function {
156 const char * const *groups;
160 struct uniphier_pinctrl_socdata {
161 const struct pinctrl_pin_desc *pins;
163 const struct uniphier_pinctrl_group *groups;
165 const struct uniphier_pinmux_function *functions;
172 #define UNIPHIER_PINCTRL_PIN(a, b, c, d, e, f, g) \
176 .drv_data = (void *)UNIPHIER_PIN_ATTR_PACKED(c, d, e, f, g), \
179 #define __UNIPHIER_PINCTRL_GROUP(grp, type) \
182 .pins = grp##_pins, \
183 .num_pins = ARRAY_SIZE(grp##_pins), \
184 .muxvals = grp##_muxvals + \
185 BUILD_BUG_ON_ZERO(ARRAY_SIZE(grp##_pins) != \
186 ARRAY_SIZE(grp##_muxvals)), \
187 .range_type = type, \
190 #define UNIPHIER_PINCTRL_GROUP(grp) \
191 __UNIPHIER_PINCTRL_GROUP(grp, UNIPHIER_PINMUX_GPIO_RANGE_NONE)
193 #define UNIPHIER_PINCTRL_GROUP_GPIO_RANGE_PORT(grp) \
194 __UNIPHIER_PINCTRL_GROUP(grp, UNIPHIER_PINMUX_GPIO_RANGE_PORT)
196 #define UNIPHIER_PINCTRL_GROUP_GPIO_RANGE_IRQ(grp) \
197 __UNIPHIER_PINCTRL_GROUP(grp, UNIPHIER_PINMUX_GPIO_RANGE_IRQ)
199 #define UNIPHIER_PINCTRL_GROUP_SINGLE(grp, array, ofst) \
202 .pins = array##_pins + ofst, \
204 .muxvals = array##_muxvals + ofst, \
207 #define UNIPHIER_PINMUX_FUNCTION(func) \
210 .groups = func##_groups, \
211 .num_groups = ARRAY_SIZE(func##_groups), \
214 int uniphier_pinctrl_probe(struct platform_device *pdev,
215 struct uniphier_pinctrl_socdata *socdata);
217 #endif /* __PINCTRL_UNIPHIER_H__ */