drivers/regulator/wm8350-regulator.c

   1 /*
   2  * wm8350.c  --  Voltage and current regulation for the Wolfson WM8350 PMIC
   3  *
   4  * Copyright 2007, 2008 Wolfson Microelectronics PLC.
   5  *
   6  * Author: Liam Girdwood
   7  *         linux@wolfsonmicro.com
   8  *
   9  *  This program is free software; you can redistribute  it and/or modify it
  10  *  under  the terms of  the GNU General  Public License as published by the
  11  *  Free Software Foundation;  either version 2 of the  License, or (at your
  12  *  option) any later version.
  13  */
  14
  15 #include <linux/module.h>
  16 #include <linux/moduleparam.h>
  17 #include <linux/init.h>
  18 #include <linux/bitops.h>
  19 #include <linux/err.h>
  20 #include <linux/i2c.h>
  21 #include <linux/mfd/wm8350/core.h>
  22 #include <linux/mfd/wm8350/pmic.h>
  23 #include <linux/platform_device.h>
  24 #include <linux/regulator/driver.h>
  25 #include <linux/regulator/machine.h>
  26
  27 /* Maximum value possible for VSEL */
  28 #define WM8350_DCDC_MAX_VSEL 0x66
  29
  30 /* Microamps */
  31 static const int isink_cur[] = {
  32         4,
  33         5,
  34         6,
  35         7,
  36         8,
  37         10,
  38         11,
  39         14,
  40         16,
  41         19,
  42         23,
  43         27,
  44         32,
  45         39,
  46         46,
  47         54,
  48         65,
  49         77,
  50         92,
  51         109,
  52         130,
  53         154,
  54         183,
  55         218,
  56         259,
  57         308,
  58         367,
  59         436,
  60         518,
  61         616,
  62         733,
  63         872,
  64         1037,
  65         1233,
  66         1466,
  67         1744,
  68         2073,
  69         2466,
  70         2933,
  71         3487,
  72         4147,
  73         4932,
  74         5865,
  75         6975,
  76         8294,
  77         9864,
  78         11730,
  79         13949,
  80         16589,
  81         19728,
  82         23460,
  83         27899,
  84         33178,
  85         39455,
  86         46920,
  87         55798,
  88         66355,
  89         78910,
  90         93840,
  91         111596,
  92         132710,
  93         157820,
  94         187681,
  95         223191
  96 };
  97
  98 static int get_isink_val(int min_uA, int max_uA, u16 *setting)
  99 {
 100         int i;
 101
 102         for (i = 0; i < ARRAY_SIZE(isink_cur); i++) {
 103                 if (min_uA <= isink_cur[i] && max_uA >= isink_cur[i]) {
 104                         *setting = i;
 105                         return 0;
 106                 }
 107         }
 108         return -EINVAL;
 109 }
 110
 111 static inline int wm8350_ldo_val_to_mvolts(unsigned int val)
 112 {
 113         if (val < 16)
 114                 return (val * 50) + 900;
 115         else
 116                 return ((val - 16) * 100) + 1800;
 117
 118 }
 119
 120 static inline unsigned int wm8350_ldo_mvolts_to_val(int mV)
 121 {
 122         if (mV < 1800)
 123                 return (mV - 900) / 50;
 124         else
 125                 return ((mV - 1800) / 100) + 16;
 126 }
 127
 128 static inline int wm8350_dcdc_val_to_mvolts(unsigned int val)
 129 {
 130         return (val * 25) + 850;
 131 }
 132
 133 static inline unsigned int wm8350_dcdc_mvolts_to_val(int mV)
 134 {
 135         return (mV - 850) / 25;
 136 }
 137
 138 static int wm8350_isink_set_current(struct regulator_dev *rdev, int min_uA,
 139         int max_uA)
 140 {
 141         struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
 142         int isink = rdev_get_id(rdev);
 143         u16 val, setting;
 144         int ret;
 145
 146         ret = get_isink_val(min_uA, max_uA, &setting);
 147         if (ret != 0)
 148                 return ret;
 149
 150         switch (isink) {
 151         case WM8350_ISINK_A:
 152                 val = wm8350_reg_read(wm8350, WM8350_CURRENT_SINK_DRIVER_A) &
 153                     ~WM8350_CS1_ISEL_MASK;
 154                 wm8350_reg_write(wm8350, WM8350_CURRENT_SINK_DRIVER_A,
 155                                  val | setting);
 156                 break;
 157         case WM8350_ISINK_B:
 158                 val = wm8350_reg_read(wm8350, WM8350_CURRENT_SINK_DRIVER_B) &
 159                     ~WM8350_CS1_ISEL_MASK;
 160                 wm8350_reg_write(wm8350, WM8350_CURRENT_SINK_DRIVER_B,
 161                                  val | setting);
 162                 break;
 163         default:
 164                 return -EINVAL;
 165         }
 166
 167         return 0;
 168 }
 169
 170 static int wm8350_isink_get_current(struct regulator_dev *rdev)
 171 {
 172         struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
 173         int isink = rdev_get_id(rdev);
 174         u16 val;
 175
 176         switch (isink) {
 177         case WM8350_ISINK_A:
 178                 val = wm8350_reg_read(wm8350, WM8350_CURRENT_SINK_DRIVER_A) &
 179                     WM8350_CS1_ISEL_MASK;
 180                 break;
 181         case WM8350_ISINK_B:
 182                 val = wm8350_reg_read(wm8350, WM8350_CURRENT_SINK_DRIVER_B) &
 183                     WM8350_CS1_ISEL_MASK;
 184                 break;
 185         default:
 186                 return 0;
 187         }
 188
 189         return isink_cur[val];
 190 }
 191
 192 /* turn on ISINK followed by DCDC */
 193 static int wm8350_isink_enable(struct regulator_dev *rdev)
 194 {
 195         struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
 196         int isink = rdev_get_id(rdev);
 197
 198         switch (isink) {
 199         case WM8350_ISINK_A:
 200                 switch (wm8350->pmic.isink_A_dcdc) {
 201                 case WM8350_DCDC_2:
 202                 case WM8350_DCDC_5:
 203                         wm8350_set_bits(wm8350, WM8350_POWER_MGMT_7,
 204                                         WM8350_CS1_ENA);
 205                         wm8350_set_bits(wm8350, WM8350_CSA_FLASH_CONTROL,
 206                                         WM8350_CS1_DRIVE);
 207                         wm8350_set_bits(wm8350, WM8350_DCDC_LDO_REQUESTED,
 208                                         1 << (wm8350->pmic.isink_A_dcdc -
 209                                               WM8350_DCDC_1));
 210                         break;
 211                 default:
 212                         return -EINVAL;
 213                 }
 214                 break;
 215         case WM8350_ISINK_B:
 216                 switch (wm8350->pmic.isink_B_dcdc) {
 217                 case WM8350_DCDC_2:
 218                 case WM8350_DCDC_5:
 219                         wm8350_set_bits(wm8350, WM8350_POWER_MGMT_7,
 220                                         WM8350_CS2_ENA);
 221                         wm8350_set_bits(wm8350, WM8350_CSB_FLASH_CONTROL,
 222                                         WM8350_CS2_DRIVE);
 223                         wm8350_set_bits(wm8350, WM8350_DCDC_LDO_REQUESTED,
 224                                         1 << (wm8350->pmic.isink_B_dcdc -
 225                                               WM8350_DCDC_1));
 226                         break;
 227                 default:
 228                         return -EINVAL;
 229                 }
 230                 break;
 231         default:
 232                 return -EINVAL;
 233         }
 234         return 0;
 235 }
 236
 237 static int wm8350_isink_disable(struct regulator_dev *rdev)
 238 {
 239         struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
 240         int isink = rdev_get_id(rdev);
 241
 242         switch (isink) {
 243         case WM8350_ISINK_A:
 244                 switch (wm8350->pmic.isink_A_dcdc) {
 245                 case WM8350_DCDC_2:
 246                 case WM8350_DCDC_5:
 247                         wm8350_clear_bits(wm8350, WM8350_DCDC_LDO_REQUESTED,
 248                                           1 << (wm8350->pmic.isink_A_dcdc -
 249                                                 WM8350_DCDC_1));
 250                         wm8350_clear_bits(wm8350, WM8350_POWER_MGMT_7,
 251                                           WM8350_CS1_ENA);
 252                         break;
 253                 default:
 254                         return -EINVAL;
 255                 }
 256                 break;
 257         case WM8350_ISINK_B:
 258                 switch (wm8350->pmic.isink_B_dcdc) {
 259                 case WM8350_DCDC_2:
 260                 case WM8350_DCDC_5:
 261                         wm8350_clear_bits(wm8350, WM8350_DCDC_LDO_REQUESTED,
 262                                           1 << (wm8350->pmic.isink_B_dcdc -
 263                                                 WM8350_DCDC_1));
 264                         wm8350_clear_bits(wm8350, WM8350_POWER_MGMT_7,
 265                                           WM8350_CS2_ENA);
 266                         break;
 267                 default:
 268                         return -EINVAL;
 269                 }
 270                 break;
 271         default:
 272                 return -EINVAL;
 273         }
 274         return 0;
 275 }
 276
 277 static int wm8350_isink_is_enabled(struct regulator_dev *rdev)
 278 {
 279         struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
 280         int isink = rdev_get_id(rdev);
 281
 282         switch (isink) {
 283         case WM8350_ISINK_A:
 284                 return wm8350_reg_read(wm8350, WM8350_CURRENT_SINK_DRIVER_A) &
 285                     0x8000;
 286         case WM8350_ISINK_B:
 287                 return wm8350_reg_read(wm8350, WM8350_CURRENT_SINK_DRIVER_B) &
 288                     0x8000;
 289         }
 290         return -EINVAL;
 291 }
 292
 293 static int wm8350_isink_enable_time(struct regulator_dev *rdev)
 294 {
 295         struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
 296         int isink = rdev_get_id(rdev);
 297         int reg;
 298
 299         switch (isink) {
 300         case WM8350_ISINK_A:
 301                 reg = wm8350_reg_read(wm8350, WM8350_CSA_FLASH_CONTROL);
 302                 break;
 303         case WM8350_ISINK_B:
 304                 reg = wm8350_reg_read(wm8350, WM8350_CSB_FLASH_CONTROL);
 305                 break;
 306         default:
 307                 return -EINVAL;
 308         }
 309
 310         if (reg & WM8350_CS1_FLASH_MODE) {
 311                 switch (reg & WM8350_CS1_ON_RAMP_MASK) {
 312                 case 0:
 313                         return 0;
 314                 case 1:
 315                         return 1950;
 316                 case 2:
 317                         return 3910;
 318                 case 3:
 319                         return 7800;
 320                 }
 321         } else {
 322                 switch (reg & WM8350_CS1_ON_RAMP_MASK) {
 323                 case 0:
 324                         return 0;
 325                 case 1:
 326                         return 250000;
 327                 case 2:
 328                         return 500000;
 329                 case 3:
 330                         return 1000000;
 331                 }
 332         }
 333
 334         return -EINVAL;
 335 }
 336
 337
 338 int wm8350_isink_set_flash(struct wm8350 *wm8350, int isink, u16 mode,
 339                            u16 trigger, u16 duration, u16 on_ramp, u16 off_ramp,
 340                            u16 drive)
 341 {
 342         switch (isink) {
 343         case WM8350_ISINK_A:
 344                 wm8350_reg_write(wm8350, WM8350_CSA_FLASH_CONTROL,
 345                                  (mode ? WM8350_CS1_FLASH_MODE : 0) |
 346                                  (trigger ? WM8350_CS1_TRIGSRC : 0) |
 347                                  duration | on_ramp | off_ramp | drive);
 348                 break;
 349         case WM8350_ISINK_B:
 350                 wm8350_reg_write(wm8350, WM8350_CSB_FLASH_CONTROL,
 351                                  (mode ? WM8350_CS2_FLASH_MODE : 0) |
 352                                  (trigger ? WM8350_CS2_TRIGSRC : 0) |
 353                                  duration | on_ramp | off_ramp | drive);
 354                 break;
 355         default:
 356                 return -EINVAL;
 357         }
 358         return 0;
 359 }
 360 EXPORT_SYMBOL_GPL(wm8350_isink_set_flash);
 361
 362 static int wm8350_dcdc_set_voltage(struct regulator_dev *rdev, int min_uV,
 363                                    int max_uV, unsigned *selector)
 364 {
 365         struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
 366         int volt_reg, dcdc = rdev_get_id(rdev), mV,
 367                 min_mV = min_uV / 1000, max_mV = max_uV / 1000;
 368         u16 val;
 369
 370         if (min_mV < 850 || min_mV > 4025)
 371                 return -EINVAL;
 372         if (max_mV < 850 || max_mV > 4025)
 373                 return -EINVAL;
 374
 375         /* step size is 25mV */
 376         mV = (min_mV - 826) / 25;
 377         if (wm8350_dcdc_val_to_mvolts(mV) > max_mV)
 378                 return -EINVAL;
 379         BUG_ON(wm8350_dcdc_val_to_mvolts(mV) < min_mV);
 380
 381         switch (dcdc) {
 382         case WM8350_DCDC_1:
 383                 volt_reg = WM8350_DCDC1_CONTROL;
 384                 break;
 385         case WM8350_DCDC_3:
 386                 volt_reg = WM8350_DCDC3_CONTROL;
 387                 break;
 388         case WM8350_DCDC_4:
 389                 volt_reg = WM8350_DCDC4_CONTROL;
 390                 break;
 391         case WM8350_DCDC_6:
 392                 volt_reg = WM8350_DCDC6_CONTROL;
 393                 break;
 394         case WM8350_DCDC_2:
 395         case WM8350_DCDC_5:
 396         default:
 397                 return -EINVAL;
 398         }
 399
 400         *selector = mV;
 401
 402         /* all DCDCs have same mV bits */
 403         val = wm8350_reg_read(wm8350, volt_reg) & ~WM8350_DC1_VSEL_MASK;
 404         wm8350_reg_write(wm8350, volt_reg, val | mV);
 405         return 0;
 406 }
 407
 408 static int wm8350_dcdc_list_voltage(struct regulator_dev *rdev,
 409                                     unsigned selector)
 410 {
 411         if (selector > WM8350_DCDC_MAX_VSEL)
 412                 return -EINVAL;
 413         return wm8350_dcdc_val_to_mvolts(selector) * 1000;
 414 }
 415
 416 static int wm8350_dcdc_set_suspend_voltage(struct regulator_dev *rdev, int uV)
 417 {
 418         struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
 419         int volt_reg, mV = uV / 1000, dcdc = rdev_get_id(rdev);
 420         u16 val;
 421
 422         dev_dbg(wm8350->dev, "%s %d mV %d\n", __func__, dcdc, mV);
 423
 424         if (mV && (mV < 850 || mV > 4025)) {
 425                 dev_err(wm8350->dev,
 426                         "DCDC%d suspend voltage %d mV out of range\n",
 427                         dcdc, mV);
 428                 return -EINVAL;
 429         }
 430         if (mV == 0)
 431                 mV = 850;
 432
 433         switch (dcdc) {
 434         case WM8350_DCDC_1:
 435                 volt_reg = WM8350_DCDC1_LOW_POWER;
 436                 break;
 437         case WM8350_DCDC_3:
 438                 volt_reg = WM8350_DCDC3_LOW_POWER;
 439                 break;
 440         case WM8350_DCDC_4:
 441                 volt_reg = WM8350_DCDC4_LOW_POWER;
 442                 break;
 443         case WM8350_DCDC_6:
 444                 volt_reg = WM8350_DCDC6_LOW_POWER;
 445                 break;
 446         case WM8350_DCDC_2:
 447         case WM8350_DCDC_5:
 448         default:
 449                 return -EINVAL;
 450         }
 451
 452         /* all DCDCs have same mV bits */
 453         val = wm8350_reg_read(wm8350, volt_reg) & ~WM8350_DC1_VSEL_MASK;
 454         wm8350_reg_write(wm8350, volt_reg,
 455                          val | wm8350_dcdc_mvolts_to_val(mV));
 456         return 0;
 457 }
 458
 459 static int wm8350_dcdc_set_suspend_enable(struct regulator_dev *rdev)
 460 {
 461         struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
 462         int dcdc = rdev_get_id(rdev);
 463         u16 val;
 464
 465         switch (dcdc) {
 466         case WM8350_DCDC_1:
 467                 val = wm8350_reg_read(wm8350, WM8350_DCDC1_LOW_POWER)
 468                         & ~WM8350_DCDC_HIB_MODE_MASK;
 469                 wm8350_reg_write(wm8350, WM8350_DCDC1_LOW_POWER,
 470                         val | wm8350->pmic.dcdc1_hib_mode);
 471                 break;
 472         case WM8350_DCDC_3:
 473                 val = wm8350_reg_read(wm8350, WM8350_DCDC3_LOW_POWER)
 474                         & ~WM8350_DCDC_HIB_MODE_MASK;
 475                 wm8350_reg_write(wm8350, WM8350_DCDC3_LOW_POWER,
 476                         val | wm8350->pmic.dcdc3_hib_mode);
 477                 break;
 478         case WM8350_DCDC_4:
 479                 val = wm8350_reg_read(wm8350, WM8350_DCDC4_LOW_POWER)
 480                         & ~WM8350_DCDC_HIB_MODE_MASK;
 481                 wm8350_reg_write(wm8350, WM8350_DCDC4_LOW_POWER,
 482                         val | wm8350->pmic.dcdc4_hib_mode);
 483                 break;
 484         case WM8350_DCDC_6:
 485                 val = wm8350_reg_read(wm8350, WM8350_DCDC6_LOW_POWER)
 486                         & ~WM8350_DCDC_HIB_MODE_MASK;
 487                 wm8350_reg_write(wm8350, WM8350_DCDC6_LOW_POWER,
 488                         val | wm8350->pmic.dcdc6_hib_mode);
 489                 break;
 490         case WM8350_DCDC_2:
 491         case WM8350_DCDC_5:
 492         default:
 493                 return -EINVAL;
 494         }
 495
 496         return 0;
 497 }
 498
 499 static int wm8350_dcdc_set_suspend_disable(struct regulator_dev *rdev)
 500 {
 501         struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
 502         int dcdc = rdev_get_id(rdev);
 503         u16 val;
 504
 505         switch (dcdc) {
 506         case WM8350_DCDC_1:
 507                 val = wm8350_reg_read(wm8350, WM8350_DCDC1_LOW_POWER);
 508                 wm8350->pmic.dcdc1_hib_mode = val & WM8350_DCDC_HIB_MODE_MASK;
 509                 wm8350_reg_write(wm8350, WM8350_DCDC1_LOW_POWER,
 510                                  val | WM8350_DCDC_HIB_MODE_DIS);
 511                 break;
 512         case WM8350_DCDC_3:
 513                 val = wm8350_reg_read(wm8350, WM8350_DCDC3_LOW_POWER);
 514                 wm8350->pmic.dcdc3_hib_mode = val & WM8350_DCDC_HIB_MODE_MASK;
 515                 wm8350_reg_write(wm8350, WM8350_DCDC3_LOW_POWER,
 516                                  val | WM8350_DCDC_HIB_MODE_DIS);
 517                 break;
 518         case WM8350_DCDC_4:
 519                 val = wm8350_reg_read(wm8350, WM8350_DCDC4_LOW_POWER);
 520                 wm8350->pmic.dcdc4_hib_mode = val & WM8350_DCDC_HIB_MODE_MASK;
 521                 wm8350_reg_write(wm8350, WM8350_DCDC4_LOW_POWER,
 522                                  val | WM8350_DCDC_HIB_MODE_DIS);
 523                 break;
 524         case WM8350_DCDC_6:
 525                 val = wm8350_reg_read(wm8350, WM8350_DCDC6_LOW_POWER);
 526                 wm8350->pmic.dcdc6_hib_mode = val & WM8350_DCDC_HIB_MODE_MASK;
 527                 wm8350_reg_write(wm8350, WM8350_DCDC6_LOW_POWER,
 528                                  val | WM8350_DCDC_HIB_MODE_DIS);
 529                 break;
 530         case WM8350_DCDC_2:
 531         case WM8350_DCDC_5:
 532         default:
 533                 return -EINVAL;
 534         }
 535
 536         return 0;
 537 }
 538
 539 static int wm8350_dcdc25_set_suspend_enable(struct regulator_dev *rdev)
 540 {
 541         struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
 542         int dcdc = rdev_get_id(rdev);
 543         u16 val;
 544
 545         switch (dcdc) {
 546         case WM8350_DCDC_2:
 547                 val = wm8350_reg_read(wm8350, WM8350_DCDC2_CONTROL)
 548                     & ~WM8350_DC2_HIB_MODE_MASK;
 549                 wm8350_reg_write(wm8350, WM8350_DCDC2_CONTROL, val |
 550                     (WM8350_DC2_HIB_MODE_ACTIVE << WM8350_DC2_HIB_MODE_SHIFT));
 551                 break;
 552         case WM8350_DCDC_5:
 553                 val = wm8350_reg_read(wm8350, WM8350_DCDC5_CONTROL)
 554                     & ~WM8350_DC5_HIB_MODE_MASK;
 555                 wm8350_reg_write(wm8350, WM8350_DCDC5_CONTROL, val |
 556                     (WM8350_DC5_HIB_MODE_ACTIVE << WM8350_DC5_HIB_MODE_SHIFT));
 557                 break;
 558         default:
 559                 return -EINVAL;
 560         }
 561         return 0;
 562 }
 563
 564 static int wm8350_dcdc25_set_suspend_disable(struct regulator_dev *rdev)
 565 {
 566         struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
 567         int dcdc = rdev_get_id(rdev);
 568         u16 val;
 569
 570         switch (dcdc) {
 571         case WM8350_DCDC_2:
 572                 val = wm8350_reg_read(wm8350, WM8350_DCDC2_CONTROL)
 573                     & ~WM8350_DC2_HIB_MODE_MASK;
 574                 wm8350_reg_write(wm8350, WM8350_DCDC2_CONTROL, val |
 575                     (WM8350_DC2_HIB_MODE_DISABLE << WM8350_DC2_HIB_MODE_SHIFT));
 576                 break;
 577         case WM8350_DCDC_5:
 578                 val = wm8350_reg_read(wm8350, WM8350_DCDC5_CONTROL)
 579                     & ~WM8350_DC5_HIB_MODE_MASK;
 580                 wm8350_reg_write(wm8350, WM8350_DCDC5_CONTROL, val |
 581                     (WM8350_DC5_HIB_MODE_DISABLE << WM8350_DC5_HIB_MODE_SHIFT));
 582                 break;
 583         default:
 584                 return -EINVAL;
 585         }
 586         return 0;
 587 }
 588
 589 static int wm8350_dcdc_set_suspend_mode(struct regulator_dev *rdev,
 590         unsigned int mode)
 591 {
 592         struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
 593         int dcdc = rdev_get_id(rdev);
 594         u16 *hib_mode;
 595
 596         switch (dcdc) {
 597         case WM8350_DCDC_1:
 598                 hib_mode = &wm8350->pmic.dcdc1_hib_mode;
 599                 break;
 600         case WM8350_DCDC_3:
 601                 hib_mode = &wm8350->pmic.dcdc3_hib_mode;
 602                 break;
 603         case WM8350_DCDC_4:
 604                 hib_mode = &wm8350->pmic.dcdc4_hib_mode;
 605                 break;
 606         case WM8350_DCDC_6:
 607                 hib_mode = &wm8350->pmic.dcdc6_hib_mode;
 608                 break;
 609         case WM8350_DCDC_2:
 610         case WM8350_DCDC_5:
 611         default:
 612                 return -EINVAL;
 613         }
 614
 615         switch (mode) {
 616         case REGULATOR_MODE_NORMAL:
 617                 *hib_mode = WM8350_DCDC_HIB_MODE_IMAGE;
 618                 break;
 619         case REGULATOR_MODE_IDLE:
 620                 *hib_mode = WM8350_DCDC_HIB_MODE_STANDBY;
 621                 break;
 622         case REGULATOR_MODE_STANDBY:
 623                 *hib_mode = WM8350_DCDC_HIB_MODE_LDO_IM;
 624                 break;
 625         default:
 626                 return -EINVAL;
 627         }
 628
 629         return 0;
 630 }
 631
 632 static int wm8350_ldo_set_suspend_voltage(struct regulator_dev *rdev, int uV)
 633 {
 634         struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
 635         int volt_reg, mV = uV / 1000, ldo = rdev_get_id(rdev);
 636         u16 val;
 637
 638         dev_dbg(wm8350->dev, "%s %d mV %d\n", __func__, ldo, mV);
 639
 640         if (mV < 900 || mV > 3300) {
 641                 dev_err(wm8350->dev, "LDO%d voltage %d mV out of range\n",
 642                         ldo, mV);
 643                 return -EINVAL;
 644         }
 645
 646         switch (ldo) {
 647         case WM8350_LDO_1:
 648                 volt_reg = WM8350_LDO1_LOW_POWER;
 649                 break;
 650         case WM8350_LDO_2:
 651                 volt_reg = WM8350_LDO2_LOW_POWER;
 652                 break;
 653         case WM8350_LDO_3:
 654                 volt_reg = WM8350_LDO3_LOW_POWER;
 655                 break;
 656         case WM8350_LDO_4:
 657                 volt_reg = WM8350_LDO4_LOW_POWER;
 658                 break;
 659         default:
 660                 return -EINVAL;
 661         }
 662
 663         /* all LDOs have same mV bits */
 664         val = wm8350_reg_read(wm8350, volt_reg) & ~WM8350_LDO1_VSEL_MASK;
 665         wm8350_reg_write(wm8350, volt_reg,
 666                          val | wm8350_ldo_mvolts_to_val(mV));
 667         return 0;
 668 }
 669
 670 static int wm8350_ldo_set_suspend_enable(struct regulator_dev *rdev)
 671 {
 672         struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
 673         int volt_reg, ldo = rdev_get_id(rdev);
 674         u16 val;
 675
 676         switch (ldo) {
 677         case WM8350_LDO_1:
 678                 volt_reg = WM8350_LDO1_LOW_POWER;
 679                 break;
 680         case WM8350_LDO_2:
 681                 volt_reg = WM8350_LDO2_LOW_POWER;
 682                 break;
 683         case WM8350_LDO_3:
 684                 volt_reg = WM8350_LDO3_LOW_POWER;
 685                 break;
 686         case WM8350_LDO_4:
 687                 volt_reg = WM8350_LDO4_LOW_POWER;
 688                 break;
 689         default:
 690                 return -EINVAL;
 691         }
 692
 693         /* all LDOs have same mV bits */
 694         val = wm8350_reg_read(wm8350, volt_reg) & ~WM8350_LDO1_HIB_MODE_MASK;
 695         wm8350_reg_write(wm8350, volt_reg, val);
 696         return 0;
 697 }
 698
 699 static int wm8350_ldo_set_suspend_disable(struct regulator_dev *rdev)
 700 {
 701         struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
 702         int volt_reg, ldo = rdev_get_id(rdev);
 703         u16 val;
 704
 705         switch (ldo) {
 706         case WM8350_LDO_1:
 707                 volt_reg = WM8350_LDO1_LOW_POWER;
 708                 break;
 709         case WM8350_LDO_2:
 710                 volt_reg = WM8350_LDO2_LOW_POWER;
 711                 break;
 712         case WM8350_LDO_3:
 713                 volt_reg = WM8350_LDO3_LOW_POWER;
 714                 break;
 715         case WM8350_LDO_4:
 716                 volt_reg = WM8350_LDO4_LOW_POWER;
 717                 break;
 718         default:
 719                 return -EINVAL;
 720         }
 721
 722         /* all LDOs have same mV bits */
 723         val = wm8350_reg_read(wm8350, volt_reg) & ~WM8350_LDO1_HIB_MODE_MASK;
 724         wm8350_reg_write(wm8350, volt_reg, val | WM8350_LDO1_HIB_MODE_DIS);
 725         return 0;
 726 }
 727
 728 static int wm8350_ldo_set_voltage(struct regulator_dev *rdev, int min_uV,
 729                                   int max_uV, unsigned *selector)
 730 {
 731         struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
 732         int volt_reg, ldo = rdev_get_id(rdev), mV, min_mV = min_uV / 1000,
 733                 max_mV = max_uV / 1000;
 734         u16 val;
 735
 736         if (min_mV < 900 || min_mV > 3300)
 737                 return -EINVAL;
 738         if (max_mV < 900 || max_mV > 3300)
 739                 return -EINVAL;
 740
 741         if (min_mV < 1800) {
 742                 /* step size is 50mV < 1800mV */
 743                 mV = (min_mV - 851) / 50;
 744                 if (wm8350_ldo_val_to_mvolts(mV) > max_mV)
 745                         return -EINVAL;
 746                 BUG_ON(wm8350_ldo_val_to_mvolts(mV) < min_mV);
 747         } else {
 748                 /* step size is 100mV > 1800mV */
 749                 mV = ((min_mV - 1701) / 100) + 16;
 750                 if (wm8350_ldo_val_to_mvolts(mV) > max_mV)
 751                         return -EINVAL;
 752                 BUG_ON(wm8350_ldo_val_to_mvolts(mV) < min_mV);
 753         }
 754
 755         switch (ldo) {
 756         case WM8350_LDO_1:
 757                 volt_reg = WM8350_LDO1_CONTROL;
 758                 break;
 759         case WM8350_LDO_2:
 760                 volt_reg = WM8350_LDO2_CONTROL;
 761                 break;
 762         case WM8350_LDO_3:
 763                 volt_reg = WM8350_LDO3_CONTROL;
 764                 break;
 765         case WM8350_LDO_4:
 766                 volt_reg = WM8350_LDO4_CONTROL;
 767                 break;
 768         default:
 769                 return -EINVAL;
 770         }
 771
 772         *selector = mV;
 773
 774         /* all LDOs have same mV bits */
 775         val = wm8350_reg_read(wm8350, volt_reg) & ~WM8350_LDO1_VSEL_MASK;
 776         wm8350_reg_write(wm8350, volt_reg, val | mV);
 777         return 0;
 778 }
 779
 780 static int wm8350_ldo_list_voltage(struct regulator_dev *rdev,
 781                                     unsigned selector)
 782 {
 783         if (selector > WM8350_LDO1_VSEL_MASK)
 784                 return -EINVAL;
 785         return wm8350_ldo_val_to_mvolts(selector) * 1000;
 786 }
 787
 788 int wm8350_dcdc_set_slot(struct wm8350 *wm8350, int dcdc, u16 start,
 789                          u16 stop, u16 fault)
 790 {
 791         int slot_reg;
 792         u16 val;
 793
 794         dev_dbg(wm8350->dev, "%s %d start %d stop %d\n",
 795                 __func__, dcdc, start, stop);
 796
 797         /* slot valid ? */
 798         if (start > 15 || stop > 15)
 799                 return -EINVAL;
 800
 801         switch (dcdc) {
 802         case WM8350_DCDC_1:
 803                 slot_reg = WM8350_DCDC1_TIMEOUTS;
 804                 break;
 805         case WM8350_DCDC_2:
 806                 slot_reg = WM8350_DCDC2_TIMEOUTS;
 807                 break;
 808         case WM8350_DCDC_3:
 809                 slot_reg = WM8350_DCDC3_TIMEOUTS;
 810                 break;
 811         case WM8350_DCDC_4:
 812                 slot_reg = WM8350_DCDC4_TIMEOUTS;
 813                 break;
 814         case WM8350_DCDC_5:
 815                 slot_reg = WM8350_DCDC5_TIMEOUTS;
 816                 break;
 817         case WM8350_DCDC_6:
 818                 slot_reg = WM8350_DCDC6_TIMEOUTS;
 819                 break;
 820         default:
 821                 return -EINVAL;
 822         }
 823
 824         val = wm8350_reg_read(wm8350, slot_reg) &
 825             ~(WM8350_DC1_ENSLOT_MASK | WM8350_DC1_SDSLOT_MASK |
 826               WM8350_DC1_ERRACT_MASK);
 827         wm8350_reg_write(wm8350, slot_reg,
 828                          val | (start << WM8350_DC1_ENSLOT_SHIFT) |
 829                          (stop << WM8350_DC1_SDSLOT_SHIFT) |
 830                          (fault << WM8350_DC1_ERRACT_SHIFT));
 831
 832         return 0;
 833 }
 834 EXPORT_SYMBOL_GPL(wm8350_dcdc_set_slot);
 835
 836 int wm8350_ldo_set_slot(struct wm8350 *wm8350, int ldo, u16 start, u16 stop)
 837 {
 838         int slot_reg;
 839         u16 val;
 840
 841         dev_dbg(wm8350->dev, "%s %d start %d stop %d\n",
 842                 __func__, ldo, start, stop);
 843
 844         /* slot valid ? */
 845         if (start > 15 || stop > 15)
 846                 return -EINVAL;
 847
 848         switch (ldo) {
 849         case WM8350_LDO_1:
 850                 slot_reg = WM8350_LDO1_TIMEOUTS;
 851                 break;
 852         case WM8350_LDO_2:
 853                 slot_reg = WM8350_LDO2_TIMEOUTS;
 854                 break;
 855         case WM8350_LDO_3:
 856                 slot_reg = WM8350_LDO3_TIMEOUTS;
 857                 break;
 858         case WM8350_LDO_4:
 859                 slot_reg = WM8350_LDO4_TIMEOUTS;
 860                 break;
 861         default:
 862                 return -EINVAL;
 863         }
 864
 865         val = wm8350_reg_read(wm8350, slot_reg) & ~WM8350_LDO1_SDSLOT_MASK;
 866         wm8350_reg_write(wm8350, slot_reg, val | ((start << 10) | (stop << 6)));
 867         return 0;
 868 }
 869 EXPORT_SYMBOL_GPL(wm8350_ldo_set_slot);
 870
 871 int wm8350_dcdc25_set_mode(struct wm8350 *wm8350, int dcdc, u16 mode,
 872                            u16 ilim, u16 ramp, u16 feedback)
 873 {
 874         u16 val;
 875
 876         dev_dbg(wm8350->dev, "%s %d mode: %s %s\n", __func__, dcdc,
 877                 mode ? "normal" : "boost", ilim ? "low" : "normal");
 878
 879         switch (dcdc) {
 880         case WM8350_DCDC_2:
 881                 val = wm8350_reg_read(wm8350, WM8350_DCDC2_CONTROL)
 882                     & ~(WM8350_DC2_MODE_MASK | WM8350_DC2_ILIM_MASK |
 883                         WM8350_DC2_RMP_MASK | WM8350_DC2_FBSRC_MASK);
 884                 wm8350_reg_write(wm8350, WM8350_DCDC2_CONTROL, val |
 885                                  (mode << WM8350_DC2_MODE_SHIFT) |
 886                                  (ilim << WM8350_DC2_ILIM_SHIFT) |
 887                                  (ramp << WM8350_DC2_RMP_SHIFT) |
 888                                  (feedback << WM8350_DC2_FBSRC_SHIFT));
 889                 break;
 890         case WM8350_DCDC_5:
 891                 val = wm8350_reg_read(wm8350, WM8350_DCDC5_CONTROL)
 892                     & ~(WM8350_DC5_MODE_MASK | WM8350_DC5_ILIM_MASK |
 893                         WM8350_DC5_RMP_MASK | WM8350_DC5_FBSRC_MASK);
 894                 wm8350_reg_write(wm8350, WM8350_DCDC5_CONTROL, val |
 895                                  (mode << WM8350_DC5_MODE_SHIFT) |
 896                                  (ilim << WM8350_DC5_ILIM_SHIFT) |
 897                                  (ramp << WM8350_DC5_RMP_SHIFT) |
 898                                  (feedback << WM8350_DC5_FBSRC_SHIFT));
 899                 break;
 900         default:
 901                 return -EINVAL;
 902         }
 903
 904         return 0;
 905 }
 906 EXPORT_SYMBOL_GPL(wm8350_dcdc25_set_mode);
 907
 908 static int force_continuous_enable(struct wm8350 *wm8350, int dcdc, int enable)
 909 {
 910         int reg = 0, ret;
 911
 912         switch (dcdc) {
 913         case WM8350_DCDC_1:
 914                 reg = WM8350_DCDC1_FORCE_PWM;
 915                 break;
 916         case WM8350_DCDC_3:
 917                 reg = WM8350_DCDC3_FORCE_PWM;
 918                 break;
 919         case WM8350_DCDC_4:
 920                 reg = WM8350_DCDC4_FORCE_PWM;
 921                 break;
 922         case WM8350_DCDC_6:
 923                 reg = WM8350_DCDC6_FORCE_PWM;
 924                 break;
 925         default:
 926                 return -EINVAL;
 927         }
 928
 929         if (enable)
 930                 ret = wm8350_set_bits(wm8350, reg,
 931                         WM8350_DCDC1_FORCE_PWM_ENA);
 932         else
 933                 ret = wm8350_clear_bits(wm8350, reg,
 934                         WM8350_DCDC1_FORCE_PWM_ENA);
 935         return ret;
 936 }
 937
 938 static int wm8350_dcdc_set_mode(struct regulator_dev *rdev, unsigned int mode)
 939 {
 940         struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
 941         int dcdc = rdev_get_id(rdev);
 942         u16 val;
 943
 944         if (dcdc < WM8350_DCDC_1 || dcdc > WM8350_DCDC_6)
 945                 return -EINVAL;
 946
 947         if (dcdc == WM8350_DCDC_2 || dcdc == WM8350_DCDC_5)
 948                 return -EINVAL;
 949
 950         val = 1 << (dcdc - WM8350_DCDC_1);
 951
 952         switch (mode) {
 953         case REGULATOR_MODE_FAST:
 954                 /* force continuous mode */
 955                 wm8350_set_bits(wm8350, WM8350_DCDC_ACTIVE_OPTIONS, val);
 956                 wm8350_clear_bits(wm8350, WM8350_DCDC_SLEEP_OPTIONS, val);
 957                 force_continuous_enable(wm8350, dcdc, 1);
 958                 break;
 959         case REGULATOR_MODE_NORMAL:
 960                 /* active / pulse skipping */
 961                 wm8350_set_bits(wm8350, WM8350_DCDC_ACTIVE_OPTIONS, val);
 962                 wm8350_clear_bits(wm8350, WM8350_DCDC_SLEEP_OPTIONS, val);
 963                 force_continuous_enable(wm8350, dcdc, 0);
 964                 break;
 965         case REGULATOR_MODE_IDLE:
 966                 /* standby mode */
 967                 force_continuous_enable(wm8350, dcdc, 0);
 968                 wm8350_clear_bits(wm8350, WM8350_DCDC_SLEEP_OPTIONS, val);
 969                 wm8350_clear_bits(wm8350, WM8350_DCDC_ACTIVE_OPTIONS, val);
 970                 break;
 971         case REGULATOR_MODE_STANDBY:
 972                 /* LDO mode */
 973                 force_continuous_enable(wm8350, dcdc, 0);
 974                 wm8350_set_bits(wm8350, WM8350_DCDC_SLEEP_OPTIONS, val);
 975                 break;
 976         }
 977
 978         return 0;
 979 }
 980
 981 static unsigned int wm8350_dcdc_get_mode(struct regulator_dev *rdev)
 982 {
 983         struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
 984         int dcdc = rdev_get_id(rdev);
 985         u16 mask, sleep, active, force;
 986         int mode = REGULATOR_MODE_NORMAL;
 987         int reg;
 988
 989         switch (dcdc) {
 990         case WM8350_DCDC_1:
 991                 reg = WM8350_DCDC1_FORCE_PWM;
 992                 break;
 993         case WM8350_DCDC_3:
 994                 reg = WM8350_DCDC3_FORCE_PWM;
 995                 break;
 996         case WM8350_DCDC_4:
 997                 reg = WM8350_DCDC4_FORCE_PWM;
 998                 break;
 999         case WM8350_DCDC_6:
1000                 reg = WM8350_DCDC6_FORCE_PWM;
1001                 break;
1002         default:
1003                 return -EINVAL;
1004         }
1005
1006         mask = 1 << (dcdc - WM8350_DCDC_1);
1007         active = wm8350_reg_read(wm8350, WM8350_DCDC_ACTIVE_OPTIONS) & mask;
1008         force = wm8350_reg_read(wm8350, reg) & WM8350_DCDC1_FORCE_PWM_ENA;
1009         sleep = wm8350_reg_read(wm8350, WM8350_DCDC_SLEEP_OPTIONS) & mask;
1010
1011         dev_dbg(wm8350->dev, "mask %x active %x sleep %x force %x",
1012                 mask, active, sleep, force);
1013
1014         if (active && !sleep) {
1015                 if (force)
1016                         mode = REGULATOR_MODE_FAST;
1017                 else
1018                         mode = REGULATOR_MODE_NORMAL;
1019         } else if (!active && !sleep)
1020                 mode = REGULATOR_MODE_IDLE;
1021         else if (sleep)
1022                 mode = REGULATOR_MODE_STANDBY;
1023
1024         return mode;
1025 }
1026
1027 static unsigned int wm8350_ldo_get_mode(struct regulator_dev *rdev)
1028 {
1029         return REGULATOR_MODE_NORMAL;
1030 }
1031
1032 struct wm8350_dcdc_efficiency {
1033         int uA_load_min;
1034         int uA_load_max;
1035         unsigned int mode;
1036 };
1037
1038 static const struct wm8350_dcdc_efficiency dcdc1_6_efficiency[] = {
1039         {0, 10000, REGULATOR_MODE_STANDBY},       /* 0 - 10mA - LDO */
1040         {10000, 100000, REGULATOR_MODE_IDLE},     /* 10mA - 100mA - Standby */
1041         {100000, 1000000, REGULATOR_MODE_NORMAL}, /* > 100mA - Active */
1042         {-1, -1, REGULATOR_MODE_NORMAL},
1043 };
1044
1045 static const struct wm8350_dcdc_efficiency dcdc3_4_efficiency[] = {
1046         {0, 10000, REGULATOR_MODE_STANDBY},      /* 0 - 10mA - LDO */
1047         {10000, 100000, REGULATOR_MODE_IDLE},    /* 10mA - 100mA - Standby */
1048         {100000, 800000, REGULATOR_MODE_NORMAL}, /* > 100mA - Active */
1049         {-1, -1, REGULATOR_MODE_NORMAL},
1050 };
1051
1052 static unsigned int get_mode(int uA, const struct wm8350_dcdc_efficiency *eff)
1053 {
1054         int i = 0;
1055
1056         while (eff[i].uA_load_min != -1) {
1057                 if (uA >= eff[i].uA_load_min && uA <= eff[i].uA_load_max)
1058                         return eff[i].mode;
1059         }
1060         return REGULATOR_MODE_NORMAL;
1061 }
1062
1063 /* Query the regulator for it's most efficient mode @ uV,uA
1064  * WM8350 regulator efficiency is pretty similar over
1065  * different input and output uV.
1066  */
1067 static unsigned int wm8350_dcdc_get_optimum_mode(struct regulator_dev *rdev,
1068                                                  int input_uV, int output_uV,
1069                                                  int output_uA)
1070 {
1071         int dcdc = rdev_get_id(rdev), mode;
1072
1073         switch (dcdc) {
1074         case WM8350_DCDC_1:
1075         case WM8350_DCDC_6:
1076                 mode = get_mode(output_uA, dcdc1_6_efficiency);
1077                 break;
1078         case WM8350_DCDC_3:
1079         case WM8350_DCDC_4:
1080                 mode = get_mode(output_uA, dcdc3_4_efficiency);
1081                 break;
1082         default:
1083                 mode = REGULATOR_MODE_NORMAL;
1084                 break;
1085         }
1086         return mode;
1087 }
1088
1089 static struct regulator_ops wm8350_dcdc_ops = {
1090         .set_voltage = wm8350_dcdc_set_voltage,
1091         .get_voltage_sel = regulator_get_voltage_sel_regmap,
1092         .list_voltage = wm8350_dcdc_list_voltage,
1093         .enable = regulator_enable_regmap,
1094         .disable = regulator_disable_regmap,
1095         .is_enabled = regulator_is_enabled_regmap,
1096         .get_mode = wm8350_dcdc_get_mode,
1097         .set_mode = wm8350_dcdc_set_mode,
1098         .get_optimum_mode = wm8350_dcdc_get_optimum_mode,
1099         .set_suspend_voltage = wm8350_dcdc_set_suspend_voltage,
1100         .set_suspend_enable = wm8350_dcdc_set_suspend_enable,
1101         .set_suspend_disable = wm8350_dcdc_set_suspend_disable,
1102         .set_suspend_mode = wm8350_dcdc_set_suspend_mode,
1103 };
1104
1105 static struct regulator_ops wm8350_dcdc2_5_ops = {
1106         .enable = regulator_enable_regmap,
1107         .disable = regulator_disable_regmap,
1108         .is_enabled = regulator_is_enabled_regmap,
1109         .set_suspend_enable = wm8350_dcdc25_set_suspend_enable,
1110         .set_suspend_disable = wm8350_dcdc25_set_suspend_disable,
1111 };
1112
1113 static struct regulator_ops wm8350_ldo_ops = {
1114         .set_voltage = wm8350_ldo_set_voltage,
1115         .get_voltage_sel = regulator_get_voltage_sel_regmap,
1116         .list_voltage = wm8350_ldo_list_voltage,
1117         .enable = regulator_enable_regmap,
1118         .disable = regulator_disable_regmap,
1119         .is_enabled = regulator_is_enabled_regmap,
1120         .get_mode = wm8350_ldo_get_mode,
1121         .set_suspend_voltage = wm8350_ldo_set_suspend_voltage,
1122         .set_suspend_enable = wm8350_ldo_set_suspend_enable,
1123         .set_suspend_disable = wm8350_ldo_set_suspend_disable,
1124 };
1125
1126 static struct regulator_ops wm8350_isink_ops = {
1127         .set_current_limit = wm8350_isink_set_current,
1128         .get_current_limit = wm8350_isink_get_current,
1129         .enable = wm8350_isink_enable,
1130         .disable = wm8350_isink_disable,
1131         .is_enabled = wm8350_isink_is_enabled,
1132         .enable_time = wm8350_isink_enable_time,
1133 };
1134
1135 static const struct regulator_desc wm8350_reg[NUM_WM8350_REGULATORS] = {
1136         {
1137                 .name = "DCDC1",
1138                 .id = WM8350_DCDC_1,
1139                 .ops = &wm8350_dcdc_ops,
1140                 .irq = WM8350_IRQ_UV_DC1,
1141                 .type = REGULATOR_VOLTAGE,
1142                 .n_voltages = WM8350_DCDC_MAX_VSEL + 1,
1143                 .vsel_reg = WM8350_DCDC1_CONTROL,
1144                 .vsel_mask = WM8350_DC1_VSEL_MASK,
1145                 .enable_reg = WM8350_DCDC_LDO_REQUESTED,
1146                 .enable_mask = WM8350_DC1_ENA,
1147                 .owner = THIS_MODULE,
1148         },
1149         {
1150                 .name = "DCDC2",
1151                 .id = WM8350_DCDC_2,
1152                 .ops = &wm8350_dcdc2_5_ops,
1153                 .irq = WM8350_IRQ_UV_DC2,
1154                 .type = REGULATOR_VOLTAGE,
1155                 .enable_reg = WM8350_DCDC_LDO_REQUESTED,
1156                 .enable_mask = WM8350_DC2_ENA,
1157                 .owner = THIS_MODULE,
1158         },
1159         {
1160                 .name = "DCDC3",
1161                 .id = WM8350_DCDC_3,
1162                 .ops = &wm8350_dcdc_ops,
1163                 .irq = WM8350_IRQ_UV_DC3,
1164                 .type = REGULATOR_VOLTAGE,
1165                 .n_voltages = WM8350_DCDC_MAX_VSEL + 1,
1166                 .vsel_reg = WM8350_DCDC3_CONTROL,
1167                 .vsel_mask = WM8350_DC3_VSEL_MASK,
1168                 .enable_reg = WM8350_DCDC_LDO_REQUESTED,
1169                 .enable_mask = WM8350_DC3_ENA,
1170                 .owner = THIS_MODULE,
1171         },
1172         {
1173                 .name = "DCDC4",
1174                 .id = WM8350_DCDC_4,
1175                 .ops = &wm8350_dcdc_ops,
1176                 .irq = WM8350_IRQ_UV_DC4,
1177                 .type = REGULATOR_VOLTAGE,
1178                 .n_voltages = WM8350_DCDC_MAX_VSEL + 1,
1179                 .vsel_reg = WM8350_DCDC4_CONTROL,
1180                 .vsel_mask = WM8350_DC4_VSEL_MASK,
1181                 .enable_reg = WM8350_DCDC_LDO_REQUESTED,
1182                 .enable_mask = WM8350_DC4_ENA,
1183                 .owner = THIS_MODULE,
1184         },
1185         {
1186                 .name = "DCDC5",
1187                 .id = WM8350_DCDC_5,
1188                 .ops = &wm8350_dcdc2_5_ops,
1189                 .irq = WM8350_IRQ_UV_DC5,
1190                 .type = REGULATOR_VOLTAGE,
1191                 .enable_reg = WM8350_DCDC_LDO_REQUESTED,
1192                 .enable_mask = WM8350_DC5_ENA,
1193                 .owner = THIS_MODULE,
1194          },
1195         {
1196                 .name = "DCDC6",
1197                 .id = WM8350_DCDC_6,
1198                 .ops = &wm8350_dcdc_ops,
1199                 .irq = WM8350_IRQ_UV_DC6,
1200                 .type = REGULATOR_VOLTAGE,
1201                 .n_voltages = WM8350_DCDC_MAX_VSEL + 1,
1202                 .vsel_reg = WM8350_DCDC6_CONTROL,
1203                 .vsel_mask = WM8350_DC6_VSEL_MASK,
1204                 .enable_reg = WM8350_DCDC_LDO_REQUESTED,
1205                 .enable_mask = WM8350_DC6_ENA,
1206                 .owner = THIS_MODULE,
1207         },
1208         {
1209                 .name = "LDO1",
1210                 .id = WM8350_LDO_1,
1211                 .ops = &wm8350_ldo_ops,
1212                 .irq = WM8350_IRQ_UV_LDO1,
1213                 .type = REGULATOR_VOLTAGE,
1214                 .n_voltages = WM8350_LDO1_VSEL_MASK + 1,
1215                 .vsel_reg = WM8350_LDO1_CONTROL,
1216                 .vsel_mask = WM8350_LDO1_VSEL_MASK,
1217                 .enable_reg = WM8350_DCDC_LDO_REQUESTED,
1218                 .enable_mask = WM8350_LDO1_ENA,
1219                 .owner = THIS_MODULE,
1220         },
1221         {
1222                 .name = "LDO2",
1223                 .id = WM8350_LDO_2,
1224                 .ops = &wm8350_ldo_ops,
1225                 .irq = WM8350_IRQ_UV_LDO2,
1226                 .type = REGULATOR_VOLTAGE,
1227                 .n_voltages = WM8350_LDO2_VSEL_MASK + 1,
1228                 .vsel_reg = WM8350_LDO2_CONTROL,
1229                 .vsel_mask = WM8350_LDO2_VSEL_MASK,
1230                 .enable_reg = WM8350_DCDC_LDO_REQUESTED,
1231                 .enable_mask = WM8350_LDO2_ENA,
1232                 .owner = THIS_MODULE,
1233         },
1234         {
1235                 .name = "LDO3",
1236                 .id = WM8350_LDO_3,
1237                 .ops = &wm8350_ldo_ops,
1238                 .irq = WM8350_IRQ_UV_LDO3,
1239                 .type = REGULATOR_VOLTAGE,
1240                 .n_voltages = WM8350_LDO3_VSEL_MASK + 1,
1241                 .vsel_reg = WM8350_LDO3_CONTROL,
1242                 .vsel_mask = WM8350_LDO3_VSEL_MASK,
1243                 .enable_reg = WM8350_DCDC_LDO_REQUESTED,
1244                 .enable_mask = WM8350_LDO3_ENA,
1245                 .owner = THIS_MODULE,
1246         },
1247         {
1248                 .name = "LDO4",
1249                 .id = WM8350_LDO_4,
1250                 .ops = &wm8350_ldo_ops,
1251                 .irq = WM8350_IRQ_UV_LDO4,
1252                 .type = REGULATOR_VOLTAGE,
1253                 .n_voltages = WM8350_LDO4_VSEL_MASK + 1,
1254                 .vsel_reg = WM8350_LDO4_CONTROL,
1255                 .vsel_mask = WM8350_LDO4_VSEL_MASK,
1256                 .enable_reg = WM8350_DCDC_LDO_REQUESTED,
1257                 .enable_mask = WM8350_LDO4_ENA,
1258                 .owner = THIS_MODULE,
1259         },
1260         {
1261                 .name = "ISINKA",
1262                 .id = WM8350_ISINK_A,
1263                 .ops = &wm8350_isink_ops,
1264                 .irq = WM8350_IRQ_CS1,
1265                 .type = REGULATOR_CURRENT,
1266                 .owner = THIS_MODULE,
1267          },
1268         {
1269                 .name = "ISINKB",
1270                 .id = WM8350_ISINK_B,
1271                 .ops = &wm8350_isink_ops,
1272                 .irq = WM8350_IRQ_CS2,
1273                 .type = REGULATOR_CURRENT,
1274                 .owner = THIS_MODULE,
1275          },
1276 };
1277
1278 static irqreturn_t pmic_uv_handler(int irq, void *data)
1279 {
1280         struct regulator_dev *rdev = (struct regulator_dev *)data;
1281         struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
1282
1283         mutex_lock(&rdev->mutex);
1284         if (irq == WM8350_IRQ_CS1 || irq == WM8350_IRQ_CS2)
1285                 regulator_notifier_call_chain(rdev,
1286                                               REGULATOR_EVENT_REGULATION_OUT,
1287                                               wm8350);
1288         else
1289                 regulator_notifier_call_chain(rdev,
1290                                               REGULATOR_EVENT_UNDER_VOLTAGE,
1291                                               wm8350);
1292         mutex_unlock(&rdev->mutex);
1293
1294         return IRQ_HANDLED;
1295 }
1296
1297 static int wm8350_regulator_probe(struct platform_device *pdev)
1298 {
1299         struct wm8350 *wm8350 = dev_get_drvdata(&pdev->dev);
1300         struct regulator_config config = { };
1301         struct regulator_dev *rdev;
1302         int ret;
1303         u16 val;
1304
1305         if (pdev->id < WM8350_DCDC_1 || pdev->id > WM8350_ISINK_B)
1306                 return -ENODEV;
1307
1308         /* do any regulatior specific init */
1309         switch (pdev->id) {
1310         case WM8350_DCDC_1:
1311                 val = wm8350_reg_read(wm8350, WM8350_DCDC1_LOW_POWER);
1312                 wm8350->pmic.dcdc1_hib_mode = val & WM8350_DCDC_HIB_MODE_MASK;
1313                 break;
1314         case WM8350_DCDC_3:
1315                 val = wm8350_reg_read(wm8350, WM8350_DCDC3_LOW_POWER);
1316                 wm8350->pmic.dcdc3_hib_mode = val & WM8350_DCDC_HIB_MODE_MASK;
1317                 break;
1318         case WM8350_DCDC_4:
1319                 val = wm8350_reg_read(wm8350, WM8350_DCDC4_LOW_POWER);
1320                 wm8350->pmic.dcdc4_hib_mode = val & WM8350_DCDC_HIB_MODE_MASK;
1321                 break;
1322         case WM8350_DCDC_6:
1323                 val = wm8350_reg_read(wm8350, WM8350_DCDC6_LOW_POWER);
1324                 wm8350->pmic.dcdc6_hib_mode = val & WM8350_DCDC_HIB_MODE_MASK;
1325                 break;
1326         }
1327
1328         config.dev = &pdev->dev;
1329         config.init_data = pdev->dev.platform_data;
1330         config.driver_data = dev_get_drvdata(&pdev->dev);
1331         config.regmap = wm8350->regmap;
1332
1333         /* register regulator */
1334         rdev = regulator_register(&wm8350_reg[pdev->id], &config);
1335         if (IS_ERR(rdev)) {
1336                 dev_err(&pdev->dev, "failed to register %s\n",
1337                         wm8350_reg[pdev->id].name);
1338                 return PTR_ERR(rdev);
1339         }
1340
1341         /* register regulator IRQ */
1342         ret = wm8350_register_irq(wm8350, wm8350_reg[pdev->id].irq,
1343                                   pmic_uv_handler, 0, "UV", rdev);
1344         if (ret < 0) {
1345                 regulator_unregister(rdev);
1346                 dev_err(&pdev->dev, "failed to register regulator %s IRQ\n",
1347                         wm8350_reg[pdev->id].name);
1348                 return ret;
1349         }
1350
1351         return 0;
1352 }
1353
1354 static int wm8350_regulator_remove(struct platform_device *pdev)
1355 {
1356         struct regulator_dev *rdev = platform_get_drvdata(pdev);
1357         struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
1358
1359         wm8350_free_irq(wm8350, wm8350_reg[pdev->id].irq, rdev);
1360
1361         regulator_unregister(rdev);
1362
1363         return 0;
1364 }
1365
1366 int wm8350_register_regulator(struct wm8350 *wm8350, int reg,
1367                               struct regulator_init_data *initdata)
1368 {
1369         struct platform_device *pdev;
1370         int ret;
1371         if (reg < 0 || reg >= NUM_WM8350_REGULATORS)
1372                 return -EINVAL;
1373
1374         if (wm8350->pmic.pdev[reg])
1375                 return -EBUSY;
1376
1377         if (reg >= WM8350_DCDC_1 && reg <= WM8350_DCDC_6 &&
1378             reg > wm8350->pmic.max_dcdc)
1379                 return -ENODEV;
1380         if (reg >= WM8350_ISINK_A && reg <= WM8350_ISINK_B &&
1381             reg > wm8350->pmic.max_isink)
1382                 return -ENODEV;
1383
1384         pdev = platform_device_alloc("wm8350-regulator", reg);
1385         if (!pdev)
1386                 return -ENOMEM;
1387
1388         wm8350->pmic.pdev[reg] = pdev;
1389
1390         initdata->driver_data = wm8350;
1391
1392         pdev->dev.platform_data = initdata;
1393         pdev->dev.parent = wm8350->dev;
1394         platform_set_drvdata(pdev, wm8350);
1395
1396         ret = platform_device_add(pdev);
1397
1398         if (ret != 0) {
1399                 dev_err(wm8350->dev, "Failed to register regulator %d: %d\n",
1400                         reg, ret);
1401                 platform_device_put(pdev);
1402                 wm8350->pmic.pdev[reg] = NULL;
1403         }
1404
1405         return ret;
1406 }
1407 EXPORT_SYMBOL_GPL(wm8350_register_regulator);
1408
1409 /**
1410  * wm8350_register_led - Register a WM8350 LED output
1411  *
1412  * @param wm8350 The WM8350 device to configure.
1413  * @param lednum LED device index to create.
1414  * @param dcdc The DCDC to use for the LED.
1415  * @param isink The ISINK to use for the LED.
1416  * @param pdata Configuration for the LED.
1417  *
1418  * The WM8350 supports the use of an ISINK together with a DCDC to
1419  * provide a power-efficient LED driver.  This function registers the
1420  * regulators and instantiates the platform device for a LED.  The
1421  * operating modes for the LED regulators must be configured using
1422  * wm8350_isink_set_flash(), wm8350_dcdc25_set_mode() and
1423  * wm8350_dcdc_set_slot() prior to calling this function.
1424  */
1425 int wm8350_register_led(struct wm8350 *wm8350, int lednum, int dcdc, int isink,
1426                         struct wm8350_led_platform_data *pdata)
1427 {
1428         struct wm8350_led *led;
1429         struct platform_device *pdev;
1430         int ret;
1431
1432         if (lednum >= ARRAY_SIZE(wm8350->pmic.led) || lednum < 0) {
1433                 dev_err(wm8350->dev, "Invalid LED index %d\n", lednum);
1434                 return -ENODEV;
1435         }
1436
1437         led = &wm8350->pmic.led[lednum];
1438
1439         if (led->pdev) {
1440                 dev_err(wm8350->dev, "LED %d already allocated\n", lednum);
1441                 return -EINVAL;
1442         }
1443
1444         pdev = platform_device_alloc("wm8350-led", lednum);
1445         if (pdev == NULL) {
1446                 dev_err(wm8350->dev, "Failed to allocate LED %d\n", lednum);
1447                 return -ENOMEM;
1448         }
1449
1450         led->isink_consumer.dev_name = dev_name(&pdev->dev);
1451         led->isink_consumer.supply = "led_isink";
1452         led->isink_init.num_consumer_supplies = 1;
1453         led->isink_init.consumer_supplies = &led->isink_consumer;
1454         led->isink_init.constraints.min_uA = 0;
1455         led->isink_init.constraints.max_uA = pdata->max_uA;
1456         led->isink_init.constraints.valid_ops_mask
1457                 = REGULATOR_CHANGE_CURRENT | REGULATOR_CHANGE_STATUS;
1458         led->isink_init.constraints.valid_modes_mask = REGULATOR_MODE_NORMAL;
1459         ret = wm8350_register_regulator(wm8350, isink, &led->isink_init);
1460         if (ret != 0) {
1461                 platform_device_put(pdev);
1462                 return ret;
1463         }
1464
1465         led->dcdc_consumer.dev_name = dev_name(&pdev->dev);
1466         led->dcdc_consumer.supply = "led_vcc";
1467         led->dcdc_init.num_consumer_supplies = 1;
1468         led->dcdc_init.consumer_supplies = &led->dcdc_consumer;
1469         led->dcdc_init.constraints.valid_modes_mask = REGULATOR_MODE_NORMAL;
1470         led->dcdc_init.constraints.valid_ops_mask =  REGULATOR_CHANGE_STATUS;
1471         ret = wm8350_register_regulator(wm8350, dcdc, &led->dcdc_init);
1472         if (ret != 0) {
1473                 platform_device_put(pdev);
1474                 return ret;
1475         }
1476
1477         switch (isink) {
1478         case WM8350_ISINK_A:
1479                 wm8350->pmic.isink_A_dcdc = dcdc;
1480                 break;
1481         case WM8350_ISINK_B:
1482                 wm8350->pmic.isink_B_dcdc = dcdc;
1483                 break;
1484         }
1485
1486         pdev->dev.platform_data = pdata;
1487         pdev->dev.parent = wm8350->dev;
1488         ret = platform_device_add(pdev);
1489         if (ret != 0) {
1490                 dev_err(wm8350->dev, "Failed to register LED %d: %d\n",
1491                         lednum, ret);
1492                 platform_device_put(pdev);
1493                 return ret;
1494         }
1495
1496         led->pdev = pdev;
1497
1498         return 0;
1499 }
1500 EXPORT_SYMBOL_GPL(wm8350_register_led);
1501
1502 static struct platform_driver wm8350_regulator_driver = {
1503         .probe = wm8350_regulator_probe,
1504         .remove = wm8350_regulator_remove,
1505         .driver         = {
1506                 .name   = "wm8350-regulator",
1507         },
1508 };
1509
1510 static int __init wm8350_regulator_init(void)
1511 {
1512         return platform_driver_register(&wm8350_regulator_driver);
1513 }
1514 subsys_initcall(wm8350_regulator_init);
1515
1516 static void __exit wm8350_regulator_exit(void)
1517 {
1518         platform_driver_unregister(&wm8350_regulator_driver);
1519 }
1520 module_exit(wm8350_regulator_exit);
1521
1522 /* Module information */
1523 MODULE_AUTHOR("Liam Girdwood");
1524 MODULE_DESCRIPTION("WM8350 voltage and current regulator driver");
1525 MODULE_LICENSE("GPL");
1526 MODULE_ALIAS("platform:wm8350-regulator");