2 * Copyright 2004-2008 Freescale Semiconductor, Inc. All Rights Reserved.
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
13 #include <linux/rtc.h>
14 #include <linux/module.h>
15 #include <linux/slab.h>
16 #include <linux/interrupt.h>
17 #include <linux/platform_device.h>
18 #include <linux/clk.h>
20 #define RTC_INPUT_CLK_32768HZ (0x00 << 5)
21 #define RTC_INPUT_CLK_32000HZ (0x01 << 5)
22 #define RTC_INPUT_CLK_38400HZ (0x02 << 5)
24 #define RTC_SW_BIT (1 << 0)
25 #define RTC_ALM_BIT (1 << 2)
26 #define RTC_1HZ_BIT (1 << 4)
27 #define RTC_2HZ_BIT (1 << 7)
28 #define RTC_SAM0_BIT (1 << 8)
29 #define RTC_SAM1_BIT (1 << 9)
30 #define RTC_SAM2_BIT (1 << 10)
31 #define RTC_SAM3_BIT (1 << 11)
32 #define RTC_SAM4_BIT (1 << 12)
33 #define RTC_SAM5_BIT (1 << 13)
34 #define RTC_SAM6_BIT (1 << 14)
35 #define RTC_SAM7_BIT (1 << 15)
36 #define PIT_ALL_ON (RTC_2HZ_BIT | RTC_SAM0_BIT | RTC_SAM1_BIT | \
37 RTC_SAM2_BIT | RTC_SAM3_BIT | RTC_SAM4_BIT | \
38 RTC_SAM5_BIT | RTC_SAM6_BIT | RTC_SAM7_BIT)
40 #define RTC_ENABLE_BIT (1 << 7)
43 #define MAX_PIE_FREQ 512
44 static const u32 PIE_BIT_DEF[MAX_PIE_NUM][2] = {
51 { 128, RTC_SAM5_BIT },
52 { 256, RTC_SAM6_BIT },
53 { MAX_PIE_FREQ, RTC_SAM7_BIT },
56 #define MXC_RTC_TIME 0
57 #define MXC_RTC_ALARM 1
59 #define RTC_HOURMIN 0x00 /* 32bit rtc hour/min counter reg */
60 #define RTC_SECOND 0x04 /* 32bit rtc seconds counter reg */
61 #define RTC_ALRM_HM 0x08 /* 32bit rtc alarm hour/min reg */
62 #define RTC_ALRM_SEC 0x0C /* 32bit rtc alarm seconds reg */
63 #define RTC_RTCCTL 0x10 /* 32bit rtc control reg */
64 #define RTC_RTCISR 0x14 /* 32bit rtc interrupt status reg */
65 #define RTC_RTCIENR 0x18 /* 32bit rtc interrupt enable reg */
66 #define RTC_STPWCH 0x1C /* 32bit rtc stopwatch min reg */
67 #define RTC_DAYR 0x20 /* 32bit rtc days counter reg */
68 #define RTC_DAYALARM 0x24 /* 32bit rtc day alarm reg */
69 #define RTC_TEST1 0x28 /* 32bit rtc test reg 1 */
70 #define RTC_TEST2 0x2C /* 32bit rtc test reg 2 */
71 #define RTC_TEST3 0x30 /* 32bit rtc test reg 3 */
78 struct rtc_plat_data {
79 struct rtc_device *rtc;
84 struct rtc_time g_rtc_alarm;
85 enum imx_rtc_type devtype;
88 static const struct platform_device_id imx_rtc_devtype[] = {
91 .driver_data = IMX1_RTC,
94 .driver_data = IMX21_RTC,
99 MODULE_DEVICE_TABLE(platform, imx_rtc_devtype);
101 static inline int is_imx1_rtc(struct rtc_plat_data *data)
103 return data->devtype == IMX1_RTC;
107 * This function is used to obtain the RTC time or the alarm value in
110 static time64_t get_alarm_or_time(struct device *dev, int time_alarm)
112 struct platform_device *pdev = to_platform_device(dev);
113 struct rtc_plat_data *pdata = platform_get_drvdata(pdev);
114 void __iomem *ioaddr = pdata->ioaddr;
115 u32 day = 0, hr = 0, min = 0, sec = 0, hr_min = 0;
117 switch (time_alarm) {
119 day = readw(ioaddr + RTC_DAYR);
120 hr_min = readw(ioaddr + RTC_HOURMIN);
121 sec = readw(ioaddr + RTC_SECOND);
124 day = readw(ioaddr + RTC_DAYALARM);
125 hr_min = readw(ioaddr + RTC_ALRM_HM) & 0xffff;
126 sec = readw(ioaddr + RTC_ALRM_SEC);
133 return ((((time64_t)day * 24 + hr) * 60) + min) * 60 + sec;
137 * This function sets the RTC alarm value or the time value.
139 static void set_alarm_or_time(struct device *dev, int time_alarm, time64_t time)
141 u32 tod, day, hr, min, sec, temp;
142 struct platform_device *pdev = to_platform_device(dev);
143 struct rtc_plat_data *pdata = platform_get_drvdata(pdev);
144 void __iomem *ioaddr = pdata->ioaddr;
146 day = div_s64_rem(time, 86400, &tod);
148 /* time is within a day now */
152 /* time is within an hour now */
154 sec = tod - min * 60;
156 temp = (hr << 8) + min;
158 switch (time_alarm) {
160 writew(day, ioaddr + RTC_DAYR);
161 writew(sec, ioaddr + RTC_SECOND);
162 writew(temp, ioaddr + RTC_HOURMIN);
165 writew(day, ioaddr + RTC_DAYALARM);
166 writew(sec, ioaddr + RTC_ALRM_SEC);
167 writew(temp, ioaddr + RTC_ALRM_HM);
173 * This function updates the RTC alarm registers and then clears all the
174 * interrupt status bits.
176 static void rtc_update_alarm(struct device *dev, struct rtc_time *alrm)
179 struct platform_device *pdev = to_platform_device(dev);
180 struct rtc_plat_data *pdata = platform_get_drvdata(pdev);
181 void __iomem *ioaddr = pdata->ioaddr;
183 time = rtc_tm_to_time64(alrm);
185 /* clear all the interrupt status bits */
186 writew(readw(ioaddr + RTC_RTCISR), ioaddr + RTC_RTCISR);
187 set_alarm_or_time(dev, MXC_RTC_ALARM, time);
190 static void mxc_rtc_irq_enable(struct device *dev, unsigned int bit,
191 unsigned int enabled)
193 struct platform_device *pdev = to_platform_device(dev);
194 struct rtc_plat_data *pdata = platform_get_drvdata(pdev);
195 void __iomem *ioaddr = pdata->ioaddr;
198 spin_lock_irq(&pdata->rtc->irq_lock);
199 reg = readw(ioaddr + RTC_RTCIENR);
206 writew(reg, ioaddr + RTC_RTCIENR);
207 spin_unlock_irq(&pdata->rtc->irq_lock);
210 /* This function is the RTC interrupt service routine. */
211 static irqreturn_t mxc_rtc_interrupt(int irq, void *dev_id)
213 struct platform_device *pdev = dev_id;
214 struct rtc_plat_data *pdata = platform_get_drvdata(pdev);
215 void __iomem *ioaddr = pdata->ioaddr;
220 spin_lock_irqsave(&pdata->rtc->irq_lock, flags);
221 status = readw(ioaddr + RTC_RTCISR) & readw(ioaddr + RTC_RTCIENR);
222 /* clear interrupt sources */
223 writew(status, ioaddr + RTC_RTCISR);
225 /* update irq data & counter */
226 if (status & RTC_ALM_BIT) {
227 events |= (RTC_AF | RTC_IRQF);
228 /* RTC alarm should be one-shot */
229 mxc_rtc_irq_enable(&pdev->dev, RTC_ALM_BIT, 0);
232 if (status & RTC_1HZ_BIT)
233 events |= (RTC_UF | RTC_IRQF);
235 if (status & PIT_ALL_ON)
236 events |= (RTC_PF | RTC_IRQF);
238 rtc_update_irq(pdata->rtc, 1, events);
239 spin_unlock_irqrestore(&pdata->rtc->irq_lock, flags);
245 * Clear all interrupts and release the IRQ
247 static void mxc_rtc_release(struct device *dev)
249 struct platform_device *pdev = to_platform_device(dev);
250 struct rtc_plat_data *pdata = platform_get_drvdata(pdev);
251 void __iomem *ioaddr = pdata->ioaddr;
253 spin_lock_irq(&pdata->rtc->irq_lock);
255 /* Disable all rtc interrupts */
256 writew(0, ioaddr + RTC_RTCIENR);
258 /* Clear all interrupt status */
259 writew(0xffffffff, ioaddr + RTC_RTCISR);
261 spin_unlock_irq(&pdata->rtc->irq_lock);
264 static int mxc_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
266 mxc_rtc_irq_enable(dev, RTC_ALM_BIT, enabled);
271 * This function reads the current RTC time into tm in Gregorian date.
273 static int mxc_rtc_read_time(struct device *dev, struct rtc_time *tm)
277 /* Avoid roll-over from reading the different registers */
279 val = get_alarm_or_time(dev, MXC_RTC_TIME);
280 } while (val != get_alarm_or_time(dev, MXC_RTC_TIME));
282 rtc_time64_to_tm(val, tm);
288 * This function sets the internal RTC time based on tm in Gregorian date.
290 static int mxc_rtc_set_mmss(struct device *dev, time64_t time)
292 struct platform_device *pdev = to_platform_device(dev);
293 struct rtc_plat_data *pdata = platform_get_drvdata(pdev);
296 * TTC_DAYR register is 9-bit in MX1 SoC, save time and day of year only
298 if (is_imx1_rtc(pdata)) {
301 rtc_time64_to_tm(time, &tm);
303 time = rtc_tm_to_time64(&tm);
306 /* Avoid roll-over from reading the different registers */
308 set_alarm_or_time(dev, MXC_RTC_TIME, time);
309 } while (time != get_alarm_or_time(dev, MXC_RTC_TIME));
315 * This function reads the current alarm value into the passed in 'alrm'
316 * argument. It updates the alrm's pending field value based on the whether
317 * an alarm interrupt occurs or not.
319 static int mxc_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
321 struct platform_device *pdev = to_platform_device(dev);
322 struct rtc_plat_data *pdata = platform_get_drvdata(pdev);
323 void __iomem *ioaddr = pdata->ioaddr;
325 rtc_time64_to_tm(get_alarm_or_time(dev, MXC_RTC_ALARM), &alrm->time);
326 alrm->pending = ((readw(ioaddr + RTC_RTCISR) & RTC_ALM_BIT)) ? 1 : 0;
332 * This function sets the RTC alarm based on passed in alrm.
334 static int mxc_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
336 struct platform_device *pdev = to_platform_device(dev);
337 struct rtc_plat_data *pdata = platform_get_drvdata(pdev);
339 rtc_update_alarm(dev, &alrm->time);
341 memcpy(&pdata->g_rtc_alarm, &alrm->time, sizeof(struct rtc_time));
342 mxc_rtc_irq_enable(dev, RTC_ALM_BIT, alrm->enabled);
348 static struct rtc_class_ops mxc_rtc_ops = {
349 .release = mxc_rtc_release,
350 .read_time = mxc_rtc_read_time,
351 .set_mmss64 = mxc_rtc_set_mmss,
352 .read_alarm = mxc_rtc_read_alarm,
353 .set_alarm = mxc_rtc_set_alarm,
354 .alarm_irq_enable = mxc_rtc_alarm_irq_enable,
357 static int mxc_rtc_probe(struct platform_device *pdev)
359 struct resource *res;
360 struct rtc_device *rtc;
361 struct rtc_plat_data *pdata = NULL;
366 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
370 pdata->devtype = pdev->id_entry->driver_data;
372 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
373 pdata->ioaddr = devm_ioremap_resource(&pdev->dev, res);
374 if (IS_ERR(pdata->ioaddr))
375 return PTR_ERR(pdata->ioaddr);
377 pdata->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
378 if (IS_ERR(pdata->clk_ipg)) {
379 dev_err(&pdev->dev, "unable to get ipg clock!\n");
380 return PTR_ERR(pdata->clk_ipg);
383 ret = clk_prepare_enable(pdata->clk_ipg);
387 pdata->clk_ref = devm_clk_get(&pdev->dev, "ref");
388 if (IS_ERR(pdata->clk_ref)) {
389 dev_err(&pdev->dev, "unable to get ref clock!\n");
390 ret = PTR_ERR(pdata->clk_ref);
391 goto exit_put_clk_ipg;
394 ret = clk_prepare_enable(pdata->clk_ref);
396 goto exit_put_clk_ipg;
398 rate = clk_get_rate(pdata->clk_ref);
401 reg = RTC_INPUT_CLK_32768HZ;
402 else if (rate == 32000)
403 reg = RTC_INPUT_CLK_32000HZ;
404 else if (rate == 38400)
405 reg = RTC_INPUT_CLK_38400HZ;
407 dev_err(&pdev->dev, "rtc clock is not valid (%lu)\n", rate);
409 goto exit_put_clk_ref;
412 reg |= RTC_ENABLE_BIT;
413 writew(reg, (pdata->ioaddr + RTC_RTCCTL));
414 if (((readw(pdata->ioaddr + RTC_RTCCTL)) & RTC_ENABLE_BIT) == 0) {
415 dev_err(&pdev->dev, "hardware module can't be enabled!\n");
417 goto exit_put_clk_ref;
420 platform_set_drvdata(pdev, pdata);
422 /* Configure and enable the RTC */
423 pdata->irq = platform_get_irq(pdev, 0);
425 if (pdata->irq >= 0 &&
426 devm_request_irq(&pdev->dev, pdata->irq, mxc_rtc_interrupt,
427 IRQF_SHARED, pdev->name, pdev) < 0) {
428 dev_warn(&pdev->dev, "interrupt not available.\n");
433 device_init_wakeup(&pdev->dev, 1);
435 rtc = devm_rtc_device_register(&pdev->dev, pdev->name, &mxc_rtc_ops,
439 goto exit_put_clk_ref;
447 clk_disable_unprepare(pdata->clk_ref);
449 clk_disable_unprepare(pdata->clk_ipg);
454 static int mxc_rtc_remove(struct platform_device *pdev)
456 struct rtc_plat_data *pdata = platform_get_drvdata(pdev);
458 clk_disable_unprepare(pdata->clk_ref);
459 clk_disable_unprepare(pdata->clk_ipg);
464 #ifdef CONFIG_PM_SLEEP
465 static int mxc_rtc_suspend(struct device *dev)
467 struct rtc_plat_data *pdata = dev_get_drvdata(dev);
469 if (device_may_wakeup(dev))
470 enable_irq_wake(pdata->irq);
475 static int mxc_rtc_resume(struct device *dev)
477 struct rtc_plat_data *pdata = dev_get_drvdata(dev);
479 if (device_may_wakeup(dev))
480 disable_irq_wake(pdata->irq);
486 static SIMPLE_DEV_PM_OPS(mxc_rtc_pm_ops, mxc_rtc_suspend, mxc_rtc_resume);
488 static struct platform_driver mxc_rtc_driver = {
491 .pm = &mxc_rtc_pm_ops,
493 .id_table = imx_rtc_devtype,
494 .probe = mxc_rtc_probe,
495 .remove = mxc_rtc_remove,
498 module_platform_driver(mxc_rtc_driver)
500 MODULE_AUTHOR("Daniel Mack <daniel@caiaq.de>");
501 MODULE_DESCRIPTION("RTC driver for Freescale MXC");
502 MODULE_LICENSE("GPL");