2 * Copyright (c) 2016 Linaro Ltd.
3 * Copyright (c) 2016 Hisilicon Limited.
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
13 #define DRV_NAME "hisi_sas_v2_hw"
15 /* global registers need init*/
16 #define DLVRY_QUEUE_ENABLE 0x0
17 #define IOST_BASE_ADDR_LO 0x8
18 #define IOST_BASE_ADDR_HI 0xc
19 #define ITCT_BASE_ADDR_LO 0x10
20 #define ITCT_BASE_ADDR_HI 0x14
21 #define IO_BROKEN_MSG_ADDR_LO 0x18
22 #define IO_BROKEN_MSG_ADDR_HI 0x1c
23 #define PHY_CONTEXT 0x20
24 #define PHY_STATE 0x24
25 #define PHY_PORT_NUM_MA 0x28
26 #define PORT_STATE 0x2c
27 #define PORT_STATE_PHY8_PORT_NUM_OFF 16
28 #define PORT_STATE_PHY8_PORT_NUM_MSK (0xf << PORT_STATE_PHY8_PORT_NUM_OFF)
29 #define PORT_STATE_PHY8_CONN_RATE_OFF 20
30 #define PORT_STATE_PHY8_CONN_RATE_MSK (0xf << PORT_STATE_PHY8_CONN_RATE_OFF)
31 #define PHY_CONN_RATE 0x30
32 #define HGC_TRANS_TASK_CNT_LIMIT 0x38
33 #define AXI_AHB_CLK_CFG 0x3c
35 #define ITCT_CLR_EN_OFF 16
36 #define ITCT_CLR_EN_MSK (0x1 << ITCT_CLR_EN_OFF)
37 #define ITCT_DEV_OFF 0
38 #define ITCT_DEV_MSK (0x7ff << ITCT_DEV_OFF)
39 #define AXI_USER1 0x48
40 #define AXI_USER2 0x4c
41 #define IO_SATA_BROKEN_MSG_ADDR_LO 0x58
42 #define IO_SATA_BROKEN_MSG_ADDR_HI 0x5c
43 #define SATA_INITI_D2H_STORE_ADDR_LO 0x60
44 #define SATA_INITI_D2H_STORE_ADDR_HI 0x64
45 #define HGC_SAS_TX_OPEN_FAIL_RETRY_CTRL 0x84
46 #define HGC_SAS_TXFAIL_RETRY_CTRL 0x88
47 #define HGC_GET_ITV_TIME 0x90
48 #define DEVICE_MSG_WORK_MODE 0x94
49 #define OPENA_WT_CONTI_TIME 0x9c
50 #define I_T_NEXUS_LOSS_TIME 0xa0
51 #define MAX_CON_TIME_LIMIT_TIME 0xa4
52 #define BUS_INACTIVE_LIMIT_TIME 0xa8
53 #define REJECT_TO_OPEN_LIMIT_TIME 0xac
54 #define CFG_AGING_TIME 0xbc
55 #define HGC_DFX_CFG2 0xc0
56 #define HGC_IOMB_PROC1_STATUS 0x104
57 #define CFG_1US_TIMER_TRSH 0xcc
58 #define HGC_INVLD_DQE_INFO 0x148
59 #define HGC_INVLD_DQE_INFO_FB_CH0_OFF 9
60 #define HGC_INVLD_DQE_INFO_FB_CH0_MSK (0x1 << HGC_INVLD_DQE_INFO_FB_CH0_OFF)
61 #define HGC_INVLD_DQE_INFO_FB_CH3_OFF 18
62 #define INT_COAL_EN 0x19c
63 #define OQ_INT_COAL_TIME 0x1a0
64 #define OQ_INT_COAL_CNT 0x1a4
65 #define ENT_INT_COAL_TIME 0x1a8
66 #define ENT_INT_COAL_CNT 0x1ac
67 #define OQ_INT_SRC 0x1b0
68 #define OQ_INT_SRC_MSK 0x1b4
69 #define ENT_INT_SRC1 0x1b8
70 #define ENT_INT_SRC1_D2H_FIS_CH0_OFF 0
71 #define ENT_INT_SRC1_D2H_FIS_CH0_MSK (0x1 << ENT_INT_SRC1_D2H_FIS_CH0_OFF)
72 #define ENT_INT_SRC1_D2H_FIS_CH1_OFF 8
73 #define ENT_INT_SRC1_D2H_FIS_CH1_MSK (0x1 << ENT_INT_SRC1_D2H_FIS_CH1_OFF)
74 #define ENT_INT_SRC2 0x1bc
75 #define ENT_INT_SRC3 0x1c0
76 #define ENT_INT_SRC3_ITC_INT_OFF 15
77 #define ENT_INT_SRC3_ITC_INT_MSK (0x1 << ENT_INT_SRC3_ITC_INT_OFF)
78 #define ENT_INT_SRC_MSK1 0x1c4
79 #define ENT_INT_SRC_MSK2 0x1c8
80 #define ENT_INT_SRC_MSK3 0x1cc
81 #define ENT_INT_SRC_MSK3_ENT95_MSK_OFF 31
82 #define ENT_INT_SRC_MSK3_ENT95_MSK_MSK (0x1 << ENT_INT_SRC_MSK3_ENT95_MSK_OFF)
83 #define SAS_ECC_INTR_MSK 0x1ec
84 #define HGC_ERR_STAT_EN 0x238
85 #define DLVRY_Q_0_BASE_ADDR_LO 0x260
86 #define DLVRY_Q_0_BASE_ADDR_HI 0x264
87 #define DLVRY_Q_0_DEPTH 0x268
88 #define DLVRY_Q_0_WR_PTR 0x26c
89 #define DLVRY_Q_0_RD_PTR 0x270
90 #define HYPER_STREAM_ID_EN_CFG 0xc80
91 #define OQ0_INT_SRC_MSK 0xc90
92 #define COMPL_Q_0_BASE_ADDR_LO 0x4e0
93 #define COMPL_Q_0_BASE_ADDR_HI 0x4e4
94 #define COMPL_Q_0_DEPTH 0x4e8
95 #define COMPL_Q_0_WR_PTR 0x4ec
96 #define COMPL_Q_0_RD_PTR 0x4f0
98 /* phy registers need init */
99 #define PORT_BASE (0x2000)
101 #define PHY_CFG (PORT_BASE + 0x0)
102 #define HARD_PHY_LINKRATE (PORT_BASE + 0x4)
103 #define PHY_CFG_ENA_OFF 0
104 #define PHY_CFG_ENA_MSK (0x1 << PHY_CFG_ENA_OFF)
105 #define PHY_CFG_DC_OPT_OFF 2
106 #define PHY_CFG_DC_OPT_MSK (0x1 << PHY_CFG_DC_OPT_OFF)
107 #define PROG_PHY_LINK_RATE (PORT_BASE + 0x8)
108 #define PROG_PHY_LINK_RATE_MAX_OFF 0
109 #define PROG_PHY_LINK_RATE_MAX_MSK (0xff << PROG_PHY_LINK_RATE_MAX_OFF)
110 #define PHY_CTRL (PORT_BASE + 0x14)
111 #define PHY_CTRL_RESET_OFF 0
112 #define PHY_CTRL_RESET_MSK (0x1 << PHY_CTRL_RESET_OFF)
113 #define SAS_PHY_CTRL (PORT_BASE + 0x20)
114 #define SL_CFG (PORT_BASE + 0x84)
115 #define PHY_PCN (PORT_BASE + 0x44)
116 #define SL_TOUT_CFG (PORT_BASE + 0x8c)
117 #define SL_CONTROL (PORT_BASE + 0x94)
118 #define SL_CONTROL_NOTIFY_EN_OFF 0
119 #define SL_CONTROL_NOTIFY_EN_MSK (0x1 << SL_CONTROL_NOTIFY_EN_OFF)
120 #define TX_ID_DWORD0 (PORT_BASE + 0x9c)
121 #define TX_ID_DWORD1 (PORT_BASE + 0xa0)
122 #define TX_ID_DWORD2 (PORT_BASE + 0xa4)
123 #define TX_ID_DWORD3 (PORT_BASE + 0xa8)
124 #define TX_ID_DWORD4 (PORT_BASE + 0xaC)
125 #define TX_ID_DWORD5 (PORT_BASE + 0xb0)
126 #define TX_ID_DWORD6 (PORT_BASE + 0xb4)
127 #define RX_IDAF_DWORD0 (PORT_BASE + 0xc4)
128 #define RX_IDAF_DWORD1 (PORT_BASE + 0xc8)
129 #define RX_IDAF_DWORD2 (PORT_BASE + 0xcc)
130 #define RX_IDAF_DWORD3 (PORT_BASE + 0xd0)
131 #define RX_IDAF_DWORD4 (PORT_BASE + 0xd4)
132 #define RX_IDAF_DWORD5 (PORT_BASE + 0xd8)
133 #define RX_IDAF_DWORD6 (PORT_BASE + 0xdc)
134 #define RXOP_CHECK_CFG_H (PORT_BASE + 0xfc)
135 #define DONE_RECEIVED_TIME (PORT_BASE + 0x11c)
136 #define CHL_INT0 (PORT_BASE + 0x1b4)
137 #define CHL_INT0_HOTPLUG_TOUT_OFF 0
138 #define CHL_INT0_HOTPLUG_TOUT_MSK (0x1 << CHL_INT0_HOTPLUG_TOUT_OFF)
139 #define CHL_INT0_SL_RX_BCST_ACK_OFF 1
140 #define CHL_INT0_SL_RX_BCST_ACK_MSK (0x1 << CHL_INT0_SL_RX_BCST_ACK_OFF)
141 #define CHL_INT0_SL_PHY_ENABLE_OFF 2
142 #define CHL_INT0_SL_PHY_ENABLE_MSK (0x1 << CHL_INT0_SL_PHY_ENABLE_OFF)
143 #define CHL_INT0_NOT_RDY_OFF 4
144 #define CHL_INT0_NOT_RDY_MSK (0x1 << CHL_INT0_NOT_RDY_OFF)
145 #define CHL_INT0_PHY_RDY_OFF 5
146 #define CHL_INT0_PHY_RDY_MSK (0x1 << CHL_INT0_PHY_RDY_OFF)
147 #define CHL_INT1 (PORT_BASE + 0x1b8)
148 #define CHL_INT1_DMAC_TX_ECC_ERR_OFF 15
149 #define CHL_INT1_DMAC_TX_ECC_ERR_MSK (0x1 << CHL_INT1_DMAC_TX_ECC_ERR_OFF)
150 #define CHL_INT1_DMAC_RX_ECC_ERR_OFF 17
151 #define CHL_INT1_DMAC_RX_ECC_ERR_MSK (0x1 << CHL_INT1_DMAC_RX_ECC_ERR_OFF)
152 #define CHL_INT2 (PORT_BASE + 0x1bc)
153 #define CHL_INT0_MSK (PORT_BASE + 0x1c0)
154 #define CHL_INT1_MSK (PORT_BASE + 0x1c4)
155 #define CHL_INT2_MSK (PORT_BASE + 0x1c8)
156 #define CHL_INT_COAL_EN (PORT_BASE + 0x1d0)
157 #define PHY_CTRL_RDY_MSK (PORT_BASE + 0x2b0)
158 #define PHYCTRL_NOT_RDY_MSK (PORT_BASE + 0x2b4)
159 #define PHYCTRL_DWS_RESET_MSK (PORT_BASE + 0x2b8)
160 #define PHYCTRL_PHY_ENA_MSK (PORT_BASE + 0x2bc)
161 #define SL_RX_BCAST_CHK_MSK (PORT_BASE + 0x2c0)
162 #define PHYCTRL_OOB_RESTART_MSK (PORT_BASE + 0x2c4)
163 #define DMA_TX_STATUS (PORT_BASE + 0x2d0)
164 #define DMA_TX_STATUS_BUSY_OFF 0
165 #define DMA_TX_STATUS_BUSY_MSK (0x1 << DMA_TX_STATUS_BUSY_OFF)
166 #define DMA_RX_STATUS (PORT_BASE + 0x2e8)
167 #define DMA_RX_STATUS_BUSY_OFF 0
168 #define DMA_RX_STATUS_BUSY_MSK (0x1 << DMA_RX_STATUS_BUSY_OFF)
170 #define AXI_CFG (0x5100)
171 #define AM_CFG_MAX_TRANS (0x5010)
172 #define AM_CFG_SINGLE_PORT_MAX_TRANS (0x5014)
174 /* HW dma structures */
175 /* Delivery queue header */
177 #define CMD_HDR_RESP_REPORT_OFF 5
178 #define CMD_HDR_RESP_REPORT_MSK (0x1 << CMD_HDR_RESP_REPORT_OFF)
179 #define CMD_HDR_TLR_CTRL_OFF 6
180 #define CMD_HDR_TLR_CTRL_MSK (0x3 << CMD_HDR_TLR_CTRL_OFF)
181 #define CMD_HDR_PORT_OFF 18
182 #define CMD_HDR_PORT_MSK (0xf << CMD_HDR_PORT_OFF)
183 #define CMD_HDR_PRIORITY_OFF 27
184 #define CMD_HDR_PRIORITY_MSK (0x1 << CMD_HDR_PRIORITY_OFF)
185 #define CMD_HDR_CMD_OFF 29
186 #define CMD_HDR_CMD_MSK (0x7 << CMD_HDR_CMD_OFF)
188 #define CMD_HDR_DIR_OFF 5
189 #define CMD_HDR_DIR_MSK (0x3 << CMD_HDR_DIR_OFF)
190 #define CMD_HDR_RESET_OFF 7
191 #define CMD_HDR_RESET_MSK (0x1 << CMD_HDR_RESET_OFF)
192 #define CMD_HDR_VDTL_OFF 10
193 #define CMD_HDR_VDTL_MSK (0x1 << CMD_HDR_VDTL_OFF)
194 #define CMD_HDR_FRAME_TYPE_OFF 11
195 #define CMD_HDR_FRAME_TYPE_MSK (0x1f << CMD_HDR_FRAME_TYPE_OFF)
196 #define CMD_HDR_DEV_ID_OFF 16
197 #define CMD_HDR_DEV_ID_MSK (0xffff << CMD_HDR_DEV_ID_OFF)
199 #define CMD_HDR_CFL_OFF 0
200 #define CMD_HDR_CFL_MSK (0x1ff << CMD_HDR_CFL_OFF)
201 #define CMD_HDR_NCQ_TAG_OFF 10
202 #define CMD_HDR_NCQ_TAG_MSK (0x1f << CMD_HDR_NCQ_TAG_OFF)
203 #define CMD_HDR_MRFL_OFF 15
204 #define CMD_HDR_MRFL_MSK (0x1ff << CMD_HDR_MRFL_OFF)
205 #define CMD_HDR_SG_MOD_OFF 24
206 #define CMD_HDR_SG_MOD_MSK (0x3 << CMD_HDR_SG_MOD_OFF)
207 #define CMD_HDR_FIRST_BURST_OFF 26
208 #define CMD_HDR_FIRST_BURST_MSK (0x1 << CMD_HDR_SG_MOD_OFF)
210 #define CMD_HDR_IPTT_OFF 0
211 #define CMD_HDR_IPTT_MSK (0xffff << CMD_HDR_IPTT_OFF)
213 #define CMD_HDR_DIF_SGL_LEN_OFF 0
214 #define CMD_HDR_DIF_SGL_LEN_MSK (0xffff << CMD_HDR_DIF_SGL_LEN_OFF)
215 #define CMD_HDR_DATA_SGL_LEN_OFF 16
216 #define CMD_HDR_DATA_SGL_LEN_MSK (0xffff << CMD_HDR_DATA_SGL_LEN_OFF)
218 /* Completion header */
220 #define CMPLT_HDR_RSPNS_XFRD_OFF 10
221 #define CMPLT_HDR_RSPNS_XFRD_MSK (0x1 << CMPLT_HDR_RSPNS_XFRD_OFF)
222 #define CMPLT_HDR_ERX_OFF 12
223 #define CMPLT_HDR_ERX_MSK (0x1 << CMPLT_HDR_ERX_OFF)
225 #define CMPLT_HDR_IPTT_OFF 0
226 #define CMPLT_HDR_IPTT_MSK (0xffff << CMPLT_HDR_IPTT_OFF)
227 #define CMPLT_HDR_DEV_ID_OFF 16
228 #define CMPLT_HDR_DEV_ID_MSK (0xffff << CMPLT_HDR_DEV_ID_OFF)
232 #define ITCT_HDR_DEV_TYPE_OFF 0
233 #define ITCT_HDR_DEV_TYPE_MSK (0x3 << ITCT_HDR_DEV_TYPE_OFF)
234 #define ITCT_HDR_VALID_OFF 2
235 #define ITCT_HDR_VALID_MSK (0x1 << ITCT_HDR_VALID_OFF)
236 #define ITCT_HDR_MCR_OFF 5
237 #define ITCT_HDR_MCR_MSK (0xf << ITCT_HDR_MCR_OFF)
238 #define ITCT_HDR_VLN_OFF 9
239 #define ITCT_HDR_VLN_MSK (0xf << ITCT_HDR_VLN_OFF)
240 #define ITCT_HDR_PORT_ID_OFF 28
241 #define ITCT_HDR_PORT_ID_MSK (0xf << ITCT_HDR_PORT_ID_OFF)
243 #define ITCT_HDR_INLT_OFF 0
244 #define ITCT_HDR_INLT_MSK (0xffffULL << ITCT_HDR_INLT_OFF)
245 #define ITCT_HDR_BITLT_OFF 16
246 #define ITCT_HDR_BITLT_MSK (0xffffULL << ITCT_HDR_BITLT_OFF)
247 #define ITCT_HDR_MCTLT_OFF 32
248 #define ITCT_HDR_MCTLT_MSK (0xffffULL << ITCT_HDR_MCTLT_OFF)
249 #define ITCT_HDR_RTOLT_OFF 48
250 #define ITCT_HDR_RTOLT_MSK (0xffffULL << ITCT_HDR_RTOLT_OFF)
252 struct hisi_sas_complete_v2_hdr {
259 struct hisi_sas_err_record_v2 {
261 __le32 trans_tx_fail_type;
264 __le32 trans_rx_fail_type;
267 __le16 dma_tx_err_type;
268 __le16 sipc_rx_err_type;
271 __le32 dma_rx_err_type;
275 HISI_SAS_PHY_PHY_UPDOWN,
276 HISI_SAS_PHY_CHNL_INT,
281 TRANS_TX_FAIL_BASE = 0x0, /* dw0 */
282 TRANS_RX_FAIL_BASE = 0x100, /* dw1 */
283 DMA_TX_ERR_BASE = 0x200, /* dw2 bit 15-0 */
284 SIPC_RX_ERR_BASE = 0x300, /* dw2 bit 31-16*/
285 DMA_RX_ERR_BASE = 0x400, /* dw3 */
288 TRANS_TX_OPEN_FAIL_WITH_IT_NEXUS_LOSS = TRANS_TX_FAIL_BASE, /* 0x0 */
289 TRANS_TX_ERR_PHY_NOT_ENABLE, /* 0x1 */
290 TRANS_TX_OPEN_CNX_ERR_WRONG_DESTINATION, /* 0x2 */
291 TRANS_TX_OPEN_CNX_ERR_ZONE_VIOLATION, /* 0x3 */
292 TRANS_TX_OPEN_CNX_ERR_BY_OTHER, /* 0x4 */
294 TRANS_TX_OPEN_CNX_ERR_AIP_TIMEOUT, /* 0x6 */
295 TRANS_TX_OPEN_CNX_ERR_STP_RESOURCES_BUSY, /* 0x7 */
296 TRANS_TX_OPEN_CNX_ERR_PROTOCOL_NOT_SUPPORTED, /* 0x8 */
297 TRANS_TX_OPEN_CNX_ERR_CONNECTION_RATE_NOT_SUPPORTED, /* 0x9 */
298 TRANS_TX_OPEN_CNX_ERR_BAD_DESTINATION, /* 0xa */
299 TRANS_TX_OPEN_CNX_ERR_BREAK_RCVD, /* 0xb */
300 TRANS_TX_OPEN_CNX_ERR_LOW_PHY_POWER, /* 0xc */
301 TRANS_TX_OPEN_CNX_ERR_PATHWAY_BLOCKED, /* 0xd */
302 TRANS_TX_OPEN_CNX_ERR_OPEN_TIMEOUT, /* 0xe */
303 TRANS_TX_OPEN_CNX_ERR_NO_DESTINATION, /* 0xf */
304 TRANS_TX_OPEN_RETRY_ERR_THRESHOLD_REACHED, /* 0x10 */
305 TRANS_TX_ERR_FRAME_TXED, /* 0x11 */
306 TRANS_TX_ERR_WITH_BREAK_TIMEOUT, /* 0x12 */
307 TRANS_TX_ERR_WITH_BREAK_REQUEST, /* 0x13 */
308 TRANS_TX_ERR_WITH_BREAK_RECEVIED, /* 0x14 */
309 TRANS_TX_ERR_WITH_CLOSE_TIMEOUT, /* 0x15 */
310 TRANS_TX_ERR_WITH_CLOSE_NORMAL, /* 0x16 for ssp*/
311 TRANS_TX_ERR_WITH_CLOSE_PHYDISALE, /* 0x17 */
312 TRANS_TX_ERR_WITH_CLOSE_DWS_TIMEOUT, /* 0x18 */
313 TRANS_TX_ERR_WITH_CLOSE_COMINIT, /* 0x19 */
314 TRANS_TX_ERR_WITH_NAK_RECEVIED, /* 0x1a for ssp*/
315 TRANS_TX_ERR_WITH_ACK_NAK_TIMEOUT, /* 0x1b for ssp*/
316 /*IO_TX_ERR_WITH_R_ERR_RECEVIED, [> 0x1b for sata/stp<] */
317 TRANS_TX_ERR_WITH_CREDIT_TIMEOUT, /* 0x1c for ssp */
318 /*IO_RX_ERR_WITH_SATA_DEVICE_LOST 0x1c for sata/stp */
319 TRANS_TX_ERR_WITH_IPTT_CONFLICT, /* 0x1d for ssp/smp */
320 TRANS_TX_ERR_WITH_OPEN_BY_DES_OR_OTHERS, /* 0x1e */
321 /*IO_TX_ERR_WITH_SYNC_RXD, [> 0x1e <] for sata/stp */
322 TRANS_TX_ERR_WITH_WAIT_RECV_TIMEOUT, /* 0x1f for sata/stp */
325 TRANS_RX_ERR_WITH_RXFRAME_CRC_ERR = TRANS_RX_FAIL_BASE, /* 0x100 */
326 TRANS_RX_ERR_WITH_RXFIS_8B10B_DISP_ERR, /* 0x101 for sata/stp */
327 TRANS_RX_ERR_WITH_RXFRAME_HAVE_ERRPRM, /* 0x102 for ssp/smp */
328 /*IO_ERR_WITH_RXFIS_8B10B_CODE_ERR, [> 0x102 <] for sata/stp */
329 TRANS_RX_ERR_WITH_RXFIS_DECODE_ERROR, /* 0x103 for sata/stp */
330 TRANS_RX_ERR_WITH_RXFIS_CRC_ERR, /* 0x104 for sata/stp */
331 TRANS_RX_ERR_WITH_RXFRAME_LENGTH_OVERRUN, /* 0x105 for smp */
332 /*IO_ERR_WITH_RXFIS_TX SYNCP, [> 0x105 <] for sata/stp */
333 TRANS_RX_ERR_WITH_RXFIS_RX_SYNCP, /* 0x106 for sata/stp*/
334 TRANS_RX_ERR_WITH_LINK_BUF_OVERRUN, /* 0x107 */
335 TRANS_RX_ERR_WITH_BREAK_TIMEOUT, /* 0x108 */
336 TRANS_RX_ERR_WITH_BREAK_REQUEST, /* 0x109 */
337 TRANS_RX_ERR_WITH_BREAK_RECEVIED, /* 0x10a */
338 RESERVED1, /* 0x10b */
339 TRANS_RX_ERR_WITH_CLOSE_NORMAL, /* 0x10c */
340 TRANS_RX_ERR_WITH_CLOSE_PHY_DISABLE, /* 0x10d */
341 TRANS_RX_ERR_WITH_CLOSE_DWS_TIMEOUT, /* 0x10e */
342 TRANS_RX_ERR_WITH_CLOSE_COMINIT, /* 0x10f */
343 TRANS_RX_ERR_WITH_DATA_LEN0, /* 0x110 for ssp/smp */
344 TRANS_RX_ERR_WITH_BAD_HASH, /* 0x111 for ssp */
345 /*IO_RX_ERR_WITH_FIS_TOO_SHORT, [> 0x111 <] for sata/stp */
346 TRANS_RX_XRDY_WLEN_ZERO_ERR, /* 0x112 for ssp*/
347 /*IO_RX_ERR_WITH_FIS_TOO_LONG, [> 0x112 <] for sata/stp */
348 TRANS_RX_SSP_FRM_LEN_ERR, /* 0x113 for ssp */
349 /*IO_RX_ERR_WITH_SATA_DEVICE_LOST, [> 0x113 <] for sata */
350 RESERVED2, /* 0x114 */
351 RESERVED3, /* 0x115 */
352 RESERVED4, /* 0x116 */
353 RESERVED5, /* 0x117 */
354 TRANS_RX_ERR_WITH_BAD_FRM_TYPE, /* 0x118 */
355 TRANS_RX_SMP_FRM_LEN_ERR, /* 0x119 */
356 TRANS_RX_SMP_RESP_TIMEOUT_ERR, /* 0x11a */
357 RESERVED6, /* 0x11b */
358 RESERVED7, /* 0x11c */
359 RESERVED8, /* 0x11d */
360 RESERVED9, /* 0x11e */
361 TRANS_RX_R_ERR, /* 0x11f */
364 DMA_TX_DIF_CRC_ERR = DMA_TX_ERR_BASE, /* 0x200 */
365 DMA_TX_DIF_APP_ERR, /* 0x201 */
366 DMA_TX_DIF_RPP_ERR, /* 0x202 */
367 DMA_TX_DATA_SGL_OVERFLOW, /* 0x203 */
368 DMA_TX_DIF_SGL_OVERFLOW, /* 0x204 */
369 DMA_TX_UNEXP_XFER_ERR, /* 0x205 */
370 DMA_TX_UNEXP_RETRANS_ERR, /* 0x206 */
371 DMA_TX_XFER_LEN_OVERFLOW, /* 0x207 */
372 DMA_TX_XFER_OFFSET_ERR, /* 0x208 */
373 DMA_TX_RAM_ECC_ERR, /* 0x209 */
374 DMA_TX_DIF_LEN_ALIGN_ERR, /* 0x20a */
377 SIPC_RX_FIS_STATUS_ERR_BIT_VLD = SIPC_RX_ERR_BASE, /* 0x300 */
378 SIPC_RX_PIO_WRSETUP_STATUS_DRQ_ERR, /* 0x301 */
379 SIPC_RX_FIS_STATUS_BSY_BIT_ERR, /* 0x302 */
380 SIPC_RX_WRSETUP_LEN_ODD_ERR, /* 0x303 */
381 SIPC_RX_WRSETUP_LEN_ZERO_ERR, /* 0x304 */
382 SIPC_RX_WRDATA_LEN_NOT_MATCH_ERR, /* 0x305 */
383 SIPC_RX_NCQ_WRSETUP_OFFSET_ERR, /* 0x306 */
384 SIPC_RX_NCQ_WRSETUP_AUTO_ACTIVE_ERR, /* 0x307 */
385 SIPC_RX_SATA_UNEXP_FIS_ERR, /* 0x308 */
386 SIPC_RX_WRSETUP_ESTATUS_ERR, /* 0x309 */
387 SIPC_RX_DATA_UNDERFLOW_ERR, /* 0x30a */
390 DMA_RX_DIF_CRC_ERR = DMA_RX_ERR_BASE, /* 0x400 */
391 DMA_RX_DIF_APP_ERR, /* 0x401 */
392 DMA_RX_DIF_RPP_ERR, /* 0x402 */
393 DMA_RX_DATA_SGL_OVERFLOW, /* 0x403 */
394 DMA_RX_DIF_SGL_OVERFLOW, /* 0x404 */
395 DMA_RX_DATA_LEN_OVERFLOW, /* 0x405 */
396 DMA_RX_DATA_LEN_UNDERFLOW, /* 0x406 */
397 DMA_RX_DATA_OFFSET_ERR, /* 0x407 */
398 RESERVED10, /* 0x408 */
399 DMA_RX_SATA_FRAME_TYPE_ERR, /* 0x409 */
400 DMA_RX_RESP_BUF_OVERFLOW, /* 0x40a */
401 DMA_RX_UNEXP_RETRANS_RESP_ERR, /* 0x40b */
402 DMA_RX_UNEXP_NORM_RESP_ERR, /* 0x40c */
403 DMA_RX_UNEXP_RDFRAME_ERR, /* 0x40d */
404 DMA_RX_PIO_DATA_LEN_ERR, /* 0x40e */
405 DMA_RX_RDSETUP_STATUS_ERR, /* 0x40f */
406 DMA_RX_RDSETUP_STATUS_DRQ_ERR, /* 0x410 */
407 DMA_RX_RDSETUP_STATUS_BSY_ERR, /* 0x411 */
408 DMA_RX_RDSETUP_LEN_ODD_ERR, /* 0x412 */
409 DMA_RX_RDSETUP_LEN_ZERO_ERR, /* 0x413 */
410 DMA_RX_RDSETUP_LEN_OVER_ERR, /* 0x414 */
411 DMA_RX_RDSETUP_OFFSET_ERR, /* 0x415 */
412 DMA_RX_RDSETUP_ACTIVE_ERR, /* 0x416 */
413 DMA_RX_RDSETUP_ESTATUS_ERR, /* 0x417 */
414 DMA_RX_RAM_ECC_ERR, /* 0x418 */
415 DMA_RX_UNKNOWN_FRM_ERR, /* 0x419 */
418 #define HISI_SAS_COMMAND_ENTRIES_V2_HW 4096
420 #define DIR_NO_DATA 0
422 #define DIR_TO_DEVICE 2
423 #define DIR_RESERVED 3
425 #define SATA_PROTOCOL_NONDATA 0x1
426 #define SATA_PROTOCOL_PIO 0x2
427 #define SATA_PROTOCOL_DMA 0x4
428 #define SATA_PROTOCOL_FPDMA 0x8
429 #define SATA_PROTOCOL_ATAPI 0x10
431 static u32 hisi_sas_read32(struct hisi_hba *hisi_hba, u32 off)
433 void __iomem *regs = hisi_hba->regs + off;
438 static u32 hisi_sas_read32_relaxed(struct hisi_hba *hisi_hba, u32 off)
440 void __iomem *regs = hisi_hba->regs + off;
442 return readl_relaxed(regs);
445 static void hisi_sas_write32(struct hisi_hba *hisi_hba, u32 off, u32 val)
447 void __iomem *regs = hisi_hba->regs + off;
452 static void hisi_sas_phy_write32(struct hisi_hba *hisi_hba, int phy_no,
455 void __iomem *regs = hisi_hba->regs + (0x400 * phy_no) + off;
460 static u32 hisi_sas_phy_read32(struct hisi_hba *hisi_hba,
463 void __iomem *regs = hisi_hba->regs + (0x400 * phy_no) + off;
468 /* This function needs to be protected from pre-emption. */
470 slot_index_alloc_quirk_v2_hw(struct hisi_hba *hisi_hba, int *slot_idx,
471 struct domain_device *device)
473 unsigned int index = 0;
474 void *bitmap = hisi_hba->slot_index_tags;
475 int sata_dev = dev_is_sata(device);
478 index = find_next_zero_bit(bitmap, hisi_hba->slot_index_count,
480 if (index >= hisi_hba->slot_index_count)
481 return -SAS_QUEUE_FULL;
483 * SAS IPTT bit0 should be 1
485 if (sata_dev || (index & 1))
490 set_bit(index, bitmap);
496 hisi_sas_device *alloc_dev_quirk_v2_hw(struct domain_device *device)
498 struct hisi_hba *hisi_hba = device->port->ha->lldd_ha;
499 struct hisi_sas_device *sas_dev = NULL;
500 int i, sata_dev = dev_is_sata(device);
502 spin_lock(&hisi_hba->lock);
503 for (i = 0; i < HISI_SAS_MAX_DEVICES; i++) {
505 * SATA device id bit0 should be 0
507 if (sata_dev && (i & 1))
509 if (hisi_hba->devices[i].dev_type == SAS_PHY_UNUSED) {
510 hisi_hba->devices[i].device_id = i;
511 sas_dev = &hisi_hba->devices[i];
512 sas_dev->dev_status = HISI_SAS_DEV_NORMAL;
513 sas_dev->dev_type = device->dev_type;
514 sas_dev->hisi_hba = hisi_hba;
515 sas_dev->sas_device = device;
519 spin_unlock(&hisi_hba->lock);
524 static void config_phy_opt_mode_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
526 u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG);
528 cfg &= ~PHY_CFG_DC_OPT_MSK;
529 cfg |= 1 << PHY_CFG_DC_OPT_OFF;
530 hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg);
533 static void config_id_frame_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
535 struct sas_identify_frame identify_frame;
536 u32 *identify_buffer;
538 memset(&identify_frame, 0, sizeof(identify_frame));
539 identify_frame.dev_type = SAS_END_DEVICE;
540 identify_frame.frame_type = 0;
541 identify_frame._un1 = 1;
542 identify_frame.initiator_bits = SAS_PROTOCOL_ALL;
543 identify_frame.target_bits = SAS_PROTOCOL_NONE;
544 memcpy(&identify_frame._un4_11[0], hisi_hba->sas_addr, SAS_ADDR_SIZE);
545 memcpy(&identify_frame.sas_addr[0], hisi_hba->sas_addr, SAS_ADDR_SIZE);
546 identify_frame.phy_id = phy_no;
547 identify_buffer = (u32 *)(&identify_frame);
549 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD0,
550 __swab32(identify_buffer[0]));
551 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD1,
553 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD2,
555 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD3,
557 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD4,
559 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD5,
560 __swab32(identify_buffer[5]));
563 static void init_id_frame_v2_hw(struct hisi_hba *hisi_hba)
567 for (i = 0; i < hisi_hba->n_phy; i++)
568 config_id_frame_v2_hw(hisi_hba, i);
571 static void setup_itct_v2_hw(struct hisi_hba *hisi_hba,
572 struct hisi_sas_device *sas_dev)
574 struct domain_device *device = sas_dev->sas_device;
575 struct device *dev = &hisi_hba->pdev->dev;
576 u64 qw0, device_id = sas_dev->device_id;
577 struct hisi_sas_itct *itct = &hisi_hba->itct[device_id];
578 struct domain_device *parent_dev = device->parent;
579 struct hisi_sas_port *port = device->port->lldd_port;
581 memset(itct, 0, sizeof(*itct));
585 switch (sas_dev->dev_type) {
587 case SAS_EDGE_EXPANDER_DEVICE:
588 case SAS_FANOUT_EXPANDER_DEVICE:
589 qw0 = HISI_SAS_DEV_TYPE_SSP << ITCT_HDR_DEV_TYPE_OFF;
592 if (parent_dev && DEV_IS_EXPANDER(parent_dev->dev_type))
593 qw0 = HISI_SAS_DEV_TYPE_STP << ITCT_HDR_DEV_TYPE_OFF;
595 qw0 = HISI_SAS_DEV_TYPE_SATA << ITCT_HDR_DEV_TYPE_OFF;
598 dev_warn(dev, "setup itct: unsupported dev type (%d)\n",
602 qw0 |= ((1 << ITCT_HDR_VALID_OFF) |
603 (device->linkrate << ITCT_HDR_MCR_OFF) |
604 (1 << ITCT_HDR_VLN_OFF) |
605 (port->id << ITCT_HDR_PORT_ID_OFF));
606 itct->qw0 = cpu_to_le64(qw0);
609 memcpy(&itct->sas_addr, device->sas_addr, SAS_ADDR_SIZE);
610 itct->sas_addr = __swab64(itct->sas_addr);
613 if (!dev_is_sata(device))
614 itct->qw2 = cpu_to_le64((500ULL << ITCT_HDR_INLT_OFF) |
615 (0x1ULL << ITCT_HDR_BITLT_OFF) |
616 (0x32ULL << ITCT_HDR_MCTLT_OFF) |
617 (0x1ULL << ITCT_HDR_RTOLT_OFF));
620 static void free_device_v2_hw(struct hisi_hba *hisi_hba,
621 struct hisi_sas_device *sas_dev)
623 u64 qw0, dev_id = sas_dev->device_id;
624 struct device *dev = &hisi_hba->pdev->dev;
625 struct hisi_sas_itct *itct = &hisi_hba->itct[dev_id];
626 u32 reg_val = hisi_sas_read32(hisi_hba, ENT_INT_SRC3);
629 /* clear the itct interrupt state */
630 if (ENT_INT_SRC3_ITC_INT_MSK & reg_val)
631 hisi_sas_write32(hisi_hba, ENT_INT_SRC3,
632 ENT_INT_SRC3_ITC_INT_MSK);
634 /* clear the itct int*/
635 for (i = 0; i < 2; i++) {
636 /* clear the itct table*/
637 reg_val = hisi_sas_read32(hisi_hba, ITCT_CLR);
638 reg_val |= ITCT_CLR_EN_MSK | (dev_id & ITCT_DEV_MSK);
639 hisi_sas_write32(hisi_hba, ITCT_CLR, reg_val);
642 reg_val = hisi_sas_read32(hisi_hba, ENT_INT_SRC3);
643 if (ENT_INT_SRC3_ITC_INT_MSK & reg_val) {
644 dev_dbg(dev, "got clear ITCT done interrupt\n");
646 /* invalid the itct state*/
647 qw0 = cpu_to_le64(itct->qw0);
648 qw0 &= ~(1 << ITCT_HDR_VALID_OFF);
649 hisi_sas_write32(hisi_hba, ENT_INT_SRC3,
650 ENT_INT_SRC3_ITC_INT_MSK);
651 hisi_hba->devices[dev_id].dev_type = SAS_PHY_UNUSED;
652 hisi_hba->devices[dev_id].dev_status = HISI_SAS_DEV_NORMAL;
655 hisi_sas_write32(hisi_hba, ITCT_CLR, 0);
656 dev_dbg(dev, "clear ITCT ok\n");
662 static int reset_hw_v2_hw(struct hisi_hba *hisi_hba)
666 unsigned long end_time;
667 struct device *dev = &hisi_hba->pdev->dev;
669 /* The mask needs to be set depending on the number of phys */
670 if (hisi_hba->n_phy == 9)
671 reset_val = 0x1fffff;
675 /* Disable all of the DQ */
676 for (i = 0; i < HISI_SAS_MAX_QUEUES; i++)
677 hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE, 0);
679 /* Disable all of the PHYs */
680 for (i = 0; i < hisi_hba->n_phy; i++) {
681 u32 phy_cfg = hisi_sas_phy_read32(hisi_hba, i, PHY_CFG);
683 phy_cfg &= ~PHY_CTRL_RESET_MSK;
684 hisi_sas_phy_write32(hisi_hba, i, PHY_CFG, phy_cfg);
688 /* Ensure DMA tx & rx idle */
689 for (i = 0; i < hisi_hba->n_phy; i++) {
690 u32 dma_tx_status, dma_rx_status;
692 end_time = jiffies + msecs_to_jiffies(1000);
695 dma_tx_status = hisi_sas_phy_read32(hisi_hba, i,
697 dma_rx_status = hisi_sas_phy_read32(hisi_hba, i,
700 if (!(dma_tx_status & DMA_TX_STATUS_BUSY_MSK) &&
701 !(dma_rx_status & DMA_RX_STATUS_BUSY_MSK))
705 if (time_after(jiffies, end_time))
710 /* Ensure axi bus idle */
711 end_time = jiffies + msecs_to_jiffies(1000);
714 hisi_sas_read32(hisi_hba, AXI_CFG);
720 if (time_after(jiffies, end_time))
724 if (ACPI_HANDLE(dev)) {
727 s = acpi_evaluate_object(ACPI_HANDLE(dev), "_RST", NULL, NULL);
728 if (ACPI_FAILURE(s)) {
729 dev_err(dev, "Reset failed\n");
732 } else if (hisi_hba->ctrl) {
733 /* reset and disable clock*/
734 regmap_write(hisi_hba->ctrl, hisi_hba->ctrl_reset_reg,
736 regmap_write(hisi_hba->ctrl, hisi_hba->ctrl_clock_ena_reg + 4,
739 regmap_read(hisi_hba->ctrl, hisi_hba->ctrl_reset_sts_reg, &val);
740 if (reset_val != (val & reset_val)) {
741 dev_err(dev, "SAS reset fail.\n");
745 /* De-reset and enable clock*/
746 regmap_write(hisi_hba->ctrl, hisi_hba->ctrl_reset_reg + 4,
748 regmap_write(hisi_hba->ctrl, hisi_hba->ctrl_clock_ena_reg,
751 regmap_read(hisi_hba->ctrl, hisi_hba->ctrl_reset_sts_reg,
753 if (val & reset_val) {
754 dev_err(dev, "SAS de-reset fail.\n");
758 dev_warn(dev, "no reset method\n");
763 static void init_reg_v2_hw(struct hisi_hba *hisi_hba)
765 struct device *dev = &hisi_hba->pdev->dev;
768 /* Global registers init */
770 /* Deal with am-max-transmissions quirk */
771 if (device_property_present(dev, "hip06-sas-v2-quirk-amt")) {
772 hisi_sas_write32(hisi_hba, AM_CFG_MAX_TRANS, 0x2020);
773 hisi_sas_write32(hisi_hba, AM_CFG_SINGLE_PORT_MAX_TRANS,
775 } /* Else, use defaults -> do nothing */
777 hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE,
778 (u32)((1ULL << hisi_hba->queue_count) - 1));
779 hisi_sas_write32(hisi_hba, AXI_USER1, 0xc0000000);
780 hisi_sas_write32(hisi_hba, AXI_USER2, 0x10000);
781 hisi_sas_write32(hisi_hba, HGC_SAS_TXFAIL_RETRY_CTRL, 0x108);
782 hisi_sas_write32(hisi_hba, HGC_SAS_TX_OPEN_FAIL_RETRY_CTRL, 0x7FF);
783 hisi_sas_write32(hisi_hba, OPENA_WT_CONTI_TIME, 0x1);
784 hisi_sas_write32(hisi_hba, I_T_NEXUS_LOSS_TIME, 0x1F4);
785 hisi_sas_write32(hisi_hba, MAX_CON_TIME_LIMIT_TIME, 0x32);
786 hisi_sas_write32(hisi_hba, BUS_INACTIVE_LIMIT_TIME, 0x1);
787 hisi_sas_write32(hisi_hba, CFG_AGING_TIME, 0x1);
788 hisi_sas_write32(hisi_hba, HGC_ERR_STAT_EN, 0x1);
789 hisi_sas_write32(hisi_hba, HGC_GET_ITV_TIME, 0x1);
790 hisi_sas_write32(hisi_hba, INT_COAL_EN, 0x1);
791 hisi_sas_write32(hisi_hba, OQ_INT_COAL_TIME, 0x1);
792 hisi_sas_write32(hisi_hba, OQ_INT_COAL_CNT, 0x1);
793 hisi_sas_write32(hisi_hba, ENT_INT_COAL_TIME, 0x1);
794 hisi_sas_write32(hisi_hba, ENT_INT_COAL_CNT, 0x1);
795 hisi_sas_write32(hisi_hba, OQ_INT_SRC, 0x0);
796 hisi_sas_write32(hisi_hba, ENT_INT_SRC1, 0xffffffff);
797 hisi_sas_write32(hisi_hba, ENT_INT_SRC2, 0xffffffff);
798 hisi_sas_write32(hisi_hba, ENT_INT_SRC3, 0xffffffff);
799 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1, 0x7efefefe);
800 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK2, 0x7efefefe);
801 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, 0x7ffffffe);
802 hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, 0xfffff3c0);
803 for (i = 0; i < hisi_hba->queue_count; i++)
804 hisi_sas_write32(hisi_hba, OQ0_INT_SRC_MSK+0x4*i, 0);
806 hisi_sas_write32(hisi_hba, AXI_AHB_CLK_CFG, 1);
807 hisi_sas_write32(hisi_hba, HYPER_STREAM_ID_EN_CFG, 1);
809 for (i = 0; i < hisi_hba->n_phy; i++) {
810 hisi_sas_phy_write32(hisi_hba, i, PROG_PHY_LINK_RATE, 0x855);
811 hisi_sas_phy_write32(hisi_hba, i, SAS_PHY_CTRL, 0x30b9908);
812 hisi_sas_phy_write32(hisi_hba, i, SL_TOUT_CFG, 0x7d7d7d7d);
813 hisi_sas_phy_write32(hisi_hba, i, DONE_RECEIVED_TIME, 0x10);
814 hisi_sas_phy_write32(hisi_hba, i, CHL_INT0, 0xffffffff);
815 hisi_sas_phy_write32(hisi_hba, i, CHL_INT1, 0xffffffff);
816 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2, 0xffffffff);
817 hisi_sas_phy_write32(hisi_hba, i, RXOP_CHECK_CFG_H, 0x1000);
818 hisi_sas_phy_write32(hisi_hba, i, CHL_INT1_MSK, 0xffffffff);
819 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2_MSK, 0x8ffffbff);
820 hisi_sas_phy_write32(hisi_hba, i, SL_CFG, 0x23f801fc);
821 hisi_sas_phy_write32(hisi_hba, i, PHY_CTRL_RDY_MSK, 0x0);
822 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_NOT_RDY_MSK, 0x0);
823 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_DWS_RESET_MSK, 0x0);
824 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_PHY_ENA_MSK, 0x0);
825 hisi_sas_phy_write32(hisi_hba, i, SL_RX_BCAST_CHK_MSK, 0x0);
826 hisi_sas_phy_write32(hisi_hba, i, CHL_INT_COAL_EN, 0x0);
827 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_OOB_RESTART_MSK, 0x0);
828 hisi_sas_phy_write32(hisi_hba, i, PHY_CTRL, 0x199B694);
831 for (i = 0; i < hisi_hba->queue_count; i++) {
833 hisi_sas_write32(hisi_hba,
834 DLVRY_Q_0_BASE_ADDR_HI + (i * 0x14),
835 upper_32_bits(hisi_hba->cmd_hdr_dma[i]));
837 hisi_sas_write32(hisi_hba, DLVRY_Q_0_BASE_ADDR_LO + (i * 0x14),
838 lower_32_bits(hisi_hba->cmd_hdr_dma[i]));
840 hisi_sas_write32(hisi_hba, DLVRY_Q_0_DEPTH + (i * 0x14),
841 HISI_SAS_QUEUE_SLOTS);
843 /* Completion queue */
844 hisi_sas_write32(hisi_hba, COMPL_Q_0_BASE_ADDR_HI + (i * 0x14),
845 upper_32_bits(hisi_hba->complete_hdr_dma[i]));
847 hisi_sas_write32(hisi_hba, COMPL_Q_0_BASE_ADDR_LO + (i * 0x14),
848 lower_32_bits(hisi_hba->complete_hdr_dma[i]));
850 hisi_sas_write32(hisi_hba, COMPL_Q_0_DEPTH + (i * 0x14),
851 HISI_SAS_QUEUE_SLOTS);
855 hisi_sas_write32(hisi_hba, ITCT_BASE_ADDR_LO,
856 lower_32_bits(hisi_hba->itct_dma));
858 hisi_sas_write32(hisi_hba, ITCT_BASE_ADDR_HI,
859 upper_32_bits(hisi_hba->itct_dma));
862 hisi_sas_write32(hisi_hba, IOST_BASE_ADDR_LO,
863 lower_32_bits(hisi_hba->iost_dma));
865 hisi_sas_write32(hisi_hba, IOST_BASE_ADDR_HI,
866 upper_32_bits(hisi_hba->iost_dma));
869 hisi_sas_write32(hisi_hba, IO_BROKEN_MSG_ADDR_LO,
870 lower_32_bits(hisi_hba->breakpoint_dma));
872 hisi_sas_write32(hisi_hba, IO_BROKEN_MSG_ADDR_HI,
873 upper_32_bits(hisi_hba->breakpoint_dma));
875 /* SATA broken msg */
876 hisi_sas_write32(hisi_hba, IO_SATA_BROKEN_MSG_ADDR_LO,
877 lower_32_bits(hisi_hba->sata_breakpoint_dma));
879 hisi_sas_write32(hisi_hba, IO_SATA_BROKEN_MSG_ADDR_HI,
880 upper_32_bits(hisi_hba->sata_breakpoint_dma));
882 /* SATA initial fis */
883 hisi_sas_write32(hisi_hba, SATA_INITI_D2H_STORE_ADDR_LO,
884 lower_32_bits(hisi_hba->initial_fis_dma));
886 hisi_sas_write32(hisi_hba, SATA_INITI_D2H_STORE_ADDR_HI,
887 upper_32_bits(hisi_hba->initial_fis_dma));
890 static int hw_init_v2_hw(struct hisi_hba *hisi_hba)
892 struct device *dev = &hisi_hba->pdev->dev;
895 rc = reset_hw_v2_hw(hisi_hba);
897 dev_err(dev, "hisi_sas_reset_hw failed, rc=%d", rc);
902 init_reg_v2_hw(hisi_hba);
904 init_id_frame_v2_hw(hisi_hba);
909 static void enable_phy_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
911 u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG);
913 cfg |= PHY_CFG_ENA_MSK;
914 hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg);
917 static void disable_phy_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
919 u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG);
921 cfg &= ~PHY_CFG_ENA_MSK;
922 hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg);
925 static void start_phy_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
927 config_id_frame_v2_hw(hisi_hba, phy_no);
928 config_phy_opt_mode_v2_hw(hisi_hba, phy_no);
929 enable_phy_v2_hw(hisi_hba, phy_no);
932 static void stop_phy_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
934 disable_phy_v2_hw(hisi_hba, phy_no);
937 static void phy_hard_reset_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
939 stop_phy_v2_hw(hisi_hba, phy_no);
941 start_phy_v2_hw(hisi_hba, phy_no);
944 static void start_phys_v2_hw(unsigned long data)
946 struct hisi_hba *hisi_hba = (struct hisi_hba *)data;
949 for (i = 0; i < hisi_hba->n_phy; i++)
950 start_phy_v2_hw(hisi_hba, i);
953 static void phys_init_v2_hw(struct hisi_hba *hisi_hba)
956 struct timer_list *timer = &hisi_hba->timer;
958 for (i = 0; i < hisi_hba->n_phy; i++) {
959 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2_MSK, 0x6a);
960 hisi_sas_phy_read32(hisi_hba, i, CHL_INT2_MSK);
963 setup_timer(timer, start_phys_v2_hw, (unsigned long)hisi_hba);
964 mod_timer(timer, jiffies + HZ);
967 static void sl_notify_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
971 sl_control = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL);
972 sl_control |= SL_CONTROL_NOTIFY_EN_MSK;
973 hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL, sl_control);
975 sl_control = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL);
976 sl_control &= ~SL_CONTROL_NOTIFY_EN_MSK;
977 hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL, sl_control);
980 static int get_wideport_bitmap_v2_hw(struct hisi_hba *hisi_hba, int port_id)
983 u32 phy_port_num_ma = hisi_sas_read32(hisi_hba, PHY_PORT_NUM_MA);
984 u32 phy_state = hisi_sas_read32(hisi_hba, PHY_STATE);
986 for (i = 0; i < (hisi_hba->n_phy < 9 ? hisi_hba->n_phy : 8); i++)
987 if (phy_state & 1 << i)
988 if (((phy_port_num_ma >> (i * 4)) & 0xf) == port_id)
991 if (hisi_hba->n_phy == 9) {
992 u32 port_state = hisi_sas_read32(hisi_hba, PORT_STATE);
994 if (phy_state & 1 << 8)
995 if (((port_state & PORT_STATE_PHY8_PORT_NUM_MSK) >>
996 PORT_STATE_PHY8_PORT_NUM_OFF) == port_id)
1004 * This function allocates across all queues to load balance.
1005 * Slots are allocated from queues in a round-robin fashion.
1007 * The callpath to this function and upto writing the write
1008 * queue pointer should be safe from interruption.
1010 static int get_free_slot_v2_hw(struct hisi_hba *hisi_hba, int *q, int *s)
1012 struct device *dev = &hisi_hba->pdev->dev;
1014 int queue = hisi_hba->queue;
1017 w = hisi_sas_read32_relaxed(hisi_hba,
1018 DLVRY_Q_0_WR_PTR + (queue * 0x14));
1019 r = hisi_sas_read32_relaxed(hisi_hba,
1020 DLVRY_Q_0_RD_PTR + (queue * 0x14));
1021 if (r == (w+1) % HISI_SAS_QUEUE_SLOTS) {
1022 queue = (queue + 1) % hisi_hba->queue_count;
1023 if (queue == hisi_hba->queue) {
1024 dev_warn(dev, "could not find free slot\n");
1031 hisi_hba->queue = (queue + 1) % hisi_hba->queue_count;
1037 static void start_delivery_v2_hw(struct hisi_hba *hisi_hba)
1039 int dlvry_queue = hisi_hba->slot_prep->dlvry_queue;
1040 int dlvry_queue_slot = hisi_hba->slot_prep->dlvry_queue_slot;
1042 hisi_sas_write32(hisi_hba, DLVRY_Q_0_WR_PTR + (dlvry_queue * 0x14),
1043 ++dlvry_queue_slot % HISI_SAS_QUEUE_SLOTS);
1046 static int prep_prd_sge_v2_hw(struct hisi_hba *hisi_hba,
1047 struct hisi_sas_slot *slot,
1048 struct hisi_sas_cmd_hdr *hdr,
1049 struct scatterlist *scatter,
1052 struct device *dev = &hisi_hba->pdev->dev;
1053 struct scatterlist *sg;
1056 if (n_elem > HISI_SAS_SGE_PAGE_CNT) {
1057 dev_err(dev, "prd err: n_elem(%d) > HISI_SAS_SGE_PAGE_CNT",
1062 slot->sge_page = dma_pool_alloc(hisi_hba->sge_page_pool, GFP_ATOMIC,
1063 &slot->sge_page_dma);
1064 if (!slot->sge_page)
1067 for_each_sg(scatter, sg, n_elem, i) {
1068 struct hisi_sas_sge *entry = &slot->sge_page->sge[i];
1070 entry->addr = cpu_to_le64(sg_dma_address(sg));
1071 entry->page_ctrl_0 = entry->page_ctrl_1 = 0;
1072 entry->data_len = cpu_to_le32(sg_dma_len(sg));
1073 entry->data_off = 0;
1076 hdr->prd_table_addr = cpu_to_le64(slot->sge_page_dma);
1078 hdr->sg_len = cpu_to_le32(n_elem << CMD_HDR_DATA_SGL_LEN_OFF);
1083 static int prep_smp_v2_hw(struct hisi_hba *hisi_hba,
1084 struct hisi_sas_slot *slot)
1086 struct sas_task *task = slot->task;
1087 struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
1088 struct domain_device *device = task->dev;
1089 struct device *dev = &hisi_hba->pdev->dev;
1090 struct hisi_sas_port *port = slot->port;
1091 struct scatterlist *sg_req, *sg_resp;
1092 struct hisi_sas_device *sas_dev = device->lldd_dev;
1093 dma_addr_t req_dma_addr;
1094 unsigned int req_len, resp_len;
1098 * DMA-map SMP request, response buffers
1101 sg_req = &task->smp_task.smp_req;
1102 elem = dma_map_sg(dev, sg_req, 1, DMA_TO_DEVICE);
1105 req_len = sg_dma_len(sg_req);
1106 req_dma_addr = sg_dma_address(sg_req);
1109 sg_resp = &task->smp_task.smp_resp;
1110 elem = dma_map_sg(dev, sg_resp, 1, DMA_FROM_DEVICE);
1115 resp_len = sg_dma_len(sg_resp);
1116 if ((req_len & 0x3) || (resp_len & 0x3)) {
1123 hdr->dw0 = cpu_to_le32((port->id << CMD_HDR_PORT_OFF) |
1124 (1 << CMD_HDR_PRIORITY_OFF) | /* high pri */
1125 (2 << CMD_HDR_CMD_OFF)); /* smp */
1127 /* map itct entry */
1128 hdr->dw1 = cpu_to_le32((sas_dev->device_id << CMD_HDR_DEV_ID_OFF) |
1129 (1 << CMD_HDR_FRAME_TYPE_OFF) |
1130 (DIR_NO_DATA << CMD_HDR_DIR_OFF));
1133 hdr->dw2 = cpu_to_le32((((req_len - 4) / 4) << CMD_HDR_CFL_OFF) |
1134 (HISI_SAS_MAX_SMP_RESP_SZ / 4 <<
1137 hdr->transfer_tags = cpu_to_le32(slot->idx << CMD_HDR_IPTT_OFF);
1139 hdr->cmd_table_addr = cpu_to_le64(req_dma_addr);
1140 hdr->sts_buffer_addr = cpu_to_le64(slot->status_buffer_dma);
1145 dma_unmap_sg(dev, &slot->task->smp_task.smp_resp, 1,
1148 dma_unmap_sg(dev, &slot->task->smp_task.smp_req, 1,
1153 static int prep_ssp_v2_hw(struct hisi_hba *hisi_hba,
1154 struct hisi_sas_slot *slot, int is_tmf,
1155 struct hisi_sas_tmf_task *tmf)
1157 struct sas_task *task = slot->task;
1158 struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
1159 struct domain_device *device = task->dev;
1160 struct hisi_sas_device *sas_dev = device->lldd_dev;
1161 struct hisi_sas_port *port = slot->port;
1162 struct sas_ssp_task *ssp_task = &task->ssp_task;
1163 struct scsi_cmnd *scsi_cmnd = ssp_task->cmd;
1164 int has_data = 0, rc, priority = is_tmf;
1166 u32 dw1 = 0, dw2 = 0;
1168 hdr->dw0 = cpu_to_le32((1 << CMD_HDR_RESP_REPORT_OFF) |
1169 (2 << CMD_HDR_TLR_CTRL_OFF) |
1170 (port->id << CMD_HDR_PORT_OFF) |
1171 (priority << CMD_HDR_PRIORITY_OFF) |
1172 (1 << CMD_HDR_CMD_OFF)); /* ssp */
1174 dw1 = 1 << CMD_HDR_VDTL_OFF;
1176 dw1 |= 2 << CMD_HDR_FRAME_TYPE_OFF;
1177 dw1 |= DIR_NO_DATA << CMD_HDR_DIR_OFF;
1179 dw1 |= 1 << CMD_HDR_FRAME_TYPE_OFF;
1180 switch (scsi_cmnd->sc_data_direction) {
1183 dw1 |= DIR_TO_DEVICE << CMD_HDR_DIR_OFF;
1185 case DMA_FROM_DEVICE:
1187 dw1 |= DIR_TO_INI << CMD_HDR_DIR_OFF;
1190 dw1 &= ~CMD_HDR_DIR_MSK;
1194 /* map itct entry */
1195 dw1 |= sas_dev->device_id << CMD_HDR_DEV_ID_OFF;
1196 hdr->dw1 = cpu_to_le32(dw1);
1198 dw2 = (((sizeof(struct ssp_command_iu) + sizeof(struct ssp_frame_hdr)
1199 + 3) / 4) << CMD_HDR_CFL_OFF) |
1200 ((HISI_SAS_MAX_SSP_RESP_SZ / 4) << CMD_HDR_MRFL_OFF) |
1201 (2 << CMD_HDR_SG_MOD_OFF);
1202 hdr->dw2 = cpu_to_le32(dw2);
1204 hdr->transfer_tags = cpu_to_le32(slot->idx);
1207 rc = prep_prd_sge_v2_hw(hisi_hba, slot, hdr, task->scatter,
1213 hdr->data_transfer_len = cpu_to_le32(task->total_xfer_len);
1214 hdr->cmd_table_addr = cpu_to_le64(slot->command_table_dma);
1215 hdr->sts_buffer_addr = cpu_to_le64(slot->status_buffer_dma);
1217 buf_cmd = slot->command_table + sizeof(struct ssp_frame_hdr);
1219 memcpy(buf_cmd, &task->ssp_task.LUN, 8);
1221 buf_cmd[9] = task->ssp_task.task_attr |
1222 (task->ssp_task.task_prio << 3);
1223 memcpy(buf_cmd + 12, task->ssp_task.cmd->cmnd,
1224 task->ssp_task.cmd->cmd_len);
1226 buf_cmd[10] = tmf->tmf;
1228 case TMF_ABORT_TASK:
1229 case TMF_QUERY_TASK:
1231 (tmf->tag_of_task_to_be_managed >> 8) & 0xff;
1233 tmf->tag_of_task_to_be_managed & 0xff;
1243 static void sata_done_v2_hw(struct hisi_hba *hisi_hba, struct sas_task *task,
1244 struct hisi_sas_slot *slot)
1246 struct task_status_struct *ts = &task->task_status;
1247 struct ata_task_resp *resp = (struct ata_task_resp *)ts->buf;
1248 struct dev_to_host_fis *d2h = slot->status_buffer +
1249 sizeof(struct hisi_sas_err_record);
1251 resp->frame_len = sizeof(struct dev_to_host_fis);
1252 memcpy(&resp->ending_fis[0], d2h, sizeof(struct dev_to_host_fis));
1254 ts->buf_valid_size = sizeof(*resp);
1257 /* by default, task resp is complete */
1258 static void slot_err_v2_hw(struct hisi_hba *hisi_hba,
1259 struct sas_task *task,
1260 struct hisi_sas_slot *slot)
1262 struct task_status_struct *ts = &task->task_status;
1263 struct hisi_sas_err_record_v2 *err_record = slot->status_buffer;
1264 u32 trans_tx_fail_type = cpu_to_le32(err_record->trans_tx_fail_type);
1265 u32 trans_rx_fail_type = cpu_to_le32(err_record->trans_rx_fail_type);
1266 u16 dma_tx_err_type = cpu_to_le16(err_record->dma_tx_err_type);
1267 u16 sipc_rx_err_type = cpu_to_le16(err_record->sipc_rx_err_type);
1268 u32 dma_rx_err_type = cpu_to_le32(err_record->dma_rx_err_type);
1271 if (dma_rx_err_type) {
1272 error = ffs(dma_rx_err_type)
1273 - 1 + DMA_RX_ERR_BASE;
1274 } else if (sipc_rx_err_type) {
1275 error = ffs(sipc_rx_err_type)
1276 - 1 + SIPC_RX_ERR_BASE;
1277 } else if (dma_tx_err_type) {
1278 error = ffs(dma_tx_err_type)
1279 - 1 + DMA_TX_ERR_BASE;
1280 } else if (trans_rx_fail_type) {
1281 error = ffs(trans_rx_fail_type)
1282 - 1 + TRANS_RX_FAIL_BASE;
1283 } else if (trans_tx_fail_type) {
1284 error = ffs(trans_tx_fail_type)
1285 - 1 + TRANS_TX_FAIL_BASE;
1288 switch (task->task_proto) {
1289 case SAS_PROTOCOL_SSP:
1292 case TRANS_TX_OPEN_CNX_ERR_NO_DESTINATION:
1294 ts->stat = SAS_OPEN_REJECT;
1295 ts->open_rej_reason = SAS_OREJ_NO_DEST;
1298 case TRANS_TX_OPEN_CNX_ERR_PATHWAY_BLOCKED:
1300 ts->stat = SAS_OPEN_REJECT;
1301 ts->open_rej_reason = SAS_OREJ_PATH_BLOCKED;
1304 case TRANS_TX_OPEN_CNX_ERR_PROTOCOL_NOT_SUPPORTED:
1306 ts->stat = SAS_OPEN_REJECT;
1307 ts->open_rej_reason = SAS_OREJ_EPROTO;
1310 case TRANS_TX_OPEN_CNX_ERR_CONNECTION_RATE_NOT_SUPPORTED:
1312 ts->stat = SAS_OPEN_REJECT;
1313 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
1316 case TRANS_TX_OPEN_CNX_ERR_BAD_DESTINATION:
1318 ts->stat = SAS_OPEN_REJECT;
1319 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
1322 case TRANS_TX_OPEN_CNX_ERR_BREAK_RCVD:
1324 ts->stat = SAS_OPEN_REJECT;
1325 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1328 case TRANS_TX_OPEN_CNX_ERR_WRONG_DESTINATION:
1330 ts->stat = SAS_OPEN_REJECT;
1331 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
1334 case TRANS_TX_OPEN_CNX_ERR_ZONE_VIOLATION:
1336 ts->stat = SAS_OPEN_REJECT;
1337 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
1340 case TRANS_TX_OPEN_CNX_ERR_LOW_PHY_POWER:
1343 ts->stat = SAS_DEV_NO_RESPONSE;
1346 case TRANS_RX_ERR_WITH_CLOSE_PHY_DISABLE:
1348 ts->stat = SAS_PHY_DOWN;
1351 case TRANS_TX_OPEN_CNX_ERR_OPEN_TIMEOUT:
1353 ts->stat = SAS_OPEN_TO;
1356 case DMA_RX_DATA_LEN_OVERFLOW:
1358 ts->stat = SAS_DATA_OVERRUN;
1362 case DMA_RX_DATA_LEN_UNDERFLOW:
1363 case SIPC_RX_DATA_UNDERFLOW_ERR:
1365 ts->residual = trans_tx_fail_type;
1366 ts->stat = SAS_DATA_UNDERRUN;
1369 case TRANS_TX_ERR_FRAME_TXED:
1371 /* This will request a retry */
1372 ts->stat = SAS_QUEUE_FULL;
1376 case TRANS_TX_OPEN_FAIL_WITH_IT_NEXUS_LOSS:
1377 case TRANS_TX_ERR_PHY_NOT_ENABLE:
1378 case TRANS_TX_OPEN_CNX_ERR_BY_OTHER:
1379 case TRANS_TX_OPEN_CNX_ERR_AIP_TIMEOUT:
1380 case TRANS_TX_OPEN_RETRY_ERR_THRESHOLD_REACHED:
1381 case TRANS_TX_ERR_WITH_BREAK_TIMEOUT:
1382 case TRANS_TX_ERR_WITH_BREAK_REQUEST:
1383 case TRANS_TX_ERR_WITH_BREAK_RECEVIED:
1384 case TRANS_TX_ERR_WITH_CLOSE_TIMEOUT:
1385 case TRANS_TX_ERR_WITH_CLOSE_NORMAL:
1386 case TRANS_TX_ERR_WITH_CLOSE_DWS_TIMEOUT:
1387 case TRANS_TX_ERR_WITH_CLOSE_COMINIT:
1388 case TRANS_TX_ERR_WITH_NAK_RECEVIED:
1389 case TRANS_TX_ERR_WITH_ACK_NAK_TIMEOUT:
1390 case TRANS_TX_ERR_WITH_IPTT_CONFLICT:
1391 case TRANS_TX_ERR_WITH_CREDIT_TIMEOUT:
1392 case TRANS_RX_ERR_WITH_RXFRAME_CRC_ERR:
1393 case TRANS_RX_ERR_WITH_RXFIS_8B10B_DISP_ERR:
1394 case TRANS_RX_ERR_WITH_RXFRAME_HAVE_ERRPRM:
1395 case TRANS_RX_ERR_WITH_BREAK_TIMEOUT:
1396 case TRANS_RX_ERR_WITH_BREAK_REQUEST:
1397 case TRANS_RX_ERR_WITH_BREAK_RECEVIED:
1398 case TRANS_RX_ERR_WITH_CLOSE_NORMAL:
1399 case TRANS_RX_ERR_WITH_CLOSE_DWS_TIMEOUT:
1400 case TRANS_RX_ERR_WITH_CLOSE_COMINIT:
1401 case TRANS_RX_ERR_WITH_DATA_LEN0:
1402 case TRANS_RX_ERR_WITH_BAD_HASH:
1403 case TRANS_RX_XRDY_WLEN_ZERO_ERR:
1404 case TRANS_RX_SSP_FRM_LEN_ERR:
1405 case TRANS_RX_ERR_WITH_BAD_FRM_TYPE:
1406 case DMA_TX_UNEXP_XFER_ERR:
1407 case DMA_TX_UNEXP_RETRANS_ERR:
1408 case DMA_TX_XFER_LEN_OVERFLOW:
1409 case DMA_TX_XFER_OFFSET_ERR:
1410 case DMA_RX_DATA_OFFSET_ERR:
1411 case DMA_RX_UNEXP_NORM_RESP_ERR:
1412 case DMA_RX_UNEXP_RDFRAME_ERR:
1413 case DMA_RX_UNKNOWN_FRM_ERR:
1415 ts->stat = SAS_OPEN_REJECT;
1416 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
1424 case SAS_PROTOCOL_SMP:
1425 ts->stat = SAM_STAT_CHECK_CONDITION;
1428 case SAS_PROTOCOL_SATA:
1429 case SAS_PROTOCOL_STP:
1430 case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP:
1433 case TRANS_TX_OPEN_CNX_ERR_LOW_PHY_POWER:
1434 case TRANS_TX_OPEN_CNX_ERR_PATHWAY_BLOCKED:
1435 case TRANS_TX_OPEN_CNX_ERR_NO_DESTINATION:
1437 ts->resp = SAS_TASK_UNDELIVERED;
1438 ts->stat = SAS_DEV_NO_RESPONSE;
1441 case TRANS_TX_OPEN_CNX_ERR_PROTOCOL_NOT_SUPPORTED:
1442 case TRANS_TX_OPEN_CNX_ERR_CONNECTION_RATE_NOT_SUPPORTED:
1443 case TRANS_TX_OPEN_CNX_ERR_BAD_DESTINATION:
1444 case TRANS_TX_OPEN_CNX_ERR_BREAK_RCVD:
1445 case TRANS_TX_OPEN_CNX_ERR_WRONG_DESTINATION:
1446 case TRANS_TX_OPEN_CNX_ERR_ZONE_VIOLATION:
1447 case TRANS_TX_OPEN_CNX_ERR_STP_RESOURCES_BUSY:
1449 ts->stat = SAS_OPEN_REJECT;
1452 case TRANS_TX_OPEN_CNX_ERR_OPEN_TIMEOUT:
1454 ts->stat = SAS_OPEN_TO;
1457 case DMA_RX_DATA_LEN_OVERFLOW:
1459 ts->stat = SAS_DATA_OVERRUN;
1462 case TRANS_TX_OPEN_FAIL_WITH_IT_NEXUS_LOSS:
1463 case TRANS_TX_ERR_PHY_NOT_ENABLE:
1464 case TRANS_TX_OPEN_CNX_ERR_BY_OTHER:
1465 case TRANS_TX_OPEN_CNX_ERR_AIP_TIMEOUT:
1466 case TRANS_TX_OPEN_RETRY_ERR_THRESHOLD_REACHED:
1467 case TRANS_TX_ERR_WITH_BREAK_TIMEOUT:
1468 case TRANS_TX_ERR_WITH_BREAK_REQUEST:
1469 case TRANS_TX_ERR_WITH_BREAK_RECEVIED:
1470 case TRANS_TX_ERR_WITH_CLOSE_TIMEOUT:
1471 case TRANS_TX_ERR_WITH_CLOSE_NORMAL:
1472 case TRANS_TX_ERR_WITH_CLOSE_DWS_TIMEOUT:
1473 case TRANS_TX_ERR_WITH_CLOSE_COMINIT:
1474 case TRANS_TX_ERR_WITH_NAK_RECEVIED:
1475 case TRANS_TX_ERR_WITH_ACK_NAK_TIMEOUT:
1476 case TRANS_TX_ERR_WITH_CREDIT_TIMEOUT:
1477 case TRANS_TX_ERR_WITH_WAIT_RECV_TIMEOUT:
1478 case TRANS_RX_ERR_WITH_RXFIS_8B10B_DISP_ERR:
1479 case TRANS_RX_ERR_WITH_RXFRAME_HAVE_ERRPRM:
1480 case TRANS_RX_ERR_WITH_RXFIS_DECODE_ERROR:
1481 case TRANS_RX_ERR_WITH_RXFIS_CRC_ERR:
1482 case TRANS_RX_ERR_WITH_RXFRAME_LENGTH_OVERRUN:
1483 case TRANS_RX_ERR_WITH_RXFIS_RX_SYNCP:
1484 case TRANS_RX_ERR_WITH_CLOSE_NORMAL:
1485 case TRANS_RX_ERR_WITH_CLOSE_PHY_DISABLE:
1486 case TRANS_RX_ERR_WITH_CLOSE_DWS_TIMEOUT:
1487 case TRANS_RX_ERR_WITH_CLOSE_COMINIT:
1488 case TRANS_RX_ERR_WITH_DATA_LEN0:
1489 case TRANS_RX_ERR_WITH_BAD_HASH:
1490 case TRANS_RX_XRDY_WLEN_ZERO_ERR:
1491 case TRANS_RX_SSP_FRM_LEN_ERR:
1492 case SIPC_RX_FIS_STATUS_ERR_BIT_VLD:
1493 case SIPC_RX_PIO_WRSETUP_STATUS_DRQ_ERR:
1494 case SIPC_RX_FIS_STATUS_BSY_BIT_ERR:
1495 case SIPC_RX_WRSETUP_LEN_ODD_ERR:
1496 case SIPC_RX_WRSETUP_LEN_ZERO_ERR:
1497 case SIPC_RX_WRDATA_LEN_NOT_MATCH_ERR:
1498 case SIPC_RX_SATA_UNEXP_FIS_ERR:
1499 case DMA_RX_SATA_FRAME_TYPE_ERR:
1500 case DMA_RX_UNEXP_RDFRAME_ERR:
1501 case DMA_RX_PIO_DATA_LEN_ERR:
1502 case DMA_RX_RDSETUP_STATUS_ERR:
1503 case DMA_RX_RDSETUP_STATUS_DRQ_ERR:
1504 case DMA_RX_RDSETUP_STATUS_BSY_ERR:
1505 case DMA_RX_RDSETUP_LEN_ODD_ERR:
1506 case DMA_RX_RDSETUP_LEN_ZERO_ERR:
1507 case DMA_RX_RDSETUP_LEN_OVER_ERR:
1508 case DMA_RX_RDSETUP_OFFSET_ERR:
1509 case DMA_RX_RDSETUP_ACTIVE_ERR:
1510 case DMA_RX_RDSETUP_ESTATUS_ERR:
1511 case DMA_RX_UNKNOWN_FRM_ERR:
1513 ts->stat = SAS_OPEN_REJECT;
1518 ts->stat = SAS_PROTO_RESPONSE;
1522 sata_done_v2_hw(hisi_hba, task, slot);
1531 slot_complete_v2_hw(struct hisi_hba *hisi_hba, struct hisi_sas_slot *slot,
1534 struct sas_task *task = slot->task;
1535 struct hisi_sas_device *sas_dev;
1536 struct device *dev = &hisi_hba->pdev->dev;
1537 struct task_status_struct *ts;
1538 struct domain_device *device;
1539 enum exec_status sts;
1540 struct hisi_sas_complete_v2_hdr *complete_queue =
1541 hisi_hba->complete_hdr[slot->cmplt_queue];
1542 struct hisi_sas_complete_v2_hdr *complete_hdr =
1543 &complete_queue[slot->cmplt_queue_slot];
1545 if (unlikely(!task || !task->lldd_task || !task->dev))
1548 ts = &task->task_status;
1550 sas_dev = device->lldd_dev;
1552 task->task_state_flags &=
1553 ~(SAS_TASK_STATE_PENDING | SAS_TASK_AT_INITIATOR);
1554 task->task_state_flags |= SAS_TASK_STATE_DONE;
1556 memset(ts, 0, sizeof(*ts));
1557 ts->resp = SAS_TASK_COMPLETE;
1559 if (unlikely(!sas_dev || abort)) {
1561 dev_dbg(dev, "slot complete: port has not device\n");
1562 ts->stat = SAS_PHY_DOWN;
1566 if ((complete_hdr->dw0 & CMPLT_HDR_ERX_MSK) &&
1567 (!(complete_hdr->dw0 & CMPLT_HDR_RSPNS_XFRD_MSK))) {
1569 slot_err_v2_hw(hisi_hba, task, slot);
1570 if (unlikely(slot->abort)) {
1571 queue_work(hisi_hba->wq, &slot->abort_slot);
1572 /* immediately return and do not complete */
1578 switch (task->task_proto) {
1579 case SAS_PROTOCOL_SSP:
1581 struct ssp_response_iu *iu = slot->status_buffer +
1582 sizeof(struct hisi_sas_err_record);
1584 sas_ssp_task_response(dev, task, iu);
1587 case SAS_PROTOCOL_SMP:
1589 struct scatterlist *sg_resp = &task->smp_task.smp_resp;
1592 ts->stat = SAM_STAT_GOOD;
1593 to = kmap_atomic(sg_page(sg_resp));
1595 dma_unmap_sg(dev, &task->smp_task.smp_resp, 1,
1597 dma_unmap_sg(dev, &task->smp_task.smp_req, 1,
1599 memcpy(to + sg_resp->offset,
1600 slot->status_buffer +
1601 sizeof(struct hisi_sas_err_record),
1602 sg_dma_len(sg_resp));
1606 case SAS_PROTOCOL_SATA:
1607 case SAS_PROTOCOL_STP:
1608 case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP:
1610 ts->stat = SAM_STAT_GOOD;
1611 sata_done_v2_hw(hisi_hba, task, slot);
1615 ts->stat = SAM_STAT_CHECK_CONDITION;
1619 if (!slot->port->port_attached) {
1620 dev_err(dev, "slot complete: port %d has removed\n",
1621 slot->port->sas_port.id);
1622 ts->stat = SAS_PHY_DOWN;
1626 if (sas_dev && sas_dev->running_req)
1627 sas_dev->running_req--;
1629 hisi_sas_slot_task_free(hisi_hba, task, slot);
1632 if (task->task_done)
1633 task->task_done(task);
1638 static u8 get_ata_protocol(u8 cmd, int direction)
1641 case ATA_CMD_FPDMA_WRITE:
1642 case ATA_CMD_FPDMA_READ:
1643 case ATA_CMD_FPDMA_RECV:
1644 case ATA_CMD_FPDMA_SEND:
1645 case ATA_CMD_NCQ_NON_DATA:
1646 return SATA_PROTOCOL_FPDMA;
1648 case ATA_CMD_ID_ATA:
1649 case ATA_CMD_PMP_READ:
1650 case ATA_CMD_READ_LOG_EXT:
1651 case ATA_CMD_PIO_READ:
1652 case ATA_CMD_PIO_READ_EXT:
1653 case ATA_CMD_PMP_WRITE:
1654 case ATA_CMD_WRITE_LOG_EXT:
1655 case ATA_CMD_PIO_WRITE:
1656 case ATA_CMD_PIO_WRITE_EXT:
1657 return SATA_PROTOCOL_PIO;
1660 case ATA_CMD_READ_EXT:
1661 case ATA_CMD_READ_LOG_DMA_EXT:
1663 case ATA_CMD_WRITE_EXT:
1664 case ATA_CMD_WRITE_QUEUED:
1665 case ATA_CMD_WRITE_LOG_DMA_EXT:
1666 return SATA_PROTOCOL_DMA;
1668 case ATA_CMD_DOWNLOAD_MICRO:
1669 case ATA_CMD_DEV_RESET:
1670 case ATA_CMD_CHK_POWER:
1672 case ATA_CMD_FLUSH_EXT:
1673 case ATA_CMD_VERIFY:
1674 case ATA_CMD_VERIFY_EXT:
1675 case ATA_CMD_SET_FEATURES:
1676 case ATA_CMD_STANDBY:
1677 case ATA_CMD_STANDBYNOW1:
1678 return SATA_PROTOCOL_NONDATA;
1680 if (direction == DMA_NONE)
1681 return SATA_PROTOCOL_NONDATA;
1682 return SATA_PROTOCOL_PIO;
1686 static int get_ncq_tag_v2_hw(struct sas_task *task, u32 *tag)
1688 struct ata_queued_cmd *qc = task->uldd_task;
1691 if (qc->tf.command == ATA_CMD_FPDMA_WRITE ||
1692 qc->tf.command == ATA_CMD_FPDMA_READ) {
1700 static int prep_ata_v2_hw(struct hisi_hba *hisi_hba,
1701 struct hisi_sas_slot *slot)
1703 struct sas_task *task = slot->task;
1704 struct domain_device *device = task->dev;
1705 struct domain_device *parent_dev = device->parent;
1706 struct hisi_sas_device *sas_dev = device->lldd_dev;
1707 struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
1708 struct hisi_sas_port *port = device->port->lldd_port;
1710 int has_data = 0, rc = 0, hdr_tag = 0;
1711 u32 dw1 = 0, dw2 = 0;
1715 hdr->dw0 = cpu_to_le32(port->id << CMD_HDR_PORT_OFF);
1716 if (parent_dev && DEV_IS_EXPANDER(parent_dev->dev_type))
1717 hdr->dw0 |= cpu_to_le32(3 << CMD_HDR_CMD_OFF);
1719 hdr->dw0 |= cpu_to_le32(4 << CMD_HDR_CMD_OFF);
1722 switch (task->data_dir) {
1725 dw1 |= DIR_TO_DEVICE << CMD_HDR_DIR_OFF;
1727 case DMA_FROM_DEVICE:
1729 dw1 |= DIR_TO_INI << CMD_HDR_DIR_OFF;
1732 dw1 &= ~CMD_HDR_DIR_MSK;
1735 if (0 == task->ata_task.fis.command)
1736 dw1 |= 1 << CMD_HDR_RESET_OFF;
1738 dw1 |= (get_ata_protocol(task->ata_task.fis.command, task->data_dir))
1739 << CMD_HDR_FRAME_TYPE_OFF;
1740 dw1 |= sas_dev->device_id << CMD_HDR_DEV_ID_OFF;
1741 hdr->dw1 = cpu_to_le32(dw1);
1744 if (task->ata_task.use_ncq && get_ncq_tag_v2_hw(task, &hdr_tag)) {
1745 task->ata_task.fis.sector_count |= (u8) (hdr_tag << 3);
1746 dw2 |= hdr_tag << CMD_HDR_NCQ_TAG_OFF;
1749 dw2 |= (HISI_SAS_MAX_STP_RESP_SZ / 4) << CMD_HDR_CFL_OFF |
1750 2 << CMD_HDR_SG_MOD_OFF;
1751 hdr->dw2 = cpu_to_le32(dw2);
1754 hdr->transfer_tags = cpu_to_le32(slot->idx);
1757 rc = prep_prd_sge_v2_hw(hisi_hba, slot, hdr, task->scatter,
1764 hdr->data_transfer_len = cpu_to_le32(task->total_xfer_len);
1765 hdr->cmd_table_addr = cpu_to_le64(slot->command_table_dma);
1766 hdr->sts_buffer_addr = cpu_to_le64(slot->status_buffer_dma);
1768 buf_cmd = slot->command_table;
1770 if (likely(!task->ata_task.device_control_reg_update))
1771 task->ata_task.fis.flags |= 0x80; /* C=1: update ATA cmd reg */
1772 /* fill in command FIS */
1773 memcpy(buf_cmd, &task->ata_task.fis, sizeof(struct host_to_dev_fis));
1778 static int phy_up_v2_hw(int phy_no, struct hisi_hba *hisi_hba)
1781 u32 context, port_id, link_rate, hard_phy_linkrate;
1782 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
1783 struct asd_sas_phy *sas_phy = &phy->sas_phy;
1784 struct device *dev = &hisi_hba->pdev->dev;
1785 u32 *frame_rcvd = (u32 *)sas_phy->frame_rcvd;
1786 struct sas_identify_frame *id = (struct sas_identify_frame *)frame_rcvd;
1788 hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_PHY_ENA_MSK, 1);
1790 /* Check for SATA dev */
1791 context = hisi_sas_read32(hisi_hba, PHY_CONTEXT);
1792 if (context & (1 << phy_no))
1796 u32 port_state = hisi_sas_read32(hisi_hba, PORT_STATE);
1798 port_id = (port_state & PORT_STATE_PHY8_PORT_NUM_MSK) >>
1799 PORT_STATE_PHY8_PORT_NUM_OFF;
1800 link_rate = (port_state & PORT_STATE_PHY8_CONN_RATE_MSK) >>
1801 PORT_STATE_PHY8_CONN_RATE_OFF;
1803 port_id = hisi_sas_read32(hisi_hba, PHY_PORT_NUM_MA);
1804 port_id = (port_id >> (4 * phy_no)) & 0xf;
1805 link_rate = hisi_sas_read32(hisi_hba, PHY_CONN_RATE);
1806 link_rate = (link_rate >> (phy_no * 4)) & 0xf;
1809 if (port_id == 0xf) {
1810 dev_err(dev, "phyup: phy%d invalid portid\n", phy_no);
1815 for (i = 0; i < 6; i++) {
1816 u32 idaf = hisi_sas_phy_read32(hisi_hba, phy_no,
1817 RX_IDAF_DWORD0 + (i * 4));
1818 frame_rcvd[i] = __swab32(idaf);
1821 /* Get the linkrates */
1822 link_rate = hisi_sas_read32(hisi_hba, PHY_CONN_RATE);
1823 link_rate = (link_rate >> (phy_no * 4)) & 0xf;
1824 sas_phy->linkrate = link_rate;
1825 hard_phy_linkrate = hisi_sas_phy_read32(hisi_hba, phy_no,
1827 phy->maximum_linkrate = hard_phy_linkrate & 0xf;
1828 phy->minimum_linkrate = (hard_phy_linkrate >> 4) & 0xf;
1830 sas_phy->oob_mode = SAS_OOB_MODE;
1831 memcpy(sas_phy->attached_sas_addr, &id->sas_addr, SAS_ADDR_SIZE);
1832 dev_info(dev, "phyup: phy%d link_rate=%d\n", phy_no, link_rate);
1833 phy->port_id = port_id;
1834 phy->phy_type &= ~(PORT_TYPE_SAS | PORT_TYPE_SATA);
1835 phy->phy_type |= PORT_TYPE_SAS;
1836 phy->phy_attached = 1;
1837 phy->identify.device_type = id->dev_type;
1838 phy->frame_rcvd_size = sizeof(struct sas_identify_frame);
1839 if (phy->identify.device_type == SAS_END_DEVICE)
1840 phy->identify.target_port_protocols =
1842 else if (phy->identify.device_type != SAS_PHY_UNUSED)
1843 phy->identify.target_port_protocols =
1845 queue_work(hisi_hba->wq, &phy->phyup_ws);
1848 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0,
1849 CHL_INT0_SL_PHY_ENABLE_MSK);
1850 hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_PHY_ENA_MSK, 0);
1855 static int phy_down_v2_hw(int phy_no, struct hisi_hba *hisi_hba)
1858 u32 phy_cfg, phy_state;
1860 hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_NOT_RDY_MSK, 1);
1862 phy_cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG);
1864 phy_state = hisi_sas_read32(hisi_hba, PHY_STATE);
1866 hisi_sas_phy_down(hisi_hba, phy_no, (phy_state & 1 << phy_no) ? 1 : 0);
1868 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0, CHL_INT0_NOT_RDY_MSK);
1869 hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_NOT_RDY_MSK, 0);
1874 static irqreturn_t int_phy_updown_v2_hw(int irq_no, void *p)
1876 struct hisi_hba *hisi_hba = p;
1879 irqreturn_t res = IRQ_HANDLED;
1881 irq_msk = (hisi_sas_read32(hisi_hba, HGC_INVLD_DQE_INFO)
1882 >> HGC_INVLD_DQE_INFO_FB_CH0_OFF) & 0x1ff;
1885 u32 irq_value = hisi_sas_phy_read32(hisi_hba, phy_no,
1888 if (irq_value & CHL_INT0_SL_PHY_ENABLE_MSK)
1890 if (phy_up_v2_hw(phy_no, hisi_hba)) {
1895 if (irq_value & CHL_INT0_NOT_RDY_MSK)
1897 if (phy_down_v2_hw(phy_no, hisi_hba)) {
1910 static void phy_bcast_v2_hw(int phy_no, struct hisi_hba *hisi_hba)
1912 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
1913 struct asd_sas_phy *sas_phy = &phy->sas_phy;
1914 struct sas_ha_struct *sas_ha = &hisi_hba->sha;
1916 hisi_sas_phy_write32(hisi_hba, phy_no, SL_RX_BCAST_CHK_MSK, 1);
1917 sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD);
1918 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0,
1919 CHL_INT0_SL_RX_BCST_ACK_MSK);
1920 hisi_sas_phy_write32(hisi_hba, phy_no, SL_RX_BCAST_CHK_MSK, 0);
1923 static irqreturn_t int_chnl_int_v2_hw(int irq_no, void *p)
1925 struct hisi_hba *hisi_hba = p;
1926 struct device *dev = &hisi_hba->pdev->dev;
1927 u32 ent_msk, ent_tmp, irq_msk;
1930 ent_msk = hisi_sas_read32(hisi_hba, ENT_INT_SRC_MSK3);
1932 ent_msk |= ENT_INT_SRC_MSK3_ENT95_MSK_MSK;
1933 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, ent_msk);
1935 irq_msk = (hisi_sas_read32(hisi_hba, HGC_INVLD_DQE_INFO) >>
1936 HGC_INVLD_DQE_INFO_FB_CH3_OFF) & 0x1ff;
1939 if (irq_msk & (1 << phy_no)) {
1940 u32 irq_value0 = hisi_sas_phy_read32(hisi_hba, phy_no,
1942 u32 irq_value1 = hisi_sas_phy_read32(hisi_hba, phy_no,
1944 u32 irq_value2 = hisi_sas_phy_read32(hisi_hba, phy_no,
1948 if (irq_value1 & (CHL_INT1_DMAC_RX_ECC_ERR_MSK |
1949 CHL_INT1_DMAC_TX_ECC_ERR_MSK))
1950 panic("%s: DMAC RX/TX ecc bad error! (0x%x)",
1951 dev_name(dev), irq_value1);
1953 hisi_sas_phy_write32(hisi_hba, phy_no,
1954 CHL_INT1, irq_value1);
1958 hisi_sas_phy_write32(hisi_hba, phy_no,
1959 CHL_INT2, irq_value2);
1963 if (irq_value0 & CHL_INT0_SL_RX_BCST_ACK_MSK)
1964 phy_bcast_v2_hw(phy_no, hisi_hba);
1966 hisi_sas_phy_write32(hisi_hba, phy_no,
1967 CHL_INT0, irq_value0
1968 & (~CHL_INT0_HOTPLUG_TOUT_MSK)
1969 & (~CHL_INT0_SL_PHY_ENABLE_MSK)
1970 & (~CHL_INT0_NOT_RDY_MSK));
1973 irq_msk &= ~(1 << phy_no);
1977 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, ent_tmp);
1982 static irqreturn_t cq_interrupt_v2_hw(int irq_no, void *p)
1984 struct hisi_sas_cq *cq = p;
1985 struct hisi_hba *hisi_hba = cq->hisi_hba;
1986 struct hisi_sas_slot *slot;
1987 struct hisi_sas_itct *itct;
1988 struct hisi_sas_complete_v2_hdr *complete_queue;
1989 u32 irq_value, rd_point, wr_point, dev_id;
1992 complete_queue = hisi_hba->complete_hdr[queue];
1993 irq_value = hisi_sas_read32(hisi_hba, OQ_INT_SRC);
1995 hisi_sas_write32(hisi_hba, OQ_INT_SRC, 1 << queue);
1997 rd_point = hisi_sas_read32(hisi_hba, COMPL_Q_0_RD_PTR +
1999 wr_point = hisi_sas_read32(hisi_hba, COMPL_Q_0_WR_PTR +
2002 while (rd_point != wr_point) {
2003 struct hisi_sas_complete_v2_hdr *complete_hdr;
2006 complete_hdr = &complete_queue[rd_point];
2008 /* Check for NCQ completion */
2009 if (complete_hdr->act) {
2010 u32 act_tmp = complete_hdr->act;
2011 int ncq_tag_count = ffs(act_tmp);
2013 dev_id = (complete_hdr->dw1 & CMPLT_HDR_DEV_ID_MSK) >>
2014 CMPLT_HDR_DEV_ID_OFF;
2015 itct = &hisi_hba->itct[dev_id];
2017 /* The NCQ tags are held in the itct header */
2018 while (ncq_tag_count) {
2019 __le64 *ncq_tag = &itct->qw4_15[0];
2022 iptt = (ncq_tag[ncq_tag_count / 5]
2023 >> (ncq_tag_count % 5) * 12) & 0xfff;
2025 slot = &hisi_hba->slot_info[iptt];
2026 slot->cmplt_queue_slot = rd_point;
2027 slot->cmplt_queue = queue;
2028 slot_complete_v2_hw(hisi_hba, slot, 0);
2030 act_tmp &= ~(1 << ncq_tag_count);
2031 ncq_tag_count = ffs(act_tmp);
2034 iptt = (complete_hdr->dw1) & CMPLT_HDR_IPTT_MSK;
2035 slot = &hisi_hba->slot_info[iptt];
2036 slot->cmplt_queue_slot = rd_point;
2037 slot->cmplt_queue = queue;
2038 slot_complete_v2_hw(hisi_hba, slot, 0);
2041 if (++rd_point >= HISI_SAS_QUEUE_SLOTS)
2045 /* update rd_point */
2046 hisi_sas_write32(hisi_hba, COMPL_Q_0_RD_PTR + (0x14 * queue), rd_point);
2050 static irqreturn_t sata_int_v2_hw(int irq_no, void *p)
2052 struct hisi_sas_phy *phy = p;
2053 struct hisi_hba *hisi_hba = phy->hisi_hba;
2054 struct asd_sas_phy *sas_phy = &phy->sas_phy;
2055 struct device *dev = &hisi_hba->pdev->dev;
2056 struct hisi_sas_initial_fis *initial_fis;
2057 struct dev_to_host_fis *fis;
2058 u32 ent_tmp, ent_msk, ent_int, port_id, link_rate, hard_phy_linkrate;
2059 irqreturn_t res = IRQ_HANDLED;
2060 u8 attached_sas_addr[SAS_ADDR_SIZE] = {0};
2063 phy_no = sas_phy->id;
2064 initial_fis = &hisi_hba->initial_fis[phy_no];
2065 fis = &initial_fis->fis;
2067 offset = 4 * (phy_no / 4);
2068 ent_msk = hisi_sas_read32(hisi_hba, ENT_INT_SRC_MSK1 + offset);
2069 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1 + offset,
2070 ent_msk | 1 << ((phy_no % 4) * 8));
2072 ent_int = hisi_sas_read32(hisi_hba, ENT_INT_SRC1 + offset);
2073 ent_tmp = ent_int & (1 << (ENT_INT_SRC1_D2H_FIS_CH1_OFF *
2075 ent_int >>= ENT_INT_SRC1_D2H_FIS_CH1_OFF * (phy_no % 4);
2076 if ((ent_int & ENT_INT_SRC1_D2H_FIS_CH0_MSK) == 0) {
2077 dev_warn(dev, "sata int: phy%d did not receive FIS\n", phy_no);
2082 if (unlikely(phy_no == 8)) {
2083 u32 port_state = hisi_sas_read32(hisi_hba, PORT_STATE);
2085 port_id = (port_state & PORT_STATE_PHY8_PORT_NUM_MSK) >>
2086 PORT_STATE_PHY8_PORT_NUM_OFF;
2087 link_rate = (port_state & PORT_STATE_PHY8_CONN_RATE_MSK) >>
2088 PORT_STATE_PHY8_CONN_RATE_OFF;
2090 port_id = hisi_sas_read32(hisi_hba, PHY_PORT_NUM_MA);
2091 port_id = (port_id >> (4 * phy_no)) & 0xf;
2092 link_rate = hisi_sas_read32(hisi_hba, PHY_CONN_RATE);
2093 link_rate = (link_rate >> (phy_no * 4)) & 0xf;
2096 if (port_id == 0xf) {
2097 dev_err(dev, "sata int: phy%d invalid portid\n", phy_no);
2102 sas_phy->linkrate = link_rate;
2103 hard_phy_linkrate = hisi_sas_phy_read32(hisi_hba, phy_no,
2105 phy->maximum_linkrate = hard_phy_linkrate & 0xf;
2106 phy->minimum_linkrate = (hard_phy_linkrate >> 4) & 0xf;
2108 sas_phy->oob_mode = SATA_OOB_MODE;
2109 /* Make up some unique SAS address */
2110 attached_sas_addr[0] = 0x50;
2111 attached_sas_addr[7] = phy_no;
2112 memcpy(sas_phy->attached_sas_addr, attached_sas_addr, SAS_ADDR_SIZE);
2113 memcpy(sas_phy->frame_rcvd, fis, sizeof(struct dev_to_host_fis));
2114 dev_info(dev, "sata int phyup: phy%d link_rate=%d\n", phy_no, link_rate);
2115 phy->phy_type &= ~(PORT_TYPE_SAS | PORT_TYPE_SATA);
2116 phy->port_id = port_id;
2117 phy->phy_type |= PORT_TYPE_SATA;
2118 phy->phy_attached = 1;
2119 phy->identify.device_type = SAS_SATA_DEV;
2120 phy->frame_rcvd_size = sizeof(struct dev_to_host_fis);
2121 phy->identify.target_port_protocols = SAS_PROTOCOL_SATA;
2122 queue_work(hisi_hba->wq, &phy->phyup_ws);
2125 hisi_sas_write32(hisi_hba, ENT_INT_SRC1 + offset, ent_tmp);
2126 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1 + offset, ent_msk);
2131 static irq_handler_t phy_interrupts[HISI_SAS_PHY_INT_NR] = {
2132 int_phy_updown_v2_hw,
2137 * There is a limitation in the hip06 chipset that we need
2138 * to map in all mbigen interrupts, even if they are not used.
2140 static int interrupt_init_v2_hw(struct hisi_hba *hisi_hba)
2142 struct platform_device *pdev = hisi_hba->pdev;
2143 struct device *dev = &pdev->dev;
2144 int i, irq, rc, irq_map[128];
2147 for (i = 0; i < 128; i++)
2148 irq_map[i] = platform_get_irq(pdev, i);
2150 for (i = 0; i < HISI_SAS_PHY_INT_NR; i++) {
2153 irq = irq_map[idx + 1]; /* Phy up/down is irq1 */
2155 dev_err(dev, "irq init: fail map phy interrupt %d\n",
2160 rc = devm_request_irq(dev, irq, phy_interrupts[i], 0,
2161 DRV_NAME " phy", hisi_hba);
2163 dev_err(dev, "irq init: could not request "
2164 "phy interrupt %d, rc=%d\n",
2170 for (i = 0; i < hisi_hba->n_phy; i++) {
2171 struct hisi_sas_phy *phy = &hisi_hba->phy[i];
2172 int idx = i + 72; /* First SATA interrupt is irq72 */
2176 dev_err(dev, "irq init: fail map phy interrupt %d\n",
2181 rc = devm_request_irq(dev, irq, sata_int_v2_hw, 0,
2182 DRV_NAME " sata", phy);
2184 dev_err(dev, "irq init: could not request "
2185 "sata interrupt %d, rc=%d\n",
2191 for (i = 0; i < hisi_hba->queue_count; i++) {
2192 int idx = i + 96; /* First cq interrupt is irq96 */
2197 "irq init: could not map cq interrupt %d\n",
2201 rc = devm_request_irq(dev, irq, cq_interrupt_v2_hw, 0,
2202 DRV_NAME " cq", &hisi_hba->cq[i]);
2205 "irq init: could not request cq interrupt %d, rc=%d\n",
2214 static int hisi_sas_v2_init(struct hisi_hba *hisi_hba)
2218 rc = hw_init_v2_hw(hisi_hba);
2222 rc = interrupt_init_v2_hw(hisi_hba);
2226 phys_init_v2_hw(hisi_hba);
2231 static const struct hisi_sas_hw hisi_sas_v2_hw = {
2232 .hw_init = hisi_sas_v2_init,
2233 .setup_itct = setup_itct_v2_hw,
2234 .slot_index_alloc = slot_index_alloc_quirk_v2_hw,
2235 .alloc_dev = alloc_dev_quirk_v2_hw,
2236 .sl_notify = sl_notify_v2_hw,
2237 .get_wideport_bitmap = get_wideport_bitmap_v2_hw,
2238 .free_device = free_device_v2_hw,
2239 .prep_smp = prep_smp_v2_hw,
2240 .prep_ssp = prep_ssp_v2_hw,
2241 .prep_stp = prep_ata_v2_hw,
2242 .get_free_slot = get_free_slot_v2_hw,
2243 .start_delivery = start_delivery_v2_hw,
2244 .slot_complete = slot_complete_v2_hw,
2245 .phy_enable = enable_phy_v2_hw,
2246 .phy_disable = disable_phy_v2_hw,
2247 .phy_hard_reset = phy_hard_reset_v2_hw,
2248 .max_command_entries = HISI_SAS_COMMAND_ENTRIES_V2_HW,
2249 .complete_hdr_size = sizeof(struct hisi_sas_complete_v2_hdr),
2252 static int hisi_sas_v2_probe(struct platform_device *pdev)
2254 return hisi_sas_probe(pdev, &hisi_sas_v2_hw);
2257 static int hisi_sas_v2_remove(struct platform_device *pdev)
2259 return hisi_sas_remove(pdev);
2262 static const struct of_device_id sas_v2_of_match[] = {
2263 { .compatible = "hisilicon,hip06-sas-v2",},
2266 MODULE_DEVICE_TABLE(of, sas_v2_of_match);
2268 static const struct acpi_device_id sas_v2_acpi_match[] = {
2273 MODULE_DEVICE_TABLE(acpi, sas_v2_acpi_match);
2275 static struct platform_driver hisi_sas_v2_driver = {
2276 .probe = hisi_sas_v2_probe,
2277 .remove = hisi_sas_v2_remove,
2280 .of_match_table = sas_v2_of_match,
2281 .acpi_match_table = ACPI_PTR(sas_v2_acpi_match),
2285 module_platform_driver(hisi_sas_v2_driver);
2287 MODULE_LICENSE("GPL");
2288 MODULE_AUTHOR("John Garry <john.garry@huawei.com>");
2289 MODULE_DESCRIPTION("HISILICON SAS controller v2 hw driver");
2290 MODULE_ALIAS("platform:" DRV_NAME);