drivers/scsi/megaraid/megaraid_sas_fusion.h

   1 /*
   2  *  Linux MegaRAID driver for SAS based RAID controllers
   3  *
   4  *  Copyright (c) 2009-2012  LSI Corporation.
   5  *
   6  *  This program is free software; you can redistribute it and/or
   7  *  modify it under the terms of the GNU General Public License
   8  *  as published by the Free Software Foundation; either version 2
   9  *  of the License, or (at your option) any later version.
  10  *
  11  *  This program is distributed in the hope that it will be useful,
  12  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  *  GNU General Public License for more details.
  15  *
  16  *  You should have received a copy of the GNU General Public License
  17  *  along with this program; if not, write to the Free Software
  18  *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  19  *
  20  *  FILE: megaraid_sas_fusion.h
  21  *
  22  *  Authors: LSI Corporation
  23  *           Manoj Jose
  24  *           Sumant Patro
  25  *
  26  *  Send feedback to: <megaraidlinux@lsi.com>
  27  *
  28  *  Mail to: LSI Corporation, 1621 Barber Lane, Milpitas, CA 95035
  29  *     ATTN: Linuxraid
  30  */
  31
  32 #ifndef _MEGARAID_SAS_FUSION_H_
  33 #define _MEGARAID_SAS_FUSION_H_
  34
  35 /* Fusion defines */
  36 #define MEGASAS_MAX_SZ_CHAIN_FRAME 1024
  37 #define MFI_FUSION_ENABLE_INTERRUPT_MASK (0x00000009)
  38 #define MEGA_MPI2_RAID_DEFAULT_IO_FRAME_SIZE 256
  39 #define MEGASAS_MPI2_FUNCTION_PASSTHRU_IO_REQUEST   0xF0
  40 #define MEGASAS_MPI2_FUNCTION_LD_IO_REQUEST         0xF1
  41 #define MEGASAS_LOAD_BALANCE_FLAG                   0x1
  42 #define MEGASAS_DCMD_MBOX_PEND_FLAG                 0x1
  43 #define HOST_DIAG_WRITE_ENABLE                      0x80
  44 #define HOST_DIAG_RESET_ADAPTER                     0x4
  45 #define MEGASAS_FUSION_MAX_RESET_TRIES              3
  46 #define MAX_MSIX_QUEUES_FUSION                      128
  47
  48 /* Invader defines */
  49 #define MPI2_TYPE_CUDA                              0x2
  50 #define MPI25_SAS_DEVICE0_FLAGS_ENABLED_FAST_PATH   0x4000
  51 #define MR_RL_FLAGS_GRANT_DESTINATION_CPU0          0x00
  52 #define MR_RL_FLAGS_GRANT_DESTINATION_CPU1          0x10
  53 #define MR_RL_FLAGS_GRANT_DESTINATION_CUDA          0x80
  54 #define MR_RL_FLAGS_SEQ_NUM_ENABLE                  0x8
  55
  56 /* T10 PI defines */
  57 #define MR_PROT_INFO_TYPE_CONTROLLER                0x8
  58 #define MEGASAS_SCSI_VARIABLE_LENGTH_CMD            0x7f
  59 #define MEGASAS_SCSI_SERVICE_ACTION_READ32          0x9
  60 #define MEGASAS_SCSI_SERVICE_ACTION_WRITE32         0xB
  61 #define MEGASAS_SCSI_ADDL_CDB_LEN                   0x18
  62 #define MEGASAS_RD_WR_PROTECT_CHECK_ALL             0x20
  63 #define MEGASAS_RD_WR_PROTECT_CHECK_NONE            0x60
  64
  65 #define MPI2_SUP_REPLY_POST_HOST_INDEX_OFFSET   (0x0000030C)
  66 #define MPI2_REPLY_POST_HOST_INDEX_OFFSET       (0x0000006C)
  67
  68 /*
  69  * Raid context flags
  70  */
  71
  72 #define MR_RAID_CTX_RAID_FLAGS_IO_SUB_TYPE_SHIFT   0x4
  73 #define MR_RAID_CTX_RAID_FLAGS_IO_SUB_TYPE_MASK    0x30
  74 enum MR_RAID_FLAGS_IO_SUB_TYPE {
  75         MR_RAID_FLAGS_IO_SUB_TYPE_NONE = 0,
  76         MR_RAID_FLAGS_IO_SUB_TYPE_SYSTEM_PD = 1,
  77 };
  78
  79 /*
  80  * Request descriptor types
  81  */
  82 #define MEGASAS_REQ_DESCRIPT_FLAGS_LD_IO           0x7
  83 #define MEGASAS_REQ_DESCRIPT_FLAGS_MFA             0x1
  84 #define MEGASAS_REQ_DESCRIPT_FLAGS_NO_LOCK         0x2
  85 #define MEGASAS_REQ_DESCRIPT_FLAGS_TYPE_SHIFT      1
  86
  87 #define MEGASAS_FP_CMD_LEN      16
  88 #define MEGASAS_FUSION_IN_RESET 0
  89 #define THRESHOLD_REPLY_COUNT 50
  90
  91 /*
  92  * Raid Context structure which describes MegaRAID specific IO Parameters
  93  * This resides at offset 0x60 where the SGL normally starts in MPT IO Frames
  94  */
  95
  96 struct RAID_CONTEXT {
  97 #if   defined(__BIG_ENDIAN_BITFIELD)
  98         u8      nseg:4;
  99         u8      Type:4;
 100 #else
 101         u8      Type:4;
 102         u8      nseg:4;
 103 #endif
 104         u8      resvd0;
 105         u16     timeoutValue;
 106         u8      regLockFlags;
 107         u8      resvd1;
 108         u16     VirtualDiskTgtId;
 109         u64     regLockRowLBA;
 110         u32     regLockLength;
 111         u16     nextLMId;
 112         u8      exStatus;
 113         u8      status;
 114         u8      RAIDFlags;
 115         u8      numSGE;
 116         u16     configSeqNum;
 117         u8      spanArm;
 118         u8      resvd2[3];
 119 };
 120
 121 #define RAID_CTX_SPANARM_ARM_SHIFT      (0)
 122 #define RAID_CTX_SPANARM_ARM_MASK       (0x1f)
 123
 124 #define RAID_CTX_SPANARM_SPAN_SHIFT     (5)
 125 #define RAID_CTX_SPANARM_SPAN_MASK      (0xE0)
 126
 127 /*
 128  * define region lock types
 129  */
 130 enum REGION_TYPE {
 131         REGION_TYPE_UNUSED       = 0,
 132         REGION_TYPE_SHARED_READ  = 1,
 133         REGION_TYPE_SHARED_WRITE = 2,
 134         REGION_TYPE_EXCLUSIVE    = 3,
 135 };
 136
 137 /* MPI2 defines */
 138 #define MPI2_FUNCTION_IOC_INIT              (0x02) /* IOC Init */
 139 #define MPI2_WHOINIT_HOST_DRIVER            (0x04)
 140 #define MPI2_VERSION_MAJOR                  (0x02)
 141 #define MPI2_VERSION_MINOR                  (0x00)
 142 #define MPI2_VERSION_MAJOR_MASK             (0xFF00)
 143 #define MPI2_VERSION_MAJOR_SHIFT            (8)
 144 #define MPI2_VERSION_MINOR_MASK             (0x00FF)
 145 #define MPI2_VERSION_MINOR_SHIFT            (0)
 146 #define MPI2_VERSION ((MPI2_VERSION_MAJOR << MPI2_VERSION_MAJOR_SHIFT) | \
 147                       MPI2_VERSION_MINOR)
 148 #define MPI2_HEADER_VERSION_UNIT            (0x10)
 149 #define MPI2_HEADER_VERSION_DEV             (0x00)
 150 #define MPI2_HEADER_VERSION_UNIT_MASK       (0xFF00)
 151 #define MPI2_HEADER_VERSION_UNIT_SHIFT      (8)
 152 #define MPI2_HEADER_VERSION_DEV_MASK        (0x00FF)
 153 #define MPI2_HEADER_VERSION_DEV_SHIFT       (0)
 154 #define MPI2_HEADER_VERSION ((MPI2_HEADER_VERSION_UNIT << 8) | \
 155                              MPI2_HEADER_VERSION_DEV)
 156 #define MPI2_IEEE_SGE_FLAGS_IOCPLBNTA_ADDR      (0x03)
 157 #define MPI2_SCSIIO_EEDPFLAGS_INC_PRI_REFTAG        (0x8000)
 158 #define MPI2_SCSIIO_EEDPFLAGS_CHECK_REFTAG          (0x0400)
 159 #define MPI2_SCSIIO_EEDPFLAGS_CHECK_REMOVE_OP       (0x0003)
 160 #define MPI2_SCSIIO_EEDPFLAGS_CHECK_APPTAG          (0x0200)
 161 #define MPI2_SCSIIO_EEDPFLAGS_CHECK_GUARD           (0x0100)
 162 #define MPI2_SCSIIO_EEDPFLAGS_INSERT_OP             (0x0004)
 163 #define MPI2_FUNCTION_SCSI_IO_REQUEST               (0x00) /* SCSI IO */
 164 #define MPI2_REQ_DESCRIPT_FLAGS_HIGH_PRIORITY           (0x06)
 165 #define MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO                 (0x00)
 166 #define MPI2_SGE_FLAGS_64_BIT_ADDRESSING        (0x02)
 167 #define MPI2_SCSIIO_CONTROL_WRITE               (0x01000000)
 168 #define MPI2_SCSIIO_CONTROL_READ                (0x02000000)
 169 #define MPI2_REQ_DESCRIPT_FLAGS_TYPE_MASK       (0x0E)
 170 #define MPI2_RPY_DESCRIPT_FLAGS_UNUSED          (0x0F)
 171 #define MPI2_RPY_DESCRIPT_FLAGS_SCSI_IO_SUCCESS (0x00)
 172 #define MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK       (0x0F)
 173 #define MPI2_WRSEQ_FLUSH_KEY_VALUE              (0x0)
 174 #define MPI2_WRITE_SEQUENCE_OFFSET              (0x00000004)
 175 #define MPI2_WRSEQ_1ST_KEY_VALUE                (0xF)
 176 #define MPI2_WRSEQ_2ND_KEY_VALUE                (0x4)
 177 #define MPI2_WRSEQ_3RD_KEY_VALUE                (0xB)
 178 #define MPI2_WRSEQ_4TH_KEY_VALUE                (0x2)
 179 #define MPI2_WRSEQ_5TH_KEY_VALUE                (0x7)
 180 #define MPI2_WRSEQ_6TH_KEY_VALUE                (0xD)
 181
 182 struct MPI25_IEEE_SGE_CHAIN64 {
 183         u64                     Address;
 184         u32                     Length;
 185         u16                     Reserved1;
 186         u8                      NextChainOffset;
 187         u8                      Flags;
 188 };
 189
 190 struct MPI2_SGE_SIMPLE_UNION {
 191         u32                     FlagsLength;
 192         union {
 193                 u32                 Address32;
 194                 u64                 Address64;
 195         } u;
 196 };
 197
 198 struct MPI2_SCSI_IO_CDB_EEDP32 {
 199         u8                      CDB[20];                    /* 0x00 */
 200         u32                     PrimaryReferenceTag;        /* 0x14 */
 201         u16                     PrimaryApplicationTag;      /* 0x18 */
 202         u16                     PrimaryApplicationTagMask;  /* 0x1A */
 203         u32                     TransferLength;             /* 0x1C */
 204 };
 205
 206 struct MPI2_SGE_CHAIN_UNION {
 207         u16                     Length;
 208         u8                      NextChainOffset;
 209         u8                      Flags;
 210         union {
 211                 u32                 Address32;
 212                 u64                 Address64;
 213         } u;
 214 };
 215
 216 struct MPI2_IEEE_SGE_SIMPLE32 {
 217         u32                     Address;
 218         u32                     FlagsLength;
 219 };
 220
 221 struct MPI2_IEEE_SGE_CHAIN32 {
 222         u32                     Address;
 223         u32                     FlagsLength;
 224 };
 225
 226 struct MPI2_IEEE_SGE_SIMPLE64 {
 227         u64                     Address;
 228         u32                     Length;
 229         u16                     Reserved1;
 230         u8                      Reserved2;
 231         u8                      Flags;
 232 };
 233
 234 struct MPI2_IEEE_SGE_CHAIN64 {
 235         u64                     Address;
 236         u32                     Length;
 237         u16                     Reserved1;
 238         u8                      Reserved2;
 239         u8                      Flags;
 240 };
 241
 242 union MPI2_IEEE_SGE_SIMPLE_UNION {
 243         struct MPI2_IEEE_SGE_SIMPLE32  Simple32;
 244         struct MPI2_IEEE_SGE_SIMPLE64  Simple64;
 245 };
 246
 247 union MPI2_IEEE_SGE_CHAIN_UNION {
 248         struct MPI2_IEEE_SGE_CHAIN32   Chain32;
 249         struct MPI2_IEEE_SGE_CHAIN64   Chain64;
 250 };
 251
 252 union MPI2_SGE_IO_UNION {
 253         struct MPI2_SGE_SIMPLE_UNION       MpiSimple;
 254         struct MPI2_SGE_CHAIN_UNION        MpiChain;
 255         union MPI2_IEEE_SGE_SIMPLE_UNION  IeeeSimple;
 256         union MPI2_IEEE_SGE_CHAIN_UNION   IeeeChain;
 257 };
 258
 259 union MPI2_SCSI_IO_CDB_UNION {
 260         u8                      CDB32[32];
 261         struct MPI2_SCSI_IO_CDB_EEDP32 EEDP32;
 262         struct MPI2_SGE_SIMPLE_UNION SGE;
 263 };
 264
 265 /*
 266  * RAID SCSI IO Request Message
 267  * Total SGE count will be one less than  _MPI2_SCSI_IO_REQUEST
 268  */
 269 struct MPI2_RAID_SCSI_IO_REQUEST {
 270         u16                     DevHandle;                      /* 0x00 */
 271         u8                      ChainOffset;                    /* 0x02 */
 272         u8                      Function;                       /* 0x03 */
 273         u16                     Reserved1;                      /* 0x04 */
 274         u8                      Reserved2;                      /* 0x06 */
 275         u8                      MsgFlags;                       /* 0x07 */
 276         u8                      VP_ID;                          /* 0x08 */
 277         u8                      VF_ID;                          /* 0x09 */
 278         u16                     Reserved3;                      /* 0x0A */
 279         u32                     SenseBufferLowAddress;          /* 0x0C */
 280         u16                     SGLFlags;                       /* 0x10 */
 281         u8                      SenseBufferLength;              /* 0x12 */
 282         u8                      Reserved4;                      /* 0x13 */
 283         u8                      SGLOffset0;                     /* 0x14 */
 284         u8                      SGLOffset1;                     /* 0x15 */
 285         u8                      SGLOffset2;                     /* 0x16 */
 286         u8                      SGLOffset3;                     /* 0x17 */
 287         u32                     SkipCount;                      /* 0x18 */
 288         u32                     DataLength;                     /* 0x1C */
 289         u32                     BidirectionalDataLength;        /* 0x20 */
 290         u16                     IoFlags;                        /* 0x24 */
 291         u16                     EEDPFlags;                      /* 0x26 */
 292         u32                     EEDPBlockSize;                  /* 0x28 */
 293         u32                     SecondaryReferenceTag;          /* 0x2C */
 294         u16                     SecondaryApplicationTag;        /* 0x30 */
 295         u16                     ApplicationTagTranslationMask;  /* 0x32 */
 296         u8                      LUN[8];                         /* 0x34 */
 297         u32                     Control;                        /* 0x3C */
 298         union MPI2_SCSI_IO_CDB_UNION  CDB;                      /* 0x40 */
 299         struct RAID_CONTEXT     RaidContext;                    /* 0x60 */
 300         union MPI2_SGE_IO_UNION       SGL;                      /* 0x80 */
 301 };
 302
 303 /*
 304  * MPT RAID MFA IO Descriptor.
 305  */
 306 struct MEGASAS_RAID_MFA_IO_REQUEST_DESCRIPTOR {
 307 #if   defined(__BIG_ENDIAN_BITFIELD)
 308         u32     MessageAddress1:24; /* bits 31:8*/
 309         u32     RequestFlags:8;
 310 #else
 311         u32     RequestFlags:8;
 312         u32     MessageAddress1:24; /* bits 31:8*/
 313 #endif
 314         u32     MessageAddress2;      /* bits 61:32 */
 315 };
 316
 317 /* Default Request Descriptor */
 318 struct MPI2_DEFAULT_REQUEST_DESCRIPTOR {
 319         u8              RequestFlags;               /* 0x00 */
 320         u8              MSIxIndex;                  /* 0x01 */
 321         u16             SMID;                       /* 0x02 */
 322         u16             LMID;                       /* 0x04 */
 323         u16             DescriptorTypeDependent;    /* 0x06 */
 324 };
 325
 326 /* High Priority Request Descriptor */
 327 struct MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR {
 328         u8              RequestFlags;               /* 0x00 */
 329         u8              MSIxIndex;                  /* 0x01 */
 330         u16             SMID;                       /* 0x02 */
 331         u16             LMID;                       /* 0x04 */
 332         u16             Reserved1;                  /* 0x06 */
 333 };
 334
 335 /* SCSI IO Request Descriptor */
 336 struct MPI2_SCSI_IO_REQUEST_DESCRIPTOR {
 337         u8              RequestFlags;               /* 0x00 */
 338         u8              MSIxIndex;                  /* 0x01 */
 339         u16             SMID;                       /* 0x02 */
 340         u16             LMID;                       /* 0x04 */
 341         u16             DevHandle;                  /* 0x06 */
 342 };
 343
 344 /* SCSI Target Request Descriptor */
 345 struct MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR {
 346         u8              RequestFlags;               /* 0x00 */
 347         u8              MSIxIndex;                  /* 0x01 */
 348         u16             SMID;                       /* 0x02 */
 349         u16             LMID;                       /* 0x04 */
 350         u16             IoIndex;                    /* 0x06 */
 351 };
 352
 353 /* RAID Accelerator Request Descriptor */
 354 struct MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR {
 355         u8              RequestFlags;               /* 0x00 */
 356         u8              MSIxIndex;                  /* 0x01 */
 357         u16             SMID;                       /* 0x02 */
 358         u16             LMID;                       /* 0x04 */
 359         u16             Reserved;                   /* 0x06 */
 360 };
 361
 362 /* union of Request Descriptors */
 363 union MEGASAS_REQUEST_DESCRIPTOR_UNION {
 364         struct MPI2_DEFAULT_REQUEST_DESCRIPTOR             Default;
 365         struct MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR       HighPriority;
 366         struct MPI2_SCSI_IO_REQUEST_DESCRIPTOR             SCSIIO;
 367         struct MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR         SCSITarget;
 368         struct MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR          RAIDAccelerator;
 369         struct MEGASAS_RAID_MFA_IO_REQUEST_DESCRIPTOR      MFAIo;
 370         union {
 371                 struct {
 372                         u32 low;
 373                         u32 high;
 374                 } u;
 375                 u64 Words;
 376         };
 377 };
 378
 379 /* Default Reply Descriptor */
 380 struct MPI2_DEFAULT_REPLY_DESCRIPTOR {
 381         u8              ReplyFlags;                 /* 0x00 */
 382         u8              MSIxIndex;                  /* 0x01 */
 383         u16             DescriptorTypeDependent1;   /* 0x02 */
 384         u32             DescriptorTypeDependent2;   /* 0x04 */
 385 };
 386
 387 /* Address Reply Descriptor */
 388 struct MPI2_ADDRESS_REPLY_DESCRIPTOR {
 389         u8              ReplyFlags;                 /* 0x00 */
 390         u8              MSIxIndex;                  /* 0x01 */
 391         u16             SMID;                       /* 0x02 */
 392         u32             ReplyFrameAddress;          /* 0x04 */
 393 };
 394
 395 /* SCSI IO Success Reply Descriptor */
 396 struct MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR {
 397         u8              ReplyFlags;                 /* 0x00 */
 398         u8              MSIxIndex;                  /* 0x01 */
 399         u16             SMID;                       /* 0x02 */
 400         u16             TaskTag;                    /* 0x04 */
 401         u16             Reserved1;                  /* 0x06 */
 402 };
 403
 404 /* TargetAssist Success Reply Descriptor */
 405 struct MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR {
 406         u8              ReplyFlags;                 /* 0x00 */
 407         u8              MSIxIndex;                  /* 0x01 */
 408         u16             SMID;                       /* 0x02 */
 409         u8              SequenceNumber;             /* 0x04 */
 410         u8              Reserved1;                  /* 0x05 */
 411         u16             IoIndex;                    /* 0x06 */
 412 };
 413
 414 /* Target Command Buffer Reply Descriptor */
 415 struct MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR {
 416         u8              ReplyFlags;                 /* 0x00 */
 417         u8              MSIxIndex;                  /* 0x01 */
 418         u8              VP_ID;                      /* 0x02 */
 419         u8              Flags;                      /* 0x03 */
 420         u16             InitiatorDevHandle;         /* 0x04 */
 421         u16             IoIndex;                    /* 0x06 */
 422 };
 423
 424 /* RAID Accelerator Success Reply Descriptor */
 425 struct MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR {
 426         u8              ReplyFlags;                 /* 0x00 */
 427         u8              MSIxIndex;                  /* 0x01 */
 428         u16             SMID;                       /* 0x02 */
 429         u32             Reserved;                   /* 0x04 */
 430 };
 431
 432 /* union of Reply Descriptors */
 433 union MPI2_REPLY_DESCRIPTORS_UNION {
 434         struct MPI2_DEFAULT_REPLY_DESCRIPTOR                   Default;
 435         struct MPI2_ADDRESS_REPLY_DESCRIPTOR                   AddressReply;
 436         struct MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR           SCSIIOSuccess;
 437         struct MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR TargetAssistSuccess;
 438         struct MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR TargetCommandBuffer;
 439         struct MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR
 440         RAIDAcceleratorSuccess;
 441         u64                                             Words;
 442 };
 443
 444 /* IOCInit Request message */
 445 struct MPI2_IOC_INIT_REQUEST {
 446         u8                      WhoInit;                        /* 0x00 */
 447         u8                      Reserved1;                      /* 0x01 */
 448         u8                      ChainOffset;                    /* 0x02 */
 449         u8                      Function;                       /* 0x03 */
 450         u16                     Reserved2;                      /* 0x04 */
 451         u8                      Reserved3;                      /* 0x06 */
 452         u8                      MsgFlags;                       /* 0x07 */
 453         u8                      VP_ID;                          /* 0x08 */
 454         u8                      VF_ID;                          /* 0x09 */
 455         u16                     Reserved4;                      /* 0x0A */
 456         u16                     MsgVersion;                     /* 0x0C */
 457         u16                     HeaderVersion;                  /* 0x0E */
 458         u32                     Reserved5;                      /* 0x10 */
 459         u16                     Reserved6;                      /* 0x14 */
 460         u8                      Reserved7;                      /* 0x16 */
 461         u8                      HostMSIxVectors;                /* 0x17 */
 462         u16                     Reserved8;                      /* 0x18 */
 463         u16                     SystemRequestFrameSize;         /* 0x1A */
 464         u16                     ReplyDescriptorPostQueueDepth;  /* 0x1C */
 465         u16                     ReplyFreeQueueDepth;            /* 0x1E */
 466         u32                     SenseBufferAddressHigh;         /* 0x20 */
 467         u32                     SystemReplyAddressHigh;         /* 0x24 */
 468         u64                     SystemRequestFrameBaseAddress;  /* 0x28 */
 469         u64                     ReplyDescriptorPostQueueAddress;/* 0x30 */
 470         u64                     ReplyFreeQueueAddress;          /* 0x38 */
 471         u64                     TimeStamp;                      /* 0x40 */
 472 };
 473
 474 /* mrpriv defines */
 475 #define MR_PD_INVALID 0xFFFF
 476 #define MAX_SPAN_DEPTH 8
 477 #define MAX_QUAD_DEPTH  MAX_SPAN_DEPTH
 478 #define MAX_RAIDMAP_SPAN_DEPTH (MAX_SPAN_DEPTH)
 479 #define MAX_ROW_SIZE 32
 480 #define MAX_RAIDMAP_ROW_SIZE (MAX_ROW_SIZE)
 481 #define MAX_LOGICAL_DRIVES 64
 482 #define MAX_LOGICAL_DRIVES_EXT 256
 483 #define MAX_RAIDMAP_LOGICAL_DRIVES (MAX_LOGICAL_DRIVES)
 484 #define MAX_RAIDMAP_VIEWS (MAX_LOGICAL_DRIVES)
 485 #define MAX_ARRAYS 128
 486 #define MAX_RAIDMAP_ARRAYS (MAX_ARRAYS)
 487 #define MAX_ARRAYS_EXT  256
 488 #define MAX_API_ARRAYS_EXT (MAX_ARRAYS_EXT)
 489 #define MAX_PHYSICAL_DEVICES 256
 490 #define MAX_RAIDMAP_PHYSICAL_DEVICES (MAX_PHYSICAL_DEVICES)
 491 #define MR_DCMD_LD_MAP_GET_INFO             0x0300e101
 492 #define MR_DCMD_CTRL_SHARED_HOST_MEM_ALLOC  0x010e8485   /* SR-IOV HB alloc*/
 493 #define MR_DCMD_LD_VF_MAP_GET_ALL_LDS_111   0x03200200
 494 #define MR_DCMD_LD_VF_MAP_GET_ALL_LDS       0x03150200
 495
 496 struct MR_DEV_HANDLE_INFO {
 497         u16     curDevHdl;
 498         u8      validHandles;
 499         u8      reserved;
 500         u16     devHandle[2];
 501 };
 502
 503 struct MR_ARRAY_INFO {
 504         u16      pd[MAX_RAIDMAP_ROW_SIZE];
 505 };
 506
 507 struct MR_QUAD_ELEMENT {
 508         u64     logStart;
 509         u64     logEnd;
 510         u64     offsetInSpan;
 511         u32     diff;
 512         u32     reserved1;
 513 };
 514
 515 struct MR_SPAN_INFO {
 516         u32             noElements;
 517         u32             reserved1;
 518         struct MR_QUAD_ELEMENT quad[MAX_RAIDMAP_SPAN_DEPTH];
 519 };
 520
 521 struct MR_LD_SPAN {
 522         u64      startBlk;
 523         u64      numBlks;
 524         u16      arrayRef;
 525         u8       spanRowSize;
 526         u8       spanRowDataSize;
 527         u8       reserved[4];
 528 };
 529
 530 struct MR_SPAN_BLOCK_INFO {
 531         u64          num_rows;
 532         struct MR_LD_SPAN   span;
 533         struct MR_SPAN_INFO block_span_info;
 534 };
 535
 536 struct MR_LD_RAID {
 537         struct {
 538 #if   defined(__BIG_ENDIAN_BITFIELD)
 539                 u32     reserved4:7;
 540                 u32     fpNonRWCapable:1;
 541                 u32     fpReadAcrossStripe:1;
 542                 u32     fpWriteAcrossStripe:1;
 543                 u32     fpReadCapable:1;
 544                 u32     fpWriteCapable:1;
 545                 u32     encryptionType:8;
 546                 u32     pdPiMode:4;
 547                 u32     ldPiMode:4;
 548                 u32     reserved5:3;
 549                 u32     fpCapable:1;
 550 #else
 551                 u32     fpCapable:1;
 552                 u32     reserved5:3;
 553                 u32     ldPiMode:4;
 554                 u32     pdPiMode:4;
 555                 u32     encryptionType:8;
 556                 u32     fpWriteCapable:1;
 557                 u32     fpReadCapable:1;
 558                 u32     fpWriteAcrossStripe:1;
 559                 u32     fpReadAcrossStripe:1;
 560                 u32     fpNonRWCapable:1;
 561                 u32     reserved4:7;
 562 #endif
 563         } capability;
 564         u32     reserved6;
 565         u64     size;
 566         u8      spanDepth;
 567         u8      level;
 568         u8      stripeShift;
 569         u8      rowSize;
 570         u8      rowDataSize;
 571         u8      writeMode;
 572         u8      PRL;
 573         u8      SRL;
 574         u16     targetId;
 575         u8      ldState;
 576         u8      regTypeReqOnWrite;
 577         u8      modFactor;
 578         u8      regTypeReqOnRead;
 579         u16     seqNum;
 580
 581         struct {
 582                 u32 ldSyncRequired:1;
 583                 u32 reserved:31;
 584         } flags;
 585
 586         u8      LUN[8]; /* 0x24 8 byte LUN field used for SCSI IO's */
 587         u8      fpIoTimeoutForLd;/*0x2C timeout value used by driver in FP IO*/
 588         u8      reserved3[0x80-0x2D]; /* 0x2D */
 589 };
 590
 591 struct MR_LD_SPAN_MAP {
 592         struct MR_LD_RAID          ldRaid;
 593         u8                  dataArmMap[MAX_RAIDMAP_ROW_SIZE];
 594         struct MR_SPAN_BLOCK_INFO  spanBlock[MAX_RAIDMAP_SPAN_DEPTH];
 595 };
 596
 597 struct MR_FW_RAID_MAP {
 598         u32                 totalSize;
 599         union {
 600                 struct {
 601                         u32         maxLd;
 602                         u32         maxSpanDepth;
 603                         u32         maxRowSize;
 604                         u32         maxPdCount;
 605                         u32         maxArrays;
 606                 } validationInfo;
 607                 u32             version[5];
 608         };
 609
 610         u32                 ldCount;
 611         u32                 Reserved1;
 612         u8                  ldTgtIdToLd[MAX_RAIDMAP_LOGICAL_DRIVES+
 613                                         MAX_RAIDMAP_VIEWS];
 614         u8                  fpPdIoTimeoutSec;
 615         u8                  reserved2[7];
 616         struct MR_ARRAY_INFO       arMapInfo[MAX_RAIDMAP_ARRAYS];
 617         struct MR_DEV_HANDLE_INFO  devHndlInfo[MAX_RAIDMAP_PHYSICAL_DEVICES];
 618         struct MR_LD_SPAN_MAP      ldSpanMap[1];
 619 };
 620
 621 struct IO_REQUEST_INFO {
 622         u64 ldStartBlock;
 623         u32 numBlocks;
 624         u16 ldTgtId;
 625         u8 isRead;
 626         u16 devHandle;
 627         u64 pdBlock;
 628         u8 fpOkForIo;
 629         u8 IoforUnevenSpan;
 630         u8 start_span;
 631         u8 reserved;
 632         u64 start_row;
 633         u8  span_arm;   /* span[7:5], arm[4:0] */
 634         u8  pd_after_lb;
 635 };
 636
 637 struct MR_LD_TARGET_SYNC {
 638         u8  targetId;
 639         u8  reserved;
 640         u16 seqNum;
 641 };
 642
 643 #define IEEE_SGE_FLAGS_ADDR_MASK            (0x03)
 644 #define IEEE_SGE_FLAGS_SYSTEM_ADDR          (0x00)
 645 #define IEEE_SGE_FLAGS_IOCDDR_ADDR          (0x01)
 646 #define IEEE_SGE_FLAGS_IOCPLB_ADDR          (0x02)
 647 #define IEEE_SGE_FLAGS_IOCPLBNTA_ADDR       (0x03)
 648 #define IEEE_SGE_FLAGS_CHAIN_ELEMENT        (0x80)
 649 #define IEEE_SGE_FLAGS_END_OF_LIST          (0x40)
 650
 651 struct megasas_register_set;
 652 struct megasas_instance;
 653
 654 union desc_word {
 655         u64 word;
 656         struct {
 657                 u32 low;
 658                 u32 high;
 659         } u;
 660 };
 661
 662 struct megasas_cmd_fusion {
 663         struct MPI2_RAID_SCSI_IO_REQUEST        *io_request;
 664         dma_addr_t                      io_request_phys_addr;
 665
 666         union MPI2_SGE_IO_UNION *sg_frame;
 667         dma_addr_t              sg_frame_phys_addr;
 668
 669         u8 *sense;
 670         dma_addr_t sense_phys_addr;
 671
 672         struct list_head list;
 673         struct scsi_cmnd *scmd;
 674         struct megasas_instance *instance;
 675
 676         u8 retry_for_fw_reset;
 677         union MEGASAS_REQUEST_DESCRIPTOR_UNION  *request_desc;
 678
 679         /*
 680          * Context for a MFI frame.
 681          * Used to get the mfi cmd from list when a MFI cmd is completed
 682          */
 683         u32 sync_cmd_idx;
 684         u32 index;
 685         u8 flags;
 686         u8 pd_r1_lb;
 687 };
 688
 689 struct LD_LOAD_BALANCE_INFO {
 690         u8      loadBalanceFlag;
 691         u8      reserved1;
 692         atomic_t     scsi_pending_cmds[MAX_PHYSICAL_DEVICES];
 693         u64     last_accessed_block[MAX_PHYSICAL_DEVICES];
 694 };
 695
 696 /* SPAN_SET is info caclulated from span info from Raid map per LD */
 697 typedef struct _LD_SPAN_SET {
 698         u64  log_start_lba;
 699         u64  log_end_lba;
 700         u64  span_row_start;
 701         u64  span_row_end;
 702         u64  data_strip_start;
 703         u64  data_strip_end;
 704         u64  data_row_start;
 705         u64  data_row_end;
 706         u8   strip_offset[MAX_SPAN_DEPTH];
 707         u32    span_row_data_width;
 708         u32    diff;
 709         u32    reserved[2];
 710 } LD_SPAN_SET, *PLD_SPAN_SET;
 711
 712 typedef struct LOG_BLOCK_SPAN_INFO {
 713         LD_SPAN_SET  span_set[MAX_SPAN_DEPTH];
 714 } LD_SPAN_INFO, *PLD_SPAN_INFO;
 715
 716 struct MR_FW_RAID_MAP_ALL {
 717         struct MR_FW_RAID_MAP raidMap;
 718         struct MR_LD_SPAN_MAP ldSpanMap[MAX_LOGICAL_DRIVES - 1];
 719 } __attribute__ ((packed));
 720
 721 struct MR_DRV_RAID_MAP {
 722         /* total size of this structure, including this field.
 723          * This feild will be manupulated by driver for ext raid map,
 724          * else pick the value from firmware raid map.
 725          */
 726         u32                 totalSize;
 727
 728         union {
 729         struct {
 730                 u32         maxLd;
 731                 u32         maxSpanDepth;
 732                 u32         maxRowSize;
 733                 u32         maxPdCount;
 734                 u32         maxArrays;
 735         } validationInfo;
 736         u32             version[5];
 737         };
 738
 739         /* timeout value used by driver in FP IOs*/
 740         u8                  fpPdIoTimeoutSec;
 741         u8                  reserved2[7];
 742
 743         u16                 ldCount;
 744         u16                 arCount;
 745         u16                 spanCount;
 746         u16                 reserve3;
 747
 748         struct MR_DEV_HANDLE_INFO  devHndlInfo[MAX_RAIDMAP_PHYSICAL_DEVICES];
 749         u8                  ldTgtIdToLd[MAX_LOGICAL_DRIVES_EXT];
 750         struct MR_ARRAY_INFO       arMapInfo[MAX_API_ARRAYS_EXT];
 751         struct MR_LD_SPAN_MAP      ldSpanMap[1];
 752
 753 };
 754
 755 /* Driver raid map size is same as raid map ext
 756  * MR_DRV_RAID_MAP_ALL is created to sync with old raid.
 757  * And it is mainly for code re-use purpose.
 758  */
 759 struct MR_DRV_RAID_MAP_ALL {
 760
 761         struct MR_DRV_RAID_MAP raidMap;
 762         struct MR_LD_SPAN_MAP      ldSpanMap[MAX_LOGICAL_DRIVES_EXT - 1];
 763 } __packed;
 764
 765
 766
 767 struct MR_FW_RAID_MAP_EXT {
 768         /* Not usred in new map */
 769         u32                 reserved;
 770
 771         union {
 772         struct {
 773                 u32         maxLd;
 774                 u32         maxSpanDepth;
 775                 u32         maxRowSize;
 776                 u32         maxPdCount;
 777                 u32         maxArrays;
 778         } validationInfo;
 779         u32             version[5];
 780         };
 781
 782         u8                  fpPdIoTimeoutSec;
 783         u8                  reserved2[7];
 784
 785         u16                 ldCount;
 786         u16                 arCount;
 787         u16                 spanCount;
 788         u16                 reserve3;
 789
 790         struct MR_DEV_HANDLE_INFO  devHndlInfo[MAX_RAIDMAP_PHYSICAL_DEVICES];
 791         u8                  ldTgtIdToLd[MAX_LOGICAL_DRIVES_EXT];
 792         struct MR_ARRAY_INFO       arMapInfo[MAX_API_ARRAYS_EXT];
 793         struct MR_LD_SPAN_MAP      ldSpanMap[MAX_LOGICAL_DRIVES_EXT];
 794 };
 795
 796 struct fusion_context {
 797         struct megasas_cmd_fusion **cmd_list;
 798         struct list_head cmd_pool;
 799
 800         spinlock_t mpt_pool_lock;
 801
 802         dma_addr_t req_frames_desc_phys;
 803         u8 *req_frames_desc;
 804
 805         struct dma_pool *io_request_frames_pool;
 806         dma_addr_t io_request_frames_phys;
 807         u8 *io_request_frames;
 808
 809         struct dma_pool *sg_dma_pool;
 810         struct dma_pool *sense_dma_pool;
 811
 812         dma_addr_t reply_frames_desc_phys;
 813         union MPI2_REPLY_DESCRIPTORS_UNION *reply_frames_desc;
 814         struct dma_pool *reply_frames_desc_pool;
 815
 816         u16 last_reply_idx[MAX_MSIX_QUEUES_FUSION];
 817
 818         u32 reply_q_depth;
 819         u32 request_alloc_sz;
 820         u32 reply_alloc_sz;
 821         u32 io_frames_alloc_sz;
 822
 823         u16     max_sge_in_main_msg;
 824         u16     max_sge_in_chain;
 825
 826         u8      chain_offset_io_request;
 827         u8      chain_offset_mfi_pthru;
 828
 829         struct MR_FW_RAID_MAP_ALL *ld_map[2];
 830         dma_addr_t ld_map_phys[2];
 831
 832         /*Non dma-able memory. Driver local copy.*/
 833         struct MR_DRV_RAID_MAP_ALL *ld_drv_map[2];
 834
 835         u32 max_map_sz;
 836         u32 current_map_sz;
 837         u32 old_map_sz;
 838         u32 new_map_sz;
 839         u32 drv_map_sz;
 840         u32 drv_map_pages;
 841         u8 fast_path_io;
 842         struct LD_LOAD_BALANCE_INFO load_balance_info[MAX_LOGICAL_DRIVES_EXT];
 843         LD_SPAN_INFO log_to_span[MAX_LOGICAL_DRIVES_EXT];
 844 };
 845
 846 union desc_value {
 847         u64 word;
 848         struct {
 849                 u32 low;
 850                 u32 high;
 851         } u;
 852 };
 853
 854
 855 #endif /* _MEGARAID_SAS_FUSION_H_ */