2 * QLogic iSCSI HBA Driver
3 * Copyright (c) 2003-2012 QLogic Corporation
5 * See LICENSE.qla4xxx for copyright and licensing details.
11 #include <linux/kernel.h>
12 #include <linux/init.h>
13 #include <linux/types.h>
14 #include <linux/module.h>
15 #include <linux/list.h>
16 #include <linux/pci.h>
17 #include <linux/dma-mapping.h>
18 #include <linux/sched.h>
19 #include <linux/slab.h>
20 #include <linux/dmapool.h>
21 #include <linux/mempool.h>
22 #include <linux/spinlock.h>
23 #include <linux/workqueue.h>
24 #include <linux/delay.h>
25 #include <linux/interrupt.h>
26 #include <linux/mutex.h>
27 #include <linux/aer.h>
28 #include <linux/bsg-lib.h>
31 #include <scsi/scsi.h>
32 #include <scsi/scsi_host.h>
33 #include <scsi/scsi_device.h>
34 #include <scsi/scsi_cmnd.h>
35 #include <scsi/scsi_transport.h>
36 #include <scsi/scsi_transport_iscsi.h>
37 #include <scsi/scsi_bsg_iscsi.h>
38 #include <scsi/scsi_netlink.h>
39 #include <scsi/libiscsi.h>
44 #include "ql4_nvram.h"
47 #ifndef PCI_DEVICE_ID_QLOGIC_ISP4010
48 #define PCI_DEVICE_ID_QLOGIC_ISP4010 0x4010
51 #ifndef PCI_DEVICE_ID_QLOGIC_ISP4022
52 #define PCI_DEVICE_ID_QLOGIC_ISP4022 0x4022
55 #ifndef PCI_DEVICE_ID_QLOGIC_ISP4032
56 #define PCI_DEVICE_ID_QLOGIC_ISP4032 0x4032
59 #ifndef PCI_DEVICE_ID_QLOGIC_ISP8022
60 #define PCI_DEVICE_ID_QLOGIC_ISP8022 0x8022
63 #ifndef PCI_DEVICE_ID_QLOGIC_ISP8324
64 #define PCI_DEVICE_ID_QLOGIC_ISP8324 0x8032
67 #define ISP4XXX_PCI_FN_1 0x1
68 #define ISP4XXX_PCI_FN_2 0x3
74 * Data bit definitions
92 #define BIT_16 0x10000
93 #define BIT_17 0x20000
94 #define BIT_18 0x40000
95 #define BIT_19 0x80000
96 #define BIT_20 0x100000
97 #define BIT_21 0x200000
98 #define BIT_22 0x400000
99 #define BIT_23 0x800000
100 #define BIT_24 0x1000000
101 #define BIT_25 0x2000000
102 #define BIT_26 0x4000000
103 #define BIT_27 0x8000000
104 #define BIT_28 0x10000000
105 #define BIT_29 0x20000000
106 #define BIT_30 0x40000000
107 #define BIT_31 0x80000000
110 * Macros to help code, maintain, etc.
112 #define ql4_printk(level, ha, format, arg...) \
113 dev_printk(level , &((ha)->pdev->dev) , format , ## arg)
117 * Host adapter default definitions
118 ***********************************/
121 #define MAX_TARGETS MAX_DEV_DB_ENTRIES
122 #define MAX_LUNS 0xffff
123 #define MAX_AEN_ENTRIES MAX_DEV_DB_ENTRIES
124 #define MAX_DDB_ENTRIES MAX_DEV_DB_ENTRIES
125 #define MAX_PDU_ENTRIES 32
126 #define INVALID_ENTRY 0xFFFF
127 #define MAX_CMDS_TO_RISC 1024
128 #define MAX_SRBS MAX_CMDS_TO_RISC
129 #define MBOX_AEN_REG_COUNT 8
130 #define MAX_INIT_RETRIES 5
135 #define REQUEST_QUEUE_DEPTH MAX_CMDS_TO_RISC
136 #define RESPONSE_QUEUE_DEPTH 64
137 #define QUEUE_SIZE 64
138 #define DMA_BUFFER_SIZE 512
139 #define IOCB_HIWAT_CUSHION 4
144 #define MAC_ADDR_LEN 6 /* in bytes */
145 #define IP_ADDR_LEN 4 /* in bytes */
146 #define IPv6_ADDR_LEN 16 /* IPv6 address size */
147 #define DRIVER_NAME "qla4xxx"
149 #define MAX_LINKED_CMDS_PER_LUN 3
150 #define MAX_REQS_SERVICED_PER_INTR 1
152 #define ISCSI_IPADDR_SIZE 4 /* IP address size */
153 #define ISCSI_ALIAS_SIZE 32 /* ISCSI Alias name size */
154 #define ISCSI_NAME_SIZE 0xE0 /* ISCSI Name size */
156 #define QL4_SESS_RECOVERY_TMO 120 /* iSCSI session */
157 /* recovery timeout */
159 #define LSDW(x) ((u32)((u64)(x)))
160 #define MSDW(x) ((u32)((((u64)(x)) >> 16) >> 16))
163 * Retry & Timeout Values
166 #define SOFT_RESET_TOV 30
167 #define RESET_INTR_TOV 3
168 #define SEMAPHORE_TOV 10
169 #define ADAPTER_INIT_TOV 30
170 #define ADAPTER_RESET_TOV 180
171 #define EXTEND_CMD_TOV 60
172 #define WAIT_CMD_TOV 30
173 #define EH_WAIT_CMD_TOV 120
174 #define FIRMWARE_UP_TOV 60
175 #define RESET_FIRMWARE_TOV 30
176 #define LOGOUT_TOV 10
177 #define IOCB_TOV_MARGIN 10
178 #define RELOGIN_TOV 18
179 #define ISNS_DEREG_TOV 5
180 #define HBA_ONLINE_TOV 30
181 #define DISABLE_ACB_TOV 30
182 #define IP_CONFIG_TOV 30
185 #define MAX_RESET_HA_RETRIES 2
186 #define FW_ALIVE_WAIT_TOV 3
188 #define CMD_SP(Cmnd) ((Cmnd)->SCp.ptr)
191 * SCSI Request Block structure (srb) that is placed
192 * on cmd->SCp location of every I/O [We have 22 bytes available]
195 struct list_head list; /* (8) */
196 struct scsi_qla_host *ha; /* HA the SP is queued on */
197 struct ddb_entry *ddb;
198 uint16_t flags; /* (1) Status flags. */
200 #define SRB_DMA_VALID BIT_3 /* DMA Buffer mapped. */
201 #define SRB_GOT_SENSE BIT_4 /* sense data received. */
202 uint8_t state; /* (1) Status flags. */
204 #define SRB_NO_QUEUE_STATE 0 /* Request is in between states */
205 #define SRB_FREE_STATE 1
206 #define SRB_ACTIVE_STATE 3
207 #define SRB_ACTIVE_TIMEOUT_STATE 4
208 #define SRB_SUSPENDED_STATE 7 /* Request in suspended state */
210 struct scsi_cmnd *cmd; /* (4) SCSI command block */
211 dma_addr_t dma_handle; /* (4) for unmap of single transfers */
212 struct kref srb_ref; /* reference count for this srb */
213 uint8_t err_id; /* error id */
214 #define SRB_ERR_PORT 1 /* Request failed because "port down" */
215 #define SRB_ERR_LOOP 2 /* Request failed because "loop down" */
216 #define SRB_ERR_DEVICE 3 /* Request failed because "device error" */
217 #define SRB_ERR_OTHER 4
221 uint16_t iocb_cnt; /* Number of used iocbs */
224 /* Used for extended sense / status continuation */
225 uint8_t *req_sense_ptr;
226 uint16_t req_sense_len;
230 /* Mailbox request block structure */
232 struct scsi_qla_host *ha;
233 struct mbox_cmd_iocb *mbox;
235 uint16_t iocb_cnt; /* Number of used iocbs */
240 * Asynchronous Event Queue structure
243 uint32_t mbox_sts[MBOX_AEN_REG_COUNT];
248 struct aen entry[MAX_AEN_ENTRIES];
252 * Device Database (DDB) structure
255 struct scsi_qla_host *ha;
256 struct iscsi_cls_session *sess;
257 struct iscsi_cls_conn *conn;
259 uint16_t fw_ddb_index; /* DDB firmware index */
260 uint32_t fw_ddb_device_state; /* F/W Device State -- see ql4_fw.h */
262 #define FLASH_DDB 0x01
264 struct dev_db_entry fw_ddb_entry;
265 int (*unblock_sess)(struct iscsi_cls_session *cls_session);
266 int (*ddb_change)(struct scsi_qla_host *ha, uint32_t fw_ddb_index,
267 struct ddb_entry *ddb_entry, uint32_t state);
269 /* Driver Re-login */
270 unsigned long flags; /* DDB Flags */
271 uint16_t default_relogin_timeout; /* Max time to wait for
272 * relogin to complete */
273 atomic_t retry_relogin_timer; /* Min Time between relogins
275 atomic_t relogin_timer; /* Max Time to wait for
276 * relogin to complete */
277 atomic_t relogin_retry_count; /* Num of times relogin has been
279 uint32_t default_time2wait; /* Default Min time between
280 * relogins (+aens) */
281 uint16_t chap_tbl_idx;
284 struct qla_ddb_index {
285 struct list_head list;
287 struct dev_db_entry fw_ddb;
288 uint8_t flash_isid[6];
291 #define DDB_IPADDR_LEN 64
293 struct ql4_tuple_ddb {
296 char ip_addr[DDB_IPADDR_LEN];
297 char iscsi_name[ISCSI_NAME_SIZE];
299 #define DDB_OPT_IPV6 0x0e0e
300 #define DDB_OPT_IPV4 0x0f0f
307 #define DDB_STATE_DEAD 0 /* We can no longer talk to
309 #define DDB_STATE_ONLINE 1 /* Device ready to accept
311 #define DDB_STATE_MISSING 2 /* Device logged off, trying
317 #define DF_RELOGIN 0 /* Relogin to device */
318 #define DF_ISNS_DISCOVERED 2 /* Device was discovered via iSNS */
319 #define DF_FO_MASKED 3
321 enum qla4_work_type {
323 QLA4_EVENT_PING_STATUS,
326 struct qla4_work_evt {
327 struct list_head list;
328 enum qla4_work_type type;
331 enum iscsi_host_event_code code;
344 struct ql82xx_hw_data {
345 /* Offsets for flash/nvram access (set to ~0 if not used). */
346 uint32_t flash_conf_off;
347 uint32_t flash_data_off;
349 uint32_t fdt_wrt_disable;
350 uint32_t fdt_erase_cmd;
351 uint32_t fdt_block_size;
352 uint32_t fdt_unprotect_sec_cmd;
353 uint32_t fdt_protect_sec_cmd;
355 uint32_t flt_region_flt;
356 uint32_t flt_region_fdt;
357 uint32_t flt_region_boot;
358 uint32_t flt_region_bootload;
359 uint32_t flt_region_fw;
361 uint32_t flt_iscsi_param;
362 uint32_t flt_region_chap;
363 uint32_t flt_chap_size;
366 struct qla4_8xxx_legacy_intr_set {
367 uint32_t int_vec_bit;
368 uint32_t tgt_status_reg;
369 uint32_t tgt_mask_reg;
370 uint32_t pci_int_reg;
375 #define QLA_MSIX_DEFAULT 0x00
376 #define QLA_MSIX_RSP_Q 0x01
378 #define QLA_MSIX_ENTRIES 2
379 #define QLA_MIDX_DEFAULT 0
380 #define QLA_MIDX_RSP_Q 1
382 struct ql4_msix_entry {
384 uint16_t msix_vector;
391 struct isp_operations {
392 int (*iospace_config) (struct scsi_qla_host *ha);
393 void (*pci_config) (struct scsi_qla_host *);
394 void (*disable_intrs) (struct scsi_qla_host *);
395 void (*enable_intrs) (struct scsi_qla_host *);
396 int (*start_firmware) (struct scsi_qla_host *);
397 int (*restart_firmware) (struct scsi_qla_host *);
398 irqreturn_t (*intr_handler) (int , void *);
399 void (*interrupt_service_routine) (struct scsi_qla_host *, uint32_t);
400 int (*need_reset) (struct scsi_qla_host *);
401 int (*reset_chip) (struct scsi_qla_host *);
402 int (*reset_firmware) (struct scsi_qla_host *);
403 void (*queue_iocb) (struct scsi_qla_host *);
404 void (*complete_iocb) (struct scsi_qla_host *);
405 uint16_t (*rd_shdw_req_q_out) (struct scsi_qla_host *);
406 uint16_t (*rd_shdw_rsp_q_in) (struct scsi_qla_host *);
407 int (*get_sys_info) (struct scsi_qla_host *);
408 uint32_t (*rd_reg_direct) (struct scsi_qla_host *, ulong);
409 void (*wr_reg_direct) (struct scsi_qla_host *, ulong, uint32_t);
410 int (*rd_reg_indirect) (struct scsi_qla_host *, uint32_t, uint32_t *);
411 int (*wr_reg_indirect) (struct scsi_qla_host *, uint32_t, uint32_t);
412 int (*idc_lock) (struct scsi_qla_host *);
413 void (*idc_unlock) (struct scsi_qla_host *);
414 void (*rom_lock_recovery) (struct scsi_qla_host *);
415 void (*queue_mailbox_command) (struct scsi_qla_host *, uint32_t *, int);
416 void (*process_mailbox_interrupt) (struct scsi_qla_host *, int);
419 struct ql4_mdump_size_table {
421 uint32_t size_cmask_02;
422 uint32_t size_cmask_04;
423 uint32_t size_cmask_08;
424 uint32_t size_cmask_10;
425 uint32_t size_cmask_FF;
429 /*qla4xxx ipaddress configuration details */
430 struct ipaddress_config {
431 uint16_t ipv4_options;
432 uint16_t tcp_options;
433 uint16_t ipv4_vlan_tag;
434 uint8_t ipv4_addr_state;
435 uint8_t ip_address[IP_ADDR_LEN];
436 uint8_t subnet_mask[IP_ADDR_LEN];
437 uint8_t gateway[IP_ADDR_LEN];
438 uint32_t ipv6_options;
439 uint32_t ipv6_addl_options;
440 uint8_t ipv6_link_local_state;
441 uint8_t ipv6_addr0_state;
442 uint8_t ipv6_addr1_state;
443 uint8_t ipv6_default_router_state;
444 uint16_t ipv6_vlan_tag;
445 struct in6_addr ipv6_link_local_addr;
446 struct in6_addr ipv6_addr0;
447 struct in6_addr ipv6_addr1;
448 struct in6_addr ipv6_default_router_addr;
449 uint16_t eth_mtu_size;
454 #define QL4_CHAP_MAX_NAME_LEN 256
455 #define QL4_CHAP_MAX_SECRET_LEN 100
459 struct ql4_chap_format {
460 u8 intr_chap_name[QL4_CHAP_MAX_NAME_LEN];
461 u8 intr_secret[QL4_CHAP_MAX_SECRET_LEN];
462 u8 target_chap_name[QL4_CHAP_MAX_NAME_LEN];
463 u8 target_secret[QL4_CHAP_MAX_SECRET_LEN];
464 u16 intr_chap_name_length;
465 u16 intr_secret_length;
466 u16 target_chap_name_length;
467 u16 target_secret_length;
470 struct ip_address_format {
475 struct ql4_conn_info {
477 struct ip_address_format dest_ipaddr;
478 struct ql4_chap_format chap;
481 struct ql4_boot_session_info {
483 struct ql4_conn_info conn_list[1];
486 struct ql4_boot_tgt_info {
487 struct ql4_boot_session_info boot_pri_sess;
488 struct ql4_boot_session_info boot_sec_sess;
492 * Linux Host Adapter structure
494 struct scsi_qla_host {
495 /* Linux adapter configuration data */
498 #define AF_ONLINE 0 /* 0x00000001 */
499 #define AF_INIT_DONE 1 /* 0x00000002 */
500 #define AF_MBOX_COMMAND 2 /* 0x00000004 */
501 #define AF_MBOX_COMMAND_DONE 3 /* 0x00000008 */
502 #define AF_INTERRUPTS_ON 6 /* 0x00000040 */
503 #define AF_GET_CRASH_RECORD 7 /* 0x00000080 */
504 #define AF_LINK_UP 8 /* 0x00000100 */
505 #define AF_LOOPBACK 9 /* 0x00000200 */
506 #define AF_IRQ_ATTACHED 10 /* 0x00000400 */
507 #define AF_DISABLE_ACB_COMPLETE 11 /* 0x00000800 */
508 #define AF_HA_REMOVAL 12 /* 0x00001000 */
509 #define AF_INTx_ENABLED 15 /* 0x00008000 */
510 #define AF_MSI_ENABLED 16 /* 0x00010000 */
511 #define AF_MSIX_ENABLED 17 /* 0x00020000 */
512 #define AF_MBOX_COMMAND_NOPOLL 18 /* 0x00040000 */
513 #define AF_FW_RECOVERY 19 /* 0x00080000 */
514 #define AF_EEH_BUSY 20 /* 0x00100000 */
515 #define AF_PCI_CHANNEL_IO_PERM_FAILURE 21 /* 0x00200000 */
516 #define AF_BUILD_DDB_LIST 22 /* 0x00400000 */
517 #define AF_82XX_FW_DUMPED 24 /* 0x01000000 */
518 #define AF_8XXX_RST_OWNER 25 /* 0x02000000 */
519 #define AF_82XX_DUMP_READING 26 /* 0x04000000 */
520 #define AF_83XX_NO_FW_DUMP 27 /* 0x08000000 */
521 #define AF_83XX_IOCB_INTR_ON 28 /* 0x10000000 */
522 #define AF_83XX_MBOX_INTR_ON 29 /* 0x20000000 */
524 unsigned long dpc_flags;
526 #define DPC_RESET_HA 1 /* 0x00000002 */
527 #define DPC_RETRY_RESET_HA 2 /* 0x00000004 */
528 #define DPC_RELOGIN_DEVICE 3 /* 0x00000008 */
529 #define DPC_RESET_HA_FW_CONTEXT 4 /* 0x00000010 */
530 #define DPC_RESET_HA_INTR 5 /* 0x00000020 */
531 #define DPC_ISNS_RESTART 7 /* 0x00000080 */
532 #define DPC_AEN 9 /* 0x00000200 */
533 #define DPC_GET_DHCP_IP_ADDR 15 /* 0x00008000 */
534 #define DPC_LINK_CHANGED 18 /* 0x00040000 */
535 #define DPC_RESET_ACTIVE 20 /* 0x00040000 */
536 #define DPC_HA_UNRECOVERABLE 21 /* 0x00080000 ISP-82xx only*/
537 #define DPC_HA_NEED_QUIESCENT 22 /* 0x00100000 ISP-82xx only*/
538 #define DPC_POST_IDC_ACK 23 /* 0x00200000 */
540 struct Scsi_Host *host; /* pointer to host data */
547 #define SRB_MIN_REQ 128
548 mempool_t *srb_mempool;
550 /* pci information */
551 struct pci_dev *pdev;
553 struct isp_reg __iomem *reg; /* Base I/O address */
554 unsigned long pio_address;
555 unsigned long pio_length;
556 #define MIN_IOBASE_LEN 0x100
558 uint16_t req_q_count;
560 unsigned long host_no;
562 /* NVRAM registers */
563 struct eeprom_data *nvram;
564 spinlock_t hardware_lock ____cacheline_aligned;
565 uint32_t eeprom_cmd_data;
567 /* Counters for general statistics */
569 uint64_t adapter_error_count;
570 uint64_t device_error_count;
571 uint64_t total_io_count;
572 uint64_t total_mbytes_xferred;
573 uint64_t link_failure_count;
574 uint64_t invalid_crc_count;
575 uint32_t bytes_xfered;
576 uint32_t spurious_int_count;
577 uint32_t aborted_io_count;
578 uint32_t io_timeout_count;
579 uint32_t mailbox_timeout_count;
580 uint32_t seconds_since_last_intr;
581 uint32_t seconds_since_last_heartbeat;
584 /* Info Needed for Management App */
585 /* --- From GetFwVersion --- */
586 uint32_t firmware_version[2];
587 uint32_t patch_number;
588 uint32_t build_number;
591 /* --- From Init_FW --- */
592 /* init_cb_t *init_cb; */
593 uint16_t firmware_options;
595 uint8_t name_string[256];
596 uint8_t heartbeat_interval;
598 /* --- From FlashSysInfo --- */
599 uint8_t my_mac[MAC_ADDR_LEN];
600 uint8_t serial_number[16];
602 /* --- From GetFwState --- */
603 uint32_t firmware_state;
604 uint32_t addl_fw_state;
606 /* Linux kernel thread */
607 struct workqueue_struct *dpc_thread;
608 struct work_struct dpc_work;
610 /* Linux timer thread */
611 struct timer_list timer;
612 uint32_t timer_active;
614 /* Recovery Timers */
615 atomic_t check_relogin_timeouts;
616 uint32_t retry_reset_ha_cnt;
617 uint32_t isp_reset_timer; /* reset test timer */
618 uint32_t nic_reset_timer; /* simulated nic reset test timer */
620 struct list_head free_srb_q;
621 uint16_t free_srb_q_count;
622 uint16_t num_srbs_allocated;
624 /* DMA Memory Block */
626 dma_addr_t queues_dma;
627 unsigned long queues_len;
629 #define MEM_ALIGN_VALUE \
630 ((max(REQUEST_QUEUE_DEPTH, RESPONSE_QUEUE_DEPTH)) * \
631 sizeof(struct queue_entry))
632 /* request and response queue variables */
633 dma_addr_t request_dma;
634 struct queue_entry *request_ring;
635 struct queue_entry *request_ptr;
636 dma_addr_t response_dma;
637 struct queue_entry *response_ring;
638 struct queue_entry *response_ptr;
639 dma_addr_t shadow_regs_dma;
640 struct shadow_regs *shadow_regs;
641 uint16_t request_in; /* Current indexes. */
642 uint16_t request_out;
643 uint16_t response_in;
644 uint16_t response_out;
646 /* aen queue variables */
647 uint16_t aen_q_count; /* Number of available aen_q entries */
648 uint16_t aen_in; /* Current indexes */
650 struct aen aen_q[MAX_AEN_ENTRIES];
652 struct ql4_aen_log aen_log;/* tracks all aens */
654 /* This mutex protects several threads to do mailbox commands
657 struct mutex mbox_sem;
659 /* temporary mailbox status registers */
660 volatile uint8_t mbox_status_count;
661 volatile uint32_t mbox_status[MBOX_REG_COUNT];
663 /* FW ddb index map */
664 struct ddb_entry *fw_ddb_index_map[MAX_DDB_ENTRIES];
666 /* Saved srb for status continuation entry processing */
667 struct srb *status_srb;
671 /* qla82xx specific fields */
672 struct device_reg_82xx __iomem *qla4_82xx_reg; /* Base I/O address */
673 unsigned long nx_pcibase; /* Base I/O address */
674 uint8_t *nx_db_rd_ptr; /* Doorbell read pointer */
675 unsigned long nx_db_wr_ptr; /* Door bell write pointer */
676 unsigned long first_page_group_start;
677 unsigned long first_page_group_end;
680 uint32_t curr_window;
681 uint32_t ddr_mn_window;
682 unsigned long mn_win_crb;
683 unsigned long ms_win_crb;
689 struct qla4_8xxx_legacy_intr_set nx_legacy_intr;
693 uint32_t fw_heartbeat_counter;
695 struct isp_operations *isp_ops;
696 struct ql82xx_hw_data hw;
698 struct ql4_msix_entry msix_entries[QLA_MSIX_ENTRIES];
700 uint32_t nx_dev_init_timeout;
701 uint32_t nx_reset_timeout;
703 uint32_t fw_dump_size;
704 uint32_t fw_dump_capture_mask;
705 void *fw_dump_tmplt_hdr;
706 uint32_t fw_dump_tmplt_size;
708 struct completion mbx_intr_comp;
710 struct ipaddress_config ip_config;
711 struct iscsi_iface *iface_ipv4;
712 struct iscsi_iface *iface_ipv6_0;
713 struct iscsi_iface *iface_ipv6_1;
715 /* --- From About Firmware --- */
716 uint16_t iscsi_major;
717 uint16_t iscsi_minor;
718 uint16_t bootload_major;
719 uint16_t bootload_minor;
720 uint16_t bootload_patch;
721 uint16_t bootload_build;
722 uint16_t def_timeout; /* Default login timeout */
724 uint32_t flash_state;
725 #define QLFLASH_WAITING 0
726 #define QLFLASH_READING 1
727 #define QLFLASH_WRITING 2
728 struct dma_pool *chap_dma_pool;
729 uint8_t *chap_list; /* CHAP table cache */
730 struct mutex chap_sem;
732 #define CHAP_DMA_BLOCK_SIZE 512
733 struct workqueue_struct *task_wq;
734 unsigned long ddb_idx_map[MAX_DDB_ENTRIES / BITS_PER_LONG];
735 #define SYSFS_FLAG_FW_SEL_BOOT 2
736 struct iscsi_boot_kset *boot_kset;
737 struct ql4_boot_tgt_info boot_tgt;
738 uint16_t phy_port_num;
739 uint16_t phy_port_cnt;
740 uint16_t iscsi_pci_func_cnt;
741 uint8_t model_name[16];
742 struct completion disable_acb_comp;
743 struct dma_pool *fw_ddb_dma_pool;
744 #define DDB_DMA_BLOCK_SIZE 512
745 uint16_t pri_ddb_idx;
746 uint16_t sec_ddb_idx;
748 uint16_t temperature;
750 /* event work list */
751 struct list_head work_list;
752 spinlock_t work_lock;
756 struct mrb *active_mrb_array[MAX_MRB];
760 struct qla4_83xx_reset_template reset_tmplt;
761 struct device_reg_83xx __iomem *qla4_83xx_reg; /* Base I/O address
764 struct qla4_83xx_idc_information idc_info;
767 struct ql4_task_data {
768 struct scsi_qla_host *ha;
769 uint8_t iocb_req_cnt;
777 struct iscsi_task *task;
778 struct passthru_status sts;
779 struct work_struct task_work;
782 struct qla_endpoint {
783 struct Scsi_Host *host;
784 struct sockaddr_storage dst_addr;
788 struct qla_endpoint *qla_ep;
791 static inline int is_ipv4_enabled(struct scsi_qla_host *ha)
793 return ((ha->ip_config.ipv4_options & IPOPT_IPV4_PROTOCOL_ENABLE) != 0);
796 static inline int is_ipv6_enabled(struct scsi_qla_host *ha)
798 return ((ha->ip_config.ipv6_options &
799 IPV6_OPT_IPV6_PROTOCOL_ENABLE) != 0);
802 static inline int is_qla4010(struct scsi_qla_host *ha)
804 return ha->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP4010;
807 static inline int is_qla4022(struct scsi_qla_host *ha)
809 return ha->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP4022;
812 static inline int is_qla4032(struct scsi_qla_host *ha)
814 return ha->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP4032;
817 static inline int is_qla40XX(struct scsi_qla_host *ha)
819 return is_qla4032(ha) || is_qla4022(ha) || is_qla4010(ha);
822 static inline int is_qla8022(struct scsi_qla_host *ha)
824 return ha->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8022;
827 static inline int is_qla8032(struct scsi_qla_host *ha)
829 return ha->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8324;
832 static inline int is_qla80XX(struct scsi_qla_host *ha)
834 return is_qla8022(ha) || is_qla8032(ha);
837 static inline int is_aer_supported(struct scsi_qla_host *ha)
839 return ((ha->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8022) ||
840 (ha->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8324));
843 static inline int adapter_up(struct scsi_qla_host *ha)
845 return (test_bit(AF_ONLINE, &ha->flags) != 0) &&
846 (test_bit(AF_LINK_UP, &ha->flags) != 0) &&
847 (!test_bit(AF_LOOPBACK, &ha->flags));
850 static inline struct scsi_qla_host* to_qla_host(struct Scsi_Host *shost)
852 return (struct scsi_qla_host *)iscsi_host_priv(shost);
855 static inline void __iomem* isp_semaphore(struct scsi_qla_host *ha)
857 return (is_qla4010(ha) ?
858 &ha->reg->u1.isp4010.nvram :
859 &ha->reg->u1.isp4022.semaphore);
862 static inline void __iomem* isp_nvram(struct scsi_qla_host *ha)
864 return (is_qla4010(ha) ?
865 &ha->reg->u1.isp4010.nvram :
866 &ha->reg->u1.isp4022.nvram);
869 static inline void __iomem* isp_ext_hw_conf(struct scsi_qla_host *ha)
871 return (is_qla4010(ha) ?
872 &ha->reg->u2.isp4010.ext_hw_conf :
873 &ha->reg->u2.isp4022.p0.ext_hw_conf);
876 static inline void __iomem* isp_port_status(struct scsi_qla_host *ha)
878 return (is_qla4010(ha) ?
879 &ha->reg->u2.isp4010.port_status :
880 &ha->reg->u2.isp4022.p0.port_status);
883 static inline void __iomem* isp_port_ctrl(struct scsi_qla_host *ha)
885 return (is_qla4010(ha) ?
886 &ha->reg->u2.isp4010.port_ctrl :
887 &ha->reg->u2.isp4022.p0.port_ctrl);
890 static inline void __iomem* isp_port_error_status(struct scsi_qla_host *ha)
892 return (is_qla4010(ha) ?
893 &ha->reg->u2.isp4010.port_err_status :
894 &ha->reg->u2.isp4022.p0.port_err_status);
897 static inline void __iomem * isp_gp_out(struct scsi_qla_host *ha)
899 return (is_qla4010(ha) ?
900 &ha->reg->u2.isp4010.gp_out :
901 &ha->reg->u2.isp4022.p0.gp_out);
904 static inline int eeprom_ext_hw_conf_offset(struct scsi_qla_host *ha)
906 return (is_qla4010(ha) ?
907 offsetof(struct eeprom_data, isp4010.ext_hw_conf) / 2 :
908 offsetof(struct eeprom_data, isp4022.ext_hw_conf) / 2);
911 int ql4xxx_sem_spinlock(struct scsi_qla_host * ha, u32 sem_mask, u32 sem_bits);
912 void ql4xxx_sem_unlock(struct scsi_qla_host * ha, u32 sem_mask);
913 int ql4xxx_sem_lock(struct scsi_qla_host * ha, u32 sem_mask, u32 sem_bits);
915 static inline int ql4xxx_lock_flash(struct scsi_qla_host *a)
918 return ql4xxx_sem_spinlock(a, QL4010_FLASH_SEM_MASK,
919 QL4010_FLASH_SEM_BITS);
921 return ql4xxx_sem_spinlock(a, QL4022_FLASH_SEM_MASK,
922 (QL4022_RESOURCE_BITS_BASE_CODE |
923 (a->mac_index)) << 13);
926 static inline void ql4xxx_unlock_flash(struct scsi_qla_host *a)
929 ql4xxx_sem_unlock(a, QL4010_FLASH_SEM_MASK);
931 ql4xxx_sem_unlock(a, QL4022_FLASH_SEM_MASK);
934 static inline int ql4xxx_lock_nvram(struct scsi_qla_host *a)
937 return ql4xxx_sem_spinlock(a, QL4010_NVRAM_SEM_MASK,
938 QL4010_NVRAM_SEM_BITS);
940 return ql4xxx_sem_spinlock(a, QL4022_NVRAM_SEM_MASK,
941 (QL4022_RESOURCE_BITS_BASE_CODE |
942 (a->mac_index)) << 10);
945 static inline void ql4xxx_unlock_nvram(struct scsi_qla_host *a)
948 ql4xxx_sem_unlock(a, QL4010_NVRAM_SEM_MASK);
950 ql4xxx_sem_unlock(a, QL4022_NVRAM_SEM_MASK);
953 static inline int ql4xxx_lock_drvr(struct scsi_qla_host *a)
956 return ql4xxx_sem_lock(a, QL4010_DRVR_SEM_MASK,
957 QL4010_DRVR_SEM_BITS);
959 return ql4xxx_sem_lock(a, QL4022_DRVR_SEM_MASK,
960 (QL4022_RESOURCE_BITS_BASE_CODE |
961 (a->mac_index)) << 1);
964 static inline void ql4xxx_unlock_drvr(struct scsi_qla_host *a)
967 ql4xxx_sem_unlock(a, QL4010_DRVR_SEM_MASK);
969 ql4xxx_sem_unlock(a, QL4022_DRVR_SEM_MASK);
972 static inline int ql4xxx_reset_active(struct scsi_qla_host *ha)
974 return test_bit(DPC_RESET_ACTIVE, &ha->dpc_flags) ||
975 test_bit(DPC_RESET_HA, &ha->dpc_flags) ||
976 test_bit(DPC_RETRY_RESET_HA, &ha->dpc_flags) ||
977 test_bit(DPC_RESET_HA_INTR, &ha->dpc_flags) ||
978 test_bit(DPC_RESET_HA_FW_CONTEXT, &ha->dpc_flags) ||
979 test_bit(DPC_HA_UNRECOVERABLE, &ha->dpc_flags);
983 static inline int qla4_8xxx_rd_direct(struct scsi_qla_host *ha,
984 const uint32_t crb_reg)
986 return ha->isp_ops->rd_reg_direct(ha, ha->reg_tbl[crb_reg]);
989 static inline void qla4_8xxx_wr_direct(struct scsi_qla_host *ha,
990 const uint32_t crb_reg,
991 const uint32_t value)
993 ha->isp_ops->wr_reg_direct(ha, ha->reg_tbl[crb_reg], value);
996 /*---------------------------------------------------------------------------*/
998 /* Defines for qla4xxx_initialize_adapter() and qla4xxx_recover_adapter() */
1000 #define INIT_ADAPTER 0
1001 #define RESET_ADAPTER 1
1003 #define PRESERVE_DDB_LIST 0
1004 #define REBUILD_DDB_LIST 1
1006 /* Defines for process_aen() */
1007 #define PROCESS_ALL_AENS 0
1008 #define FLUSH_DDB_CHANGED_AENS 1
1010 /* Defines for udev events */
1011 #define QL4_UEVENT_CODE_FW_DUMP 0
1013 #endif /*_QLA4XXX_H */