drivers/scsi/stex.c

   1 /*
   2  * SuperTrak EX Series Storage Controller driver for Linux
   3  *
   4  *      Copyright (C) 2005-2015 Promise Technology Inc.
   5  *
   6  *      This program is free software; you can redistribute it and/or
   7  *      modify it under the terms of the GNU General Public License
   8  *      as published by the Free Software Foundation; either version
   9  *      2 of the License, or (at your option) any later version.
  10  *
  11  *      Written By:
  12  *              Ed Lin <promise_linux@promise.com>
  13  *
  14  */
  15
  16 #include <linux/init.h>
  17 #include <linux/errno.h>
  18 #include <linux/kernel.h>
  19 #include <linux/delay.h>
  20 #include <linux/slab.h>
  21 #include <linux/time.h>
  22 #include <linux/pci.h>
  23 #include <linux/blkdev.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/types.h>
  26 #include <linux/module.h>
  27 #include <linux/spinlock.h>
  28 #include <linux/ktime.h>
  29 #include <asm/io.h>
  30 #include <asm/irq.h>
  31 #include <asm/byteorder.h>
  32 #include <scsi/scsi.h>
  33 #include <scsi/scsi_device.h>
  34 #include <scsi/scsi_cmnd.h>
  35 #include <scsi/scsi_host.h>
  36 #include <scsi/scsi_tcq.h>
  37 #include <scsi/scsi_dbg.h>
  38 #include <scsi/scsi_eh.h>
  39
  40 #define DRV_NAME "stex"
  41 #define ST_DRIVER_VERSION       "5.00.0000.01"
  42 #define ST_VER_MAJOR            5
  43 #define ST_VER_MINOR            00
  44 #define ST_OEM                          0000
  45 #define ST_BUILD_VER            01
  46
  47 enum {
  48         /* MU register offset */
  49         IMR0    = 0x10, /* MU_INBOUND_MESSAGE_REG0 */
  50         IMR1    = 0x14, /* MU_INBOUND_MESSAGE_REG1 */
  51         OMR0    = 0x18, /* MU_OUTBOUND_MESSAGE_REG0 */
  52         OMR1    = 0x1c, /* MU_OUTBOUND_MESSAGE_REG1 */
  53         IDBL    = 0x20, /* MU_INBOUND_DOORBELL */
  54         IIS     = 0x24, /* MU_INBOUND_INTERRUPT_STATUS */
  55         IIM     = 0x28, /* MU_INBOUND_INTERRUPT_MASK */
  56         ODBL    = 0x2c, /* MU_OUTBOUND_DOORBELL */
  57         OIS     = 0x30, /* MU_OUTBOUND_INTERRUPT_STATUS */
  58         OIM     = 0x3c, /* MU_OUTBOUND_INTERRUPT_MASK */
  59
  60         YIOA_STATUS                             = 0x00,
  61         YH2I_INT                                = 0x20,
  62         YINT_EN                                 = 0x34,
  63         YI2H_INT                                = 0x9c,
  64         YI2H_INT_C                              = 0xa0,
  65         YH2I_REQ                                = 0xc0,
  66         YH2I_REQ_HI                             = 0xc4,
  67
  68         /* MU register value */
  69         MU_INBOUND_DOORBELL_HANDSHAKE           = (1 << 0),
  70         MU_INBOUND_DOORBELL_REQHEADCHANGED      = (1 << 1),
  71         MU_INBOUND_DOORBELL_STATUSTAILCHANGED   = (1 << 2),
  72         MU_INBOUND_DOORBELL_HMUSTOPPED          = (1 << 3),
  73         MU_INBOUND_DOORBELL_RESET               = (1 << 4),
  74
  75         MU_OUTBOUND_DOORBELL_HANDSHAKE          = (1 << 0),
  76         MU_OUTBOUND_DOORBELL_REQUESTTAILCHANGED = (1 << 1),
  77         MU_OUTBOUND_DOORBELL_STATUSHEADCHANGED  = (1 << 2),
  78         MU_OUTBOUND_DOORBELL_BUSCHANGE          = (1 << 3),
  79         MU_OUTBOUND_DOORBELL_HASEVENT           = (1 << 4),
  80         MU_OUTBOUND_DOORBELL_REQUEST_RESET      = (1 << 27),
  81
  82         /* MU status code */
  83         MU_STATE_STARTING                       = 1,
  84         MU_STATE_STARTED                        = 2,
  85         MU_STATE_RESETTING                      = 3,
  86         MU_STATE_FAILED                         = 4,
  87         MU_STATE_STOP                           = 5,
  88         MU_STATE_NOCONNECT                      = 6,
  89
  90         MU_MAX_DELAY                            = 120,
  91         MU_HANDSHAKE_SIGNATURE                  = 0x55aaaa55,
  92         MU_HANDSHAKE_SIGNATURE_HALF             = 0x5a5a0000,
  93         MU_HARD_RESET_WAIT                      = 30000,
  94         HMU_PARTNER_TYPE                        = 2,
  95
  96         /* firmware returned values */
  97         SRB_STATUS_SUCCESS                      = 0x01,
  98         SRB_STATUS_ERROR                        = 0x04,
  99         SRB_STATUS_BUSY                         = 0x05,
 100         SRB_STATUS_INVALID_REQUEST              = 0x06,
 101         SRB_STATUS_SELECTION_TIMEOUT            = 0x0A,
 102         SRB_SEE_SENSE                           = 0x80,
 103
 104         /* task attribute */
 105         TASK_ATTRIBUTE_SIMPLE                   = 0x0,
 106         TASK_ATTRIBUTE_HEADOFQUEUE              = 0x1,
 107         TASK_ATTRIBUTE_ORDERED                  = 0x2,
 108         TASK_ATTRIBUTE_ACA                      = 0x4,
 109
 110         SS_STS_NORMAL                           = 0x80000000,
 111         SS_STS_DONE                             = 0x40000000,
 112         SS_STS_HANDSHAKE                        = 0x20000000,
 113
 114         SS_HEAD_HANDSHAKE                       = 0x80,
 115
 116         SS_H2I_INT_RESET                        = 0x100,
 117
 118         SS_I2H_REQUEST_RESET                    = 0x2000,
 119
 120         SS_MU_OPERATIONAL                       = 0x80000000,
 121
 122         STEX_CDB_LENGTH                         = 16,
 123         STATUS_VAR_LEN                          = 128,
 124
 125         /* sg flags */
 126         SG_CF_EOT                               = 0x80, /* end of table */
 127         SG_CF_64B                               = 0x40, /* 64 bit item */
 128         SG_CF_HOST                              = 0x20, /* sg in host memory */
 129         MSG_DATA_DIR_ND                         = 0,
 130         MSG_DATA_DIR_IN                         = 1,
 131         MSG_DATA_DIR_OUT                        = 2,
 132
 133         st_shasta                               = 0,
 134         st_vsc                                  = 1,
 135         st_yosemite                             = 2,
 136         st_seq                                  = 3,
 137         st_yel                                  = 4,
 138
 139         PASSTHRU_REQ_TYPE                       = 0x00000001,
 140         PASSTHRU_REQ_NO_WAKEUP                  = 0x00000100,
 141         ST_INTERNAL_TIMEOUT                     = 180,
 142
 143         ST_TO_CMD                               = 0,
 144         ST_FROM_CMD                             = 1,
 145
 146         /* vendor specific commands of Promise */
 147         MGT_CMD                                 = 0xd8,
 148         SINBAND_MGT_CMD                         = 0xd9,
 149         ARRAY_CMD                               = 0xe0,
 150         CONTROLLER_CMD                          = 0xe1,
 151         DEBUGGING_CMD                           = 0xe2,
 152         PASSTHRU_CMD                            = 0xe3,
 153
 154         PASSTHRU_GET_ADAPTER                    = 0x05,
 155         PASSTHRU_GET_DRVVER                     = 0x10,
 156
 157         CTLR_CONFIG_CMD                         = 0x03,
 158         CTLR_SHUTDOWN                           = 0x0d,
 159
 160         CTLR_POWER_STATE_CHANGE                 = 0x0e,
 161         CTLR_POWER_SAVING                       = 0x01,
 162
 163         PASSTHRU_SIGNATURE                      = 0x4e415041,
 164         MGT_CMD_SIGNATURE                       = 0xba,
 165
 166         INQUIRY_EVPD                            = 0x01,
 167
 168         ST_ADDITIONAL_MEM                       = 0x200000,
 169         ST_ADDITIONAL_MEM_MIN                   = 0x80000,
 170 };
 171
 172 struct st_sgitem {
 173         u8 ctrl;        /* SG_CF_xxx */
 174         u8 reserved[3];
 175         __le32 count;
 176         __le64 addr;
 177 };
 178
 179 struct st_ss_sgitem {
 180         __le32 addr;
 181         __le32 addr_hi;
 182         __le32 count;
 183 };
 184
 185 struct st_sgtable {
 186         __le16 sg_count;
 187         __le16 max_sg_count;
 188         __le32 sz_in_byte;
 189 };
 190
 191 struct st_msg_header {
 192         __le64 handle;
 193         u8 flag;
 194         u8 channel;
 195         __le16 timeout;
 196         u32 reserved;
 197 };
 198
 199 struct handshake_frame {
 200         __le64 rb_phy;          /* request payload queue physical address */
 201         __le16 req_sz;          /* size of each request payload */
 202         __le16 req_cnt;         /* count of reqs the buffer can hold */
 203         __le16 status_sz;       /* size of each status payload */
 204         __le16 status_cnt;      /* count of status the buffer can hold */
 205         __le64 hosttime;        /* seconds from Jan 1, 1970 (GMT) */
 206         u8 partner_type;        /* who sends this frame */
 207         u8 reserved0[7];
 208         __le32 partner_ver_major;
 209         __le32 partner_ver_minor;
 210         __le32 partner_ver_oem;
 211         __le32 partner_ver_build;
 212         __le32 extra_offset;    /* NEW */
 213         __le32 extra_size;      /* NEW */
 214         __le32 scratch_size;
 215         u32 reserved1;
 216 };
 217
 218 struct req_msg {
 219         __le16 tag;
 220         u8 lun;
 221         u8 target;
 222         u8 task_attr;
 223         u8 task_manage;
 224         u8 data_dir;
 225         u8 payload_sz;          /* payload size in 4-byte, not used */
 226         u8 cdb[STEX_CDB_LENGTH];
 227         u32 variable[0];
 228 };
 229
 230 struct status_msg {
 231         __le16 tag;
 232         u8 lun;
 233         u8 target;
 234         u8 srb_status;
 235         u8 scsi_status;
 236         u8 reserved;
 237         u8 payload_sz;          /* payload size in 4-byte */
 238         u8 variable[STATUS_VAR_LEN];
 239 };
 240
 241 struct ver_info {
 242         u32 major;
 243         u32 minor;
 244         u32 oem;
 245         u32 build;
 246         u32 reserved[2];
 247 };
 248
 249 struct st_frame {
 250         u32 base[6];
 251         u32 rom_addr;
 252
 253         struct ver_info drv_ver;
 254         struct ver_info bios_ver;
 255
 256         u32 bus;
 257         u32 slot;
 258         u32 irq_level;
 259         u32 irq_vec;
 260         u32 id;
 261         u32 subid;
 262
 263         u32 dimm_size;
 264         u8 dimm_type;
 265         u8 reserved[3];
 266
 267         u32 channel;
 268         u32 reserved1;
 269 };
 270
 271 struct st_drvver {
 272         u32 major;
 273         u32 minor;
 274         u32 oem;
 275         u32 build;
 276         u32 signature[2];
 277         u8 console_id;
 278         u8 host_no;
 279         u8 reserved0[2];
 280         u32 reserved[3];
 281 };
 282
 283 struct st_ccb {
 284         struct req_msg *req;
 285         struct scsi_cmnd *cmd;
 286
 287         void *sense_buffer;
 288         unsigned int sense_bufflen;
 289         int sg_count;
 290
 291         u32 req_type;
 292         u8 srb_status;
 293         u8 scsi_status;
 294         u8 reserved[2];
 295 };
 296
 297 struct st_hba {
 298         void __iomem *mmio_base;        /* iomapped PCI memory space */
 299         void *dma_mem;
 300         dma_addr_t dma_handle;
 301         size_t dma_size;
 302
 303         struct Scsi_Host *host;
 304         struct pci_dev *pdev;
 305
 306         struct req_msg * (*alloc_rq) (struct st_hba *);
 307         int (*map_sg)(struct st_hba *, struct req_msg *, struct st_ccb *);
 308         void (*send) (struct st_hba *, struct req_msg *, u16);
 309
 310         u32 req_head;
 311         u32 req_tail;
 312         u32 status_head;
 313         u32 status_tail;
 314
 315         struct status_msg *status_buffer;
 316         void *copy_buffer; /* temp buffer for driver-handled commands */
 317         struct st_ccb *ccb;
 318         struct st_ccb *wait_ccb;
 319         __le32 *scratch;
 320
 321         char work_q_name[20];
 322         struct workqueue_struct *work_q;
 323         struct work_struct reset_work;
 324         wait_queue_head_t reset_waitq;
 325         unsigned int mu_status;
 326         unsigned int cardtype;
 327         int msi_enabled;
 328         int out_req_cnt;
 329         u32 extra_offset;
 330         u16 rq_count;
 331         u16 rq_size;
 332         u16 sts_count;
 333         u8  supports_pm;
 334 };
 335
 336 struct st_card_info {
 337         struct req_msg * (*alloc_rq) (struct st_hba *);
 338         int (*map_sg)(struct st_hba *, struct req_msg *, struct st_ccb *);
 339         void (*send) (struct st_hba *, struct req_msg *, u16);
 340         unsigned int max_id;
 341         unsigned int max_lun;
 342         unsigned int max_channel;
 343         u16 rq_count;
 344         u16 rq_size;
 345         u16 sts_count;
 346 };
 347
 348 static int msi;
 349 module_param(msi, int, 0);
 350 MODULE_PARM_DESC(msi, "Enable Message Signaled Interrupts(0=off, 1=on)");
 351
 352 static const char console_inq_page[] =
 353 {
 354         0x03,0x00,0x03,0x03,0xFA,0x00,0x00,0x30,
 355         0x50,0x72,0x6F,0x6D,0x69,0x73,0x65,0x20,        /* "Promise " */
 356         0x52,0x41,0x49,0x44,0x20,0x43,0x6F,0x6E,        /* "RAID Con" */
 357         0x73,0x6F,0x6C,0x65,0x20,0x20,0x20,0x20,        /* "sole    " */
 358         0x31,0x2E,0x30,0x30,0x20,0x20,0x20,0x20,        /* "1.00    " */
 359         0x53,0x58,0x2F,0x52,0x53,0x41,0x46,0x2D,        /* "SX/RSAF-" */
 360         0x54,0x45,0x31,0x2E,0x30,0x30,0x20,0x20,        /* "TE1.00  " */
 361         0x0C,0x20,0x20,0x20,0x20,0x20,0x20,0x20
 362 };
 363
 364 MODULE_AUTHOR("Ed Lin");
 365 MODULE_DESCRIPTION("Promise Technology SuperTrak EX Controllers");
 366 MODULE_LICENSE("GPL");
 367 MODULE_VERSION(ST_DRIVER_VERSION);
 368
 369 static struct status_msg *stex_get_status(struct st_hba *hba)
 370 {
 371         struct status_msg *status = hba->status_buffer + hba->status_tail;
 372
 373         ++hba->status_tail;
 374         hba->status_tail %= hba->sts_count+1;
 375
 376         return status;
 377 }
 378
 379 static void stex_invalid_field(struct scsi_cmnd *cmd,
 380                                void (*done)(struct scsi_cmnd *))
 381 {
 382         cmd->result = (DRIVER_SENSE << 24) | SAM_STAT_CHECK_CONDITION;
 383
 384         /* "Invalid field in cdb" */
 385         scsi_build_sense_buffer(0, cmd->sense_buffer, ILLEGAL_REQUEST, 0x24,
 386                                 0x0);
 387         done(cmd);
 388 }
 389
 390 static struct req_msg *stex_alloc_req(struct st_hba *hba)
 391 {
 392         struct req_msg *req = hba->dma_mem + hba->req_head * hba->rq_size;
 393
 394         ++hba->req_head;
 395         hba->req_head %= hba->rq_count+1;
 396
 397         return req;
 398 }
 399
 400 static struct req_msg *stex_ss_alloc_req(struct st_hba *hba)
 401 {
 402         return (struct req_msg *)(hba->dma_mem +
 403                 hba->req_head * hba->rq_size + sizeof(struct st_msg_header));
 404 }
 405
 406 static int stex_map_sg(struct st_hba *hba,
 407         struct req_msg *req, struct st_ccb *ccb)
 408 {
 409         struct scsi_cmnd *cmd;
 410         struct scatterlist *sg;
 411         struct st_sgtable *dst;
 412         struct st_sgitem *table;
 413         int i, nseg;
 414
 415         cmd = ccb->cmd;
 416         nseg = scsi_dma_map(cmd);
 417         BUG_ON(nseg < 0);
 418         if (nseg) {
 419                 dst = (struct st_sgtable *)req->variable;
 420
 421                 ccb->sg_count = nseg;
 422                 dst->sg_count = cpu_to_le16((u16)nseg);
 423                 dst->max_sg_count = cpu_to_le16(hba->host->sg_tablesize);
 424                 dst->sz_in_byte = cpu_to_le32(scsi_bufflen(cmd));
 425
 426                 table = (struct st_sgitem *)(dst + 1);
 427                 scsi_for_each_sg(cmd, sg, nseg, i) {
 428                         table[i].count = cpu_to_le32((u32)sg_dma_len(sg));
 429                         table[i].addr = cpu_to_le64(sg_dma_address(sg));
 430                         table[i].ctrl = SG_CF_64B | SG_CF_HOST;
 431                 }
 432                 table[--i].ctrl |= SG_CF_EOT;
 433         }
 434
 435         return nseg;
 436 }
 437
 438 static int stex_ss_map_sg(struct st_hba *hba,
 439         struct req_msg *req, struct st_ccb *ccb)
 440 {
 441         struct scsi_cmnd *cmd;
 442         struct scatterlist *sg;
 443         struct st_sgtable *dst;
 444         struct st_ss_sgitem *table;
 445         int i, nseg;
 446
 447         cmd = ccb->cmd;
 448         nseg = scsi_dma_map(cmd);
 449         BUG_ON(nseg < 0);
 450         if (nseg) {
 451                 dst = (struct st_sgtable *)req->variable;
 452
 453                 ccb->sg_count = nseg;
 454                 dst->sg_count = cpu_to_le16((u16)nseg);
 455                 dst->max_sg_count = cpu_to_le16(hba->host->sg_tablesize);
 456                 dst->sz_in_byte = cpu_to_le32(scsi_bufflen(cmd));
 457
 458                 table = (struct st_ss_sgitem *)(dst + 1);
 459                 scsi_for_each_sg(cmd, sg, nseg, i) {
 460                         table[i].count = cpu_to_le32((u32)sg_dma_len(sg));
 461                         table[i].addr =
 462                                 cpu_to_le32(sg_dma_address(sg) & 0xffffffff);
 463                         table[i].addr_hi =
 464                                 cpu_to_le32((sg_dma_address(sg) >> 16) >> 16);
 465                 }
 466         }
 467
 468         return nseg;
 469 }
 470
 471 static void stex_controller_info(struct st_hba *hba, struct st_ccb *ccb)
 472 {
 473         struct st_frame *p;
 474         size_t count = sizeof(struct st_frame);
 475
 476         p = hba->copy_buffer;
 477         scsi_sg_copy_to_buffer(ccb->cmd, p, count);
 478         memset(p->base, 0, sizeof(u32)*6);
 479         *(unsigned long *)(p->base) = pci_resource_start(hba->pdev, 0);
 480         p->rom_addr = 0;
 481
 482         p->drv_ver.major = ST_VER_MAJOR;
 483         p->drv_ver.minor = ST_VER_MINOR;
 484         p->drv_ver.oem = ST_OEM;
 485         p->drv_ver.build = ST_BUILD_VER;
 486
 487         p->bus = hba->pdev->bus->number;
 488         p->slot = hba->pdev->devfn;
 489         p->irq_level = 0;
 490         p->irq_vec = hba->pdev->irq;
 491         p->id = hba->pdev->vendor << 16 | hba->pdev->device;
 492         p->subid =
 493                 hba->pdev->subsystem_vendor << 16 | hba->pdev->subsystem_device;
 494
 495         scsi_sg_copy_from_buffer(ccb->cmd, p, count);
 496 }
 497
 498 static void
 499 stex_send_cmd(struct st_hba *hba, struct req_msg *req, u16 tag)
 500 {
 501         req->tag = cpu_to_le16(tag);
 502
 503         hba->ccb[tag].req = req;
 504         hba->out_req_cnt++;
 505
 506         writel(hba->req_head, hba->mmio_base + IMR0);
 507         writel(MU_INBOUND_DOORBELL_REQHEADCHANGED, hba->mmio_base + IDBL);
 508         readl(hba->mmio_base + IDBL); /* flush */
 509 }
 510
 511 static void
 512 stex_ss_send_cmd(struct st_hba *hba, struct req_msg *req, u16 tag)
 513 {
 514         struct scsi_cmnd *cmd;
 515         struct st_msg_header *msg_h;
 516         dma_addr_t addr;
 517
 518         req->tag = cpu_to_le16(tag);
 519
 520         hba->ccb[tag].req = req;
 521         hba->out_req_cnt++;
 522
 523         cmd = hba->ccb[tag].cmd;
 524         msg_h = (struct st_msg_header *)req - 1;
 525         if (likely(cmd)) {
 526                 msg_h->channel = (u8)cmd->device->channel;
 527                 msg_h->timeout = cpu_to_le16(cmd->request->timeout/HZ);
 528         }
 529         addr = hba->dma_handle + hba->req_head * hba->rq_size;
 530         addr += (hba->ccb[tag].sg_count+4)/11;
 531         msg_h->handle = cpu_to_le64(addr);
 532
 533         ++hba->req_head;
 534         hba->req_head %= hba->rq_count+1;
 535
 536         writel((addr >> 16) >> 16, hba->mmio_base + YH2I_REQ_HI);
 537         readl(hba->mmio_base + YH2I_REQ_HI); /* flush */
 538         writel(addr, hba->mmio_base + YH2I_REQ);
 539         readl(hba->mmio_base + YH2I_REQ); /* flush */
 540 }
 541
 542 static void return_abnormal_state(struct st_hba *hba, int status)
 543 {
 544         struct st_ccb *ccb;
 545         unsigned long flags;
 546         u16 tag;
 547
 548         spin_lock_irqsave(hba->host->host_lock, flags);
 549         for (tag = 0; tag < hba->host->can_queue; tag++) {
 550                 ccb = &hba->ccb[tag];
 551                 if (ccb->req == NULL)
 552                         continue;
 553                 ccb->req = NULL;
 554                 if (ccb->cmd) {
 555                         scsi_dma_unmap(ccb->cmd);
 556                         ccb->cmd->result = status << 16;
 557                         ccb->cmd->scsi_done(ccb->cmd);
 558                         ccb->cmd = NULL;
 559                 }
 560         }
 561         spin_unlock_irqrestore(hba->host->host_lock, flags);
 562 }
 563 static int
 564 stex_slave_config(struct scsi_device *sdev)
 565 {
 566         sdev->use_10_for_rw = 1;
 567         sdev->use_10_for_ms = 1;
 568         blk_queue_rq_timeout(sdev->request_queue, 60 * HZ);
 569
 570         return 0;
 571 }
 572
 573 static int
 574 stex_queuecommand_lck(struct scsi_cmnd *cmd, void (*done)(struct scsi_cmnd *))
 575 {
 576         struct st_hba *hba;
 577         struct Scsi_Host *host;
 578         unsigned int id, lun;
 579         struct req_msg *req;
 580         u16 tag;
 581
 582         host = cmd->device->host;
 583         id = cmd->device->id;
 584         lun = cmd->device->lun;
 585         hba = (struct st_hba *) &host->hostdata[0];
 586         if (hba->mu_status == MU_STATE_NOCONNECT) {
 587                 cmd->result = DID_NO_CONNECT;
 588                 done(cmd);
 589                 return 0;
 590         }
 591         if (unlikely(hba->mu_status != MU_STATE_STARTED))
 592                 return SCSI_MLQUEUE_HOST_BUSY;
 593
 594         switch (cmd->cmnd[0]) {
 595         case MODE_SENSE_10:
 596         {
 597                 static char ms10_caching_page[12] =
 598                         { 0, 0x12, 0, 0, 0, 0, 0, 0, 0x8, 0xa, 0x4, 0 };
 599                 unsigned char page;
 600
 601                 page = cmd->cmnd[2] & 0x3f;
 602                 if (page == 0x8 || page == 0x3f) {
 603                         scsi_sg_copy_from_buffer(cmd, ms10_caching_page,
 604                                                  sizeof(ms10_caching_page));
 605                         cmd->result = DID_OK << 16 | COMMAND_COMPLETE << 8;
 606                         done(cmd);
 607                 } else
 608                         stex_invalid_field(cmd, done);
 609                 return 0;
 610         }
 611         case REPORT_LUNS:
 612                 /*
 613                  * The shasta firmware does not report actual luns in the
 614                  * target, so fail the command to force sequential lun scan.
 615                  * Also, the console device does not support this command.
 616                  */
 617                 if (hba->cardtype == st_shasta || id == host->max_id - 1) {
 618                         stex_invalid_field(cmd, done);
 619                         return 0;
 620                 }
 621                 break;
 622         case TEST_UNIT_READY:
 623                 if (id == host->max_id - 1) {
 624                         cmd->result = DID_OK << 16 | COMMAND_COMPLETE << 8;
 625                         done(cmd);
 626                         return 0;
 627                 }
 628                 break;
 629         case INQUIRY:
 630                 if (lun >= host->max_lun) {
 631                         cmd->result = DID_NO_CONNECT << 16;
 632                         done(cmd);
 633                         return 0;
 634                 }
 635                 if (id != host->max_id - 1)
 636                         break;
 637                 if (!lun && !cmd->device->channel &&
 638                         (cmd->cmnd[1] & INQUIRY_EVPD) == 0) {
 639                         scsi_sg_copy_from_buffer(cmd, (void *)console_inq_page,
 640                                                  sizeof(console_inq_page));
 641                         cmd->result = DID_OK << 16 | COMMAND_COMPLETE << 8;
 642                         done(cmd);
 643                 } else
 644                         stex_invalid_field(cmd, done);
 645                 return 0;
 646         case PASSTHRU_CMD:
 647                 if (cmd->cmnd[1] == PASSTHRU_GET_DRVVER) {
 648                         struct st_drvver ver;
 649                         size_t cp_len = sizeof(ver);
 650
 651                         ver.major = ST_VER_MAJOR;
 652                         ver.minor = ST_VER_MINOR;
 653                         ver.oem = ST_OEM;
 654                         ver.build = ST_BUILD_VER;
 655                         ver.signature[0] = PASSTHRU_SIGNATURE;
 656                         ver.console_id = host->max_id - 1;
 657                         ver.host_no = hba->host->host_no;
 658                         cp_len = scsi_sg_copy_from_buffer(cmd, &ver, cp_len);
 659                         cmd->result = sizeof(ver) == cp_len ?
 660                                 DID_OK << 16 | COMMAND_COMPLETE << 8 :
 661                                 DID_ERROR << 16 | COMMAND_COMPLETE << 8;
 662                         done(cmd);
 663                         return 0;
 664                 }
 665         default:
 666                 break;
 667         }
 668
 669         cmd->scsi_done = done;
 670
 671         tag = cmd->request->tag;
 672
 673         if (unlikely(tag >= host->can_queue))
 674                 return SCSI_MLQUEUE_HOST_BUSY;
 675
 676         req = hba->alloc_rq(hba);
 677
 678         req->lun = lun;
 679         req->target = id;
 680
 681         /* cdb */
 682         memcpy(req->cdb, cmd->cmnd, STEX_CDB_LENGTH);
 683
 684         if (cmd->sc_data_direction == DMA_FROM_DEVICE)
 685                 req->data_dir = MSG_DATA_DIR_IN;
 686         else if (cmd->sc_data_direction == DMA_TO_DEVICE)
 687                 req->data_dir = MSG_DATA_DIR_OUT;
 688         else
 689                 req->data_dir = MSG_DATA_DIR_ND;
 690
 691         hba->ccb[tag].cmd = cmd;
 692         hba->ccb[tag].sense_bufflen = SCSI_SENSE_BUFFERSIZE;
 693         hba->ccb[tag].sense_buffer = cmd->sense_buffer;
 694
 695         if (!hba->map_sg(hba, req, &hba->ccb[tag])) {
 696                 hba->ccb[tag].sg_count = 0;
 697                 memset(&req->variable[0], 0, 8);
 698         }
 699
 700         hba->send(hba, req, tag);
 701         return 0;
 702 }
 703
 704 static DEF_SCSI_QCMD(stex_queuecommand)
 705
 706 static void stex_scsi_done(struct st_ccb *ccb)
 707 {
 708         struct scsi_cmnd *cmd = ccb->cmd;
 709         int result;
 710
 711         if (ccb->srb_status == SRB_STATUS_SUCCESS || ccb->srb_status == 0) {
 712                 result = ccb->scsi_status;
 713                 switch (ccb->scsi_status) {
 714                 case SAM_STAT_GOOD:
 715                         result |= DID_OK << 16 | COMMAND_COMPLETE << 8;
 716                         break;
 717                 case SAM_STAT_CHECK_CONDITION:
 718                         result |= DRIVER_SENSE << 24;
 719                         break;
 720                 case SAM_STAT_BUSY:
 721                         result |= DID_BUS_BUSY << 16 | COMMAND_COMPLETE << 8;
 722                         break;
 723                 default:
 724                         result |= DID_ERROR << 16 | COMMAND_COMPLETE << 8;
 725                         break;
 726                 }
 727         }
 728         else if (ccb->srb_status & SRB_SEE_SENSE)
 729                 result = DRIVER_SENSE << 24 | SAM_STAT_CHECK_CONDITION;
 730         else switch (ccb->srb_status) {
 731                 case SRB_STATUS_SELECTION_TIMEOUT:
 732                         result = DID_NO_CONNECT << 16 | COMMAND_COMPLETE << 8;
 733                         break;
 734                 case SRB_STATUS_BUSY:
 735                         result = DID_BUS_BUSY << 16 | COMMAND_COMPLETE << 8;
 736                         break;
 737                 case SRB_STATUS_INVALID_REQUEST:
 738                 case SRB_STATUS_ERROR:
 739                 default:
 740                         result = DID_ERROR << 16 | COMMAND_COMPLETE << 8;
 741                         break;
 742         }
 743
 744         cmd->result = result;
 745         cmd->scsi_done(cmd);
 746 }
 747
 748 static void stex_copy_data(struct st_ccb *ccb,
 749         struct status_msg *resp, unsigned int variable)
 750 {
 751         if (resp->scsi_status != SAM_STAT_GOOD) {
 752                 if (ccb->sense_buffer != NULL)
 753                         memcpy(ccb->sense_buffer, resp->variable,
 754                                 min(variable, ccb->sense_bufflen));
 755                 return;
 756         }
 757
 758         if (ccb->cmd == NULL)
 759                 return;
 760         scsi_sg_copy_from_buffer(ccb->cmd, resp->variable, variable);
 761 }
 762
 763 static void stex_check_cmd(struct st_hba *hba,
 764         struct st_ccb *ccb, struct status_msg *resp)
 765 {
 766         if (ccb->cmd->cmnd[0] == MGT_CMD &&
 767                 resp->scsi_status != SAM_STAT_CHECK_CONDITION)
 768                 scsi_set_resid(ccb->cmd, scsi_bufflen(ccb->cmd) -
 769                         le32_to_cpu(*(__le32 *)&resp->variable[0]));
 770 }
 771
 772 static void stex_mu_intr(struct st_hba *hba, u32 doorbell)
 773 {
 774         void __iomem *base = hba->mmio_base;
 775         struct status_msg *resp;
 776         struct st_ccb *ccb;
 777         unsigned int size;
 778         u16 tag;
 779
 780         if (unlikely(!(doorbell & MU_OUTBOUND_DOORBELL_STATUSHEADCHANGED)))
 781                 return;
 782
 783         /* status payloads */
 784         hba->status_head = readl(base + OMR1);
 785         if (unlikely(hba->status_head > hba->sts_count)) {
 786                 printk(KERN_WARNING DRV_NAME "(%s): invalid status head\n",
 787                         pci_name(hba->pdev));
 788                 return;
 789         }
 790
 791         /*
 792          * it's not a valid status payload if:
 793          * 1. there are no pending requests(e.g. during init stage)
 794          * 2. there are some pending requests, but the controller is in
 795          *     reset status, and its type is not st_yosemite
 796          * firmware of st_yosemite in reset status will return pending requests
 797          * to driver, so we allow it to pass
 798          */
 799         if (unlikely(hba->out_req_cnt <= 0 ||
 800                         (hba->mu_status == MU_STATE_RESETTING &&
 801                          hba->cardtype != st_yosemite))) {
 802                 hba->status_tail = hba->status_head;
 803                 goto update_status;
 804         }
 805
 806         while (hba->status_tail != hba->status_head) {
 807                 resp = stex_get_status(hba);
 808                 tag = le16_to_cpu(resp->tag);
 809                 if (unlikely(tag >= hba->host->can_queue)) {
 810                         printk(KERN_WARNING DRV_NAME
 811                                 "(%s): invalid tag\n", pci_name(hba->pdev));
 812                         continue;
 813                 }
 814
 815                 hba->out_req_cnt--;
 816                 ccb = &hba->ccb[tag];
 817                 if (unlikely(hba->wait_ccb == ccb))
 818                         hba->wait_ccb = NULL;
 819                 if (unlikely(ccb->req == NULL)) {
 820                         printk(KERN_WARNING DRV_NAME
 821                                 "(%s): lagging req\n", pci_name(hba->pdev));
 822                         continue;
 823                 }
 824
 825                 size = resp->payload_sz * sizeof(u32); /* payload size */
 826                 if (unlikely(size < sizeof(*resp) - STATUS_VAR_LEN ||
 827                         size > sizeof(*resp))) {
 828                         printk(KERN_WARNING DRV_NAME "(%s): bad status size\n",
 829                                 pci_name(hba->pdev));
 830                 } else {
 831                         size -= sizeof(*resp) - STATUS_VAR_LEN; /* copy size */
 832                         if (size)
 833                                 stex_copy_data(ccb, resp, size);
 834                 }
 835
 836                 ccb->req = NULL;
 837                 ccb->srb_status = resp->srb_status;
 838                 ccb->scsi_status = resp->scsi_status;
 839
 840                 if (likely(ccb->cmd != NULL)) {
 841                         if (hba->cardtype == st_yosemite)
 842                                 stex_check_cmd(hba, ccb, resp);
 843
 844                         if (unlikely(ccb->cmd->cmnd[0] == PASSTHRU_CMD &&
 845                                 ccb->cmd->cmnd[1] == PASSTHRU_GET_ADAPTER))
 846                                 stex_controller_info(hba, ccb);
 847
 848                         scsi_dma_unmap(ccb->cmd);
 849                         stex_scsi_done(ccb);
 850                 } else
 851                         ccb->req_type = 0;
 852         }
 853
 854 update_status:
 855         writel(hba->status_head, base + IMR1);
 856         readl(base + IMR1); /* flush */
 857 }
 858
 859 static irqreturn_t stex_intr(int irq, void *__hba)
 860 {
 861         struct st_hba *hba = __hba;
 862         void __iomem *base = hba->mmio_base;
 863         u32 data;
 864         unsigned long flags;
 865
 866         spin_lock_irqsave(hba->host->host_lock, flags);
 867
 868         data = readl(base + ODBL);
 869
 870         if (data && data != 0xffffffff) {
 871                 /* clear the interrupt */
 872                 writel(data, base + ODBL);
 873                 readl(base + ODBL); /* flush */
 874                 stex_mu_intr(hba, data);
 875                 spin_unlock_irqrestore(hba->host->host_lock, flags);
 876                 if (unlikely(data & MU_OUTBOUND_DOORBELL_REQUEST_RESET &&
 877                         hba->cardtype == st_shasta))
 878                         queue_work(hba->work_q, &hba->reset_work);
 879                 return IRQ_HANDLED;
 880         }
 881
 882         spin_unlock_irqrestore(hba->host->host_lock, flags);
 883
 884         return IRQ_NONE;
 885 }
 886
 887 static void stex_ss_mu_intr(struct st_hba *hba)
 888 {
 889         struct status_msg *resp;
 890         struct st_ccb *ccb;
 891         __le32 *scratch;
 892         unsigned int size;
 893         int count = 0;
 894         u32 value;
 895         u16 tag;
 896
 897         if (unlikely(hba->out_req_cnt <= 0 ||
 898                         hba->mu_status == MU_STATE_RESETTING))
 899                 return;
 900
 901         while (count < hba->sts_count) {
 902                 scratch = hba->scratch + hba->status_tail;
 903                 value = le32_to_cpu(*scratch);
 904                 if (unlikely(!(value & SS_STS_NORMAL)))
 905                         return;
 906
 907                 resp = hba->status_buffer + hba->status_tail;
 908                 *scratch = 0;
 909                 ++count;
 910                 ++hba->status_tail;
 911                 hba->status_tail %= hba->sts_count+1;
 912
 913                 tag = (u16)value;
 914                 if (unlikely(tag >= hba->host->can_queue)) {
 915                         printk(KERN_WARNING DRV_NAME
 916                                 "(%s): invalid tag\n", pci_name(hba->pdev));
 917                         continue;
 918                 }
 919
 920                 hba->out_req_cnt--;
 921                 ccb = &hba->ccb[tag];
 922                 if (unlikely(hba->wait_ccb == ccb))
 923                         hba->wait_ccb = NULL;
 924                 if (unlikely(ccb->req == NULL)) {
 925                         printk(KERN_WARNING DRV_NAME
 926                                 "(%s): lagging req\n", pci_name(hba->pdev));
 927                         continue;
 928                 }
 929
 930                 ccb->req = NULL;
 931                 if (likely(value & SS_STS_DONE)) { /* normal case */
 932                         ccb->srb_status = SRB_STATUS_SUCCESS;
 933                         ccb->scsi_status = SAM_STAT_GOOD;
 934                 } else {
 935                         ccb->srb_status = resp->srb_status;
 936                         ccb->scsi_status = resp->scsi_status;
 937                         size = resp->payload_sz * sizeof(u32);
 938                         if (unlikely(size < sizeof(*resp) - STATUS_VAR_LEN ||
 939                                 size > sizeof(*resp))) {
 940                                 printk(KERN_WARNING DRV_NAME
 941                                         "(%s): bad status size\n",
 942                                         pci_name(hba->pdev));
 943                         } else {
 944                                 size -= sizeof(*resp) - STATUS_VAR_LEN;
 945                                 if (size)
 946                                         stex_copy_data(ccb, resp, size);
 947                         }
 948                         if (likely(ccb->cmd != NULL))
 949                                 stex_check_cmd(hba, ccb, resp);
 950                 }
 951
 952                 if (likely(ccb->cmd != NULL)) {
 953                         scsi_dma_unmap(ccb->cmd);
 954                         stex_scsi_done(ccb);
 955                 } else
 956                         ccb->req_type = 0;
 957         }
 958 }
 959
 960 static irqreturn_t stex_ss_intr(int irq, void *__hba)
 961 {
 962         struct st_hba *hba = __hba;
 963         void __iomem *base = hba->mmio_base;
 964         u32 data;
 965         unsigned long flags;
 966
 967         spin_lock_irqsave(hba->host->host_lock, flags);
 968
 969         data = readl(base + YI2H_INT);
 970         if (data && data != 0xffffffff) {
 971                 /* clear the interrupt */
 972                 writel(data, base + YI2H_INT_C);
 973                 stex_ss_mu_intr(hba);
 974                 spin_unlock_irqrestore(hba->host->host_lock, flags);
 975                 if (unlikely(data & SS_I2H_REQUEST_RESET))
 976                         queue_work(hba->work_q, &hba->reset_work);
 977                 return IRQ_HANDLED;
 978         }
 979
 980         spin_unlock_irqrestore(hba->host->host_lock, flags);
 981
 982         return IRQ_NONE;
 983 }
 984
 985 static int stex_common_handshake(struct st_hba *hba)
 986 {
 987         void __iomem *base = hba->mmio_base;
 988         struct handshake_frame *h;
 989         dma_addr_t status_phys;
 990         u32 data;
 991         unsigned long before;
 992
 993         if (readl(base + OMR0) != MU_HANDSHAKE_SIGNATURE) {
 994                 writel(MU_INBOUND_DOORBELL_HANDSHAKE, base + IDBL);
 995                 readl(base + IDBL);
 996                 before = jiffies;
 997                 while (readl(base + OMR0) != MU_HANDSHAKE_SIGNATURE) {
 998                         if (time_after(jiffies, before + MU_MAX_DELAY * HZ)) {
 999                                 printk(KERN_ERR DRV_NAME
1000                                         "(%s): no handshake signature\n",
1001                                         pci_name(hba->pdev));
1002                                 return -1;
1003                         }
1004                         rmb();
1005                         msleep(1);
1006                 }
1007         }
1008
1009         udelay(10);
1010
1011         data = readl(base + OMR1);
1012         if ((data & 0xffff0000) == MU_HANDSHAKE_SIGNATURE_HALF) {
1013                 data &= 0x0000ffff;
1014                 if (hba->host->can_queue > data) {
1015                         hba->host->can_queue = data;
1016                         hba->host->cmd_per_lun = data;
1017                 }
1018         }
1019
1020         h = (struct handshake_frame *)hba->status_buffer;
1021         h->rb_phy = cpu_to_le64(hba->dma_handle);
1022         h->req_sz = cpu_to_le16(hba->rq_size);
1023         h->req_cnt = cpu_to_le16(hba->rq_count+1);
1024         h->status_sz = cpu_to_le16(sizeof(struct status_msg));
1025         h->status_cnt = cpu_to_le16(hba->sts_count+1);
1026         h->hosttime = cpu_to_le64(ktime_get_real_seconds());
1027         h->partner_type = HMU_PARTNER_TYPE;
1028         if (hba->extra_offset) {
1029                 h->extra_offset = cpu_to_le32(hba->extra_offset);
1030                 h->extra_size = cpu_to_le32(hba->dma_size - hba->extra_offset);
1031         } else
1032                 h->extra_offset = h->extra_size = 0;
1033
1034         status_phys = hba->dma_handle + (hba->rq_count+1) * hba->rq_size;
1035         writel(status_phys, base + IMR0);
1036         readl(base + IMR0);
1037         writel((status_phys >> 16) >> 16, base + IMR1);
1038         readl(base + IMR1);
1039
1040         writel((status_phys >> 16) >> 16, base + OMR0); /* old fw compatible */
1041         readl(base + OMR0);
1042         writel(MU_INBOUND_DOORBELL_HANDSHAKE, base + IDBL);
1043         readl(base + IDBL); /* flush */
1044
1045         udelay(10);
1046         before = jiffies;
1047         while (readl(base + OMR0) != MU_HANDSHAKE_SIGNATURE) {
1048                 if (time_after(jiffies, before + MU_MAX_DELAY * HZ)) {
1049                         printk(KERN_ERR DRV_NAME
1050                                 "(%s): no signature after handshake frame\n",
1051                                 pci_name(hba->pdev));
1052                         return -1;
1053                 }
1054                 rmb();
1055                 msleep(1);
1056         }
1057
1058         writel(0, base + IMR0);
1059         readl(base + IMR0);
1060         writel(0, base + OMR0);
1061         readl(base + OMR0);
1062         writel(0, base + IMR1);
1063         readl(base + IMR1);
1064         writel(0, base + OMR1);
1065         readl(base + OMR1); /* flush */
1066         return 0;
1067 }
1068
1069 static int stex_ss_handshake(struct st_hba *hba)
1070 {
1071         void __iomem *base = hba->mmio_base;
1072         struct st_msg_header *msg_h;
1073         struct handshake_frame *h;
1074         __le32 *scratch;
1075         u32 data, scratch_size;
1076         unsigned long before;
1077         int ret = 0;
1078
1079         before = jiffies;
1080         while ((readl(base + YIOA_STATUS) & SS_MU_OPERATIONAL) == 0) {
1081                 if (time_after(jiffies, before + MU_MAX_DELAY * HZ)) {
1082                         printk(KERN_ERR DRV_NAME
1083                                 "(%s): firmware not operational\n",
1084                                 pci_name(hba->pdev));
1085                         return -1;
1086                 }
1087                 msleep(1);
1088         }
1089
1090         msg_h = (struct st_msg_header *)hba->dma_mem;
1091         msg_h->handle = cpu_to_le64(hba->dma_handle);
1092         msg_h->flag = SS_HEAD_HANDSHAKE;
1093
1094         h = (struct handshake_frame *)(msg_h + 1);
1095         h->rb_phy = cpu_to_le64(hba->dma_handle);
1096         h->req_sz = cpu_to_le16(hba->rq_size);
1097         h->req_cnt = cpu_to_le16(hba->rq_count+1);
1098         h->status_sz = cpu_to_le16(sizeof(struct status_msg));
1099         h->status_cnt = cpu_to_le16(hba->sts_count+1);
1100         h->hosttime = cpu_to_le64(ktime_get_real_seconds());
1101         h->partner_type = HMU_PARTNER_TYPE;
1102         h->extra_offset = h->extra_size = 0;
1103         scratch_size = (hba->sts_count+1)*sizeof(u32);
1104         h->scratch_size = cpu_to_le32(scratch_size);
1105
1106         data = readl(base + YINT_EN);
1107         data &= ~4;
1108         writel(data, base + YINT_EN);
1109         writel((hba->dma_handle >> 16) >> 16, base + YH2I_REQ_HI);
1110         readl(base + YH2I_REQ_HI);
1111         writel(hba->dma_handle, base + YH2I_REQ);
1112         readl(base + YH2I_REQ); /* flush */
1113
1114         scratch = hba->scratch;
1115         before = jiffies;
1116         while (!(le32_to_cpu(*scratch) & SS_STS_HANDSHAKE)) {
1117                 if (time_after(jiffies, before + MU_MAX_DELAY * HZ)) {
1118                         printk(KERN_ERR DRV_NAME
1119                                 "(%s): no signature after handshake frame\n",
1120                                 pci_name(hba->pdev));
1121                         ret = -1;
1122                         break;
1123                 }
1124                 rmb();
1125                 msleep(1);
1126         }
1127
1128         memset(scratch, 0, scratch_size);
1129         msg_h->flag = 0;
1130         return ret;
1131 }
1132
1133 static int stex_handshake(struct st_hba *hba)
1134 {
1135         int err;
1136         unsigned long flags;
1137         unsigned int mu_status;
1138
1139         err = (hba->cardtype == st_yel) ?
1140                 stex_ss_handshake(hba) : stex_common_handshake(hba);
1141         spin_lock_irqsave(hba->host->host_lock, flags);
1142         mu_status = hba->mu_status;
1143         if (err == 0) {
1144                 hba->req_head = 0;
1145                 hba->req_tail = 0;
1146                 hba->status_head = 0;
1147                 hba->status_tail = 0;
1148                 hba->out_req_cnt = 0;
1149                 hba->mu_status = MU_STATE_STARTED;
1150         } else
1151                 hba->mu_status = MU_STATE_FAILED;
1152         if (mu_status == MU_STATE_RESETTING)
1153                 wake_up_all(&hba->reset_waitq);
1154         spin_unlock_irqrestore(hba->host->host_lock, flags);
1155         return err;
1156 }
1157
1158 static int stex_abort(struct scsi_cmnd *cmd)
1159 {
1160         struct Scsi_Host *host = cmd->device->host;
1161         struct st_hba *hba = (struct st_hba *)host->hostdata;
1162         u16 tag = cmd->request->tag;
1163         void __iomem *base;
1164         u32 data;
1165         int result = SUCCESS;
1166         unsigned long flags;
1167
1168         scmd_printk(KERN_INFO, cmd, "aborting command\n");
1169
1170         base = hba->mmio_base;
1171         spin_lock_irqsave(host->host_lock, flags);
1172         if (tag < host->can_queue &&
1173                 hba->ccb[tag].req && hba->ccb[tag].cmd == cmd)
1174                 hba->wait_ccb = &hba->ccb[tag];
1175         else
1176                 goto out;
1177
1178         if (hba->cardtype == st_yel) {
1179                 data = readl(base + YI2H_INT);
1180                 if (data == 0 || data == 0xffffffff)
1181                         goto fail_out;
1182
1183                 writel(data, base + YI2H_INT_C);
1184                 stex_ss_mu_intr(hba);
1185         } else {
1186                 data = readl(base + ODBL);
1187                 if (data == 0 || data == 0xffffffff)
1188                         goto fail_out;
1189
1190                 writel(data, base + ODBL);
1191                 readl(base + ODBL); /* flush */
1192
1193                 stex_mu_intr(hba, data);
1194         }
1195         if (hba->wait_ccb == NULL) {
1196                 printk(KERN_WARNING DRV_NAME
1197                         "(%s): lost interrupt\n", pci_name(hba->pdev));
1198                 goto out;
1199         }
1200
1201 fail_out:
1202         scsi_dma_unmap(cmd);
1203         hba->wait_ccb->req = NULL; /* nullify the req's future return */
1204         hba->wait_ccb = NULL;
1205         result = FAILED;
1206 out:
1207         spin_unlock_irqrestore(host->host_lock, flags);
1208         return result;
1209 }
1210
1211 static void stex_hard_reset(struct st_hba *hba)
1212 {
1213         struct pci_bus *bus;
1214         int i;
1215         u16 pci_cmd;
1216         u8 pci_bctl;
1217
1218         for (i = 0; i < 16; i++)
1219                 pci_read_config_dword(hba->pdev, i * 4,
1220                         &hba->pdev->saved_config_space[i]);
1221
1222         /* Reset secondary bus. Our controller(MU/ATU) is the only device on
1223            secondary bus. Consult Intel 80331/3 developer's manual for detail */
1224         bus = hba->pdev->bus;
1225         pci_read_config_byte(bus->self, PCI_BRIDGE_CONTROL, &pci_bctl);
1226         pci_bctl |= PCI_BRIDGE_CTL_BUS_RESET;
1227         pci_write_config_byte(bus->self, PCI_BRIDGE_CONTROL, pci_bctl);
1228
1229         /*
1230          * 1 ms may be enough for 8-port controllers. But 16-port controllers
1231          * require more time to finish bus reset. Use 100 ms here for safety
1232          */
1233         msleep(100);
1234         pci_bctl &= ~PCI_BRIDGE_CTL_BUS_RESET;
1235         pci_write_config_byte(bus->self, PCI_BRIDGE_CONTROL, pci_bctl);
1236
1237         for (i = 0; i < MU_HARD_RESET_WAIT; i++) {
1238                 pci_read_config_word(hba->pdev, PCI_COMMAND, &pci_cmd);
1239                 if (pci_cmd != 0xffff && (pci_cmd & PCI_COMMAND_MASTER))
1240                         break;
1241                 msleep(1);
1242         }
1243
1244         ssleep(5);
1245         for (i = 0; i < 16; i++)
1246                 pci_write_config_dword(hba->pdev, i * 4,
1247                         hba->pdev->saved_config_space[i]);
1248 }
1249
1250 static int stex_yos_reset(struct st_hba *hba)
1251 {
1252         void __iomem *base;
1253         unsigned long flags, before;
1254         int ret = 0;
1255
1256         base = hba->mmio_base;
1257         writel(MU_INBOUND_DOORBELL_RESET, base + IDBL);
1258         readl(base + IDBL); /* flush */
1259         before = jiffies;
1260         while (hba->out_req_cnt > 0) {
1261                 if (time_after(jiffies, before + ST_INTERNAL_TIMEOUT * HZ)) {
1262                         printk(KERN_WARNING DRV_NAME
1263                                 "(%s): reset timeout\n", pci_name(hba->pdev));
1264                         ret = -1;
1265                         break;
1266                 }
1267                 msleep(1);
1268         }
1269
1270         spin_lock_irqsave(hba->host->host_lock, flags);
1271         if (ret == -1)
1272                 hba->mu_status = MU_STATE_FAILED;
1273         else
1274                 hba->mu_status = MU_STATE_STARTED;
1275         wake_up_all(&hba->reset_waitq);
1276         spin_unlock_irqrestore(hba->host->host_lock, flags);
1277
1278         return ret;
1279 }
1280
1281 static void stex_ss_reset(struct st_hba *hba)
1282 {
1283         writel(SS_H2I_INT_RESET, hba->mmio_base + YH2I_INT);
1284         readl(hba->mmio_base + YH2I_INT);
1285         ssleep(5);
1286 }
1287
1288 static int stex_do_reset(struct st_hba *hba)
1289 {
1290         unsigned long flags;
1291         unsigned int mu_status = MU_STATE_RESETTING;
1292
1293         spin_lock_irqsave(hba->host->host_lock, flags);
1294         if (hba->mu_status == MU_STATE_STARTING) {
1295                 spin_unlock_irqrestore(hba->host->host_lock, flags);
1296                 printk(KERN_INFO DRV_NAME "(%s): request reset during init\n",
1297                         pci_name(hba->pdev));
1298                 return 0;
1299         }
1300         while (hba->mu_status == MU_STATE_RESETTING) {
1301                 spin_unlock_irqrestore(hba->host->host_lock, flags);
1302                 wait_event_timeout(hba->reset_waitq,
1303                                    hba->mu_status != MU_STATE_RESETTING,
1304                                    MU_MAX_DELAY * HZ);
1305                 spin_lock_irqsave(hba->host->host_lock, flags);
1306                 mu_status = hba->mu_status;
1307         }
1308
1309         if (mu_status != MU_STATE_RESETTING) {
1310                 spin_unlock_irqrestore(hba->host->host_lock, flags);
1311                 return (mu_status == MU_STATE_STARTED) ? 0 : -1;
1312         }
1313
1314         hba->mu_status = MU_STATE_RESETTING;
1315         spin_unlock_irqrestore(hba->host->host_lock, flags);
1316
1317         if (hba->cardtype == st_yosemite)
1318                 return stex_yos_reset(hba);
1319
1320         if (hba->cardtype == st_shasta)
1321                 stex_hard_reset(hba);
1322         else if (hba->cardtype == st_yel)
1323                 stex_ss_reset(hba);
1324
1325
1326         return_abnormal_state(hba, DID_RESET);
1327
1328         if (stex_handshake(hba) == 0)
1329                 return 0;
1330
1331         printk(KERN_WARNING DRV_NAME "(%s): resetting: handshake failed\n",
1332                 pci_name(hba->pdev));
1333         return -1;
1334 }
1335
1336 static int stex_reset(struct scsi_cmnd *cmd)
1337 {
1338         struct st_hba *hba;
1339
1340         hba = (struct st_hba *) &cmd->device->host->hostdata[0];
1341
1342         shost_printk(KERN_INFO, cmd->device->host,
1343                      "resetting host\n");
1344
1345         return stex_do_reset(hba) ? FAILED : SUCCESS;
1346 }
1347
1348 static void stex_reset_work(struct work_struct *work)
1349 {
1350         struct st_hba *hba = container_of(work, struct st_hba, reset_work);
1351
1352         stex_do_reset(hba);
1353 }
1354
1355 static int stex_biosparam(struct scsi_device *sdev,
1356         struct block_device *bdev, sector_t capacity, int geom[])
1357 {
1358         int heads = 255, sectors = 63;
1359
1360         if (capacity < 0x200000) {
1361                 heads = 64;
1362                 sectors = 32;
1363         }
1364
1365         sector_div(capacity, heads * sectors);
1366
1367         geom[0] = heads;
1368         geom[1] = sectors;
1369         geom[2] = capacity;
1370
1371         return 0;
1372 }
1373
1374 static struct scsi_host_template driver_template = {
1375         .module                         = THIS_MODULE,
1376         .name                           = DRV_NAME,
1377         .proc_name                      = DRV_NAME,
1378         .bios_param                     = stex_biosparam,
1379         .queuecommand                   = stex_queuecommand,
1380         .slave_configure                = stex_slave_config,
1381         .eh_abort_handler               = stex_abort,
1382         .eh_host_reset_handler          = stex_reset,
1383         .this_id                        = -1,
1384 };
1385
1386 static struct pci_device_id stex_pci_tbl[] = {
1387         /* st_shasta */
1388         { 0x105a, 0x8350, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1389                 st_shasta }, /* SuperTrak EX8350/8300/16350/16300 */
1390         { 0x105a, 0xc350, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1391                 st_shasta }, /* SuperTrak EX12350 */
1392         { 0x105a, 0x4302, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1393                 st_shasta }, /* SuperTrak EX4350 */
1394         { 0x105a, 0xe350, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1395                 st_shasta }, /* SuperTrak EX24350 */
1396
1397         /* st_vsc */
1398         { 0x105a, 0x7250, PCI_ANY_ID, PCI_ANY_ID, 0, 0, st_vsc },
1399
1400         /* st_yosemite */
1401         { 0x105a, 0x8650, 0x105a, PCI_ANY_ID, 0, 0, st_yosemite },
1402
1403         /* st_seq */
1404         { 0x105a, 0x3360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, st_seq },
1405
1406         /* st_yel */
1407         { 0x105a, 0x8650, 0x1033, PCI_ANY_ID, 0, 0, st_yel },
1408         { 0x105a, 0x8760, PCI_ANY_ID, PCI_ANY_ID, 0, 0, st_yel },
1409         { }     /* terminate list */
1410 };
1411
1412 static struct st_card_info stex_card_info[] = {
1413         /* st_shasta */
1414         {
1415                 .max_id         = 17,
1416                 .max_lun        = 8,
1417                 .max_channel    = 0,
1418                 .rq_count       = 32,
1419                 .rq_size        = 1048,
1420                 .sts_count      = 32,
1421                 .alloc_rq       = stex_alloc_req,
1422                 .map_sg         = stex_map_sg,
1423                 .send           = stex_send_cmd,
1424         },
1425
1426         /* st_vsc */
1427         {
1428                 .max_id         = 129,
1429                 .max_lun        = 1,
1430                 .max_channel    = 0,
1431                 .rq_count       = 32,
1432                 .rq_size        = 1048,
1433                 .sts_count      = 32,
1434                 .alloc_rq       = stex_alloc_req,
1435                 .map_sg         = stex_map_sg,
1436                 .send           = stex_send_cmd,
1437         },
1438
1439         /* st_yosemite */
1440         {
1441                 .max_id         = 2,
1442                 .max_lun        = 256,
1443                 .max_channel    = 0,
1444                 .rq_count       = 256,
1445                 .rq_size        = 1048,
1446                 .sts_count      = 256,
1447                 .alloc_rq       = stex_alloc_req,
1448                 .map_sg         = stex_map_sg,
1449                 .send           = stex_send_cmd,
1450         },
1451
1452         /* st_seq */
1453         {
1454                 .max_id         = 129,
1455                 .max_lun        = 1,
1456                 .max_channel    = 0,
1457                 .rq_count       = 32,
1458                 .rq_size        = 1048,
1459                 .sts_count      = 32,
1460                 .alloc_rq       = stex_alloc_req,
1461                 .map_sg         = stex_map_sg,
1462                 .send           = stex_send_cmd,
1463         },
1464
1465         /* st_yel */
1466         {
1467                 .max_id         = 129,
1468                 .max_lun        = 256,
1469                 .max_channel    = 3,
1470                 .rq_count       = 801,
1471                 .rq_size        = 512,
1472                 .sts_count      = 801,
1473                 .alloc_rq       = stex_ss_alloc_req,
1474                 .map_sg         = stex_ss_map_sg,
1475                 .send           = stex_ss_send_cmd,
1476         },
1477 };
1478
1479 static int stex_set_dma_mask(struct pci_dev * pdev)
1480 {
1481         int ret;
1482
1483         if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))
1484                 && !pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)))
1485                 return 0;
1486         ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
1487         if (!ret)
1488                 ret = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
1489         return ret;
1490 }
1491
1492 static int stex_request_irq(struct st_hba *hba)
1493 {
1494         struct pci_dev *pdev = hba->pdev;
1495         int status;
1496
1497         if (msi) {
1498                 status = pci_enable_msi(pdev);
1499                 if (status != 0)
1500                         printk(KERN_ERR DRV_NAME
1501                                 "(%s): error %d setting up MSI\n",
1502                                 pci_name(pdev), status);
1503                 else
1504                         hba->msi_enabled = 1;
1505         } else
1506                 hba->msi_enabled = 0;
1507
1508         status = request_irq(pdev->irq, hba->cardtype == st_yel ?
1509                 stex_ss_intr : stex_intr, IRQF_SHARED, DRV_NAME, hba);
1510
1511         if (status != 0) {
1512                 if (hba->msi_enabled)
1513                         pci_disable_msi(pdev);
1514         }
1515         return status;
1516 }
1517
1518 static void stex_free_irq(struct st_hba *hba)
1519 {
1520         struct pci_dev *pdev = hba->pdev;
1521
1522         free_irq(pdev->irq, hba);
1523         if (hba->msi_enabled)
1524                 pci_disable_msi(pdev);
1525 }
1526
1527 static int stex_probe(struct pci_dev *pdev, const struct pci_device_id *id)
1528 {
1529         struct st_hba *hba;
1530         struct Scsi_Host *host;
1531         const struct st_card_info *ci = NULL;
1532         u32 sts_offset, cp_offset, scratch_offset;
1533         int err;
1534
1535         err = pci_enable_device(pdev);
1536         if (err)
1537                 return err;
1538
1539         pci_set_master(pdev);
1540
1541         host = scsi_host_alloc(&driver_template, sizeof(struct st_hba));
1542
1543         if (!host) {
1544                 printk(KERN_ERR DRV_NAME "(%s): scsi_host_alloc failed\n",
1545                         pci_name(pdev));
1546                 err = -ENOMEM;
1547                 goto out_disable;
1548         }
1549
1550         hba = (struct st_hba *)host->hostdata;
1551         memset(hba, 0, sizeof(struct st_hba));
1552
1553         err = pci_request_regions(pdev, DRV_NAME);
1554         if (err < 0) {
1555                 printk(KERN_ERR DRV_NAME "(%s): request regions failed\n",
1556                         pci_name(pdev));
1557                 goto out_scsi_host_put;
1558         }
1559
1560         hba->mmio_base = pci_ioremap_bar(pdev, 0);
1561         if ( !hba->mmio_base) {
1562                 printk(KERN_ERR DRV_NAME "(%s): memory map failed\n",
1563                         pci_name(pdev));
1564                 err = -ENOMEM;
1565                 goto out_release_regions;
1566         }
1567
1568         err = stex_set_dma_mask(pdev);
1569         if (err) {
1570                 printk(KERN_ERR DRV_NAME "(%s): set dma mask failed\n",
1571                         pci_name(pdev));
1572                 goto out_iounmap;
1573         }
1574
1575         hba->cardtype = (unsigned int) id->driver_data;
1576         ci = &stex_card_info[hba->cardtype];
1577         switch (id->subdevice) {
1578         case 0x4221:
1579         case 0x4222:
1580         case 0x4223:
1581         case 0x4224:
1582         case 0x4225:
1583         case 0x4226:
1584         case 0x4227:
1585         case 0x4261:
1586         case 0x4262:
1587         case 0x4263:
1588         case 0x4264:
1589         case 0x4265:
1590                 break;
1591         default:
1592                 if (hba->cardtype == st_yel)
1593                         hba->supports_pm = 1;
1594         }
1595
1596         sts_offset = scratch_offset = (ci->rq_count+1) * ci->rq_size;
1597         if (hba->cardtype == st_yel)
1598                 sts_offset += (ci->sts_count+1) * sizeof(u32);
1599         cp_offset = sts_offset + (ci->sts_count+1) * sizeof(struct status_msg);
1600         hba->dma_size = cp_offset + sizeof(struct st_frame);
1601         if (hba->cardtype == st_seq ||
1602                 (hba->cardtype == st_vsc && (pdev->subsystem_device & 1))) {
1603                 hba->extra_offset = hba->dma_size;
1604                 hba->dma_size += ST_ADDITIONAL_MEM;
1605         }
1606         hba->dma_mem = dma_alloc_coherent(&pdev->dev,
1607                 hba->dma_size, &hba->dma_handle, GFP_KERNEL);
1608         if (!hba->dma_mem) {
1609                 /* Retry minimum coherent mapping for st_seq and st_vsc */
1610                 if (hba->cardtype == st_seq ||
1611                     (hba->cardtype == st_vsc && (pdev->subsystem_device & 1))) {
1612                         printk(KERN_WARNING DRV_NAME
1613                                 "(%s): allocating min buffer for controller\n",
1614                                 pci_name(pdev));
1615                         hba->dma_size = hba->extra_offset
1616                                 + ST_ADDITIONAL_MEM_MIN;
1617                         hba->dma_mem = dma_alloc_coherent(&pdev->dev,
1618                                 hba->dma_size, &hba->dma_handle, GFP_KERNEL);
1619                 }
1620
1621                 if (!hba->dma_mem) {
1622                         err = -ENOMEM;
1623                         printk(KERN_ERR DRV_NAME "(%s): dma mem alloc failed\n",
1624                                 pci_name(pdev));
1625                         goto out_iounmap;
1626                 }
1627         }
1628
1629         hba->ccb = kcalloc(ci->rq_count, sizeof(struct st_ccb), GFP_KERNEL);
1630         if (!hba->ccb) {
1631                 err = -ENOMEM;
1632                 printk(KERN_ERR DRV_NAME "(%s): ccb alloc failed\n",
1633                         pci_name(pdev));
1634                 goto out_pci_free;
1635         }
1636
1637         if (hba->cardtype == st_yel)
1638                 hba->scratch = (__le32 *)(hba->dma_mem + scratch_offset);
1639         hba->status_buffer = (struct status_msg *)(hba->dma_mem + sts_offset);
1640         hba->copy_buffer = hba->dma_mem + cp_offset;
1641         hba->rq_count = ci->rq_count;
1642         hba->rq_size = ci->rq_size;
1643         hba->sts_count = ci->sts_count;
1644         hba->alloc_rq = ci->alloc_rq;
1645         hba->map_sg = ci->map_sg;
1646         hba->send = ci->send;
1647         hba->mu_status = MU_STATE_STARTING;
1648
1649         if (hba->cardtype == st_yel)
1650                 host->sg_tablesize = 38;
1651         else
1652                 host->sg_tablesize = 32;
1653         host->can_queue = ci->rq_count;
1654         host->cmd_per_lun = ci->rq_count;
1655         host->max_id = ci->max_id;
1656         host->max_lun = ci->max_lun;
1657         host->max_channel = ci->max_channel;
1658         host->unique_id = host->host_no;
1659         host->max_cmd_len = STEX_CDB_LENGTH;
1660
1661         hba->host = host;
1662         hba->pdev = pdev;
1663         init_waitqueue_head(&hba->reset_waitq);
1664
1665         snprintf(hba->work_q_name, sizeof(hba->work_q_name),
1666                  "stex_wq_%d", host->host_no);
1667         hba->work_q = create_singlethread_workqueue(hba->work_q_name);
1668         if (!hba->work_q) {
1669                 printk(KERN_ERR DRV_NAME "(%s): create workqueue failed\n",
1670                         pci_name(pdev));
1671                 err = -ENOMEM;
1672                 goto out_ccb_free;
1673         }
1674         INIT_WORK(&hba->reset_work, stex_reset_work);
1675
1676         err = stex_request_irq(hba);
1677         if (err) {
1678                 printk(KERN_ERR DRV_NAME "(%s): request irq failed\n",
1679                         pci_name(pdev));
1680                 goto out_free_wq;
1681         }
1682
1683         err = stex_handshake(hba);
1684         if (err)
1685                 goto out_free_irq;
1686
1687         pci_set_drvdata(pdev, hba);
1688
1689         err = scsi_add_host(host, &pdev->dev);
1690         if (err) {
1691                 printk(KERN_ERR DRV_NAME "(%s): scsi_add_host failed\n",
1692                         pci_name(pdev));
1693                 goto out_free_irq;
1694         }
1695
1696         scsi_scan_host(host);
1697
1698         return 0;
1699
1700 out_free_irq:
1701         stex_free_irq(hba);
1702 out_free_wq:
1703         destroy_workqueue(hba->work_q);
1704 out_ccb_free:
1705         kfree(hba->ccb);
1706 out_pci_free:
1707         dma_free_coherent(&pdev->dev, hba->dma_size,
1708                           hba->dma_mem, hba->dma_handle);
1709 out_iounmap:
1710         iounmap(hba->mmio_base);
1711 out_release_regions:
1712         pci_release_regions(pdev);
1713 out_scsi_host_put:
1714         scsi_host_put(host);
1715 out_disable:
1716         pci_disable_device(pdev);
1717
1718         return err;
1719 }
1720
1721 static void stex_hba_stop(struct st_hba *hba)
1722 {
1723         struct req_msg *req;
1724         struct st_msg_header *msg_h;
1725         unsigned long flags;
1726         unsigned long before;
1727         u16 tag = 0;
1728
1729         spin_lock_irqsave(hba->host->host_lock, flags);
1730         req = hba->alloc_rq(hba);
1731         if (hba->cardtype == st_yel) {
1732                 msg_h = (struct st_msg_header *)req - 1;
1733                 memset(msg_h, 0, hba->rq_size);
1734         } else
1735                 memset(req, 0, hba->rq_size);
1736
1737         if (hba->cardtype == st_yosemite || hba->cardtype == st_yel) {
1738                 req->cdb[0] = MGT_CMD;
1739                 req->cdb[1] = MGT_CMD_SIGNATURE;
1740                 req->cdb[2] = CTLR_CONFIG_CMD;
1741                 req->cdb[3] = CTLR_SHUTDOWN;
1742         } else {
1743                 req->cdb[0] = CONTROLLER_CMD;
1744                 req->cdb[1] = CTLR_POWER_STATE_CHANGE;
1745                 req->cdb[2] = CTLR_POWER_SAVING;
1746         }
1747
1748         hba->ccb[tag].cmd = NULL;
1749         hba->ccb[tag].sg_count = 0;
1750         hba->ccb[tag].sense_bufflen = 0;
1751         hba->ccb[tag].sense_buffer = NULL;
1752         hba->ccb[tag].req_type = PASSTHRU_REQ_TYPE;
1753
1754         hba->send(hba, req, tag);
1755         spin_unlock_irqrestore(hba->host->host_lock, flags);
1756
1757         before = jiffies;
1758         while (hba->ccb[tag].req_type & PASSTHRU_REQ_TYPE) {
1759                 if (time_after(jiffies, before + ST_INTERNAL_TIMEOUT * HZ)) {
1760                         hba->ccb[tag].req_type = 0;
1761                         return;
1762                 }
1763                 msleep(1);
1764         }
1765 }
1766
1767 static void stex_hba_free(struct st_hba *hba)
1768 {
1769         stex_free_irq(hba);
1770
1771         destroy_workqueue(hba->work_q);
1772
1773         iounmap(hba->mmio_base);
1774
1775         pci_release_regions(hba->pdev);
1776
1777         kfree(hba->ccb);
1778
1779         dma_free_coherent(&hba->pdev->dev, hba->dma_size,
1780                           hba->dma_mem, hba->dma_handle);
1781 }
1782
1783 static void stex_remove(struct pci_dev *pdev)
1784 {
1785         struct st_hba *hba = pci_get_drvdata(pdev);
1786
1787         hba->mu_status = MU_STATE_NOCONNECT;
1788         return_abnormal_state(hba, DID_NO_CONNECT);
1789         scsi_remove_host(hba->host);
1790
1791         scsi_block_requests(hba->host);
1792
1793         stex_hba_free(hba);
1794
1795         scsi_host_put(hba->host);
1796
1797         pci_disable_device(pdev);
1798 }
1799
1800 static void stex_shutdown(struct pci_dev *pdev)
1801 {
1802         struct st_hba *hba = pci_get_drvdata(pdev);
1803
1804         stex_hba_stop(hba);
1805 }
1806
1807 MODULE_DEVICE_TABLE(pci, stex_pci_tbl);
1808
1809 static struct pci_driver stex_pci_driver = {
1810         .name           = DRV_NAME,
1811         .id_table       = stex_pci_tbl,
1812         .probe          = stex_probe,
1813         .remove         = stex_remove,
1814         .shutdown       = stex_shutdown,
1815 };
1816
1817 static int __init stex_init(void)
1818 {
1819         printk(KERN_INFO DRV_NAME
1820                 ": Promise SuperTrak EX Driver version: %s\n",
1821                  ST_DRIVER_VERSION);
1822
1823         return pci_register_driver(&stex_pci_driver);
1824 }
1825
1826 static void __exit stex_exit(void)
1827 {
1828         pci_unregister_driver(&stex_pci_driver);
1829 }
1830
1831 module_init(stex_init);
1832 module_exit(stex_exit);