2 * Sun3 SCSI stuff by Erik Verbruggen (erik@bigmama.xtdnet.nl)
4 * Sun3 DMA additions by Sam Creasey (sammy@sammy.net)
6 * Adapted from mac_scsinew.h:
9 * Cumana Generic NCR5380 driver defines
11 * Copyright 1993, Drew Eckhardt
13 * (Unix and Linux consulting and custom programming)
23 #define SUN3SCSI_PUBLIC_RELEASE 1
26 * Int: level 2 autovector
27 * IO: type 1, base 0x00140000, 5 bits phys space: A<4..0>
29 #define IRQ_SUN3_SCSI 2
30 #define IOBASE_SUN3_SCSI 0x00140000
32 #define IOBASE_SUN3_VMESCSI 0xff200000
43 #define SG_TABLESIZE SG_NONE
50 #ifndef USE_TAGGED_QUEUING
51 #define USE_TAGGED_QUEUING 1
54 #include <scsi/scsicam.h>
57 #define SUN3_SCSI_NAME "Sun3 NCR5380 VME SCSI"
59 #define SUN3_SCSI_NAME "Sun3 NCR5380 SCSI"
62 #define NCR5380_implementation_fields /* none */
64 #define NCR5380_local_declare() \
65 struct Scsi_Host *_instance
67 #define NCR5380_setup(instance) \
70 #define NCR5380_read(reg) sun3scsi_read(reg)
71 #define NCR5380_write(reg, value) sun3scsi_write(reg, value)
73 #define NCR5380_queue_command sun3scsi_queue_command
74 #define NCR5380_bus_reset sun3scsi_bus_reset
75 #define NCR5380_abort sun3scsi_abort
76 #define NCR5380_show_info sun3scsi_show_info
77 #define NCR5380_info sun3scsi_info
78 #define NCR5380_dma_xfer_len(i, cmd, phase) \
79 sun3scsi_dma_xfer_len(cmd->SCp.this_residual,cmd,((phase) & SR_IO) ? 0 : 1)
81 #define NCR5380_dma_write_setup(instance, data, count) sun3scsi_dma_setup(data, count, 1)
82 #define NCR5380_dma_read_setup(instance, data, count) sun3scsi_dma_setup(data, count, 0)
83 #define NCR5380_dma_residual sun3scsi_dma_residual
85 /* additional registers - mainly DMA control regs */
86 /* these start at regbase + 8 -- directly after the NCR regs */
87 struct sun3_dma_regs {
88 unsigned short dma_addr_hi; /* vme only */
89 unsigned short dma_addr_lo; /* vme only */
90 unsigned short dma_count_hi; /* vme only */
91 unsigned short dma_count_lo; /* vme only */
92 unsigned short udc_data; /* udc dma data reg (obio only) */
93 unsigned short udc_addr; /* uda dma addr reg (obio only) */
94 unsigned short fifo_data; /* fifo data reg, holds extra byte on
96 unsigned short fifo_count;
97 unsigned short csr; /* control/status reg */
98 unsigned short bpack_hi; /* vme only */
99 unsigned short bpack_lo; /* vme only */
100 unsigned short ivect; /* vme only */
101 unsigned short fifo_count_hi; /* vme only */
104 /* ucd chip specific regs - live in dvma space */
105 struct sun3_udc_regs {
106 unsigned short rsel; /* select regs to load */
107 unsigned short addr_hi; /* high word of addr */
108 unsigned short addr_lo; /* low word */
109 unsigned short count; /* words to be xfer'd */
110 unsigned short mode_hi; /* high word of channel mode */
111 unsigned short mode_lo; /* low word of channel mode */
114 /* addresses of the udc registers */
115 #define UDC_MODE 0x38
116 #define UDC_CSR 0x2e /* command/status */
117 #define UDC_CHN_HI 0x26 /* chain high word */
118 #define UDC_CHN_LO 0x22 /* chain lo word */
119 #define UDC_CURA_HI 0x1a /* cur reg A high */
120 #define UDC_CURA_LO 0x0a /* cur reg A low */
121 #define UDC_CURB_HI 0x12 /* cur reg B high */
122 #define UDC_CURB_LO 0x02 /* cur reg B low */
123 #define UDC_MODE_HI 0x56 /* mode reg high */
124 #define UDC_MODE_LO 0x52 /* mode reg low */
125 #define UDC_COUNT 0x32 /* words to xfer */
127 /* some udc commands */
129 #define UDC_CHN_START 0xa0 /* start chain */
130 #define UDC_INT_ENABLE 0x32 /* channel 1 int on */
133 #define UDC_MODE_HIWORD 0x40
134 #define UDC_MODE_LSEND 0xc2
135 #define UDC_MODE_LRECV 0xd2
137 /* udc reg selections */
138 #define UDC_RSEL_SEND 0x282
139 #define UDC_RSEL_RECV 0x182
141 /* bits in csr reg */
142 #define CSR_DMA_ACTIVE 0x8000
143 #define CSR_DMA_CONFLICT 0x4000
144 #define CSR_DMA_BUSERR 0x2000
146 #define CSR_FIFO_EMPTY 0x400 /* fifo flushed? */
147 #define CSR_SDB_INT 0x200 /* sbc interrupt pending */
148 #define CSR_DMA_INT 0x100 /* dma interrupt pending */
150 #define CSR_LEFT 0xc0
151 #define CSR_LEFT_3 0xc0
152 #define CSR_LEFT_2 0x80
153 #define CSR_LEFT_1 0x40
154 #define CSR_PACK_ENABLE 0x20
156 #define CSR_DMA_ENABLE 0x10
158 #define CSR_SEND 0x8 /* 1 = send 0 = recv */
159 #define CSR_FIFO 0x2 /* reset fifo */
160 #define CSR_INTR 0x4 /* interrupt enable */
163 #define VME_DATA24 0x3d00
165 #endif /* SUN3_SCSI_H */