2 * linux/drivers/serial/imx.c
4 * Driver for Motorola IMX serial ports
6 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
8 * Author: Sascha Hauer <sascha@saschahauer.de>
9 * Copyright (C) 2004 Pengutronix
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
25 * [29-Mar-2005] Mike Lee
26 * Added hardware handshake
29 #if defined(CONFIG_SERIAL_IMX_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
33 #include <linux/module.h>
34 #include <linux/ioport.h>
35 #include <linux/init.h>
36 #include <linux/console.h>
37 #include <linux/sysrq.h>
38 #include <linux/platform_device.h>
39 #include <linux/tty.h>
40 #include <linux/tty_flip.h>
41 #include <linux/serial_core.h>
42 #include <linux/serial.h>
46 #include <asm/hardware.h>
47 #include <asm/arch/imx-uart.h>
49 /* Register definitions */
50 #define URXD0 0x0 /* Receiver Register */
51 #define URTX0 0x40 /* Transmitter Register */
52 #define UCR1 0x80 /* Control Register 1 */
53 #define UCR2 0x84 /* Control Register 2 */
54 #define UCR3 0x88 /* Control Register 3 */
55 #define UCR4 0x8c /* Control Register 4 */
56 #define UFCR 0x90 /* FIFO Control Register */
57 #define USR1 0x94 /* Status Register 1 */
58 #define USR2 0x98 /* Status Register 2 */
59 #define UESC 0x9c /* Escape Character Register */
60 #define UTIM 0xa0 /* Escape Timer Register */
61 #define UBIR 0xa4 /* BRM Incremental Register */
62 #define UBMR 0xa8 /* BRM Modulator Register */
63 #define UBRC 0xac /* Baud Rate Count Register */
64 #define BIPR1 0xb0 /* Incremental Preset Register 1 */
65 #define BIPR2 0xb4 /* Incremental Preset Register 2 */
66 #define BIPR3 0xb8 /* Incremental Preset Register 3 */
67 #define BIPR4 0xbc /* Incremental Preset Register 4 */
68 #define BMPR1 0xc0 /* BRM Modulator Register 1 */
69 #define BMPR2 0xc4 /* BRM Modulator Register 2 */
70 #define BMPR3 0xc8 /* BRM Modulator Register 3 */
71 #define BMPR4 0xcc /* BRM Modulator Register 4 */
72 #define UTS 0xd0 /* UART Test Register */
74 /* UART Control Register Bit Fields.*/
75 #define URXD_CHARRDY (1<<15)
76 #define URXD_ERR (1<<14)
77 #define URXD_OVRRUN (1<<13)
78 #define URXD_FRMERR (1<<12)
79 #define URXD_BRK (1<<11)
80 #define URXD_PRERR (1<<10)
81 #define UCR1_ADEN (1<<15) /* Auto dectect interrupt */
82 #define UCR1_ADBR (1<<14) /* Auto detect baud rate */
83 #define UCR1_TRDYEN (1<<13) /* Transmitter ready interrupt enable */
84 #define UCR1_IDEN (1<<12) /* Idle condition interrupt */
85 #define UCR1_RRDYEN (1<<9) /* Recv ready interrupt enable */
86 #define UCR1_RDMAEN (1<<8) /* Recv ready DMA enable */
87 #define UCR1_IREN (1<<7) /* Infrared interface enable */
88 #define UCR1_TXMPTYEN (1<<6) /* Transimitter empty interrupt enable */
89 #define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */
90 #define UCR1_SNDBRK (1<<4) /* Send break */
91 #define UCR1_TDMAEN (1<<3) /* Transmitter ready DMA enable */
92 #define UCR1_UARTCLKEN (1<<2) /* UART clock enabled */
93 #define UCR1_DOZE (1<<1) /* Doze */
94 #define UCR1_UARTEN (1<<0) /* UART enabled */
95 #define UCR2_ESCI (1<<15) /* Escape seq interrupt enable */
96 #define UCR2_IRTS (1<<14) /* Ignore RTS pin */
97 #define UCR2_CTSC (1<<13) /* CTS pin control */
98 #define UCR2_CTS (1<<12) /* Clear to send */
99 #define UCR2_ESCEN (1<<11) /* Escape enable */
100 #define UCR2_PREN (1<<8) /* Parity enable */
101 #define UCR2_PROE (1<<7) /* Parity odd/even */
102 #define UCR2_STPB (1<<6) /* Stop */
103 #define UCR2_WS (1<<5) /* Word size */
104 #define UCR2_RTSEN (1<<4) /* Request to send interrupt enable */
105 #define UCR2_TXEN (1<<2) /* Transmitter enabled */
106 #define UCR2_RXEN (1<<1) /* Receiver enabled */
107 #define UCR2_SRST (1<<0) /* SW reset */
108 #define UCR3_DTREN (1<<13) /* DTR interrupt enable */
109 #define UCR3_PARERREN (1<<12) /* Parity enable */
110 #define UCR3_FRAERREN (1<<11) /* Frame error interrupt enable */
111 #define UCR3_DSR (1<<10) /* Data set ready */
112 #define UCR3_DCD (1<<9) /* Data carrier detect */
113 #define UCR3_RI (1<<8) /* Ring indicator */
114 #define UCR3_TIMEOUTEN (1<<7) /* Timeout interrupt enable */
115 #define UCR3_RXDSEN (1<<6) /* Receive status interrupt enable */
116 #define UCR3_AIRINTEN (1<<5) /* Async IR wake interrupt enable */
117 #define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */
118 #define UCR3_REF25 (1<<3) /* Ref freq 25 MHz */
119 #define UCR3_REF30 (1<<2) /* Ref Freq 30 MHz */
120 #define UCR3_INVT (1<<1) /* Inverted Infrared transmission */
121 #define UCR3_BPEN (1<<0) /* Preset registers enable */
122 #define UCR4_CTSTL_32 (32<<10) /* CTS trigger level (32 chars) */
123 #define UCR4_INVR (1<<9) /* Inverted infrared reception */
124 #define UCR4_ENIRI (1<<8) /* Serial infrared interrupt enable */
125 #define UCR4_WKEN (1<<7) /* Wake interrupt enable */
126 #define UCR4_REF16 (1<<6) /* Ref freq 16 MHz */
127 #define UCR4_IRSC (1<<5) /* IR special case */
128 #define UCR4_TCEN (1<<3) /* Transmit complete interrupt enable */
129 #define UCR4_BKEN (1<<2) /* Break condition interrupt enable */
130 #define UCR4_OREN (1<<1) /* Receiver overrun interrupt enable */
131 #define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */
132 #define UFCR_RXTL_SHF 0 /* Receiver trigger level shift */
133 #define UFCR_RFDIV (7<<7) /* Reference freq divider mask */
134 #define UFCR_TXTL_SHF 10 /* Transmitter trigger level shift */
135 #define USR1_PARITYERR (1<<15) /* Parity error interrupt flag */
136 #define USR1_RTSS (1<<14) /* RTS pin status */
137 #define USR1_TRDY (1<<13) /* Transmitter ready interrupt/dma flag */
138 #define USR1_RTSD (1<<12) /* RTS delta */
139 #define USR1_ESCF (1<<11) /* Escape seq interrupt flag */
140 #define USR1_FRAMERR (1<<10) /* Frame error interrupt flag */
141 #define USR1_RRDY (1<<9) /* Receiver ready interrupt/dma flag */
142 #define USR1_TIMEOUT (1<<7) /* Receive timeout interrupt status */
143 #define USR1_RXDS (1<<6) /* Receiver idle interrupt flag */
144 #define USR1_AIRINT (1<<5) /* Async IR wake interrupt flag */
145 #define USR1_AWAKE (1<<4) /* Aysnc wake interrupt flag */
146 #define USR2_ADET (1<<15) /* Auto baud rate detect complete */
147 #define USR2_TXFE (1<<14) /* Transmit buffer FIFO empty */
148 #define USR2_DTRF (1<<13) /* DTR edge interrupt flag */
149 #define USR2_IDLE (1<<12) /* Idle condition */
150 #define USR2_IRINT (1<<8) /* Serial infrared interrupt flag */
151 #define USR2_WAKE (1<<7) /* Wake */
152 #define USR2_RTSF (1<<4) /* RTS edge interrupt flag */
153 #define USR2_TXDC (1<<3) /* Transmitter complete */
154 #define USR2_BRCD (1<<2) /* Break condition */
155 #define USR2_ORE (1<<1) /* Overrun error */
156 #define USR2_RDR (1<<0) /* Recv data ready */
157 #define UTS_FRCPERR (1<<13) /* Force parity error */
158 #define UTS_LOOP (1<<12) /* Loop tx and rx */
159 #define UTS_TXEMPTY (1<<6) /* TxFIFO empty */
160 #define UTS_RXEMPTY (1<<5) /* RxFIFO empty */
161 #define UTS_TXFULL (1<<4) /* TxFIFO full */
162 #define UTS_RXFULL (1<<3) /* RxFIFO full */
163 #define UTS_SOFTRST (1<<0) /* Software reset */
165 /* We've been assigned a range on the "Low-density serial ports" major */
166 #define SERIAL_IMX_MAJOR 204
167 #define MINOR_START 41
170 * This determines how often we check the modem status signals
171 * for any change. They generally aren't connected to an IRQ
172 * so we have to poll them. We also check immediately before
173 * filling the TX fifo incase CTS has been dropped.
175 #define MCTRL_TIMEOUT (250*HZ/1000)
177 #define DRIVER_NAME "IMX-uart"
180 struct uart_port port;
181 struct timer_list timer;
182 unsigned int old_status;
183 int txirq,rxirq,rtsirq;
188 * Handle any change of modem status signal since we were last called.
190 static void imx_mctrl_check(struct imx_port *sport)
192 unsigned int status, changed;
194 status = sport->port.ops->get_mctrl(&sport->port);
195 changed = status ^ sport->old_status;
200 sport->old_status = status;
202 if (changed & TIOCM_RI)
203 sport->port.icount.rng++;
204 if (changed & TIOCM_DSR)
205 sport->port.icount.dsr++;
206 if (changed & TIOCM_CAR)
207 uart_handle_dcd_change(&sport->port, status & TIOCM_CAR);
208 if (changed & TIOCM_CTS)
209 uart_handle_cts_change(&sport->port, status & TIOCM_CTS);
211 wake_up_interruptible(&sport->port.info->delta_msr_wait);
215 * This is our per-port timeout handler, for checking the
216 * modem status signals.
218 static void imx_timeout(unsigned long data)
220 struct imx_port *sport = (struct imx_port *)data;
223 if (sport->port.info) {
224 spin_lock_irqsave(&sport->port.lock, flags);
225 imx_mctrl_check(sport);
226 spin_unlock_irqrestore(&sport->port.lock, flags);
228 mod_timer(&sport->timer, jiffies + MCTRL_TIMEOUT);
233 * interrupts disabled on entry
235 static void imx_stop_tx(struct uart_port *port)
237 struct imx_port *sport = (struct imx_port *)port;
240 temp = readl(sport->port.membase + UCR1);
241 writel(temp & ~UCR1_TXMPTYEN, sport->port.membase + UCR1);
245 * interrupts disabled on entry
247 static void imx_stop_rx(struct uart_port *port)
249 struct imx_port *sport = (struct imx_port *)port;
252 temp = readl(sport->port.membase + UCR2);
253 writel(temp &~ UCR2_RXEN, sport->port.membase + UCR2);
257 * Set the modem control timer to fire immediately.
259 static void imx_enable_ms(struct uart_port *port)
261 struct imx_port *sport = (struct imx_port *)port;
263 mod_timer(&sport->timer, jiffies);
266 static inline void imx_transmit_buffer(struct imx_port *sport)
268 struct circ_buf *xmit = &sport->port.info->xmit;
270 while (!(readl(sport->port.membase + UTS) & UTS_TXFULL)) {
271 /* send xmit->buf[xmit->tail]
272 * out the port here */
273 writel(xmit->buf[xmit->tail], sport->port.membase + URTX0);
274 xmit->tail = (xmit->tail + 1) &
275 (UART_XMIT_SIZE - 1);
276 sport->port.icount.tx++;
277 if (uart_circ_empty(xmit))
281 if (uart_circ_empty(xmit))
282 imx_stop_tx(&sport->port);
286 * interrupts disabled on entry
288 static void imx_start_tx(struct uart_port *port)
290 struct imx_port *sport = (struct imx_port *)port;
293 temp = readl(sport->port.membase + UCR1);
294 writel(temp | UCR1_TXMPTYEN, sport->port.membase + UCR1);
296 if (readl(sport->port.membase + UTS) & UTS_TXEMPTY)
297 imx_transmit_buffer(sport);
300 static irqreturn_t imx_rtsint(int irq, void *dev_id)
302 struct imx_port *sport = dev_id;
303 unsigned int val = readl(sport->port.membase + USR1) & USR1_RTSS;
306 spin_lock_irqsave(&sport->port.lock, flags);
308 writel(USR1_RTSD, sport->port.membase + USR1);
309 uart_handle_cts_change(&sport->port, !!val);
310 wake_up_interruptible(&sport->port.info->delta_msr_wait);
312 spin_unlock_irqrestore(&sport->port.lock, flags);
316 static irqreturn_t imx_txint(int irq, void *dev_id)
318 struct imx_port *sport = dev_id;
319 struct circ_buf *xmit = &sport->port.info->xmit;
322 spin_lock_irqsave(&sport->port.lock,flags);
323 if (sport->port.x_char)
326 writel(sport->port.x_char, sport->port.membase + URTX0);
330 if (uart_circ_empty(xmit) || uart_tx_stopped(&sport->port)) {
331 imx_stop_tx(&sport->port);
335 imx_transmit_buffer(sport);
337 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
338 uart_write_wakeup(&sport->port);
341 spin_unlock_irqrestore(&sport->port.lock,flags);
345 static irqreturn_t imx_rxint(int irq, void *dev_id)
347 struct imx_port *sport = dev_id;
348 unsigned int rx,flg,ignored = 0;
349 struct tty_struct *tty = sport->port.info->tty;
350 unsigned long flags, temp;
352 spin_lock_irqsave(&sport->port.lock,flags);
354 while (readl(sport->port.membase + USR2) & USR2_RDR) {
356 sport->port.icount.rx++;
358 rx = readl(sport->port.membase + URXD0);
360 temp = readl(sport->port.membase + USR2);
361 if (temp & USR2_BRCD) {
362 writel(temp | USR2_BRCD, sport->port.membase + USR2);
363 if (uart_handle_break(&sport->port))
367 if (uart_handle_sysrq_char
368 (&sport->port, (unsigned char)rx))
371 if (rx & (URXD_PRERR | URXD_OVRRUN | URXD_FRMERR) ) {
373 sport->port.icount.parity++;
374 else if (rx & URXD_FRMERR)
375 sport->port.icount.frame++;
376 if (rx & URXD_OVRRUN)
377 sport->port.icount.overrun++;
379 if (rx & sport->port.ignore_status_mask) {
385 rx &= sport->port.read_status_mask;
389 else if (rx & URXD_FRMERR)
391 if (rx & URXD_OVRRUN)
395 sport->port.sysrq = 0;
399 tty_insert_flip_char(tty, rx, flg);
403 spin_unlock_irqrestore(&sport->port.lock,flags);
404 tty_flip_buffer_push(tty);
409 * Return TIOCSER_TEMT when transmitter is not busy.
411 static unsigned int imx_tx_empty(struct uart_port *port)
413 struct imx_port *sport = (struct imx_port *)port;
415 return (readl(sport->port.membase + USR2) & USR2_TXDC) ? TIOCSER_TEMT : 0;
419 * We have a modem side uart, so the meanings of RTS and CTS are inverted.
421 static unsigned int imx_get_mctrl(struct uart_port *port)
423 struct imx_port *sport = (struct imx_port *)port;
424 unsigned int tmp = TIOCM_DSR | TIOCM_CAR;
426 if (readl(sport->port.membase + USR1) & USR1_RTSS)
429 if (readl(sport->port.membase + UCR2) & UCR2_CTS)
435 static void imx_set_mctrl(struct uart_port *port, unsigned int mctrl)
437 struct imx_port *sport = (struct imx_port *)port;
440 temp = readl(sport->port.membase + UCR2) & ~UCR2_CTS;
442 if (mctrl & TIOCM_RTS)
445 writel(temp, sport->port.membase + UCR2);
449 * Interrupts always disabled.
451 static void imx_break_ctl(struct uart_port *port, int break_state)
453 struct imx_port *sport = (struct imx_port *)port;
454 unsigned long flags, temp;
456 spin_lock_irqsave(&sport->port.lock, flags);
458 temp = readl(sport->port.membase + UCR1) & ~UCR1_SNDBRK;
460 if ( break_state != 0 )
463 writel(temp, sport->port.membase + UCR1);
465 spin_unlock_irqrestore(&sport->port.lock, flags);
468 #define TXTL 2 /* reset default */
469 #define RXTL 1 /* reset default */
471 static int imx_setup_ufcr(struct imx_port *sport, unsigned int mode)
474 unsigned int ufcr_rfdiv;
476 /* set receiver / transmitter trigger level.
477 * RFDIV is set such way to satisfy requested uartclk value
479 val = TXTL << 10 | RXTL;
480 ufcr_rfdiv = (imx_get_perclk1() + sport->port.uartclk / 2) / sport->port.uartclk;
488 ufcr_rfdiv = 6 - ufcr_rfdiv;
490 val |= UFCR_RFDIV & (ufcr_rfdiv << 7);
492 writel(val, sport->port.membase + UFCR);
497 static int imx_startup(struct uart_port *port)
499 struct imx_port *sport = (struct imx_port *)port;
501 unsigned long flags, temp;
503 imx_setup_ufcr(sport, 0);
505 /* disable the DREN bit (Data Ready interrupt enable) before
508 temp = readl(sport->port.membase + UCR4);
509 writel(temp & ~UCR4_DREN, sport->port.membase + UCR4);
514 retval = request_irq(sport->rxirq, imx_rxint, 0,
516 if (retval) goto error_out1;
518 retval = request_irq(sport->txirq, imx_txint, 0,
520 if (retval) goto error_out2;
522 retval = request_irq(sport->rtsirq, imx_rtsint,
523 (sport->rtsirq < IMX_IRQS) ? 0 :
524 IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING,
526 if (retval) goto error_out3;
529 * Finally, clear and enable interrupts
531 writel(USR1_RTSD, sport->port.membase + USR1);
533 temp = readl(sport->port.membase + UCR1);
534 temp |= UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN;
535 writel(temp, sport->port.membase + UCR1);
537 temp = readl(sport->port.membase + UCR2);
538 temp |= (UCR2_RXEN | UCR2_TXEN);
539 writel(temp, sport->port.membase + UCR2);
542 * Enable modem status interrupts
544 spin_lock_irqsave(&sport->port.lock,flags);
545 imx_enable_ms(&sport->port);
546 spin_unlock_irqrestore(&sport->port.lock,flags);
551 free_irq(sport->txirq, sport);
553 free_irq(sport->rxirq, sport);
558 static void imx_shutdown(struct uart_port *port)
560 struct imx_port *sport = (struct imx_port *)port;
566 del_timer_sync(&sport->timer);
569 * Free the interrupts
571 free_irq(sport->rtsirq, sport);
572 free_irq(sport->txirq, sport);
573 free_irq(sport->rxirq, sport);
576 * Disable all interrupts, port and break condition.
579 temp = readl(sport->port.membase + UCR1);
580 temp &= ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN);
581 writel(temp, sport->port.membase + UCR1);
585 imx_set_termios(struct uart_port *port, struct ktermios *termios,
586 struct ktermios *old)
588 struct imx_port *sport = (struct imx_port *)port;
590 unsigned int ucr2, old_ucr1, old_txrxen, baud, quot;
591 unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8;
592 unsigned int div, num, denom, ufcr;
595 * If we don't support modem control lines, don't allow
599 termios->c_cflag &= ~(HUPCL | CRTSCTS | CMSPAR);
600 termios->c_cflag |= CLOCAL;
604 * We only support CS7 and CS8.
606 while ((termios->c_cflag & CSIZE) != CS7 &&
607 (termios->c_cflag & CSIZE) != CS8) {
608 termios->c_cflag &= ~CSIZE;
609 termios->c_cflag |= old_csize;
613 if ((termios->c_cflag & CSIZE) == CS8)
614 ucr2 = UCR2_WS | UCR2_SRST | UCR2_IRTS;
616 ucr2 = UCR2_SRST | UCR2_IRTS;
618 if (termios->c_cflag & CRTSCTS) {
619 if( sport->have_rtscts ) {
623 termios->c_cflag &= ~CRTSCTS;
627 if (termios->c_cflag & CSTOPB)
629 if (termios->c_cflag & PARENB) {
631 if (termios->c_cflag & PARODD)
636 * Ask the core to calculate the divisor for us.
638 baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16);
639 quot = uart_get_divisor(port, baud);
641 spin_lock_irqsave(&sport->port.lock, flags);
643 sport->port.read_status_mask = 0;
644 if (termios->c_iflag & INPCK)
645 sport->port.read_status_mask |= (URXD_FRMERR | URXD_PRERR);
646 if (termios->c_iflag & (BRKINT | PARMRK))
647 sport->port.read_status_mask |= URXD_BRK;
650 * Characters to ignore
652 sport->port.ignore_status_mask = 0;
653 if (termios->c_iflag & IGNPAR)
654 sport->port.ignore_status_mask |= URXD_PRERR;
655 if (termios->c_iflag & IGNBRK) {
656 sport->port.ignore_status_mask |= URXD_BRK;
658 * If we're ignoring parity and break indicators,
659 * ignore overruns too (for real raw support).
661 if (termios->c_iflag & IGNPAR)
662 sport->port.ignore_status_mask |= URXD_OVRRUN;
665 del_timer_sync(&sport->timer);
668 * Update the per-port timeout.
670 uart_update_timeout(port, termios->c_cflag, baud);
673 * disable interrupts and drain transmitter
675 old_ucr1 = readl(sport->port.membase + UCR1);
676 writel(old_ucr1 & ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN),
677 sport->port.membase + UCR1);
679 while ( !(readl(sport->port.membase + USR2) & USR2_TXDC))
682 /* then, disable everything */
683 old_txrxen = readl(sport->port.membase + UCR2);
684 writel(old_txrxen & ~( UCR2_TXEN | UCR2_RXEN),
685 sport->port.membase + UCR2);
686 old_txrxen &= (UCR2_TXEN | UCR2_RXEN);
688 div = sport->port.uartclk / (baud * 16);
695 denom = port->uartclk / div / 16;
697 /* shift num and denom right until they fit into 16 bits */
698 while (num > 0x10000 || denom > 0x10000) {
707 writel(num, sport->port.membase + UBIR);
708 writel(denom, sport->port.membase + UBMR);
711 div = 6; /* 6 in RFDIV means divide by 7 */
715 ufcr = readl(sport->port.membase + UFCR);
716 ufcr = (ufcr & (~UFCR_RFDIV)) |
718 writel(ufcr, sport->port.membase + UFCR);
721 writel(sport->port.uartclk / div / 1000, sport->port.membase + ONEMS);
724 writel(old_ucr1, sport->port.membase + UCR1);
726 /* set the parity, stop bits and data size */
727 writel(ucr2 | old_txrxen, sport->port.membase + UCR2);
729 if (UART_ENABLE_MS(&sport->port, termios->c_cflag))
730 imx_enable_ms(&sport->port);
732 spin_unlock_irqrestore(&sport->port.lock, flags);
735 static const char *imx_type(struct uart_port *port)
737 struct imx_port *sport = (struct imx_port *)port;
739 return sport->port.type == PORT_IMX ? "IMX" : NULL;
743 * Release the memory region(s) being used by 'port'.
745 static void imx_release_port(struct uart_port *port)
747 struct platform_device *pdev = to_platform_device(port->dev);
748 struct resource *mmres;
750 mmres = platform_get_resource(pdev, IORESOURCE_MEM, 0);
751 release_mem_region(mmres->start, mmres->end - mmres->start + 1);
755 * Request the memory region(s) being used by 'port'.
757 static int imx_request_port(struct uart_port *port)
759 struct platform_device *pdev = to_platform_device(port->dev);
760 struct resource *mmres;
763 mmres = platform_get_resource(pdev, IORESOURCE_MEM, 0);
767 ret = request_mem_region(mmres->start, mmres->end - mmres->start + 1,
770 return ret ? 0 : -EBUSY;
774 * Configure/autoconfigure the port.
776 static void imx_config_port(struct uart_port *port, int flags)
778 struct imx_port *sport = (struct imx_port *)port;
780 if (flags & UART_CONFIG_TYPE &&
781 imx_request_port(&sport->port) == 0)
782 sport->port.type = PORT_IMX;
786 * Verify the new serial_struct (for TIOCSSERIAL).
787 * The only change we allow are to the flags and type, and
788 * even then only between PORT_IMX and PORT_UNKNOWN
791 imx_verify_port(struct uart_port *port, struct serial_struct *ser)
793 struct imx_port *sport = (struct imx_port *)port;
796 if (ser->type != PORT_UNKNOWN && ser->type != PORT_IMX)
798 if (sport->port.irq != ser->irq)
800 if (ser->io_type != UPIO_MEM)
802 if (sport->port.uartclk / 16 != ser->baud_base)
804 if ((void *)sport->port.mapbase != ser->iomem_base)
806 if (sport->port.iobase != ser->port)
813 static struct uart_ops imx_pops = {
814 .tx_empty = imx_tx_empty,
815 .set_mctrl = imx_set_mctrl,
816 .get_mctrl = imx_get_mctrl,
817 .stop_tx = imx_stop_tx,
818 .start_tx = imx_start_tx,
819 .stop_rx = imx_stop_rx,
820 .enable_ms = imx_enable_ms,
821 .break_ctl = imx_break_ctl,
822 .startup = imx_startup,
823 .shutdown = imx_shutdown,
824 .set_termios = imx_set_termios,
826 .release_port = imx_release_port,
827 .request_port = imx_request_port,
828 .config_port = imx_config_port,
829 .verify_port = imx_verify_port,
832 static struct imx_port imx_ports[] = {
834 .txirq = UART1_MINT_TX,
835 .rxirq = UART1_MINT_RX,
836 .rtsirq = UART1_MINT_RTS,
840 .membase = (void *)IMX_UART1_BASE,
841 .mapbase = 0x00206000,
842 .irq = UART1_MINT_RX,
844 .flags = UPF_BOOT_AUTOCONF,
849 .txirq = UART2_MINT_TX,
850 .rxirq = UART2_MINT_RX,
851 .rtsirq = UART2_MINT_RTS,
855 .membase = (void *)IMX_UART2_BASE,
856 .mapbase = 0x00207000,
857 .irq = UART2_MINT_RX,
859 .flags = UPF_BOOT_AUTOCONF,
867 * Setup the IMX serial ports.
868 * Note also that we support "console=ttySMXx" where "x" is either 0 or 1.
869 * Which serial port this ends up being depends on the machine you're
870 * running this kernel on. I'm not convinced that this is a good idea,
871 * but that's the way it traditionally works.
874 static void __init imx_init_ports(void)
876 static int first = 1;
883 for (i = 0; i < ARRAY_SIZE(imx_ports); i++) {
884 init_timer(&imx_ports[i].timer);
885 imx_ports[i].timer.function = imx_timeout;
886 imx_ports[i].timer.data = (unsigned long)&imx_ports[i];
888 imx_ports[i].port.uartclk = imx_get_perclk1();
892 #ifdef CONFIG_SERIAL_IMX_CONSOLE
893 static void imx_console_putchar(struct uart_port *port, int ch)
895 struct imx_port *sport = (struct imx_port *)port;
897 while (readl(sport->port.membase + UTS) & UTS_TXFULL)
900 writel(ch, sport->port.membase + URTX0);
904 * Interrupts are disabled on entering
907 imx_console_write(struct console *co, const char *s, unsigned int count)
909 struct imx_port *sport = &imx_ports[co->index];
910 unsigned int old_ucr1, old_ucr2;
913 * First, save UCR1/2 and then disable interrupts
915 old_ucr1 = readl(sport->port.membase + UCR1);
916 old_ucr2 = readl(sport->port.membase + UCR2);
918 writel((old_ucr1 | UCR1_UARTCLKEN | UCR1_UARTEN) &
919 ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN),
920 sport->port.membase + UCR1);
922 writel(old_ucr2 | UCR2_TXEN, sport->port.membase + UCR2);
924 uart_console_write(&sport->port, s, count, imx_console_putchar);
927 * Finally, wait for transmitter to become empty
930 while (!(readl(sport->port.membase + USR2) & USR2_TXDC));
932 writel(old_ucr1, sport->port.membase + UCR1);
933 writel(old_ucr2, sport->port.membase + UCR2);
937 * If the port was already initialised (eg, by a boot loader),
938 * try to determine the current setup.
941 imx_console_get_options(struct imx_port *sport, int *baud,
942 int *parity, int *bits)
945 if ( readl(sport->port.membase + UCR1) | UCR1_UARTEN ) {
946 /* ok, the port was enabled */
947 unsigned int ucr2, ubir,ubmr, uartclk;
948 unsigned int baud_raw;
949 unsigned int ucfr_rfdiv;
951 ucr2 = readl(sport->port.membase + UCR2);
954 if (ucr2 & UCR2_PREN) {
955 if (ucr2 & UCR2_PROE)
966 ubir = readl(sport->port.membase + UBIR) & 0xffff;
967 ubmr = readl(sport->port.membase + UBMR) & 0xffff;
969 ucfr_rfdiv = (readl(sport->port.membase + UFCR) & UFCR_RFDIV) >> 7;
973 ucfr_rfdiv = 6 - ucfr_rfdiv;
975 uartclk = imx_get_perclk1();
976 uartclk /= ucfr_rfdiv;
979 * The next code provides exact computation of
980 * baud_raw = round(((uartclk/16) * (ubir + 1)) / (ubmr + 1))
981 * without need of float support or long long division,
982 * which would be required to prevent 32bit arithmetic overflow
984 unsigned int mul = ubir + 1;
985 unsigned int div = 16 * (ubmr + 1);
986 unsigned int rem = uartclk % div;
988 baud_raw = (uartclk / div) * mul;
989 baud_raw += (rem * mul + div / 2) / div;
990 *baud = (baud_raw + 50) / 100 * 100;
993 if(*baud != baud_raw)
994 printk(KERN_INFO "Serial: Console IMX rounded baud rate from %d to %d\n",
1000 imx_console_setup(struct console *co, char *options)
1002 struct imx_port *sport;
1009 * Check whether an invalid uart number has been specified, and
1010 * if so, search for the first available port that does have
1013 if (co->index == -1 || co->index >= ARRAY_SIZE(imx_ports))
1015 sport = &imx_ports[co->index];
1018 uart_parse_options(options, &baud, &parity, &bits, &flow);
1020 imx_console_get_options(sport, &baud, &parity, &bits);
1022 imx_setup_ufcr(sport, 0);
1024 return uart_set_options(&sport->port, co, baud, parity, bits, flow);
1027 static struct uart_driver imx_reg;
1028 static struct console imx_console = {
1030 .write = imx_console_write,
1031 .device = uart_console_device,
1032 .setup = imx_console_setup,
1033 .flags = CON_PRINTBUFFER,
1038 static int __init imx_rs_console_init(void)
1041 register_console(&imx_console);
1044 console_initcall(imx_rs_console_init);
1046 #define IMX_CONSOLE &imx_console
1048 #define IMX_CONSOLE NULL
1051 static struct uart_driver imx_reg = {
1052 .owner = THIS_MODULE,
1053 .driver_name = DRIVER_NAME,
1054 .dev_name = "ttySMX",
1055 .major = SERIAL_IMX_MAJOR,
1056 .minor = MINOR_START,
1057 .nr = ARRAY_SIZE(imx_ports),
1058 .cons = IMX_CONSOLE,
1061 static int serial_imx_suspend(struct platform_device *dev, pm_message_t state)
1063 struct imx_port *sport = platform_get_drvdata(dev);
1066 uart_suspend_port(&imx_reg, &sport->port);
1071 static int serial_imx_resume(struct platform_device *dev)
1073 struct imx_port *sport = platform_get_drvdata(dev);
1076 uart_resume_port(&imx_reg, &sport->port);
1081 static int serial_imx_probe(struct platform_device *dev)
1083 struct imxuart_platform_data *pdata;
1085 imx_ports[dev->id].port.dev = &dev->dev;
1087 pdata = (struct imxuart_platform_data *)dev->dev.platform_data;
1088 if(pdata && (pdata->flags & IMXUART_HAVE_RTSCTS))
1089 imx_ports[dev->id].have_rtscts = 1;
1091 uart_add_one_port(&imx_reg, &imx_ports[dev->id].port);
1092 platform_set_drvdata(dev, &imx_ports[dev->id]);
1096 static int serial_imx_remove(struct platform_device *dev)
1098 struct imx_port *sport = platform_get_drvdata(dev);
1100 platform_set_drvdata(dev, NULL);
1103 uart_remove_one_port(&imx_reg, &sport->port);
1108 static struct platform_driver serial_imx_driver = {
1109 .probe = serial_imx_probe,
1110 .remove = serial_imx_remove,
1112 .suspend = serial_imx_suspend,
1113 .resume = serial_imx_resume,
1116 .owner = THIS_MODULE,
1120 static int __init imx_serial_init(void)
1124 printk(KERN_INFO "Serial: IMX driver\n");
1128 ret = uart_register_driver(&imx_reg);
1132 ret = platform_driver_register(&serial_imx_driver);
1134 uart_unregister_driver(&imx_reg);
1139 static void __exit imx_serial_exit(void)
1141 platform_driver_unregister(&serial_imx_driver);
1142 uart_unregister_driver(&imx_reg);
1145 module_init(imx_serial_init);
1146 module_exit(imx_serial_exit);
1148 MODULE_AUTHOR("Sascha Hauer");
1149 MODULE_DESCRIPTION("IMX generic serial port driver");
1150 MODULE_LICENSE("GPL");
1151 MODULE_ALIAS("platform:imx-uart");