2 * Shared interrupt handling code for IPR and INTC2 types of IRQs.
4 * Copyright (C) 2007, 2008 Magnus Damm
5 * Copyright (C) 2009, 2010 Paul Mundt
7 * Based on intc2.c and ipr.c
9 * Copyright (C) 1999 Niibe Yutaka & Takeshi Yaegashi
10 * Copyright (C) 2000 Kazumoto Kojima
11 * Copyright (C) 2001 David J. Mckay (david.mckay@st.com)
12 * Copyright (C) 2003 Takashi Kusuda <kusuda-takashi@hitachi-ul.co.jp>
13 * Copyright (C) 2005, 2006 Paul Mundt
15 * This file is subject to the terms and conditions of the GNU General Public
16 * License. See the file "COPYING" in the main directory of this archive
19 #include <linux/init.h>
20 #include <linux/irq.h>
21 #include <linux/module.h>
23 #include <linux/interrupt.h>
24 #include <linux/sh_intc.h>
25 #include <linux/sysdev.h>
26 #include <linux/list.h>
27 #include <linux/topology.h>
28 #include <linux/bitmap.h>
29 #include <linux/cpumask.h>
31 #define _INTC_MK(fn, mode, addr_e, addr_d, width, shift) \
32 ((shift) | ((width) << 5) | ((fn) << 9) | ((mode) << 13) | \
33 ((addr_e) << 16) | ((addr_d << 24)))
35 #define _INTC_SHIFT(h) (h & 0x1f)
36 #define _INTC_WIDTH(h) ((h >> 5) & 0xf)
37 #define _INTC_FN(h) ((h >> 9) & 0xf)
38 #define _INTC_MODE(h) ((h >> 13) & 0x7)
39 #define _INTC_ADDR_E(h) ((h >> 16) & 0xff)
40 #define _INTC_ADDR_D(h) ((h >> 24) & 0xff)
42 struct intc_handle_int {
53 struct intc_desc_int {
54 struct list_head list;
55 struct sys_device sysdev;
62 struct intc_handle_int *prio;
64 struct intc_handle_int *sense;
65 unsigned int nr_sense;
66 struct intc_window *window;
67 unsigned int nr_windows;
71 static LIST_HEAD(intc_list);
74 * The intc_irq_map provides a global map of bound IRQ vectors for a
75 * given platform. Allocation of IRQs are either static through the CPU
76 * vector map, or dynamic in the case of board mux vectors or MSI.
78 * As this is a central point for all IRQ controllers on the system,
79 * each of the available sources are mapped out here. This combined with
80 * sparseirq makes it quite trivial to keep the vector map tightly packed
81 * when dynamically creating IRQs, as well as tying in to otherwise
82 * unused irq_desc positions in the sparse array.
84 static DECLARE_BITMAP(intc_irq_map, NR_IRQS);
85 static DEFINE_SPINLOCK(vector_lock);
88 #define IS_SMP(x) x.smp
89 #define INTC_REG(d, x, c) (d->reg[(x)] + ((d->smp[(x)] & 0xff) * c))
90 #define SMP_NR(d, x) ((d->smp[(x)] >> 8) ? (d->smp[(x)] >> 8) : 1)
93 #define INTC_REG(d, x, c) (d->reg[(x)])
94 #define SMP_NR(d, x) 1
97 static unsigned int intc_prio_level[NR_IRQS]; /* for now */
98 static unsigned long ack_handle[NR_IRQS];
100 static inline struct intc_desc_int *get_intc_desc(unsigned int irq)
102 struct irq_chip *chip = get_irq_chip(irq);
103 return container_of(chip, struct intc_desc_int, chip);
106 static inline unsigned int set_field(unsigned int value,
107 unsigned int field_value,
110 unsigned int width = _INTC_WIDTH(handle);
111 unsigned int shift = _INTC_SHIFT(handle);
113 value &= ~(((1 << width) - 1) << shift);
114 value |= field_value << shift;
118 static void write_8(unsigned long addr, unsigned long h, unsigned long data)
120 __raw_writeb(set_field(0, data, h), addr);
121 (void)__raw_readb(addr); /* Defeat write posting */
124 static void write_16(unsigned long addr, unsigned long h, unsigned long data)
126 __raw_writew(set_field(0, data, h), addr);
127 (void)__raw_readw(addr); /* Defeat write posting */
130 static void write_32(unsigned long addr, unsigned long h, unsigned long data)
132 __raw_writel(set_field(0, data, h), addr);
133 (void)__raw_readl(addr); /* Defeat write posting */
136 static void modify_8(unsigned long addr, unsigned long h, unsigned long data)
139 local_irq_save(flags);
140 __raw_writeb(set_field(__raw_readb(addr), data, h), addr);
141 (void)__raw_readb(addr); /* Defeat write posting */
142 local_irq_restore(flags);
145 static void modify_16(unsigned long addr, unsigned long h, unsigned long data)
148 local_irq_save(flags);
149 __raw_writew(set_field(__raw_readw(addr), data, h), addr);
150 (void)__raw_readw(addr); /* Defeat write posting */
151 local_irq_restore(flags);
154 static void modify_32(unsigned long addr, unsigned long h, unsigned long data)
157 local_irq_save(flags);
158 __raw_writel(set_field(__raw_readl(addr), data, h), addr);
159 (void)__raw_readl(addr); /* Defeat write posting */
160 local_irq_restore(flags);
163 enum { REG_FN_ERR = 0, REG_FN_WRITE_BASE = 1, REG_FN_MODIFY_BASE = 5 };
165 static void (*intc_reg_fns[])(unsigned long addr,
167 unsigned long data) = {
168 [REG_FN_WRITE_BASE + 0] = write_8,
169 [REG_FN_WRITE_BASE + 1] = write_16,
170 [REG_FN_WRITE_BASE + 3] = write_32,
171 [REG_FN_MODIFY_BASE + 0] = modify_8,
172 [REG_FN_MODIFY_BASE + 1] = modify_16,
173 [REG_FN_MODIFY_BASE + 3] = modify_32,
176 enum { MODE_ENABLE_REG = 0, /* Bit(s) set -> interrupt enabled */
177 MODE_MASK_REG, /* Bit(s) set -> interrupt disabled */
178 MODE_DUAL_REG, /* Two registers, set bit to enable / disable */
179 MODE_PRIO_REG, /* Priority value written to enable interrupt */
180 MODE_PCLR_REG, /* Above plus all bits set to disable interrupt */
183 static void intc_mode_field(unsigned long addr,
184 unsigned long handle,
185 void (*fn)(unsigned long,
190 fn(addr, handle, ((1 << _INTC_WIDTH(handle)) - 1));
193 static void intc_mode_zero(unsigned long addr,
194 unsigned long handle,
195 void (*fn)(unsigned long,
203 static void intc_mode_prio(unsigned long addr,
204 unsigned long handle,
205 void (*fn)(unsigned long,
210 fn(addr, handle, intc_prio_level[irq]);
213 static void (*intc_enable_fns[])(unsigned long addr,
214 unsigned long handle,
215 void (*fn)(unsigned long,
218 unsigned int irq) = {
219 [MODE_ENABLE_REG] = intc_mode_field,
220 [MODE_MASK_REG] = intc_mode_zero,
221 [MODE_DUAL_REG] = intc_mode_field,
222 [MODE_PRIO_REG] = intc_mode_prio,
223 [MODE_PCLR_REG] = intc_mode_prio,
226 static void (*intc_disable_fns[])(unsigned long addr,
227 unsigned long handle,
228 void (*fn)(unsigned long,
231 unsigned int irq) = {
232 [MODE_ENABLE_REG] = intc_mode_zero,
233 [MODE_MASK_REG] = intc_mode_field,
234 [MODE_DUAL_REG] = intc_mode_field,
235 [MODE_PRIO_REG] = intc_mode_zero,
236 [MODE_PCLR_REG] = intc_mode_field,
239 static inline void _intc_enable(unsigned int irq, unsigned long handle)
241 struct intc_desc_int *d = get_intc_desc(irq);
245 for (cpu = 0; cpu < SMP_NR(d, _INTC_ADDR_E(handle)); cpu++) {
247 if (!cpumask_test_cpu(cpu, irq_to_desc(irq)->affinity))
250 addr = INTC_REG(d, _INTC_ADDR_E(handle), cpu);
251 intc_enable_fns[_INTC_MODE(handle)](addr, handle, intc_reg_fns\
252 [_INTC_FN(handle)], irq);
256 static void intc_enable(unsigned int irq)
258 _intc_enable(irq, (unsigned long)get_irq_chip_data(irq));
261 static void intc_disable(unsigned int irq)
263 struct intc_desc_int *d = get_intc_desc(irq);
264 unsigned long handle = (unsigned long) get_irq_chip_data(irq);
268 for (cpu = 0; cpu < SMP_NR(d, _INTC_ADDR_D(handle)); cpu++) {
270 if (!cpumask_test_cpu(cpu, irq_to_desc(irq)->affinity))
273 addr = INTC_REG(d, _INTC_ADDR_D(handle), cpu);
274 intc_disable_fns[_INTC_MODE(handle)](addr, handle,intc_reg_fns\
275 [_INTC_FN(handle)], irq);
279 static void (*intc_enable_noprio_fns[])(unsigned long addr,
280 unsigned long handle,
281 void (*fn)(unsigned long,
284 unsigned int irq) = {
285 [MODE_ENABLE_REG] = intc_mode_field,
286 [MODE_MASK_REG] = intc_mode_zero,
287 [MODE_DUAL_REG] = intc_mode_field,
288 [MODE_PRIO_REG] = intc_mode_field,
289 [MODE_PCLR_REG] = intc_mode_field,
292 static void intc_enable_disable(struct intc_desc_int *d,
293 unsigned long handle, int do_enable)
297 void (*fn)(unsigned long, unsigned long,
298 void (*)(unsigned long, unsigned long, unsigned long),
302 for (cpu = 0; cpu < SMP_NR(d, _INTC_ADDR_E(handle)); cpu++) {
303 addr = INTC_REG(d, _INTC_ADDR_E(handle), cpu);
304 fn = intc_enable_noprio_fns[_INTC_MODE(handle)];
305 fn(addr, handle, intc_reg_fns[_INTC_FN(handle)], 0);
308 for (cpu = 0; cpu < SMP_NR(d, _INTC_ADDR_D(handle)); cpu++) {
309 addr = INTC_REG(d, _INTC_ADDR_D(handle), cpu);
310 fn = intc_disable_fns[_INTC_MODE(handle)];
311 fn(addr, handle, intc_reg_fns[_INTC_FN(handle)], 0);
316 static int intc_set_wake(unsigned int irq, unsigned int on)
318 return 0; /* allow wakeup, but setup hardware in intc_suspend() */
323 * This is held with the irq desc lock held, so we don't require any
324 * additional locking here at the intc desc level. The affinity mask is
325 * later tested in the enable/disable paths.
327 static int intc_set_affinity(unsigned int irq, const struct cpumask *cpumask)
329 if (!cpumask_intersects(cpumask, cpu_online_mask))
332 cpumask_copy(irq_to_desc(irq)->affinity, cpumask);
338 static void intc_mask_ack(unsigned int irq)
340 struct intc_desc_int *d = get_intc_desc(irq);
341 unsigned long handle = ack_handle[irq];
346 /* read register and write zero only to the assocaited bit */
349 addr = INTC_REG(d, _INTC_ADDR_D(handle), 0);
350 switch (_INTC_FN(handle)) {
351 case REG_FN_MODIFY_BASE + 0: /* 8bit */
353 __raw_writeb(0xff ^ set_field(0, 1, handle), addr);
355 case REG_FN_MODIFY_BASE + 1: /* 16bit */
357 __raw_writew(0xffff ^ set_field(0, 1, handle), addr);
359 case REG_FN_MODIFY_BASE + 3: /* 32bit */
361 __raw_writel(0xffffffff ^ set_field(0, 1, handle), addr);
370 static struct intc_handle_int *intc_find_irq(struct intc_handle_int *hp,
376 /* this doesn't scale well, but...
378 * this function should only be used for cerain uncommon
379 * operations such as intc_set_priority() and intc_set_sense()
380 * and in those rare cases performance doesn't matter that much.
381 * keeping the memory footprint low is more important.
383 * one rather simple way to speed this up and still keep the
384 * memory footprint down is to make sure the array is sorted
385 * and then perform a bisect to lookup the irq.
388 for (i = 0; i < nr_hp; i++) {
389 if ((hp + i)->irq != irq)
398 int intc_set_priority(unsigned int irq, unsigned int prio)
400 struct intc_desc_int *d = get_intc_desc(irq);
401 struct intc_handle_int *ihp;
403 if (!intc_prio_level[irq] || prio <= 1)
406 ihp = intc_find_irq(d->prio, d->nr_prio, irq);
408 if (prio >= (1 << _INTC_WIDTH(ihp->handle)))
411 intc_prio_level[irq] = prio;
414 * only set secondary masking method directly
415 * primary masking method is using intc_prio_level[irq]
416 * priority level will be set during next enable()
419 if (_INTC_FN(ihp->handle) != REG_FN_ERR)
420 _intc_enable(irq, ihp->handle);
425 #define VALID(x) (x | 0x80)
427 static unsigned char intc_irq_sense_table[IRQ_TYPE_SENSE_MASK + 1] = {
428 [IRQ_TYPE_EDGE_FALLING] = VALID(0),
429 [IRQ_TYPE_EDGE_RISING] = VALID(1),
430 [IRQ_TYPE_LEVEL_LOW] = VALID(2),
431 /* SH7706, SH7707 and SH7709 do not support high level triggered */
432 #if !defined(CONFIG_CPU_SUBTYPE_SH7706) && \
433 !defined(CONFIG_CPU_SUBTYPE_SH7707) && \
434 !defined(CONFIG_CPU_SUBTYPE_SH7709)
435 [IRQ_TYPE_LEVEL_HIGH] = VALID(3),
439 static int intc_set_sense(unsigned int irq, unsigned int type)
441 struct intc_desc_int *d = get_intc_desc(irq);
442 unsigned char value = intc_irq_sense_table[type & IRQ_TYPE_SENSE_MASK];
443 struct intc_handle_int *ihp;
449 ihp = intc_find_irq(d->sense, d->nr_sense, irq);
451 addr = INTC_REG(d, _INTC_ADDR_E(ihp->handle), 0);
452 intc_reg_fns[_INTC_FN(ihp->handle)](addr, ihp->handle, value);
457 static unsigned long intc_phys_to_virt(struct intc_desc_int *d,
458 unsigned long address)
460 struct intc_window *window;
463 /* scan through physical windows and convert address */
464 for (k = 0; k < d->nr_windows; k++) {
465 window = d->window + k;
467 if (address < window->phys)
470 if (address >= (window->phys + window->size))
473 address -= window->phys;
474 address += (unsigned long)window->virt;
479 /* no windows defined, register must be 1:1 mapped virt:phys */
483 static unsigned int __init intc_get_reg(struct intc_desc_int *d,
484 unsigned long address)
488 address = intc_phys_to_virt(d, address);
490 for (k = 0; k < d->nr_reg; k++) {
491 if (d->reg[k] == address)
499 static intc_enum __init intc_grp_id(struct intc_desc *desc,
502 struct intc_group *g = desc->hw.groups;
505 for (i = 0; g && enum_id && i < desc->hw.nr_groups; i++) {
506 g = desc->hw.groups + i;
508 for (j = 0; g->enum_ids[j]; j++) {
509 if (g->enum_ids[j] != enum_id)
519 static unsigned int __init _intc_mask_data(struct intc_desc *desc,
520 struct intc_desc_int *d,
522 unsigned int *reg_idx,
523 unsigned int *fld_idx)
525 struct intc_mask_reg *mr = desc->hw.mask_regs;
526 unsigned int fn, mode;
527 unsigned long reg_e, reg_d;
529 while (mr && enum_id && *reg_idx < desc->hw.nr_mask_regs) {
530 mr = desc->hw.mask_regs + *reg_idx;
532 for (; *fld_idx < ARRAY_SIZE(mr->enum_ids); (*fld_idx)++) {
533 if (mr->enum_ids[*fld_idx] != enum_id)
536 if (mr->set_reg && mr->clr_reg) {
537 fn = REG_FN_WRITE_BASE;
538 mode = MODE_DUAL_REG;
542 fn = REG_FN_MODIFY_BASE;
544 mode = MODE_ENABLE_REG;
548 mode = MODE_MASK_REG;
554 fn += (mr->reg_width >> 3) - 1;
555 return _INTC_MK(fn, mode,
556 intc_get_reg(d, reg_e),
557 intc_get_reg(d, reg_d),
559 (mr->reg_width - 1) - *fld_idx);
569 static unsigned int __init intc_mask_data(struct intc_desc *desc,
570 struct intc_desc_int *d,
571 intc_enum enum_id, int do_grps)
577 ret = _intc_mask_data(desc, d, enum_id, &i, &j);
582 return intc_mask_data(desc, d, intc_grp_id(desc, enum_id), 0);
587 static unsigned int __init _intc_prio_data(struct intc_desc *desc,
588 struct intc_desc_int *d,
590 unsigned int *reg_idx,
591 unsigned int *fld_idx)
593 struct intc_prio_reg *pr = desc->hw.prio_regs;
594 unsigned int fn, n, mode, bit;
595 unsigned long reg_e, reg_d;
597 while (pr && enum_id && *reg_idx < desc->hw.nr_prio_regs) {
598 pr = desc->hw.prio_regs + *reg_idx;
600 for (; *fld_idx < ARRAY_SIZE(pr->enum_ids); (*fld_idx)++) {
601 if (pr->enum_ids[*fld_idx] != enum_id)
604 if (pr->set_reg && pr->clr_reg) {
605 fn = REG_FN_WRITE_BASE;
606 mode = MODE_PCLR_REG;
610 fn = REG_FN_MODIFY_BASE;
611 mode = MODE_PRIO_REG;
618 fn += (pr->reg_width >> 3) - 1;
621 BUG_ON(n * pr->field_width > pr->reg_width);
623 bit = pr->reg_width - (n * pr->field_width);
625 return _INTC_MK(fn, mode,
626 intc_get_reg(d, reg_e),
627 intc_get_reg(d, reg_d),
628 pr->field_width, bit);
638 static unsigned int __init intc_prio_data(struct intc_desc *desc,
639 struct intc_desc_int *d,
640 intc_enum enum_id, int do_grps)
646 ret = _intc_prio_data(desc, d, enum_id, &i, &j);
651 return intc_prio_data(desc, d, intc_grp_id(desc, enum_id), 0);
656 static void __init intc_enable_disable_enum(struct intc_desc *desc,
657 struct intc_desc_int *d,
658 intc_enum enum_id, int enable)
660 unsigned int i, j, data;
662 /* go through and enable/disable all mask bits */
665 data = _intc_mask_data(desc, d, enum_id, &i, &j);
667 intc_enable_disable(d, data, enable);
671 /* go through and enable/disable all priority fields */
674 data = _intc_prio_data(desc, d, enum_id, &i, &j);
676 intc_enable_disable(d, data, enable);
682 static unsigned int __init intc_ack_data(struct intc_desc *desc,
683 struct intc_desc_int *d,
686 struct intc_mask_reg *mr = desc->hw.ack_regs;
687 unsigned int i, j, fn, mode;
688 unsigned long reg_e, reg_d;
690 for (i = 0; mr && enum_id && i < desc->hw.nr_ack_regs; i++) {
691 mr = desc->hw.ack_regs + i;
693 for (j = 0; j < ARRAY_SIZE(mr->enum_ids); j++) {
694 if (mr->enum_ids[j] != enum_id)
697 fn = REG_FN_MODIFY_BASE;
698 mode = MODE_ENABLE_REG;
702 fn += (mr->reg_width >> 3) - 1;
703 return _INTC_MK(fn, mode,
704 intc_get_reg(d, reg_e),
705 intc_get_reg(d, reg_d),
707 (mr->reg_width - 1) - j);
714 static unsigned int __init intc_sense_data(struct intc_desc *desc,
715 struct intc_desc_int *d,
718 struct intc_sense_reg *sr = desc->hw.sense_regs;
719 unsigned int i, j, fn, bit;
721 for (i = 0; sr && enum_id && i < desc->hw.nr_sense_regs; i++) {
722 sr = desc->hw.sense_regs + i;
724 for (j = 0; j < ARRAY_SIZE(sr->enum_ids); j++) {
725 if (sr->enum_ids[j] != enum_id)
728 fn = REG_FN_MODIFY_BASE;
729 fn += (sr->reg_width >> 3) - 1;
731 BUG_ON((j + 1) * sr->field_width > sr->reg_width);
733 bit = sr->reg_width - ((j + 1) * sr->field_width);
735 return _INTC_MK(fn, 0, intc_get_reg(d, sr->reg),
736 0, sr->field_width, bit);
743 static void __init intc_register_irq(struct intc_desc *desc,
744 struct intc_desc_int *d,
748 struct intc_handle_int *hp;
749 unsigned int data[2], primary;
752 * Register the IRQ position with the global IRQ map
754 set_bit(irq, intc_irq_map);
756 /* Prefer single interrupt source bitmap over other combinations:
757 * 1. bitmap, single interrupt source
758 * 2. priority, single interrupt source
759 * 3. bitmap, multiple interrupt sources (groups)
760 * 4. priority, multiple interrupt sources (groups)
763 data[0] = intc_mask_data(desc, d, enum_id, 0);
764 data[1] = intc_prio_data(desc, d, enum_id, 0);
767 if (!data[0] && data[1])
770 if (!data[0] && !data[1])
771 pr_warning("intc: missing unique irq mask for "
772 "irq %d (vect 0x%04x)\n", irq, irq2evt(irq));
774 data[0] = data[0] ? data[0] : intc_mask_data(desc, d, enum_id, 1);
775 data[1] = data[1] ? data[1] : intc_prio_data(desc, d, enum_id, 1);
780 BUG_ON(!data[primary]); /* must have primary masking method */
782 disable_irq_nosync(irq);
783 set_irq_chip_and_handler_name(irq, &d->chip,
784 handle_level_irq, "level");
785 set_irq_chip_data(irq, (void *)data[primary]);
787 /* set priority level
788 * - this needs to be at least 2 for 5-bit priorities on 7780
790 intc_prio_level[irq] = 2;
792 /* enable secondary masking method if present */
794 _intc_enable(irq, data[!primary]);
796 /* add irq to d->prio list if priority is available */
798 hp = d->prio + d->nr_prio;
800 hp->handle = data[1];
804 * only secondary priority should access registers, so
805 * set _INTC_FN(h) = REG_FN_ERR for intc_set_priority()
808 hp->handle &= ~_INTC_MK(0x0f, 0, 0, 0, 0, 0);
809 hp->handle |= _INTC_MK(REG_FN_ERR, 0, 0, 0, 0, 0);
814 /* add irq to d->sense list if sense is available */
815 data[0] = intc_sense_data(desc, d, enum_id);
817 (d->sense + d->nr_sense)->irq = irq;
818 (d->sense + d->nr_sense)->handle = data[0];
822 /* irq should be disabled by default */
825 if (desc->hw.ack_regs)
826 ack_handle[irq] = intc_ack_data(desc, d, enum_id);
829 set_irq_flags(irq, IRQF_VALID); /* Enable IRQ on ARM systems */
833 static unsigned int __init save_reg(struct intc_desc_int *d,
839 value = intc_phys_to_virt(d, value);
851 static void intc_redirect_irq(unsigned int irq, struct irq_desc *desc)
853 generic_handle_irq((unsigned int)get_irq_data(irq));
856 int __init register_intc_controller(struct intc_desc *desc)
858 unsigned int i, k, smp;
859 struct intc_hw_desc *hw = &desc->hw;
860 struct intc_desc_int *d;
861 struct resource *res;
863 d = kzalloc(sizeof(*d), GFP_NOWAIT);
867 INIT_LIST_HEAD(&d->list);
868 list_add(&d->list, &intc_list);
870 if (desc->num_resources) {
871 d->nr_windows = desc->num_resources;
872 d->window = kzalloc(d->nr_windows * sizeof(*d->window),
877 for (k = 0; k < d->nr_windows; k++) {
878 res = desc->resource + k;
879 WARN_ON(resource_type(res) != IORESOURCE_MEM);
880 d->window[k].phys = res->start;
881 d->window[k].size = resource_size(res);
882 d->window[k].virt = ioremap_nocache(res->start,
884 if (!d->window[k].virt)
889 d->nr_reg = hw->mask_regs ? hw->nr_mask_regs * 2 : 0;
890 d->nr_reg += hw->prio_regs ? hw->nr_prio_regs * 2 : 0;
891 d->nr_reg += hw->sense_regs ? hw->nr_sense_regs : 0;
892 d->nr_reg += hw->ack_regs ? hw->nr_ack_regs : 0;
894 d->reg = kzalloc(d->nr_reg * sizeof(*d->reg), GFP_NOWAIT);
899 d->smp = kzalloc(d->nr_reg * sizeof(*d->smp), GFP_NOWAIT);
906 for (i = 0; i < hw->nr_mask_regs; i++) {
907 smp = IS_SMP(hw->mask_regs[i]);
908 k += save_reg(d, k, hw->mask_regs[i].set_reg, smp);
909 k += save_reg(d, k, hw->mask_regs[i].clr_reg, smp);
914 d->prio = kzalloc(hw->nr_vectors * sizeof(*d->prio),
919 for (i = 0; i < hw->nr_prio_regs; i++) {
920 smp = IS_SMP(hw->prio_regs[i]);
921 k += save_reg(d, k, hw->prio_regs[i].set_reg, smp);
922 k += save_reg(d, k, hw->prio_regs[i].clr_reg, smp);
926 if (hw->sense_regs) {
927 d->sense = kzalloc(hw->nr_vectors * sizeof(*d->sense),
932 for (i = 0; i < hw->nr_sense_regs; i++)
933 k += save_reg(d, k, hw->sense_regs[i].reg, 0);
936 d->chip.name = desc->name;
937 d->chip.mask = intc_disable;
938 d->chip.unmask = intc_enable;
939 d->chip.mask_ack = intc_disable;
940 d->chip.enable = intc_enable;
941 d->chip.disable = intc_disable;
942 d->chip.shutdown = intc_disable;
943 d->chip.set_type = intc_set_sense;
944 d->chip.set_wake = intc_set_wake;
946 d->chip.set_affinity = intc_set_affinity;
950 for (i = 0; i < hw->nr_ack_regs; i++)
951 k += save_reg(d, k, hw->ack_regs[i].set_reg, 0);
953 d->chip.mask_ack = intc_mask_ack;
956 /* disable bits matching force_disable before registering irqs */
957 if (desc->force_disable)
958 intc_enable_disable_enum(desc, d, desc->force_disable, 0);
960 /* disable bits matching force_enable before registering irqs */
961 if (desc->force_enable)
962 intc_enable_disable_enum(desc, d, desc->force_enable, 0);
964 BUG_ON(k > 256); /* _INTC_ADDR_E() and _INTC_ADDR_D() are 8 bits */
966 /* register the vectors one by one */
967 for (i = 0; i < hw->nr_vectors; i++) {
968 struct intc_vect *vect = hw->vectors + i;
969 unsigned int irq = evt2irq(vect->vect);
970 struct irq_desc *irq_desc;
975 irq_desc = irq_to_desc_alloc_node(irq, numa_node_id());
976 if (unlikely(!irq_desc)) {
977 pr_info("can't get irq_desc for %d\n", irq);
981 intc_register_irq(desc, d, vect->enum_id, irq);
983 for (k = i + 1; k < hw->nr_vectors; k++) {
984 struct intc_vect *vect2 = hw->vectors + k;
985 unsigned int irq2 = evt2irq(vect2->vect);
987 if (vect->enum_id != vect2->enum_id)
991 * In the case of multi-evt handling and sparse
992 * IRQ support, each vector still needs to have
993 * its own backing irq_desc.
995 irq_desc = irq_to_desc_alloc_node(irq2, numa_node_id());
996 if (unlikely(!irq_desc)) {
997 pr_info("can't get irq_desc for %d\n", irq2);
1003 /* redirect this interrupts to the first one */
1004 set_irq_chip(irq2, &dummy_irq_chip);
1005 set_irq_chained_handler(irq2, intc_redirect_irq);
1006 set_irq_data(irq2, (void *)irq);
1010 /* enable bits matching force_enable after registering irqs */
1011 if (desc->force_enable)
1012 intc_enable_disable_enum(desc, d, desc->force_enable, 1);
1024 for (k = 0; k < d->nr_windows; k++)
1025 if (d->window[k].virt)
1026 iounmap(d->window[k].virt);
1032 pr_err("unable to allocate INTC memory\n");
1038 show_intc_name(struct sys_device *dev, struct sysdev_attribute *attr, char *buf)
1040 struct intc_desc_int *d;
1042 d = container_of(dev, struct intc_desc_int, sysdev);
1044 return sprintf(buf, "%s\n", d->chip.name);
1047 static SYSDEV_ATTR(name, S_IRUGO, show_intc_name, NULL);
1049 static int intc_suspend(struct sys_device *dev, pm_message_t state)
1051 struct intc_desc_int *d;
1052 struct irq_desc *desc;
1055 /* get intc controller associated with this sysdev */
1056 d = container_of(dev, struct intc_desc_int, sysdev);
1058 switch (state.event) {
1060 if (d->state.event != PM_EVENT_FREEZE)
1062 for_each_irq_desc(irq, desc) {
1063 if (desc->handle_irq == intc_redirect_irq)
1065 if (desc->chip != &d->chip)
1067 if (desc->status & IRQ_DISABLED)
1073 case PM_EVENT_FREEZE:
1074 /* nothing has to be done */
1076 case PM_EVENT_SUSPEND:
1077 /* enable wakeup irqs belonging to this intc controller */
1078 for_each_irq_desc(irq, desc) {
1079 if ((desc->status & IRQ_WAKEUP) && (desc->chip == &d->chip))
1089 static int intc_resume(struct sys_device *dev)
1091 return intc_suspend(dev, PMSG_ON);
1094 static struct sysdev_class intc_sysdev_class = {
1096 .suspend = intc_suspend,
1097 .resume = intc_resume,
1100 /* register this intc as sysdev to allow suspend/resume */
1101 static int __init register_intc_sysdevs(void)
1103 struct intc_desc_int *d;
1107 error = sysdev_class_register(&intc_sysdev_class);
1109 list_for_each_entry(d, &intc_list, list) {
1111 d->sysdev.cls = &intc_sysdev_class;
1112 error = sysdev_register(&d->sysdev);
1114 error = sysdev_create_file(&d->sysdev,
1124 pr_warning("intc: sysdev registration error\n");
1128 device_initcall(register_intc_sysdevs);
1131 * Dynamic IRQ allocation and deallocation
1133 unsigned int create_irq_nr(unsigned int irq_want, int node)
1135 unsigned int irq = 0, new;
1136 unsigned long flags;
1137 struct irq_desc *desc;
1139 spin_lock_irqsave(&vector_lock, flags);
1142 * First try the wanted IRQ
1144 if (test_and_set_bit(irq_want, intc_irq_map) == 0) {
1147 /* .. then fall back to scanning. */
1148 new = find_first_zero_bit(intc_irq_map, nr_irqs);
1149 if (unlikely(new == nr_irqs))
1152 __set_bit(new, intc_irq_map);
1155 desc = irq_to_desc_alloc_node(new, node);
1156 if (unlikely(!desc)) {
1157 pr_info("can't get irq_desc for %d\n", new);
1161 desc = move_irq_desc(desc, node);
1165 spin_unlock_irqrestore(&vector_lock, flags);
1168 dynamic_irq_init(irq);
1170 set_irq_flags(irq, IRQF_VALID); /* Enable IRQ on ARM systems */
1177 int create_irq(void)
1179 int nid = cpu_to_node(smp_processor_id());
1182 irq = create_irq_nr(NR_IRQS_LEGACY, nid);
1189 void destroy_irq(unsigned int irq)
1191 unsigned long flags;
1193 dynamic_irq_cleanup(irq);
1195 spin_lock_irqsave(&vector_lock, flags);
1196 __clear_bit(irq, intc_irq_map);
1197 spin_unlock_irqrestore(&vector_lock, flags);
1200 int reserve_irq_vector(unsigned int irq)
1202 unsigned long flags;
1205 spin_lock_irqsave(&vector_lock, flags);
1206 if (test_and_set_bit(irq, intc_irq_map))
1208 spin_unlock_irqrestore(&vector_lock, flags);
1213 void reserve_irq_legacy(void)
1215 unsigned long flags;
1218 spin_lock_irqsave(&vector_lock, flags);
1219 j = find_first_bit(intc_irq_map, nr_irqs);
1220 for (i = 0; i < j; i++)
1221 __set_bit(i, intc_irq_map);
1222 spin_unlock_irqrestore(&vector_lock, flags);