2 * Shared interrupt handling code for IPR and INTC2 types of IRQs.
4 * Copyright (C) 2007, 2008 Magnus Damm
5 * Copyright (C) 2009 Paul Mundt
7 * Based on intc2.c and ipr.c
9 * Copyright (C) 1999 Niibe Yutaka & Takeshi Yaegashi
10 * Copyright (C) 2000 Kazumoto Kojima
11 * Copyright (C) 2001 David J. Mckay (david.mckay@st.com)
12 * Copyright (C) 2003 Takashi Kusuda <kusuda-takashi@hitachi-ul.co.jp>
13 * Copyright (C) 2005, 2006 Paul Mundt
15 * This file is subject to the terms and conditions of the GNU General Public
16 * License. See the file "COPYING" in the main directory of this archive
19 #include <linux/init.h>
20 #include <linux/irq.h>
21 #include <linux/module.h>
23 #include <linux/interrupt.h>
24 #include <linux/sh_intc.h>
25 #include <linux/sysdev.h>
26 #include <linux/list.h>
27 #include <linux/topology.h>
28 #include <linux/bitmap.h>
30 #define _INTC_MK(fn, mode, addr_e, addr_d, width, shift) \
31 ((shift) | ((width) << 5) | ((fn) << 9) | ((mode) << 13) | \
32 ((addr_e) << 16) | ((addr_d << 24)))
34 #define _INTC_SHIFT(h) (h & 0x1f)
35 #define _INTC_WIDTH(h) ((h >> 5) & 0xf)
36 #define _INTC_FN(h) ((h >> 9) & 0xf)
37 #define _INTC_MODE(h) ((h >> 13) & 0x7)
38 #define _INTC_ADDR_E(h) ((h >> 16) & 0xff)
39 #define _INTC_ADDR_D(h) ((h >> 24) & 0xff)
41 struct intc_handle_int {
52 struct intc_desc_int {
53 struct list_head list;
54 struct sys_device sysdev;
61 struct intc_handle_int *prio;
63 struct intc_handle_int *sense;
64 unsigned int nr_sense;
65 struct intc_window *window;
66 unsigned int nr_windows;
70 static LIST_HEAD(intc_list);
73 * The intc_irq_map provides a global map of bound IRQ vectors for a
74 * given platform. Allocation of IRQs are either static through the CPU
75 * vector map, or dynamic in the case of board mux vectors or MSI.
77 * As this is a central point for all IRQ controllers on the system,
78 * each of the available sources are mapped out here. This combined with
79 * sparseirq makes it quite trivial to keep the vector map tightly packed
80 * when dynamically creating IRQs, as well as tying in to otherwise
81 * unused irq_desc positions in the sparse array.
83 static DECLARE_BITMAP(intc_irq_map, NR_IRQS);
84 static DEFINE_SPINLOCK(vector_lock);
87 #define IS_SMP(x) x.smp
88 #define INTC_REG(d, x, c) (d->reg[(x)] + ((d->smp[(x)] & 0xff) * c))
89 #define SMP_NR(d, x) ((d->smp[(x)] >> 8) ? (d->smp[(x)] >> 8) : 1)
92 #define INTC_REG(d, x, c) (d->reg[(x)])
93 #define SMP_NR(d, x) 1
96 static unsigned int intc_prio_level[NR_IRQS]; /* for now */
97 static unsigned long ack_handle[NR_IRQS];
99 static inline struct intc_desc_int *get_intc_desc(unsigned int irq)
101 struct irq_chip *chip = get_irq_chip(irq);
102 return container_of(chip, struct intc_desc_int, chip);
105 static inline unsigned int set_field(unsigned int value,
106 unsigned int field_value,
109 unsigned int width = _INTC_WIDTH(handle);
110 unsigned int shift = _INTC_SHIFT(handle);
112 value &= ~(((1 << width) - 1) << shift);
113 value |= field_value << shift;
117 static void write_8(unsigned long addr, unsigned long h, unsigned long data)
119 __raw_writeb(set_field(0, data, h), addr);
120 (void)__raw_readb(addr); /* Defeat write posting */
123 static void write_16(unsigned long addr, unsigned long h, unsigned long data)
125 __raw_writew(set_field(0, data, h), addr);
126 (void)__raw_readw(addr); /* Defeat write posting */
129 static void write_32(unsigned long addr, unsigned long h, unsigned long data)
131 __raw_writel(set_field(0, data, h), addr);
132 (void)__raw_readl(addr); /* Defeat write posting */
135 static void modify_8(unsigned long addr, unsigned long h, unsigned long data)
138 local_irq_save(flags);
139 __raw_writeb(set_field(__raw_readb(addr), data, h), addr);
140 (void)__raw_readb(addr); /* Defeat write posting */
141 local_irq_restore(flags);
144 static void modify_16(unsigned long addr, unsigned long h, unsigned long data)
147 local_irq_save(flags);
148 __raw_writew(set_field(__raw_readw(addr), data, h), addr);
149 (void)__raw_readw(addr); /* Defeat write posting */
150 local_irq_restore(flags);
153 static void modify_32(unsigned long addr, unsigned long h, unsigned long data)
156 local_irq_save(flags);
157 __raw_writel(set_field(__raw_readl(addr), data, h), addr);
158 (void)__raw_readl(addr); /* Defeat write posting */
159 local_irq_restore(flags);
162 enum { REG_FN_ERR = 0, REG_FN_WRITE_BASE = 1, REG_FN_MODIFY_BASE = 5 };
164 static void (*intc_reg_fns[])(unsigned long addr,
166 unsigned long data) = {
167 [REG_FN_WRITE_BASE + 0] = write_8,
168 [REG_FN_WRITE_BASE + 1] = write_16,
169 [REG_FN_WRITE_BASE + 3] = write_32,
170 [REG_FN_MODIFY_BASE + 0] = modify_8,
171 [REG_FN_MODIFY_BASE + 1] = modify_16,
172 [REG_FN_MODIFY_BASE + 3] = modify_32,
175 enum { MODE_ENABLE_REG = 0, /* Bit(s) set -> interrupt enabled */
176 MODE_MASK_REG, /* Bit(s) set -> interrupt disabled */
177 MODE_DUAL_REG, /* Two registers, set bit to enable / disable */
178 MODE_PRIO_REG, /* Priority value written to enable interrupt */
179 MODE_PCLR_REG, /* Above plus all bits set to disable interrupt */
182 static void intc_mode_field(unsigned long addr,
183 unsigned long handle,
184 void (*fn)(unsigned long,
189 fn(addr, handle, ((1 << _INTC_WIDTH(handle)) - 1));
192 static void intc_mode_zero(unsigned long addr,
193 unsigned long handle,
194 void (*fn)(unsigned long,
202 static void intc_mode_prio(unsigned long addr,
203 unsigned long handle,
204 void (*fn)(unsigned long,
209 fn(addr, handle, intc_prio_level[irq]);
212 static void (*intc_enable_fns[])(unsigned long addr,
213 unsigned long handle,
214 void (*fn)(unsigned long,
217 unsigned int irq) = {
218 [MODE_ENABLE_REG] = intc_mode_field,
219 [MODE_MASK_REG] = intc_mode_zero,
220 [MODE_DUAL_REG] = intc_mode_field,
221 [MODE_PRIO_REG] = intc_mode_prio,
222 [MODE_PCLR_REG] = intc_mode_prio,
225 static void (*intc_disable_fns[])(unsigned long addr,
226 unsigned long handle,
227 void (*fn)(unsigned long,
230 unsigned int irq) = {
231 [MODE_ENABLE_REG] = intc_mode_zero,
232 [MODE_MASK_REG] = intc_mode_field,
233 [MODE_DUAL_REG] = intc_mode_field,
234 [MODE_PRIO_REG] = intc_mode_zero,
235 [MODE_PCLR_REG] = intc_mode_field,
238 static inline void _intc_enable(unsigned int irq, unsigned long handle)
240 struct intc_desc_int *d = get_intc_desc(irq);
244 for (cpu = 0; cpu < SMP_NR(d, _INTC_ADDR_E(handle)); cpu++) {
245 addr = INTC_REG(d, _INTC_ADDR_E(handle), cpu);
246 intc_enable_fns[_INTC_MODE(handle)](addr, handle, intc_reg_fns\
247 [_INTC_FN(handle)], irq);
251 static void intc_enable(unsigned int irq)
253 _intc_enable(irq, (unsigned long)get_irq_chip_data(irq));
256 static void intc_disable(unsigned int irq)
258 struct intc_desc_int *d = get_intc_desc(irq);
259 unsigned long handle = (unsigned long) get_irq_chip_data(irq);
263 for (cpu = 0; cpu < SMP_NR(d, _INTC_ADDR_D(handle)); cpu++) {
264 addr = INTC_REG(d, _INTC_ADDR_D(handle), cpu);
265 intc_disable_fns[_INTC_MODE(handle)](addr, handle,intc_reg_fns\
266 [_INTC_FN(handle)], irq);
270 static void (*intc_enable_noprio_fns[])(unsigned long addr,
271 unsigned long handle,
272 void (*fn)(unsigned long,
275 unsigned int irq) = {
276 [MODE_ENABLE_REG] = intc_mode_field,
277 [MODE_MASK_REG] = intc_mode_zero,
278 [MODE_DUAL_REG] = intc_mode_field,
279 [MODE_PRIO_REG] = intc_mode_field,
280 [MODE_PCLR_REG] = intc_mode_field,
283 static void intc_enable_disable(struct intc_desc_int *d,
284 unsigned long handle, int do_enable)
288 void (*fn)(unsigned long, unsigned long,
289 void (*)(unsigned long, unsigned long, unsigned long),
293 for (cpu = 0; cpu < SMP_NR(d, _INTC_ADDR_E(handle)); cpu++) {
294 addr = INTC_REG(d, _INTC_ADDR_E(handle), cpu);
295 fn = intc_enable_noprio_fns[_INTC_MODE(handle)];
296 fn(addr, handle, intc_reg_fns[_INTC_FN(handle)], 0);
299 for (cpu = 0; cpu < SMP_NR(d, _INTC_ADDR_D(handle)); cpu++) {
300 addr = INTC_REG(d, _INTC_ADDR_D(handle), cpu);
301 fn = intc_disable_fns[_INTC_MODE(handle)];
302 fn(addr, handle, intc_reg_fns[_INTC_FN(handle)], 0);
307 static int intc_set_wake(unsigned int irq, unsigned int on)
309 return 0; /* allow wakeup, but setup hardware in intc_suspend() */
312 static void intc_mask_ack(unsigned int irq)
314 struct intc_desc_int *d = get_intc_desc(irq);
315 unsigned long handle = ack_handle[irq];
320 /* read register and write zero only to the assocaited bit */
323 addr = INTC_REG(d, _INTC_ADDR_D(handle), 0);
324 switch (_INTC_FN(handle)) {
325 case REG_FN_MODIFY_BASE + 0: /* 8bit */
327 __raw_writeb(0xff ^ set_field(0, 1, handle), addr);
329 case REG_FN_MODIFY_BASE + 1: /* 16bit */
331 __raw_writew(0xffff ^ set_field(0, 1, handle), addr);
333 case REG_FN_MODIFY_BASE + 3: /* 32bit */
335 __raw_writel(0xffffffff ^ set_field(0, 1, handle), addr);
344 static struct intc_handle_int *intc_find_irq(struct intc_handle_int *hp,
350 /* this doesn't scale well, but...
352 * this function should only be used for cerain uncommon
353 * operations such as intc_set_priority() and intc_set_sense()
354 * and in those rare cases performance doesn't matter that much.
355 * keeping the memory footprint low is more important.
357 * one rather simple way to speed this up and still keep the
358 * memory footprint down is to make sure the array is sorted
359 * and then perform a bisect to lookup the irq.
362 for (i = 0; i < nr_hp; i++) {
363 if ((hp + i)->irq != irq)
372 int intc_set_priority(unsigned int irq, unsigned int prio)
374 struct intc_desc_int *d = get_intc_desc(irq);
375 struct intc_handle_int *ihp;
377 if (!intc_prio_level[irq] || prio <= 1)
380 ihp = intc_find_irq(d->prio, d->nr_prio, irq);
382 if (prio >= (1 << _INTC_WIDTH(ihp->handle)))
385 intc_prio_level[irq] = prio;
388 * only set secondary masking method directly
389 * primary masking method is using intc_prio_level[irq]
390 * priority level will be set during next enable()
393 if (_INTC_FN(ihp->handle) != REG_FN_ERR)
394 _intc_enable(irq, ihp->handle);
399 #define VALID(x) (x | 0x80)
401 static unsigned char intc_irq_sense_table[IRQ_TYPE_SENSE_MASK + 1] = {
402 [IRQ_TYPE_EDGE_FALLING] = VALID(0),
403 [IRQ_TYPE_EDGE_RISING] = VALID(1),
404 [IRQ_TYPE_LEVEL_LOW] = VALID(2),
405 /* SH7706, SH7707 and SH7709 do not support high level triggered */
406 #if !defined(CONFIG_CPU_SUBTYPE_SH7706) && \
407 !defined(CONFIG_CPU_SUBTYPE_SH7707) && \
408 !defined(CONFIG_CPU_SUBTYPE_SH7709)
409 [IRQ_TYPE_LEVEL_HIGH] = VALID(3),
413 static int intc_set_sense(unsigned int irq, unsigned int type)
415 struct intc_desc_int *d = get_intc_desc(irq);
416 unsigned char value = intc_irq_sense_table[type & IRQ_TYPE_SENSE_MASK];
417 struct intc_handle_int *ihp;
423 ihp = intc_find_irq(d->sense, d->nr_sense, irq);
425 addr = INTC_REG(d, _INTC_ADDR_E(ihp->handle), 0);
426 intc_reg_fns[_INTC_FN(ihp->handle)](addr, ihp->handle, value);
431 static unsigned long intc_phys_to_virt(struct intc_desc_int *d,
432 unsigned long address)
434 struct intc_window *window;
437 /* scan through physical windows and convert address */
438 for (k = 0; k < d->nr_windows; k++) {
439 window = d->window + k;
441 if (address < window->phys)
444 if (address >= (window->phys + window->size))
447 address -= window->phys;
448 address += (unsigned long)window->virt;
453 /* no windows defined, register must be 1:1 mapped virt:phys */
457 static unsigned int __init intc_get_reg(struct intc_desc_int *d,
458 unsigned long address)
462 address = intc_phys_to_virt(d, address);
464 for (k = 0; k < d->nr_reg; k++) {
465 if (d->reg[k] == address)
473 static intc_enum __init intc_grp_id(struct intc_desc *desc,
476 struct intc_group *g = desc->hw.groups;
479 for (i = 0; g && enum_id && i < desc->hw.nr_groups; i++) {
480 g = desc->hw.groups + i;
482 for (j = 0; g->enum_ids[j]; j++) {
483 if (g->enum_ids[j] != enum_id)
493 static unsigned int __init _intc_mask_data(struct intc_desc *desc,
494 struct intc_desc_int *d,
496 unsigned int *reg_idx,
497 unsigned int *fld_idx)
499 struct intc_mask_reg *mr = desc->hw.mask_regs;
500 unsigned int fn, mode;
501 unsigned long reg_e, reg_d;
503 while (mr && enum_id && *reg_idx < desc->hw.nr_mask_regs) {
504 mr = desc->hw.mask_regs + *reg_idx;
506 for (; *fld_idx < ARRAY_SIZE(mr->enum_ids); (*fld_idx)++) {
507 if (mr->enum_ids[*fld_idx] != enum_id)
510 if (mr->set_reg && mr->clr_reg) {
511 fn = REG_FN_WRITE_BASE;
512 mode = MODE_DUAL_REG;
516 fn = REG_FN_MODIFY_BASE;
518 mode = MODE_ENABLE_REG;
522 mode = MODE_MASK_REG;
528 fn += (mr->reg_width >> 3) - 1;
529 return _INTC_MK(fn, mode,
530 intc_get_reg(d, reg_e),
531 intc_get_reg(d, reg_d),
533 (mr->reg_width - 1) - *fld_idx);
543 static unsigned int __init intc_mask_data(struct intc_desc *desc,
544 struct intc_desc_int *d,
545 intc_enum enum_id, int do_grps)
551 ret = _intc_mask_data(desc, d, enum_id, &i, &j);
556 return intc_mask_data(desc, d, intc_grp_id(desc, enum_id), 0);
561 static unsigned int __init _intc_prio_data(struct intc_desc *desc,
562 struct intc_desc_int *d,
564 unsigned int *reg_idx,
565 unsigned int *fld_idx)
567 struct intc_prio_reg *pr = desc->hw.prio_regs;
568 unsigned int fn, n, mode, bit;
569 unsigned long reg_e, reg_d;
571 while (pr && enum_id && *reg_idx < desc->hw.nr_prio_regs) {
572 pr = desc->hw.prio_regs + *reg_idx;
574 for (; *fld_idx < ARRAY_SIZE(pr->enum_ids); (*fld_idx)++) {
575 if (pr->enum_ids[*fld_idx] != enum_id)
578 if (pr->set_reg && pr->clr_reg) {
579 fn = REG_FN_WRITE_BASE;
580 mode = MODE_PCLR_REG;
584 fn = REG_FN_MODIFY_BASE;
585 mode = MODE_PRIO_REG;
592 fn += (pr->reg_width >> 3) - 1;
595 BUG_ON(n * pr->field_width > pr->reg_width);
597 bit = pr->reg_width - (n * pr->field_width);
599 return _INTC_MK(fn, mode,
600 intc_get_reg(d, reg_e),
601 intc_get_reg(d, reg_d),
602 pr->field_width, bit);
612 static unsigned int __init intc_prio_data(struct intc_desc *desc,
613 struct intc_desc_int *d,
614 intc_enum enum_id, int do_grps)
620 ret = _intc_prio_data(desc, d, enum_id, &i, &j);
625 return intc_prio_data(desc, d, intc_grp_id(desc, enum_id), 0);
630 static void __init intc_enable_disable_enum(struct intc_desc *desc,
631 struct intc_desc_int *d,
632 intc_enum enum_id, int enable)
634 unsigned int i, j, data;
636 /* go through and enable/disable all mask bits */
639 data = _intc_mask_data(desc, d, enum_id, &i, &j);
641 intc_enable_disable(d, data, enable);
645 /* go through and enable/disable all priority fields */
648 data = _intc_prio_data(desc, d, enum_id, &i, &j);
650 intc_enable_disable(d, data, enable);
656 static unsigned int __init intc_ack_data(struct intc_desc *desc,
657 struct intc_desc_int *d,
660 struct intc_mask_reg *mr = desc->hw.ack_regs;
661 unsigned int i, j, fn, mode;
662 unsigned long reg_e, reg_d;
664 for (i = 0; mr && enum_id && i < desc->hw.nr_ack_regs; i++) {
665 mr = desc->hw.ack_regs + i;
667 for (j = 0; j < ARRAY_SIZE(mr->enum_ids); j++) {
668 if (mr->enum_ids[j] != enum_id)
671 fn = REG_FN_MODIFY_BASE;
672 mode = MODE_ENABLE_REG;
676 fn += (mr->reg_width >> 3) - 1;
677 return _INTC_MK(fn, mode,
678 intc_get_reg(d, reg_e),
679 intc_get_reg(d, reg_d),
681 (mr->reg_width - 1) - j);
688 static unsigned int __init intc_sense_data(struct intc_desc *desc,
689 struct intc_desc_int *d,
692 struct intc_sense_reg *sr = desc->hw.sense_regs;
693 unsigned int i, j, fn, bit;
695 for (i = 0; sr && enum_id && i < desc->hw.nr_sense_regs; i++) {
696 sr = desc->hw.sense_regs + i;
698 for (j = 0; j < ARRAY_SIZE(sr->enum_ids); j++) {
699 if (sr->enum_ids[j] != enum_id)
702 fn = REG_FN_MODIFY_BASE;
703 fn += (sr->reg_width >> 3) - 1;
705 BUG_ON((j + 1) * sr->field_width > sr->reg_width);
707 bit = sr->reg_width - ((j + 1) * sr->field_width);
709 return _INTC_MK(fn, 0, intc_get_reg(d, sr->reg),
710 0, sr->field_width, bit);
717 static void __init intc_register_irq(struct intc_desc *desc,
718 struct intc_desc_int *d,
722 struct intc_handle_int *hp;
723 unsigned int data[2], primary;
726 * Register the IRQ position with the global IRQ map
728 set_bit(irq, intc_irq_map);
730 /* Prefer single interrupt source bitmap over other combinations:
731 * 1. bitmap, single interrupt source
732 * 2. priority, single interrupt source
733 * 3. bitmap, multiple interrupt sources (groups)
734 * 4. priority, multiple interrupt sources (groups)
737 data[0] = intc_mask_data(desc, d, enum_id, 0);
738 data[1] = intc_prio_data(desc, d, enum_id, 0);
741 if (!data[0] && data[1])
744 if (!data[0] && !data[1])
745 pr_warning("intc: missing unique irq mask for "
746 "irq %d (vect 0x%04x)\n", irq, irq2evt(irq));
748 data[0] = data[0] ? data[0] : intc_mask_data(desc, d, enum_id, 1);
749 data[1] = data[1] ? data[1] : intc_prio_data(desc, d, enum_id, 1);
754 BUG_ON(!data[primary]); /* must have primary masking method */
756 disable_irq_nosync(irq);
757 set_irq_chip_and_handler_name(irq, &d->chip,
758 handle_level_irq, "level");
759 set_irq_chip_data(irq, (void *)data[primary]);
761 /* set priority level
762 * - this needs to be at least 2 for 5-bit priorities on 7780
764 intc_prio_level[irq] = 2;
766 /* enable secondary masking method if present */
768 _intc_enable(irq, data[!primary]);
770 /* add irq to d->prio list if priority is available */
772 hp = d->prio + d->nr_prio;
774 hp->handle = data[1];
778 * only secondary priority should access registers, so
779 * set _INTC_FN(h) = REG_FN_ERR for intc_set_priority()
782 hp->handle &= ~_INTC_MK(0x0f, 0, 0, 0, 0, 0);
783 hp->handle |= _INTC_MK(REG_FN_ERR, 0, 0, 0, 0, 0);
788 /* add irq to d->sense list if sense is available */
789 data[0] = intc_sense_data(desc, d, enum_id);
791 (d->sense + d->nr_sense)->irq = irq;
792 (d->sense + d->nr_sense)->handle = data[0];
796 /* irq should be disabled by default */
799 if (desc->hw.ack_regs)
800 ack_handle[irq] = intc_ack_data(desc, d, enum_id);
803 set_irq_flags(irq, IRQF_VALID); /* Enable IRQ on ARM systems */
807 static unsigned int __init save_reg(struct intc_desc_int *d,
813 value = intc_phys_to_virt(d, value);
825 static void intc_redirect_irq(unsigned int irq, struct irq_desc *desc)
827 generic_handle_irq((unsigned int)get_irq_data(irq));
830 int __init register_intc_controller(struct intc_desc *desc)
832 unsigned int i, k, smp;
833 struct intc_hw_desc *hw = &desc->hw;
834 struct intc_desc_int *d;
835 struct resource *res;
837 d = kzalloc(sizeof(*d), GFP_NOWAIT);
841 INIT_LIST_HEAD(&d->list);
842 list_add(&d->list, &intc_list);
844 if (desc->num_resources) {
845 d->nr_windows = desc->num_resources;
846 d->window = kzalloc(d->nr_windows * sizeof(*d->window),
851 for (k = 0; k < d->nr_windows; k++) {
852 res = desc->resource + k;
853 WARN_ON(resource_type(res) != IORESOURCE_MEM);
854 d->window[k].phys = res->start;
855 d->window[k].size = resource_size(res);
856 d->window[k].virt = ioremap_nocache(res->start,
858 if (!d->window[k].virt)
863 d->nr_reg = hw->mask_regs ? hw->nr_mask_regs * 2 : 0;
864 d->nr_reg += hw->prio_regs ? hw->nr_prio_regs * 2 : 0;
865 d->nr_reg += hw->sense_regs ? hw->nr_sense_regs : 0;
866 d->nr_reg += hw->ack_regs ? hw->nr_ack_regs : 0;
868 d->reg = kzalloc(d->nr_reg * sizeof(*d->reg), GFP_NOWAIT);
873 d->smp = kzalloc(d->nr_reg * sizeof(*d->smp), GFP_NOWAIT);
880 for (i = 0; i < hw->nr_mask_regs; i++) {
881 smp = IS_SMP(hw->mask_regs[i]);
882 k += save_reg(d, k, hw->mask_regs[i].set_reg, smp);
883 k += save_reg(d, k, hw->mask_regs[i].clr_reg, smp);
888 d->prio = kzalloc(hw->nr_vectors * sizeof(*d->prio),
893 for (i = 0; i < hw->nr_prio_regs; i++) {
894 smp = IS_SMP(hw->prio_regs[i]);
895 k += save_reg(d, k, hw->prio_regs[i].set_reg, smp);
896 k += save_reg(d, k, hw->prio_regs[i].clr_reg, smp);
900 if (hw->sense_regs) {
901 d->sense = kzalloc(hw->nr_vectors * sizeof(*d->sense),
906 for (i = 0; i < hw->nr_sense_regs; i++)
907 k += save_reg(d, k, hw->sense_regs[i].reg, 0);
910 d->chip.name = desc->name;
911 d->chip.mask = intc_disable;
912 d->chip.unmask = intc_enable;
913 d->chip.mask_ack = intc_disable;
914 d->chip.enable = intc_enable;
915 d->chip.disable = intc_disable;
916 d->chip.shutdown = intc_disable;
917 d->chip.set_type = intc_set_sense;
918 d->chip.set_wake = intc_set_wake;
921 for (i = 0; i < hw->nr_ack_regs; i++)
922 k += save_reg(d, k, hw->ack_regs[i].set_reg, 0);
924 d->chip.mask_ack = intc_mask_ack;
927 /* disable bits matching force_disable before registering irqs */
928 if (desc->force_disable)
929 intc_enable_disable_enum(desc, d, desc->force_disable, 0);
931 /* disable bits matching force_enable before registering irqs */
932 if (desc->force_enable)
933 intc_enable_disable_enum(desc, d, desc->force_enable, 0);
935 BUG_ON(k > 256); /* _INTC_ADDR_E() and _INTC_ADDR_D() are 8 bits */
937 /* register the vectors one by one */
938 for (i = 0; i < hw->nr_vectors; i++) {
939 struct intc_vect *vect = hw->vectors + i;
940 unsigned int irq = evt2irq(vect->vect);
941 struct irq_desc *irq_desc;
946 irq_desc = irq_to_desc_alloc_node(irq, numa_node_id());
947 if (unlikely(!irq_desc)) {
948 pr_info("can't get irq_desc for %d\n", irq);
952 intc_register_irq(desc, d, vect->enum_id, irq);
954 for (k = i + 1; k < hw->nr_vectors; k++) {
955 struct intc_vect *vect2 = hw->vectors + k;
956 unsigned int irq2 = evt2irq(vect2->vect);
958 if (vect->enum_id != vect2->enum_id)
962 * In the case of multi-evt handling and sparse
963 * IRQ support, each vector still needs to have
964 * its own backing irq_desc.
966 irq_desc = irq_to_desc_alloc_node(irq2, numa_node_id());
967 if (unlikely(!irq_desc)) {
968 pr_info("can't get irq_desc for %d\n", irq2);
974 /* redirect this interrupts to the first one */
975 set_irq_chip(irq2, &dummy_irq_chip);
976 set_irq_chained_handler(irq2, intc_redirect_irq);
977 set_irq_data(irq2, (void *)irq);
981 /* enable bits matching force_enable after registering irqs */
982 if (desc->force_enable)
983 intc_enable_disable_enum(desc, d, desc->force_enable, 1);
995 for (k = 0; k < d->nr_windows; k++)
996 if (d->window[k].virt)
997 iounmap(d->window[k].virt);
1003 pr_err("unable to allocate INTC memory\n");
1008 static int intc_suspend(struct sys_device *dev, pm_message_t state)
1010 struct intc_desc_int *d;
1011 struct irq_desc *desc;
1014 /* get intc controller associated with this sysdev */
1015 d = container_of(dev, struct intc_desc_int, sysdev);
1017 switch (state.event) {
1019 if (d->state.event != PM_EVENT_FREEZE)
1021 for_each_irq_desc(irq, desc) {
1022 if (desc->handle_irq == intc_redirect_irq)
1024 if (desc->chip != &d->chip)
1026 if (desc->status & IRQ_DISABLED)
1032 case PM_EVENT_FREEZE:
1033 /* nothing has to be done */
1035 case PM_EVENT_SUSPEND:
1036 /* enable wakeup irqs belonging to this intc controller */
1037 for_each_irq_desc(irq, desc) {
1038 if ((desc->status & IRQ_WAKEUP) && (desc->chip == &d->chip))
1048 static int intc_resume(struct sys_device *dev)
1050 return intc_suspend(dev, PMSG_ON);
1053 static struct sysdev_class intc_sysdev_class = {
1055 .suspend = intc_suspend,
1056 .resume = intc_resume,
1059 /* register this intc as sysdev to allow suspend/resume */
1060 static int __init register_intc_sysdevs(void)
1062 struct intc_desc_int *d;
1066 error = sysdev_class_register(&intc_sysdev_class);
1068 list_for_each_entry(d, &intc_list, list) {
1070 d->sysdev.cls = &intc_sysdev_class;
1071 error = sysdev_register(&d->sysdev);
1079 pr_warning("intc: sysdev registration error\n");
1083 device_initcall(register_intc_sysdevs);
1086 * Dynamic IRQ allocation and deallocation
1088 unsigned int create_irq_nr(unsigned int irq_want, int node)
1090 unsigned int irq = 0, new;
1091 unsigned long flags;
1092 struct irq_desc *desc;
1094 spin_lock_irqsave(&vector_lock, flags);
1097 * First try the wanted IRQ
1099 if (test_and_set_bit(irq_want, intc_irq_map) == 0) {
1102 /* .. then fall back to scanning. */
1103 new = find_first_zero_bit(intc_irq_map, nr_irqs);
1104 if (unlikely(new == nr_irqs))
1107 __set_bit(new, intc_irq_map);
1110 desc = irq_to_desc_alloc_node(new, node);
1111 if (unlikely(!desc)) {
1112 pr_info("can't get irq_desc for %d\n", new);
1116 desc = move_irq_desc(desc, node);
1120 spin_unlock_irqrestore(&vector_lock, flags);
1123 dynamic_irq_init(irq);
1125 set_irq_flags(irq, IRQF_VALID); /* Enable IRQ on ARM systems */
1132 int create_irq(void)
1134 int nid = cpu_to_node(smp_processor_id());
1137 irq = create_irq_nr(NR_IRQS_LEGACY, nid);
1144 void destroy_irq(unsigned int irq)
1146 unsigned long flags;
1148 dynamic_irq_cleanup(irq);
1150 spin_lock_irqsave(&vector_lock, flags);
1151 __clear_bit(irq, intc_irq_map);
1152 spin_unlock_irqrestore(&vector_lock, flags);
1155 int reserve_irq_vector(unsigned int irq)
1157 unsigned long flags;
1160 spin_lock_irqsave(&vector_lock, flags);
1161 if (test_and_set_bit(irq, intc_irq_map))
1163 spin_unlock_irqrestore(&vector_lock, flags);
1168 void reserve_irq_legacy(void)
1170 unsigned long flags;
1173 spin_lock_irqsave(&vector_lock, flags);
1174 j = find_first_bit(intc_irq_map, nr_irqs);
1175 for (i = 0; i < j; i++)
1176 __set_bit(i, intc_irq_map);
1177 spin_unlock_irqrestore(&vector_lock, flags);