2 * Copyright (C) 2009 Texas Instruments.
3 * Copyright (C) 2010 EF Johnson Technologies
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 #include <linux/interrupt.h>
22 #include <linux/gpio.h>
23 #include <linux/module.h>
24 #include <linux/delay.h>
25 #include <linux/platform_device.h>
26 #include <linux/err.h>
27 #include <linux/clk.h>
28 #include <linux/dmaengine.h>
29 #include <linux/dma-mapping.h>
30 #include <linux/edma.h>
32 #include <linux/of_device.h>
33 #include <linux/of_gpio.h>
34 #include <linux/spi/spi.h>
35 #include <linux/spi/spi_bitbang.h>
36 #include <linux/slab.h>
38 #include <linux/platform_data/spi-davinci.h>
40 #define SPI_NO_RESOURCE ((resource_size_t)-1)
42 #define CS_DEFAULT 0xFF
44 #define SPIFMT_PHASE_MASK BIT(16)
45 #define SPIFMT_POLARITY_MASK BIT(17)
46 #define SPIFMT_DISTIMER_MASK BIT(18)
47 #define SPIFMT_SHIFTDIR_MASK BIT(20)
48 #define SPIFMT_WAITENA_MASK BIT(21)
49 #define SPIFMT_PARITYENA_MASK BIT(22)
50 #define SPIFMT_ODD_PARITY_MASK BIT(23)
51 #define SPIFMT_WDELAY_MASK 0x3f000000u
52 #define SPIFMT_WDELAY_SHIFT 24
53 #define SPIFMT_PRESCALE_SHIFT 8
56 #define SPIPC0_DIFUN_MASK BIT(11) /* MISO */
57 #define SPIPC0_DOFUN_MASK BIT(10) /* MOSI */
58 #define SPIPC0_CLKFUN_MASK BIT(9) /* CLK */
59 #define SPIPC0_SPIENA_MASK BIT(8) /* nREADY */
61 #define SPIINT_MASKALL 0x0101035F
62 #define SPIINT_MASKINT 0x0000015F
63 #define SPI_INTLVL_1 0x000001FF
64 #define SPI_INTLVL_0 0x00000000
66 /* SPIDAT1 (upper 16 bit defines) */
67 #define SPIDAT1_CSHOLD_MASK BIT(12)
70 #define SPIGCR1_CLKMOD_MASK BIT(1)
71 #define SPIGCR1_MASTER_MASK BIT(0)
72 #define SPIGCR1_POWERDOWN_MASK BIT(8)
73 #define SPIGCR1_LOOPBACK_MASK BIT(16)
74 #define SPIGCR1_SPIENA_MASK BIT(24)
77 #define SPIBUF_TXFULL_MASK BIT(29)
78 #define SPIBUF_RXEMPTY_MASK BIT(31)
81 #define SPIDELAY_C2TDELAY_SHIFT 24
82 #define SPIDELAY_C2TDELAY_MASK (0xFF << SPIDELAY_C2TDELAY_SHIFT)
83 #define SPIDELAY_T2CDELAY_SHIFT 16
84 #define SPIDELAY_T2CDELAY_MASK (0xFF << SPIDELAY_T2CDELAY_SHIFT)
85 #define SPIDELAY_T2EDELAY_SHIFT 8
86 #define SPIDELAY_T2EDELAY_MASK (0xFF << SPIDELAY_T2EDELAY_SHIFT)
87 #define SPIDELAY_C2EDELAY_SHIFT 0
88 #define SPIDELAY_C2EDELAY_MASK 0xFF
91 #define SPIFLG_DLEN_ERR_MASK BIT(0)
92 #define SPIFLG_TIMEOUT_MASK BIT(1)
93 #define SPIFLG_PARERR_MASK BIT(2)
94 #define SPIFLG_DESYNC_MASK BIT(3)
95 #define SPIFLG_BITERR_MASK BIT(4)
96 #define SPIFLG_OVRRUN_MASK BIT(6)
97 #define SPIFLG_BUF_INIT_ACTIVE_MASK BIT(24)
98 #define SPIFLG_ERROR_MASK (SPIFLG_DLEN_ERR_MASK \
99 | SPIFLG_TIMEOUT_MASK | SPIFLG_PARERR_MASK \
100 | SPIFLG_DESYNC_MASK | SPIFLG_BITERR_MASK \
101 | SPIFLG_OVRRUN_MASK)
103 #define SPIINT_DMA_REQ_EN BIT(16)
105 /* SPI Controller registers */
114 #define SPIDELAY 0x48
118 /* SPI Controller driver's private data. */
120 struct spi_bitbang bitbang;
124 resource_size_t pbase;
127 struct completion done;
134 struct dma_chan *dma_rx;
135 struct dma_chan *dma_tx;
139 struct davinci_spi_platform_data pdata;
141 void (*get_rx)(u32 rx_data, struct davinci_spi *);
142 u32 (*get_tx)(struct davinci_spi *);
147 static struct davinci_spi_config davinci_spi_default_cfg;
149 static void davinci_spi_rx_buf_u8(u32 data, struct davinci_spi *dspi)
158 static void davinci_spi_rx_buf_u16(u32 data, struct davinci_spi *dspi)
167 static u32 davinci_spi_tx_buf_u8(struct davinci_spi *dspi)
171 const u8 *tx = dspi->tx;
178 static u32 davinci_spi_tx_buf_u16(struct davinci_spi *dspi)
182 const u16 *tx = dspi->tx;
189 static inline void set_io_bits(void __iomem *addr, u32 bits)
191 u32 v = ioread32(addr);
197 static inline void clear_io_bits(void __iomem *addr, u32 bits)
199 u32 v = ioread32(addr);
206 * Interface to control the chip select signal
208 static void davinci_spi_chipselect(struct spi_device *spi, int value)
210 struct davinci_spi *dspi;
211 struct davinci_spi_platform_data *pdata;
212 u8 chip_sel = spi->chip_select;
213 u16 spidat1 = CS_DEFAULT;
214 bool gpio_chipsel = false;
217 dspi = spi_master_get_devdata(spi->master);
218 pdata = &dspi->pdata;
220 if (spi->cs_gpio >= 0) {
221 /* SPI core parse and update master->cs_gpio */
227 * Board specific chip select logic decides the polarity and cs
228 * line for the controller
231 if (value == BITBANG_CS_ACTIVE)
232 gpio_set_value(gpio, spi->mode & SPI_CS_HIGH);
234 gpio_set_value(gpio, !(spi->mode & SPI_CS_HIGH));
236 if (value == BITBANG_CS_ACTIVE) {
237 spidat1 |= SPIDAT1_CSHOLD_MASK;
238 spidat1 &= ~(0x1 << chip_sel);
241 iowrite16(spidat1, dspi->base + SPIDAT1 + 2);
246 * davinci_spi_get_prescale - Calculates the correct prescale value
247 * @maxspeed_hz: the maximum rate the SPI clock can run at
249 * This function calculates the prescale value that generates a clock rate
250 * less than or equal to the specified maximum.
252 * Returns: calculated prescale - 1 for easy programming into SPI registers
253 * or negative error number if valid prescalar cannot be updated.
255 static inline int davinci_spi_get_prescale(struct davinci_spi *dspi,
260 ret = DIV_ROUND_UP(clk_get_rate(dspi->clk), max_speed_hz);
262 if (ret < 3 || ret > 256)
269 * davinci_spi_setup_transfer - This functions will determine transfer method
270 * @spi: spi device on which data transfer to be done
271 * @t: spi transfer in which transfer info is filled
273 * This function determines data transfer method (8/16/32 bit transfer).
274 * It will also set the SPI Clock Control register according to
275 * SPI slave device freq.
277 static int davinci_spi_setup_transfer(struct spi_device *spi,
278 struct spi_transfer *t)
281 struct davinci_spi *dspi;
282 struct davinci_spi_config *spicfg;
283 u8 bits_per_word = 0;
284 u32 hz = 0, spifmt = 0;
287 dspi = spi_master_get_devdata(spi->master);
288 spicfg = (struct davinci_spi_config *)spi->controller_data;
290 spicfg = &davinci_spi_default_cfg;
293 bits_per_word = t->bits_per_word;
297 /* if bits_per_word is not set then set it default */
299 bits_per_word = spi->bits_per_word;
302 * Assign function pointer to appropriate transfer method
303 * 8bit, 16bit or 32bit transfer
305 if (bits_per_word <= 8) {
306 dspi->get_rx = davinci_spi_rx_buf_u8;
307 dspi->get_tx = davinci_spi_tx_buf_u8;
308 dspi->bytes_per_word[spi->chip_select] = 1;
310 dspi->get_rx = davinci_spi_rx_buf_u16;
311 dspi->get_tx = davinci_spi_tx_buf_u16;
312 dspi->bytes_per_word[spi->chip_select] = 2;
316 hz = spi->max_speed_hz;
318 /* Set up SPIFMTn register, unique to this chipselect. */
320 prescale = davinci_spi_get_prescale(dspi, hz);
324 spifmt = (prescale << SPIFMT_PRESCALE_SHIFT) | (bits_per_word & 0x1f);
326 if (spi->mode & SPI_LSB_FIRST)
327 spifmt |= SPIFMT_SHIFTDIR_MASK;
329 if (spi->mode & SPI_CPOL)
330 spifmt |= SPIFMT_POLARITY_MASK;
332 if (!(spi->mode & SPI_CPHA))
333 spifmt |= SPIFMT_PHASE_MASK;
336 * Version 1 hardware supports two basic SPI modes:
337 * - Standard SPI mode uses 4 pins, with chipselect
338 * - 3 pin SPI is a 4 pin variant without CS (SPI_NO_CS)
339 * (distinct from SPI_3WIRE, with just one data wire;
340 * or similar variants without MOSI or without MISO)
342 * Version 2 hardware supports an optional handshaking signal,
343 * so it can support two more modes:
344 * - 5 pin SPI variant is standard SPI plus SPI_READY
345 * - 4 pin with enable is (SPI_READY | SPI_NO_CS)
348 if (dspi->version == SPI_VERSION_2) {
352 spifmt |= ((spicfg->wdelay << SPIFMT_WDELAY_SHIFT)
353 & SPIFMT_WDELAY_MASK);
355 if (spicfg->odd_parity)
356 spifmt |= SPIFMT_ODD_PARITY_MASK;
358 if (spicfg->parity_enable)
359 spifmt |= SPIFMT_PARITYENA_MASK;
361 if (spicfg->timer_disable) {
362 spifmt |= SPIFMT_DISTIMER_MASK;
364 delay |= (spicfg->c2tdelay << SPIDELAY_C2TDELAY_SHIFT)
365 & SPIDELAY_C2TDELAY_MASK;
366 delay |= (spicfg->t2cdelay << SPIDELAY_T2CDELAY_SHIFT)
367 & SPIDELAY_T2CDELAY_MASK;
370 if (spi->mode & SPI_READY) {
371 spifmt |= SPIFMT_WAITENA_MASK;
372 delay |= (spicfg->t2edelay << SPIDELAY_T2EDELAY_SHIFT)
373 & SPIDELAY_T2EDELAY_MASK;
374 delay |= (spicfg->c2edelay << SPIDELAY_C2EDELAY_SHIFT)
375 & SPIDELAY_C2EDELAY_MASK;
378 iowrite32(delay, dspi->base + SPIDELAY);
381 iowrite32(spifmt, dspi->base + SPIFMT0);
387 * davinci_spi_setup - This functions will set default transfer method
388 * @spi: spi device on which data transfer to be done
390 * This functions sets the default transfer method.
392 static int davinci_spi_setup(struct spi_device *spi)
395 struct davinci_spi *dspi;
396 struct davinci_spi_platform_data *pdata;
397 struct spi_master *master = spi->master;
398 struct device_node *np = spi->dev.of_node;
399 bool internal_cs = true;
401 dspi = spi_master_get_devdata(spi->master);
402 pdata = &dspi->pdata;
404 if (!(spi->mode & SPI_NO_CS)) {
405 if (np && (master->cs_gpios != NULL) && (spi->cs_gpio >= 0)) {
406 retval = gpio_direction_output(
407 spi->cs_gpio, !(spi->mode & SPI_CS_HIGH));
409 } else if (pdata->chip_sel &&
410 spi->chip_select < pdata->num_chipselect &&
411 pdata->chip_sel[spi->chip_select] != SPI_INTERN_CS) {
412 spi->cs_gpio = pdata->chip_sel[spi->chip_select];
413 retval = gpio_direction_output(
414 spi->cs_gpio, !(spi->mode & SPI_CS_HIGH));
419 dev_err(&spi->dev, "GPIO %d setup failed (%d)\n",
420 spi->cs_gpio, retval);
425 set_io_bits(dspi->base + SPIPC0, 1 << spi->chip_select);
428 if (spi->mode & SPI_READY)
429 set_io_bits(dspi->base + SPIPC0, SPIPC0_SPIENA_MASK);
431 if (spi->mode & SPI_LOOP)
432 set_io_bits(dspi->base + SPIGCR1, SPIGCR1_LOOPBACK_MASK);
434 clear_io_bits(dspi->base + SPIGCR1, SPIGCR1_LOOPBACK_MASK);
439 static int davinci_spi_check_error(struct davinci_spi *dspi, int int_status)
441 struct device *sdev = dspi->bitbang.master->dev.parent;
443 if (int_status & SPIFLG_TIMEOUT_MASK) {
444 dev_dbg(sdev, "SPI Time-out Error\n");
447 if (int_status & SPIFLG_DESYNC_MASK) {
448 dev_dbg(sdev, "SPI Desynchronization Error\n");
451 if (int_status & SPIFLG_BITERR_MASK) {
452 dev_dbg(sdev, "SPI Bit error\n");
456 if (dspi->version == SPI_VERSION_2) {
457 if (int_status & SPIFLG_DLEN_ERR_MASK) {
458 dev_dbg(sdev, "SPI Data Length Error\n");
461 if (int_status & SPIFLG_PARERR_MASK) {
462 dev_dbg(sdev, "SPI Parity Error\n");
465 if (int_status & SPIFLG_OVRRUN_MASK) {
466 dev_dbg(sdev, "SPI Data Overrun error\n");
469 if (int_status & SPIFLG_BUF_INIT_ACTIVE_MASK) {
470 dev_dbg(sdev, "SPI Buffer Init Active\n");
479 * davinci_spi_process_events - check for and handle any SPI controller events
480 * @dspi: the controller data
482 * This function will check the SPIFLG register and handle any events that are
485 static int davinci_spi_process_events(struct davinci_spi *dspi)
487 u32 buf, status, errors = 0, spidat1;
489 buf = ioread32(dspi->base + SPIBUF);
491 if (dspi->rcount > 0 && !(buf & SPIBUF_RXEMPTY_MASK)) {
492 dspi->get_rx(buf & 0xFFFF, dspi);
496 status = ioread32(dspi->base + SPIFLG);
498 if (unlikely(status & SPIFLG_ERROR_MASK)) {
499 errors = status & SPIFLG_ERROR_MASK;
503 if (dspi->wcount > 0 && !(buf & SPIBUF_TXFULL_MASK)) {
504 spidat1 = ioread32(dspi->base + SPIDAT1);
507 spidat1 |= 0xFFFF & dspi->get_tx(dspi);
508 iowrite32(spidat1, dspi->base + SPIDAT1);
515 static void davinci_spi_dma_rx_callback(void *data)
517 struct davinci_spi *dspi = (struct davinci_spi *)data;
521 if (!dspi->wcount && !dspi->rcount)
522 complete(&dspi->done);
525 static void davinci_spi_dma_tx_callback(void *data)
527 struct davinci_spi *dspi = (struct davinci_spi *)data;
531 if (!dspi->wcount && !dspi->rcount)
532 complete(&dspi->done);
536 * davinci_spi_bufs - functions which will handle transfer data
537 * @spi: spi device on which data transfer to be done
538 * @t: spi transfer in which transfer info is filled
540 * This function will put data to be transferred into data register
541 * of SPI controller and then wait until the completion will be marked
542 * by the IRQ Handler.
544 static int davinci_spi_bufs(struct spi_device *spi, struct spi_transfer *t)
546 struct davinci_spi *dspi;
547 int data_type, ret = -ENOMEM;
548 u32 tx_data, spidat1;
550 struct davinci_spi_config *spicfg;
551 struct davinci_spi_platform_data *pdata;
552 unsigned uninitialized_var(rx_buf_count);
553 void *dummy_buf = NULL;
554 struct scatterlist sg_rx, sg_tx;
556 dspi = spi_master_get_devdata(spi->master);
557 pdata = &dspi->pdata;
558 spicfg = (struct davinci_spi_config *)spi->controller_data;
560 spicfg = &davinci_spi_default_cfg;
562 /* convert len to words based on bits_per_word */
563 data_type = dspi->bytes_per_word[spi->chip_select];
565 dspi->tx = t->tx_buf;
566 dspi->rx = t->rx_buf;
567 dspi->wcount = t->len / data_type;
568 dspi->rcount = dspi->wcount;
570 spidat1 = ioread32(dspi->base + SPIDAT1);
572 clear_io_bits(dspi->base + SPIGCR1, SPIGCR1_POWERDOWN_MASK);
573 set_io_bits(dspi->base + SPIGCR1, SPIGCR1_SPIENA_MASK);
575 reinit_completion(&dspi->done);
577 if (spicfg->io_type == SPI_IO_TYPE_INTR)
578 set_io_bits(dspi->base + SPIINT, SPIINT_MASKINT);
580 if (spicfg->io_type != SPI_IO_TYPE_DMA) {
581 /* start the transfer */
583 tx_data = dspi->get_tx(dspi);
584 spidat1 &= 0xFFFF0000;
585 spidat1 |= tx_data & 0xFFFF;
586 iowrite32(spidat1, dspi->base + SPIDAT1);
588 struct dma_slave_config dma_rx_conf = {
589 .direction = DMA_DEV_TO_MEM,
590 .src_addr = (unsigned long)dspi->pbase + SPIBUF,
591 .src_addr_width = data_type,
594 struct dma_slave_config dma_tx_conf = {
595 .direction = DMA_MEM_TO_DEV,
596 .dst_addr = (unsigned long)dspi->pbase + SPIDAT1,
597 .dst_addr_width = data_type,
600 struct dma_async_tx_descriptor *rxdesc;
601 struct dma_async_tx_descriptor *txdesc;
604 dummy_buf = kzalloc(t->len, GFP_KERNEL);
606 goto err_alloc_dummy_buf;
608 dmaengine_slave_config(dspi->dma_rx, &dma_rx_conf);
609 dmaengine_slave_config(dspi->dma_tx, &dma_tx_conf);
611 sg_init_table(&sg_rx, 1);
616 t->rx_dma = dma_map_single(&spi->dev, buf,
617 t->len, DMA_FROM_DEVICE);
622 sg_dma_address(&sg_rx) = t->rx_dma;
623 sg_dma_len(&sg_rx) = t->len;
625 sg_init_table(&sg_tx, 1);
629 buf = (void *)t->tx_buf;
630 t->tx_dma = dma_map_single(&spi->dev, buf,
631 t->len, DMA_TO_DEVICE);
636 sg_dma_address(&sg_tx) = t->tx_dma;
637 sg_dma_len(&sg_tx) = t->len;
639 rxdesc = dmaengine_prep_slave_sg(dspi->dma_rx,
640 &sg_rx, 1, DMA_DEV_TO_MEM,
641 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
645 txdesc = dmaengine_prep_slave_sg(dspi->dma_tx,
646 &sg_tx, 1, DMA_MEM_TO_DEV,
647 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
651 rxdesc->callback = davinci_spi_dma_rx_callback;
652 rxdesc->callback_param = (void *)dspi;
653 txdesc->callback = davinci_spi_dma_tx_callback;
654 txdesc->callback_param = (void *)dspi;
656 if (pdata->cshold_bug)
657 iowrite16(spidat1 >> 16, dspi->base + SPIDAT1 + 2);
659 dmaengine_submit(rxdesc);
660 dmaengine_submit(txdesc);
662 dma_async_issue_pending(dspi->dma_rx);
663 dma_async_issue_pending(dspi->dma_tx);
665 set_io_bits(dspi->base + SPIINT, SPIINT_DMA_REQ_EN);
668 /* Wait for the transfer to complete */
669 if (spicfg->io_type != SPI_IO_TYPE_POLL) {
670 wait_for_completion_interruptible(&(dspi->done));
672 while (dspi->rcount > 0 || dspi->wcount > 0) {
673 errors = davinci_spi_process_events(dspi);
680 clear_io_bits(dspi->base + SPIINT, SPIINT_MASKALL);
681 if (spicfg->io_type == SPI_IO_TYPE_DMA) {
682 clear_io_bits(dspi->base + SPIINT, SPIINT_DMA_REQ_EN);
684 dma_unmap_single(&spi->dev, t->rx_dma,
685 t->len, DMA_FROM_DEVICE);
686 dma_unmap_single(&spi->dev, t->tx_dma,
687 t->len, DMA_TO_DEVICE);
691 clear_io_bits(dspi->base + SPIGCR1, SPIGCR1_SPIENA_MASK);
692 set_io_bits(dspi->base + SPIGCR1, SPIGCR1_POWERDOWN_MASK);
695 * Check for bit error, desync error,parity error,timeout error and
696 * receive overflow errors
699 ret = davinci_spi_check_error(dspi, errors);
700 WARN(!ret, "%s: error reported but no error found!\n",
701 dev_name(&spi->dev));
705 if (dspi->rcount != 0 || dspi->wcount != 0) {
706 dev_err(&spi->dev, "SPI data transfer error\n");
713 dma_unmap_single(&spi->dev, t->tx_dma, t->len, DMA_TO_DEVICE);
715 dma_unmap_single(&spi->dev, t->rx_dma, t->len, DMA_FROM_DEVICE);
723 * dummy_thread_fn - dummy thread function
724 * @irq: IRQ number for this SPI Master
725 * @context_data: structure for SPI Master controller davinci_spi
727 * This is to satisfy the request_threaded_irq() API so that the irq
728 * handler is called in interrupt context.
730 static irqreturn_t dummy_thread_fn(s32 irq, void *data)
736 * davinci_spi_irq - Interrupt handler for SPI Master Controller
737 * @irq: IRQ number for this SPI Master
738 * @context_data: structure for SPI Master controller davinci_spi
740 * ISR will determine that interrupt arrives either for READ or WRITE command.
741 * According to command it will do the appropriate action. It will check
742 * transfer length and if it is not zero then dispatch transfer command again.
743 * If transfer length is zero then it will indicate the COMPLETION so that
744 * davinci_spi_bufs function can go ahead.
746 static irqreturn_t davinci_spi_irq(s32 irq, void *data)
748 struct davinci_spi *dspi = data;
751 status = davinci_spi_process_events(dspi);
752 if (unlikely(status != 0))
753 clear_io_bits(dspi->base + SPIINT, SPIINT_MASKINT);
755 if ((!dspi->rcount && !dspi->wcount) || status)
756 complete(&dspi->done);
761 static int davinci_spi_request_dma(struct davinci_spi *dspi)
764 struct device *sdev = dspi->bitbang.master->dev.parent;
768 dma_cap_set(DMA_SLAVE, mask);
770 dspi->dma_rx = dma_request_channel(mask, edma_filter_fn,
771 &dspi->dma_rx_chnum);
773 dev_err(sdev, "request RX DMA channel failed\n");
778 dspi->dma_tx = dma_request_channel(mask, edma_filter_fn,
779 &dspi->dma_tx_chnum);
781 dev_err(sdev, "request TX DMA channel failed\n");
789 dma_release_channel(dspi->dma_rx);
794 #if defined(CONFIG_OF)
795 static const struct of_device_id davinci_spi_of_match[] = {
797 .compatible = "ti,dm6441-spi",
800 .compatible = "ti,da830-spi",
801 .data = (void *)SPI_VERSION_2,
805 MODULE_DEVICE_TABLE(of, davinci_spi_of_match);
808 * spi_davinci_get_pdata - Get platform data from DTS binding
809 * @pdev: ptr to platform data
810 * @dspi: ptr to driver data
812 * Parses and populates pdata in dspi from device tree bindings.
814 * NOTE: Not all platform data params are supported currently.
816 static int spi_davinci_get_pdata(struct platform_device *pdev,
817 struct davinci_spi *dspi)
819 struct device_node *node = pdev->dev.of_node;
820 struct davinci_spi_platform_data *pdata;
821 unsigned int num_cs, intr_line = 0;
822 const struct of_device_id *match;
824 pdata = &dspi->pdata;
826 pdata->version = SPI_VERSION_1;
827 match = of_match_device(davinci_spi_of_match, &pdev->dev);
831 /* match data has the SPI version number for SPI_VERSION_2 */
832 if (match->data == (void *)SPI_VERSION_2)
833 pdata->version = SPI_VERSION_2;
836 * default num_cs is 1 and all chipsel are internal to the chip
837 * indicated by chip_sel being NULL or cs_gpios being NULL or
838 * set to -ENOENT. num-cs includes internal as well as gpios.
839 * indicated by chip_sel being NULL. GPIO based CS is not
840 * supported yet in DT bindings.
843 of_property_read_u32(node, "num-cs", &num_cs);
844 pdata->num_chipselect = num_cs;
845 of_property_read_u32(node, "ti,davinci-spi-intr-line", &intr_line);
846 pdata->intr_line = intr_line;
850 static struct davinci_spi_platform_data
851 *spi_davinci_get_pdata(struct platform_device *pdev,
852 struct davinci_spi *dspi)
859 * davinci_spi_probe - probe function for SPI Master Controller
860 * @pdev: platform_device structure which contains plateform specific data
862 * According to Linux Device Model this function will be invoked by Linux
863 * with platform_device struct which contains the device specific info.
864 * This function will map the SPI controller's memory, register IRQ,
865 * Reset SPI controller and setting its registers to default value.
866 * It will invoke spi_bitbang_start to create work queue so that client driver
867 * can register transfer method to work queue.
869 static int davinci_spi_probe(struct platform_device *pdev)
871 struct spi_master *master;
872 struct davinci_spi *dspi;
873 struct davinci_spi_platform_data *pdata;
875 resource_size_t dma_rx_chan = SPI_NO_RESOURCE;
876 resource_size_t dma_tx_chan = SPI_NO_RESOURCE;
880 master = spi_alloc_master(&pdev->dev, sizeof(struct davinci_spi));
881 if (master == NULL) {
886 platform_set_drvdata(pdev, master);
888 dspi = spi_master_get_devdata(master);
890 if (dev_get_platdata(&pdev->dev)) {
891 pdata = dev_get_platdata(&pdev->dev);
892 dspi->pdata = *pdata;
894 /* update dspi pdata with that from the DT */
895 ret = spi_davinci_get_pdata(pdev, dspi);
900 /* pdata in dspi is now updated and point pdata to that */
901 pdata = &dspi->pdata;
903 dspi->bytes_per_word = devm_kzalloc(&pdev->dev,
904 sizeof(*dspi->bytes_per_word) *
905 pdata->num_chipselect, GFP_KERNEL);
906 if (dspi->bytes_per_word == NULL) {
911 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
917 dspi->pbase = r->start;
919 dspi->base = devm_ioremap_resource(&pdev->dev, r);
920 if (IS_ERR(dspi->base)) {
921 ret = PTR_ERR(dspi->base);
925 dspi->irq = platform_get_irq(pdev, 0);
926 if (dspi->irq <= 0) {
931 ret = devm_request_threaded_irq(&pdev->dev, dspi->irq, davinci_spi_irq,
932 dummy_thread_fn, 0, dev_name(&pdev->dev), dspi);
936 dspi->bitbang.master = master;
938 dspi->clk = devm_clk_get(&pdev->dev, NULL);
939 if (IS_ERR(dspi->clk)) {
943 clk_prepare_enable(dspi->clk);
945 master->dev.of_node = pdev->dev.of_node;
946 master->bus_num = pdev->id;
947 master->num_chipselect = pdata->num_chipselect;
948 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(2, 16);
949 master->setup = davinci_spi_setup;
951 dspi->bitbang.chipselect = davinci_spi_chipselect;
952 dspi->bitbang.setup_transfer = davinci_spi_setup_transfer;
954 dspi->version = pdata->version;
956 dspi->bitbang.flags = SPI_NO_CS | SPI_LSB_FIRST | SPI_LOOP;
957 if (dspi->version == SPI_VERSION_2)
958 dspi->bitbang.flags |= SPI_READY;
960 if (pdev->dev.of_node) {
963 for (i = 0; i < pdata->num_chipselect; i++) {
964 int cs_gpio = of_get_named_gpio(pdev->dev.of_node,
967 if (cs_gpio == -EPROBE_DEFER) {
972 if (gpio_is_valid(cs_gpio)) {
973 ret = devm_gpio_request(&pdev->dev, cs_gpio,
974 dev_name(&pdev->dev));
981 r = platform_get_resource(pdev, IORESOURCE_DMA, 0);
983 dma_rx_chan = r->start;
984 r = platform_get_resource(pdev, IORESOURCE_DMA, 1);
986 dma_tx_chan = r->start;
988 dspi->bitbang.txrx_bufs = davinci_spi_bufs;
989 if (dma_rx_chan != SPI_NO_RESOURCE &&
990 dma_tx_chan != SPI_NO_RESOURCE) {
991 dspi->dma_rx_chnum = dma_rx_chan;
992 dspi->dma_tx_chnum = dma_tx_chan;
994 ret = davinci_spi_request_dma(dspi);
998 dev_info(&pdev->dev, "DMA: supported\n");
999 dev_info(&pdev->dev, "DMA: RX channel: %pa, TX channel: %pa, "
1000 "event queue: %d\n", &dma_rx_chan, &dma_tx_chan,
1001 pdata->dma_event_q);
1004 dspi->get_rx = davinci_spi_rx_buf_u8;
1005 dspi->get_tx = davinci_spi_tx_buf_u8;
1007 init_completion(&dspi->done);
1009 /* Reset In/OUT SPI module */
1010 iowrite32(0, dspi->base + SPIGCR0);
1012 iowrite32(1, dspi->base + SPIGCR0);
1014 /* Set up SPIPC0. CS and ENA init is done in davinci_spi_setup */
1015 spipc0 = SPIPC0_DIFUN_MASK | SPIPC0_DOFUN_MASK | SPIPC0_CLKFUN_MASK;
1016 iowrite32(spipc0, dspi->base + SPIPC0);
1018 if (pdata->intr_line)
1019 iowrite32(SPI_INTLVL_1, dspi->base + SPILVL);
1021 iowrite32(SPI_INTLVL_0, dspi->base + SPILVL);
1023 iowrite32(CS_DEFAULT, dspi->base + SPIDEF);
1025 /* master mode default */
1026 set_io_bits(dspi->base + SPIGCR1, SPIGCR1_CLKMOD_MASK);
1027 set_io_bits(dspi->base + SPIGCR1, SPIGCR1_MASTER_MASK);
1028 set_io_bits(dspi->base + SPIGCR1, SPIGCR1_POWERDOWN_MASK);
1030 ret = spi_bitbang_start(&dspi->bitbang);
1034 dev_info(&pdev->dev, "Controller at 0x%p\n", dspi->base);
1039 dma_release_channel(dspi->dma_rx);
1040 dma_release_channel(dspi->dma_tx);
1042 clk_disable_unprepare(dspi->clk);
1044 spi_master_put(master);
1050 * davinci_spi_remove - remove function for SPI Master Controller
1051 * @pdev: platform_device structure which contains plateform specific data
1053 * This function will do the reverse action of davinci_spi_probe function
1054 * It will free the IRQ and SPI controller's memory region.
1055 * It will also call spi_bitbang_stop to destroy the work queue which was
1056 * created by spi_bitbang_start.
1058 static int davinci_spi_remove(struct platform_device *pdev)
1060 struct davinci_spi *dspi;
1061 struct spi_master *master;
1063 master = platform_get_drvdata(pdev);
1064 dspi = spi_master_get_devdata(master);
1066 spi_bitbang_stop(&dspi->bitbang);
1068 clk_disable_unprepare(dspi->clk);
1069 spi_master_put(master);
1074 static struct platform_driver davinci_spi_driver = {
1076 .name = "spi_davinci",
1077 .owner = THIS_MODULE,
1078 .of_match_table = of_match_ptr(davinci_spi_of_match),
1080 .probe = davinci_spi_probe,
1081 .remove = davinci_spi_remove,
1083 module_platform_driver(davinci_spi_driver);
1085 MODULE_DESCRIPTION("TI DaVinci SPI Master Controller Driver");
1086 MODULE_LICENSE("GPL");