2 * Freescale eSPI controller driver.
4 * Copyright 2010 Freescale Semiconductor, Inc.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
11 #include <linux/delay.h>
12 #include <linux/err.h>
13 #include <linux/fsl_devices.h>
14 #include <linux/interrupt.h>
15 #include <linux/module.h>
18 #include <linux/of_address.h>
19 #include <linux/of_irq.h>
20 #include <linux/of_platform.h>
21 #include <linux/platform_device.h>
22 #include <linux/spi/spi.h>
23 #include <linux/pm_runtime.h>
24 #include <sysdev/fsl_soc.h>
26 #include "spi-fsl-lib.h"
28 /* eSPI Controller registers */
30 __be32 mode; /* 0x000 - eSPI mode register */
31 __be32 event; /* 0x004 - eSPI event register */
32 __be32 mask; /* 0x008 - eSPI mask register */
33 __be32 command; /* 0x00c - eSPI command register */
34 __be32 transmit; /* 0x010 - eSPI transmit FIFO access register*/
35 __be32 receive; /* 0x014 - eSPI receive FIFO access register*/
36 u8 res[8]; /* 0x018 - 0x01c reserved */
37 __be32 csmode[4]; /* 0x020 - 0x02c eSPI cs mode register */
40 struct fsl_espi_transfer {
46 unsigned actual_length;
50 /* eSPI Controller mode register definitions */
51 #define SPMODE_ENABLE (1 << 31)
52 #define SPMODE_LOOP (1 << 30)
53 #define SPMODE_TXTHR(x) ((x) << 8)
54 #define SPMODE_RXTHR(x) ((x) << 0)
56 /* eSPI Controller CS mode register definitions */
57 #define CSMODE_CI_INACTIVEHIGH (1 << 31)
58 #define CSMODE_CP_BEGIN_EDGECLK (1 << 30)
59 #define CSMODE_REV (1 << 29)
60 #define CSMODE_DIV16 (1 << 28)
61 #define CSMODE_PM(x) ((x) << 24)
62 #define CSMODE_POL_1 (1 << 20)
63 #define CSMODE_LEN(x) ((x) << 16)
64 #define CSMODE_BEF(x) ((x) << 12)
65 #define CSMODE_AFT(x) ((x) << 8)
66 #define CSMODE_CG(x) ((x) << 3)
68 /* Default mode/csmode for eSPI controller */
69 #define SPMODE_INIT_VAL (SPMODE_TXTHR(4) | SPMODE_RXTHR(3))
70 #define CSMODE_INIT_VAL (CSMODE_POL_1 | CSMODE_BEF(0) \
71 | CSMODE_AFT(0) | CSMODE_CG(1))
73 /* SPIE register values */
74 #define SPIE_NE 0x00000200 /* Not empty */
75 #define SPIE_NF 0x00000100 /* Not full */
77 /* SPIM register values */
78 #define SPIM_NE 0x00000200 /* Not empty */
79 #define SPIM_NF 0x00000100 /* Not full */
80 #define SPIE_RXCNT(reg) ((reg >> 24) & 0x3F)
81 #define SPIE_TXCNT(reg) ((reg >> 16) & 0x3F)
83 /* SPCOM register values */
84 #define SPCOM_CS(x) ((x) << 30)
85 #define SPCOM_TRANLEN(x) ((x) << 0)
86 #define SPCOM_TRANLEN_MAX 0x10000 /* Max transaction length */
88 #define AUTOSUSPEND_TIMEOUT 2000
90 static void fsl_espi_change_mode(struct spi_device *spi)
92 struct mpc8xxx_spi *mspi = spi_master_get_devdata(spi->master);
93 struct spi_mpc8xxx_cs *cs = spi->controller_state;
94 struct fsl_espi_reg *reg_base = mspi->reg_base;
95 __be32 __iomem *mode = ®_base->csmode[spi->chip_select];
96 __be32 __iomem *espi_mode = ®_base->mode;
100 /* Turn off IRQs locally to minimize time that SPI is disabled. */
101 local_irq_save(flags);
103 /* Turn off SPI unit prior changing mode */
104 tmp = mpc8xxx_spi_read_reg(espi_mode);
105 mpc8xxx_spi_write_reg(espi_mode, tmp & ~SPMODE_ENABLE);
106 mpc8xxx_spi_write_reg(mode, cs->hw_mode);
107 mpc8xxx_spi_write_reg(espi_mode, tmp);
109 local_irq_restore(flags);
112 static u32 fsl_espi_tx_buf_lsb(struct mpc8xxx_spi *mpc8xxx_spi)
117 const u32 *tx = mpc8xxx_spi->tx;
122 data = *tx++ << mpc8xxx_spi->tx_shift;
123 data_l = data & 0xffff;
124 data_h = (data >> 16) & 0xffff;
127 data = data_h | data_l;
129 mpc8xxx_spi->tx = tx;
133 static void fsl_espi_setup_transfer(struct spi_device *spi,
134 struct spi_transfer *t)
136 struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master);
137 int bits_per_word = 0;
140 struct spi_mpc8xxx_cs *cs = spi->controller_state;
143 bits_per_word = t->bits_per_word;
147 /* spi_transfer level calls that work per-word */
149 bits_per_word = spi->bits_per_word;
152 hz = spi->max_speed_hz;
156 cs->get_rx = mpc8xxx_spi_rx_buf_u32;
157 cs->get_tx = mpc8xxx_spi_tx_buf_u32;
158 if (bits_per_word <= 8) {
159 cs->rx_shift = 8 - bits_per_word;
161 cs->rx_shift = 16 - bits_per_word;
162 if (spi->mode & SPI_LSB_FIRST)
163 cs->get_tx = fsl_espi_tx_buf_lsb;
166 mpc8xxx_spi->rx_shift = cs->rx_shift;
167 mpc8xxx_spi->tx_shift = cs->tx_shift;
168 mpc8xxx_spi->get_rx = cs->get_rx;
169 mpc8xxx_spi->get_tx = cs->get_tx;
171 bits_per_word = bits_per_word - 1;
173 /* mask out bits we are going to set */
174 cs->hw_mode &= ~(CSMODE_LEN(0xF) | CSMODE_DIV16 | CSMODE_PM(0xF));
176 cs->hw_mode |= CSMODE_LEN(bits_per_word);
178 if ((mpc8xxx_spi->spibrg / hz) > 64) {
179 cs->hw_mode |= CSMODE_DIV16;
180 pm = DIV_ROUND_UP(mpc8xxx_spi->spibrg, hz * 16 * 4);
182 WARN_ONCE(pm > 33, "%s: Requested speed is too low: %d Hz. "
183 "Will use %d Hz instead.\n", dev_name(&spi->dev),
184 hz, mpc8xxx_spi->spibrg / (4 * 16 * (32 + 1)));
188 pm = DIV_ROUND_UP(mpc8xxx_spi->spibrg, hz * 4);
195 cs->hw_mode |= CSMODE_PM(pm);
197 fsl_espi_change_mode(spi);
200 static void fsl_espi_cpu_bufs(struct mpc8xxx_spi *mspi, struct spi_transfer *t,
204 struct fsl_espi_reg *reg_base = mspi->reg_base;
209 mpc8xxx_spi_write_reg(®_base->mask, SPIM_NE);
212 word = mspi->get_tx(mspi);
213 mpc8xxx_spi_write_reg(®_base->transmit, word);
216 static int fsl_espi_bufs(struct spi_device *spi, struct spi_transfer *t)
218 struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master);
219 struct fsl_espi_reg *reg_base = mpc8xxx_spi->reg_base;
220 unsigned int len = t->len;
223 mpc8xxx_spi->len = t->len;
224 len = roundup(len, 4) / 4;
226 mpc8xxx_spi->tx = t->tx_buf;
227 mpc8xxx_spi->rx = t->rx_buf;
229 reinit_completion(&mpc8xxx_spi->done);
231 /* Set SPCOM[CS] and SPCOM[TRANLEN] field */
232 if (t->len > SPCOM_TRANLEN_MAX) {
233 dev_err(mpc8xxx_spi->dev, "Transaction length (%d)"
234 " beyond the SPCOM[TRANLEN] field\n", t->len);
237 mpc8xxx_spi_write_reg(®_base->command,
238 (SPCOM_CS(spi->chip_select) | SPCOM_TRANLEN(t->len - 1)));
240 fsl_espi_cpu_bufs(mpc8xxx_spi, t, len);
242 /* Won't hang up forever, SPI bus sometimes got lost interrupts... */
243 ret = wait_for_completion_timeout(&mpc8xxx_spi->done, 2 * HZ);
245 dev_err(mpc8xxx_spi->dev,
246 "Transaction hanging up (left %d bytes)\n",
249 /* disable rx ints */
250 mpc8xxx_spi_write_reg(®_base->mask, 0);
252 return mpc8xxx_spi->count;
255 static void fsl_espi_do_trans(struct spi_message *m,
256 struct fsl_espi_transfer *tr)
258 struct spi_device *spi = m->spi;
259 struct mpc8xxx_spi *mspi = spi_master_get_devdata(spi->master);
260 struct fsl_espi_transfer *espi_trans = tr;
261 struct spi_transfer *t, *first, trans;
264 memset(&trans, 0, sizeof(trans));
266 first = list_first_entry(&m->transfers, struct spi_transfer,
268 list_for_each_entry(t, &m->transfers, transfer_list) {
269 if ((first->bits_per_word != t->bits_per_word) ||
270 (first->speed_hz != t->speed_hz)) {
271 espi_trans->status = -EINVAL;
273 "bits_per_word/speed_hz should be same for the same SPI transfer\n");
277 trans.speed_hz = t->speed_hz;
278 trans.bits_per_word = t->bits_per_word;
279 trans.delay_usecs = max(first->delay_usecs, t->delay_usecs);
282 trans.len = espi_trans->len;
283 trans.tx_buf = espi_trans->tx_buf;
284 trans.rx_buf = espi_trans->rx_buf;
286 if (trans.bits_per_word || trans.speed_hz)
287 fsl_espi_setup_transfer(spi, &trans);
290 status = fsl_espi_bufs(spi, &trans);
295 if (trans.delay_usecs)
296 udelay(trans.delay_usecs);
298 espi_trans->status = status;
299 fsl_espi_setup_transfer(spi, NULL);
302 static void fsl_espi_cmd_trans(struct spi_message *m,
303 struct fsl_espi_transfer *trans, u8 *rx_buff)
305 struct spi_transfer *t;
308 struct fsl_espi_transfer *espi_trans = trans;
310 local_buf = kzalloc(SPCOM_TRANLEN_MAX, GFP_KERNEL);
312 espi_trans->status = -ENOMEM;
316 list_for_each_entry(t, &m->transfers, transfer_list) {
318 memcpy(local_buf + i, t->tx_buf, t->len);
323 espi_trans->tx_buf = local_buf;
324 espi_trans->rx_buf = local_buf;
325 fsl_espi_do_trans(m, espi_trans);
327 espi_trans->actual_length = espi_trans->len;
331 static void fsl_espi_rw_trans(struct spi_message *m,
332 struct fsl_espi_transfer *trans, u8 *rx_buff)
334 struct spi_transfer *t;
336 unsigned int tx_only = 0;
339 local_buf = kzalloc(SPCOM_TRANLEN_MAX, GFP_KERNEL);
341 trans->status = -ENOMEM;
345 list_for_each_entry(t, &m->transfers, transfer_list) {
347 memcpy(local_buf + i, t->tx_buf, t->len);
354 trans->tx_buf = local_buf;
355 trans->rx_buf = local_buf;
356 fsl_espi_do_trans(m, trans);
358 if (!trans->status) {
359 /* If there is at least one RX byte then copy it to rx_buff */
360 if (trans->len > tx_only)
361 memcpy(rx_buff, trans->rx_buf + tx_only,
362 trans->len - tx_only);
363 trans->actual_length += trans->len;
369 static int fsl_espi_do_one_msg(struct spi_master *master,
370 struct spi_message *m)
372 struct spi_transfer *t;
374 unsigned int n_tx = 0;
375 unsigned int n_rx = 0;
376 unsigned int xfer_len = 0;
377 struct fsl_espi_transfer espi_trans;
379 list_for_each_entry(t, &m->transfers, transfer_list) {
386 if ((t->tx_buf) || (t->rx_buf))
390 espi_trans.n_tx = n_tx;
391 espi_trans.n_rx = n_rx;
392 espi_trans.len = xfer_len;
393 espi_trans.actual_length = 0;
394 espi_trans.status = 0;
397 fsl_espi_cmd_trans(m, &espi_trans, NULL);
399 fsl_espi_rw_trans(m, &espi_trans, rx_buf);
401 m->actual_length = espi_trans.actual_length;
402 m->status = espi_trans.status;
403 spi_finalize_current_message(master);
407 static int fsl_espi_setup(struct spi_device *spi)
409 struct mpc8xxx_spi *mpc8xxx_spi;
410 struct fsl_espi_reg *reg_base;
413 struct spi_mpc8xxx_cs *cs = spi_get_ctldata(spi);
415 if (!spi->max_speed_hz)
419 cs = kzalloc(sizeof(*cs), GFP_KERNEL);
422 spi_set_ctldata(spi, cs);
425 mpc8xxx_spi = spi_master_get_devdata(spi->master);
426 reg_base = mpc8xxx_spi->reg_base;
428 pm_runtime_get_sync(mpc8xxx_spi->dev);
430 hw_mode = cs->hw_mode; /* Save original settings */
431 cs->hw_mode = mpc8xxx_spi_read_reg(
432 ®_base->csmode[spi->chip_select]);
433 /* mask out bits we are going to set */
434 cs->hw_mode &= ~(CSMODE_CP_BEGIN_EDGECLK | CSMODE_CI_INACTIVEHIGH
437 if (spi->mode & SPI_CPHA)
438 cs->hw_mode |= CSMODE_CP_BEGIN_EDGECLK;
439 if (spi->mode & SPI_CPOL)
440 cs->hw_mode |= CSMODE_CI_INACTIVEHIGH;
441 if (!(spi->mode & SPI_LSB_FIRST))
442 cs->hw_mode |= CSMODE_REV;
444 /* Handle the loop mode */
445 loop_mode = mpc8xxx_spi_read_reg(®_base->mode);
446 loop_mode &= ~SPMODE_LOOP;
447 if (spi->mode & SPI_LOOP)
448 loop_mode |= SPMODE_LOOP;
449 mpc8xxx_spi_write_reg(®_base->mode, loop_mode);
451 fsl_espi_setup_transfer(spi, NULL);
453 pm_runtime_mark_last_busy(mpc8xxx_spi->dev);
454 pm_runtime_put_autosuspend(mpc8xxx_spi->dev);
459 static void fsl_espi_cleanup(struct spi_device *spi)
461 struct spi_mpc8xxx_cs *cs = spi_get_ctldata(spi);
464 spi_set_ctldata(spi, NULL);
467 static void fsl_espi_cpu_irq(struct mpc8xxx_spi *mspi, u32 events)
469 struct fsl_espi_reg *reg_base = mspi->reg_base;
471 /* We need handle RX first */
472 if (events & SPIE_NE) {
478 /* Spin until RX is done */
479 if (SPIE_RXCNT(events) < min(4, mspi->len)) {
480 ret = spin_event_timeout(
481 !(SPIE_RXCNT(events =
482 mpc8xxx_spi_read_reg(®_base->event)) <
484 10000, 0); /* 10 msec */
487 "tired waiting for SPIE_RXCNT\n");
490 if (mspi->len >= 4) {
491 rx_data = mpc8xxx_spi_read_reg(®_base->receive);
492 } else if (mspi->len <= 0) {
494 "unexpected RX(SPIE_NE) interrupt occurred,\n"
495 "(local rxlen %d bytes, reg rxlen %d bytes)\n",
496 min(4, mspi->len), SPIE_RXCNT(events));
499 rx_nr_bytes = mspi->len;
503 rx_data_8 = in_8((u8 *)®_base->receive);
504 rx_data |= (rx_data_8 << (tmp * 8));
507 rx_data <<= (4 - mspi->len) * 8;
510 mspi->len -= rx_nr_bytes;
513 mspi->get_rx(rx_data, mspi);
516 if (!(events & SPIE_NF)) {
519 /* spin until TX is done */
520 ret = spin_event_timeout(((events = mpc8xxx_spi_read_reg(
521 ®_base->event)) & SPIE_NF), 1000, 0);
523 dev_err(mspi->dev, "tired waiting for SPIE_NF\n");
525 /* Clear the SPIE bits */
526 mpc8xxx_spi_write_reg(®_base->event, events);
527 complete(&mspi->done);
532 /* Clear the events */
533 mpc8xxx_spi_write_reg(®_base->event, events);
537 u32 word = mspi->get_tx(mspi);
539 mpc8xxx_spi_write_reg(®_base->transmit, word);
541 complete(&mspi->done);
545 static irqreturn_t fsl_espi_irq(s32 irq, void *context_data)
547 struct mpc8xxx_spi *mspi = context_data;
548 struct fsl_espi_reg *reg_base = mspi->reg_base;
549 irqreturn_t ret = IRQ_NONE;
552 /* Get interrupt events(tx/rx) */
553 events = mpc8xxx_spi_read_reg(®_base->event);
557 dev_vdbg(mspi->dev, "%s: events %x\n", __func__, events);
559 fsl_espi_cpu_irq(mspi, events);
565 static int fsl_espi_runtime_suspend(struct device *dev)
567 struct spi_master *master = dev_get_drvdata(dev);
568 struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(master);
569 struct fsl_espi_reg *reg_base = mpc8xxx_spi->reg_base;
572 regval = mpc8xxx_spi_read_reg(®_base->mode);
573 regval &= ~SPMODE_ENABLE;
574 mpc8xxx_spi_write_reg(®_base->mode, regval);
579 static int fsl_espi_runtime_resume(struct device *dev)
581 struct spi_master *master = dev_get_drvdata(dev);
582 struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(master);
583 struct fsl_espi_reg *reg_base = mpc8xxx_spi->reg_base;
586 regval = mpc8xxx_spi_read_reg(®_base->mode);
587 regval |= SPMODE_ENABLE;
588 mpc8xxx_spi_write_reg(®_base->mode, regval);
594 static size_t fsl_espi_max_message_size(struct spi_device *spi)
596 return SPCOM_TRANLEN_MAX;
599 static struct spi_master * fsl_espi_probe(struct device *dev,
600 struct resource *mem, unsigned int irq)
602 struct fsl_spi_platform_data *pdata = dev_get_platdata(dev);
603 struct spi_master *master;
604 struct mpc8xxx_spi *mpc8xxx_spi;
605 struct fsl_espi_reg *reg_base;
606 struct device_node *nc;
611 master = spi_alloc_master(dev, sizeof(struct mpc8xxx_spi));
617 dev_set_drvdata(dev, master);
619 mpc8xxx_spi_probe(dev, mem, irq);
621 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 16);
622 master->setup = fsl_espi_setup;
623 master->cleanup = fsl_espi_cleanup;
624 master->transfer_one_message = fsl_espi_do_one_msg;
625 master->auto_runtime_pm = true;
626 master->max_message_size = fsl_espi_max_message_size;
628 mpc8xxx_spi = spi_master_get_devdata(master);
630 mpc8xxx_spi->reg_base = devm_ioremap_resource(dev, mem);
631 if (IS_ERR(mpc8xxx_spi->reg_base)) {
632 ret = PTR_ERR(mpc8xxx_spi->reg_base);
636 reg_base = mpc8xxx_spi->reg_base;
638 /* Register for SPI Interrupt */
639 ret = devm_request_irq(dev, mpc8xxx_spi->irq, fsl_espi_irq,
640 0, "fsl_espi", mpc8xxx_spi);
644 if (mpc8xxx_spi->flags & SPI_QE_CPU_MODE) {
645 mpc8xxx_spi->rx_shift = 16;
646 mpc8xxx_spi->tx_shift = 24;
649 /* SPI controller initializations */
650 mpc8xxx_spi_write_reg(®_base->mode, 0);
651 mpc8xxx_spi_write_reg(®_base->mask, 0);
652 mpc8xxx_spi_write_reg(®_base->command, 0);
653 mpc8xxx_spi_write_reg(®_base->event, 0xffffffff);
655 /* Init eSPI CS mode register */
656 for_each_available_child_of_node(master->dev.of_node, nc) {
657 /* get chip select */
658 prop = of_get_property(nc, "reg", &len);
659 if (!prop || len < sizeof(*prop))
661 i = be32_to_cpup(prop);
662 if (i < 0 || i >= pdata->max_chipselect)
665 csmode = CSMODE_INIT_VAL;
666 /* check if CSBEF is set in device tree */
667 prop = of_get_property(nc, "fsl,csbef", &len);
668 if (prop && len >= sizeof(*prop)) {
669 csmode &= ~(CSMODE_BEF(0xf));
670 csmode |= CSMODE_BEF(be32_to_cpup(prop));
672 /* check if CSAFT is set in device tree */
673 prop = of_get_property(nc, "fsl,csaft", &len);
674 if (prop && len >= sizeof(*prop)) {
675 csmode &= ~(CSMODE_AFT(0xf));
676 csmode |= CSMODE_AFT(be32_to_cpup(prop));
678 mpc8xxx_spi_write_reg(®_base->csmode[i], csmode);
680 dev_info(dev, "cs=%d, init_csmode=0x%x\n", i, csmode);
683 /* Enable SPI interface */
684 regval = pdata->initial_spmode | SPMODE_INIT_VAL | SPMODE_ENABLE;
686 mpc8xxx_spi_write_reg(®_base->mode, regval);
688 pm_runtime_set_autosuspend_delay(dev, AUTOSUSPEND_TIMEOUT);
689 pm_runtime_use_autosuspend(dev);
690 pm_runtime_set_active(dev);
691 pm_runtime_enable(dev);
692 pm_runtime_get_sync(dev);
694 ret = devm_spi_register_master(dev, master);
698 dev_info(dev, "at 0x%p (irq = %d)\n", reg_base, mpc8xxx_spi->irq);
700 pm_runtime_mark_last_busy(dev);
701 pm_runtime_put_autosuspend(dev);
706 pm_runtime_put_noidle(dev);
707 pm_runtime_disable(dev);
708 pm_runtime_set_suspended(dev);
710 spi_master_put(master);
715 static int of_fsl_espi_get_chipselects(struct device *dev)
717 struct device_node *np = dev->of_node;
718 struct fsl_spi_platform_data *pdata = dev_get_platdata(dev);
722 prop = of_get_property(np, "fsl,espi-num-chipselects", &len);
723 if (!prop || len < sizeof(*prop)) {
724 dev_err(dev, "No 'fsl,espi-num-chipselects' property\n");
728 pdata->max_chipselect = *prop;
729 pdata->cs_control = NULL;
734 static int of_fsl_espi_probe(struct platform_device *ofdev)
736 struct device *dev = &ofdev->dev;
737 struct device_node *np = ofdev->dev.of_node;
738 struct spi_master *master;
743 ret = of_mpc8xxx_spi_probe(ofdev);
747 ret = of_fsl_espi_get_chipselects(dev);
751 ret = of_address_to_resource(np, 0, &mem);
755 irq = irq_of_parse_and_map(np, 0);
761 master = fsl_espi_probe(dev, &mem, irq);
762 if (IS_ERR(master)) {
763 ret = PTR_ERR(master);
773 static int of_fsl_espi_remove(struct platform_device *dev)
775 pm_runtime_disable(&dev->dev);
780 #ifdef CONFIG_PM_SLEEP
781 static int of_fsl_espi_suspend(struct device *dev)
783 struct spi_master *master = dev_get_drvdata(dev);
786 ret = spi_master_suspend(master);
788 dev_warn(dev, "cannot suspend master\n");
792 ret = pm_runtime_force_suspend(dev);
799 static int of_fsl_espi_resume(struct device *dev)
801 struct fsl_spi_platform_data *pdata = dev_get_platdata(dev);
802 struct spi_master *master = dev_get_drvdata(dev);
803 struct mpc8xxx_spi *mpc8xxx_spi;
804 struct fsl_espi_reg *reg_base;
808 mpc8xxx_spi = spi_master_get_devdata(master);
809 reg_base = mpc8xxx_spi->reg_base;
811 /* SPI controller initializations */
812 mpc8xxx_spi_write_reg(®_base->mode, 0);
813 mpc8xxx_spi_write_reg(®_base->mask, 0);
814 mpc8xxx_spi_write_reg(®_base->command, 0);
815 mpc8xxx_spi_write_reg(®_base->event, 0xffffffff);
817 /* Init eSPI CS mode register */
818 for (i = 0; i < pdata->max_chipselect; i++)
819 mpc8xxx_spi_write_reg(®_base->csmode[i], CSMODE_INIT_VAL);
821 /* Enable SPI interface */
822 regval = pdata->initial_spmode | SPMODE_INIT_VAL | SPMODE_ENABLE;
824 mpc8xxx_spi_write_reg(®_base->mode, regval);
826 ret = pm_runtime_force_resume(dev);
830 return spi_master_resume(master);
832 #endif /* CONFIG_PM_SLEEP */
834 static const struct dev_pm_ops espi_pm = {
835 SET_RUNTIME_PM_OPS(fsl_espi_runtime_suspend,
836 fsl_espi_runtime_resume, NULL)
837 SET_SYSTEM_SLEEP_PM_OPS(of_fsl_espi_suspend, of_fsl_espi_resume)
840 static const struct of_device_id of_fsl_espi_match[] = {
841 { .compatible = "fsl,mpc8536-espi" },
844 MODULE_DEVICE_TABLE(of, of_fsl_espi_match);
846 static struct platform_driver fsl_espi_driver = {
849 .of_match_table = of_fsl_espi_match,
852 .probe = of_fsl_espi_probe,
853 .remove = of_fsl_espi_remove,
855 module_platform_driver(fsl_espi_driver);
857 MODULE_AUTHOR("Mingkai Hu");
858 MODULE_DESCRIPTION("Enhanced Freescale SPI Driver");
859 MODULE_LICENSE("GPL");