2 * Freescale eSPI controller driver.
4 * Copyright 2010 Freescale Semiconductor, Inc.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
11 #include <linux/delay.h>
12 #include <linux/err.h>
13 #include <linux/fsl_devices.h>
14 #include <linux/interrupt.h>
15 #include <linux/module.h>
18 #include <linux/of_address.h>
19 #include <linux/of_irq.h>
20 #include <linux/of_platform.h>
21 #include <linux/platform_device.h>
22 #include <linux/spi/spi.h>
23 #include <linux/pm_runtime.h>
24 #include <sysdev/fsl_soc.h>
26 #include "spi-fsl-lib.h"
28 /* eSPI Controller registers */
30 __be32 mode; /* 0x000 - eSPI mode register */
31 __be32 event; /* 0x004 - eSPI event register */
32 __be32 mask; /* 0x008 - eSPI mask register */
33 __be32 command; /* 0x00c - eSPI command register */
34 __be32 transmit; /* 0x010 - eSPI transmit FIFO access register*/
35 __be32 receive; /* 0x014 - eSPI receive FIFO access register*/
36 u8 res[8]; /* 0x018 - 0x01c reserved */
37 __be32 csmode[4]; /* 0x020 - 0x02c eSPI cs mode register */
40 /* eSPI Controller mode register definitions */
41 #define SPMODE_ENABLE (1 << 31)
42 #define SPMODE_LOOP (1 << 30)
43 #define SPMODE_TXTHR(x) ((x) << 8)
44 #define SPMODE_RXTHR(x) ((x) << 0)
46 /* eSPI Controller CS mode register definitions */
47 #define CSMODE_CI_INACTIVEHIGH (1 << 31)
48 #define CSMODE_CP_BEGIN_EDGECLK (1 << 30)
49 #define CSMODE_REV (1 << 29)
50 #define CSMODE_DIV16 (1 << 28)
51 #define CSMODE_PM(x) ((x) << 24)
52 #define CSMODE_POL_1 (1 << 20)
53 #define CSMODE_LEN(x) ((x) << 16)
54 #define CSMODE_BEF(x) ((x) << 12)
55 #define CSMODE_AFT(x) ((x) << 8)
56 #define CSMODE_CG(x) ((x) << 3)
58 /* Default mode/csmode for eSPI controller */
59 #define SPMODE_INIT_VAL (SPMODE_TXTHR(4) | SPMODE_RXTHR(3))
60 #define CSMODE_INIT_VAL (CSMODE_POL_1 | CSMODE_BEF(0) \
61 | CSMODE_AFT(0) | CSMODE_CG(1))
63 /* SPIE register values */
64 #define SPIE_NE 0x00000200 /* Not empty */
65 #define SPIE_NF 0x00000100 /* Not full */
67 /* SPIM register values */
68 #define SPIM_NE 0x00000200 /* Not empty */
69 #define SPIM_NF 0x00000100 /* Not full */
70 #define SPIE_RXCNT(reg) ((reg >> 24) & 0x3F)
71 #define SPIE_TXCNT(reg) ((reg >> 16) & 0x3F)
73 /* SPCOM register values */
74 #define SPCOM_CS(x) ((x) << 30)
75 #define SPCOM_TRANLEN(x) ((x) << 0)
76 #define SPCOM_TRANLEN_MAX 0x10000 /* Max transaction length */
78 #define AUTOSUSPEND_TIMEOUT 2000
80 static void fsl_espi_copy_to_buf(struct spi_message *m,
81 struct mpc8xxx_spi *mspi)
83 struct spi_transfer *t;
84 u8 *buf = mspi->local_buf;
86 list_for_each_entry(t, &m->transfers, transfer_list) {
88 memcpy(buf, t->tx_buf, t->len);
90 memset(buf, 0, t->len);
95 static void fsl_espi_copy_from_buf(struct spi_message *m,
96 struct mpc8xxx_spi *mspi)
98 struct spi_transfer *t;
99 u8 *buf = mspi->local_buf;
101 list_for_each_entry(t, &m->transfers, transfer_list) {
103 memcpy(t->rx_buf, buf, t->len);
108 static int fsl_espi_check_message(struct spi_message *m)
110 struct mpc8xxx_spi *mspi = spi_master_get_devdata(m->spi->master);
111 struct spi_transfer *t, *first;
113 if (m->frame_length > SPCOM_TRANLEN_MAX) {
114 dev_err(mspi->dev, "message too long, size is %u bytes\n",
119 first = list_first_entry(&m->transfers, struct spi_transfer,
121 list_for_each_entry(t, &m->transfers, transfer_list) {
122 if (first->bits_per_word != t->bits_per_word ||
123 first->speed_hz != t->speed_hz) {
124 dev_err(mspi->dev, "bits_per_word/speed_hz should be the same for all transfers\n");
132 static void fsl_espi_change_mode(struct spi_device *spi)
134 struct mpc8xxx_spi *mspi = spi_master_get_devdata(spi->master);
135 struct spi_mpc8xxx_cs *cs = spi->controller_state;
136 struct fsl_espi_reg *reg_base = mspi->reg_base;
137 __be32 __iomem *mode = ®_base->csmode[spi->chip_select];
138 __be32 __iomem *espi_mode = ®_base->mode;
142 /* Turn off IRQs locally to minimize time that SPI is disabled. */
143 local_irq_save(flags);
145 /* Turn off SPI unit prior changing mode */
146 tmp = mpc8xxx_spi_read_reg(espi_mode);
147 mpc8xxx_spi_write_reg(espi_mode, tmp & ~SPMODE_ENABLE);
148 mpc8xxx_spi_write_reg(mode, cs->hw_mode);
149 mpc8xxx_spi_write_reg(espi_mode, tmp);
151 local_irq_restore(flags);
154 static u32 fsl_espi_tx_buf_lsb(struct mpc8xxx_spi *mpc8xxx_spi)
159 const u32 *tx = mpc8xxx_spi->tx;
164 data = *tx++ << mpc8xxx_spi->tx_shift;
165 data_l = data & 0xffff;
166 data_h = (data >> 16) & 0xffff;
169 data = data_h | data_l;
171 mpc8xxx_spi->tx = tx;
175 static void fsl_espi_setup_transfer(struct spi_device *spi,
176 struct spi_transfer *t)
178 struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master);
179 int bits_per_word = t ? t->bits_per_word : spi->bits_per_word;
180 u32 hz = t ? t->speed_hz : spi->max_speed_hz;
182 struct spi_mpc8xxx_cs *cs = spi->controller_state;
186 cs->get_rx = mpc8xxx_spi_rx_buf_u32;
187 cs->get_tx = mpc8xxx_spi_tx_buf_u32;
188 if (bits_per_word <= 8) {
189 cs->rx_shift = 8 - bits_per_word;
191 cs->rx_shift = 16 - bits_per_word;
192 if (spi->mode & SPI_LSB_FIRST)
193 cs->get_tx = fsl_espi_tx_buf_lsb;
196 mpc8xxx_spi->rx_shift = cs->rx_shift;
197 mpc8xxx_spi->tx_shift = cs->tx_shift;
198 mpc8xxx_spi->get_rx = cs->get_rx;
199 mpc8xxx_spi->get_tx = cs->get_tx;
201 /* mask out bits we are going to set */
202 cs->hw_mode &= ~(CSMODE_LEN(0xF) | CSMODE_DIV16 | CSMODE_PM(0xF));
204 cs->hw_mode |= CSMODE_LEN(bits_per_word - 1);
206 if ((mpc8xxx_spi->spibrg / hz) > 64) {
207 cs->hw_mode |= CSMODE_DIV16;
208 pm = DIV_ROUND_UP(mpc8xxx_spi->spibrg, hz * 16 * 4);
210 WARN_ONCE(pm > 33, "%s: Requested speed is too low: %d Hz. "
211 "Will use %d Hz instead.\n", dev_name(&spi->dev),
212 hz, mpc8xxx_spi->spibrg / (4 * 16 * (32 + 1)));
216 pm = DIV_ROUND_UP(mpc8xxx_spi->spibrg, hz * 4);
223 cs->hw_mode |= CSMODE_PM(pm);
225 fsl_espi_change_mode(spi);
228 static int fsl_espi_bufs(struct spi_device *spi, struct spi_transfer *t)
230 struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master);
231 struct fsl_espi_reg *reg_base = mpc8xxx_spi->reg_base;
235 mpc8xxx_spi->len = t->len;
236 mpc8xxx_spi->count = roundup(t->len, 4) / 4;
238 mpc8xxx_spi->tx = t->tx_buf;
239 mpc8xxx_spi->rx = t->rx_buf;
241 reinit_completion(&mpc8xxx_spi->done);
243 /* Set SPCOM[CS] and SPCOM[TRANLEN] field */
244 mpc8xxx_spi_write_reg(®_base->command,
245 (SPCOM_CS(spi->chip_select) | SPCOM_TRANLEN(t->len - 1)));
248 mpc8xxx_spi_write_reg(®_base->mask, SPIM_NE);
251 word = mpc8xxx_spi->get_tx(mpc8xxx_spi);
252 mpc8xxx_spi_write_reg(®_base->transmit, word);
254 /* Won't hang up forever, SPI bus sometimes got lost interrupts... */
255 ret = wait_for_completion_timeout(&mpc8xxx_spi->done, 2 * HZ);
257 dev_err(mpc8xxx_spi->dev,
258 "Transaction hanging up (left %d bytes)\n",
261 /* disable rx ints */
262 mpc8xxx_spi_write_reg(®_base->mask, 0);
264 return mpc8xxx_spi->count > 0 ? -EMSGSIZE : 0;
267 static int fsl_espi_trans(struct spi_message *m, struct spi_transfer *trans)
269 struct mpc8xxx_spi *mspi = spi_master_get_devdata(m->spi->master);
270 struct spi_device *spi = m->spi;
273 fsl_espi_copy_to_buf(m, mspi);
274 fsl_espi_setup_transfer(spi, trans);
276 ret = fsl_espi_bufs(spi, trans);
278 if (trans->delay_usecs)
279 udelay(trans->delay_usecs);
281 fsl_espi_setup_transfer(spi, NULL);
284 fsl_espi_copy_from_buf(m, mspi);
289 static int fsl_espi_do_one_msg(struct spi_master *master,
290 struct spi_message *m)
292 struct mpc8xxx_spi *mspi = spi_master_get_devdata(m->spi->master);
293 unsigned int delay_usecs = 0;
294 struct spi_transfer *t, trans = {};
297 ret = fsl_espi_check_message(m);
301 list_for_each_entry(t, &m->transfers, transfer_list) {
302 if (t->delay_usecs > delay_usecs)
303 delay_usecs = t->delay_usecs;
306 t = list_first_entry(&m->transfers, struct spi_transfer,
309 trans.len = m->frame_length;
310 trans.speed_hz = t->speed_hz;
311 trans.bits_per_word = t->bits_per_word;
312 trans.delay_usecs = delay_usecs;
313 trans.tx_buf = mspi->local_buf;
314 trans.rx_buf = mspi->local_buf;
317 ret = fsl_espi_trans(m, &trans);
319 m->actual_length = ret ? 0 : trans.len;
321 if (m->status == -EINPROGRESS)
324 spi_finalize_current_message(master);
329 static int fsl_espi_setup(struct spi_device *spi)
331 struct mpc8xxx_spi *mpc8xxx_spi;
332 struct fsl_espi_reg *reg_base;
335 struct spi_mpc8xxx_cs *cs = spi_get_ctldata(spi);
337 if (!spi->max_speed_hz)
341 cs = kzalloc(sizeof(*cs), GFP_KERNEL);
344 spi_set_ctldata(spi, cs);
347 mpc8xxx_spi = spi_master_get_devdata(spi->master);
348 reg_base = mpc8xxx_spi->reg_base;
350 pm_runtime_get_sync(mpc8xxx_spi->dev);
352 hw_mode = cs->hw_mode; /* Save original settings */
353 cs->hw_mode = mpc8xxx_spi_read_reg(
354 ®_base->csmode[spi->chip_select]);
355 /* mask out bits we are going to set */
356 cs->hw_mode &= ~(CSMODE_CP_BEGIN_EDGECLK | CSMODE_CI_INACTIVEHIGH
359 if (spi->mode & SPI_CPHA)
360 cs->hw_mode |= CSMODE_CP_BEGIN_EDGECLK;
361 if (spi->mode & SPI_CPOL)
362 cs->hw_mode |= CSMODE_CI_INACTIVEHIGH;
363 if (!(spi->mode & SPI_LSB_FIRST))
364 cs->hw_mode |= CSMODE_REV;
366 /* Handle the loop mode */
367 loop_mode = mpc8xxx_spi_read_reg(®_base->mode);
368 loop_mode &= ~SPMODE_LOOP;
369 if (spi->mode & SPI_LOOP)
370 loop_mode |= SPMODE_LOOP;
371 mpc8xxx_spi_write_reg(®_base->mode, loop_mode);
373 fsl_espi_setup_transfer(spi, NULL);
375 pm_runtime_mark_last_busy(mpc8xxx_spi->dev);
376 pm_runtime_put_autosuspend(mpc8xxx_spi->dev);
381 static void fsl_espi_cleanup(struct spi_device *spi)
383 struct spi_mpc8xxx_cs *cs = spi_get_ctldata(spi);
386 spi_set_ctldata(spi, NULL);
389 static void fsl_espi_cpu_irq(struct mpc8xxx_spi *mspi, u32 events)
391 struct fsl_espi_reg *reg_base = mspi->reg_base;
393 /* We need handle RX first */
394 if (events & SPIE_NE) {
400 /* Spin until RX is done */
401 if (SPIE_RXCNT(events) < min(4, mspi->len)) {
402 ret = spin_event_timeout(
403 !(SPIE_RXCNT(events =
404 mpc8xxx_spi_read_reg(®_base->event)) <
406 10000, 0); /* 10 msec */
409 "tired waiting for SPIE_RXCNT\n");
412 if (mspi->len >= 4) {
413 rx_data = mpc8xxx_spi_read_reg(®_base->receive);
414 } else if (mspi->len <= 0) {
416 "unexpected RX(SPIE_NE) interrupt occurred,\n"
417 "(local rxlen %d bytes, reg rxlen %d bytes)\n",
418 min(4, mspi->len), SPIE_RXCNT(events));
421 rx_nr_bytes = mspi->len;
425 rx_data_8 = in_8((u8 *)®_base->receive);
426 rx_data |= (rx_data_8 << (tmp * 8));
429 rx_data <<= (4 - mspi->len) * 8;
432 mspi->len -= rx_nr_bytes;
435 mspi->get_rx(rx_data, mspi);
438 if (!(events & SPIE_NF)) {
441 /* spin until TX is done */
442 ret = spin_event_timeout(((events = mpc8xxx_spi_read_reg(
443 ®_base->event)) & SPIE_NF), 1000, 0);
445 dev_err(mspi->dev, "tired waiting for SPIE_NF\n");
446 complete(&mspi->done);
453 u32 word = mspi->get_tx(mspi);
455 mpc8xxx_spi_write_reg(®_base->transmit, word);
457 complete(&mspi->done);
461 static irqreturn_t fsl_espi_irq(s32 irq, void *context_data)
463 struct mpc8xxx_spi *mspi = context_data;
464 struct fsl_espi_reg *reg_base = mspi->reg_base;
467 /* Get interrupt events(tx/rx) */
468 events = mpc8xxx_spi_read_reg(®_base->event);
472 dev_vdbg(mspi->dev, "%s: events %x\n", __func__, events);
474 fsl_espi_cpu_irq(mspi, events);
476 /* Clear the events */
477 mpc8xxx_spi_write_reg(®_base->event, events);
483 static int fsl_espi_runtime_suspend(struct device *dev)
485 struct spi_master *master = dev_get_drvdata(dev);
486 struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(master);
487 struct fsl_espi_reg *reg_base = mpc8xxx_spi->reg_base;
490 regval = mpc8xxx_spi_read_reg(®_base->mode);
491 regval &= ~SPMODE_ENABLE;
492 mpc8xxx_spi_write_reg(®_base->mode, regval);
497 static int fsl_espi_runtime_resume(struct device *dev)
499 struct spi_master *master = dev_get_drvdata(dev);
500 struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(master);
501 struct fsl_espi_reg *reg_base = mpc8xxx_spi->reg_base;
504 regval = mpc8xxx_spi_read_reg(®_base->mode);
505 regval |= SPMODE_ENABLE;
506 mpc8xxx_spi_write_reg(®_base->mode, regval);
512 static size_t fsl_espi_max_message_size(struct spi_device *spi)
514 return SPCOM_TRANLEN_MAX;
517 static struct spi_master * fsl_espi_probe(struct device *dev,
518 struct resource *mem, unsigned int irq)
520 struct fsl_spi_platform_data *pdata = dev_get_platdata(dev);
521 struct spi_master *master;
522 struct mpc8xxx_spi *mpc8xxx_spi;
523 struct fsl_espi_reg *reg_base;
524 struct device_node *nc;
529 master = spi_alloc_master(dev, sizeof(struct mpc8xxx_spi));
535 dev_set_drvdata(dev, master);
537 mpc8xxx_spi_probe(dev, mem, irq);
539 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 16);
540 master->setup = fsl_espi_setup;
541 master->cleanup = fsl_espi_cleanup;
542 master->transfer_one_message = fsl_espi_do_one_msg;
543 master->auto_runtime_pm = true;
544 master->max_message_size = fsl_espi_max_message_size;
546 mpc8xxx_spi = spi_master_get_devdata(master);
548 mpc8xxx_spi->local_buf =
549 devm_kmalloc(dev, SPCOM_TRANLEN_MAX, GFP_KERNEL);
550 if (!mpc8xxx_spi->local_buf) {
555 mpc8xxx_spi->reg_base = devm_ioremap_resource(dev, mem);
556 if (IS_ERR(mpc8xxx_spi->reg_base)) {
557 ret = PTR_ERR(mpc8xxx_spi->reg_base);
561 reg_base = mpc8xxx_spi->reg_base;
563 /* Register for SPI Interrupt */
564 ret = devm_request_irq(dev, mpc8xxx_spi->irq, fsl_espi_irq,
565 0, "fsl_espi", mpc8xxx_spi);
569 if (mpc8xxx_spi->flags & SPI_QE_CPU_MODE) {
570 mpc8xxx_spi->rx_shift = 16;
571 mpc8xxx_spi->tx_shift = 24;
574 /* SPI controller initializations */
575 mpc8xxx_spi_write_reg(®_base->mode, 0);
576 mpc8xxx_spi_write_reg(®_base->mask, 0);
577 mpc8xxx_spi_write_reg(®_base->command, 0);
578 mpc8xxx_spi_write_reg(®_base->event, 0xffffffff);
580 /* Init eSPI CS mode register */
581 for_each_available_child_of_node(master->dev.of_node, nc) {
582 /* get chip select */
583 prop = of_get_property(nc, "reg", &len);
584 if (!prop || len < sizeof(*prop))
586 i = be32_to_cpup(prop);
587 if (i < 0 || i >= pdata->max_chipselect)
590 csmode = CSMODE_INIT_VAL;
591 /* check if CSBEF is set in device tree */
592 prop = of_get_property(nc, "fsl,csbef", &len);
593 if (prop && len >= sizeof(*prop)) {
594 csmode &= ~(CSMODE_BEF(0xf));
595 csmode |= CSMODE_BEF(be32_to_cpup(prop));
597 /* check if CSAFT is set in device tree */
598 prop = of_get_property(nc, "fsl,csaft", &len);
599 if (prop && len >= sizeof(*prop)) {
600 csmode &= ~(CSMODE_AFT(0xf));
601 csmode |= CSMODE_AFT(be32_to_cpup(prop));
603 mpc8xxx_spi_write_reg(®_base->csmode[i], csmode);
605 dev_info(dev, "cs=%d, init_csmode=0x%x\n", i, csmode);
608 /* Enable SPI interface */
609 regval = pdata->initial_spmode | SPMODE_INIT_VAL | SPMODE_ENABLE;
611 mpc8xxx_spi_write_reg(®_base->mode, regval);
613 pm_runtime_set_autosuspend_delay(dev, AUTOSUSPEND_TIMEOUT);
614 pm_runtime_use_autosuspend(dev);
615 pm_runtime_set_active(dev);
616 pm_runtime_enable(dev);
617 pm_runtime_get_sync(dev);
619 ret = devm_spi_register_master(dev, master);
623 dev_info(dev, "at 0x%p (irq = %d)\n", reg_base, mpc8xxx_spi->irq);
625 pm_runtime_mark_last_busy(dev);
626 pm_runtime_put_autosuspend(dev);
631 pm_runtime_put_noidle(dev);
632 pm_runtime_disable(dev);
633 pm_runtime_set_suspended(dev);
635 spi_master_put(master);
640 static int of_fsl_espi_get_chipselects(struct device *dev)
642 struct device_node *np = dev->of_node;
643 struct fsl_spi_platform_data *pdata = dev_get_platdata(dev);
647 prop = of_get_property(np, "fsl,espi-num-chipselects", &len);
648 if (!prop || len < sizeof(*prop)) {
649 dev_err(dev, "No 'fsl,espi-num-chipselects' property\n");
653 pdata->max_chipselect = *prop;
654 pdata->cs_control = NULL;
659 static int of_fsl_espi_probe(struct platform_device *ofdev)
661 struct device *dev = &ofdev->dev;
662 struct device_node *np = ofdev->dev.of_node;
663 struct spi_master *master;
668 ret = of_mpc8xxx_spi_probe(ofdev);
672 ret = of_fsl_espi_get_chipselects(dev);
676 ret = of_address_to_resource(np, 0, &mem);
680 irq = irq_of_parse_and_map(np, 0);
686 master = fsl_espi_probe(dev, &mem, irq);
687 if (IS_ERR(master)) {
688 ret = PTR_ERR(master);
698 static int of_fsl_espi_remove(struct platform_device *dev)
700 pm_runtime_disable(&dev->dev);
705 #ifdef CONFIG_PM_SLEEP
706 static int of_fsl_espi_suspend(struct device *dev)
708 struct spi_master *master = dev_get_drvdata(dev);
711 ret = spi_master_suspend(master);
713 dev_warn(dev, "cannot suspend master\n");
717 ret = pm_runtime_force_suspend(dev);
724 static int of_fsl_espi_resume(struct device *dev)
726 struct fsl_spi_platform_data *pdata = dev_get_platdata(dev);
727 struct spi_master *master = dev_get_drvdata(dev);
728 struct mpc8xxx_spi *mpc8xxx_spi;
729 struct fsl_espi_reg *reg_base;
733 mpc8xxx_spi = spi_master_get_devdata(master);
734 reg_base = mpc8xxx_spi->reg_base;
736 /* SPI controller initializations */
737 mpc8xxx_spi_write_reg(®_base->mode, 0);
738 mpc8xxx_spi_write_reg(®_base->mask, 0);
739 mpc8xxx_spi_write_reg(®_base->command, 0);
740 mpc8xxx_spi_write_reg(®_base->event, 0xffffffff);
742 /* Init eSPI CS mode register */
743 for (i = 0; i < pdata->max_chipselect; i++)
744 mpc8xxx_spi_write_reg(®_base->csmode[i], CSMODE_INIT_VAL);
746 /* Enable SPI interface */
747 regval = pdata->initial_spmode | SPMODE_INIT_VAL | SPMODE_ENABLE;
749 mpc8xxx_spi_write_reg(®_base->mode, regval);
751 ret = pm_runtime_force_resume(dev);
755 return spi_master_resume(master);
757 #endif /* CONFIG_PM_SLEEP */
759 static const struct dev_pm_ops espi_pm = {
760 SET_RUNTIME_PM_OPS(fsl_espi_runtime_suspend,
761 fsl_espi_runtime_resume, NULL)
762 SET_SYSTEM_SLEEP_PM_OPS(of_fsl_espi_suspend, of_fsl_espi_resume)
765 static const struct of_device_id of_fsl_espi_match[] = {
766 { .compatible = "fsl,mpc8536-espi" },
769 MODULE_DEVICE_TABLE(of, of_fsl_espi_match);
771 static struct platform_driver fsl_espi_driver = {
774 .of_match_table = of_fsl_espi_match,
777 .probe = of_fsl_espi_probe,
778 .remove = of_fsl_espi_remove,
780 module_platform_driver(fsl_espi_driver);
782 MODULE_AUTHOR("Mingkai Hu");
783 MODULE_DESCRIPTION("Enhanced Freescale SPI Driver");
784 MODULE_LICENSE("GPL");