2 * Freescale eSPI controller driver.
4 * Copyright 2010 Freescale Semiconductor, Inc.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
11 #include <linux/delay.h>
12 #include <linux/err.h>
13 #include <linux/fsl_devices.h>
14 #include <linux/interrupt.h>
15 #include <linux/module.h>
18 #include <linux/of_address.h>
19 #include <linux/of_irq.h>
20 #include <linux/of_platform.h>
21 #include <linux/platform_device.h>
22 #include <linux/spi/spi.h>
23 #include <linux/pm_runtime.h>
24 #include <sysdev/fsl_soc.h>
26 #include "spi-fsl-lib.h"
28 /* eSPI Controller registers */
29 #define ESPI_SPMODE 0x00 /* eSPI mode register */
30 #define ESPI_SPIE 0x04 /* eSPI event register */
31 #define ESPI_SPIM 0x08 /* eSPI mask register */
32 #define ESPI_SPCOM 0x0c /* eSPI command register */
33 #define ESPI_SPITF 0x10 /* eSPI transmit FIFO access register*/
34 #define ESPI_SPIRF 0x14 /* eSPI receive FIFO access register*/
35 #define ESPI_SPMODE0 0x20 /* eSPI cs0 mode register */
37 #define ESPI_SPMODEx(x) (ESPI_SPMODE0 + (x) * 4)
39 /* eSPI Controller mode register definitions */
40 #define SPMODE_ENABLE BIT(31)
41 #define SPMODE_LOOP BIT(30)
42 #define SPMODE_TXTHR(x) ((x) << 8)
43 #define SPMODE_RXTHR(x) ((x) << 0)
45 /* eSPI Controller CS mode register definitions */
46 #define CSMODE_CI_INACTIVEHIGH BIT(31)
47 #define CSMODE_CP_BEGIN_EDGECLK BIT(30)
48 #define CSMODE_REV BIT(29)
49 #define CSMODE_DIV16 BIT(28)
50 #define CSMODE_PM(x) ((x) << 24)
51 #define CSMODE_POL_1 BIT(20)
52 #define CSMODE_LEN(x) ((x) << 16)
53 #define CSMODE_BEF(x) ((x) << 12)
54 #define CSMODE_AFT(x) ((x) << 8)
55 #define CSMODE_CG(x) ((x) << 3)
57 /* Default mode/csmode for eSPI controller */
58 #define SPMODE_INIT_VAL (SPMODE_TXTHR(4) | SPMODE_RXTHR(3))
59 #define CSMODE_INIT_VAL (CSMODE_POL_1 | CSMODE_BEF(0) \
60 | CSMODE_AFT(0) | CSMODE_CG(1))
62 /* SPIE register values */
63 #define SPIE_RXCNT(reg) ((reg >> 24) & 0x3F)
64 #define SPIE_TXCNT(reg) ((reg >> 16) & 0x3F)
65 #define SPIE_TXE BIT(15) /* TX FIFO empty */
66 #define SPIE_DON BIT(14) /* TX done */
67 #define SPIE_RXT BIT(13) /* RX FIFO threshold */
68 #define SPIE_RXF BIT(12) /* RX FIFO full */
69 #define SPIE_TXT BIT(11) /* TX FIFO threshold*/
70 #define SPIE_RNE BIT(9) /* RX FIFO not empty */
71 #define SPIE_TNF BIT(8) /* TX FIFO not full */
73 /* SPIM register values */
74 #define SPIM_TXE BIT(15) /* TX FIFO empty */
75 #define SPIM_DON BIT(14) /* TX done */
76 #define SPIM_RXT BIT(13) /* RX FIFO threshold */
77 #define SPIM_RXF BIT(12) /* RX FIFO full */
78 #define SPIM_TXT BIT(11) /* TX FIFO threshold*/
79 #define SPIM_RNE BIT(9) /* RX FIFO not empty */
80 #define SPIM_TNF BIT(8) /* TX FIFO not full */
82 /* SPCOM register values */
83 #define SPCOM_CS(x) ((x) << 30)
84 #define SPCOM_DO BIT(28) /* Dual output */
85 #define SPCOM_TO BIT(27) /* TX only */
86 #define SPCOM_RXSKIP(x) ((x) << 16)
87 #define SPCOM_TRANLEN(x) ((x) << 0)
89 #define SPCOM_TRANLEN_MAX 0x10000 /* Max transaction length */
91 #define AUTOSUSPEND_TIMEOUT 2000
93 static inline u32 fsl_espi_read_reg(struct mpc8xxx_spi *mspi, int offset)
95 return ioread32be(mspi->reg_base + offset);
98 static inline u8 fsl_espi_read_reg8(struct mpc8xxx_spi *mspi, int offset)
100 return ioread8(mspi->reg_base + offset);
103 static inline void fsl_espi_write_reg(struct mpc8xxx_spi *mspi, int offset,
106 iowrite32be(val, mspi->reg_base + offset);
109 static inline void fsl_espi_write_reg8(struct mpc8xxx_spi *mspi, int offset,
112 iowrite8(val, mspi->reg_base + offset);
115 static void fsl_espi_copy_to_buf(struct spi_message *m,
116 struct mpc8xxx_spi *mspi)
118 struct spi_transfer *t;
119 u8 *buf = mspi->local_buf;
121 list_for_each_entry(t, &m->transfers, transfer_list) {
123 memcpy(buf, t->tx_buf, t->len);
125 memset(buf, 0, t->len);
130 static void fsl_espi_copy_from_buf(struct spi_message *m,
131 struct mpc8xxx_spi *mspi)
133 struct spi_transfer *t;
134 u8 *buf = mspi->local_buf;
136 list_for_each_entry(t, &m->transfers, transfer_list) {
138 memcpy(t->rx_buf, buf, t->len);
143 static int fsl_espi_check_message(struct spi_message *m)
145 struct mpc8xxx_spi *mspi = spi_master_get_devdata(m->spi->master);
146 struct spi_transfer *t, *first;
148 if (m->frame_length > SPCOM_TRANLEN_MAX) {
149 dev_err(mspi->dev, "message too long, size is %u bytes\n",
154 first = list_first_entry(&m->transfers, struct spi_transfer,
156 list_for_each_entry(t, &m->transfers, transfer_list) {
157 if (first->bits_per_word != t->bits_per_word ||
158 first->speed_hz != t->speed_hz) {
159 dev_err(mspi->dev, "bits_per_word/speed_hz should be the same for all transfers\n");
167 static void fsl_espi_change_mode(struct spi_device *spi)
169 struct mpc8xxx_spi *mspi = spi_master_get_devdata(spi->master);
170 struct spi_mpc8xxx_cs *cs = spi->controller_state;
174 /* Turn off IRQs locally to minimize time that SPI is disabled. */
175 local_irq_save(flags);
177 /* Turn off SPI unit prior changing mode */
178 tmp = fsl_espi_read_reg(mspi, ESPI_SPMODE);
179 fsl_espi_write_reg(mspi, ESPI_SPMODE, tmp & ~SPMODE_ENABLE);
180 fsl_espi_write_reg(mspi, ESPI_SPMODEx(spi->chip_select),
182 fsl_espi_write_reg(mspi, ESPI_SPMODE, tmp);
184 local_irq_restore(flags);
187 static u32 fsl_espi_tx_buf_lsb(struct mpc8xxx_spi *mpc8xxx_spi)
192 const u32 *tx = mpc8xxx_spi->tx;
197 data = *tx++ << mpc8xxx_spi->tx_shift;
198 data_l = data & 0xffff;
199 data_h = (data >> 16) & 0xffff;
202 data = data_h | data_l;
204 mpc8xxx_spi->tx = tx;
208 static void fsl_espi_setup_transfer(struct spi_device *spi,
209 struct spi_transfer *t)
211 struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master);
212 int bits_per_word = t ? t->bits_per_word : spi->bits_per_word;
213 u32 hz = t ? t->speed_hz : spi->max_speed_hz;
215 struct spi_mpc8xxx_cs *cs = spi->controller_state;
219 cs->get_rx = mpc8xxx_spi_rx_buf_u32;
220 cs->get_tx = mpc8xxx_spi_tx_buf_u32;
221 if (bits_per_word <= 8) {
222 cs->rx_shift = 8 - bits_per_word;
224 cs->rx_shift = 16 - bits_per_word;
225 if (spi->mode & SPI_LSB_FIRST)
226 cs->get_tx = fsl_espi_tx_buf_lsb;
229 mpc8xxx_spi->rx_shift = cs->rx_shift;
230 mpc8xxx_spi->tx_shift = cs->tx_shift;
231 mpc8xxx_spi->get_rx = cs->get_rx;
232 mpc8xxx_spi->get_tx = cs->get_tx;
234 /* mask out bits we are going to set */
235 cs->hw_mode &= ~(CSMODE_LEN(0xF) | CSMODE_DIV16 | CSMODE_PM(0xF));
237 cs->hw_mode |= CSMODE_LEN(bits_per_word - 1);
239 if ((mpc8xxx_spi->spibrg / hz) > 64) {
240 cs->hw_mode |= CSMODE_DIV16;
241 pm = DIV_ROUND_UP(mpc8xxx_spi->spibrg, hz * 16 * 4);
243 WARN_ONCE(pm > 33, "%s: Requested speed is too low: %d Hz. "
244 "Will use %d Hz instead.\n", dev_name(&spi->dev),
245 hz, mpc8xxx_spi->spibrg / (4 * 16 * (32 + 1)));
249 pm = DIV_ROUND_UP(mpc8xxx_spi->spibrg, hz * 4);
256 cs->hw_mode |= CSMODE_PM(pm);
258 fsl_espi_change_mode(spi);
261 static int fsl_espi_bufs(struct spi_device *spi, struct spi_transfer *t)
263 struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master);
267 mpc8xxx_spi->len = t->len;
268 mpc8xxx_spi->count = roundup(t->len, 4) / 4;
270 mpc8xxx_spi->tx = t->tx_buf;
271 mpc8xxx_spi->rx = t->rx_buf;
273 reinit_completion(&mpc8xxx_spi->done);
275 /* Set SPCOM[CS] and SPCOM[TRANLEN] field */
276 fsl_espi_write_reg(mpc8xxx_spi, ESPI_SPCOM,
277 (SPCOM_CS(spi->chip_select) | SPCOM_TRANLEN(t->len - 1)));
280 fsl_espi_write_reg(mpc8xxx_spi, ESPI_SPIM, SPIM_RNE);
283 word = mpc8xxx_spi->get_tx(mpc8xxx_spi);
284 fsl_espi_write_reg(mpc8xxx_spi, ESPI_SPITF, word);
286 /* Won't hang up forever, SPI bus sometimes got lost interrupts... */
287 ret = wait_for_completion_timeout(&mpc8xxx_spi->done, 2 * HZ);
289 dev_err(mpc8xxx_spi->dev,
290 "Transaction hanging up (left %d bytes)\n",
293 /* disable rx ints */
294 fsl_espi_write_reg(mpc8xxx_spi, ESPI_SPIM, 0);
296 return mpc8xxx_spi->count > 0 ? -EMSGSIZE : 0;
299 static int fsl_espi_trans(struct spi_message *m, struct spi_transfer *trans)
301 struct mpc8xxx_spi *mspi = spi_master_get_devdata(m->spi->master);
302 struct spi_device *spi = m->spi;
305 fsl_espi_copy_to_buf(m, mspi);
306 fsl_espi_setup_transfer(spi, trans);
308 ret = fsl_espi_bufs(spi, trans);
310 if (trans->delay_usecs)
311 udelay(trans->delay_usecs);
313 fsl_espi_setup_transfer(spi, NULL);
316 fsl_espi_copy_from_buf(m, mspi);
321 static int fsl_espi_do_one_msg(struct spi_master *master,
322 struct spi_message *m)
324 struct mpc8xxx_spi *mspi = spi_master_get_devdata(m->spi->master);
325 unsigned int delay_usecs = 0;
326 struct spi_transfer *t, trans = {};
329 ret = fsl_espi_check_message(m);
333 list_for_each_entry(t, &m->transfers, transfer_list) {
334 if (t->delay_usecs > delay_usecs)
335 delay_usecs = t->delay_usecs;
338 t = list_first_entry(&m->transfers, struct spi_transfer,
341 trans.len = m->frame_length;
342 trans.speed_hz = t->speed_hz;
343 trans.bits_per_word = t->bits_per_word;
344 trans.delay_usecs = delay_usecs;
345 trans.tx_buf = mspi->local_buf;
346 trans.rx_buf = mspi->local_buf;
349 ret = fsl_espi_trans(m, &trans);
351 m->actual_length = ret ? 0 : trans.len;
353 if (m->status == -EINPROGRESS)
356 spi_finalize_current_message(master);
361 static int fsl_espi_setup(struct spi_device *spi)
363 struct mpc8xxx_spi *mpc8xxx_spi;
366 struct spi_mpc8xxx_cs *cs = spi_get_ctldata(spi);
368 if (!spi->max_speed_hz)
372 cs = kzalloc(sizeof(*cs), GFP_KERNEL);
375 spi_set_ctldata(spi, cs);
378 mpc8xxx_spi = spi_master_get_devdata(spi->master);
380 pm_runtime_get_sync(mpc8xxx_spi->dev);
382 hw_mode = cs->hw_mode; /* Save original settings */
383 cs->hw_mode = fsl_espi_read_reg(mpc8xxx_spi,
384 ESPI_SPMODEx(spi->chip_select));
385 /* mask out bits we are going to set */
386 cs->hw_mode &= ~(CSMODE_CP_BEGIN_EDGECLK | CSMODE_CI_INACTIVEHIGH
389 if (spi->mode & SPI_CPHA)
390 cs->hw_mode |= CSMODE_CP_BEGIN_EDGECLK;
391 if (spi->mode & SPI_CPOL)
392 cs->hw_mode |= CSMODE_CI_INACTIVEHIGH;
393 if (!(spi->mode & SPI_LSB_FIRST))
394 cs->hw_mode |= CSMODE_REV;
396 /* Handle the loop mode */
397 loop_mode = fsl_espi_read_reg(mpc8xxx_spi, ESPI_SPMODE);
398 loop_mode &= ~SPMODE_LOOP;
399 if (spi->mode & SPI_LOOP)
400 loop_mode |= SPMODE_LOOP;
401 fsl_espi_write_reg(mpc8xxx_spi, ESPI_SPMODE, loop_mode);
403 fsl_espi_setup_transfer(spi, NULL);
405 pm_runtime_mark_last_busy(mpc8xxx_spi->dev);
406 pm_runtime_put_autosuspend(mpc8xxx_spi->dev);
411 static void fsl_espi_cleanup(struct spi_device *spi)
413 struct spi_mpc8xxx_cs *cs = spi_get_ctldata(spi);
416 spi_set_ctldata(spi, NULL);
419 static void fsl_espi_cpu_irq(struct mpc8xxx_spi *mspi, u32 events)
421 /* We need handle RX first */
422 if (events & SPIE_RNE) {
428 /* Spin until RX is done */
429 if (SPIE_RXCNT(events) < min(4, mspi->len)) {
430 ret = spin_event_timeout(
431 !(SPIE_RXCNT(events =
432 fsl_espi_read_reg(mspi, ESPI_SPIE)) <
434 10000, 0); /* 10 msec */
437 "tired waiting for SPIE_RXCNT\n");
440 if (mspi->len >= 4) {
441 rx_data = fsl_espi_read_reg(mspi, ESPI_SPIRF);
442 } else if (mspi->len <= 0) {
444 "unexpected RX(SPIE_RNE) interrupt occurred,\n"
445 "(local rxlen %d bytes, reg rxlen %d bytes)\n",
446 min(4, mspi->len), SPIE_RXCNT(events));
449 rx_nr_bytes = mspi->len;
453 rx_data_8 = fsl_espi_read_reg8(mspi,
455 rx_data |= (rx_data_8 << (tmp * 8));
458 rx_data <<= (4 - mspi->len) * 8;
461 mspi->len -= rx_nr_bytes;
464 mspi->get_rx(rx_data, mspi);
467 if (!(events & SPIE_TNF)) {
470 /* spin until TX is done */
471 ret = spin_event_timeout(((events = fsl_espi_read_reg(
472 mspi, ESPI_SPIE)) & SPIE_TNF), 1000, 0);
474 dev_err(mspi->dev, "tired waiting for SPIE_TNF\n");
475 complete(&mspi->done);
482 u32 word = mspi->get_tx(mspi);
484 fsl_espi_write_reg(mspi, ESPI_SPITF, word);
486 complete(&mspi->done);
490 static irqreturn_t fsl_espi_irq(s32 irq, void *context_data)
492 struct mpc8xxx_spi *mspi = context_data;
495 /* Get interrupt events(tx/rx) */
496 events = fsl_espi_read_reg(mspi, ESPI_SPIE);
500 dev_vdbg(mspi->dev, "%s: events %x\n", __func__, events);
502 fsl_espi_cpu_irq(mspi, events);
504 /* Clear the events */
505 fsl_espi_write_reg(mspi, ESPI_SPIE, events);
511 static int fsl_espi_runtime_suspend(struct device *dev)
513 struct spi_master *master = dev_get_drvdata(dev);
514 struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(master);
517 regval = fsl_espi_read_reg(mpc8xxx_spi, ESPI_SPMODE);
518 regval &= ~SPMODE_ENABLE;
519 fsl_espi_write_reg(mpc8xxx_spi, ESPI_SPMODE, regval);
524 static int fsl_espi_runtime_resume(struct device *dev)
526 struct spi_master *master = dev_get_drvdata(dev);
527 struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(master);
530 regval = fsl_espi_read_reg(mpc8xxx_spi, ESPI_SPMODE);
531 regval |= SPMODE_ENABLE;
532 fsl_espi_write_reg(mpc8xxx_spi, ESPI_SPMODE, regval);
538 static size_t fsl_espi_max_message_size(struct spi_device *spi)
540 return SPCOM_TRANLEN_MAX;
543 static struct spi_master * fsl_espi_probe(struct device *dev,
544 struct resource *mem, unsigned int irq)
546 struct fsl_spi_platform_data *pdata = dev_get_platdata(dev);
547 struct spi_master *master;
548 struct mpc8xxx_spi *mpc8xxx_spi;
549 struct device_node *nc;
554 master = spi_alloc_master(dev, sizeof(struct mpc8xxx_spi));
560 dev_set_drvdata(dev, master);
562 mpc8xxx_spi_probe(dev, mem, irq);
564 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 16);
565 master->setup = fsl_espi_setup;
566 master->cleanup = fsl_espi_cleanup;
567 master->transfer_one_message = fsl_espi_do_one_msg;
568 master->auto_runtime_pm = true;
569 master->max_message_size = fsl_espi_max_message_size;
571 mpc8xxx_spi = spi_master_get_devdata(master);
573 mpc8xxx_spi->local_buf =
574 devm_kmalloc(dev, SPCOM_TRANLEN_MAX, GFP_KERNEL);
575 if (!mpc8xxx_spi->local_buf) {
580 mpc8xxx_spi->reg_base = devm_ioremap_resource(dev, mem);
581 if (IS_ERR(mpc8xxx_spi->reg_base)) {
582 ret = PTR_ERR(mpc8xxx_spi->reg_base);
586 /* Register for SPI Interrupt */
587 ret = devm_request_irq(dev, mpc8xxx_spi->irq, fsl_espi_irq,
588 0, "fsl_espi", mpc8xxx_spi);
592 if (mpc8xxx_spi->flags & SPI_QE_CPU_MODE) {
593 mpc8xxx_spi->rx_shift = 16;
594 mpc8xxx_spi->tx_shift = 24;
597 /* SPI controller initializations */
598 fsl_espi_write_reg(mpc8xxx_spi, ESPI_SPMODE, 0);
599 fsl_espi_write_reg(mpc8xxx_spi, ESPI_SPIM, 0);
600 fsl_espi_write_reg(mpc8xxx_spi, ESPI_SPCOM, 0);
601 fsl_espi_write_reg(mpc8xxx_spi, ESPI_SPIE, 0xffffffff);
603 /* Init eSPI CS mode register */
604 for_each_available_child_of_node(master->dev.of_node, nc) {
605 /* get chip select */
606 prop = of_get_property(nc, "reg", &len);
607 if (!prop || len < sizeof(*prop))
609 i = be32_to_cpup(prop);
610 if (i < 0 || i >= pdata->max_chipselect)
613 csmode = CSMODE_INIT_VAL;
614 /* check if CSBEF is set in device tree */
615 prop = of_get_property(nc, "fsl,csbef", &len);
616 if (prop && len >= sizeof(*prop)) {
617 csmode &= ~(CSMODE_BEF(0xf));
618 csmode |= CSMODE_BEF(be32_to_cpup(prop));
620 /* check if CSAFT is set in device tree */
621 prop = of_get_property(nc, "fsl,csaft", &len);
622 if (prop && len >= sizeof(*prop)) {
623 csmode &= ~(CSMODE_AFT(0xf));
624 csmode |= CSMODE_AFT(be32_to_cpup(prop));
626 fsl_espi_write_reg(mpc8xxx_spi, ESPI_SPMODEx(i), csmode);
628 dev_info(dev, "cs=%d, init_csmode=0x%x\n", i, csmode);
631 /* Enable SPI interface */
632 regval = pdata->initial_spmode | SPMODE_INIT_VAL | SPMODE_ENABLE;
634 fsl_espi_write_reg(mpc8xxx_spi, ESPI_SPMODE, regval);
636 pm_runtime_set_autosuspend_delay(dev, AUTOSUSPEND_TIMEOUT);
637 pm_runtime_use_autosuspend(dev);
638 pm_runtime_set_active(dev);
639 pm_runtime_enable(dev);
640 pm_runtime_get_sync(dev);
642 ret = devm_spi_register_master(dev, master);
646 dev_info(dev, "at 0x%p (irq = %d)\n", mpc8xxx_spi->reg_base,
649 pm_runtime_mark_last_busy(dev);
650 pm_runtime_put_autosuspend(dev);
655 pm_runtime_put_noidle(dev);
656 pm_runtime_disable(dev);
657 pm_runtime_set_suspended(dev);
659 spi_master_put(master);
664 static int of_fsl_espi_get_chipselects(struct device *dev)
666 struct device_node *np = dev->of_node;
667 struct fsl_spi_platform_data *pdata = dev_get_platdata(dev);
671 prop = of_get_property(np, "fsl,espi-num-chipselects", &len);
672 if (!prop || len < sizeof(*prop)) {
673 dev_err(dev, "No 'fsl,espi-num-chipselects' property\n");
677 pdata->max_chipselect = *prop;
678 pdata->cs_control = NULL;
683 static int of_fsl_espi_probe(struct platform_device *ofdev)
685 struct device *dev = &ofdev->dev;
686 struct device_node *np = ofdev->dev.of_node;
687 struct spi_master *master;
692 ret = of_mpc8xxx_spi_probe(ofdev);
696 ret = of_fsl_espi_get_chipselects(dev);
700 ret = of_address_to_resource(np, 0, &mem);
704 irq = irq_of_parse_and_map(np, 0);
710 master = fsl_espi_probe(dev, &mem, irq);
711 if (IS_ERR(master)) {
712 ret = PTR_ERR(master);
722 static int of_fsl_espi_remove(struct platform_device *dev)
724 pm_runtime_disable(&dev->dev);
729 #ifdef CONFIG_PM_SLEEP
730 static int of_fsl_espi_suspend(struct device *dev)
732 struct spi_master *master = dev_get_drvdata(dev);
735 ret = spi_master_suspend(master);
737 dev_warn(dev, "cannot suspend master\n");
741 ret = pm_runtime_force_suspend(dev);
748 static int of_fsl_espi_resume(struct device *dev)
750 struct fsl_spi_platform_data *pdata = dev_get_platdata(dev);
751 struct spi_master *master = dev_get_drvdata(dev);
752 struct mpc8xxx_spi *mpc8xxx_spi;
756 mpc8xxx_spi = spi_master_get_devdata(master);
758 /* SPI controller initializations */
759 fsl_espi_write_reg(mpc8xxx_spi, ESPI_SPMODE, 0);
760 fsl_espi_write_reg(mpc8xxx_spi, ESPI_SPIM, 0);
761 fsl_espi_write_reg(mpc8xxx_spi, ESPI_SPCOM, 0);
762 fsl_espi_write_reg(mpc8xxx_spi, ESPI_SPIE, 0xffffffff);
764 /* Init eSPI CS mode register */
765 for (i = 0; i < pdata->max_chipselect; i++)
766 fsl_espi_write_reg(mpc8xxx_spi, ESPI_SPMODEx(i),
769 /* Enable SPI interface */
770 regval = pdata->initial_spmode | SPMODE_INIT_VAL | SPMODE_ENABLE;
772 fsl_espi_write_reg(mpc8xxx_spi, ESPI_SPMODE, regval);
774 ret = pm_runtime_force_resume(dev);
778 return spi_master_resume(master);
780 #endif /* CONFIG_PM_SLEEP */
782 static const struct dev_pm_ops espi_pm = {
783 SET_RUNTIME_PM_OPS(fsl_espi_runtime_suspend,
784 fsl_espi_runtime_resume, NULL)
785 SET_SYSTEM_SLEEP_PM_OPS(of_fsl_espi_suspend, of_fsl_espi_resume)
788 static const struct of_device_id of_fsl_espi_match[] = {
789 { .compatible = "fsl,mpc8536-espi" },
792 MODULE_DEVICE_TABLE(of, of_fsl_espi_match);
794 static struct platform_driver fsl_espi_driver = {
797 .of_match_table = of_fsl_espi_match,
800 .probe = of_fsl_espi_probe,
801 .remove = of_fsl_espi_remove,
803 module_platform_driver(fsl_espi_driver);
805 MODULE_AUTHOR("Mingkai Hu");
806 MODULE_DESCRIPTION("Enhanced Freescale SPI Driver");
807 MODULE_LICENSE("GPL");