2 * Freescale eSPI controller driver.
4 * Copyright 2010 Freescale Semiconductor, Inc.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
11 #include <linux/delay.h>
12 #include <linux/err.h>
13 #include <linux/fsl_devices.h>
14 #include <linux/interrupt.h>
15 #include <linux/module.h>
18 #include <linux/of_address.h>
19 #include <linux/of_irq.h>
20 #include <linux/of_platform.h>
21 #include <linux/platform_device.h>
22 #include <linux/spi/spi.h>
23 #include <linux/pm_runtime.h>
24 #include <sysdev/fsl_soc.h>
26 #include "spi-fsl-lib.h"
28 /* eSPI Controller registers */
30 __be32 mode; /* 0x000 - eSPI mode register */
31 __be32 event; /* 0x004 - eSPI event register */
32 __be32 mask; /* 0x008 - eSPI mask register */
33 __be32 command; /* 0x00c - eSPI command register */
34 __be32 transmit; /* 0x010 - eSPI transmit FIFO access register*/
35 __be32 receive; /* 0x014 - eSPI receive FIFO access register*/
36 u8 res[8]; /* 0x018 - 0x01c reserved */
37 __be32 csmode[4]; /* 0x020 - 0x02c eSPI cs mode register */
40 /* eSPI Controller mode register definitions */
41 #define SPMODE_ENABLE (1 << 31)
42 #define SPMODE_LOOP (1 << 30)
43 #define SPMODE_TXTHR(x) ((x) << 8)
44 #define SPMODE_RXTHR(x) ((x) << 0)
46 /* eSPI Controller CS mode register definitions */
47 #define CSMODE_CI_INACTIVEHIGH (1 << 31)
48 #define CSMODE_CP_BEGIN_EDGECLK (1 << 30)
49 #define CSMODE_REV (1 << 29)
50 #define CSMODE_DIV16 (1 << 28)
51 #define CSMODE_PM(x) ((x) << 24)
52 #define CSMODE_POL_1 (1 << 20)
53 #define CSMODE_LEN(x) ((x) << 16)
54 #define CSMODE_BEF(x) ((x) << 12)
55 #define CSMODE_AFT(x) ((x) << 8)
56 #define CSMODE_CG(x) ((x) << 3)
58 /* Default mode/csmode for eSPI controller */
59 #define SPMODE_INIT_VAL (SPMODE_TXTHR(4) | SPMODE_RXTHR(3))
60 #define CSMODE_INIT_VAL (CSMODE_POL_1 | CSMODE_BEF(0) \
61 | CSMODE_AFT(0) | CSMODE_CG(1))
63 /* SPIE register values */
64 #define SPIE_NE 0x00000200 /* Not empty */
65 #define SPIE_NF 0x00000100 /* Not full */
67 /* SPIM register values */
68 #define SPIM_NE 0x00000200 /* Not empty */
69 #define SPIM_NF 0x00000100 /* Not full */
70 #define SPIE_RXCNT(reg) ((reg >> 24) & 0x3F)
71 #define SPIE_TXCNT(reg) ((reg >> 16) & 0x3F)
73 /* SPCOM register values */
74 #define SPCOM_CS(x) ((x) << 30)
75 #define SPCOM_TRANLEN(x) ((x) << 0)
76 #define SPCOM_TRANLEN_MAX 0x10000 /* Max transaction length */
78 #define AUTOSUSPEND_TIMEOUT 2000
80 static unsigned int fsl_espi_copy_to_buf(struct spi_message *m,
81 struct mpc8xxx_spi *mspi)
83 unsigned int tx_only = 0;
84 struct spi_transfer *t;
85 u8 *buf = mspi->local_buf;
87 list_for_each_entry(t, &m->transfers, transfer_list) {
89 memcpy(buf, t->tx_buf, t->len);
93 memset(buf, 0, t->len);
101 static void fsl_espi_change_mode(struct spi_device *spi)
103 struct mpc8xxx_spi *mspi = spi_master_get_devdata(spi->master);
104 struct spi_mpc8xxx_cs *cs = spi->controller_state;
105 struct fsl_espi_reg *reg_base = mspi->reg_base;
106 __be32 __iomem *mode = ®_base->csmode[spi->chip_select];
107 __be32 __iomem *espi_mode = ®_base->mode;
111 /* Turn off IRQs locally to minimize time that SPI is disabled. */
112 local_irq_save(flags);
114 /* Turn off SPI unit prior changing mode */
115 tmp = mpc8xxx_spi_read_reg(espi_mode);
116 mpc8xxx_spi_write_reg(espi_mode, tmp & ~SPMODE_ENABLE);
117 mpc8xxx_spi_write_reg(mode, cs->hw_mode);
118 mpc8xxx_spi_write_reg(espi_mode, tmp);
120 local_irq_restore(flags);
123 static u32 fsl_espi_tx_buf_lsb(struct mpc8xxx_spi *mpc8xxx_spi)
128 const u32 *tx = mpc8xxx_spi->tx;
133 data = *tx++ << mpc8xxx_spi->tx_shift;
134 data_l = data & 0xffff;
135 data_h = (data >> 16) & 0xffff;
138 data = data_h | data_l;
140 mpc8xxx_spi->tx = tx;
144 static void fsl_espi_setup_transfer(struct spi_device *spi,
145 struct spi_transfer *t)
147 struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master);
148 int bits_per_word = 0;
151 struct spi_mpc8xxx_cs *cs = spi->controller_state;
154 bits_per_word = t->bits_per_word;
158 /* spi_transfer level calls that work per-word */
160 bits_per_word = spi->bits_per_word;
163 hz = spi->max_speed_hz;
167 cs->get_rx = mpc8xxx_spi_rx_buf_u32;
168 cs->get_tx = mpc8xxx_spi_tx_buf_u32;
169 if (bits_per_word <= 8) {
170 cs->rx_shift = 8 - bits_per_word;
172 cs->rx_shift = 16 - bits_per_word;
173 if (spi->mode & SPI_LSB_FIRST)
174 cs->get_tx = fsl_espi_tx_buf_lsb;
177 mpc8xxx_spi->rx_shift = cs->rx_shift;
178 mpc8xxx_spi->tx_shift = cs->tx_shift;
179 mpc8xxx_spi->get_rx = cs->get_rx;
180 mpc8xxx_spi->get_tx = cs->get_tx;
182 /* mask out bits we are going to set */
183 cs->hw_mode &= ~(CSMODE_LEN(0xF) | CSMODE_DIV16 | CSMODE_PM(0xF));
185 cs->hw_mode |= CSMODE_LEN(bits_per_word - 1);
187 if ((mpc8xxx_spi->spibrg / hz) > 64) {
188 cs->hw_mode |= CSMODE_DIV16;
189 pm = DIV_ROUND_UP(mpc8xxx_spi->spibrg, hz * 16 * 4);
191 WARN_ONCE(pm > 33, "%s: Requested speed is too low: %d Hz. "
192 "Will use %d Hz instead.\n", dev_name(&spi->dev),
193 hz, mpc8xxx_spi->spibrg / (4 * 16 * (32 + 1)));
197 pm = DIV_ROUND_UP(mpc8xxx_spi->spibrg, hz * 4);
204 cs->hw_mode |= CSMODE_PM(pm);
206 fsl_espi_change_mode(spi);
209 static void fsl_espi_cpu_bufs(struct mpc8xxx_spi *mspi, struct spi_transfer *t,
213 struct fsl_espi_reg *reg_base = mspi->reg_base;
218 mpc8xxx_spi_write_reg(®_base->mask, SPIM_NE);
221 word = mspi->get_tx(mspi);
222 mpc8xxx_spi_write_reg(®_base->transmit, word);
225 static int fsl_espi_bufs(struct spi_device *spi, struct spi_transfer *t)
227 struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master);
228 struct fsl_espi_reg *reg_base = mpc8xxx_spi->reg_base;
229 unsigned int len = t->len;
232 mpc8xxx_spi->len = t->len;
233 len = roundup(len, 4) / 4;
235 mpc8xxx_spi->tx = t->tx_buf;
236 mpc8xxx_spi->rx = t->rx_buf;
238 reinit_completion(&mpc8xxx_spi->done);
240 /* Set SPCOM[CS] and SPCOM[TRANLEN] field */
241 if (t->len > SPCOM_TRANLEN_MAX) {
242 dev_err(mpc8xxx_spi->dev, "Transaction length (%d)"
243 " beyond the SPCOM[TRANLEN] field\n", t->len);
246 mpc8xxx_spi_write_reg(®_base->command,
247 (SPCOM_CS(spi->chip_select) | SPCOM_TRANLEN(t->len - 1)));
249 fsl_espi_cpu_bufs(mpc8xxx_spi, t, len);
251 /* Won't hang up forever, SPI bus sometimes got lost interrupts... */
252 ret = wait_for_completion_timeout(&mpc8xxx_spi->done, 2 * HZ);
254 dev_err(mpc8xxx_spi->dev,
255 "Transaction hanging up (left %d bytes)\n",
258 /* disable rx ints */
259 mpc8xxx_spi_write_reg(®_base->mask, 0);
261 return mpc8xxx_spi->count > 0 ? -EMSGSIZE : 0;
264 static int fsl_espi_do_trans(struct spi_message *m, struct spi_transfer *trans)
266 struct spi_device *spi = m->spi;
267 struct mpc8xxx_spi *mspi = spi_master_get_devdata(spi->master);
268 struct spi_transfer *t, *first;
271 first = list_first_entry(&m->transfers, struct spi_transfer,
273 list_for_each_entry(t, &m->transfers, transfer_list) {
274 if ((first->bits_per_word != t->bits_per_word) ||
275 (first->speed_hz != t->speed_hz)) {
277 "bits_per_word/speed_hz should be same for the same SPI transfer\n");
281 trans->speed_hz = t->speed_hz;
282 trans->bits_per_word = t->bits_per_word;
283 trans->delay_usecs = max(first->delay_usecs, t->delay_usecs);
286 fsl_espi_setup_transfer(spi, trans);
289 ret = fsl_espi_bufs(spi, trans);
291 if (trans->delay_usecs)
292 udelay(trans->delay_usecs);
294 fsl_espi_setup_transfer(spi, NULL);
299 static int fsl_espi_trans(struct spi_message *m, struct spi_transfer *trans,
302 struct mpc8xxx_spi *mspi = spi_master_get_devdata(m->spi->master);
303 unsigned int tx_only;
306 tx_only = fsl_espi_copy_to_buf(m, mspi);
308 trans->tx_buf = mspi->local_buf;
309 trans->rx_buf = mspi->local_buf;
310 ret = fsl_espi_do_trans(m, trans);
312 /* If there is at least one RX byte then copy it to rx_buff */
313 if (!ret && rx_buff && trans->len > tx_only)
314 memcpy(rx_buff, trans->rx_buf + tx_only, trans->len - tx_only);
319 static int fsl_espi_do_one_msg(struct spi_master *master,
320 struct spi_message *m)
323 unsigned int xfer_len = 0;
324 struct spi_transfer *t, trans = {};
327 list_for_each_entry(t, &m->transfers, transfer_list) {
330 if ((t->tx_buf) || (t->rx_buf))
334 trans.len = xfer_len;
336 ret = fsl_espi_trans(m, &trans, rx_buf);
338 m->actual_length = ret ? 0 : trans.len;
340 if (m->status == -EINPROGRESS)
343 spi_finalize_current_message(master);
348 static int fsl_espi_setup(struct spi_device *spi)
350 struct mpc8xxx_spi *mpc8xxx_spi;
351 struct fsl_espi_reg *reg_base;
354 struct spi_mpc8xxx_cs *cs = spi_get_ctldata(spi);
356 if (!spi->max_speed_hz)
360 cs = kzalloc(sizeof(*cs), GFP_KERNEL);
363 spi_set_ctldata(spi, cs);
366 mpc8xxx_spi = spi_master_get_devdata(spi->master);
367 reg_base = mpc8xxx_spi->reg_base;
369 pm_runtime_get_sync(mpc8xxx_spi->dev);
371 hw_mode = cs->hw_mode; /* Save original settings */
372 cs->hw_mode = mpc8xxx_spi_read_reg(
373 ®_base->csmode[spi->chip_select]);
374 /* mask out bits we are going to set */
375 cs->hw_mode &= ~(CSMODE_CP_BEGIN_EDGECLK | CSMODE_CI_INACTIVEHIGH
378 if (spi->mode & SPI_CPHA)
379 cs->hw_mode |= CSMODE_CP_BEGIN_EDGECLK;
380 if (spi->mode & SPI_CPOL)
381 cs->hw_mode |= CSMODE_CI_INACTIVEHIGH;
382 if (!(spi->mode & SPI_LSB_FIRST))
383 cs->hw_mode |= CSMODE_REV;
385 /* Handle the loop mode */
386 loop_mode = mpc8xxx_spi_read_reg(®_base->mode);
387 loop_mode &= ~SPMODE_LOOP;
388 if (spi->mode & SPI_LOOP)
389 loop_mode |= SPMODE_LOOP;
390 mpc8xxx_spi_write_reg(®_base->mode, loop_mode);
392 fsl_espi_setup_transfer(spi, NULL);
394 pm_runtime_mark_last_busy(mpc8xxx_spi->dev);
395 pm_runtime_put_autosuspend(mpc8xxx_spi->dev);
400 static void fsl_espi_cleanup(struct spi_device *spi)
402 struct spi_mpc8xxx_cs *cs = spi_get_ctldata(spi);
405 spi_set_ctldata(spi, NULL);
408 static void fsl_espi_cpu_irq(struct mpc8xxx_spi *mspi, u32 events)
410 struct fsl_espi_reg *reg_base = mspi->reg_base;
412 /* We need handle RX first */
413 if (events & SPIE_NE) {
419 /* Spin until RX is done */
420 if (SPIE_RXCNT(events) < min(4, mspi->len)) {
421 ret = spin_event_timeout(
422 !(SPIE_RXCNT(events =
423 mpc8xxx_spi_read_reg(®_base->event)) <
425 10000, 0); /* 10 msec */
428 "tired waiting for SPIE_RXCNT\n");
431 if (mspi->len >= 4) {
432 rx_data = mpc8xxx_spi_read_reg(®_base->receive);
433 } else if (mspi->len <= 0) {
435 "unexpected RX(SPIE_NE) interrupt occurred,\n"
436 "(local rxlen %d bytes, reg rxlen %d bytes)\n",
437 min(4, mspi->len), SPIE_RXCNT(events));
440 rx_nr_bytes = mspi->len;
444 rx_data_8 = in_8((u8 *)®_base->receive);
445 rx_data |= (rx_data_8 << (tmp * 8));
448 rx_data <<= (4 - mspi->len) * 8;
451 mspi->len -= rx_nr_bytes;
454 mspi->get_rx(rx_data, mspi);
457 if (!(events & SPIE_NF)) {
460 /* spin until TX is done */
461 ret = spin_event_timeout(((events = mpc8xxx_spi_read_reg(
462 ®_base->event)) & SPIE_NF), 1000, 0);
464 dev_err(mspi->dev, "tired waiting for SPIE_NF\n");
466 /* Clear the SPIE bits */
467 mpc8xxx_spi_write_reg(®_base->event, events);
468 complete(&mspi->done);
473 /* Clear the events */
474 mpc8xxx_spi_write_reg(®_base->event, events);
478 u32 word = mspi->get_tx(mspi);
480 mpc8xxx_spi_write_reg(®_base->transmit, word);
482 complete(&mspi->done);
486 static irqreturn_t fsl_espi_irq(s32 irq, void *context_data)
488 struct mpc8xxx_spi *mspi = context_data;
489 struct fsl_espi_reg *reg_base = mspi->reg_base;
490 irqreturn_t ret = IRQ_NONE;
493 /* Get interrupt events(tx/rx) */
494 events = mpc8xxx_spi_read_reg(®_base->event);
498 dev_vdbg(mspi->dev, "%s: events %x\n", __func__, events);
500 fsl_espi_cpu_irq(mspi, events);
506 static int fsl_espi_runtime_suspend(struct device *dev)
508 struct spi_master *master = dev_get_drvdata(dev);
509 struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(master);
510 struct fsl_espi_reg *reg_base = mpc8xxx_spi->reg_base;
513 regval = mpc8xxx_spi_read_reg(®_base->mode);
514 regval &= ~SPMODE_ENABLE;
515 mpc8xxx_spi_write_reg(®_base->mode, regval);
520 static int fsl_espi_runtime_resume(struct device *dev)
522 struct spi_master *master = dev_get_drvdata(dev);
523 struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(master);
524 struct fsl_espi_reg *reg_base = mpc8xxx_spi->reg_base;
527 regval = mpc8xxx_spi_read_reg(®_base->mode);
528 regval |= SPMODE_ENABLE;
529 mpc8xxx_spi_write_reg(®_base->mode, regval);
535 static size_t fsl_espi_max_message_size(struct spi_device *spi)
537 return SPCOM_TRANLEN_MAX;
540 static struct spi_master * fsl_espi_probe(struct device *dev,
541 struct resource *mem, unsigned int irq)
543 struct fsl_spi_platform_data *pdata = dev_get_platdata(dev);
544 struct spi_master *master;
545 struct mpc8xxx_spi *mpc8xxx_spi;
546 struct fsl_espi_reg *reg_base;
547 struct device_node *nc;
552 master = spi_alloc_master(dev, sizeof(struct mpc8xxx_spi));
558 dev_set_drvdata(dev, master);
560 mpc8xxx_spi_probe(dev, mem, irq);
562 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 16);
563 master->setup = fsl_espi_setup;
564 master->cleanup = fsl_espi_cleanup;
565 master->transfer_one_message = fsl_espi_do_one_msg;
566 master->auto_runtime_pm = true;
567 master->max_message_size = fsl_espi_max_message_size;
569 mpc8xxx_spi = spi_master_get_devdata(master);
571 mpc8xxx_spi->local_buf =
572 devm_kmalloc(dev, SPCOM_TRANLEN_MAX, GFP_KERNEL);
573 if (!mpc8xxx_spi->local_buf) {
578 mpc8xxx_spi->reg_base = devm_ioremap_resource(dev, mem);
579 if (IS_ERR(mpc8xxx_spi->reg_base)) {
580 ret = PTR_ERR(mpc8xxx_spi->reg_base);
584 reg_base = mpc8xxx_spi->reg_base;
586 /* Register for SPI Interrupt */
587 ret = devm_request_irq(dev, mpc8xxx_spi->irq, fsl_espi_irq,
588 0, "fsl_espi", mpc8xxx_spi);
592 if (mpc8xxx_spi->flags & SPI_QE_CPU_MODE) {
593 mpc8xxx_spi->rx_shift = 16;
594 mpc8xxx_spi->tx_shift = 24;
597 /* SPI controller initializations */
598 mpc8xxx_spi_write_reg(®_base->mode, 0);
599 mpc8xxx_spi_write_reg(®_base->mask, 0);
600 mpc8xxx_spi_write_reg(®_base->command, 0);
601 mpc8xxx_spi_write_reg(®_base->event, 0xffffffff);
603 /* Init eSPI CS mode register */
604 for_each_available_child_of_node(master->dev.of_node, nc) {
605 /* get chip select */
606 prop = of_get_property(nc, "reg", &len);
607 if (!prop || len < sizeof(*prop))
609 i = be32_to_cpup(prop);
610 if (i < 0 || i >= pdata->max_chipselect)
613 csmode = CSMODE_INIT_VAL;
614 /* check if CSBEF is set in device tree */
615 prop = of_get_property(nc, "fsl,csbef", &len);
616 if (prop && len >= sizeof(*prop)) {
617 csmode &= ~(CSMODE_BEF(0xf));
618 csmode |= CSMODE_BEF(be32_to_cpup(prop));
620 /* check if CSAFT is set in device tree */
621 prop = of_get_property(nc, "fsl,csaft", &len);
622 if (prop && len >= sizeof(*prop)) {
623 csmode &= ~(CSMODE_AFT(0xf));
624 csmode |= CSMODE_AFT(be32_to_cpup(prop));
626 mpc8xxx_spi_write_reg(®_base->csmode[i], csmode);
628 dev_info(dev, "cs=%d, init_csmode=0x%x\n", i, csmode);
631 /* Enable SPI interface */
632 regval = pdata->initial_spmode | SPMODE_INIT_VAL | SPMODE_ENABLE;
634 mpc8xxx_spi_write_reg(®_base->mode, regval);
636 pm_runtime_set_autosuspend_delay(dev, AUTOSUSPEND_TIMEOUT);
637 pm_runtime_use_autosuspend(dev);
638 pm_runtime_set_active(dev);
639 pm_runtime_enable(dev);
640 pm_runtime_get_sync(dev);
642 ret = devm_spi_register_master(dev, master);
646 dev_info(dev, "at 0x%p (irq = %d)\n", reg_base, mpc8xxx_spi->irq);
648 pm_runtime_mark_last_busy(dev);
649 pm_runtime_put_autosuspend(dev);
654 pm_runtime_put_noidle(dev);
655 pm_runtime_disable(dev);
656 pm_runtime_set_suspended(dev);
658 spi_master_put(master);
663 static int of_fsl_espi_get_chipselects(struct device *dev)
665 struct device_node *np = dev->of_node;
666 struct fsl_spi_platform_data *pdata = dev_get_platdata(dev);
670 prop = of_get_property(np, "fsl,espi-num-chipselects", &len);
671 if (!prop || len < sizeof(*prop)) {
672 dev_err(dev, "No 'fsl,espi-num-chipselects' property\n");
676 pdata->max_chipselect = *prop;
677 pdata->cs_control = NULL;
682 static int of_fsl_espi_probe(struct platform_device *ofdev)
684 struct device *dev = &ofdev->dev;
685 struct device_node *np = ofdev->dev.of_node;
686 struct spi_master *master;
691 ret = of_mpc8xxx_spi_probe(ofdev);
695 ret = of_fsl_espi_get_chipselects(dev);
699 ret = of_address_to_resource(np, 0, &mem);
703 irq = irq_of_parse_and_map(np, 0);
709 master = fsl_espi_probe(dev, &mem, irq);
710 if (IS_ERR(master)) {
711 ret = PTR_ERR(master);
721 static int of_fsl_espi_remove(struct platform_device *dev)
723 pm_runtime_disable(&dev->dev);
728 #ifdef CONFIG_PM_SLEEP
729 static int of_fsl_espi_suspend(struct device *dev)
731 struct spi_master *master = dev_get_drvdata(dev);
734 ret = spi_master_suspend(master);
736 dev_warn(dev, "cannot suspend master\n");
740 ret = pm_runtime_force_suspend(dev);
747 static int of_fsl_espi_resume(struct device *dev)
749 struct fsl_spi_platform_data *pdata = dev_get_platdata(dev);
750 struct spi_master *master = dev_get_drvdata(dev);
751 struct mpc8xxx_spi *mpc8xxx_spi;
752 struct fsl_espi_reg *reg_base;
756 mpc8xxx_spi = spi_master_get_devdata(master);
757 reg_base = mpc8xxx_spi->reg_base;
759 /* SPI controller initializations */
760 mpc8xxx_spi_write_reg(®_base->mode, 0);
761 mpc8xxx_spi_write_reg(®_base->mask, 0);
762 mpc8xxx_spi_write_reg(®_base->command, 0);
763 mpc8xxx_spi_write_reg(®_base->event, 0xffffffff);
765 /* Init eSPI CS mode register */
766 for (i = 0; i < pdata->max_chipselect; i++)
767 mpc8xxx_spi_write_reg(®_base->csmode[i], CSMODE_INIT_VAL);
769 /* Enable SPI interface */
770 regval = pdata->initial_spmode | SPMODE_INIT_VAL | SPMODE_ENABLE;
772 mpc8xxx_spi_write_reg(®_base->mode, regval);
774 ret = pm_runtime_force_resume(dev);
778 return spi_master_resume(master);
780 #endif /* CONFIG_PM_SLEEP */
782 static const struct dev_pm_ops espi_pm = {
783 SET_RUNTIME_PM_OPS(fsl_espi_runtime_suspend,
784 fsl_espi_runtime_resume, NULL)
785 SET_SYSTEM_SLEEP_PM_OPS(of_fsl_espi_suspend, of_fsl_espi_resume)
788 static const struct of_device_id of_fsl_espi_match[] = {
789 { .compatible = "fsl,mpc8536-espi" },
792 MODULE_DEVICE_TABLE(of, of_fsl_espi_match);
794 static struct platform_driver fsl_espi_driver = {
797 .of_match_table = of_fsl_espi_match,
800 .probe = of_fsl_espi_probe,
801 .remove = of_fsl_espi_remove,
803 module_platform_driver(fsl_espi_driver);
805 MODULE_AUTHOR("Mingkai Hu");
806 MODULE_DESCRIPTION("Enhanced Freescale SPI Driver");
807 MODULE_LICENSE("GPL");