2 * Copyright (C) 2005 Stephen Street / StreetFire Sound Labs
3 * Copyright (C) 2013, Intel Corporation
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20 #include <linux/init.h>
21 #include <linux/module.h>
22 #include <linux/device.h>
23 #include <linux/ioport.h>
24 #include <linux/errno.h>
25 #include <linux/interrupt.h>
26 #include <linux/platform_device.h>
27 #include <linux/spi/pxa2xx_spi.h>
28 #include <linux/spi/spi.h>
29 #include <linux/workqueue.h>
30 #include <linux/delay.h>
31 #include <linux/gpio.h>
32 #include <linux/slab.h>
33 #include <linux/clk.h>
34 #include <linux/pm_runtime.h>
35 #include <linux/acpi.h>
39 #include <asm/delay.h>
41 #include "spi-pxa2xx.h"
43 MODULE_AUTHOR("Stephen Street");
44 MODULE_DESCRIPTION("PXA2xx SSP SPI Controller");
45 MODULE_LICENSE("GPL");
46 MODULE_ALIAS("platform:pxa2xx-spi");
50 #define TIMOUT_DFLT 1000
53 * for testing SSCR1 changes that require SSP restart, basically
54 * everything except the service and interrupt enables, the pxa270 developer
55 * manual says only SSCR1_SCFR, SSCR1_SPH, SSCR1_SPO need to be in this
56 * list, but the PXA255 dev man says all bits without really meaning the
57 * service and interrupt enables
59 #define SSCR1_CHANGE_MASK (SSCR1_TTELP | SSCR1_TTE | SSCR1_SCFR \
60 | SSCR1_ECRA | SSCR1_ECRB | SSCR1_SCLKDIR \
61 | SSCR1_SFRMDIR | SSCR1_RWOT | SSCR1_TRAIL \
62 | SSCR1_IFS | SSCR1_STRF | SSCR1_EFWR \
63 | SSCR1_RFT | SSCR1_TFT | SSCR1_MWDS \
64 | SSCR1_SPH | SSCR1_SPO | SSCR1_LBM)
66 #define LPSS_RX_THRESH_DFLT 64
67 #define LPSS_TX_LOTHRESH_DFLT 160
68 #define LPSS_TX_HITHRESH_DFLT 224
70 /* Offset from drv_data->lpss_base */
72 #define SPI_CS_CONTROL 0x18
73 #define SPI_CS_CONTROL_SW_MODE BIT(0)
74 #define SPI_CS_CONTROL_CS_HIGH BIT(1)
76 static bool is_lpss_ssp(const struct driver_data *drv_data)
78 return drv_data->ssp_type == LPSS_SSP;
82 * Read and write LPSS SSP private registers. Caller must first check that
83 * is_lpss_ssp() returns true before these can be called.
85 static u32 __lpss_ssp_read_priv(struct driver_data *drv_data, unsigned offset)
87 WARN_ON(!drv_data->lpss_base);
88 return readl(drv_data->lpss_base + offset);
91 static void __lpss_ssp_write_priv(struct driver_data *drv_data,
92 unsigned offset, u32 value)
94 WARN_ON(!drv_data->lpss_base);
95 writel(value, drv_data->lpss_base + offset);
99 * lpss_ssp_setup - perform LPSS SSP specific setup
100 * @drv_data: pointer to the driver private data
102 * Perform LPSS SSP specific setup. This function must be called first if
103 * one is going to use LPSS SSP private registers.
105 static void lpss_ssp_setup(struct driver_data *drv_data)
107 unsigned offset = 0x400;
110 if (!is_lpss_ssp(drv_data))
114 * Perform auto-detection of the LPSS SSP private registers. They
115 * can be either at 1k or 2k offset from the base address.
117 orig = readl(drv_data->ioaddr + offset + SPI_CS_CONTROL);
119 value = orig | SPI_CS_CONTROL_SW_MODE;
120 writel(value, drv_data->ioaddr + offset + SPI_CS_CONTROL);
121 value = readl(drv_data->ioaddr + offset + SPI_CS_CONTROL);
122 if (value != (orig | SPI_CS_CONTROL_SW_MODE)) {
127 value &= ~SPI_CS_CONTROL_SW_MODE;
128 writel(value, drv_data->ioaddr + offset + SPI_CS_CONTROL);
129 value = readl(drv_data->ioaddr + offset + SPI_CS_CONTROL);
136 /* Now set the LPSS base */
137 drv_data->lpss_base = drv_data->ioaddr + offset;
139 /* Enable software chip select control */
140 value = SPI_CS_CONTROL_SW_MODE | SPI_CS_CONTROL_CS_HIGH;
141 __lpss_ssp_write_priv(drv_data, SPI_CS_CONTROL, value);
143 /* Enable multiblock DMA transfers */
144 if (drv_data->master_info->enable_dma)
145 __lpss_ssp_write_priv(drv_data, SSP_REG, 1);
148 static void lpss_ssp_cs_control(struct driver_data *drv_data, bool enable)
152 if (!is_lpss_ssp(drv_data))
155 value = __lpss_ssp_read_priv(drv_data, SPI_CS_CONTROL);
157 value &= ~SPI_CS_CONTROL_CS_HIGH;
159 value |= SPI_CS_CONTROL_CS_HIGH;
160 __lpss_ssp_write_priv(drv_data, SPI_CS_CONTROL, value);
163 static void cs_assert(struct driver_data *drv_data)
165 struct chip_data *chip = drv_data->cur_chip;
167 if (drv_data->ssp_type == CE4100_SSP) {
168 write_SSSR(drv_data->cur_chip->frm, drv_data->ioaddr);
172 if (chip->cs_control) {
173 chip->cs_control(PXA2XX_CS_ASSERT);
177 if (gpio_is_valid(chip->gpio_cs)) {
178 gpio_set_value(chip->gpio_cs, chip->gpio_cs_inverted);
182 lpss_ssp_cs_control(drv_data, true);
185 static void cs_deassert(struct driver_data *drv_data)
187 struct chip_data *chip = drv_data->cur_chip;
189 if (drv_data->ssp_type == CE4100_SSP)
192 if (chip->cs_control) {
193 chip->cs_control(PXA2XX_CS_DEASSERT);
197 if (gpio_is_valid(chip->gpio_cs)) {
198 gpio_set_value(chip->gpio_cs, !chip->gpio_cs_inverted);
202 lpss_ssp_cs_control(drv_data, false);
205 int pxa2xx_spi_flush(struct driver_data *drv_data)
207 unsigned long limit = loops_per_jiffy << 1;
209 void __iomem *reg = drv_data->ioaddr;
212 while (read_SSSR(reg) & SSSR_RNE) {
215 } while ((read_SSSR(reg) & SSSR_BSY) && --limit);
216 write_SSSR_CS(drv_data, SSSR_ROR);
221 static int null_writer(struct driver_data *drv_data)
223 void __iomem *reg = drv_data->ioaddr;
224 u8 n_bytes = drv_data->n_bytes;
226 if (((read_SSSR(reg) & SSSR_TFL_MASK) == SSSR_TFL_MASK)
227 || (drv_data->tx == drv_data->tx_end))
231 drv_data->tx += n_bytes;
236 static int null_reader(struct driver_data *drv_data)
238 void __iomem *reg = drv_data->ioaddr;
239 u8 n_bytes = drv_data->n_bytes;
241 while ((read_SSSR(reg) & SSSR_RNE)
242 && (drv_data->rx < drv_data->rx_end)) {
244 drv_data->rx += n_bytes;
247 return drv_data->rx == drv_data->rx_end;
250 static int u8_writer(struct driver_data *drv_data)
252 void __iomem *reg = drv_data->ioaddr;
254 if (((read_SSSR(reg) & SSSR_TFL_MASK) == SSSR_TFL_MASK)
255 || (drv_data->tx == drv_data->tx_end))
258 write_SSDR(*(u8 *)(drv_data->tx), reg);
264 static int u8_reader(struct driver_data *drv_data)
266 void __iomem *reg = drv_data->ioaddr;
268 while ((read_SSSR(reg) & SSSR_RNE)
269 && (drv_data->rx < drv_data->rx_end)) {
270 *(u8 *)(drv_data->rx) = read_SSDR(reg);
274 return drv_data->rx == drv_data->rx_end;
277 static int u16_writer(struct driver_data *drv_data)
279 void __iomem *reg = drv_data->ioaddr;
281 if (((read_SSSR(reg) & SSSR_TFL_MASK) == SSSR_TFL_MASK)
282 || (drv_data->tx == drv_data->tx_end))
285 write_SSDR(*(u16 *)(drv_data->tx), reg);
291 static int u16_reader(struct driver_data *drv_data)
293 void __iomem *reg = drv_data->ioaddr;
295 while ((read_SSSR(reg) & SSSR_RNE)
296 && (drv_data->rx < drv_data->rx_end)) {
297 *(u16 *)(drv_data->rx) = read_SSDR(reg);
301 return drv_data->rx == drv_data->rx_end;
304 static int u32_writer(struct driver_data *drv_data)
306 void __iomem *reg = drv_data->ioaddr;
308 if (((read_SSSR(reg) & SSSR_TFL_MASK) == SSSR_TFL_MASK)
309 || (drv_data->tx == drv_data->tx_end))
312 write_SSDR(*(u32 *)(drv_data->tx), reg);
318 static int u32_reader(struct driver_data *drv_data)
320 void __iomem *reg = drv_data->ioaddr;
322 while ((read_SSSR(reg) & SSSR_RNE)
323 && (drv_data->rx < drv_data->rx_end)) {
324 *(u32 *)(drv_data->rx) = read_SSDR(reg);
328 return drv_data->rx == drv_data->rx_end;
331 void *pxa2xx_spi_next_transfer(struct driver_data *drv_data)
333 struct spi_message *msg = drv_data->cur_msg;
334 struct spi_transfer *trans = drv_data->cur_transfer;
336 /* Move to next transfer */
337 if (trans->transfer_list.next != &msg->transfers) {
338 drv_data->cur_transfer =
339 list_entry(trans->transfer_list.next,
342 return RUNNING_STATE;
347 /* caller already set message->status; dma and pio irqs are blocked */
348 static void giveback(struct driver_data *drv_data)
350 struct spi_transfer* last_transfer;
351 struct spi_message *msg;
353 msg = drv_data->cur_msg;
354 drv_data->cur_msg = NULL;
355 drv_data->cur_transfer = NULL;
357 last_transfer = list_entry(msg->transfers.prev,
361 /* Delay if requested before any change in chip select */
362 if (last_transfer->delay_usecs)
363 udelay(last_transfer->delay_usecs);
365 /* Drop chip select UNLESS cs_change is true or we are returning
366 * a message with an error, or next message is for another chip
368 if (!last_transfer->cs_change)
369 cs_deassert(drv_data);
371 struct spi_message *next_msg;
373 /* Holding of cs was hinted, but we need to make sure
374 * the next message is for the same chip. Don't waste
375 * time with the following tests unless this was hinted.
377 * We cannot postpone this until pump_messages, because
378 * after calling msg->complete (below) the driver that
379 * sent the current message could be unloaded, which
380 * could invalidate the cs_control() callback...
383 /* get a pointer to the next message, if any */
384 next_msg = spi_get_next_queued_message(drv_data->master);
386 /* see if the next and current messages point
389 if (next_msg && next_msg->spi != msg->spi)
391 if (!next_msg || msg->state == ERROR_STATE)
392 cs_deassert(drv_data);
395 spi_finalize_current_message(drv_data->master);
396 drv_data->cur_chip = NULL;
399 static void reset_sccr1(struct driver_data *drv_data)
401 void __iomem *reg = drv_data->ioaddr;
402 struct chip_data *chip = drv_data->cur_chip;
405 sccr1_reg = read_SSCR1(reg) & ~drv_data->int_cr1;
406 sccr1_reg &= ~SSCR1_RFT;
407 sccr1_reg |= chip->threshold;
408 write_SSCR1(sccr1_reg, reg);
411 static void int_error_stop(struct driver_data *drv_data, const char* msg)
413 void __iomem *reg = drv_data->ioaddr;
415 /* Stop and reset SSP */
416 write_SSSR_CS(drv_data, drv_data->clear_sr);
417 reset_sccr1(drv_data);
418 if (!pxa25x_ssp_comp(drv_data))
420 pxa2xx_spi_flush(drv_data);
421 write_SSCR0(read_SSCR0(reg) & ~SSCR0_SSE, reg);
423 dev_err(&drv_data->pdev->dev, "%s\n", msg);
425 drv_data->cur_msg->state = ERROR_STATE;
426 tasklet_schedule(&drv_data->pump_transfers);
429 static void int_transfer_complete(struct driver_data *drv_data)
431 void __iomem *reg = drv_data->ioaddr;
434 write_SSSR_CS(drv_data, drv_data->clear_sr);
435 reset_sccr1(drv_data);
436 if (!pxa25x_ssp_comp(drv_data))
439 /* Update total byte transferred return count actual bytes read */
440 drv_data->cur_msg->actual_length += drv_data->len -
441 (drv_data->rx_end - drv_data->rx);
443 /* Transfer delays and chip select release are
444 * handled in pump_transfers or giveback
447 /* Move to next transfer */
448 drv_data->cur_msg->state = pxa2xx_spi_next_transfer(drv_data);
450 /* Schedule transfer tasklet */
451 tasklet_schedule(&drv_data->pump_transfers);
454 static irqreturn_t interrupt_transfer(struct driver_data *drv_data)
456 void __iomem *reg = drv_data->ioaddr;
458 u32 irq_mask = (read_SSCR1(reg) & SSCR1_TIE) ?
459 drv_data->mask_sr : drv_data->mask_sr & ~SSSR_TFS;
461 u32 irq_status = read_SSSR(reg) & irq_mask;
463 if (irq_status & SSSR_ROR) {
464 int_error_stop(drv_data, "interrupt_transfer: fifo overrun");
468 if (irq_status & SSSR_TINT) {
469 write_SSSR(SSSR_TINT, reg);
470 if (drv_data->read(drv_data)) {
471 int_transfer_complete(drv_data);
476 /* Drain rx fifo, Fill tx fifo and prevent overruns */
478 if (drv_data->read(drv_data)) {
479 int_transfer_complete(drv_data);
482 } while (drv_data->write(drv_data));
484 if (drv_data->read(drv_data)) {
485 int_transfer_complete(drv_data);
489 if (drv_data->tx == drv_data->tx_end) {
493 sccr1_reg = read_SSCR1(reg);
494 sccr1_reg &= ~SSCR1_TIE;
497 * PXA25x_SSP has no timeout, set up rx threshould for the
498 * remaining RX bytes.
500 if (pxa25x_ssp_comp(drv_data)) {
502 sccr1_reg &= ~SSCR1_RFT;
504 bytes_left = drv_data->rx_end - drv_data->rx;
505 switch (drv_data->n_bytes) {
512 if (bytes_left > RX_THRESH_DFLT)
513 bytes_left = RX_THRESH_DFLT;
515 sccr1_reg |= SSCR1_RxTresh(bytes_left);
517 write_SSCR1(sccr1_reg, reg);
520 /* We did something */
524 static irqreturn_t ssp_int(int irq, void *dev_id)
526 struct driver_data *drv_data = dev_id;
527 void __iomem *reg = drv_data->ioaddr;
529 u32 mask = drv_data->mask_sr;
533 * The IRQ might be shared with other peripherals so we must first
534 * check that are we RPM suspended or not. If we are we assume that
535 * the IRQ was not for us (we shouldn't be RPM suspended when the
536 * interrupt is enabled).
538 if (pm_runtime_suspended(&drv_data->pdev->dev))
541 sccr1_reg = read_SSCR1(reg);
542 status = read_SSSR(reg);
544 /* Ignore possible writes if we don't need to write */
545 if (!(sccr1_reg & SSCR1_TIE))
548 if (!(status & mask))
551 if (!drv_data->cur_msg) {
553 write_SSCR0(read_SSCR0(reg) & ~SSCR0_SSE, reg);
554 write_SSCR1(read_SSCR1(reg) & ~drv_data->int_cr1, reg);
555 if (!pxa25x_ssp_comp(drv_data))
557 write_SSSR_CS(drv_data, drv_data->clear_sr);
559 dev_err(&drv_data->pdev->dev, "bad message state "
560 "in interrupt handler\n");
566 return drv_data->transfer_handler(drv_data);
569 static unsigned int ssp_get_clk_div(struct driver_data *drv_data, int rate)
571 unsigned long ssp_clk = drv_data->max_clk_rate;
572 const struct ssp_device *ssp = drv_data->ssp;
574 rate = min_t(int, ssp_clk, rate);
576 if (ssp->type == PXA25x_SSP || ssp->type == CE4100_SSP)
577 return ((ssp_clk / (2 * rate) - 1) & 0xff) << 8;
579 return ((ssp_clk / rate - 1) & 0xfff) << 8;
582 static void pump_transfers(unsigned long data)
584 struct driver_data *drv_data = (struct driver_data *)data;
585 struct spi_message *message = NULL;
586 struct spi_transfer *transfer = NULL;
587 struct spi_transfer *previous = NULL;
588 struct chip_data *chip = NULL;
589 void __iomem *reg = drv_data->ioaddr;
595 u32 dma_thresh = drv_data->cur_chip->dma_threshold;
596 u32 dma_burst = drv_data->cur_chip->dma_burst_size;
598 /* Get current state information */
599 message = drv_data->cur_msg;
600 transfer = drv_data->cur_transfer;
601 chip = drv_data->cur_chip;
603 /* Handle for abort */
604 if (message->state == ERROR_STATE) {
605 message->status = -EIO;
610 /* Handle end of message */
611 if (message->state == DONE_STATE) {
617 /* Delay if requested at end of transfer before CS change */
618 if (message->state == RUNNING_STATE) {
619 previous = list_entry(transfer->transfer_list.prev,
622 if (previous->delay_usecs)
623 udelay(previous->delay_usecs);
625 /* Drop chip select only if cs_change is requested */
626 if (previous->cs_change)
627 cs_deassert(drv_data);
630 /* Check if we can DMA this transfer */
631 if (!pxa2xx_spi_dma_is_possible(transfer->len) && chip->enable_dma) {
633 /* reject already-mapped transfers; PIO won't always work */
634 if (message->is_dma_mapped
635 || transfer->rx_dma || transfer->tx_dma) {
636 dev_err(&drv_data->pdev->dev,
637 "pump_transfers: mapped transfer length "
638 "of %u is greater than %d\n",
639 transfer->len, MAX_DMA_LEN);
640 message->status = -EINVAL;
645 /* warn ... we force this to PIO mode */
646 if (printk_ratelimit())
647 dev_warn(&message->spi->dev, "pump_transfers: "
648 "DMA disabled for transfer length %ld "
650 (long)drv_data->len, MAX_DMA_LEN);
653 /* Setup the transfer state based on the type of transfer */
654 if (pxa2xx_spi_flush(drv_data) == 0) {
655 dev_err(&drv_data->pdev->dev, "pump_transfers: flush failed\n");
656 message->status = -EIO;
660 drv_data->n_bytes = chip->n_bytes;
661 drv_data->tx = (void *)transfer->tx_buf;
662 drv_data->tx_end = drv_data->tx + transfer->len;
663 drv_data->rx = transfer->rx_buf;
664 drv_data->rx_end = drv_data->rx + transfer->len;
665 drv_data->rx_dma = transfer->rx_dma;
666 drv_data->tx_dma = transfer->tx_dma;
667 drv_data->len = transfer->len;
668 drv_data->write = drv_data->tx ? chip->write : null_writer;
669 drv_data->read = drv_data->rx ? chip->read : null_reader;
671 /* Change speed and bit per word on a per transfer */
673 if (transfer->speed_hz || transfer->bits_per_word) {
675 bits = chip->bits_per_word;
676 speed = chip->speed_hz;
678 if (transfer->speed_hz)
679 speed = transfer->speed_hz;
681 if (transfer->bits_per_word)
682 bits = transfer->bits_per_word;
684 clk_div = ssp_get_clk_div(drv_data, speed);
687 drv_data->n_bytes = 1;
688 drv_data->read = drv_data->read != null_reader ?
689 u8_reader : null_reader;
690 drv_data->write = drv_data->write != null_writer ?
691 u8_writer : null_writer;
692 } else if (bits <= 16) {
693 drv_data->n_bytes = 2;
694 drv_data->read = drv_data->read != null_reader ?
695 u16_reader : null_reader;
696 drv_data->write = drv_data->write != null_writer ?
697 u16_writer : null_writer;
698 } else if (bits <= 32) {
699 drv_data->n_bytes = 4;
700 drv_data->read = drv_data->read != null_reader ?
701 u32_reader : null_reader;
702 drv_data->write = drv_data->write != null_writer ?
703 u32_writer : null_writer;
705 /* if bits/word is changed in dma mode, then must check the
706 * thresholds and burst also */
707 if (chip->enable_dma) {
708 if (pxa2xx_spi_set_dma_burst_and_threshold(chip,
712 if (printk_ratelimit())
713 dev_warn(&message->spi->dev,
715 "DMA burst size reduced to "
716 "match bits_per_word\n");
721 | SSCR0_DataSize(bits > 16 ? bits - 16 : bits)
723 | (bits > 16 ? SSCR0_EDSS : 0);
726 message->state = RUNNING_STATE;
728 drv_data->dma_mapped = 0;
729 if (pxa2xx_spi_dma_is_possible(drv_data->len))
730 drv_data->dma_mapped = pxa2xx_spi_map_dma_buffers(drv_data);
731 if (drv_data->dma_mapped) {
733 /* Ensure we have the correct interrupt handler */
734 drv_data->transfer_handler = pxa2xx_spi_dma_transfer;
736 pxa2xx_spi_dma_prepare(drv_data, dma_burst);
738 /* Clear status and start DMA engine */
739 cr1 = chip->cr1 | dma_thresh | drv_data->dma_cr1;
740 write_SSSR(drv_data->clear_sr, reg);
742 pxa2xx_spi_dma_start(drv_data);
744 /* Ensure we have the correct interrupt handler */
745 drv_data->transfer_handler = interrupt_transfer;
748 cr1 = chip->cr1 | chip->threshold | drv_data->int_cr1;
749 write_SSSR_CS(drv_data, drv_data->clear_sr);
752 if (is_lpss_ssp(drv_data)) {
753 if ((read_SSIRF(reg) & 0xff) != chip->lpss_rx_threshold)
754 write_SSIRF(chip->lpss_rx_threshold, reg);
755 if ((read_SSITF(reg) & 0xffff) != chip->lpss_tx_threshold)
756 write_SSITF(chip->lpss_tx_threshold, reg);
759 /* see if we need to reload the config registers */
760 if ((read_SSCR0(reg) != cr0)
761 || (read_SSCR1(reg) & SSCR1_CHANGE_MASK) !=
762 (cr1 & SSCR1_CHANGE_MASK)) {
764 /* stop the SSP, and update the other bits */
765 write_SSCR0(cr0 & ~SSCR0_SSE, reg);
766 if (!pxa25x_ssp_comp(drv_data))
767 write_SSTO(chip->timeout, reg);
768 /* first set CR1 without interrupt and service enables */
769 write_SSCR1(cr1 & SSCR1_CHANGE_MASK, reg);
770 /* restart the SSP */
771 write_SSCR0(cr0, reg);
774 if (!pxa25x_ssp_comp(drv_data))
775 write_SSTO(chip->timeout, reg);
780 /* after chip select, release the data by enabling service
781 * requests and interrupts, without changing any mode bits */
782 write_SSCR1(cr1, reg);
785 static int pxa2xx_spi_transfer_one_message(struct spi_master *master,
786 struct spi_message *msg)
788 struct driver_data *drv_data = spi_master_get_devdata(master);
790 drv_data->cur_msg = msg;
791 /* Initial message state*/
792 drv_data->cur_msg->state = START_STATE;
793 drv_data->cur_transfer = list_entry(drv_data->cur_msg->transfers.next,
797 /* prepare to setup the SSP, in pump_transfers, using the per
798 * chip configuration */
799 drv_data->cur_chip = spi_get_ctldata(drv_data->cur_msg->spi);
801 /* Mark as busy and launch transfers */
802 tasklet_schedule(&drv_data->pump_transfers);
806 static int pxa2xx_spi_prepare_transfer(struct spi_master *master)
808 struct driver_data *drv_data = spi_master_get_devdata(master);
810 pm_runtime_get_sync(&drv_data->pdev->dev);
814 static int pxa2xx_spi_unprepare_transfer(struct spi_master *master)
816 struct driver_data *drv_data = spi_master_get_devdata(master);
818 /* Disable the SSP now */
819 write_SSCR0(read_SSCR0(drv_data->ioaddr) & ~SSCR0_SSE,
822 pm_runtime_mark_last_busy(&drv_data->pdev->dev);
823 pm_runtime_put_autosuspend(&drv_data->pdev->dev);
827 static int setup_cs(struct spi_device *spi, struct chip_data *chip,
828 struct pxa2xx_spi_chip *chip_info)
832 if (chip == NULL || chip_info == NULL)
835 /* NOTE: setup() can be called multiple times, possibly with
836 * different chip_info, release previously requested GPIO
838 if (gpio_is_valid(chip->gpio_cs))
839 gpio_free(chip->gpio_cs);
841 /* If (*cs_control) is provided, ignore GPIO chip select */
842 if (chip_info->cs_control) {
843 chip->cs_control = chip_info->cs_control;
847 if (gpio_is_valid(chip_info->gpio_cs)) {
848 err = gpio_request(chip_info->gpio_cs, "SPI_CS");
850 dev_err(&spi->dev, "failed to request chip select "
851 "GPIO%d\n", chip_info->gpio_cs);
855 chip->gpio_cs = chip_info->gpio_cs;
856 chip->gpio_cs_inverted = spi->mode & SPI_CS_HIGH;
858 err = gpio_direction_output(chip->gpio_cs,
859 !chip->gpio_cs_inverted);
865 static int setup(struct spi_device *spi)
867 struct pxa2xx_spi_chip *chip_info = NULL;
868 struct chip_data *chip;
869 struct driver_data *drv_data = spi_master_get_devdata(spi->master);
870 unsigned int clk_div;
871 uint tx_thres, tx_hi_thres, rx_thres;
873 if (is_lpss_ssp(drv_data)) {
874 tx_thres = LPSS_TX_LOTHRESH_DFLT;
875 tx_hi_thres = LPSS_TX_HITHRESH_DFLT;
876 rx_thres = LPSS_RX_THRESH_DFLT;
878 tx_thres = TX_THRESH_DFLT;
880 rx_thres = RX_THRESH_DFLT;
883 if (!pxa25x_ssp_comp(drv_data)
884 && (spi->bits_per_word < 4 || spi->bits_per_word > 32)) {
885 dev_err(&spi->dev, "failed setup: ssp_type=%d, bits/wrd=%d "
886 "b/w not 4-32 for type non-PXA25x_SSP\n",
887 drv_data->ssp_type, spi->bits_per_word);
889 } else if (pxa25x_ssp_comp(drv_data)
890 && (spi->bits_per_word < 4
891 || spi->bits_per_word > 16)) {
892 dev_err(&spi->dev, "failed setup: ssp_type=%d, bits/wrd=%d "
893 "b/w not 4-16 for type PXA25x_SSP\n",
894 drv_data->ssp_type, spi->bits_per_word);
898 /* Only alloc on first setup */
899 chip = spi_get_ctldata(spi);
901 chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL);
904 "failed setup: can't allocate chip data\n");
908 if (drv_data->ssp_type == CE4100_SSP) {
909 if (spi->chip_select > 4) {
910 dev_err(&spi->dev, "failed setup: "
911 "cs number must not be > 4.\n");
916 chip->frm = spi->chip_select;
919 chip->enable_dma = 0;
920 chip->timeout = TIMOUT_DFLT;
923 /* protocol drivers may change the chip settings, so...
924 * if chip_info exists, use it */
925 chip_info = spi->controller_data;
927 /* chip_info isn't always needed */
930 if (chip_info->timeout)
931 chip->timeout = chip_info->timeout;
932 if (chip_info->tx_threshold)
933 tx_thres = chip_info->tx_threshold;
934 if (chip_info->tx_hi_threshold)
935 tx_hi_thres = chip_info->tx_hi_threshold;
936 if (chip_info->rx_threshold)
937 rx_thres = chip_info->rx_threshold;
938 chip->enable_dma = drv_data->master_info->enable_dma;
939 chip->dma_threshold = 0;
940 if (chip_info->enable_loopback)
941 chip->cr1 = SSCR1_LBM;
942 } else if (ACPI_HANDLE(&spi->dev)) {
944 * Slave devices enumerated from ACPI namespace don't
945 * usually have chip_info but we still might want to use
948 chip->enable_dma = drv_data->master_info->enable_dma;
951 chip->threshold = (SSCR1_RxTresh(rx_thres) & SSCR1_RFT) |
952 (SSCR1_TxTresh(tx_thres) & SSCR1_TFT);
954 chip->lpss_rx_threshold = SSIRF_RxThresh(rx_thres);
955 chip->lpss_tx_threshold = SSITF_TxLoThresh(tx_thres)
956 | SSITF_TxHiThresh(tx_hi_thres);
958 /* set dma burst and threshold outside of chip_info path so that if
959 * chip_info goes away after setting chip->enable_dma, the
960 * burst and threshold can still respond to changes in bits_per_word */
961 if (chip->enable_dma) {
962 /* set up legal burst and threshold for dma */
963 if (pxa2xx_spi_set_dma_burst_and_threshold(chip, spi,
965 &chip->dma_burst_size,
966 &chip->dma_threshold)) {
967 dev_warn(&spi->dev, "in setup: DMA burst size reduced "
968 "to match bits_per_word\n");
972 clk_div = ssp_get_clk_div(drv_data, spi->max_speed_hz);
973 chip->speed_hz = spi->max_speed_hz;
977 | SSCR0_DataSize(spi->bits_per_word > 16 ?
978 spi->bits_per_word - 16 : spi->bits_per_word)
980 | (spi->bits_per_word > 16 ? SSCR0_EDSS : 0);
981 chip->cr1 &= ~(SSCR1_SPO | SSCR1_SPH);
982 chip->cr1 |= (((spi->mode & SPI_CPHA) != 0) ? SSCR1_SPH : 0)
983 | (((spi->mode & SPI_CPOL) != 0) ? SSCR1_SPO : 0);
985 if (spi->mode & SPI_LOOP)
986 chip->cr1 |= SSCR1_LBM;
988 /* NOTE: PXA25x_SSP _could_ use external clocking ... */
989 if (!pxa25x_ssp_comp(drv_data))
990 dev_dbg(&spi->dev, "%ld Hz actual, %s\n",
991 drv_data->max_clk_rate
992 / (1 + ((chip->cr0 & SSCR0_SCR(0xfff)) >> 8)),
993 chip->enable_dma ? "DMA" : "PIO");
995 dev_dbg(&spi->dev, "%ld Hz actual, %s\n",
996 drv_data->max_clk_rate / 2
997 / (1 + ((chip->cr0 & SSCR0_SCR(0x0ff)) >> 8)),
998 chip->enable_dma ? "DMA" : "PIO");
1000 if (spi->bits_per_word <= 8) {
1002 chip->read = u8_reader;
1003 chip->write = u8_writer;
1004 } else if (spi->bits_per_word <= 16) {
1006 chip->read = u16_reader;
1007 chip->write = u16_writer;
1008 } else if (spi->bits_per_word <= 32) {
1009 chip->cr0 |= SSCR0_EDSS;
1011 chip->read = u32_reader;
1012 chip->write = u32_writer;
1014 dev_err(&spi->dev, "invalid wordsize\n");
1017 chip->bits_per_word = spi->bits_per_word;
1019 spi_set_ctldata(spi, chip);
1021 if (drv_data->ssp_type == CE4100_SSP)
1024 return setup_cs(spi, chip, chip_info);
1027 static void cleanup(struct spi_device *spi)
1029 struct chip_data *chip = spi_get_ctldata(spi);
1030 struct driver_data *drv_data = spi_master_get_devdata(spi->master);
1035 if (drv_data->ssp_type != CE4100_SSP && gpio_is_valid(chip->gpio_cs))
1036 gpio_free(chip->gpio_cs);
1042 static int pxa2xx_spi_acpi_add_dma(struct acpi_resource *res, void *data)
1044 struct pxa2xx_spi_master *pdata = data;
1046 if (res->type == ACPI_RESOURCE_TYPE_FIXED_DMA) {
1047 const struct acpi_resource_fixed_dma *dma;
1049 dma = &res->data.fixed_dma;
1050 if (pdata->tx_slave_id < 0) {
1051 pdata->tx_slave_id = dma->request_lines;
1052 pdata->tx_chan_id = dma->channels;
1053 } else if (pdata->rx_slave_id < 0) {
1054 pdata->rx_slave_id = dma->request_lines;
1055 pdata->rx_chan_id = dma->channels;
1059 /* Tell the ACPI core to skip this resource */
1063 static struct pxa2xx_spi_master *
1064 pxa2xx_spi_acpi_get_pdata(struct platform_device *pdev)
1066 struct pxa2xx_spi_master *pdata;
1067 struct list_head resource_list;
1068 struct acpi_device *adev;
1069 struct ssp_device *ssp;
1070 struct resource *res;
1073 if (!ACPI_HANDLE(&pdev->dev) ||
1074 acpi_bus_get_device(ACPI_HANDLE(&pdev->dev), &adev))
1077 pdata = devm_kzalloc(&pdev->dev, sizeof(*ssp), GFP_KERNEL);
1080 "failed to allocate memory for platform data\n");
1084 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1090 ssp->phys_base = res->start;
1091 ssp->mmio_base = devm_request_and_ioremap(&pdev->dev, res);
1092 if (!ssp->mmio_base) {
1093 dev_err(&pdev->dev, "failed to ioremap mmio_base\n");
1097 ssp->clk = devm_clk_get(&pdev->dev, NULL);
1098 ssp->irq = platform_get_irq(pdev, 0);
1099 ssp->type = LPSS_SSP;
1103 if (adev->pnp.unique_id && !kstrtoint(adev->pnp.unique_id, 0, &devid))
1104 ssp->port_id = devid;
1106 pdata->num_chipselect = 1;
1107 pdata->rx_slave_id = -1;
1108 pdata->tx_slave_id = -1;
1110 INIT_LIST_HEAD(&resource_list);
1111 acpi_dev_get_resources(adev, &resource_list, pxa2xx_spi_acpi_add_dma,
1113 acpi_dev_free_resource_list(&resource_list);
1115 pdata->enable_dma = pdata->rx_slave_id >= 0 && pdata->tx_slave_id >= 0;
1120 static struct acpi_device_id pxa2xx_spi_acpi_match[] = {
1125 MODULE_DEVICE_TABLE(acpi, pxa2xx_spi_acpi_match);
1127 static inline struct pxa2xx_spi_master *
1128 pxa2xx_spi_acpi_get_pdata(struct platform_device *pdev)
1134 static int pxa2xx_spi_probe(struct platform_device *pdev)
1136 struct device *dev = &pdev->dev;
1137 struct pxa2xx_spi_master *platform_info;
1138 struct spi_master *master;
1139 struct driver_data *drv_data;
1140 struct ssp_device *ssp;
1143 platform_info = dev_get_platdata(dev);
1144 if (!platform_info) {
1145 platform_info = pxa2xx_spi_acpi_get_pdata(pdev);
1146 if (!platform_info) {
1147 dev_err(&pdev->dev, "missing platform data\n");
1152 ssp = pxa_ssp_request(pdev->id, pdev->name);
1154 ssp = &platform_info->ssp;
1156 if (!ssp->mmio_base) {
1157 dev_err(&pdev->dev, "failed to get ssp\n");
1161 /* Allocate master with space for drv_data and null dma buffer */
1162 master = spi_alloc_master(dev, sizeof(struct driver_data) + 16);
1164 dev_err(&pdev->dev, "cannot alloc spi_master\n");
1168 drv_data = spi_master_get_devdata(master);
1169 drv_data->master = master;
1170 drv_data->master_info = platform_info;
1171 drv_data->pdev = pdev;
1172 drv_data->ssp = ssp;
1174 master->dev.parent = &pdev->dev;
1175 master->dev.of_node = pdev->dev.of_node;
1176 ACPI_HANDLE_SET(&master->dev, ACPI_HANDLE(&pdev->dev));
1177 /* the spi->mode bits understood by this driver: */
1178 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LOOP;
1180 master->bus_num = ssp->port_id;
1181 master->num_chipselect = platform_info->num_chipselect;
1182 master->dma_alignment = DMA_ALIGNMENT;
1183 master->cleanup = cleanup;
1184 master->setup = setup;
1185 master->transfer_one_message = pxa2xx_spi_transfer_one_message;
1186 master->prepare_transfer_hardware = pxa2xx_spi_prepare_transfer;
1187 master->unprepare_transfer_hardware = pxa2xx_spi_unprepare_transfer;
1189 drv_data->ssp_type = ssp->type;
1190 drv_data->null_dma_buf = (u32 *)PTR_ALIGN(&drv_data[1], DMA_ALIGNMENT);
1192 drv_data->ioaddr = ssp->mmio_base;
1193 drv_data->ssdr_physical = ssp->phys_base + SSDR;
1194 if (pxa25x_ssp_comp(drv_data)) {
1195 drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE;
1196 drv_data->dma_cr1 = 0;
1197 drv_data->clear_sr = SSSR_ROR;
1198 drv_data->mask_sr = SSSR_RFS | SSSR_TFS | SSSR_ROR;
1200 drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE | SSCR1_TINTE;
1201 drv_data->dma_cr1 = DEFAULT_DMA_CR1;
1202 drv_data->clear_sr = SSSR_ROR | SSSR_TINT;
1203 drv_data->mask_sr = SSSR_TINT | SSSR_RFS | SSSR_TFS | SSSR_ROR;
1206 status = request_irq(ssp->irq, ssp_int, IRQF_SHARED, dev_name(dev),
1209 dev_err(&pdev->dev, "cannot get IRQ %d\n", ssp->irq);
1210 goto out_error_master_alloc;
1213 /* Setup DMA if requested */
1214 drv_data->tx_channel = -1;
1215 drv_data->rx_channel = -1;
1216 if (platform_info->enable_dma) {
1217 status = pxa2xx_spi_dma_setup(drv_data);
1219 dev_warn(dev, "failed to setup DMA, using PIO\n");
1220 platform_info->enable_dma = false;
1224 /* Enable SOC clock */
1225 clk_prepare_enable(ssp->clk);
1227 drv_data->max_clk_rate = clk_get_rate(ssp->clk);
1229 /* Load default SSP configuration */
1230 write_SSCR0(0, drv_data->ioaddr);
1231 write_SSCR1(SSCR1_RxTresh(RX_THRESH_DFLT) |
1232 SSCR1_TxTresh(TX_THRESH_DFLT),
1234 write_SSCR0(SSCR0_SCR(2)
1236 | SSCR0_DataSize(8),
1238 if (!pxa25x_ssp_comp(drv_data))
1239 write_SSTO(0, drv_data->ioaddr);
1240 write_SSPSP(0, drv_data->ioaddr);
1242 lpss_ssp_setup(drv_data);
1244 tasklet_init(&drv_data->pump_transfers, pump_transfers,
1245 (unsigned long)drv_data);
1247 /* Register with the SPI framework */
1248 platform_set_drvdata(pdev, drv_data);
1249 status = spi_register_master(master);
1251 dev_err(&pdev->dev, "problem registering spi master\n");
1252 goto out_error_clock_enabled;
1255 pm_runtime_set_autosuspend_delay(&pdev->dev, 50);
1256 pm_runtime_use_autosuspend(&pdev->dev);
1257 pm_runtime_set_active(&pdev->dev);
1258 pm_runtime_enable(&pdev->dev);
1262 out_error_clock_enabled:
1263 clk_disable_unprepare(ssp->clk);
1264 pxa2xx_spi_dma_release(drv_data);
1265 free_irq(ssp->irq, drv_data);
1267 out_error_master_alloc:
1268 spi_master_put(master);
1273 static int pxa2xx_spi_remove(struct platform_device *pdev)
1275 struct driver_data *drv_data = platform_get_drvdata(pdev);
1276 struct ssp_device *ssp;
1280 ssp = drv_data->ssp;
1282 pm_runtime_get_sync(&pdev->dev);
1284 /* Disable the SSP at the peripheral and SOC level */
1285 write_SSCR0(0, drv_data->ioaddr);
1286 clk_disable_unprepare(ssp->clk);
1289 if (drv_data->master_info->enable_dma)
1290 pxa2xx_spi_dma_release(drv_data);
1292 pm_runtime_put_noidle(&pdev->dev);
1293 pm_runtime_disable(&pdev->dev);
1296 free_irq(ssp->irq, drv_data);
1301 /* Disconnect from the SPI framework */
1302 spi_unregister_master(drv_data->master);
1304 /* Prevent double remove */
1305 platform_set_drvdata(pdev, NULL);
1310 static void pxa2xx_spi_shutdown(struct platform_device *pdev)
1314 if ((status = pxa2xx_spi_remove(pdev)) != 0)
1315 dev_err(&pdev->dev, "shutdown failed with %d\n", status);
1319 static int pxa2xx_spi_suspend(struct device *dev)
1321 struct driver_data *drv_data = dev_get_drvdata(dev);
1322 struct ssp_device *ssp = drv_data->ssp;
1325 status = spi_master_suspend(drv_data->master);
1328 write_SSCR0(0, drv_data->ioaddr);
1329 clk_disable_unprepare(ssp->clk);
1334 static int pxa2xx_spi_resume(struct device *dev)
1336 struct driver_data *drv_data = dev_get_drvdata(dev);
1337 struct ssp_device *ssp = drv_data->ssp;
1340 pxa2xx_spi_dma_resume(drv_data);
1342 /* Enable the SSP clock */
1343 clk_prepare_enable(ssp->clk);
1345 /* Start the queue running */
1346 status = spi_master_resume(drv_data->master);
1348 dev_err(dev, "problem starting queue (%d)\n", status);
1356 #ifdef CONFIG_PM_RUNTIME
1357 static int pxa2xx_spi_runtime_suspend(struct device *dev)
1359 struct driver_data *drv_data = dev_get_drvdata(dev);
1361 clk_disable_unprepare(drv_data->ssp->clk);
1365 static int pxa2xx_spi_runtime_resume(struct device *dev)
1367 struct driver_data *drv_data = dev_get_drvdata(dev);
1369 clk_prepare_enable(drv_data->ssp->clk);
1374 static const struct dev_pm_ops pxa2xx_spi_pm_ops = {
1375 SET_SYSTEM_SLEEP_PM_OPS(pxa2xx_spi_suspend, pxa2xx_spi_resume)
1376 SET_RUNTIME_PM_OPS(pxa2xx_spi_runtime_suspend,
1377 pxa2xx_spi_runtime_resume, NULL)
1380 static struct platform_driver driver = {
1382 .name = "pxa2xx-spi",
1383 .owner = THIS_MODULE,
1384 .pm = &pxa2xx_spi_pm_ops,
1385 .acpi_match_table = ACPI_PTR(pxa2xx_spi_acpi_match),
1387 .probe = pxa2xx_spi_probe,
1388 .remove = pxa2xx_spi_remove,
1389 .shutdown = pxa2xx_spi_shutdown,
1392 static int __init pxa2xx_spi_init(void)
1394 return platform_driver_register(&driver);
1396 subsys_initcall(pxa2xx_spi_init);
1398 static void __exit pxa2xx_spi_exit(void)
1400 platform_driver_unregister(&driver);
1402 module_exit(pxa2xx_spi_exit);