2 * Copyright (c) 2014, Fuzhou Rockchip Electronics Co., Ltd
3 * Author: Addy Ke <addy.ke@rock-chips.com>
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 #include <linux/init.h>
17 #include <linux/module.h>
18 #include <linux/clk.h>
19 #include <linux/err.h>
20 #include <linux/delay.h>
21 #include <linux/interrupt.h>
22 #include <linux/platform_device.h>
23 #include <linux/slab.h>
24 #include <linux/spi/spi.h>
25 #include <linux/scatterlist.h>
27 #include <linux/pm_runtime.h>
29 #include <linux/dmaengine.h>
31 #define DRIVER_NAME "rockchip-spi"
33 /* SPI register offsets */
34 #define ROCKCHIP_SPI_CTRLR0 0x0000
35 #define ROCKCHIP_SPI_CTRLR1 0x0004
36 #define ROCKCHIP_SPI_SSIENR 0x0008
37 #define ROCKCHIP_SPI_SER 0x000c
38 #define ROCKCHIP_SPI_BAUDR 0x0010
39 #define ROCKCHIP_SPI_TXFTLR 0x0014
40 #define ROCKCHIP_SPI_RXFTLR 0x0018
41 #define ROCKCHIP_SPI_TXFLR 0x001c
42 #define ROCKCHIP_SPI_RXFLR 0x0020
43 #define ROCKCHIP_SPI_SR 0x0024
44 #define ROCKCHIP_SPI_IPR 0x0028
45 #define ROCKCHIP_SPI_IMR 0x002c
46 #define ROCKCHIP_SPI_ISR 0x0030
47 #define ROCKCHIP_SPI_RISR 0x0034
48 #define ROCKCHIP_SPI_ICR 0x0038
49 #define ROCKCHIP_SPI_DMACR 0x003c
50 #define ROCKCHIP_SPI_DMATDLR 0x0040
51 #define ROCKCHIP_SPI_DMARDLR 0x0044
52 #define ROCKCHIP_SPI_TXDR 0x0400
53 #define ROCKCHIP_SPI_RXDR 0x0800
55 /* Bit fields in CTRLR0 */
56 #define CR0_DFS_OFFSET 0
58 #define CR0_CFS_OFFSET 2
60 #define CR0_SCPH_OFFSET 6
62 #define CR0_SCPOL_OFFSET 7
64 #define CR0_CSM_OFFSET 8
65 #define CR0_CSM_KEEP 0x0
66 /* ss_n be high for half sclk_out cycles */
67 #define CR0_CSM_HALF 0X1
68 /* ss_n be high for one sclk_out cycle */
69 #define CR0_CSM_ONE 0x2
71 /* ss_n to sclk_out delay */
72 #define CR0_SSD_OFFSET 10
74 * The period between ss_n active and
75 * sclk_out active is half sclk_out cycles
77 #define CR0_SSD_HALF 0x0
79 * The period between ss_n active and
80 * sclk_out active is one sclk_out cycle
82 #define CR0_SSD_ONE 0x1
84 #define CR0_EM_OFFSET 11
85 #define CR0_EM_LITTLE 0x0
86 #define CR0_EM_BIG 0x1
88 #define CR0_FBM_OFFSET 12
89 #define CR0_FBM_MSB 0x0
90 #define CR0_FBM_LSB 0x1
92 #define CR0_BHT_OFFSET 13
93 #define CR0_BHT_16BIT 0x0
94 #define CR0_BHT_8BIT 0x1
96 #define CR0_RSD_OFFSET 14
98 #define CR0_FRF_OFFSET 16
99 #define CR0_FRF_SPI 0x0
100 #define CR0_FRF_SSP 0x1
101 #define CR0_FRF_MICROWIRE 0x2
103 #define CR0_XFM_OFFSET 18
104 #define CR0_XFM_MASK (0x03 << SPI_XFM_OFFSET)
105 #define CR0_XFM_TR 0x0
106 #define CR0_XFM_TO 0x1
107 #define CR0_XFM_RO 0x2
109 #define CR0_OPM_OFFSET 20
110 #define CR0_OPM_MASTER 0x0
111 #define CR0_OPM_SLAVE 0x1
113 #define CR0_MTM_OFFSET 0x21
115 /* Bit fields in SER, 2bit */
118 /* Bit fields in SR, 5bit */
120 #define SR_BUSY (1 << 0)
121 #define SR_TF_FULL (1 << 1)
122 #define SR_TF_EMPTY (1 << 2)
123 #define SR_RF_EMPTY (1 << 3)
124 #define SR_RF_FULL (1 << 4)
126 /* Bit fields in ISR, IMR, ISR, RISR, 5bit */
127 #define INT_MASK 0x1f
128 #define INT_TF_EMPTY (1 << 0)
129 #define INT_TF_OVERFLOW (1 << 1)
130 #define INT_RF_UNDERFLOW (1 << 2)
131 #define INT_RF_OVERFLOW (1 << 3)
132 #define INT_RF_FULL (1 << 4)
134 /* Bit fields in ICR, 4bit */
135 #define ICR_MASK 0x0f
136 #define ICR_ALL (1 << 0)
137 #define ICR_RF_UNDERFLOW (1 << 1)
138 #define ICR_RF_OVERFLOW (1 << 2)
139 #define ICR_TF_OVERFLOW (1 << 3)
141 /* Bit fields in DMACR */
142 #define RF_DMA_EN (1 << 0)
143 #define TF_DMA_EN (1 << 1)
145 #define RXBUSY (1 << 0)
146 #define TXBUSY (1 << 1)
148 enum rockchip_ssi_type {
154 struct rockchip_spi_dma_data {
156 enum dma_transfer_direction direction;
160 struct rockchip_spi {
162 struct spi_master *master;
165 struct clk *apb_pclk;
168 /*depth of the FIFO buffer */
170 /* max bus freq supported */
172 /* supported slave numbers */
173 enum rockchip_ssi_type type;
191 struct completion xfer_completion;
194 struct sg_table tx_sg;
195 struct sg_table rx_sg;
196 struct rockchip_spi_dma_data dma_rx;
197 struct rockchip_spi_dma_data dma_tx;
200 static inline void spi_enable_chip(struct rockchip_spi *rs, int enable)
202 writel_relaxed((enable ? 1 : 0), rs->regs + ROCKCHIP_SPI_SSIENR);
205 static inline void spi_set_clk(struct rockchip_spi *rs, u16 div)
207 writel_relaxed(div, rs->regs + ROCKCHIP_SPI_BAUDR);
210 static inline void flush_fifo(struct rockchip_spi *rs)
212 while (readl_relaxed(rs->regs + ROCKCHIP_SPI_RXFLR))
213 readl_relaxed(rs->regs + ROCKCHIP_SPI_RXDR);
216 static inline void wait_for_idle(struct rockchip_spi *rs)
218 unsigned long timeout = jiffies + msecs_to_jiffies(5);
221 if (!(readl_relaxed(rs->regs + ROCKCHIP_SPI_SR) & SR_BUSY))
223 } while (time_before(jiffies, timeout));
225 dev_warn(rs->dev, "spi controller is in busy state!\n");
228 static u32 get_fifo_len(struct rockchip_spi *rs)
232 for (fifo = 2; fifo < 32; fifo++) {
233 writel_relaxed(fifo, rs->regs + ROCKCHIP_SPI_TXFTLR);
234 if (fifo != readl_relaxed(rs->regs + ROCKCHIP_SPI_TXFTLR))
238 writel_relaxed(0, rs->regs + ROCKCHIP_SPI_TXFTLR);
240 return (fifo == 31) ? 0 : fifo;
243 static inline u32 tx_max(struct rockchip_spi *rs)
245 u32 tx_left, tx_room;
247 tx_left = (rs->tx_end - rs->tx) / rs->n_bytes;
248 tx_room = rs->fifo_len - readl_relaxed(rs->regs + ROCKCHIP_SPI_TXFLR);
250 return min(tx_left, tx_room);
253 static inline u32 rx_max(struct rockchip_spi *rs)
255 u32 rx_left = (rs->rx_end - rs->rx) / rs->n_bytes;
256 u32 rx_room = (u32)readl_relaxed(rs->regs + ROCKCHIP_SPI_RXFLR);
258 return min(rx_left, rx_room);
261 static void rockchip_spi_set_cs(struct spi_device *spi, bool enable)
264 struct rockchip_spi *rs = spi_master_get_devdata(spi->master);
266 ser = readl_relaxed(rs->regs + ROCKCHIP_SPI_SER) & SER_MASK;
270 * static void spi_set_cs(struct spi_device *spi, bool enable)
272 * if (spi->mode & SPI_CS_HIGH)
275 * if (spi->cs_gpio >= 0)
276 * gpio_set_value(spi->cs_gpio, !enable);
277 * else if (spi->master->set_cs)
278 * spi->master->set_cs(spi, !enable);
281 * Note: enable(rockchip_spi_set_cs) = !enable(spi_set_cs)
284 ser |= 1 << spi->chip_select;
286 ser &= ~(1 << spi->chip_select);
288 writel_relaxed(ser, rs->regs + ROCKCHIP_SPI_SER);
291 static int rockchip_spi_prepare_message(struct spi_master *master,
292 struct spi_message *msg)
294 struct rockchip_spi *rs = spi_master_get_devdata(master);
295 struct spi_device *spi = msg->spi;
297 rs->mode = spi->mode;
302 static int rockchip_spi_unprepare_message(struct spi_master *master,
303 struct spi_message *msg)
306 struct rockchip_spi *rs = spi_master_get_devdata(master);
308 spin_lock_irqsave(&rs->lock, flags);
311 * For DMA mode, we need terminate DMA channel and flush
312 * fifo for the next transfer if DMA thansfer timeout.
313 * unprepare_message() was called by core if transfer complete
314 * or timeout. Maybe it is reasonable for error handling here.
317 if (rs->state & RXBUSY) {
318 dmaengine_terminate_all(rs->dma_rx.ch);
322 if (rs->state & TXBUSY)
323 dmaengine_terminate_all(rs->dma_tx.ch);
326 spin_unlock_irqrestore(&rs->lock, flags);
331 static void rockchip_spi_pio_writer(struct rockchip_spi *rs)
333 u32 max = tx_max(rs);
337 if (rs->n_bytes == 1)
338 txw = *(u8 *)(rs->tx);
340 txw = *(u16 *)(rs->tx);
342 writel_relaxed(txw, rs->regs + ROCKCHIP_SPI_TXDR);
343 rs->tx += rs->n_bytes;
347 static void rockchip_spi_pio_reader(struct rockchip_spi *rs)
349 u32 max = rx_max(rs);
353 rxw = readl_relaxed(rs->regs + ROCKCHIP_SPI_RXDR);
354 if (rs->n_bytes == 1)
355 *(u8 *)(rs->rx) = (u8)rxw;
357 *(u16 *)(rs->rx) = (u16)rxw;
358 rs->rx += rs->n_bytes;
362 static int rockchip_spi_pio_transfer(struct rockchip_spi *rs)
368 remain = rs->tx_end - rs->tx;
369 rockchip_spi_pio_writer(rs);
373 remain = rs->rx_end - rs->rx;
374 rockchip_spi_pio_reader(rs);
380 /* If tx, wait until the FIFO data completely. */
387 static void rockchip_spi_dma_rxcb(void *data)
390 struct rockchip_spi *rs = data;
392 spin_lock_irqsave(&rs->lock, flags);
394 rs->state &= ~RXBUSY;
395 if (!(rs->state & TXBUSY))
396 spi_finalize_current_transfer(rs->master);
398 spin_unlock_irqrestore(&rs->lock, flags);
401 static void rockchip_spi_dma_txcb(void *data)
404 struct rockchip_spi *rs = data;
406 /* Wait until the FIFO data completely. */
409 spin_lock_irqsave(&rs->lock, flags);
411 rs->state &= ~TXBUSY;
412 if (!(rs->state & RXBUSY))
413 spi_finalize_current_transfer(rs->master);
415 spin_unlock_irqrestore(&rs->lock, flags);
418 static void rockchip_spi_prepare_dma(struct rockchip_spi *rs)
421 struct dma_slave_config rxconf, txconf;
422 struct dma_async_tx_descriptor *rxdesc, *txdesc;
424 spin_lock_irqsave(&rs->lock, flags);
425 rs->state &= ~RXBUSY;
426 rs->state &= ~TXBUSY;
427 spin_unlock_irqrestore(&rs->lock, flags);
430 rxconf.direction = rs->dma_rx.direction;
431 rxconf.src_addr = rs->dma_rx.addr;
432 rxconf.src_addr_width = rs->n_bytes;
433 rxconf.src_maxburst = rs->n_bytes;
434 dmaengine_slave_config(rs->dma_rx.ch, &rxconf);
436 rxdesc = dmaengine_prep_slave_sg(
438 rs->rx_sg.sgl, rs->rx_sg.nents,
439 rs->dma_rx.direction, DMA_PREP_INTERRUPT);
441 rxdesc->callback = rockchip_spi_dma_rxcb;
442 rxdesc->callback_param = rs;
446 txconf.direction = rs->dma_tx.direction;
447 txconf.dst_addr = rs->dma_tx.addr;
448 txconf.dst_addr_width = rs->n_bytes;
449 txconf.dst_maxburst = rs->n_bytes;
450 dmaengine_slave_config(rs->dma_tx.ch, &txconf);
452 txdesc = dmaengine_prep_slave_sg(
454 rs->tx_sg.sgl, rs->tx_sg.nents,
455 rs->dma_tx.direction, DMA_PREP_INTERRUPT);
457 txdesc->callback = rockchip_spi_dma_txcb;
458 txdesc->callback_param = rs;
461 /* rx must be started before tx due to spi instinct */
463 spin_lock_irqsave(&rs->lock, flags);
465 spin_unlock_irqrestore(&rs->lock, flags);
466 dmaengine_submit(rxdesc);
467 dma_async_issue_pending(rs->dma_rx.ch);
471 spin_lock_irqsave(&rs->lock, flags);
473 spin_unlock_irqrestore(&rs->lock, flags);
474 dmaengine_submit(txdesc);
475 dma_async_issue_pending(rs->dma_tx.ch);
479 static void rockchip_spi_config(struct rockchip_spi *rs)
484 u32 cr0 = (CR0_BHT_8BIT << CR0_BHT_OFFSET)
485 | (CR0_SSD_ONE << CR0_SSD_OFFSET);
487 cr0 |= (rs->n_bytes << CR0_DFS_OFFSET);
488 cr0 |= ((rs->mode & 0x3) << CR0_SCPH_OFFSET);
489 cr0 |= (rs->tmode << CR0_XFM_OFFSET);
490 cr0 |= (rs->type << CR0_FRF_OFFSET);
499 /* div doesn't support odd number */
500 div = rs->max_freq / rs->speed;
501 div = (div + 1) & 0xfffe;
503 spi_enable_chip(rs, 0);
505 writel_relaxed(cr0, rs->regs + ROCKCHIP_SPI_CTRLR0);
507 writel_relaxed(rs->len - 1, rs->regs + ROCKCHIP_SPI_CTRLR1);
508 writel_relaxed(rs->fifo_len / 2 - 1, rs->regs + ROCKCHIP_SPI_TXFTLR);
509 writel_relaxed(rs->fifo_len / 2 - 1, rs->regs + ROCKCHIP_SPI_RXFTLR);
511 writel_relaxed(0, rs->regs + ROCKCHIP_SPI_DMATDLR);
512 writel_relaxed(0, rs->regs + ROCKCHIP_SPI_DMARDLR);
513 writel_relaxed(dmacr, rs->regs + ROCKCHIP_SPI_DMACR);
515 spi_set_clk(rs, div);
517 dev_dbg(rs->dev, "cr0 0x%x, div %d\n", cr0, div);
519 spi_enable_chip(rs, 1);
522 static int rockchip_spi_transfer_one(
523 struct spi_master *master,
524 struct spi_device *spi,
525 struct spi_transfer *xfer)
528 struct rockchip_spi *rs = spi_master_get_devdata(master);
530 WARN_ON((readl_relaxed(rs->regs + ROCKCHIP_SPI_SR) & SR_BUSY));
532 if (!xfer->tx_buf && !xfer->rx_buf) {
533 dev_err(rs->dev, "No buffer for transfer\n");
537 rs->speed = xfer->speed_hz;
538 rs->bpw = xfer->bits_per_word;
539 rs->n_bytes = rs->bpw >> 3;
541 rs->tx = xfer->tx_buf;
542 rs->tx_end = rs->tx + xfer->len;
543 rs->rx = xfer->rx_buf;
544 rs->rx_end = rs->rx + xfer->len;
547 rs->tx_sg = xfer->tx_sg;
548 rs->rx_sg = xfer->rx_sg;
550 if (rs->tx && rs->rx)
551 rs->tmode = CR0_XFM_TR;
553 rs->tmode = CR0_XFM_TO;
555 rs->tmode = CR0_XFM_RO;
557 /* we need prepare dma before spi was enabled */
558 if (master->can_dma && master->can_dma(master, spi, xfer)) {
560 rockchip_spi_prepare_dma(rs);
565 rockchip_spi_config(rs);
568 ret = rockchip_spi_pio_transfer(rs);
573 static bool rockchip_spi_can_dma(struct spi_master *master,
574 struct spi_device *spi,
575 struct spi_transfer *xfer)
577 struct rockchip_spi *rs = spi_master_get_devdata(master);
579 return (xfer->len > rs->fifo_len);
582 static int rockchip_spi_probe(struct platform_device *pdev)
585 struct rockchip_spi *rs;
586 struct spi_master *master;
587 struct resource *mem;
589 master = spi_alloc_master(&pdev->dev, sizeof(struct rockchip_spi));
593 platform_set_drvdata(pdev, master);
595 rs = spi_master_get_devdata(master);
596 memset(rs, 0, sizeof(struct rockchip_spi));
598 /* Get basic io resource and map it */
599 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
600 rs->regs = devm_ioremap_resource(&pdev->dev, mem);
601 if (IS_ERR(rs->regs)) {
602 ret = PTR_ERR(rs->regs);
603 goto err_ioremap_resource;
606 rs->apb_pclk = devm_clk_get(&pdev->dev, "apb_pclk");
607 if (IS_ERR(rs->apb_pclk)) {
608 dev_err(&pdev->dev, "Failed to get apb_pclk\n");
609 ret = PTR_ERR(rs->apb_pclk);
610 goto err_ioremap_resource;
613 rs->spiclk = devm_clk_get(&pdev->dev, "spiclk");
614 if (IS_ERR(rs->spiclk)) {
615 dev_err(&pdev->dev, "Failed to get spi_pclk\n");
616 ret = PTR_ERR(rs->spiclk);
617 goto err_ioremap_resource;
620 ret = clk_prepare_enable(rs->apb_pclk);
622 dev_err(&pdev->dev, "Failed to enable apb_pclk\n");
623 goto err_ioremap_resource;
626 ret = clk_prepare_enable(rs->spiclk);
628 dev_err(&pdev->dev, "Failed to enable spi_clk\n");
629 goto err_spiclk_enable;
632 spi_enable_chip(rs, 0);
634 rs->type = SSI_MOTO_SPI;
636 rs->dev = &pdev->dev;
637 rs->max_freq = clk_get_rate(rs->spiclk);
639 rs->fifo_len = get_fifo_len(rs);
641 dev_err(&pdev->dev, "Failed to get fifo length\n");
643 goto err_get_fifo_len;
646 spin_lock_init(&rs->lock);
648 pm_runtime_set_active(&pdev->dev);
649 pm_runtime_enable(&pdev->dev);
651 master->auto_runtime_pm = true;
652 master->bus_num = pdev->id;
653 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LOOP;
654 master->num_chipselect = 2;
655 master->dev.of_node = pdev->dev.of_node;
656 master->bits_per_word_mask = SPI_BPW_MASK(16) | SPI_BPW_MASK(8);
658 master->set_cs = rockchip_spi_set_cs;
659 master->prepare_message = rockchip_spi_prepare_message;
660 master->unprepare_message = rockchip_spi_unprepare_message;
661 master->transfer_one = rockchip_spi_transfer_one;
663 rs->dma_tx.ch = dma_request_slave_channel(rs->dev, "tx");
665 dev_warn(rs->dev, "Failed to request TX DMA channel\n");
667 rs->dma_rx.ch = dma_request_slave_channel(rs->dev, "rx");
668 if (!rs->dma_rx.ch) {
670 dma_release_channel(rs->dma_tx.ch);
671 rs->dma_tx.ch = NULL;
673 dev_warn(rs->dev, "Failed to request RX DMA channel\n");
676 if (rs->dma_tx.ch && rs->dma_rx.ch) {
677 rs->dma_tx.addr = (dma_addr_t)(mem->start + ROCKCHIP_SPI_TXDR);
678 rs->dma_rx.addr = (dma_addr_t)(mem->start + ROCKCHIP_SPI_RXDR);
679 rs->dma_tx.direction = DMA_MEM_TO_DEV;
680 rs->dma_tx.direction = DMA_DEV_TO_MEM;
682 master->can_dma = rockchip_spi_can_dma;
683 master->dma_tx = rs->dma_tx.ch;
684 master->dma_rx = rs->dma_rx.ch;
687 ret = devm_spi_register_master(&pdev->dev, master);
689 dev_err(&pdev->dev, "Failed to register master\n");
690 goto err_register_master;
697 dma_release_channel(rs->dma_tx.ch);
699 dma_release_channel(rs->dma_rx.ch);
701 clk_disable_unprepare(rs->spiclk);
703 clk_disable_unprepare(rs->apb_pclk);
704 err_ioremap_resource:
705 spi_master_put(master);
710 static int rockchip_spi_remove(struct platform_device *pdev)
712 struct spi_master *master = spi_master_get(platform_get_drvdata(pdev));
713 struct rockchip_spi *rs = spi_master_get_devdata(master);
715 pm_runtime_disable(&pdev->dev);
717 clk_disable_unprepare(rs->spiclk);
718 clk_disable_unprepare(rs->apb_pclk);
721 dma_release_channel(rs->dma_tx.ch);
723 dma_release_channel(rs->dma_rx.ch);
725 spi_master_put(master);
730 #ifdef CONFIG_PM_SLEEP
731 static int rockchip_spi_suspend(struct device *dev)
734 struct spi_master *master = dev_get_drvdata(dev);
735 struct rockchip_spi *rs = spi_master_get_devdata(master);
737 ret = spi_master_suspend(rs->master);
741 if (!pm_runtime_suspended(dev)) {
742 clk_disable_unprepare(rs->spiclk);
743 clk_disable_unprepare(rs->apb_pclk);
749 static int rockchip_spi_resume(struct device *dev)
752 struct spi_master *master = dev_get_drvdata(dev);
753 struct rockchip_spi *rs = spi_master_get_devdata(master);
755 if (!pm_runtime_suspended(dev)) {
756 ret = clk_prepare_enable(rs->apb_pclk);
760 ret = clk_prepare_enable(rs->spiclk);
762 clk_disable_unprepare(rs->apb_pclk);
767 ret = spi_master_resume(rs->master);
769 clk_disable_unprepare(rs->spiclk);
770 clk_disable_unprepare(rs->apb_pclk);
775 #endif /* CONFIG_PM_SLEEP */
777 #ifdef CONFIG_PM_RUNTIME
778 static int rockchip_spi_runtime_suspend(struct device *dev)
780 struct spi_master *master = dev_get_drvdata(dev);
781 struct rockchip_spi *rs = spi_master_get_devdata(master);
783 clk_disable_unprepare(rs->spiclk);
784 clk_disable_unprepare(rs->apb_pclk);
789 static int rockchip_spi_runtime_resume(struct device *dev)
792 struct spi_master *master = dev_get_drvdata(dev);
793 struct rockchip_spi *rs = spi_master_get_devdata(master);
795 ret = clk_prepare_enable(rs->apb_pclk);
799 ret = clk_prepare_enable(rs->spiclk);
801 clk_disable_unprepare(rs->apb_pclk);
805 #endif /* CONFIG_PM_RUNTIME */
807 static const struct dev_pm_ops rockchip_spi_pm = {
808 SET_SYSTEM_SLEEP_PM_OPS(rockchip_spi_suspend, rockchip_spi_resume)
809 SET_RUNTIME_PM_OPS(rockchip_spi_runtime_suspend,
810 rockchip_spi_runtime_resume, NULL)
813 static const struct of_device_id rockchip_spi_dt_match[] = {
814 { .compatible = "rockchip,rk3066-spi", },
815 { .compatible = "rockchip,rk3188-spi", },
816 { .compatible = "rockchip,rk3288-spi", },
819 MODULE_DEVICE_TABLE(of, rockchip_spi_dt_match);
821 static struct platform_driver rockchip_spi_driver = {
824 .owner = THIS_MODULE,
825 .pm = &rockchip_spi_pm,
826 .of_match_table = of_match_ptr(rockchip_spi_dt_match),
828 .probe = rockchip_spi_probe,
829 .remove = rockchip_spi_remove,
832 module_platform_driver(rockchip_spi_driver);
834 MODULE_AUTHOR("Addy Ke <addy.ke@rock-chips.com>");
835 MODULE_DESCRIPTION("ROCKCHIP SPI Controller Driver");
836 MODULE_LICENSE("GPL v2");