drivers/spi/spi-s3c64xx.c

   1 /*
   2  * Copyright (C) 2009 Samsung Electronics Ltd.
   3  *      Jaswinder Singh <jassi.brar@samsung.com>
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation; either version 2 of the License, or
   8  * (at your option) any later version.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  18  */
  19
  20 #include <linux/init.h>
  21 #include <linux/module.h>
  22 #include <linux/workqueue.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/delay.h>
  25 #include <linux/clk.h>
  26 #include <linux/dma-mapping.h>
  27 #include <linux/dmaengine.h>
  28 #include <linux/platform_device.h>
  29 #include <linux/pm_runtime.h>
  30 #include <linux/spi/spi.h>
  31 #include <linux/gpio.h>
  32 #include <linux/of.h>
  33 #include <linux/of_gpio.h>
  34
  35 #include <linux/platform_data/spi-s3c64xx.h>
  36
  37 #ifdef CONFIG_S3C_DMA
  38 #include <mach/dma.h>
  39 #endif
  40
  41 #define MAX_SPI_PORTS           3
  42 #define S3C64XX_SPI_QUIRK_POLL          (1 << 0)
  43
  44 /* Registers and bit-fields */
  45
  46 #define S3C64XX_SPI_CH_CFG              0x00
  47 #define S3C64XX_SPI_CLK_CFG             0x04
  48 #define S3C64XX_SPI_MODE_CFG    0x08
  49 #define S3C64XX_SPI_SLAVE_SEL   0x0C
  50 #define S3C64XX_SPI_INT_EN              0x10
  51 #define S3C64XX_SPI_STATUS              0x14
  52 #define S3C64XX_SPI_TX_DATA             0x18
  53 #define S3C64XX_SPI_RX_DATA             0x1C
  54 #define S3C64XX_SPI_PACKET_CNT  0x20
  55 #define S3C64XX_SPI_PENDING_CLR 0x24
  56 #define S3C64XX_SPI_SWAP_CFG    0x28
  57 #define S3C64XX_SPI_FB_CLK              0x2C
  58
  59 #define S3C64XX_SPI_CH_HS_EN            (1<<6)  /* High Speed Enable */
  60 #define S3C64XX_SPI_CH_SW_RST           (1<<5)
  61 #define S3C64XX_SPI_CH_SLAVE            (1<<4)
  62 #define S3C64XX_SPI_CPOL_L              (1<<3)
  63 #define S3C64XX_SPI_CPHA_B              (1<<2)
  64 #define S3C64XX_SPI_CH_RXCH_ON          (1<<1)
  65 #define S3C64XX_SPI_CH_TXCH_ON          (1<<0)
  66
  67 #define S3C64XX_SPI_CLKSEL_SRCMSK       (3<<9)
  68 #define S3C64XX_SPI_CLKSEL_SRCSHFT      9
  69 #define S3C64XX_SPI_ENCLK_ENABLE        (1<<8)
  70 #define S3C64XX_SPI_PSR_MASK            0xff
  71
  72 #define S3C64XX_SPI_MODE_CH_TSZ_BYTE            (0<<29)
  73 #define S3C64XX_SPI_MODE_CH_TSZ_HALFWORD        (1<<29)
  74 #define S3C64XX_SPI_MODE_CH_TSZ_WORD            (2<<29)
  75 #define S3C64XX_SPI_MODE_CH_TSZ_MASK            (3<<29)
  76 #define S3C64XX_SPI_MODE_BUS_TSZ_BYTE           (0<<17)
  77 #define S3C64XX_SPI_MODE_BUS_TSZ_HALFWORD       (1<<17)
  78 #define S3C64XX_SPI_MODE_BUS_TSZ_WORD           (2<<17)
  79 #define S3C64XX_SPI_MODE_BUS_TSZ_MASK           (3<<17)
  80 #define S3C64XX_SPI_MODE_RXDMA_ON               (1<<2)
  81 #define S3C64XX_SPI_MODE_TXDMA_ON               (1<<1)
  82 #define S3C64XX_SPI_MODE_4BURST                 (1<<0)
  83
  84 #define S3C64XX_SPI_SLAVE_AUTO                  (1<<1)
  85 #define S3C64XX_SPI_SLAVE_SIG_INACT             (1<<0)
  86
  87 #define S3C64XX_SPI_INT_TRAILING_EN             (1<<6)
  88 #define S3C64XX_SPI_INT_RX_OVERRUN_EN           (1<<5)
  89 #define S3C64XX_SPI_INT_RX_UNDERRUN_EN          (1<<4)
  90 #define S3C64XX_SPI_INT_TX_OVERRUN_EN           (1<<3)
  91 #define S3C64XX_SPI_INT_TX_UNDERRUN_EN          (1<<2)
  92 #define S3C64XX_SPI_INT_RX_FIFORDY_EN           (1<<1)
  93 #define S3C64XX_SPI_INT_TX_FIFORDY_EN           (1<<0)
  94
  95 #define S3C64XX_SPI_ST_RX_OVERRUN_ERR           (1<<5)
  96 #define S3C64XX_SPI_ST_RX_UNDERRUN_ERR  (1<<4)
  97 #define S3C64XX_SPI_ST_TX_OVERRUN_ERR           (1<<3)
  98 #define S3C64XX_SPI_ST_TX_UNDERRUN_ERR  (1<<2)
  99 #define S3C64XX_SPI_ST_RX_FIFORDY               (1<<1)
 100 #define S3C64XX_SPI_ST_TX_FIFORDY               (1<<0)
 101
 102 #define S3C64XX_SPI_PACKET_CNT_EN               (1<<16)
 103
 104 #define S3C64XX_SPI_PND_TX_UNDERRUN_CLR         (1<<4)
 105 #define S3C64XX_SPI_PND_TX_OVERRUN_CLR          (1<<3)
 106 #define S3C64XX_SPI_PND_RX_UNDERRUN_CLR         (1<<2)
 107 #define S3C64XX_SPI_PND_RX_OVERRUN_CLR          (1<<1)
 108 #define S3C64XX_SPI_PND_TRAILING_CLR            (1<<0)
 109
 110 #define S3C64XX_SPI_SWAP_RX_HALF_WORD           (1<<7)
 111 #define S3C64XX_SPI_SWAP_RX_BYTE                (1<<6)
 112 #define S3C64XX_SPI_SWAP_RX_BIT                 (1<<5)
 113 #define S3C64XX_SPI_SWAP_RX_EN                  (1<<4)
 114 #define S3C64XX_SPI_SWAP_TX_HALF_WORD           (1<<3)
 115 #define S3C64XX_SPI_SWAP_TX_BYTE                (1<<2)
 116 #define S3C64XX_SPI_SWAP_TX_BIT                 (1<<1)
 117 #define S3C64XX_SPI_SWAP_TX_EN                  (1<<0)
 118
 119 #define S3C64XX_SPI_FBCLK_MSK           (3<<0)
 120
 121 #define FIFO_LVL_MASK(i) ((i)->port_conf->fifo_lvl_mask[i->port_id])
 122 #define S3C64XX_SPI_ST_TX_DONE(v, i) (((v) & \
 123                                 (1 << (i)->port_conf->tx_st_done)) ? 1 : 0)
 124 #define TX_FIFO_LVL(v, i) (((v) >> 6) & FIFO_LVL_MASK(i))
 125 #define RX_FIFO_LVL(v, i) (((v) >> (i)->port_conf->rx_lvl_offset) & \
 126                                         FIFO_LVL_MASK(i))
 127
 128 #define S3C64XX_SPI_MAX_TRAILCNT        0x3ff
 129 #define S3C64XX_SPI_TRAILCNT_OFF        19
 130
 131 #define S3C64XX_SPI_TRAILCNT            S3C64XX_SPI_MAX_TRAILCNT
 132
 133 #define msecs_to_loops(t) (loops_per_jiffy / 1000 * HZ * t)
 134 #define is_polling(x)   (x->port_conf->quirks & S3C64XX_SPI_QUIRK_POLL)
 135
 136 #define RXBUSY    (1<<2)
 137 #define TXBUSY    (1<<3)
 138
 139 struct s3c64xx_spi_dma_data {
 140         struct dma_chan *ch;
 141         enum dma_transfer_direction direction;
 142         unsigned int dmach;
 143 };
 144
 145 /**
 146  * struct s3c64xx_spi_info - SPI Controller hardware info
 147  * @fifo_lvl_mask: Bit-mask for {TX|RX}_FIFO_LVL bits in SPI_STATUS register.
 148  * @rx_lvl_offset: Bit offset of RX_FIFO_LVL bits in SPI_STATUS regiter.
 149  * @tx_st_done: Bit offset of TX_DONE bit in SPI_STATUS regiter.
 150  * @high_speed: True, if the controller supports HIGH_SPEED_EN bit.
 151  * @clk_from_cmu: True, if the controller does not include a clock mux and
 152  *      prescaler unit.
 153  *
 154  * The Samsung s3c64xx SPI controller are used on various Samsung SoC's but
 155  * differ in some aspects such as the size of the fifo and spi bus clock
 156  * setup. Such differences are specified to the driver using this structure
 157  * which is provided as driver data to the driver.
 158  */
 159 struct s3c64xx_spi_port_config {
 160         int     fifo_lvl_mask[MAX_SPI_PORTS];
 161         int     rx_lvl_offset;
 162         int     tx_st_done;
 163         int     quirks;
 164         bool    high_speed;
 165         bool    clk_from_cmu;
 166 };
 167
 168 /**
 169  * struct s3c64xx_spi_driver_data - Runtime info holder for SPI driver.
 170  * @clk: Pointer to the spi clock.
 171  * @src_clk: Pointer to the clock used to generate SPI signals.
 172  * @master: Pointer to the SPI Protocol master.
 173  * @cntrlr_info: Platform specific data for the controller this driver manages.
 174  * @tgl_spi: Pointer to the last CS left untoggled by the cs_change hint.
 175  * @queue: To log SPI xfer requests.
 176  * @lock: Controller specific lock.
 177  * @state: Set of FLAGS to indicate status.
 178  * @rx_dmach: Controller's DMA channel for Rx.
 179  * @tx_dmach: Controller's DMA channel for Tx.
 180  * @sfr_start: BUS address of SPI controller regs.
 181  * @regs: Pointer to ioremap'ed controller registers.
 182  * @irq: interrupt
 183  * @xfer_completion: To indicate completion of xfer task.
 184  * @cur_mode: Stores the active configuration of the controller.
 185  * @cur_bpw: Stores the active bits per word settings.
 186  * @cur_speed: Stores the active xfer clock speed.
 187  */
 188 struct s3c64xx_spi_driver_data {
 189         void __iomem                    *regs;
 190         struct clk                      *clk;
 191         struct clk                      *src_clk;
 192         struct platform_device          *pdev;
 193         struct spi_master               *master;
 194         struct s3c64xx_spi_info  *cntrlr_info;
 195         struct spi_device               *tgl_spi;
 196         struct list_head                queue;
 197         spinlock_t                      lock;
 198         unsigned long                   sfr_start;
 199         struct completion               xfer_completion;
 200         unsigned                        state;
 201         unsigned                        cur_mode, cur_bpw;
 202         unsigned                        cur_speed;
 203         struct s3c64xx_spi_dma_data     rx_dma;
 204         struct s3c64xx_spi_dma_data     tx_dma;
 205 #ifdef CONFIG_S3C_DMA
 206         struct samsung_dma_ops          *ops;
 207 #endif
 208         struct s3c64xx_spi_port_config  *port_conf;
 209         unsigned int                    port_id;
 210         unsigned long                   gpios[4];
 211         bool                            cs_gpio;
 212 };
 213
 214 static void flush_fifo(struct s3c64xx_spi_driver_data *sdd)
 215 {
 216         void __iomem *regs = sdd->regs;
 217         unsigned long loops;
 218         u32 val;
 219
 220         writel(0, regs + S3C64XX_SPI_PACKET_CNT);
 221
 222         val = readl(regs + S3C64XX_SPI_CH_CFG);
 223         val &= ~(S3C64XX_SPI_CH_RXCH_ON | S3C64XX_SPI_CH_TXCH_ON);
 224         writel(val, regs + S3C64XX_SPI_CH_CFG);
 225
 226         val = readl(regs + S3C64XX_SPI_CH_CFG);
 227         val |= S3C64XX_SPI_CH_SW_RST;
 228         val &= ~S3C64XX_SPI_CH_HS_EN;
 229         writel(val, regs + S3C64XX_SPI_CH_CFG);
 230
 231         /* Flush TxFIFO*/
 232         loops = msecs_to_loops(1);
 233         do {
 234                 val = readl(regs + S3C64XX_SPI_STATUS);
 235         } while (TX_FIFO_LVL(val, sdd) && loops--);
 236
 237         if (loops == 0)
 238                 dev_warn(&sdd->pdev->dev, "Timed out flushing TX FIFO\n");
 239
 240         /* Flush RxFIFO*/
 241         loops = msecs_to_loops(1);
 242         do {
 243                 val = readl(regs + S3C64XX_SPI_STATUS);
 244                 if (RX_FIFO_LVL(val, sdd))
 245                         readl(regs + S3C64XX_SPI_RX_DATA);
 246                 else
 247                         break;
 248         } while (loops--);
 249
 250         if (loops == 0)
 251                 dev_warn(&sdd->pdev->dev, "Timed out flushing RX FIFO\n");
 252
 253         val = readl(regs + S3C64XX_SPI_CH_CFG);
 254         val &= ~S3C64XX_SPI_CH_SW_RST;
 255         writel(val, regs + S3C64XX_SPI_CH_CFG);
 256
 257         val = readl(regs + S3C64XX_SPI_MODE_CFG);
 258         val &= ~(S3C64XX_SPI_MODE_TXDMA_ON | S3C64XX_SPI_MODE_RXDMA_ON);
 259         writel(val, regs + S3C64XX_SPI_MODE_CFG);
 260 }
 261
 262 static void s3c64xx_spi_dmacb(void *data)
 263 {
 264         struct s3c64xx_spi_driver_data *sdd;
 265         struct s3c64xx_spi_dma_data *dma = data;
 266         unsigned long flags;
 267
 268         if (dma->direction == DMA_DEV_TO_MEM)
 269                 sdd = container_of(data,
 270                         struct s3c64xx_spi_driver_data, rx_dma);
 271         else
 272                 sdd = container_of(data,
 273                         struct s3c64xx_spi_driver_data, tx_dma);
 274
 275         spin_lock_irqsave(&sdd->lock, flags);
 276
 277         if (dma->direction == DMA_DEV_TO_MEM) {
 278                 sdd->state &= ~RXBUSY;
 279                 if (!(sdd->state & TXBUSY))
 280                         complete(&sdd->xfer_completion);
 281         } else {
 282                 sdd->state &= ~TXBUSY;
 283                 if (!(sdd->state & RXBUSY))
 284                         complete(&sdd->xfer_completion);
 285         }
 286
 287         spin_unlock_irqrestore(&sdd->lock, flags);
 288 }
 289
 290 #ifdef CONFIG_S3C_DMA
 291 /* FIXME: remove this section once arch/arm/mach-s3c64xx uses dmaengine */
 292
 293 static struct s3c2410_dma_client s3c64xx_spi_dma_client = {
 294         .name = "samsung-spi-dma",
 295 };
 296
 297 static void prepare_dma(struct s3c64xx_spi_dma_data *dma,
 298                                         unsigned len, dma_addr_t buf)
 299 {
 300         struct s3c64xx_spi_driver_data *sdd;
 301         struct samsung_dma_prep info;
 302         struct samsung_dma_config config;
 303
 304         if (dma->direction == DMA_DEV_TO_MEM) {
 305                 sdd = container_of((void *)dma,
 306                         struct s3c64xx_spi_driver_data, rx_dma);
 307                 config.direction = sdd->rx_dma.direction;
 308                 config.fifo = sdd->sfr_start + S3C64XX_SPI_RX_DATA;
 309                 config.width = sdd->cur_bpw / 8;
 310                 sdd->ops->config((enum dma_ch)sdd->rx_dma.ch, &config);
 311         } else {
 312                 sdd = container_of((void *)dma,
 313                         struct s3c64xx_spi_driver_data, tx_dma);
 314                 config.direction =  sdd->tx_dma.direction;
 315                 config.fifo = sdd->sfr_start + S3C64XX_SPI_TX_DATA;
 316                 config.width = sdd->cur_bpw / 8;
 317                 sdd->ops->config((enum dma_ch)sdd->tx_dma.ch, &config);
 318         }
 319
 320         info.cap = DMA_SLAVE;
 321         info.len = len;
 322         info.fp = s3c64xx_spi_dmacb;
 323         info.fp_param = dma;
 324         info.direction = dma->direction;
 325         info.buf = buf;
 326
 327         sdd->ops->prepare((enum dma_ch)dma->ch, &info);
 328         sdd->ops->trigger((enum dma_ch)dma->ch);
 329 }
 330
 331 static int acquire_dma(struct s3c64xx_spi_driver_data *sdd)
 332 {
 333         struct samsung_dma_req req;
 334         struct device *dev = &sdd->pdev->dev;
 335
 336         sdd->ops = samsung_dma_get_ops();
 337
 338         req.cap = DMA_SLAVE;
 339         req.client = &s3c64xx_spi_dma_client;
 340
 341         sdd->rx_dma.ch = (void *)sdd->ops->request(sdd->rx_dma.dmach, &req, dev, "rx");
 342         sdd->tx_dma.ch = (void *)sdd->ops->request(sdd->tx_dma.dmach, &req, dev, "tx");
 343
 344         return 1;
 345 }
 346
 347 static int s3c64xx_spi_prepare_transfer(struct spi_master *spi)
 348 {
 349         struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(spi);
 350
 351         /*
 352          * If DMA resource was not available during
 353          * probe, no need to continue with dma requests
 354          * else Acquire DMA channels
 355          */
 356         while (!is_polling(sdd) && !acquire_dma(sdd))
 357                 usleep_range(10000, 11000);
 358
 359         pm_runtime_get_sync(&sdd->pdev->dev);
 360
 361         return 0;
 362 }
 363
 364 static int s3c64xx_spi_unprepare_transfer(struct spi_master *spi)
 365 {
 366         struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(spi);
 367
 368         /* Free DMA channels */
 369         if (!is_polling(sdd)) {
 370                 sdd->ops->release((enum dma_ch)sdd->rx_dma.ch,
 371                                         &s3c64xx_spi_dma_client);
 372                 sdd->ops->release((enum dma_ch)sdd->tx_dma.ch,
 373                                         &s3c64xx_spi_dma_client);
 374         }
 375         pm_runtime_put(&sdd->pdev->dev);
 376
 377         return 0;
 378 }
 379
 380 static void s3c64xx_spi_dma_stop(struct s3c64xx_spi_driver_data *sdd,
 381                                  struct s3c64xx_spi_dma_data *dma)
 382 {
 383         sdd->ops->stop((enum dma_ch)dma->ch);
 384 }
 385 #else
 386
 387 static void prepare_dma(struct s3c64xx_spi_dma_data *dma,
 388                                         unsigned len, dma_addr_t buf)
 389 {
 390         struct s3c64xx_spi_driver_data *sdd;
 391         struct dma_slave_config config;
 392         struct scatterlist sg;
 393         struct dma_async_tx_descriptor *desc;
 394
 395         if (dma->direction == DMA_DEV_TO_MEM) {
 396                 sdd = container_of((void *)dma,
 397                         struct s3c64xx_spi_driver_data, rx_dma);
 398                 config.direction = dma->direction;
 399                 config.src_addr = sdd->sfr_start + S3C64XX_SPI_RX_DATA;
 400                 config.src_addr_width = sdd->cur_bpw / 8;
 401                 config.src_maxburst = 1;
 402                 dmaengine_slave_config(dma->ch, &config);
 403         } else {
 404                 sdd = container_of((void *)dma,
 405                         struct s3c64xx_spi_driver_data, tx_dma);
 406                 config.direction = dma->direction;
 407                 config.dst_addr = sdd->sfr_start + S3C64XX_SPI_TX_DATA;
 408                 config.dst_addr_width = sdd->cur_bpw / 8;
 409                 config.dst_maxburst = 1;
 410                 dmaengine_slave_config(dma->ch, &config);
 411         }
 412
 413         sg_init_table(&sg, 1);
 414         sg_dma_len(&sg) = len;
 415         sg_set_page(&sg, pfn_to_page(PFN_DOWN(buf)),
 416                     len, offset_in_page(buf));
 417         sg_dma_address(&sg) = buf;
 418
 419         desc = dmaengine_prep_slave_sg(dma->ch,
 420                 &sg, 1, dma->direction, DMA_PREP_INTERRUPT);
 421
 422         desc->callback = s3c64xx_spi_dmacb;
 423         desc->callback_param = dma;
 424
 425         dmaengine_submit(desc);
 426         dma_async_issue_pending(dma->ch);
 427 }
 428
 429 static int s3c64xx_spi_prepare_transfer(struct spi_master *spi)
 430 {
 431         struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(spi);
 432         dma_filter_fn filter = sdd->cntrlr_info->filter;
 433         struct device *dev = &sdd->pdev->dev;
 434         dma_cap_mask_t mask;
 435         int ret;
 436
 437         dma_cap_zero(mask);
 438         dma_cap_set(DMA_SLAVE, mask);
 439
 440         /* Acquire DMA channels */
 441         sdd->rx_dma.ch = dma_request_slave_channel_compat(mask, filter,
 442                                 (void*)sdd->rx_dma.dmach, dev, "rx");
 443         if (!sdd->rx_dma.ch) {
 444                 dev_err(dev, "Failed to get RX DMA channel\n");
 445                 ret = -EBUSY;
 446                 goto out;
 447         }
 448
 449         sdd->tx_dma.ch = dma_request_slave_channel_compat(mask, filter,
 450                                 (void*)sdd->tx_dma.dmach, dev, "tx");
 451         if (!sdd->tx_dma.ch) {
 452                 dev_err(dev, "Failed to get TX DMA channel\n");
 453                 ret = -EBUSY;
 454                 goto out_rx;
 455         }
 456
 457         ret = pm_runtime_get_sync(&sdd->pdev->dev);
 458         if (ret < 0) {
 459                 dev_err(dev, "Failed to enable device: %d\n", ret);
 460                 goto out_tx;
 461         }
 462
 463         return 0;
 464
 465 out_tx:
 466         dma_release_channel(sdd->tx_dma.ch);
 467 out_rx:
 468         dma_release_channel(sdd->rx_dma.ch);
 469 out:
 470         return ret;
 471 }
 472
 473 static int s3c64xx_spi_unprepare_transfer(struct spi_master *spi)
 474 {
 475         struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(spi);
 476
 477         /* Free DMA channels */
 478         if (!is_polling(sdd)) {
 479                 dma_release_channel(sdd->rx_dma.ch);
 480                 dma_release_channel(sdd->tx_dma.ch);
 481         }
 482
 483         pm_runtime_put(&sdd->pdev->dev);
 484         return 0;
 485 }
 486
 487 static void s3c64xx_spi_dma_stop(struct s3c64xx_spi_driver_data *sdd,
 488                                  struct s3c64xx_spi_dma_data *dma)
 489 {
 490         dmaengine_terminate_all(dma->ch);
 491 }
 492 #endif
 493
 494 static void enable_datapath(struct s3c64xx_spi_driver_data *sdd,
 495                                 struct spi_device *spi,
 496                                 struct spi_transfer *xfer, int dma_mode)
 497 {
 498         void __iomem *regs = sdd->regs;
 499         u32 modecfg, chcfg;
 500
 501         modecfg = readl(regs + S3C64XX_SPI_MODE_CFG);
 502         modecfg &= ~(S3C64XX_SPI_MODE_TXDMA_ON | S3C64XX_SPI_MODE_RXDMA_ON);
 503
 504         chcfg = readl(regs + S3C64XX_SPI_CH_CFG);
 505         chcfg &= ~S3C64XX_SPI_CH_TXCH_ON;
 506
 507         if (dma_mode) {
 508                 chcfg &= ~S3C64XX_SPI_CH_RXCH_ON;
 509         } else {
 510                 /* Always shift in data in FIFO, even if xfer is Tx only,
 511                  * this helps setting PCKT_CNT value for generating clocks
 512                  * as exactly needed.
 513                  */
 514                 chcfg |= S3C64XX_SPI_CH_RXCH_ON;
 515                 writel(((xfer->len * 8 / sdd->cur_bpw) & 0xffff)
 516                                         | S3C64XX_SPI_PACKET_CNT_EN,
 517                                         regs + S3C64XX_SPI_PACKET_CNT);
 518         }
 519
 520         if (xfer->tx_buf != NULL) {
 521                 sdd->state |= TXBUSY;
 522                 chcfg |= S3C64XX_SPI_CH_TXCH_ON;
 523                 if (dma_mode) {
 524                         modecfg |= S3C64XX_SPI_MODE_TXDMA_ON;
 525                         prepare_dma(&sdd->tx_dma, xfer->len, xfer->tx_dma);
 526                 } else {
 527                         switch (sdd->cur_bpw) {
 528                         case 32:
 529                                 iowrite32_rep(regs + S3C64XX_SPI_TX_DATA,
 530                                         xfer->tx_buf, xfer->len / 4);
 531                                 break;
 532                         case 16:
 533                                 iowrite16_rep(regs + S3C64XX_SPI_TX_DATA,
 534                                         xfer->tx_buf, xfer->len / 2);
 535                                 break;
 536                         default:
 537                                 iowrite8_rep(regs + S3C64XX_SPI_TX_DATA,
 538                                         xfer->tx_buf, xfer->len);
 539                                 break;
 540                         }
 541                 }
 542         }
 543
 544         if (xfer->rx_buf != NULL) {
 545                 sdd->state |= RXBUSY;
 546
 547                 if (sdd->port_conf->high_speed && sdd->cur_speed >= 30000000UL
 548                                         && !(sdd->cur_mode & SPI_CPHA))
 549                         chcfg |= S3C64XX_SPI_CH_HS_EN;
 550
 551                 if (dma_mode) {
 552                         modecfg |= S3C64XX_SPI_MODE_RXDMA_ON;
 553                         chcfg |= S3C64XX_SPI_CH_RXCH_ON;
 554                         writel(((xfer->len * 8 / sdd->cur_bpw) & 0xffff)
 555                                         | S3C64XX_SPI_PACKET_CNT_EN,
 556                                         regs + S3C64XX_SPI_PACKET_CNT);
 557                         prepare_dma(&sdd->rx_dma, xfer->len, xfer->rx_dma);
 558                 }
 559         }
 560
 561         writel(modecfg, regs + S3C64XX_SPI_MODE_CFG);
 562         writel(chcfg, regs + S3C64XX_SPI_CH_CFG);
 563 }
 564
 565 static inline void enable_cs(struct s3c64xx_spi_driver_data *sdd,
 566                                                 struct spi_device *spi)
 567 {
 568         struct s3c64xx_spi_csinfo *cs;
 569
 570         if (sdd->tgl_spi != NULL) { /* If last device toggled after mssg */
 571                 if (sdd->tgl_spi != spi) { /* if last mssg on diff device */
 572                         /* Deselect the last toggled device */
 573                         cs = sdd->tgl_spi->controller_data;
 574                         if (sdd->cs_gpio)
 575                                 gpio_set_value(cs->line,
 576                                         spi->mode & SPI_CS_HIGH ? 0 : 1);
 577                 }
 578                 sdd->tgl_spi = NULL;
 579         }
 580
 581         cs = spi->controller_data;
 582         if (sdd->cs_gpio)
 583                 gpio_set_value(cs->line, spi->mode & SPI_CS_HIGH ? 1 : 0);
 584
 585         /* Start the signals */
 586         writel(0, sdd->regs + S3C64XX_SPI_SLAVE_SEL);
 587 }
 588
 589 static u32 s3c64xx_spi_wait_for_timeout(struct s3c64xx_spi_driver_data *sdd,
 590                                         int timeout_ms)
 591 {
 592         void __iomem *regs = sdd->regs;
 593         unsigned long val = 1;
 594         u32 status;
 595
 596         /* max fifo depth available */
 597         u32 max_fifo = (FIFO_LVL_MASK(sdd) >> 1) + 1;
 598
 599         if (timeout_ms)
 600                 val = msecs_to_loops(timeout_ms);
 601
 602         do {
 603                 status = readl(regs + S3C64XX_SPI_STATUS);
 604         } while (RX_FIFO_LVL(status, sdd) < max_fifo && --val);
 605
 606         /* return the actual received data length */
 607         return RX_FIFO_LVL(status, sdd);
 608 }
 609
 610 static int wait_for_xfer(struct s3c64xx_spi_driver_data *sdd,
 611                                 struct spi_transfer *xfer, int dma_mode)
 612 {
 613         void __iomem *regs = sdd->regs;
 614         unsigned long val;
 615         int ms;
 616
 617         /* millisecs to xfer 'len' bytes @ 'cur_speed' */
 618         ms = xfer->len * 8 * 1000 / sdd->cur_speed;
 619         ms += 10; /* some tolerance */
 620
 621         if (dma_mode) {
 622                 val = msecs_to_jiffies(ms) + 10;
 623                 val = wait_for_completion_timeout(&sdd->xfer_completion, val);
 624         } else {
 625                 u32 status;
 626                 val = msecs_to_loops(ms);
 627                 do {
 628                         status = readl(regs + S3C64XX_SPI_STATUS);
 629                 } while (RX_FIFO_LVL(status, sdd) < xfer->len && --val);
 630         }
 631
 632         if (dma_mode) {
 633                 u32 status;
 634
 635                 /*
 636                  * If the previous xfer was completed within timeout, then
 637                  * proceed further else return -EIO.
 638                  * DmaTx returns after simply writing data in the FIFO,
 639                  * w/o waiting for real transmission on the bus to finish.
 640                  * DmaRx returns only after Dma read data from FIFO which
 641                  * needs bus transmission to finish, so we don't worry if
 642                  * Xfer involved Rx(with or without Tx).
 643                  */
 644                 if (val && !xfer->rx_buf) {
 645                         val = msecs_to_loops(10);
 646                         status = readl(regs + S3C64XX_SPI_STATUS);
 647                         while ((TX_FIFO_LVL(status, sdd)
 648                                 || !S3C64XX_SPI_ST_TX_DONE(status, sdd))
 649                                         && --val) {
 650                                 cpu_relax();
 651                                 status = readl(regs + S3C64XX_SPI_STATUS);
 652                         }
 653
 654                 }
 655
 656                 /* If timed out while checking rx/tx status return error */
 657                 if (!val)
 658                         return -EIO;
 659         } else {
 660                 int loops;
 661                 u32 cpy_len;
 662                 u8 *buf;
 663
 664                 /* If it was only Tx */
 665                 if (!xfer->rx_buf) {
 666                         sdd->state &= ~TXBUSY;
 667                         return 0;
 668                 }
 669
 670                 /*
 671                  * If the receive length is bigger than the controller fifo
 672                  * size, calculate the loops and read the fifo as many times.
 673                  * loops = length / max fifo size (calculated by using the
 674                  * fifo mask).
 675                  * For any size less than the fifo size the below code is
 676                  * executed atleast once.
 677                  */
 678                 loops = xfer->len / ((FIFO_LVL_MASK(sdd) >> 1) + 1);
 679                 buf = xfer->rx_buf;
 680                 do {
 681                         /* wait for data to be received in the fifo */
 682                         cpy_len = s3c64xx_spi_wait_for_timeout(sdd,
 683                                                 (loops ? ms : 0));
 684
 685                         switch (sdd->cur_bpw) {
 686                         case 32:
 687                                 ioread32_rep(regs + S3C64XX_SPI_RX_DATA,
 688                                         buf, cpy_len / 4);
 689                                 break;
 690                         case 16:
 691                                 ioread16_rep(regs + S3C64XX_SPI_RX_DATA,
 692                                         buf, cpy_len / 2);
 693                                 break;
 694                         default:
 695                                 ioread8_rep(regs + S3C64XX_SPI_RX_DATA,
 696                                         buf, cpy_len);
 697                                 break;
 698                         }
 699
 700                         buf = buf + cpy_len;
 701                 } while (loops--);
 702                 sdd->state &= ~RXBUSY;
 703         }
 704
 705         return 0;
 706 }
 707
 708 static inline void disable_cs(struct s3c64xx_spi_driver_data *sdd,
 709                                                 struct spi_device *spi)
 710 {
 711         struct s3c64xx_spi_csinfo *cs = spi->controller_data;
 712
 713         if (sdd->tgl_spi == spi)
 714                 sdd->tgl_spi = NULL;
 715
 716         if (sdd->cs_gpio)
 717                 gpio_set_value(cs->line, spi->mode & SPI_CS_HIGH ? 0 : 1);
 718
 719         /* Quiese the signals */
 720         writel(S3C64XX_SPI_SLAVE_SIG_INACT, sdd->regs + S3C64XX_SPI_SLAVE_SEL);
 721 }
 722
 723 static void s3c64xx_spi_config(struct s3c64xx_spi_driver_data *sdd)
 724 {
 725         void __iomem *regs = sdd->regs;
 726         u32 val;
 727
 728         /* Disable Clock */
 729         if (sdd->port_conf->clk_from_cmu) {
 730                 clk_disable_unprepare(sdd->src_clk);
 731         } else {
 732                 val = readl(regs + S3C64XX_SPI_CLK_CFG);
 733                 val &= ~S3C64XX_SPI_ENCLK_ENABLE;
 734                 writel(val, regs + S3C64XX_SPI_CLK_CFG);
 735         }
 736
 737         /* Set Polarity and Phase */
 738         val = readl(regs + S3C64XX_SPI_CH_CFG);
 739         val &= ~(S3C64XX_SPI_CH_SLAVE |
 740                         S3C64XX_SPI_CPOL_L |
 741                         S3C64XX_SPI_CPHA_B);
 742
 743         if (sdd->cur_mode & SPI_CPOL)
 744                 val |= S3C64XX_SPI_CPOL_L;
 745
 746         if (sdd->cur_mode & SPI_CPHA)
 747                 val |= S3C64XX_SPI_CPHA_B;
 748
 749         writel(val, regs + S3C64XX_SPI_CH_CFG);
 750
 751         /* Set Channel & DMA Mode */
 752         val = readl(regs + S3C64XX_SPI_MODE_CFG);
 753         val &= ~(S3C64XX_SPI_MODE_BUS_TSZ_MASK
 754                         | S3C64XX_SPI_MODE_CH_TSZ_MASK);
 755
 756         switch (sdd->cur_bpw) {
 757         case 32:
 758                 val |= S3C64XX_SPI_MODE_BUS_TSZ_WORD;
 759                 val |= S3C64XX_SPI_MODE_CH_TSZ_WORD;
 760                 break;
 761         case 16:
 762                 val |= S3C64XX_SPI_MODE_BUS_TSZ_HALFWORD;
 763                 val |= S3C64XX_SPI_MODE_CH_TSZ_HALFWORD;
 764                 break;
 765         default:
 766                 val |= S3C64XX_SPI_MODE_BUS_TSZ_BYTE;
 767                 val |= S3C64XX_SPI_MODE_CH_TSZ_BYTE;
 768                 break;
 769         }
 770
 771         writel(val, regs + S3C64XX_SPI_MODE_CFG);
 772
 773         if (sdd->port_conf->clk_from_cmu) {
 774                 /* Configure Clock */
 775                 /* There is half-multiplier before the SPI */
 776                 clk_set_rate(sdd->src_clk, sdd->cur_speed * 2);
 777                 /* Enable Clock */
 778                 clk_prepare_enable(sdd->src_clk);
 779         } else {
 780                 /* Configure Clock */
 781                 val = readl(regs + S3C64XX_SPI_CLK_CFG);
 782                 val &= ~S3C64XX_SPI_PSR_MASK;
 783                 val |= ((clk_get_rate(sdd->src_clk) / sdd->cur_speed / 2 - 1)
 784                                 & S3C64XX_SPI_PSR_MASK);
 785                 writel(val, regs + S3C64XX_SPI_CLK_CFG);
 786
 787                 /* Enable Clock */
 788                 val = readl(regs + S3C64XX_SPI_CLK_CFG);
 789                 val |= S3C64XX_SPI_ENCLK_ENABLE;
 790                 writel(val, regs + S3C64XX_SPI_CLK_CFG);
 791         }
 792 }
 793
 794 #define XFER_DMAADDR_INVALID DMA_BIT_MASK(32)
 795
 796 static int s3c64xx_spi_map_mssg(struct s3c64xx_spi_driver_data *sdd,
 797                                                 struct spi_message *msg)
 798 {
 799         struct device *dev = &sdd->pdev->dev;
 800         struct spi_transfer *xfer;
 801
 802         if (is_polling(sdd) || msg->is_dma_mapped)
 803                 return 0;
 804
 805         /* First mark all xfer unmapped */
 806         list_for_each_entry(xfer, &msg->transfers, transfer_list) {
 807                 xfer->rx_dma = XFER_DMAADDR_INVALID;
 808                 xfer->tx_dma = XFER_DMAADDR_INVALID;
 809         }
 810
 811         /* Map until end or first fail */
 812         list_for_each_entry(xfer, &msg->transfers, transfer_list) {
 813
 814                 if (xfer->len <= ((FIFO_LVL_MASK(sdd) >> 1) + 1))
 815                         continue;
 816
 817                 if (xfer->tx_buf != NULL) {
 818                         xfer->tx_dma = dma_map_single(dev,
 819                                         (void *)xfer->tx_buf, xfer->len,
 820                                         DMA_TO_DEVICE);
 821                         if (dma_mapping_error(dev, xfer->tx_dma)) {
 822                                 dev_err(dev, "dma_map_single Tx failed\n");
 823                                 xfer->tx_dma = XFER_DMAADDR_INVALID;
 824                                 return -ENOMEM;
 825                         }
 826                 }
 827
 828                 if (xfer->rx_buf != NULL) {
 829                         xfer->rx_dma = dma_map_single(dev, xfer->rx_buf,
 830                                                 xfer->len, DMA_FROM_DEVICE);
 831                         if (dma_mapping_error(dev, xfer->rx_dma)) {
 832                                 dev_err(dev, "dma_map_single Rx failed\n");
 833                                 dma_unmap_single(dev, xfer->tx_dma,
 834                                                 xfer->len, DMA_TO_DEVICE);
 835                                 xfer->tx_dma = XFER_DMAADDR_INVALID;
 836                                 xfer->rx_dma = XFER_DMAADDR_INVALID;
 837                                 return -ENOMEM;
 838                         }
 839                 }
 840         }
 841
 842         return 0;
 843 }
 844
 845 static void s3c64xx_spi_unmap_mssg(struct s3c64xx_spi_driver_data *sdd,
 846                                                 struct spi_message *msg)
 847 {
 848         struct device *dev = &sdd->pdev->dev;
 849         struct spi_transfer *xfer;
 850
 851         if (is_polling(sdd) || msg->is_dma_mapped)
 852                 return;
 853
 854         list_for_each_entry(xfer, &msg->transfers, transfer_list) {
 855
 856                 if (xfer->len <= ((FIFO_LVL_MASK(sdd) >> 1) + 1))
 857                         continue;
 858
 859                 if (xfer->rx_buf != NULL
 860                                 && xfer->rx_dma != XFER_DMAADDR_INVALID)
 861                         dma_unmap_single(dev, xfer->rx_dma,
 862                                                 xfer->len, DMA_FROM_DEVICE);
 863
 864                 if (xfer->tx_buf != NULL
 865                                 && xfer->tx_dma != XFER_DMAADDR_INVALID)
 866                         dma_unmap_single(dev, xfer->tx_dma,
 867                                                 xfer->len, DMA_TO_DEVICE);
 868         }
 869 }
 870
 871 static int s3c64xx_spi_transfer_one_message(struct spi_master *master,
 872                                             struct spi_message *msg)
 873 {
 874         struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
 875         struct spi_device *spi = msg->spi;
 876         struct s3c64xx_spi_csinfo *cs = spi->controller_data;
 877         struct spi_transfer *xfer;
 878         int status = 0, cs_toggle = 0;
 879         u32 speed;
 880         u8 bpw;
 881
 882         /* If Master's(controller) state differs from that needed by Slave */
 883         if (sdd->cur_speed != spi->max_speed_hz
 884                         || sdd->cur_mode != spi->mode
 885                         || sdd->cur_bpw != spi->bits_per_word) {
 886                 sdd->cur_bpw = spi->bits_per_word;
 887                 sdd->cur_speed = spi->max_speed_hz;
 888                 sdd->cur_mode = spi->mode;
 889                 s3c64xx_spi_config(sdd);
 890         }
 891
 892         /* Map all the transfers if needed */
 893         if (s3c64xx_spi_map_mssg(sdd, msg)) {
 894                 dev_err(&spi->dev,
 895                         "Xfer: Unable to map message buffers!\n");
 896                 status = -ENOMEM;
 897                 goto out;
 898         }
 899
 900         /* Configure feedback delay */
 901         writel(cs->fb_delay & 0x3, sdd->regs + S3C64XX_SPI_FB_CLK);
 902
 903         list_for_each_entry(xfer, &msg->transfers, transfer_list) {
 904
 905                 unsigned long flags;
 906                 int use_dma;
 907
 908                 INIT_COMPLETION(sdd->xfer_completion);
 909
 910                 /* Only BPW and Speed may change across transfers */
 911                 bpw = xfer->bits_per_word;
 912                 speed = xfer->speed_hz ? : spi->max_speed_hz;
 913
 914                 if (xfer->len % (bpw / 8)) {
 915                         dev_err(&spi->dev,
 916                                 "Xfer length(%u) not a multiple of word size(%u)\n",
 917                                 xfer->len, bpw / 8);
 918                         status = -EIO;
 919                         goto out;
 920                 }
 921
 922                 if (bpw != sdd->cur_bpw || speed != sdd->cur_speed) {
 923                         sdd->cur_bpw = bpw;
 924                         sdd->cur_speed = speed;
 925                         s3c64xx_spi_config(sdd);
 926                 }
 927
 928                 /* Polling method for xfers not bigger than FIFO capacity */
 929                 use_dma = 0;
 930                 if (!is_polling(sdd) &&
 931                         (sdd->rx_dma.ch && sdd->tx_dma.ch &&
 932                         (xfer->len > ((FIFO_LVL_MASK(sdd) >> 1) + 1))))
 933                         use_dma = 1;
 934
 935                 spin_lock_irqsave(&sdd->lock, flags);
 936
 937                 /* Pending only which is to be done */
 938                 sdd->state &= ~RXBUSY;
 939                 sdd->state &= ~TXBUSY;
 940
 941                 enable_datapath(sdd, spi, xfer, use_dma);
 942
 943                 /* Slave Select */
 944                 enable_cs(sdd, spi);
 945
 946                 spin_unlock_irqrestore(&sdd->lock, flags);
 947
 948                 status = wait_for_xfer(sdd, xfer, use_dma);
 949
 950                 if (status) {
 951                         dev_err(&spi->dev, "I/O Error: rx-%d tx-%d res:rx-%c tx-%c len-%d\n",
 952                                 xfer->rx_buf ? 1 : 0, xfer->tx_buf ? 1 : 0,
 953                                 (sdd->state & RXBUSY) ? 'f' : 'p',
 954                                 (sdd->state & TXBUSY) ? 'f' : 'p',
 955                                 xfer->len);
 956
 957                         if (use_dma) {
 958                                 if (xfer->tx_buf != NULL
 959                                                 && (sdd->state & TXBUSY))
 960                                         s3c64xx_spi_dma_stop(sdd, &sdd->tx_dma);
 961                                 if (xfer->rx_buf != NULL
 962                                                 && (sdd->state & RXBUSY))
 963                                         s3c64xx_spi_dma_stop(sdd, &sdd->rx_dma);
 964                         }
 965
 966                         goto out;
 967                 }
 968
 969                 if (xfer->delay_usecs)
 970                         udelay(xfer->delay_usecs);
 971
 972                 if (xfer->cs_change) {
 973                         /* Hint that the next mssg is gonna be
 974                            for the same device */
 975                         if (list_is_last(&xfer->transfer_list,
 976                                                 &msg->transfers))
 977                                 cs_toggle = 1;
 978                 }
 979
 980                 msg->actual_length += xfer->len;
 981
 982                 flush_fifo(sdd);
 983         }
 984
 985 out:
 986         if (!cs_toggle || status)
 987                 disable_cs(sdd, spi);
 988         else
 989                 sdd->tgl_spi = spi;
 990
 991         s3c64xx_spi_unmap_mssg(sdd, msg);
 992
 993         msg->status = status;
 994
 995         spi_finalize_current_message(master);
 996
 997         return 0;
 998 }
 999
1000 static struct s3c64xx_spi_csinfo *s3c64xx_get_slave_ctrldata(
1001                                 struct spi_device *spi)
1002 {
1003         struct s3c64xx_spi_csinfo *cs;
1004         struct device_node *slave_np, *data_np = NULL;
1005         struct s3c64xx_spi_driver_data *sdd;
1006         u32 fb_delay = 0;
1007
1008         sdd = spi_master_get_devdata(spi->master);
1009         slave_np = spi->dev.of_node;
1010         if (!slave_np) {
1011                 dev_err(&spi->dev, "device node not found\n");
1012                 return ERR_PTR(-EINVAL);
1013         }
1014
1015         data_np = of_get_child_by_name(slave_np, "controller-data");
1016         if (!data_np) {
1017                 dev_err(&spi->dev, "child node 'controller-data' not found\n");
1018                 return ERR_PTR(-EINVAL);
1019         }
1020
1021         cs = kzalloc(sizeof(*cs), GFP_KERNEL);
1022         if (!cs) {
1023                 dev_err(&spi->dev, "could not allocate memory for controller data\n");
1024                 of_node_put(data_np);
1025                 return ERR_PTR(-ENOMEM);
1026         }
1027
1028         /* The CS line is asserted/deasserted by the gpio pin */
1029         if (sdd->cs_gpio)
1030                 cs->line = of_get_named_gpio(data_np, "cs-gpio", 0);
1031
1032         if (!gpio_is_valid(cs->line)) {
1033                 dev_err(&spi->dev, "chip select gpio is not specified or invalid\n");
1034                 kfree(cs);
1035                 of_node_put(data_np);
1036                 return ERR_PTR(-EINVAL);
1037         }
1038
1039         of_property_read_u32(data_np, "samsung,spi-feedback-delay", &fb_delay);
1040         cs->fb_delay = fb_delay;
1041         of_node_put(data_np);
1042         return cs;
1043 }
1044
1045 /*
1046  * Here we only check the validity of requested configuration
1047  * and save the configuration in a local data-structure.
1048  * The controller is actually configured only just before we
1049  * get a message to transfer.
1050  */
1051 static int s3c64xx_spi_setup(struct spi_device *spi)
1052 {
1053         struct s3c64xx_spi_csinfo *cs = spi->controller_data;
1054         struct s3c64xx_spi_driver_data *sdd;
1055         struct s3c64xx_spi_info *sci;
1056         struct spi_message *msg;
1057         unsigned long flags;
1058         int err;
1059
1060         sdd = spi_master_get_devdata(spi->master);
1061         if (!cs && spi->dev.of_node) {
1062                 cs = s3c64xx_get_slave_ctrldata(spi);
1063                 spi->controller_data = cs;
1064         }
1065
1066         if (IS_ERR_OR_NULL(cs)) {
1067                 dev_err(&spi->dev, "No CS for SPI(%d)\n", spi->chip_select);
1068                 return -ENODEV;
1069         }
1070
1071         /* Request gpio only if cs line is asserted by gpio pins */
1072         if (sdd->cs_gpio) {
1073                 err = gpio_request_one(cs->line, GPIOF_OUT_INIT_HIGH,
1074                                        dev_name(&spi->dev));
1075                 if (err) {
1076                         dev_err(&spi->dev,
1077                                 "Failed to get /CS gpio [%d]: %d\n",
1078                                 cs->line, err);
1079                         goto err_gpio_req;
1080                 }
1081         }
1082
1083         if (!spi_get_ctldata(spi))
1084                 spi_set_ctldata(spi, cs);
1085
1086         sci = sdd->cntrlr_info;
1087
1088         spin_lock_irqsave(&sdd->lock, flags);
1089
1090         list_for_each_entry(msg, &sdd->queue, queue) {
1091                 /* Is some mssg is already queued for this device */
1092                 if (msg->spi == spi) {
1093                         dev_err(&spi->dev,
1094                                 "setup: attempt while mssg in queue!\n");
1095                         spin_unlock_irqrestore(&sdd->lock, flags);
1096                         err = -EBUSY;
1097                         goto err_msgq;
1098                 }
1099         }
1100
1101         spin_unlock_irqrestore(&sdd->lock, flags);
1102
1103         pm_runtime_get_sync(&sdd->pdev->dev);
1104
1105         /* Check if we can provide the requested rate */
1106         if (!sdd->port_conf->clk_from_cmu) {
1107                 u32 psr, speed;
1108
1109                 /* Max possible */
1110                 speed = clk_get_rate(sdd->src_clk) / 2 / (0 + 1);
1111
1112                 if (spi->max_speed_hz > speed)
1113                         spi->max_speed_hz = speed;
1114
1115                 psr = clk_get_rate(sdd->src_clk) / 2 / spi->max_speed_hz - 1;
1116                 psr &= S3C64XX_SPI_PSR_MASK;
1117                 if (psr == S3C64XX_SPI_PSR_MASK)
1118                         psr--;
1119
1120                 speed = clk_get_rate(sdd->src_clk) / 2 / (psr + 1);
1121                 if (spi->max_speed_hz < speed) {
1122                         if (psr+1 < S3C64XX_SPI_PSR_MASK) {
1123                                 psr++;
1124                         } else {
1125                                 err = -EINVAL;
1126                                 goto setup_exit;
1127                         }
1128                 }
1129
1130                 speed = clk_get_rate(sdd->src_clk) / 2 / (psr + 1);
1131                 if (spi->max_speed_hz >= speed) {
1132                         spi->max_speed_hz = speed;
1133                 } else {
1134                         dev_err(&spi->dev, "Can't set %dHz transfer speed\n",
1135                                 spi->max_speed_hz);
1136                         err = -EINVAL;
1137                         goto setup_exit;
1138                 }
1139         }
1140
1141         pm_runtime_put(&sdd->pdev->dev);
1142         disable_cs(sdd, spi);
1143         return 0;
1144
1145 setup_exit:
1146         /* setup() returns with device de-selected */
1147         disable_cs(sdd, spi);
1148
1149 err_msgq:
1150         gpio_free(cs->line);
1151         spi_set_ctldata(spi, NULL);
1152
1153 err_gpio_req:
1154         if (spi->dev.of_node)
1155                 kfree(cs);
1156
1157         return err;
1158 }
1159
1160 static void s3c64xx_spi_cleanup(struct spi_device *spi)
1161 {
1162         struct s3c64xx_spi_csinfo *cs = spi_get_ctldata(spi);
1163         struct s3c64xx_spi_driver_data *sdd;
1164
1165         sdd = spi_master_get_devdata(spi->master);
1166         if (cs && sdd->cs_gpio) {
1167                 gpio_free(cs->line);
1168                 if (spi->dev.of_node)
1169                         kfree(cs);
1170         }
1171         spi_set_ctldata(spi, NULL);
1172 }
1173
1174 static irqreturn_t s3c64xx_spi_irq(int irq, void *data)
1175 {
1176         struct s3c64xx_spi_driver_data *sdd = data;
1177         struct spi_master *spi = sdd->master;
1178         unsigned int val, clr = 0;
1179
1180         val = readl(sdd->regs + S3C64XX_SPI_STATUS);
1181
1182         if (val & S3C64XX_SPI_ST_RX_OVERRUN_ERR) {
1183                 clr = S3C64XX_SPI_PND_RX_OVERRUN_CLR;
1184                 dev_err(&spi->dev, "RX overrun\n");
1185         }
1186         if (val & S3C64XX_SPI_ST_RX_UNDERRUN_ERR) {
1187                 clr |= S3C64XX_SPI_PND_RX_UNDERRUN_CLR;
1188                 dev_err(&spi->dev, "RX underrun\n");
1189         }
1190         if (val & S3C64XX_SPI_ST_TX_OVERRUN_ERR) {
1191                 clr |= S3C64XX_SPI_PND_TX_OVERRUN_CLR;
1192                 dev_err(&spi->dev, "TX overrun\n");
1193         }
1194         if (val & S3C64XX_SPI_ST_TX_UNDERRUN_ERR) {
1195                 clr |= S3C64XX_SPI_PND_TX_UNDERRUN_CLR;
1196                 dev_err(&spi->dev, "TX underrun\n");
1197         }
1198
1199         /* Clear the pending irq by setting and then clearing it */
1200         writel(clr, sdd->regs + S3C64XX_SPI_PENDING_CLR);
1201         writel(0, sdd->regs + S3C64XX_SPI_PENDING_CLR);
1202
1203         return IRQ_HANDLED;
1204 }
1205
1206 static void s3c64xx_spi_hwinit(struct s3c64xx_spi_driver_data *sdd, int channel)
1207 {
1208         struct s3c64xx_spi_info *sci = sdd->cntrlr_info;
1209         void __iomem *regs = sdd->regs;
1210         unsigned int val;
1211
1212         sdd->cur_speed = 0;
1213
1214         writel(S3C64XX_SPI_SLAVE_SIG_INACT, sdd->regs + S3C64XX_SPI_SLAVE_SEL);
1215
1216         /* Disable Interrupts - we use Polling if not DMA mode */
1217         writel(0, regs + S3C64XX_SPI_INT_EN);
1218
1219         if (!sdd->port_conf->clk_from_cmu)
1220                 writel(sci->src_clk_nr << S3C64XX_SPI_CLKSEL_SRCSHFT,
1221                                 regs + S3C64XX_SPI_CLK_CFG);
1222         writel(0, regs + S3C64XX_SPI_MODE_CFG);
1223         writel(0, regs + S3C64XX_SPI_PACKET_CNT);
1224
1225         /* Clear any irq pending bits, should set and clear the bits */
1226         val = S3C64XX_SPI_PND_RX_OVERRUN_CLR |
1227                 S3C64XX_SPI_PND_RX_UNDERRUN_CLR |
1228                 S3C64XX_SPI_PND_TX_OVERRUN_CLR |
1229                 S3C64XX_SPI_PND_TX_UNDERRUN_CLR;
1230         writel(val, regs + S3C64XX_SPI_PENDING_CLR);
1231         writel(0, regs + S3C64XX_SPI_PENDING_CLR);
1232
1233         writel(0, regs + S3C64XX_SPI_SWAP_CFG);
1234
1235         val = readl(regs + S3C64XX_SPI_MODE_CFG);
1236         val &= ~S3C64XX_SPI_MODE_4BURST;
1237         val &= ~(S3C64XX_SPI_MAX_TRAILCNT << S3C64XX_SPI_TRAILCNT_OFF);
1238         val |= (S3C64XX_SPI_TRAILCNT << S3C64XX_SPI_TRAILCNT_OFF);
1239         writel(val, regs + S3C64XX_SPI_MODE_CFG);
1240
1241         flush_fifo(sdd);
1242 }
1243
1244 #ifdef CONFIG_OF
1245 static struct s3c64xx_spi_info *s3c64xx_spi_parse_dt(struct device *dev)
1246 {
1247         struct s3c64xx_spi_info *sci;
1248         u32 temp;
1249
1250         sci = devm_kzalloc(dev, sizeof(*sci), GFP_KERNEL);
1251         if (!sci) {
1252                 dev_err(dev, "memory allocation for spi_info failed\n");
1253                 return ERR_PTR(-ENOMEM);
1254         }
1255
1256         if (of_property_read_u32(dev->of_node, "samsung,spi-src-clk", &temp)) {
1257                 dev_warn(dev, "spi bus clock parent not specified, using clock at index 0 as parent\n");
1258                 sci->src_clk_nr = 0;
1259         } else {
1260                 sci->src_clk_nr = temp;
1261         }
1262
1263         if (of_property_read_u32(dev->of_node, "num-cs", &temp)) {
1264                 dev_warn(dev, "number of chip select lines not specified, assuming 1 chip select line\n");
1265                 sci->num_cs = 1;
1266         } else {
1267                 sci->num_cs = temp;
1268         }
1269
1270         return sci;
1271 }
1272 #else
1273 static struct s3c64xx_spi_info *s3c64xx_spi_parse_dt(struct device *dev)
1274 {
1275         return dev->platform_data;
1276 }
1277 #endif
1278
1279 static const struct of_device_id s3c64xx_spi_dt_match[];
1280
1281 static inline struct s3c64xx_spi_port_config *s3c64xx_spi_get_port_config(
1282                                                 struct platform_device *pdev)
1283 {
1284 #ifdef CONFIG_OF
1285         if (pdev->dev.of_node) {
1286                 const struct of_device_id *match;
1287                 match = of_match_node(s3c64xx_spi_dt_match, pdev->dev.of_node);
1288                 return (struct s3c64xx_spi_port_config *)match->data;
1289         }
1290 #endif
1291         return (struct s3c64xx_spi_port_config *)
1292                          platform_get_device_id(pdev)->driver_data;
1293 }
1294
1295 static int s3c64xx_spi_probe(struct platform_device *pdev)
1296 {
1297         struct resource *mem_res;
1298         struct resource *res;
1299         struct s3c64xx_spi_driver_data *sdd;
1300         struct s3c64xx_spi_info *sci = pdev->dev.platform_data;
1301         struct spi_master *master;
1302         int ret, irq;
1303         char clk_name[16];
1304
1305         if (!sci && pdev->dev.of_node) {
1306                 sci = s3c64xx_spi_parse_dt(&pdev->dev);
1307                 if (IS_ERR(sci))
1308                         return PTR_ERR(sci);
1309         }
1310
1311         if (!sci) {
1312                 dev_err(&pdev->dev, "platform_data missing!\n");
1313                 return -ENODEV;
1314         }
1315
1316         mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1317         if (mem_res == NULL) {
1318                 dev_err(&pdev->dev, "Unable to get SPI MEM resource\n");
1319                 return -ENXIO;
1320         }
1321
1322         irq = platform_get_irq(pdev, 0);
1323         if (irq < 0) {
1324                 dev_warn(&pdev->dev, "Failed to get IRQ: %d\n", irq);
1325                 return irq;
1326         }
1327
1328         master = spi_alloc_master(&pdev->dev,
1329                                 sizeof(struct s3c64xx_spi_driver_data));
1330         if (master == NULL) {
1331                 dev_err(&pdev->dev, "Unable to allocate SPI Master\n");
1332                 return -ENOMEM;
1333         }
1334
1335         platform_set_drvdata(pdev, master);
1336
1337         sdd = spi_master_get_devdata(master);
1338         sdd->port_conf = s3c64xx_spi_get_port_config(pdev);
1339         sdd->master = master;
1340         sdd->cntrlr_info = sci;
1341         sdd->pdev = pdev;
1342         sdd->sfr_start = mem_res->start;
1343         sdd->cs_gpio = true;
1344         if (pdev->dev.of_node) {
1345                 if (!of_find_property(pdev->dev.of_node, "cs-gpio", NULL))
1346                         sdd->cs_gpio = false;
1347
1348                 ret = of_alias_get_id(pdev->dev.of_node, "spi");
1349                 if (ret < 0) {
1350                         dev_err(&pdev->dev, "failed to get alias id, errno %d\n",
1351                                 ret);
1352                         goto err0;
1353                 }
1354                 sdd->port_id = ret;
1355         } else {
1356                 sdd->port_id = pdev->id;
1357         }
1358
1359         sdd->cur_bpw = 8;
1360
1361         if (!sdd->pdev->dev.of_node) {
1362                 res = platform_get_resource(pdev, IORESOURCE_DMA,  0);
1363                 if (!res) {
1364                         dev_warn(&pdev->dev, "Unable to get SPI tx dma "
1365                                         "resource. Switching to poll mode\n");
1366                         sdd->port_conf->quirks = S3C64XX_SPI_QUIRK_POLL;
1367                 } else
1368                         sdd->tx_dma.dmach = res->start;
1369
1370                 res = platform_get_resource(pdev, IORESOURCE_DMA,  1);
1371                 if (!res) {
1372                         dev_warn(&pdev->dev, "Unable to get SPI rx dma "
1373                                         "resource. Switching to poll mode\n");
1374                         sdd->port_conf->quirks = S3C64XX_SPI_QUIRK_POLL;
1375                 } else
1376                         sdd->rx_dma.dmach = res->start;
1377         }
1378
1379         sdd->tx_dma.direction = DMA_MEM_TO_DEV;
1380         sdd->rx_dma.direction = DMA_DEV_TO_MEM;
1381
1382         master->dev.of_node = pdev->dev.of_node;
1383         master->bus_num = sdd->port_id;
1384         master->setup = s3c64xx_spi_setup;
1385         master->cleanup = s3c64xx_spi_cleanup;
1386         master->prepare_transfer_hardware = s3c64xx_spi_prepare_transfer;
1387         master->transfer_one_message = s3c64xx_spi_transfer_one_message;
1388         master->unprepare_transfer_hardware = s3c64xx_spi_unprepare_transfer;
1389         master->num_chipselect = sci->num_cs;
1390         master->dma_alignment = 8;
1391         master->bits_per_word_mask = SPI_BPW_MASK(32) | SPI_BPW_MASK(16) |
1392                                         SPI_BPW_MASK(8);
1393         /* the spi->mode bits understood by this driver: */
1394         master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
1395
1396         sdd->regs = devm_ioremap_resource(&pdev->dev, mem_res);
1397         if (IS_ERR(sdd->regs)) {
1398                 ret = PTR_ERR(sdd->regs);
1399                 goto err0;
1400         }
1401
1402         if (sci->cfg_gpio && sci->cfg_gpio()) {
1403                 dev_err(&pdev->dev, "Unable to config gpio\n");
1404                 ret = -EBUSY;
1405                 goto err0;
1406         }
1407
1408         /* Setup clocks */
1409         sdd->clk = devm_clk_get(&pdev->dev, "spi");
1410         if (IS_ERR(sdd->clk)) {
1411                 dev_err(&pdev->dev, "Unable to acquire clock 'spi'\n");
1412                 ret = PTR_ERR(sdd->clk);
1413                 goto err0;
1414         }
1415
1416         if (clk_prepare_enable(sdd->clk)) {
1417                 dev_err(&pdev->dev, "Couldn't enable clock 'spi'\n");
1418                 ret = -EBUSY;
1419                 goto err0;
1420         }
1421
1422         sprintf(clk_name, "spi_busclk%d", sci->src_clk_nr);
1423         sdd->src_clk = devm_clk_get(&pdev->dev, clk_name);
1424         if (IS_ERR(sdd->src_clk)) {
1425                 dev_err(&pdev->dev,
1426                         "Unable to acquire clock '%s'\n", clk_name);
1427                 ret = PTR_ERR(sdd->src_clk);
1428                 goto err2;
1429         }
1430
1431         if (clk_prepare_enable(sdd->src_clk)) {
1432                 dev_err(&pdev->dev, "Couldn't enable clock '%s'\n", clk_name);
1433                 ret = -EBUSY;
1434                 goto err2;
1435         }
1436
1437         /* Setup Deufult Mode */
1438         s3c64xx_spi_hwinit(sdd, sdd->port_id);
1439
1440         spin_lock_init(&sdd->lock);
1441         init_completion(&sdd->xfer_completion);
1442         INIT_LIST_HEAD(&sdd->queue);
1443
1444         ret = devm_request_irq(&pdev->dev, irq, s3c64xx_spi_irq, 0,
1445                                 "spi-s3c64xx", sdd);
1446         if (ret != 0) {
1447                 dev_err(&pdev->dev, "Failed to request IRQ %d: %d\n",
1448                         irq, ret);
1449                 goto err3;
1450         }
1451
1452         writel(S3C64XX_SPI_INT_RX_OVERRUN_EN | S3C64XX_SPI_INT_RX_UNDERRUN_EN |
1453                S3C64XX_SPI_INT_TX_OVERRUN_EN | S3C64XX_SPI_INT_TX_UNDERRUN_EN,
1454                sdd->regs + S3C64XX_SPI_INT_EN);
1455
1456         if (spi_register_master(master)) {
1457                 dev_err(&pdev->dev, "cannot register SPI master\n");
1458                 ret = -EBUSY;
1459                 goto err3;
1460         }
1461
1462         dev_dbg(&pdev->dev, "Samsung SoC SPI Driver loaded for Bus SPI-%d with %d Slaves attached\n",
1463                                         sdd->port_id, master->num_chipselect);
1464         dev_dbg(&pdev->dev, "\tIOmem=[0x%x-0x%x]\tDMA=[Rx-%d, Tx-%d]\n",
1465                                         mem_res->end, mem_res->start,
1466                                         sdd->rx_dma.dmach, sdd->tx_dma.dmach);
1467
1468         pm_runtime_enable(&pdev->dev);
1469
1470         return 0;
1471
1472 err3:
1473         clk_disable_unprepare(sdd->src_clk);
1474 err2:
1475         clk_disable_unprepare(sdd->clk);
1476 err0:
1477         spi_master_put(master);
1478
1479         return ret;
1480 }
1481
1482 static int s3c64xx_spi_remove(struct platform_device *pdev)
1483 {
1484         struct spi_master *master = spi_master_get(platform_get_drvdata(pdev));
1485         struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
1486
1487         pm_runtime_disable(&pdev->dev);
1488
1489         spi_unregister_master(master);
1490
1491         writel(0, sdd->regs + S3C64XX_SPI_INT_EN);
1492
1493         clk_disable_unprepare(sdd->src_clk);
1494
1495         clk_disable_unprepare(sdd->clk);
1496
1497         spi_master_put(master);
1498
1499         return 0;
1500 }
1501
1502 #ifdef CONFIG_PM_SLEEP
1503 static int s3c64xx_spi_suspend(struct device *dev)
1504 {
1505         struct spi_master *master = dev_get_drvdata(dev);
1506         struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
1507
1508         spi_master_suspend(master);
1509
1510         /* Disable the clock */
1511         clk_disable_unprepare(sdd->src_clk);
1512         clk_disable_unprepare(sdd->clk);
1513
1514         sdd->cur_speed = 0; /* Output Clock is stopped */
1515
1516         return 0;
1517 }
1518
1519 static int s3c64xx_spi_resume(struct device *dev)
1520 {
1521         struct spi_master *master = dev_get_drvdata(dev);
1522         struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
1523         struct s3c64xx_spi_info *sci = sdd->cntrlr_info;
1524
1525         if (sci->cfg_gpio)
1526                 sci->cfg_gpio();
1527
1528         /* Enable the clock */
1529         clk_prepare_enable(sdd->src_clk);
1530         clk_prepare_enable(sdd->clk);
1531
1532         s3c64xx_spi_hwinit(sdd, sdd->port_id);
1533
1534         spi_master_resume(master);
1535
1536         return 0;
1537 }
1538 #endif /* CONFIG_PM_SLEEP */
1539
1540 #ifdef CONFIG_PM_RUNTIME
1541 static int s3c64xx_spi_runtime_suspend(struct device *dev)
1542 {
1543         struct spi_master *master = dev_get_drvdata(dev);
1544         struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
1545
1546         clk_disable_unprepare(sdd->clk);
1547         clk_disable_unprepare(sdd->src_clk);
1548
1549         return 0;
1550 }
1551
1552 static int s3c64xx_spi_runtime_resume(struct device *dev)
1553 {
1554         struct spi_master *master = dev_get_drvdata(dev);
1555         struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
1556
1557         clk_prepare_enable(sdd->src_clk);
1558         clk_prepare_enable(sdd->clk);
1559
1560         return 0;
1561 }
1562 #endif /* CONFIG_PM_RUNTIME */
1563
1564 static const struct dev_pm_ops s3c64xx_spi_pm = {
1565         SET_SYSTEM_SLEEP_PM_OPS(s3c64xx_spi_suspend, s3c64xx_spi_resume)
1566         SET_RUNTIME_PM_OPS(s3c64xx_spi_runtime_suspend,
1567                            s3c64xx_spi_runtime_resume, NULL)
1568 };
1569
1570 static struct s3c64xx_spi_port_config s3c2443_spi_port_config = {
1571         .fifo_lvl_mask  = { 0x7f },
1572         .rx_lvl_offset  = 13,
1573         .tx_st_done     = 21,
1574         .high_speed     = true,
1575 };
1576
1577 static struct s3c64xx_spi_port_config s3c6410_spi_port_config = {
1578         .fifo_lvl_mask  = { 0x7f, 0x7F },
1579         .rx_lvl_offset  = 13,
1580         .tx_st_done     = 21,
1581 };
1582
1583 static struct s3c64xx_spi_port_config s5p64x0_spi_port_config = {
1584         .fifo_lvl_mask  = { 0x1ff, 0x7F },
1585         .rx_lvl_offset  = 15,
1586         .tx_st_done     = 25,
1587 };
1588
1589 static struct s3c64xx_spi_port_config s5pc100_spi_port_config = {
1590         .fifo_lvl_mask  = { 0x7f, 0x7F },
1591         .rx_lvl_offset  = 13,
1592         .tx_st_done     = 21,
1593         .high_speed     = true,
1594 };
1595
1596 static struct s3c64xx_spi_port_config s5pv210_spi_port_config = {
1597         .fifo_lvl_mask  = { 0x1ff, 0x7F },
1598         .rx_lvl_offset  = 15,
1599         .tx_st_done     = 25,
1600         .high_speed     = true,
1601 };
1602
1603 static struct s3c64xx_spi_port_config exynos4_spi_port_config = {
1604         .fifo_lvl_mask  = { 0x1ff, 0x7F, 0x7F },
1605         .rx_lvl_offset  = 15,
1606         .tx_st_done     = 25,
1607         .high_speed     = true,
1608         .clk_from_cmu   = true,
1609 };
1610
1611 static struct s3c64xx_spi_port_config exynos5440_spi_port_config = {
1612         .fifo_lvl_mask  = { 0x1ff },
1613         .rx_lvl_offset  = 15,
1614         .tx_st_done     = 25,
1615         .high_speed     = true,
1616         .clk_from_cmu   = true,
1617         .quirks         = S3C64XX_SPI_QUIRK_POLL,
1618 };
1619
1620 static struct platform_device_id s3c64xx_spi_driver_ids[] = {
1621         {
1622                 .name           = "s3c2443-spi",
1623                 .driver_data    = (kernel_ulong_t)&s3c2443_spi_port_config,
1624         }, {
1625                 .name           = "s3c6410-spi",
1626                 .driver_data    = (kernel_ulong_t)&s3c6410_spi_port_config,
1627         }, {
1628                 .name           = "s5p64x0-spi",
1629                 .driver_data    = (kernel_ulong_t)&s5p64x0_spi_port_config,
1630         }, {
1631                 .name           = "s5pc100-spi",
1632                 .driver_data    = (kernel_ulong_t)&s5pc100_spi_port_config,
1633         }, {
1634                 .name           = "s5pv210-spi",
1635                 .driver_data    = (kernel_ulong_t)&s5pv210_spi_port_config,
1636         }, {
1637                 .name           = "exynos4210-spi",
1638                 .driver_data    = (kernel_ulong_t)&exynos4_spi_port_config,
1639         },
1640         { },
1641 };
1642
1643 static const struct of_device_id s3c64xx_spi_dt_match[] = {
1644         { .compatible = "samsung,exynos4210-spi",
1645                         .data = (void *)&exynos4_spi_port_config,
1646         },
1647         { .compatible = "samsung,exynos5440-spi",
1648                         .data = (void *)&exynos5440_spi_port_config,
1649         },
1650         { },
1651 };
1652 MODULE_DEVICE_TABLE(of, s3c64xx_spi_dt_match);
1653
1654 static struct platform_driver s3c64xx_spi_driver = {
1655         .driver = {
1656                 .name   = "s3c64xx-spi",
1657                 .owner = THIS_MODULE,
1658                 .pm = &s3c64xx_spi_pm,
1659                 .of_match_table = of_match_ptr(s3c64xx_spi_dt_match),
1660         },
1661         .remove = s3c64xx_spi_remove,
1662         .id_table = s3c64xx_spi_driver_ids,
1663 };
1664 MODULE_ALIAS("platform:s3c64xx-spi");
1665
1666 static int __init s3c64xx_spi_init(void)
1667 {
1668         return platform_driver_probe(&s3c64xx_spi_driver, s3c64xx_spi_probe);
1669 }
1670 subsys_initcall(s3c64xx_spi_init);
1671
1672 static void __exit s3c64xx_spi_exit(void)
1673 {
1674         platform_driver_unregister(&s3c64xx_spi_driver);
1675 }
1676 module_exit(s3c64xx_spi_exit);
1677
1678 MODULE_AUTHOR("Jaswinder Singh <jassi.brar@samsung.com>");
1679 MODULE_DESCRIPTION("S3C64XX SPI Controller Driver");
1680 MODULE_LICENSE("GPL");