drivers/spi/spi-sun6i.c

   1 /*
   2  * Copyright (C) 2012 - 2014 Allwinner Tech
   3  * Pan Nan <pannan@allwinnertech.com>
   4  *
   5  * Copyright (C) 2014 Maxime Ripard
   6  * Maxime Ripard <maxime.ripard@free-electrons.com>
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  */
  13
  14 #include <linux/clk.h>
  15 #include <linux/delay.h>
  16 #include <linux/device.h>
  17 #include <linux/interrupt.h>
  18 #include <linux/io.h>
  19 #include <linux/module.h>
  20 #include <linux/platform_device.h>
  21 #include <linux/pm_runtime.h>
  22 #include <linux/reset.h>
  23
  24 #include <linux/spi/spi.h>
  25
  26 #define SUN6I_FIFO_DEPTH                128
  27
  28 #define SUN6I_GBL_CTL_REG               0x04
  29 #define SUN6I_GBL_CTL_BUS_ENABLE                BIT(0)
  30 #define SUN6I_GBL_CTL_MASTER                    BIT(1)
  31 #define SUN6I_GBL_CTL_TP                        BIT(7)
  32 #define SUN6I_GBL_CTL_RST                       BIT(31)
  33
  34 #define SUN6I_TFR_CTL_REG               0x08
  35 #define SUN6I_TFR_CTL_CPHA                      BIT(0)
  36 #define SUN6I_TFR_CTL_CPOL                      BIT(1)
  37 #define SUN6I_TFR_CTL_SPOL                      BIT(2)
  38 #define SUN6I_TFR_CTL_CS_MASK                   0x30
  39 #define SUN6I_TFR_CTL_CS(cs)                    (((cs) << 4) & SUN6I_TFR_CTL_CS_MASK)
  40 #define SUN6I_TFR_CTL_CS_MANUAL                 BIT(6)
  41 #define SUN6I_TFR_CTL_CS_LEVEL                  BIT(7)
  42 #define SUN6I_TFR_CTL_DHB                       BIT(8)
  43 #define SUN6I_TFR_CTL_FBS                       BIT(12)
  44 #define SUN6I_TFR_CTL_XCH                       BIT(31)
  45
  46 #define SUN6I_INT_CTL_REG               0x10
  47 #define SUN6I_INT_CTL_RF_OVF                    BIT(8)
  48 #define SUN6I_INT_CTL_TC                        BIT(12)
  49
  50 #define SUN6I_INT_STA_REG               0x14
  51
  52 #define SUN6I_FIFO_CTL_REG              0x18
  53 #define SUN6I_FIFO_CTL_RF_RST                   BIT(15)
  54 #define SUN6I_FIFO_CTL_TF_RST                   BIT(31)
  55
  56 #define SUN6I_FIFO_STA_REG              0x1c
  57 #define SUN6I_FIFO_STA_RF_CNT_MASK              0x7f
  58 #define SUN6I_FIFO_STA_RF_CNT_BITS              0
  59 #define SUN6I_FIFO_STA_TF_CNT_MASK              0x7f
  60 #define SUN6I_FIFO_STA_TF_CNT_BITS              16
  61
  62 #define SUN6I_CLK_CTL_REG               0x24
  63 #define SUN6I_CLK_CTL_CDR2_MASK                 0xff
  64 #define SUN6I_CLK_CTL_CDR2(div)                 (((div) & SUN6I_CLK_CTL_CDR2_MASK) << 0)
  65 #define SUN6I_CLK_CTL_CDR1_MASK                 0xf
  66 #define SUN6I_CLK_CTL_CDR1(div)                 (((div) & SUN6I_CLK_CTL_CDR1_MASK) << 8)
  67 #define SUN6I_CLK_CTL_DRS                       BIT(12)
  68
  69 #define SUN6I_BURST_CNT_REG             0x30
  70 #define SUN6I_BURST_CNT(cnt)                    ((cnt) & 0xffffff)
  71
  72 #define SUN6I_XMIT_CNT_REG              0x34
  73 #define SUN6I_XMIT_CNT(cnt)                     ((cnt) & 0xffffff)
  74
  75 #define SUN6I_BURST_CTL_CNT_REG         0x38
  76 #define SUN6I_BURST_CTL_CNT_STC(cnt)            ((cnt) & 0xffffff)
  77
  78 #define SUN6I_TXDATA_REG                0x200
  79 #define SUN6I_RXDATA_REG                0x300
  80
  81 struct sun6i_spi {
  82         struct spi_master       *master;
  83         void __iomem            *base_addr;
  84         struct clk              *hclk;
  85         struct clk              *mclk;
  86         struct reset_control    *rstc;
  87
  88         struct completion       done;
  89
  90         const u8                *tx_buf;
  91         u8                      *rx_buf;
  92         int                     len;
  93 };
  94
  95 static inline u32 sun6i_spi_read(struct sun6i_spi *sspi, u32 reg)
  96 {
  97         return readl(sspi->base_addr + reg);
  98 }
  99
 100 static inline void sun6i_spi_write(struct sun6i_spi *sspi, u32 reg, u32 value)
 101 {
 102         writel(value, sspi->base_addr + reg);
 103 }
 104
 105 static inline void sun6i_spi_drain_fifo(struct sun6i_spi *sspi, int len)
 106 {
 107         u32 reg, cnt;
 108         u8 byte;
 109
 110         /* See how much data is available */
 111         reg = sun6i_spi_read(sspi, SUN6I_FIFO_STA_REG);
 112         reg &= SUN6I_FIFO_STA_RF_CNT_MASK;
 113         cnt = reg >> SUN6I_FIFO_STA_RF_CNT_BITS;
 114
 115         if (len > cnt)
 116                 len = cnt;
 117
 118         while (len--) {
 119                 byte = readb(sspi->base_addr + SUN6I_RXDATA_REG);
 120                 if (sspi->rx_buf)
 121                         *sspi->rx_buf++ = byte;
 122         }
 123 }
 124
 125 static inline void sun6i_spi_fill_fifo(struct sun6i_spi *sspi, int len)
 126 {
 127         u8 byte;
 128
 129         if (len > sspi->len)
 130                 len = sspi->len;
 131
 132         while (len--) {
 133                 byte = sspi->tx_buf ? *sspi->tx_buf++ : 0;
 134                 writeb(byte, sspi->base_addr + SUN6I_TXDATA_REG);
 135                 sspi->len--;
 136         }
 137 }
 138
 139 static void sun6i_spi_set_cs(struct spi_device *spi, bool enable)
 140 {
 141         struct sun6i_spi *sspi = spi_master_get_devdata(spi->master);
 142         u32 reg;
 143
 144         reg = sun6i_spi_read(sspi, SUN6I_TFR_CTL_REG);
 145         reg &= ~SUN6I_TFR_CTL_CS_MASK;
 146         reg |= SUN6I_TFR_CTL_CS(spi->chip_select);
 147
 148         if (enable)
 149                 reg |= SUN6I_TFR_CTL_CS_LEVEL;
 150         else
 151                 reg &= ~SUN6I_TFR_CTL_CS_LEVEL;
 152
 153         sun6i_spi_write(sspi, SUN6I_TFR_CTL_REG, reg);
 154 }
 155
 156 static size_t sun6i_spi_max_transfer_size(struct spi_device *spi)
 157 {
 158         return SUN6I_FIFO_DEPTH - 1;
 159 }
 160
 161 static int sun6i_spi_transfer_one(struct spi_master *master,
 162                                   struct spi_device *spi,
 163                                   struct spi_transfer *tfr)
 164 {
 165         struct sun6i_spi *sspi = spi_master_get_devdata(master);
 166         unsigned int mclk_rate, div, timeout;
 167         unsigned int tx_len = 0;
 168         int ret = 0;
 169         u32 reg;
 170
 171         /* We don't support transfer larger than the FIFO */
 172         if (tfr->len > SUN6I_FIFO_DEPTH)
 173                 return -EINVAL;
 174
 175         reinit_completion(&sspi->done);
 176         sspi->tx_buf = tfr->tx_buf;
 177         sspi->rx_buf = tfr->rx_buf;
 178         sspi->len = tfr->len;
 179
 180         /* Clear pending interrupts */
 181         sun6i_spi_write(sspi, SUN6I_INT_STA_REG, ~0);
 182
 183         /* Reset FIFO */
 184         sun6i_spi_write(sspi, SUN6I_FIFO_CTL_REG,
 185                         SUN6I_FIFO_CTL_RF_RST | SUN6I_FIFO_CTL_TF_RST);
 186
 187         /*
 188          * Setup the transfer control register: Chip Select,
 189          * polarities, etc.
 190          */
 191         reg = sun6i_spi_read(sspi, SUN6I_TFR_CTL_REG);
 192
 193         if (spi->mode & SPI_CPOL)
 194                 reg |= SUN6I_TFR_CTL_CPOL;
 195         else
 196                 reg &= ~SUN6I_TFR_CTL_CPOL;
 197
 198         if (spi->mode & SPI_CPHA)
 199                 reg |= SUN6I_TFR_CTL_CPHA;
 200         else
 201                 reg &= ~SUN6I_TFR_CTL_CPHA;
 202
 203         if (spi->mode & SPI_LSB_FIRST)
 204                 reg |= SUN6I_TFR_CTL_FBS;
 205         else
 206                 reg &= ~SUN6I_TFR_CTL_FBS;
 207
 208         /*
 209          * If it's a TX only transfer, we don't want to fill the RX
 210          * FIFO with bogus data
 211          */
 212         if (sspi->rx_buf)
 213                 reg &= ~SUN6I_TFR_CTL_DHB;
 214         else
 215                 reg |= SUN6I_TFR_CTL_DHB;
 216
 217         /* We want to control the chip select manually */
 218         reg |= SUN6I_TFR_CTL_CS_MANUAL;
 219
 220         sun6i_spi_write(sspi, SUN6I_TFR_CTL_REG, reg);
 221
 222         /* Ensure that we have a parent clock fast enough */
 223         mclk_rate = clk_get_rate(sspi->mclk);
 224         if (mclk_rate < (2 * tfr->speed_hz)) {
 225                 clk_set_rate(sspi->mclk, 2 * tfr->speed_hz);
 226                 mclk_rate = clk_get_rate(sspi->mclk);
 227         }
 228
 229         /*
 230          * Setup clock divider.
 231          *
 232          * We have two choices there. Either we can use the clock
 233          * divide rate 1, which is calculated thanks to this formula:
 234          * SPI_CLK = MOD_CLK / (2 ^ cdr)
 235          * Or we can use CDR2, which is calculated with the formula:
 236          * SPI_CLK = MOD_CLK / (2 * (cdr + 1))
 237          * Wether we use the former or the latter is set through the
 238          * DRS bit.
 239          *
 240          * First try CDR2, and if we can't reach the expected
 241          * frequency, fall back to CDR1.
 242          */
 243         div = mclk_rate / (2 * tfr->speed_hz);
 244         if (div <= (SUN6I_CLK_CTL_CDR2_MASK + 1)) {
 245                 if (div > 0)
 246                         div--;
 247
 248                 reg = SUN6I_CLK_CTL_CDR2(div) | SUN6I_CLK_CTL_DRS;
 249         } else {
 250                 div = ilog2(mclk_rate) - ilog2(tfr->speed_hz);
 251                 reg = SUN6I_CLK_CTL_CDR1(div);
 252         }
 253
 254         sun6i_spi_write(sspi, SUN6I_CLK_CTL_REG, reg);
 255
 256         /* Setup the transfer now... */
 257         if (sspi->tx_buf)
 258                 tx_len = tfr->len;
 259
 260         /* Setup the counters */
 261         sun6i_spi_write(sspi, SUN6I_BURST_CNT_REG, SUN6I_BURST_CNT(tfr->len));
 262         sun6i_spi_write(sspi, SUN6I_XMIT_CNT_REG, SUN6I_XMIT_CNT(tx_len));
 263         sun6i_spi_write(sspi, SUN6I_BURST_CTL_CNT_REG,
 264                         SUN6I_BURST_CTL_CNT_STC(tx_len));
 265
 266         /* Fill the TX FIFO */
 267         sun6i_spi_fill_fifo(sspi, SUN6I_FIFO_DEPTH);
 268
 269         /* Enable the interrupts */
 270         sun6i_spi_write(sspi, SUN6I_INT_CTL_REG, SUN6I_INT_CTL_TC);
 271
 272         /* Start the transfer */
 273         reg = sun6i_spi_read(sspi, SUN6I_TFR_CTL_REG);
 274         sun6i_spi_write(sspi, SUN6I_TFR_CTL_REG, reg | SUN6I_TFR_CTL_XCH);
 275
 276         timeout = wait_for_completion_timeout(&sspi->done,
 277                                               msecs_to_jiffies(1000));
 278         if (!timeout) {
 279                 ret = -ETIMEDOUT;
 280                 goto out;
 281         }
 282
 283         sun6i_spi_drain_fifo(sspi, SUN6I_FIFO_DEPTH);
 284
 285 out:
 286         sun6i_spi_write(sspi, SUN6I_INT_CTL_REG, 0);
 287
 288         return ret;
 289 }
 290
 291 static irqreturn_t sun6i_spi_handler(int irq, void *dev_id)
 292 {
 293         struct sun6i_spi *sspi = dev_id;
 294         u32 status = sun6i_spi_read(sspi, SUN6I_INT_STA_REG);
 295
 296         /* Transfer complete */
 297         if (status & SUN6I_INT_CTL_TC) {
 298                 sun6i_spi_write(sspi, SUN6I_INT_STA_REG, SUN6I_INT_CTL_TC);
 299                 complete(&sspi->done);
 300                 return IRQ_HANDLED;
 301         }
 302
 303         return IRQ_NONE;
 304 }
 305
 306 static int sun6i_spi_runtime_resume(struct device *dev)
 307 {
 308         struct spi_master *master = dev_get_drvdata(dev);
 309         struct sun6i_spi *sspi = spi_master_get_devdata(master);
 310         int ret;
 311
 312         ret = clk_prepare_enable(sspi->hclk);
 313         if (ret) {
 314                 dev_err(dev, "Couldn't enable AHB clock\n");
 315                 goto out;
 316         }
 317
 318         ret = clk_prepare_enable(sspi->mclk);
 319         if (ret) {
 320                 dev_err(dev, "Couldn't enable module clock\n");
 321                 goto err;
 322         }
 323
 324         ret = reset_control_deassert(sspi->rstc);
 325         if (ret) {
 326                 dev_err(dev, "Couldn't deassert the device from reset\n");
 327                 goto err2;
 328         }
 329
 330         sun6i_spi_write(sspi, SUN6I_GBL_CTL_REG,
 331                         SUN6I_GBL_CTL_BUS_ENABLE | SUN6I_GBL_CTL_MASTER | SUN6I_GBL_CTL_TP);
 332
 333         return 0;
 334
 335 err2:
 336         clk_disable_unprepare(sspi->mclk);
 337 err:
 338         clk_disable_unprepare(sspi->hclk);
 339 out:
 340         return ret;
 341 }
 342
 343 static int sun6i_spi_runtime_suspend(struct device *dev)
 344 {
 345         struct spi_master *master = dev_get_drvdata(dev);
 346         struct sun6i_spi *sspi = spi_master_get_devdata(master);
 347
 348         reset_control_assert(sspi->rstc);
 349         clk_disable_unprepare(sspi->mclk);
 350         clk_disable_unprepare(sspi->hclk);
 351
 352         return 0;
 353 }
 354
 355 static int sun6i_spi_probe(struct platform_device *pdev)
 356 {
 357         struct spi_master *master;
 358         struct sun6i_spi *sspi;
 359         struct resource *res;
 360         int ret = 0, irq;
 361
 362         master = spi_alloc_master(&pdev->dev, sizeof(struct sun6i_spi));
 363         if (!master) {
 364                 dev_err(&pdev->dev, "Unable to allocate SPI Master\n");
 365                 return -ENOMEM;
 366         }
 367
 368         platform_set_drvdata(pdev, master);
 369         sspi = spi_master_get_devdata(master);
 370
 371         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 372         sspi->base_addr = devm_ioremap_resource(&pdev->dev, res);
 373         if (IS_ERR(sspi->base_addr)) {
 374                 ret = PTR_ERR(sspi->base_addr);
 375                 goto err_free_master;
 376         }
 377
 378         irq = platform_get_irq(pdev, 0);
 379         if (irq < 0) {
 380                 dev_err(&pdev->dev, "No spi IRQ specified\n");
 381                 ret = -ENXIO;
 382                 goto err_free_master;
 383         }
 384
 385         ret = devm_request_irq(&pdev->dev, irq, sun6i_spi_handler,
 386                                0, "sun6i-spi", sspi);
 387         if (ret) {
 388                 dev_err(&pdev->dev, "Cannot request IRQ\n");
 389                 goto err_free_master;
 390         }
 391
 392         sspi->master = master;
 393         master->set_cs = sun6i_spi_set_cs;
 394         master->transfer_one = sun6i_spi_transfer_one;
 395         master->num_chipselect = 4;
 396         master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LSB_FIRST;
 397         master->bits_per_word_mask = SPI_BPW_MASK(8);
 398         master->dev.of_node = pdev->dev.of_node;
 399         master->auto_runtime_pm = true;
 400         master->max_transfer_size = sun6i_spi_max_transfer_size;
 401
 402         sspi->hclk = devm_clk_get(&pdev->dev, "ahb");
 403         if (IS_ERR(sspi->hclk)) {
 404                 dev_err(&pdev->dev, "Unable to acquire AHB clock\n");
 405                 ret = PTR_ERR(sspi->hclk);
 406                 goto err_free_master;
 407         }
 408
 409         sspi->mclk = devm_clk_get(&pdev->dev, "mod");
 410         if (IS_ERR(sspi->mclk)) {
 411                 dev_err(&pdev->dev, "Unable to acquire module clock\n");
 412                 ret = PTR_ERR(sspi->mclk);
 413                 goto err_free_master;
 414         }
 415
 416         init_completion(&sspi->done);
 417
 418         sspi->rstc = devm_reset_control_get(&pdev->dev, NULL);
 419         if (IS_ERR(sspi->rstc)) {
 420                 dev_err(&pdev->dev, "Couldn't get reset controller\n");
 421                 ret = PTR_ERR(sspi->rstc);
 422                 goto err_free_master;
 423         }
 424
 425         /*
 426          * This wake-up/shutdown pattern is to be able to have the
 427          * device woken up, even if runtime_pm is disabled
 428          */
 429         ret = sun6i_spi_runtime_resume(&pdev->dev);
 430         if (ret) {
 431                 dev_err(&pdev->dev, "Couldn't resume the device\n");
 432                 goto err_free_master;
 433         }
 434
 435         pm_runtime_set_active(&pdev->dev);
 436         pm_runtime_enable(&pdev->dev);
 437         pm_runtime_idle(&pdev->dev);
 438
 439         ret = devm_spi_register_master(&pdev->dev, master);
 440         if (ret) {
 441                 dev_err(&pdev->dev, "cannot register SPI master\n");
 442                 goto err_pm_disable;
 443         }
 444
 445         return 0;
 446
 447 err_pm_disable:
 448         pm_runtime_disable(&pdev->dev);
 449         sun6i_spi_runtime_suspend(&pdev->dev);
 450 err_free_master:
 451         spi_master_put(master);
 452         return ret;
 453 }
 454
 455 static int sun6i_spi_remove(struct platform_device *pdev)
 456 {
 457         pm_runtime_disable(&pdev->dev);
 458
 459         return 0;
 460 }
 461
 462 static const struct of_device_id sun6i_spi_match[] = {
 463         { .compatible = "allwinner,sun6i-a31-spi", },
 464         {}
 465 };
 466 MODULE_DEVICE_TABLE(of, sun6i_spi_match);
 467
 468 static const struct dev_pm_ops sun6i_spi_pm_ops = {
 469         .runtime_resume         = sun6i_spi_runtime_resume,
 470         .runtime_suspend        = sun6i_spi_runtime_suspend,
 471 };
 472
 473 static struct platform_driver sun6i_spi_driver = {
 474         .probe  = sun6i_spi_probe,
 475         .remove = sun6i_spi_remove,
 476         .driver = {
 477                 .name           = "sun6i-spi",
 478                 .of_match_table = sun6i_spi_match,
 479                 .pm             = &sun6i_spi_pm_ops,
 480         },
 481 };
 482 module_platform_driver(sun6i_spi_driver);
 483
 484 MODULE_AUTHOR("Pan Nan <pannan@allwinnertech.com>");
 485 MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>");
 486 MODULE_DESCRIPTION("Allwinner A31 SPI controller driver");
 487 MODULE_LICENSE("GPL");