2 * Blackfin On-Chip SPI Driver
4 * Copyright 2004-2007 Analog Devices Inc.
6 * Enter bugs at http://blackfin.uclinux.org/
8 * Licensed under the GPL-2 or later.
11 #include <linux/init.h>
12 #include <linux/module.h>
13 #include <linux/delay.h>
14 #include <linux/device.h>
15 #include <linux/slab.h>
17 #include <linux/ioport.h>
18 #include <linux/irq.h>
19 #include <linux/errno.h>
20 #include <linux/interrupt.h>
21 #include <linux/platform_device.h>
22 #include <linux/dma-mapping.h>
23 #include <linux/spi/spi.h>
24 #include <linux/workqueue.h>
27 #include <asm/portmux.h>
28 #include <asm/bfin5xx_spi.h>
29 #include <asm/cacheflush.h>
31 #define DRV_NAME "bfin-spi"
32 #define DRV_AUTHOR "Bryan Wu, Luke Yang"
33 #define DRV_DESC "Blackfin on-chip SPI Controller Driver"
34 #define DRV_VERSION "1.0"
36 MODULE_AUTHOR(DRV_AUTHOR);
37 MODULE_DESCRIPTION(DRV_DESC);
38 MODULE_LICENSE("GPL");
40 #define START_STATE ((void *)0)
41 #define RUNNING_STATE ((void *)1)
42 #define DONE_STATE ((void *)2)
43 #define ERROR_STATE ((void *)-1)
48 void (*write) (struct master_data *);
49 void (*read) (struct master_data *);
50 void (*duplex) (struct master_data *);
54 /* Driver model hookup */
55 struct platform_device *pdev;
57 /* SPI framework hookup */
58 struct spi_master *master;
60 /* Regs base of SPI controller */
61 void __iomem *regs_base;
63 /* Pin request list */
67 struct bfin5xx_spi_master *master_info;
69 /* Driver message queue */
70 struct workqueue_struct *workqueue;
71 struct work_struct pump_messages;
73 struct list_head queue;
77 /* Message Transfer pump */
78 struct tasklet_struct pump_transfers;
80 /* Current message transfer state info */
81 struct spi_message *cur_msg;
82 struct spi_transfer *cur_transfer;
83 struct slave_data *cur_chip;
108 const struct transfer_ops *ops;
118 u8 width; /* 0 or 1 */
120 u8 bits_per_word; /* 8 or 16 */
121 u16 cs_chg_udelay; /* Some devices require > 255usec delay */
124 u8 pio_interrupt; /* use spi data irq */
125 const struct transfer_ops *ops;
128 #define DEFINE_SPI_REG(reg, off) \
129 static inline u16 read_##reg(struct master_data *drv_data) \
130 { return bfin_read16(drv_data->regs_base + off); } \
131 static inline void write_##reg(struct master_data *drv_data, u16 v) \
132 { bfin_write16(drv_data->regs_base + off, v); }
134 DEFINE_SPI_REG(CTRL, 0x00)
135 DEFINE_SPI_REG(FLAG, 0x04)
136 DEFINE_SPI_REG(STAT, 0x08)
137 DEFINE_SPI_REG(TDBR, 0x0C)
138 DEFINE_SPI_REG(RDBR, 0x10)
139 DEFINE_SPI_REG(BAUD, 0x14)
140 DEFINE_SPI_REG(SHAW, 0x18)
142 static void bfin_spi_enable(struct master_data *drv_data)
146 cr = read_CTRL(drv_data);
147 write_CTRL(drv_data, (cr | BIT_CTL_ENABLE));
150 static void bfin_spi_disable(struct master_data *drv_data)
154 cr = read_CTRL(drv_data);
155 write_CTRL(drv_data, (cr & (~BIT_CTL_ENABLE)));
158 /* Caculate the SPI_BAUD register value based on input HZ */
159 static u16 hz_to_spi_baud(u32 speed_hz)
161 u_long sclk = get_sclk();
162 u16 spi_baud = (sclk / (2 * speed_hz));
164 if ((sclk % (2 * speed_hz)) > 0)
167 if (spi_baud < MIN_SPI_BAUD_VAL)
168 spi_baud = MIN_SPI_BAUD_VAL;
173 static int bfin_spi_flush(struct master_data *drv_data)
175 unsigned long limit = loops_per_jiffy << 1;
177 /* wait for stop and clear stat */
178 while (!(read_STAT(drv_data) & BIT_STAT_SPIF) && --limit)
181 write_STAT(drv_data, BIT_STAT_CLR);
186 /* Chip select operation functions for cs_change flag */
187 static void bfin_spi_cs_active(struct master_data *drv_data, struct slave_data *chip)
189 if (likely(chip->chip_select_num < MAX_CTRL_CS)) {
190 u16 flag = read_FLAG(drv_data);
194 write_FLAG(drv_data, flag);
196 gpio_set_value(chip->cs_gpio, 0);
200 static void bfin_spi_cs_deactive(struct master_data *drv_data, struct slave_data *chip)
202 if (likely(chip->chip_select_num < MAX_CTRL_CS)) {
203 u16 flag = read_FLAG(drv_data);
207 write_FLAG(drv_data, flag);
209 gpio_set_value(chip->cs_gpio, 1);
212 /* Move delay here for consistency */
213 if (chip->cs_chg_udelay)
214 udelay(chip->cs_chg_udelay);
217 /* enable or disable the pin muxed by GPIO and SPI CS to work as SPI CS */
218 static inline void bfin_spi_cs_enable(struct master_data *drv_data, struct slave_data *chip)
220 if (chip->chip_select_num < MAX_CTRL_CS) {
221 u16 flag = read_FLAG(drv_data);
223 flag |= (chip->flag >> 8);
225 write_FLAG(drv_data, flag);
229 static inline void bfin_spi_cs_disable(struct master_data *drv_data, struct slave_data *chip)
231 if (chip->chip_select_num < MAX_CTRL_CS) {
232 u16 flag = read_FLAG(drv_data);
234 flag &= ~(chip->flag >> 8);
236 write_FLAG(drv_data, flag);
240 /* stop controller and re-config current chip*/
241 static void bfin_spi_restore_state(struct master_data *drv_data)
243 struct slave_data *chip = drv_data->cur_chip;
245 /* Clear status and disable clock */
246 write_STAT(drv_data, BIT_STAT_CLR);
247 bfin_spi_disable(drv_data);
248 dev_dbg(&drv_data->pdev->dev, "restoring spi ctl state\n");
252 /* Load the registers */
253 write_CTRL(drv_data, chip->ctl_reg);
254 write_BAUD(drv_data, chip->baud);
256 bfin_spi_enable(drv_data);
257 bfin_spi_cs_active(drv_data, chip);
260 /* used to kick off transfer in rx mode and read unwanted RX data */
261 static inline void bfin_spi_dummy_read(struct master_data *drv_data)
263 (void) read_RDBR(drv_data);
266 static void bfin_spi_u8_writer(struct master_data *drv_data)
268 /* clear RXS (we check for RXS inside the loop) */
269 bfin_spi_dummy_read(drv_data);
271 while (drv_data->tx < drv_data->tx_end) {
272 write_TDBR(drv_data, (*(u8 *) (drv_data->tx++)));
273 /* wait until transfer finished.
274 checking SPIF or TXS may not guarantee transfer completion */
275 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
277 /* discard RX data and clear RXS */
278 bfin_spi_dummy_read(drv_data);
282 static void bfin_spi_u8_reader(struct master_data *drv_data)
284 u16 tx_val = drv_data->cur_chip->idle_tx_val;
286 /* discard old RX data and clear RXS */
287 bfin_spi_dummy_read(drv_data);
289 while (drv_data->rx < drv_data->rx_end) {
290 write_TDBR(drv_data, tx_val);
291 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
293 *(u8 *) (drv_data->rx++) = read_RDBR(drv_data);
297 static void bfin_spi_u8_duplex(struct master_data *drv_data)
299 /* discard old RX data and clear RXS */
300 bfin_spi_dummy_read(drv_data);
302 while (drv_data->rx < drv_data->rx_end) {
303 write_TDBR(drv_data, (*(u8 *) (drv_data->tx++)));
304 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
306 *(u8 *) (drv_data->rx++) = read_RDBR(drv_data);
310 static const struct transfer_ops bfin_transfer_ops_u8 = {
311 .write = bfin_spi_u8_writer,
312 .read = bfin_spi_u8_reader,
313 .duplex = bfin_spi_u8_duplex,
316 static void bfin_spi_u16_writer(struct master_data *drv_data)
318 /* clear RXS (we check for RXS inside the loop) */
319 bfin_spi_dummy_read(drv_data);
321 while (drv_data->tx < drv_data->tx_end) {
322 write_TDBR(drv_data, (*(u16 *) (drv_data->tx)));
324 /* wait until transfer finished.
325 checking SPIF or TXS may not guarantee transfer completion */
326 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
328 /* discard RX data and clear RXS */
329 bfin_spi_dummy_read(drv_data);
333 static void bfin_spi_u16_reader(struct master_data *drv_data)
335 u16 tx_val = drv_data->cur_chip->idle_tx_val;
337 /* discard old RX data and clear RXS */
338 bfin_spi_dummy_read(drv_data);
340 while (drv_data->rx < drv_data->rx_end) {
341 write_TDBR(drv_data, tx_val);
342 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
344 *(u16 *) (drv_data->rx) = read_RDBR(drv_data);
349 static void bfin_spi_u16_duplex(struct master_data *drv_data)
351 /* discard old RX data and clear RXS */
352 bfin_spi_dummy_read(drv_data);
354 while (drv_data->rx < drv_data->rx_end) {
355 write_TDBR(drv_data, (*(u16 *) (drv_data->tx)));
357 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
359 *(u16 *) (drv_data->rx) = read_RDBR(drv_data);
364 static const struct transfer_ops bfin_transfer_ops_u16 = {
365 .write = bfin_spi_u16_writer,
366 .read = bfin_spi_u16_reader,
367 .duplex = bfin_spi_u16_duplex,
370 /* test if ther is more transfer to be done */
371 static void *bfin_spi_next_transfer(struct master_data *drv_data)
373 struct spi_message *msg = drv_data->cur_msg;
374 struct spi_transfer *trans = drv_data->cur_transfer;
376 /* Move to next transfer */
377 if (trans->transfer_list.next != &msg->transfers) {
378 drv_data->cur_transfer =
379 list_entry(trans->transfer_list.next,
380 struct spi_transfer, transfer_list);
381 return RUNNING_STATE;
387 * caller already set message->status;
388 * dma and pio irqs are blocked give finished message back
390 static void bfin_spi_giveback(struct master_data *drv_data)
392 struct slave_data *chip = drv_data->cur_chip;
393 struct spi_transfer *last_transfer;
395 struct spi_message *msg;
397 spin_lock_irqsave(&drv_data->lock, flags);
398 msg = drv_data->cur_msg;
399 drv_data->cur_msg = NULL;
400 drv_data->cur_transfer = NULL;
401 drv_data->cur_chip = NULL;
402 queue_work(drv_data->workqueue, &drv_data->pump_messages);
403 spin_unlock_irqrestore(&drv_data->lock, flags);
405 last_transfer = list_entry(msg->transfers.prev,
406 struct spi_transfer, transfer_list);
410 if (!drv_data->cs_change)
411 bfin_spi_cs_deactive(drv_data, chip);
413 /* Not stop spi in autobuffer mode */
414 if (drv_data->tx_dma != 0xFFFF)
415 bfin_spi_disable(drv_data);
418 msg->complete(msg->context);
421 /* spi data irq handler */
422 static irqreturn_t bfin_spi_pio_irq_handler(int irq, void *dev_id)
424 struct master_data *drv_data = dev_id;
425 struct slave_data *chip = drv_data->cur_chip;
426 struct spi_message *msg = drv_data->cur_msg;
427 int n_bytes = drv_data->n_bytes;
429 /* wait until transfer finished. */
430 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
433 if ((drv_data->tx && drv_data->tx >= drv_data->tx_end) ||
434 (drv_data->rx && drv_data->rx >= (drv_data->rx_end - n_bytes))) {
437 dev_dbg(&drv_data->pdev->dev, "last read\n");
439 *(u16 *) (drv_data->rx) = read_RDBR(drv_data);
440 else if (n_bytes == 1)
441 *(u8 *) (drv_data->rx) = read_RDBR(drv_data);
442 drv_data->rx += n_bytes;
445 msg->actual_length += drv_data->len_in_bytes;
446 if (drv_data->cs_change)
447 bfin_spi_cs_deactive(drv_data, chip);
448 /* Move to next transfer */
449 msg->state = bfin_spi_next_transfer(drv_data);
451 disable_irq(drv_data->spi_irq);
453 /* Schedule transfer tasklet */
454 tasklet_schedule(&drv_data->pump_transfers);
458 if (drv_data->rx && drv_data->tx) {
460 dev_dbg(&drv_data->pdev->dev, "duplex: write_TDBR\n");
461 if (drv_data->n_bytes == 2) {
462 *(u16 *) (drv_data->rx) = read_RDBR(drv_data);
463 write_TDBR(drv_data, (*(u16 *) (drv_data->tx)));
464 } else if (drv_data->n_bytes == 1) {
465 *(u8 *) (drv_data->rx) = read_RDBR(drv_data);
466 write_TDBR(drv_data, (*(u8 *) (drv_data->tx)));
468 } else if (drv_data->rx) {
470 dev_dbg(&drv_data->pdev->dev, "read: write_TDBR\n");
471 if (drv_data->n_bytes == 2)
472 *(u16 *) (drv_data->rx) = read_RDBR(drv_data);
473 else if (drv_data->n_bytes == 1)
474 *(u8 *) (drv_data->rx) = read_RDBR(drv_data);
475 write_TDBR(drv_data, chip->idle_tx_val);
476 } else if (drv_data->tx) {
478 dev_dbg(&drv_data->pdev->dev, "write: write_TDBR\n");
479 bfin_spi_dummy_read(drv_data);
480 if (drv_data->n_bytes == 2)
481 write_TDBR(drv_data, (*(u16 *) (drv_data->tx)));
482 else if (drv_data->n_bytes == 1)
483 write_TDBR(drv_data, (*(u8 *) (drv_data->tx)));
487 drv_data->tx += n_bytes;
489 drv_data->rx += n_bytes;
494 static irqreturn_t bfin_spi_dma_irq_handler(int irq, void *dev_id)
496 struct master_data *drv_data = dev_id;
497 struct slave_data *chip = drv_data->cur_chip;
498 struct spi_message *msg = drv_data->cur_msg;
499 unsigned long timeout;
500 unsigned short dmastat = get_dma_curr_irqstat(drv_data->dma_channel);
501 u16 spistat = read_STAT(drv_data);
503 dev_dbg(&drv_data->pdev->dev,
504 "in dma_irq_handler dmastat:0x%x spistat:0x%x\n",
507 clear_dma_irqstat(drv_data->dma_channel);
510 * wait for the last transaction shifted out. HRM states:
511 * at this point there may still be data in the SPI DMA FIFO waiting
512 * to be transmitted ... software needs to poll TXS in the SPI_STAT
513 * register until it goes low for 2 successive reads
515 if (drv_data->tx != NULL) {
516 while ((read_STAT(drv_data) & BIT_STAT_TXS) ||
517 (read_STAT(drv_data) & BIT_STAT_TXS))
521 dev_dbg(&drv_data->pdev->dev,
522 "in dma_irq_handler dmastat:0x%x spistat:0x%x\n",
523 dmastat, read_STAT(drv_data));
525 timeout = jiffies + HZ;
526 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
527 if (!time_before(jiffies, timeout)) {
528 dev_warn(&drv_data->pdev->dev, "timeout waiting for SPIF");
533 if ((dmastat & DMA_ERR) && (spistat & BIT_STAT_RBSY)) {
534 msg->state = ERROR_STATE;
535 dev_err(&drv_data->pdev->dev, "dma receive: fifo/buffer overflow\n");
537 msg->actual_length += drv_data->len_in_bytes;
539 if (drv_data->cs_change)
540 bfin_spi_cs_deactive(drv_data, chip);
542 /* Move to next transfer */
543 msg->state = bfin_spi_next_transfer(drv_data);
546 /* Schedule transfer tasklet */
547 tasklet_schedule(&drv_data->pump_transfers);
549 /* free the irq handler before next transfer */
550 dev_dbg(&drv_data->pdev->dev,
551 "disable dma channel irq%d\n",
552 drv_data->dma_channel);
553 dma_disable_irq(drv_data->dma_channel);
558 static void bfin_spi_pump_transfers(unsigned long data)
560 struct master_data *drv_data = (struct master_data *)data;
561 struct spi_message *message = NULL;
562 struct spi_transfer *transfer = NULL;
563 struct spi_transfer *previous = NULL;
564 struct slave_data *chip = NULL;
566 u16 cr, dma_width, dma_config;
567 u32 tranf_success = 1;
570 /* Get current state information */
571 message = drv_data->cur_msg;
572 transfer = drv_data->cur_transfer;
573 chip = drv_data->cur_chip;
576 * if msg is error or done, report it back using complete() callback
579 /* Handle for abort */
580 if (message->state == ERROR_STATE) {
581 dev_dbg(&drv_data->pdev->dev, "transfer: we've hit an error\n");
582 message->status = -EIO;
583 bfin_spi_giveback(drv_data);
587 /* Handle end of message */
588 if (message->state == DONE_STATE) {
589 dev_dbg(&drv_data->pdev->dev, "transfer: all done!\n");
591 bfin_spi_giveback(drv_data);
595 /* Delay if requested at end of transfer */
596 if (message->state == RUNNING_STATE) {
597 dev_dbg(&drv_data->pdev->dev, "transfer: still running ...\n");
598 previous = list_entry(transfer->transfer_list.prev,
599 struct spi_transfer, transfer_list);
600 if (previous->delay_usecs)
601 udelay(previous->delay_usecs);
604 /* Flush any existing transfers that may be sitting in the hardware */
605 if (bfin_spi_flush(drv_data) == 0) {
606 dev_err(&drv_data->pdev->dev, "pump_transfers: flush failed\n");
607 message->status = -EIO;
608 bfin_spi_giveback(drv_data);
612 if (transfer->len == 0) {
613 /* Move to next transfer of this msg */
614 message->state = bfin_spi_next_transfer(drv_data);
615 /* Schedule next transfer tasklet */
616 tasklet_schedule(&drv_data->pump_transfers);
619 if (transfer->tx_buf != NULL) {
620 drv_data->tx = (void *)transfer->tx_buf;
621 drv_data->tx_end = drv_data->tx + transfer->len;
622 dev_dbg(&drv_data->pdev->dev, "tx_buf is %p, tx_end is %p\n",
623 transfer->tx_buf, drv_data->tx_end);
628 if (transfer->rx_buf != NULL) {
629 full_duplex = transfer->tx_buf != NULL;
630 drv_data->rx = transfer->rx_buf;
631 drv_data->rx_end = drv_data->rx + transfer->len;
632 dev_dbg(&drv_data->pdev->dev, "rx_buf is %p, rx_end is %p\n",
633 transfer->rx_buf, drv_data->rx_end);
638 drv_data->rx_dma = transfer->rx_dma;
639 drv_data->tx_dma = transfer->tx_dma;
640 drv_data->len_in_bytes = transfer->len;
641 drv_data->cs_change = transfer->cs_change;
643 /* Bits per word setup */
644 switch (transfer->bits_per_word) {
646 drv_data->n_bytes = 1;
647 width = CFG_SPI_WORDSIZE8;
648 drv_data->ops = &bfin_transfer_ops_u8;
652 drv_data->n_bytes = 2;
653 width = CFG_SPI_WORDSIZE16;
654 drv_data->ops = &bfin_transfer_ops_u16;
658 /* No change, the same as default setting */
659 transfer->bits_per_word = chip->bits_per_word;
660 drv_data->n_bytes = chip->n_bytes;
662 drv_data->ops = chip->ops;
665 cr = (read_CTRL(drv_data) & (~BIT_CTL_TIMOD));
667 write_CTRL(drv_data, cr);
669 if (width == CFG_SPI_WORDSIZE16) {
670 drv_data->len = (transfer->len) >> 1;
672 drv_data->len = transfer->len;
674 dev_dbg(&drv_data->pdev->dev,
675 "transfer: drv_data->ops is %p, chip->ops is %p, u8_ops is %p\n",
676 drv_data->ops, chip->ops, &bfin_transfer_ops_u8);
678 message->state = RUNNING_STATE;
681 /* Speed setup (surely valid because already checked) */
682 if (transfer->speed_hz)
683 write_BAUD(drv_data, hz_to_spi_baud(transfer->speed_hz));
685 write_BAUD(drv_data, chip->baud);
687 write_STAT(drv_data, BIT_STAT_CLR);
688 cr = (read_CTRL(drv_data) & (~BIT_CTL_TIMOD));
689 if (drv_data->cs_change)
690 bfin_spi_cs_active(drv_data, chip);
692 dev_dbg(&drv_data->pdev->dev,
693 "now pumping a transfer: width is %d, len is %d\n",
694 width, transfer->len);
697 * Try to map dma buffer and do a dma transfer. If successful use,
698 * different way to r/w according to the enable_dma settings and if
699 * we are not doing a full duplex transfer (since the hardware does
700 * not support full duplex DMA transfers).
702 if (!full_duplex && drv_data->cur_chip->enable_dma
703 && drv_data->len > 6) {
705 unsigned long dma_start_addr, flags;
707 disable_dma(drv_data->dma_channel);
708 clear_dma_irqstat(drv_data->dma_channel);
710 /* config dma channel */
711 dev_dbg(&drv_data->pdev->dev, "doing dma transfer\n");
712 set_dma_x_count(drv_data->dma_channel, drv_data->len);
713 if (width == CFG_SPI_WORDSIZE16) {
714 set_dma_x_modify(drv_data->dma_channel, 2);
715 dma_width = WDSIZE_16;
717 set_dma_x_modify(drv_data->dma_channel, 1);
718 dma_width = WDSIZE_8;
721 /* poll for SPI completion before start */
722 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
725 /* dirty hack for autobuffer DMA mode */
726 if (drv_data->tx_dma == 0xFFFF) {
727 dev_dbg(&drv_data->pdev->dev,
728 "doing autobuffer DMA out.\n");
730 /* no irq in autobuffer mode */
732 (DMAFLOW_AUTO | RESTART | dma_width | DI_EN);
733 set_dma_config(drv_data->dma_channel, dma_config);
734 set_dma_start_addr(drv_data->dma_channel,
735 (unsigned long)drv_data->tx);
736 enable_dma(drv_data->dma_channel);
738 /* start SPI transfer */
739 write_CTRL(drv_data, cr | BIT_CTL_TIMOD_DMA_TX);
741 /* just return here, there can only be one transfer
745 bfin_spi_giveback(drv_data);
749 /* In dma mode, rx or tx must be NULL in one transfer */
750 dma_config = (RESTART | dma_width | DI_EN);
751 if (drv_data->rx != NULL) {
752 /* set transfer mode, and enable SPI */
753 dev_dbg(&drv_data->pdev->dev, "doing DMA in to %p (size %zx)\n",
754 drv_data->rx, drv_data->len_in_bytes);
756 /* invalidate caches, if needed */
757 if (bfin_addr_dcacheable((unsigned long) drv_data->rx))
758 invalidate_dcache_range((unsigned long) drv_data->rx,
759 (unsigned long) (drv_data->rx +
760 drv_data->len_in_bytes));
763 dma_start_addr = (unsigned long)drv_data->rx;
764 cr |= BIT_CTL_TIMOD_DMA_RX | BIT_CTL_SENDOPT;
766 } else if (drv_data->tx != NULL) {
767 dev_dbg(&drv_data->pdev->dev, "doing DMA out.\n");
769 /* flush caches, if needed */
770 if (bfin_addr_dcacheable((unsigned long) drv_data->tx))
771 flush_dcache_range((unsigned long) drv_data->tx,
772 (unsigned long) (drv_data->tx +
773 drv_data->len_in_bytes));
775 dma_start_addr = (unsigned long)drv_data->tx;
776 cr |= BIT_CTL_TIMOD_DMA_TX;
781 /* oh man, here there be monsters ... and i dont mean the
782 * fluffy cute ones from pixar, i mean the kind that'll eat
783 * your data, kick your dog, and love it all. do *not* try
784 * and change these lines unless you (1) heavily test DMA
785 * with SPI flashes on a loaded system (e.g. ping floods),
786 * (2) know just how broken the DMA engine interaction with
787 * the SPI peripheral is, and (3) have someone else to blame
788 * when you screw it all up anyways.
790 set_dma_start_addr(drv_data->dma_channel, dma_start_addr);
791 set_dma_config(drv_data->dma_channel, dma_config);
792 local_irq_save(flags);
794 write_CTRL(drv_data, cr);
795 enable_dma(drv_data->dma_channel);
796 dma_enable_irq(drv_data->dma_channel);
797 local_irq_restore(flags);
802 if (chip->pio_interrupt) {
803 /* use write mode. spi irq should have been disabled */
804 cr = (read_CTRL(drv_data) & (~BIT_CTL_TIMOD));
805 write_CTRL(drv_data, (cr | CFG_SPI_WRITE));
807 /* discard old RX data and clear RXS */
808 bfin_spi_dummy_read(drv_data);
811 if (drv_data->tx == NULL)
812 write_TDBR(drv_data, chip->idle_tx_val);
814 if (transfer->bits_per_word == 8)
815 write_TDBR(drv_data, (*(u8 *) (drv_data->tx)));
816 else if (transfer->bits_per_word == 16)
817 write_TDBR(drv_data, (*(u16 *) (drv_data->tx)));
818 drv_data->tx += drv_data->n_bytes;
821 /* once TDBR is empty, interrupt is triggered */
822 enable_irq(drv_data->spi_irq);
827 dev_dbg(&drv_data->pdev->dev, "doing IO transfer\n");
829 /* we always use SPI_WRITE mode. SPI_READ mode
830 seems to have problems with setting up the
831 output value in TDBR prior to the transfer. */
832 write_CTRL(drv_data, (cr | CFG_SPI_WRITE));
835 /* full duplex mode */
836 BUG_ON((drv_data->tx_end - drv_data->tx) !=
837 (drv_data->rx_end - drv_data->rx));
838 dev_dbg(&drv_data->pdev->dev,
839 "IO duplex: cr is 0x%x\n", cr);
841 drv_data->ops->duplex(drv_data);
843 if (drv_data->tx != drv_data->tx_end)
845 } else if (drv_data->tx != NULL) {
846 /* write only half duplex */
847 dev_dbg(&drv_data->pdev->dev,
848 "IO write: cr is 0x%x\n", cr);
850 drv_data->ops->write(drv_data);
852 if (drv_data->tx != drv_data->tx_end)
854 } else if (drv_data->rx != NULL) {
855 /* read only half duplex */
856 dev_dbg(&drv_data->pdev->dev,
857 "IO read: cr is 0x%x\n", cr);
859 drv_data->ops->read(drv_data);
860 if (drv_data->rx != drv_data->rx_end)
864 if (!tranf_success) {
865 dev_dbg(&drv_data->pdev->dev,
866 "IO write error!\n");
867 message->state = ERROR_STATE;
869 /* Update total byte transfered */
870 message->actual_length += drv_data->len_in_bytes;
871 /* Move to next transfer of this msg */
872 message->state = bfin_spi_next_transfer(drv_data);
873 if (drv_data->cs_change)
874 bfin_spi_cs_deactive(drv_data, chip);
877 /* Schedule next transfer tasklet */
878 tasklet_schedule(&drv_data->pump_transfers);
881 /* pop a msg from queue and kick off real transfer */
882 static void bfin_spi_pump_messages(struct work_struct *work)
884 struct master_data *drv_data;
887 drv_data = container_of(work, struct master_data, pump_messages);
889 /* Lock queue and check for queue work */
890 spin_lock_irqsave(&drv_data->lock, flags);
891 if (list_empty(&drv_data->queue) || !drv_data->running) {
892 /* pumper kicked off but no work to do */
894 spin_unlock_irqrestore(&drv_data->lock, flags);
898 /* Make sure we are not already running a message */
899 if (drv_data->cur_msg) {
900 spin_unlock_irqrestore(&drv_data->lock, flags);
904 /* Extract head of queue */
905 drv_data->cur_msg = list_entry(drv_data->queue.next,
906 struct spi_message, queue);
908 /* Setup the SSP using the per chip configuration */
909 drv_data->cur_chip = spi_get_ctldata(drv_data->cur_msg->spi);
910 bfin_spi_restore_state(drv_data);
912 list_del_init(&drv_data->cur_msg->queue);
914 /* Initial message state */
915 drv_data->cur_msg->state = START_STATE;
916 drv_data->cur_transfer = list_entry(drv_data->cur_msg->transfers.next,
917 struct spi_transfer, transfer_list);
919 dev_dbg(&drv_data->pdev->dev, "got a message to pump, "
920 "state is set to: baud %d, flag 0x%x, ctl 0x%x\n",
921 drv_data->cur_chip->baud, drv_data->cur_chip->flag,
922 drv_data->cur_chip->ctl_reg);
924 dev_dbg(&drv_data->pdev->dev,
925 "the first transfer len is %d\n",
926 drv_data->cur_transfer->len);
928 /* Mark as busy and launch transfers */
929 tasklet_schedule(&drv_data->pump_transfers);
932 spin_unlock_irqrestore(&drv_data->lock, flags);
936 * got a msg to transfer, queue it in drv_data->queue.
937 * And kick off message pumper
939 static int bfin_spi_transfer(struct spi_device *spi, struct spi_message *msg)
941 struct master_data *drv_data = spi_master_get_devdata(spi->master);
944 spin_lock_irqsave(&drv_data->lock, flags);
946 if (!drv_data->running) {
947 spin_unlock_irqrestore(&drv_data->lock, flags);
951 msg->actual_length = 0;
952 msg->status = -EINPROGRESS;
953 msg->state = START_STATE;
955 dev_dbg(&spi->dev, "adding an msg in transfer() \n");
956 list_add_tail(&msg->queue, &drv_data->queue);
958 if (drv_data->running && !drv_data->busy)
959 queue_work(drv_data->workqueue, &drv_data->pump_messages);
961 spin_unlock_irqrestore(&drv_data->lock, flags);
966 #define MAX_SPI_SSEL 7
968 static u16 ssel[][MAX_SPI_SSEL] = {
969 {P_SPI0_SSEL1, P_SPI0_SSEL2, P_SPI0_SSEL3,
970 P_SPI0_SSEL4, P_SPI0_SSEL5,
971 P_SPI0_SSEL6, P_SPI0_SSEL7},
973 {P_SPI1_SSEL1, P_SPI1_SSEL2, P_SPI1_SSEL3,
974 P_SPI1_SSEL4, P_SPI1_SSEL5,
975 P_SPI1_SSEL6, P_SPI1_SSEL7},
977 {P_SPI2_SSEL1, P_SPI2_SSEL2, P_SPI2_SSEL3,
978 P_SPI2_SSEL4, P_SPI2_SSEL5,
979 P_SPI2_SSEL6, P_SPI2_SSEL7},
982 /* setup for devices (may be called multiple times -- not just first setup) */
983 static int bfin_spi_setup(struct spi_device *spi)
985 struct bfin5xx_spi_chip *chip_info;
986 struct slave_data *chip = NULL;
987 struct master_data *drv_data = spi_master_get_devdata(spi->master);
990 if (spi->bits_per_word != 8 && spi->bits_per_word != 16)
993 /* Only alloc (or use chip_info) on first setup */
995 chip = spi_get_ctldata(spi);
997 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
999 dev_err(&spi->dev, "cannot allocate chip data\n");
1004 chip->enable_dma = 0;
1005 chip_info = spi->controller_data;
1008 /* chip_info isn't always needed */
1010 /* Make sure people stop trying to set fields via ctl_reg
1011 * when they should actually be using common SPI framework.
1012 * Currently we let through: WOM EMISO PSSE GM SZ.
1013 * Not sure if a user actually needs/uses any of these,
1014 * but let's assume (for now) they do.
1016 if (chip_info->ctl_reg & ~(BIT_CTL_OPENDRAIN | BIT_CTL_EMISO | \
1017 BIT_CTL_PSSE | BIT_CTL_GM | BIT_CTL_SZ)) {
1018 dev_err(&spi->dev, "do not set bits in ctl_reg "
1019 "that the SPI framework manages\n");
1023 chip->enable_dma = chip_info->enable_dma != 0
1024 && drv_data->master_info->enable_dma;
1025 chip->ctl_reg = chip_info->ctl_reg;
1026 chip->bits_per_word = chip_info->bits_per_word;
1027 chip->cs_chg_udelay = chip_info->cs_chg_udelay;
1028 chip->idle_tx_val = chip_info->idle_tx_val;
1029 chip->pio_interrupt = chip_info->pio_interrupt;
1032 /* translate common spi framework into our register */
1033 if (spi->mode & SPI_CPOL)
1034 chip->ctl_reg |= BIT_CTL_CPOL;
1035 if (spi->mode & SPI_CPHA)
1036 chip->ctl_reg |= BIT_CTL_CPHA;
1037 if (spi->mode & SPI_LSB_FIRST)
1038 chip->ctl_reg |= BIT_CTL_LSBF;
1039 /* we dont support running in slave mode (yet?) */
1040 chip->ctl_reg |= BIT_CTL_MASTER;
1043 * Notice: for blackfin, the speed_hz is the value of register
1044 * SPI_BAUD, not the real baudrate
1046 chip->baud = hz_to_spi_baud(spi->max_speed_hz);
1047 chip->chip_select_num = spi->chip_select;
1048 if (chip->chip_select_num < MAX_CTRL_CS)
1049 chip->flag = (1 << spi->chip_select) << 8;
1051 chip->cs_gpio = chip->chip_select_num - MAX_CTRL_CS;
1053 switch (chip->bits_per_word) {
1056 chip->width = CFG_SPI_WORDSIZE8;
1057 chip->ops = &bfin_transfer_ops_u8;
1062 chip->width = CFG_SPI_WORDSIZE16;
1063 chip->ops = &bfin_transfer_ops_u16;
1067 dev_err(&spi->dev, "%d bits_per_word is not supported\n",
1068 chip->bits_per_word);
1072 if (chip->enable_dma && chip->pio_interrupt) {
1073 dev_err(&spi->dev, "enable_dma is set, "
1074 "do not set pio_interrupt\n");
1078 * if any one SPI chip is registered and wants DMA, request the
1079 * DMA channel for it
1081 if (chip->enable_dma && !drv_data->dma_requested) {
1082 /* register dma irq handler */
1083 ret = request_dma(drv_data->dma_channel, "BFIN_SPI_DMA");
1086 "Unable to request BlackFin SPI DMA channel\n");
1089 drv_data->dma_requested = 1;
1091 ret = set_dma_callback(drv_data->dma_channel,
1092 bfin_spi_dma_irq_handler, drv_data);
1094 dev_err(&spi->dev, "Unable to set dma callback\n");
1097 dma_disable_irq(drv_data->dma_channel);
1100 if (chip->pio_interrupt && !drv_data->irq_requested) {
1101 ret = request_irq(drv_data->spi_irq, bfin_spi_pio_irq_handler,
1102 IRQF_DISABLED, "BFIN_SPI", drv_data);
1104 dev_err(&spi->dev, "Unable to register spi IRQ\n");
1107 drv_data->irq_requested = 1;
1108 /* we use write mode, spi irq has to be disabled here */
1109 disable_irq(drv_data->spi_irq);
1112 if (chip->chip_select_num >= MAX_CTRL_CS) {
1113 ret = gpio_request(chip->cs_gpio, spi->modalias);
1115 dev_err(&spi->dev, "gpio_request() error\n");
1118 gpio_direction_output(chip->cs_gpio, 1);
1121 dev_dbg(&spi->dev, "setup spi chip %s, width is %d, dma is %d\n",
1122 spi->modalias, chip->width, chip->enable_dma);
1123 dev_dbg(&spi->dev, "ctl_reg is 0x%x, flag_reg is 0x%x\n",
1124 chip->ctl_reg, chip->flag);
1126 spi_set_ctldata(spi, chip);
1128 dev_dbg(&spi->dev, "chip select number is %d\n", chip->chip_select_num);
1129 if (chip->chip_select_num < MAX_CTRL_CS) {
1130 ret = peripheral_request(ssel[spi->master->bus_num]
1131 [chip->chip_select_num-1], spi->modalias);
1133 dev_err(&spi->dev, "peripheral_request() error\n");
1138 bfin_spi_cs_enable(drv_data, chip);
1139 bfin_spi_cs_deactive(drv_data, chip);
1144 if (chip->chip_select_num >= MAX_CTRL_CS)
1145 gpio_free(chip->cs_gpio);
1147 peripheral_free(ssel[spi->master->bus_num]
1148 [chip->chip_select_num - 1]);
1151 if (drv_data->dma_requested)
1152 free_dma(drv_data->dma_channel);
1153 drv_data->dma_requested = 0;
1156 /* prevent free 'chip' twice */
1157 spi_set_ctldata(spi, NULL);
1164 * callback for spi framework.
1165 * clean driver specific data
1167 static void bfin_spi_cleanup(struct spi_device *spi)
1169 struct slave_data *chip = spi_get_ctldata(spi);
1170 struct master_data *drv_data = spi_master_get_devdata(spi->master);
1175 if (chip->chip_select_num < MAX_CTRL_CS) {
1176 peripheral_free(ssel[spi->master->bus_num]
1177 [chip->chip_select_num-1]);
1178 bfin_spi_cs_disable(drv_data, chip);
1180 gpio_free(chip->cs_gpio);
1183 /* prevent free 'chip' twice */
1184 spi_set_ctldata(spi, NULL);
1187 static inline int bfin_spi_init_queue(struct master_data *drv_data)
1189 INIT_LIST_HEAD(&drv_data->queue);
1190 spin_lock_init(&drv_data->lock);
1192 drv_data->running = false;
1195 /* init transfer tasklet */
1196 tasklet_init(&drv_data->pump_transfers,
1197 bfin_spi_pump_transfers, (unsigned long)drv_data);
1199 /* init messages workqueue */
1200 INIT_WORK(&drv_data->pump_messages, bfin_spi_pump_messages);
1201 drv_data->workqueue = create_singlethread_workqueue(
1202 dev_name(drv_data->master->dev.parent));
1203 if (drv_data->workqueue == NULL)
1209 static inline int bfin_spi_start_queue(struct master_data *drv_data)
1211 unsigned long flags;
1213 spin_lock_irqsave(&drv_data->lock, flags);
1215 if (drv_data->running || drv_data->busy) {
1216 spin_unlock_irqrestore(&drv_data->lock, flags);
1220 drv_data->running = true;
1221 drv_data->cur_msg = NULL;
1222 drv_data->cur_transfer = NULL;
1223 drv_data->cur_chip = NULL;
1224 spin_unlock_irqrestore(&drv_data->lock, flags);
1226 queue_work(drv_data->workqueue, &drv_data->pump_messages);
1231 static inline int bfin_spi_stop_queue(struct master_data *drv_data)
1233 unsigned long flags;
1234 unsigned limit = 500;
1237 spin_lock_irqsave(&drv_data->lock, flags);
1240 * This is a bit lame, but is optimized for the common execution path.
1241 * A wait_queue on the drv_data->busy could be used, but then the common
1242 * execution path (pump_messages) would be required to call wake_up or
1243 * friends on every SPI message. Do this instead
1245 drv_data->running = false;
1246 while (!list_empty(&drv_data->queue) && drv_data->busy && limit--) {
1247 spin_unlock_irqrestore(&drv_data->lock, flags);
1249 spin_lock_irqsave(&drv_data->lock, flags);
1252 if (!list_empty(&drv_data->queue) || drv_data->busy)
1255 spin_unlock_irqrestore(&drv_data->lock, flags);
1260 static inline int bfin_spi_destroy_queue(struct master_data *drv_data)
1264 status = bfin_spi_stop_queue(drv_data);
1268 destroy_workqueue(drv_data->workqueue);
1273 static int __init bfin_spi_probe(struct platform_device *pdev)
1275 struct device *dev = &pdev->dev;
1276 struct bfin5xx_spi_master *platform_info;
1277 struct spi_master *master;
1278 struct master_data *drv_data;
1279 struct resource *res;
1282 platform_info = dev->platform_data;
1284 /* Allocate master with space for drv_data */
1285 master = spi_alloc_master(dev, sizeof(*drv_data));
1287 dev_err(&pdev->dev, "can not alloc spi_master\n");
1291 drv_data = spi_master_get_devdata(master);
1292 drv_data->master = master;
1293 drv_data->master_info = platform_info;
1294 drv_data->pdev = pdev;
1295 drv_data->pin_req = platform_info->pin_req;
1297 /* the spi->mode bits supported by this driver: */
1298 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST;
1300 master->bus_num = pdev->id;
1301 master->num_chipselect = platform_info->num_chipselect;
1302 master->cleanup = bfin_spi_cleanup;
1303 master->setup = bfin_spi_setup;
1304 master->transfer = bfin_spi_transfer;
1306 /* Find and map our resources */
1307 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1309 dev_err(dev, "Cannot get IORESOURCE_MEM\n");
1311 goto out_error_get_res;
1314 drv_data->regs_base = ioremap(res->start, resource_size(res));
1315 if (drv_data->regs_base == NULL) {
1316 dev_err(dev, "Cannot map IO\n");
1318 goto out_error_ioremap;
1321 res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
1323 dev_err(dev, "No DMA channel specified\n");
1325 goto out_error_free_io;
1327 drv_data->dma_channel = res->start;
1329 drv_data->spi_irq = platform_get_irq(pdev, 0);
1330 if (drv_data->spi_irq < 0) {
1331 dev_err(dev, "No spi pio irq specified\n");
1333 goto out_error_free_io;
1336 /* Initial and start queue */
1337 status = bfin_spi_init_queue(drv_data);
1339 dev_err(dev, "problem initializing queue\n");
1340 goto out_error_queue_alloc;
1343 status = bfin_spi_start_queue(drv_data);
1345 dev_err(dev, "problem starting queue\n");
1346 goto out_error_queue_alloc;
1349 status = peripheral_request_list(drv_data->pin_req, DRV_NAME);
1351 dev_err(&pdev->dev, ": Requesting Peripherals failed\n");
1352 goto out_error_queue_alloc;
1355 /* Reset SPI registers. If these registers were used by the boot loader,
1356 * the sky may fall on your head if you enable the dma controller.
1358 write_CTRL(drv_data, BIT_CTL_CPHA | BIT_CTL_MASTER);
1359 write_FLAG(drv_data, 0xFF00);
1361 /* Register with the SPI framework */
1362 platform_set_drvdata(pdev, drv_data);
1363 status = spi_register_master(master);
1365 dev_err(dev, "problem registering spi master\n");
1366 goto out_error_queue_alloc;
1369 dev_info(dev, "%s, Version %s, regs_base@%p, dma channel@%d\n",
1370 DRV_DESC, DRV_VERSION, drv_data->regs_base,
1371 drv_data->dma_channel);
1374 out_error_queue_alloc:
1375 bfin_spi_destroy_queue(drv_data);
1377 iounmap((void *) drv_data->regs_base);
1380 spi_master_put(master);
1385 /* stop hardware and remove the driver */
1386 static int __devexit bfin_spi_remove(struct platform_device *pdev)
1388 struct master_data *drv_data = platform_get_drvdata(pdev);
1394 /* Remove the queue */
1395 status = bfin_spi_destroy_queue(drv_data);
1399 /* Disable the SSP at the peripheral and SOC level */
1400 bfin_spi_disable(drv_data);
1403 if (drv_data->master_info->enable_dma) {
1404 if (dma_channel_active(drv_data->dma_channel))
1405 free_dma(drv_data->dma_channel);
1408 if (drv_data->irq_requested) {
1409 free_irq(drv_data->spi_irq, drv_data);
1410 drv_data->irq_requested = 0;
1413 /* Disconnect from the SPI framework */
1414 spi_unregister_master(drv_data->master);
1416 peripheral_free_list(drv_data->pin_req);
1418 /* Prevent double remove */
1419 platform_set_drvdata(pdev, NULL);
1425 static int bfin_spi_suspend(struct platform_device *pdev, pm_message_t state)
1427 struct master_data *drv_data = platform_get_drvdata(pdev);
1430 status = bfin_spi_stop_queue(drv_data);
1434 drv_data->ctrl_reg = read_CTRL(drv_data);
1435 drv_data->flag_reg = read_FLAG(drv_data);
1438 * reset SPI_CTL and SPI_FLG registers
1440 write_CTRL(drv_data, BIT_CTL_CPHA | BIT_CTL_MASTER);
1441 write_FLAG(drv_data, 0xFF00);
1446 static int bfin_spi_resume(struct platform_device *pdev)
1448 struct master_data *drv_data = platform_get_drvdata(pdev);
1451 write_CTRL(drv_data, drv_data->ctrl_reg);
1452 write_FLAG(drv_data, drv_data->flag_reg);
1454 /* Start the queue running */
1455 status = bfin_spi_start_queue(drv_data);
1457 dev_err(&pdev->dev, "problem starting queue (%d)\n", status);
1464 #define bfin_spi_suspend NULL
1465 #define bfin_spi_resume NULL
1466 #endif /* CONFIG_PM */
1468 MODULE_ALIAS("platform:bfin-spi");
1469 static struct platform_driver bfin_spi_driver = {
1472 .owner = THIS_MODULE,
1474 .suspend = bfin_spi_suspend,
1475 .resume = bfin_spi_resume,
1476 .remove = __devexit_p(bfin_spi_remove),
1479 static int __init bfin_spi_init(void)
1481 return platform_driver_probe(&bfin_spi_driver, bfin_spi_probe);
1483 module_init(bfin_spi_init);
1485 static void __exit bfin_spi_exit(void)
1487 platform_driver_unregister(&bfin_spi_driver);
1489 module_exit(bfin_spi_exit);