2 * Copyright (c) 2010 Broadcom Corporation
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 #include <linux/types.h>
18 #include <linux/kernel.h>
19 #include <linux/printk.h>
20 #include <linux/pci_ids.h>
21 #include <linux/netdevice.h>
22 #include <linux/sched.h>
23 #include <linux/mmc/sdio.h>
24 #include <asm/unaligned.h>
26 #include <brcmu_wifi.h>
27 #include <brcmu_utils.h>
28 #include <brcm_hw_ids.h>
30 #include "sdio_host.h"
32 /* register access macros */
36 brcmf_sdcard_reg_read(NULL, (unsigned long)(r), sizeof(*(r)))
40 __typeof(*(r)) __osl_v; \
41 __asm__ __volatile__("sync"); \
42 __osl_v = brcmf_sdcard_reg_read(NULL, (unsigned long)(r),\
44 __asm__ __volatile__("sync"); \
49 #define W_REG(r, v) do { \
50 brcmf_sdcard_reg_write(NULL, (unsigned long)(r), sizeof(*(r)), \
53 #else /* __BIG_ENDIAN */
55 brcmf_sdcard_reg_read(NULL, (unsigned long)(r), sizeof(*(r)))
56 #define W_REG(r, v) do { \
57 brcmf_sdcard_reg_write(NULL, (unsigned long)(r), sizeof(*(r)), \
60 #endif /* __BIG_ENDIAN */
62 #define AND_REG(r, v) W_REG((r), R_REG(r) & (v))
63 #define OR_REG(r, v) W_REG((r), R_REG(r) | (v))
65 #define SET_REG(r, mask, val) \
66 W_REG((r), ((R_REG(r) & ~(mask)) | (val)))
70 /* ARM trap handling */
72 /* Trap types defined by ARM (see arminc.h) */
74 /* Trap locations in lo memory */
76 #define FIRST_TRAP TR_RST
77 #define LAST_TRAP (TR_FIQ * TRAP_STRIDE)
79 #if defined(__ARM_ARCH_4T__)
80 #define MAX_TRAP_TYPE (TR_FIQ + 1)
81 #elif defined(__ARM_ARCH_7M__)
82 #define MAX_TRAP_TYPE (TR_ISR + ARMCM3_NUMINTS)
83 #endif /* __ARM_ARCH_7M__ */
85 /* The trap structure is defined here as offsets for assembly */
91 #define TR_REG(n) (TR_REGS + (n) * 4)
92 #define TR_SP TR_REG(13)
93 #define TR_LR TR_REG(14)
94 #define TR_PC TR_REG(15)
96 #define TRAP_T_SIZE 80
98 typedef struct _trap_struct {
121 #define CBUF_LEN (128)
123 #define LOG_BUF_LEN 1024
126 u32 buf; /* Can't be pointer on (64-bit) hosts */
129 char *_buf_compat; /* Redundant pointer for backward compat. */
134 * When there is no UART (e.g. Quickturn),
135 * the host should write a complete
136 * input line directly into cbuf and then write
137 * the length into vcons_in.
138 * This may also be used when there is a real UART
139 * (at risk of conflicting with
140 * the real UART). vcons_out is currently unused.
142 volatile uint vcons_in;
143 volatile uint vcons_out;
145 /* Output (logging) buffer
146 * Console output is written to a ring buffer log_buf at index log_idx.
147 * The host may read the output when it sees log_idx advance.
148 * Output will be lost if the output wraps around faster than the host
153 /* Console input line buffer
154 * Characters are read one at a time into cbuf
155 * until <CR> is received, then
156 * the buffer is processed as a command line.
157 * Also used for virtual UART.
163 #endif /* DHD_DEBUG */
164 #include <chipcommon.h>
168 #include "dngl_stats.h"
171 #include "dhd_proto.h"
176 #ifndef DHDSDIO_MEM_DUMP_FNAME
177 #define DHDSDIO_MEM_DUMP_FNAME "mem_dump"
180 #define TXQLEN 2048 /* bulk tx queue length */
181 #define TXHI (TXQLEN - 256) /* turn on flow control above TXHI */
182 #define TXLOW (TXHI - 256) /* turn off flow control below TXLOW */
185 #define TXRETRIES 2 /* # of retries for tx frames */
187 #if defined(CONFIG_MACH_SANDGATE2G)
188 #define DHD_RXBOUND 250 /* Default for max rx frames in
191 #define DHD_RXBOUND 50 /* Default for max rx frames in
193 #endif /* defined(CONFIG_MACH_SANDGATE2G) */
195 #define DHD_TXBOUND 20 /* Default for max tx frames in
198 #define DHD_TXMINMAX 1 /* Max tx frames if rx still pending */
200 #define MEMBLOCK 2048 /* Block size used for downloading
202 #define MAX_DATA_BUF (32 * 1024) /* Must be large enough to hold
203 biggest possible glom */
205 /* Packet alignment for most efficient SDIO (can change based on platform) */
207 #define DHD_SDALIGN 32
209 #if !ISPOWEROF2(DHD_SDALIGN)
210 #error DHD_SDALIGN is not a power of 2!
213 #ifndef DHD_FIRSTREAD
214 #define DHD_FIRSTREAD 32
216 #if !ISPOWEROF2(DHD_FIRSTREAD)
217 #error DHD_FIRSTREAD is not a power of 2!
220 /* Total length of frame header for dongle protocol */
221 #define SDPCM_HDRLEN (SDPCM_FRAMETAG_LEN + SDPCM_SWHEADER_LEN)
223 #define SDPCM_RESERVE (SDPCM_HDRLEN + SDPCM_TEST_HDRLEN + DHD_SDALIGN)
225 #define SDPCM_RESERVE (SDPCM_HDRLEN + DHD_SDALIGN)
229 * Software allocation of To SB Mailbox resources
232 /* tosbmailbox bits corresponding to intstatus bits */
233 #define SMB_NAK (1 << 0) /* Frame NAK */
234 #define SMB_INT_ACK (1 << 1) /* Host Interrupt ACK */
235 #define SMB_USE_OOB (1 << 2) /* Use OOB Wakeup */
236 #define SMB_DEV_INT (1 << 3) /* Miscellaneous Interrupt */
238 /* tosbmailboxdata */
239 #define SMB_DATA_VERSION_SHIFT 16 /* host protocol version */
242 * Software allocation of To Host Mailbox resources
246 #define I_HMB_FC_STATE I_HMB_SW0 /* Flow Control State */
247 #define I_HMB_FC_CHANGE I_HMB_SW1 /* Flow Control State Changed */
248 #define I_HMB_FRAME_IND I_HMB_SW2 /* Frame Indication */
249 #define I_HMB_HOST_INT I_HMB_SW3 /* Miscellaneous Interrupt */
251 /* tohostmailboxdata */
252 #define HMB_DATA_NAKHANDLED 1 /* retransmit NAK'd frame */
253 #define HMB_DATA_DEVREADY 2 /* talk to host after enable */
254 #define HMB_DATA_FC 4 /* per prio flowcontrol update flag */
255 #define HMB_DATA_FWREADY 8 /* fw ready for protocol activity */
257 #define HMB_DATA_FCDATA_MASK 0xff000000
258 #define HMB_DATA_FCDATA_SHIFT 24
260 #define HMB_DATA_VERSION_MASK 0x00ff0000
261 #define HMB_DATA_VERSION_SHIFT 16
264 * Software-defined protocol header
267 /* Current protocol version */
268 #define SDPCM_PROT_VERSION 4
270 /* SW frame header */
271 #define SDPCM_PACKET_SEQUENCE(p) (((u8 *)p)[0] & 0xff)
273 #define SDPCM_CHANNEL_MASK 0x00000f00
274 #define SDPCM_CHANNEL_SHIFT 8
275 #define SDPCM_PACKET_CHANNEL(p) (((u8 *)p)[1] & 0x0f)
277 #define SDPCM_NEXTLEN_OFFSET 2
279 /* Data Offset from SOF (HW Tag, SW Tag, Pad) */
280 #define SDPCM_DOFFSET_OFFSET 3 /* Data Offset */
281 #define SDPCM_DOFFSET_VALUE(p) (((u8 *)p)[SDPCM_DOFFSET_OFFSET] & 0xff)
282 #define SDPCM_DOFFSET_MASK 0xff000000
283 #define SDPCM_DOFFSET_SHIFT 24
284 #define SDPCM_FCMASK_OFFSET 4 /* Flow control */
285 #define SDPCM_FCMASK_VALUE(p) (((u8 *)p)[SDPCM_FCMASK_OFFSET] & 0xff)
286 #define SDPCM_WINDOW_OFFSET 5 /* Credit based fc */
287 #define SDPCM_WINDOW_VALUE(p) (((u8 *)p)[SDPCM_WINDOW_OFFSET] & 0xff)
289 #define SDPCM_SWHEADER_LEN 8 /* SW header is 64 bits */
291 /* logical channel numbers */
292 #define SDPCM_CONTROL_CHANNEL 0 /* Control channel Id */
293 #define SDPCM_EVENT_CHANNEL 1 /* Asyc Event Indication Channel Id */
294 #define SDPCM_DATA_CHANNEL 2 /* Data Xmit/Recv Channel Id */
295 #define SDPCM_GLOM_CHANNEL 3 /* For coalesced packets */
296 #define SDPCM_TEST_CHANNEL 15 /* Reserved for test/debug packets */
298 #define SDPCM_SEQUENCE_WRAP 256 /* wrap-around val for 8bit frame seq */
300 #define SDPCM_GLOMDESC(p) (((u8 *)p)[1] & 0x80)
302 /* For TEST_CHANNEL packets, define another 4-byte header */
303 #define SDPCM_TEST_HDRLEN 4 /*
304 * Generally: Cmd(1), Ext(1), Len(2);
305 * Semantics of Ext byte depend on
306 * command. Len is current or requested
307 * frame length, not including test
308 * header; sent little-endian.
310 #define SDPCM_TEST_DISCARD 0x01 /* Receiver discards. Ext:pattern id. */
311 #define SDPCM_TEST_ECHOREQ 0x02 /* Echo request. Ext:pattern id. */
312 #define SDPCM_TEST_ECHORSP 0x03 /* Echo response. Ext:pattern id. */
313 #define SDPCM_TEST_BURST 0x04 /*
314 * Receiver to send a burst.
315 * Ext is a frame count
317 #define SDPCM_TEST_SEND 0x05 /*
318 * Receiver sets send mode.
319 * Ext is boolean on/off
322 /* Handy macro for filling in datagen packets with a pattern */
323 #define SDPCM_TEST_FILL(byteno, id) ((u8)(id + byteno))
326 * Shared structure between dongle and the host.
327 * The structure contains pointers to trap or assert information.
329 #define SDPCM_SHARED_VERSION 0x0002
330 #define SDPCM_SHARED_VERSION_MASK 0x00FF
331 #define SDPCM_SHARED_ASSERT_BUILT 0x0100
332 #define SDPCM_SHARED_ASSERT 0x0200
333 #define SDPCM_SHARED_TRAP 0x0400
336 /* Space for header read, limit for data packets */
338 #define MAX_HDR_READ 32
340 #if !ISPOWEROF2(MAX_HDR_READ)
341 #error MAX_HDR_READ is not a power of 2!
344 #define MAX_RX_DATASZ 2048
346 /* Maximum milliseconds to wait for F2 to come up */
347 #define DHD_WAIT_F2RDY 3000
349 /* Bump up limit on waiting for HT to account for first startup;
350 * if the image is doing a CRC calculation before programming the PMU
351 * for HT availability, it could take a couple hundred ms more, so
352 * max out at a 1 second (1000000us).
354 #if (PMU_MAX_TRANSITION_DLY <= 1000000)
355 #undef PMU_MAX_TRANSITION_DLY
356 #define PMU_MAX_TRANSITION_DLY 1000000
359 /* Value for ChipClockCSR during initial setup */
360 #define DHD_INIT_CLKCTL1 (SBSDIO_FORCE_HW_CLKREQ_OFF | \
361 SBSDIO_ALP_AVAIL_REQ)
362 #define DHD_INIT_CLKCTL2 (SBSDIO_FORCE_HW_CLKREQ_OFF | SBSDIO_FORCE_ALP)
364 /* Flags for SDH calls */
365 #define F2SYNC (SDIO_REQ_4BYTE | SDIO_REQ_FIXED)
368 #define SBIM_IBE 0x20000 /* inbanderror */
369 #define SBIM_TO 0x40000 /* timeout */
370 #define SBIM_BY 0x01800000 /* busy (sonics >= 2.3) */
371 #define SBIM_RJ 0x02000000 /* reject (sonics >= 2.3) */
374 #define SBTML_RESET 0x0001 /* reset */
375 #define SBTML_REJ_MASK 0x0006 /* reject field */
376 #define SBTML_REJ 0x0002 /* reject */
377 #define SBTML_TMPREJ 0x0004 /* temporary reject, for error recovery */
379 #define SBTML_SICF_SHIFT 16 /* Shift to locate the SI control flags in sbtml */
382 #define SBTMH_SERR 0x0001 /* serror */
383 #define SBTMH_INT 0x0002 /* interrupt */
384 #define SBTMH_BUSY 0x0004 /* busy */
385 #define SBTMH_TO 0x0020 /* timeout (sonics >= 2.3) */
387 #define SBTMH_SISF_SHIFT 16 /* Shift to locate the SI status flags in sbtmh */
390 #define SBIDL_INIT 0x80 /* initiator */
393 #define SBIDH_RC_MASK 0x000f /* revision code */
394 #define SBIDH_RCE_MASK 0x7000 /* revision code extension field */
395 #define SBIDH_RCE_SHIFT 8
396 #define SBCOREREV(sbidh) \
397 ((((sbidh) & SBIDH_RCE_MASK) >> SBIDH_RCE_SHIFT) | ((sbidh) & SBIDH_RC_MASK))
398 #define SBIDH_CC_MASK 0x8ff0 /* core code */
399 #define SBIDH_CC_SHIFT 4
400 #define SBIDH_VC_MASK 0xffff0000 /* vendor code */
401 #define SBIDH_VC_SHIFT 16
404 * Conversion of 802.1D priority to precedence level
406 #define PRIO2PREC(prio) \
407 (((prio) == PRIO_8021D_NONE || (prio) == PRIO_8021D_BE) ? \
410 DHD_SPINWAIT_SLEEP_INIT(sdioh_spinwait_sleep);
412 /* Core reg address translation */
413 #define CORE_CC_REG(base, field) (base + offsetof(chipcregs_t, field))
414 #define CORE_BUS_REG(base, field) \
415 (base + offsetof(struct sdpcmd_regs, field))
416 #define CORE_SB(base, field) \
417 (base + SBCONFIGOFF + offsetof(sbconfig_t, field))
420 /* Device console log buffer state */
421 typedef struct dhd_console {
422 uint count; /* Poll interval msec counter */
423 uint log_addr; /* Log struct address (fixed) */
424 rte_log_t log; /* Log struct (host copy) */
425 uint bufsize; /* Size of log buffer */
426 u8 *buf; /* Log buffer (host copy) */
427 uint last; /* Last buffer read index */
429 #endif /* DHD_DEBUG */
431 struct sdpcm_shared {
435 u32 assert_file_addr;
437 u32 console_addr; /* Address of rte_cons_t */
443 /* misc chip info needed by some of the routines */
459 /* Private data for SDIO bus interaction */
460 typedef struct dhd_bus {
463 struct brcmf_sdio *sdh; /* Handle for BCMSDH calls */
464 struct chip_info *ci; /* Chip info struct */
465 char *vars; /* Variables (from CIS and/or other) */
466 uint varsz; /* Size of variables buffer */
467 u32 sbaddr; /* Current SB window pointer (-1, invalid) */
469 struct sdpcmd_regs *regs; /* SDIO core */
470 uint sdpcmrev; /* SDIO core revision */
471 uint armrev; /* CPU core revision */
472 uint ramrev; /* SOCRAM core revision */
473 u32 ramsize; /* Size of RAM in SOCRAM (bytes) */
474 u32 orig_ramsize; /* Size of RAM in SOCRAM (bytes) */
476 u32 bus; /* gSPI or SDIO bus */
477 u32 hostintmask; /* Copy of Host Interrupt Mask */
478 u32 intstatus; /* Intstatus bits (events) pending */
479 bool dpc_sched; /* Indicates DPC schedule (intrpt rcvd) */
480 bool fcstate; /* State of dongle flow-control */
482 u16 cl_devid; /* cached devid for brcmf_sdio_probe_attach() */
483 char *fw_path; /* module_param: path to firmware image */
484 char *nv_path; /* module_param: path to nvram vars file */
485 const char *nvram_params; /* user specified nvram params. */
487 uint blocksize; /* Block size of SDIO transfers */
488 uint roundup; /* Max roundup limit */
490 struct pktq txq; /* Queue length used for flow-control */
491 u8 flowcontrol; /* per prio flow control bitmask */
492 u8 tx_seq; /* Transmit sequence number (next) */
493 u8 tx_max; /* Maximum transmit sequence allowed */
495 u8 hdrbuf[MAX_HDR_READ + DHD_SDALIGN];
496 u8 *rxhdr; /* Header of current rx frame (in hdrbuf) */
497 u16 nextlen; /* Next Read Len from last header */
498 u8 rx_seq; /* Receive sequence number (expected) */
499 bool rxskip; /* Skip receive (awaiting NAK ACK) */
501 struct sk_buff *glomd; /* Packet containing glomming descriptor */
502 struct sk_buff *glom; /* Packet chain for glommed superframe */
503 uint glomerr; /* Glom packet read errors */
505 u8 *rxbuf; /* Buffer for receiving control packets */
506 uint rxblen; /* Allocated length of rxbuf */
507 u8 *rxctl; /* Aligned pointer into rxbuf */
508 u8 *databuf; /* Buffer for receiving big glom packet */
509 u8 *dataptr; /* Aligned pointer into databuf */
510 uint rxlen; /* Length of valid data in buffer */
512 u8 sdpcm_ver; /* Bus protocol reported by dongle */
514 bool intr; /* Use interrupts */
515 bool poll; /* Use polling */
516 bool ipend; /* Device interrupt is pending */
517 bool intdis; /* Interrupts disabled by isr */
518 uint intrcount; /* Count of device interrupt callbacks */
519 uint lastintrs; /* Count as of last watchdog timer */
520 uint spurious; /* Count of spurious interrupts */
521 uint pollrate; /* Ticks between device polls */
522 uint polltick; /* Tick counter */
523 uint pollcnt; /* Count of active polls */
526 dhd_console_t console; /* Console output polling support */
527 uint console_addr; /* Console address from shared struct */
528 #endif /* DHD_DEBUG */
530 uint regfails; /* Count of R_REG/W_REG failures */
532 uint clkstate; /* State of sd and backplane clock(s) */
533 bool activity; /* Activity flag for clock down */
534 s32 idletime; /* Control for activity timeout */
535 s32 idlecount; /* Activity timeout counter */
536 s32 idleclock; /* How to set bus driver when idle */
537 s32 sd_rxchain; /* If bcmsdh api accepts PKT chains */
538 bool use_rxchain; /* If dhd should use PKT chains */
539 bool sleeping; /* Is SDIO bus sleeping? */
540 bool rxflow_mode; /* Rx flow control mode */
541 bool rxflow; /* Is rx flow control on */
542 uint prev_rxlim_hit; /* Is prev rx limit exceeded
543 (per dpc schedule) */
544 bool alp_only; /* Don't use HT clock (ALP only) */
545 /* Field to decide if rx of control frames happen in rxbuf or lb-pool */
549 /* external loopback */
553 /* pktgen configuration */
554 uint pktgen_freq; /* Ticks between bursts */
555 uint pktgen_count; /* Packets to send each burst */
556 uint pktgen_print; /* Bursts between count displays */
557 uint pktgen_total; /* Stop after this many */
558 uint pktgen_minlen; /* Minimum packet data len */
559 uint pktgen_maxlen; /* Maximum packet data len */
560 uint pktgen_mode; /* Configured mode: tx, rx, or echo */
561 uint pktgen_stop; /* Number of tx failures causing stop */
563 /* active pktgen fields */
564 uint pktgen_tick; /* Tick counter for bursts */
565 uint pktgen_ptick; /* Burst counter for printing */
566 uint pktgen_sent; /* Number of test packets generated */
567 uint pktgen_rcvd; /* Number of test packets received */
568 uint pktgen_fail; /* Number of failed send attempts */
569 u16 pktgen_len; /* Length of next packet to send */
572 /* Some additional counters */
573 uint tx_sderrs; /* Count of tx attempts with sd errors */
574 uint fcqueued; /* Tx packets that got queued */
575 uint rxrtx; /* Count of rtx requests (NAK to dongle) */
576 uint rx_toolong; /* Receive frames too long to receive */
577 uint rxc_errors; /* SDIO errors when reading control frames */
578 uint rx_hdrfail; /* SDIO errors on header reads */
579 uint rx_badhdr; /* Bad received headers (roosync?) */
580 uint rx_badseq; /* Mismatched rx sequence number */
581 uint fc_rcvd; /* Number of flow-control events received */
582 uint fc_xoff; /* Number which turned on flow-control */
583 uint fc_xon; /* Number which turned off flow-control */
584 uint rxglomfail; /* Failed deglom attempts */
585 uint rxglomframes; /* Number of glom frames (superframes) */
586 uint rxglompkts; /* Number of packets from glom frames */
587 uint f2rxhdrs; /* Number of header reads */
588 uint f2rxdata; /* Number of frame data reads */
589 uint f2txdata; /* Number of f2 frame writes */
590 uint f1regdata; /* Number of f1 register accesses */
594 bool ctrl_frame_stat;
599 typedef volatile struct _sbconfig {
601 u32 sbipsflag; /* initiator port ocp slave flag */
603 u32 sbtpsflag; /* target port ocp slave flag */
605 u32 sbtmerrloga; /* (sonics >= 2.3) */
607 u32 sbtmerrlog; /* (sonics >= 2.3) */
609 u32 sbadmatch3; /* address match3 */
611 u32 sbadmatch2; /* address match2 */
613 u32 sbadmatch1; /* address match1 */
615 u32 sbimstate; /* initiator agent state */
616 u32 sbintvec; /* interrupt mask */
617 u32 sbtmstatelow; /* target state */
618 u32 sbtmstatehigh; /* target state */
619 u32 sbbwa0; /* bandwidth allocation table0 */
621 u32 sbimconfiglow; /* initiator configuration */
622 u32 sbimconfighigh; /* initiator configuration */
623 u32 sbadmatch0; /* address match0 */
625 u32 sbtmconfiglow; /* target configuration */
626 u32 sbtmconfighigh; /* target configuration */
627 u32 sbbconfig; /* broadcast configuration */
629 u32 sbbstate; /* broadcast state */
631 u32 sbactcnfg; /* activate configuration */
633 u32 sbflagst; /* current sbflags */
635 u32 sbidlow; /* identification */
636 u32 sbidhigh; /* identification */
642 #define CLK_PENDING 2 /* Not used yet */
645 #define DHD_NOPMU(dhd) (false)
648 static int qcount[NUMPRIO];
649 static int tx_packets[NUMPRIO];
650 #endif /* DHD_DEBUG */
652 /* Deferred transmit */
653 const uint brcmf_deferred_tx = 1;
660 /* override the RAM size if possible */
661 #define DONGLE_MIN_MEMSIZE (128 * 1024)
662 int brcmf_dongle_memsize;
664 static bool dhd_alignctl;
668 static bool retrydata;
669 #define RETRYCHAN(chan) (((chan) == SDPCM_EVENT_CHANNEL) || retrydata)
671 static const uint watermark = 8;
672 static const uint firstread = DHD_FIRSTREAD;
674 #define HDATLEN (firstread - (SDPCM_HDRLEN))
676 /* Retry count for register access failures */
677 static const uint retry_limit = 2;
679 /* Force even SD lengths (some host controllers mess up on odd bytes) */
680 static bool forcealign;
684 #if defined(OOB_INTR_ONLY) && defined(HW_OOB)
685 extern void brcmf_sdcard_enable_hw_oob_intr(void *sdh, bool enable);
688 #if defined(OOB_INTR_ONLY) && defined(SDIO_ISR_THREAD)
689 #error OOB_INTR_ONLY is NOT working with SDIO_ISR_THREAD
690 #endif /* defined(OOB_INTR_ONLY) && defined(SDIO_ISR_THREAD) */
691 #define PKTALIGN(_p, _len, _align) \
694 datalign = (unsigned long)((_p)->data); \
695 datalign = roundup(datalign, (_align)) - datalign; \
696 ASSERT(datalign < (_align)); \
697 ASSERT((_p)->len >= ((_len) + datalign)); \
699 skb_pull((_p), datalign); \
700 __skb_trim((_p), (_len)); \
703 /* Limit on rounding up frames */
704 static const uint max_roundup = 512;
706 /* Try doing readahead */
707 static bool dhd_readahead;
709 /* To check if there's window offered */
710 #define DATAOK(bus) \
711 (((u8)(bus->tx_max - bus->tx_seq) != 0) && \
712 (((u8)(bus->tx_max - bus->tx_seq) & 0x80) == 0))
714 /* Macros to get register read/write status */
715 /* NOTE: these assume a local dhdsdio_bus_t *bus! */
716 #define R_SDREG(regvar, regaddr, retryvar) \
720 regvar = R_REG(regaddr); \
721 } while (brcmf_sdcard_regfail(bus->sdh) && \
722 (++retryvar <= retry_limit)); \
724 bus->regfails += (retryvar-1); \
725 if (retryvar > retry_limit) { \
726 DHD_ERROR(("%s: FAILED" #regvar "READ, LINE %d\n", \
727 __func__, __LINE__)); \
733 #define W_SDREG(regval, regaddr, retryvar) \
737 W_REG(regaddr, regval); \
738 } while (brcmf_sdcard_regfail(bus->sdh) && \
739 (++retryvar <= retry_limit)); \
741 bus->regfails += (retryvar-1); \
742 if (retryvar > retry_limit) \
743 DHD_ERROR(("%s: FAILED REGISTER WRITE, LINE %d\n", \
744 __func__, __LINE__)); \
748 #define DHD_BUS SDIO_BUS
750 #define PKT_AVAILABLE() (intstatus & I_HMB_FRAME_IND)
752 #define HOSTINTMASK (I_HMB_SW_MASK | I_CHIPACTIVE)
755 static void brcmf_sdbrcm_checkdied(dhd_bus_t *bus, void *pkt, uint seq);
756 static void brcmf_sdbrcm_sdtest_set(dhd_bus_t *bus, bool start);
760 static int brcmf_sdbrcm_checkdied(dhd_bus_t *bus, u8 *data, uint size);
761 static int brcmf_sdbrcm_mem_dump(dhd_bus_t *bus);
762 #endif /* DHD_DEBUG */
763 static int brcmf_sdbrcm_download_state(dhd_bus_t *bus, bool enter);
765 static void brcmf_sdbrcm_release(dhd_bus_t *bus);
766 static void brcmf_sdbrcm_release_malloc(dhd_bus_t *bus);
767 static void brcmf_sdbrcm_disconnect(void *ptr);
768 static bool brcmf_sdbrcm_chipmatch(u16 chipid);
769 static bool brcmf_sdbrcm_probe_attach(dhd_bus_t *bus, void *sdh,
770 void *regsva, u16 devid);
771 static bool brcmf_sdbrcm_probe_malloc(dhd_bus_t *bus, void *sdh);
772 static bool brcmf_sdbrcm_probe_init(dhd_bus_t *bus, void *sdh);
773 static void brcmf_sdbrcm_release_dongle(dhd_bus_t *bus);
775 static uint brcmf_process_nvram_vars(char *varbuf, uint len);
777 static void brcmf_sdbrcm_setmemsize(struct dhd_bus *bus, int mem_size);
778 static int brcmf_sdbrcm_send_buf(dhd_bus_t *bus, u32 addr, uint fn,
779 uint flags, u8 *buf, uint nbytes,
780 struct sk_buff *pkt, bcmsdh_cmplt_fn_t complete,
783 static bool brcmf_sdbrcm_download_firmware(struct dhd_bus *bus, void *sdh);
784 static int _brcmf_sdbrcm_download_firmware(struct dhd_bus *bus);
787 brcmf_sdbrcm_download_code_file(struct dhd_bus *bus, char *image_path);
788 static int brcmf_sdbrcm_download_nvram(struct dhd_bus *bus);
789 static void brcmf_sdbrcm_chip_disablecore(struct brcmf_sdio *sdh, u32 corebase);
790 static int brcmf_sdbrcm_chip_attach(struct dhd_bus *bus, void *regs);
791 static void brcmf_sdbrcm_chip_resetcore(struct brcmf_sdio *sdh, u32 corebase);
792 static void brcmf_sdbrcm_sdiod_drive_strength_init(struct dhd_bus *bus,
794 static void brcmf_sdbrcm_chip_detach(struct dhd_bus *bus);
796 /* Packet free applicable unconditionally for sdio and sdspi.
797 * Conditional if bufpool was present for gspi bus.
799 static void brcmf_sdbrcm_pktfree2(dhd_bus_t *bus, struct sk_buff *pkt)
801 if ((bus->bus != SPI_BUS) || bus->usebufpool)
802 brcmu_pkt_buf_free_skb(pkt);
805 static void brcmf_sdbrcm_setmemsize(struct dhd_bus *bus, int mem_size)
807 s32 min_size = DONGLE_MIN_MEMSIZE;
808 /* Restrict the memsize to user specified limit */
809 DHD_ERROR(("user: Restrict the dongle ram size to %d, min %d\n",
810 brcmf_dongle_memsize, min_size));
811 if ((brcmf_dongle_memsize > min_size) &&
812 (brcmf_dongle_memsize < (s32) bus->orig_ramsize))
813 bus->ramsize = brcmf_dongle_memsize;
816 static int brcmf_sdbrcm_set_siaddr_window(dhd_bus_t *bus, u32 address)
819 brcmf_sdcard_cfg_write(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_SBADDRLOW,
820 (address >> 8) & SBSDIO_SBADDRLOW_MASK, &err);
822 brcmf_sdcard_cfg_write(bus->sdh, SDIO_FUNC_1,
823 SBSDIO_FUNC1_SBADDRMID,
824 (address >> 16) & SBSDIO_SBADDRMID_MASK, &err);
826 brcmf_sdcard_cfg_write(bus->sdh, SDIO_FUNC_1,
827 SBSDIO_FUNC1_SBADDRHIGH,
828 (address >> 24) & SBSDIO_SBADDRHIGH_MASK,
833 /* Turn backplane clock on or off */
834 static int brcmf_sdbrcm_htclk(dhd_bus_t *bus, bool on, bool pendok)
837 u8 clkctl, clkreq, devctl;
838 struct brcmf_sdio *sdh;
840 DHD_TRACE(("%s: Enter\n", __func__));
842 #if defined(OOB_INTR_ONLY)
849 /* Request HT Avail */
851 bus->alp_only ? SBSDIO_ALP_AVAIL_REQ : SBSDIO_HT_AVAIL_REQ;
853 if ((bus->ci->chip == BCM4329_CHIP_ID)
854 && (bus->ci->chiprev == 0))
855 clkreq |= SBSDIO_FORCE_ALP;
857 brcmf_sdcard_cfg_write(sdh, SDIO_FUNC_1,
858 SBSDIO_FUNC1_CHIPCLKCSR, clkreq, &err);
860 DHD_ERROR(("%s: HT Avail request error: %d\n",
865 if (pendok && ((bus->ci->buscoretype == PCMCIA_CORE_ID)
866 && (bus->ci->buscorerev == 9))) {
868 R_SDREG(dummy, &bus->regs->clockctlstatus, retries);
871 /* Check current status */
872 clkctl = brcmf_sdcard_cfg_read(sdh, SDIO_FUNC_1,
873 SBSDIO_FUNC1_CHIPCLKCSR, &err);
875 DHD_ERROR(("%s: HT Avail read error: %d\n",
880 /* Go to pending and await interrupt if appropriate */
881 if (!SBSDIO_CLKAV(clkctl, bus->alp_only) && pendok) {
882 /* Allow only clock-available interrupt */
883 devctl = brcmf_sdcard_cfg_read(sdh, SDIO_FUNC_1,
884 SBSDIO_DEVICE_CTL, &err);
886 DHD_ERROR(("%s: Devctl error setting CA: %d\n",
891 devctl |= SBSDIO_DEVCTL_CA_INT_ONLY;
892 brcmf_sdcard_cfg_write(sdh, SDIO_FUNC_1,
893 SBSDIO_DEVICE_CTL, devctl, &err);
894 DHD_INFO(("CLKCTL: set PENDING\n"));
895 bus->clkstate = CLK_PENDING;
898 } else if (bus->clkstate == CLK_PENDING) {
899 /* Cancel CA-only interrupt filter */
901 brcmf_sdcard_cfg_read(sdh, SDIO_FUNC_1,
902 SBSDIO_DEVICE_CTL, &err);
903 devctl &= ~SBSDIO_DEVCTL_CA_INT_ONLY;
904 brcmf_sdcard_cfg_write(sdh, SDIO_FUNC_1,
905 SBSDIO_DEVICE_CTL, devctl, &err);
908 /* Otherwise, wait here (polling) for HT Avail */
909 if (!SBSDIO_CLKAV(clkctl, bus->alp_only)) {
910 SPINWAIT_SLEEP(sdioh_spinwait_sleep,
912 brcmf_sdcard_cfg_read(sdh, SDIO_FUNC_1,
913 SBSDIO_FUNC1_CHIPCLKCSR,
915 !SBSDIO_CLKAV(clkctl, bus->alp_only)),
916 PMU_MAX_TRANSITION_DLY);
919 DHD_ERROR(("%s: HT Avail request error: %d\n",
923 if (!SBSDIO_CLKAV(clkctl, bus->alp_only)) {
924 DHD_ERROR(("%s: HT Avail timeout (%d): clkctl 0x%02x\n",
925 __func__, PMU_MAX_TRANSITION_DLY, clkctl));
929 /* Mark clock available */
930 bus->clkstate = CLK_AVAIL;
931 DHD_INFO(("CLKCTL: turned ON\n"));
933 #if defined(DHD_DEBUG)
934 if (bus->alp_only == true) {
935 #if !defined(BCMLXSDMMC)
936 if (!SBSDIO_ALPONLY(clkctl)) {
937 DHD_ERROR(("%s: HT Clock, when ALP Only\n",
940 #endif /* !defined(BCMLXSDMMC) */
942 if (SBSDIO_ALPONLY(clkctl)) {
943 DHD_ERROR(("%s: HT Clock should be on.\n",
947 #endif /* defined (DHD_DEBUG) */
949 bus->activity = true;
953 if (bus->clkstate == CLK_PENDING) {
954 /* Cancel CA-only interrupt filter */
955 devctl = brcmf_sdcard_cfg_read(sdh, SDIO_FUNC_1,
956 SBSDIO_DEVICE_CTL, &err);
957 devctl &= ~SBSDIO_DEVCTL_CA_INT_ONLY;
958 brcmf_sdcard_cfg_write(sdh, SDIO_FUNC_1,
959 SBSDIO_DEVICE_CTL, devctl, &err);
962 bus->clkstate = CLK_SDONLY;
963 brcmf_sdcard_cfg_write(sdh, SDIO_FUNC_1,
964 SBSDIO_FUNC1_CHIPCLKCSR, clkreq, &err);
965 DHD_INFO(("CLKCTL: turned OFF\n"));
967 DHD_ERROR(("%s: Failed access turning clock off: %d\n",
975 /* Change idle/active SD state */
976 static int brcmf_sdbrcm_sdclk(dhd_bus_t *bus, bool on)
978 DHD_TRACE(("%s: Enter\n", __func__));
981 bus->clkstate = CLK_SDONLY;
983 bus->clkstate = CLK_NONE;
988 /* Transition SD and backplane clock readiness */
989 static int brcmf_sdbrcm_clkctl(dhd_bus_t *bus, uint target, bool pendok)
992 uint oldstate = bus->clkstate;
993 #endif /* DHD_DEBUG */
995 DHD_TRACE(("%s: Enter\n", __func__));
997 /* Early exit if we're already there */
998 if (bus->clkstate == target) {
999 if (target == CLK_AVAIL) {
1000 brcmf_os_wd_timer(bus->dhd, brcmf_watchdog_ms);
1001 bus->activity = true;
1008 /* Make sure SD clock is available */
1009 if (bus->clkstate == CLK_NONE)
1010 brcmf_sdbrcm_sdclk(bus, true);
1011 /* Now request HT Avail on the backplane */
1012 brcmf_sdbrcm_htclk(bus, true, pendok);
1013 brcmf_os_wd_timer(bus->dhd, brcmf_watchdog_ms);
1014 bus->activity = true;
1018 /* Remove HT request, or bring up SD clock */
1019 if (bus->clkstate == CLK_NONE)
1020 brcmf_sdbrcm_sdclk(bus, true);
1021 else if (bus->clkstate == CLK_AVAIL)
1022 brcmf_sdbrcm_htclk(bus, false, false);
1024 DHD_ERROR(("brcmf_sdbrcm_clkctl: request for %d -> %d"
1025 "\n", bus->clkstate, target));
1026 brcmf_os_wd_timer(bus->dhd, brcmf_watchdog_ms);
1030 /* Make sure to remove HT request */
1031 if (bus->clkstate == CLK_AVAIL)
1032 brcmf_sdbrcm_htclk(bus, false, false);
1033 /* Now remove the SD clock */
1034 brcmf_sdbrcm_sdclk(bus, false);
1035 brcmf_os_wd_timer(bus->dhd, 0);
1039 DHD_INFO(("brcmf_sdbrcm_clkctl: %d -> %d\n", oldstate, bus->clkstate));
1040 #endif /* DHD_DEBUG */
1045 int brcmf_sdbrcm_bussleep(dhd_bus_t *bus, bool sleep)
1047 struct brcmf_sdio *sdh = bus->sdh;
1048 struct sdpcmd_regs *regs = bus->regs;
1051 DHD_INFO(("brcmf_sdbrcm_bussleep: request %s (currently %s)\n",
1052 (sleep ? "SLEEP" : "WAKE"),
1053 (bus->sleeping ? "SLEEP" : "WAKE")));
1055 /* Done if we're already in the requested state */
1056 if (sleep == bus->sleeping)
1059 /* Going to sleep: set the alarm and turn off the lights... */
1061 /* Don't sleep if something is pending */
1062 if (bus->dpc_sched || bus->rxskip || pktq_len(&bus->txq))
1065 /* Disable SDIO interrupts (no longer interested) */
1066 brcmf_sdcard_intr_disable(bus->sdh);
1068 /* Make sure the controller has the bus up */
1069 brcmf_sdbrcm_clkctl(bus, CLK_AVAIL, false);
1071 /* Tell device to start using OOB wakeup */
1072 W_SDREG(SMB_USE_OOB, ®s->tosbmailbox, retries);
1073 if (retries > retry_limit)
1074 DHD_ERROR(("CANNOT SIGNAL CHIP, WILL NOT WAKE UP!!\n"));
1076 /* Turn off our contribution to the HT clock request */
1077 brcmf_sdbrcm_clkctl(bus, CLK_SDONLY, false);
1079 brcmf_sdcard_cfg_write(sdh, SDIO_FUNC_1,
1080 SBSDIO_FUNC1_CHIPCLKCSR,
1081 SBSDIO_FORCE_HW_CLKREQ_OFF, NULL);
1083 /* Isolate the bus */
1084 if (bus->ci->chip != BCM4329_CHIP_ID
1085 && bus->ci->chip != BCM4319_CHIP_ID) {
1086 brcmf_sdcard_cfg_write(sdh, SDIO_FUNC_1,
1088 SBSDIO_DEVCTL_PADS_ISO, NULL);
1092 bus->sleeping = true;
1095 /* Waking up: bus power up is ok, set local state */
1097 brcmf_sdcard_cfg_write(sdh, SDIO_FUNC_1,
1098 SBSDIO_FUNC1_CHIPCLKCSR, 0, NULL);
1100 /* Force pad isolation off if possible
1101 (in case power never toggled) */
1102 if ((bus->ci->buscoretype == PCMCIA_CORE_ID)
1103 && (bus->ci->buscorerev >= 10))
1104 brcmf_sdcard_cfg_write(sdh, SDIO_FUNC_1,
1105 SBSDIO_DEVICE_CTL, 0, NULL);
1107 /* Make sure the controller has the bus up */
1108 brcmf_sdbrcm_clkctl(bus, CLK_AVAIL, false);
1110 /* Send misc interrupt to indicate OOB not needed */
1111 W_SDREG(0, ®s->tosbmailboxdata, retries);
1112 if (retries <= retry_limit)
1113 W_SDREG(SMB_DEV_INT, ®s->tosbmailbox, retries);
1115 if (retries > retry_limit)
1116 DHD_ERROR(("CANNOT SIGNAL CHIP TO CLEAR OOB!!\n"));
1118 /* Make sure we have SD bus access */
1119 brcmf_sdbrcm_clkctl(bus, CLK_SDONLY, false);
1122 bus->sleeping = false;
1124 /* Enable interrupts again */
1125 if (bus->intr && (bus->dhd->busstate == DHD_BUS_DATA)) {
1126 bus->intdis = false;
1127 brcmf_sdcard_intr_enable(bus->sdh);
1134 #if defined(OOB_INTR_ONLY)
1135 void brcmf_sdbrcm_enable_oob_intr(struct dhd_bus *bus, bool enable)
1138 brcmf_sdcard_enable_hw_oob_intr(bus->sdh, enable);
1140 sdpcmd_regs_t *regs = bus->regs;
1143 brcmf_sdbrcm_clkctl(bus, CLK_AVAIL, false);
1144 if (enable == true) {
1146 /* Tell device to start using OOB wakeup */
1147 W_SDREG(SMB_USE_OOB, ®s->tosbmailbox, retries);
1148 if (retries > retry_limit)
1149 DHD_ERROR(("CANNOT SIGNAL CHIP, WILL NOT WAKE UP!!\n"));
1152 /* Send misc interrupt to indicate OOB not needed */
1153 W_SDREG(0, ®s->tosbmailboxdata, retries);
1154 if (retries <= retry_limit)
1155 W_SDREG(SMB_DEV_INT, ®s->tosbmailbox, retries);
1158 /* Turn off our contribution to the HT clock request */
1159 brcmf_sdbrcm_clkctl(bus, CLK_SDONLY, false);
1160 #endif /* !defined(HW_OOB) */
1162 #endif /* defined(OOB_INTR_ONLY) */
1164 #define BUS_WAKE(bus) \
1166 if ((bus)->sleeping) \
1167 brcmf_sdbrcm_bussleep((bus), false); \
1170 /* Writes a HW/SW header into the packet and sends it. */
1171 /* Assumes: (a) header space already there, (b) caller holds lock */
1172 static int brcmf_sdbrcm_txpkt(dhd_bus_t *bus, struct sk_buff *pkt, uint chan,
1180 struct brcmf_sdio *sdh;
1181 struct sk_buff *new;
1184 DHD_TRACE(("%s: Enter\n", __func__));
1188 if (bus->dhd->dongle_reset) {
1193 frame = (u8 *) (pkt->data);
1195 /* Add alignment padding, allocate new packet if needed */
1196 pad = ((unsigned long)frame % DHD_SDALIGN);
1198 if (skb_headroom(pkt) < pad) {
1199 DHD_INFO(("%s: insufficient headroom %d for %d pad\n",
1200 __func__, skb_headroom(pkt), pad));
1201 bus->dhd->tx_realloc++;
1202 new = brcmu_pkt_buf_get_skb(pkt->len + DHD_SDALIGN);
1204 DHD_ERROR(("%s: couldn't allocate new %d-byte "
1206 __func__, pkt->len + DHD_SDALIGN));
1211 PKTALIGN(new, pkt->len, DHD_SDALIGN);
1212 memcpy(new->data, pkt->data, pkt->len);
1214 brcmu_pkt_buf_free_skb(pkt);
1215 /* free the pkt if canned one is not used */
1218 frame = (u8 *) (pkt->data);
1219 ASSERT(((unsigned long)frame % DHD_SDALIGN) == 0);
1223 frame = (u8 *) (pkt->data);
1225 ASSERT((pad + SDPCM_HDRLEN) <= (int)(pkt->len));
1226 memset(frame, 0, pad + SDPCM_HDRLEN);
1229 ASSERT(pad < DHD_SDALIGN);
1231 /* Hardware tag: 2 byte len followed by 2 byte ~len check (all LE) */
1232 len = (u16) (pkt->len);
1233 *(u16 *) frame = cpu_to_le16(len);
1234 *(((u16 *) frame) + 1) = cpu_to_le16(~len);
1236 /* Software tag: channel, sequence number, data offset */
1238 ((chan << SDPCM_CHANNEL_SHIFT) & SDPCM_CHANNEL_MASK) | bus->tx_seq |
1240 SDPCM_HDRLEN) << SDPCM_DOFFSET_SHIFT) & SDPCM_DOFFSET_MASK);
1242 put_unaligned_le32(swheader, frame + SDPCM_FRAMETAG_LEN);
1243 put_unaligned_le32(0, frame + SDPCM_FRAMETAG_LEN + sizeof(swheader));
1246 tx_packets[pkt->priority]++;
1247 if (DHD_BYTES_ON() &&
1248 (((DHD_CTL_ON() && (chan == SDPCM_CONTROL_CHANNEL)) ||
1249 (DHD_DATA_ON() && (chan != SDPCM_CONTROL_CHANNEL))))) {
1250 printk(KERN_DEBUG "Tx Frame:\n");
1251 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, frame, len);
1252 } else if (DHD_HDRS_ON()) {
1253 printk(KERN_DEBUG "TxHdr:\n");
1254 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
1255 frame, min_t(u16, len, 16));
1259 /* Raise len to next SDIO block to eliminate tail command */
1260 if (bus->roundup && bus->blocksize && (len > bus->blocksize)) {
1261 u16 pad = bus->blocksize - (len % bus->blocksize);
1262 if ((pad <= bus->roundup) && (pad < bus->blocksize))
1264 if (pad <= skb_tailroom(pkt))
1265 #endif /* NOTUSED */
1267 } else if (len % DHD_SDALIGN) {
1268 len += DHD_SDALIGN - (len % DHD_SDALIGN);
1271 /* Some controllers have trouble with odd bytes -- round to even */
1272 if (forcealign && (len & (ALIGNMENT - 1))) {
1274 if (skb_tailroom(pkt))
1276 len = roundup(len, ALIGNMENT);
1279 DHD_ERROR(("%s: sending unrounded %d-byte packet\n",
1285 ret = brcmf_sdbrcm_send_buf(bus, brcmf_sdcard_cur_sbwad(sdh),
1286 SDIO_FUNC_2, F2SYNC, frame, len, pkt, NULL, NULL);
1288 ASSERT(ret != -BCME_PENDING);
1291 /* On failure, abort the command
1292 and terminate the frame */
1293 DHD_INFO(("%s: sdio error %d, abort command and "
1294 "terminate frame.\n", __func__, ret));
1297 brcmf_sdcard_abort(sdh, SDIO_FUNC_2);
1298 brcmf_sdcard_cfg_write(sdh, SDIO_FUNC_1,
1299 SBSDIO_FUNC1_FRAMECTRL, SFC_WF_TERM,
1303 for (i = 0; i < 3; i++) {
1305 hi = brcmf_sdcard_cfg_read(sdh, SDIO_FUNC_1,
1306 SBSDIO_FUNC1_WFRAMEBCHI,
1308 lo = brcmf_sdcard_cfg_read(sdh, SDIO_FUNC_1,
1309 SBSDIO_FUNC1_WFRAMEBCLO,
1311 bus->f1regdata += 2;
1312 if ((hi == 0) && (lo == 0))
1318 bus->tx_seq = (bus->tx_seq + 1) % SDPCM_SEQUENCE_WRAP;
1320 } while ((ret < 0) && retrydata && retries++ < TXRETRIES);
1323 /* restore pkt buffer pointer before calling tx complete routine */
1324 skb_pull(pkt, SDPCM_HDRLEN + pad);
1325 brcmf_os_sdunlock(bus->dhd);
1326 brcmf_txcomplete(bus->dhd, pkt, ret != 0);
1327 brcmf_os_sdlock(bus->dhd);
1330 brcmu_pkt_buf_free_skb(pkt);
1335 int brcmf_sdbrcm_bus_txdata(struct dhd_bus *bus, struct sk_buff *pkt)
1340 DHD_TRACE(("%s: Enter\n", __func__));
1345 /* Push the test header if doing loopback */
1346 if (bus->ext_loop) {
1348 skb_push(pkt, SDPCM_TEST_HDRLEN);
1350 *data++ = SDPCM_TEST_ECHOREQ;
1351 *data++ = (u8) bus->loopid++;
1352 *data++ = (datalen >> 0);
1353 *data++ = (datalen >> 8);
1354 datalen += SDPCM_TEST_HDRLEN;
1358 /* Add space for the header */
1359 skb_push(pkt, SDPCM_HDRLEN);
1360 ASSERT(IS_ALIGNED((unsigned long)(pkt->data), 2));
1362 prec = PRIO2PREC((pkt->priority & PRIOMASK));
1364 /* Check for existing queue, current flow-control,
1365 pending event, or pending clock */
1366 if (brcmf_deferred_tx || bus->fcstate || pktq_len(&bus->txq)
1367 || bus->dpc_sched || (!DATAOK(bus))
1368 || (bus->flowcontrol & NBITVAL(prec))
1369 || (bus->clkstate != CLK_AVAIL)) {
1370 DHD_TRACE(("%s: deferring pktq len %d\n", __func__,
1371 pktq_len(&bus->txq)));
1374 /* Priority based enq */
1375 spin_lock_bh(&bus->txqlock);
1376 if (brcmf_c_prec_enq(bus->dhd, &bus->txq, pkt, prec) == false) {
1377 skb_pull(pkt, SDPCM_HDRLEN);
1378 brcmf_txcomplete(bus->dhd, pkt, false);
1379 brcmu_pkt_buf_free_skb(pkt);
1380 DHD_ERROR(("%s: out of bus->txq !!!\n", __func__));
1385 spin_unlock_bh(&bus->txqlock);
1387 if (pktq_len(&bus->txq) >= TXHI)
1388 brcmf_txflowcontrol(bus->dhd, 0, ON);
1391 if (pktq_plen(&bus->txq, prec) > qcount[prec])
1392 qcount[prec] = pktq_plen(&bus->txq, prec);
1394 /* Schedule DPC if needed to send queued packet(s) */
1395 if (brcmf_deferred_tx && !bus->dpc_sched) {
1396 bus->dpc_sched = true;
1397 brcmf_sched_dpc(bus->dhd);
1400 /* Lock: we're about to use shared data/code (and SDIO) */
1401 brcmf_os_sdlock(bus->dhd);
1403 /* Otherwise, send it now */
1405 /* Make sure back plane ht clk is on, no pending allowed */
1406 brcmf_sdbrcm_clkctl(bus, CLK_AVAIL, true);
1409 DHD_TRACE(("%s: calling txpkt\n", __func__));
1410 ret = brcmf_sdbrcm_txpkt(bus, pkt, SDPCM_DATA_CHANNEL, true);
1412 ret = brcmf_sdbrcm_txpkt(bus, pkt,
1413 (bus->ext_loop ? SDPCM_TEST_CHANNEL :
1414 SDPCM_DATA_CHANNEL), true);
1417 bus->dhd->tx_errors++;
1419 bus->dhd->dstats.tx_bytes += datalen;
1421 if ((bus->idletime == DHD_IDLE_IMMEDIATE) && !bus->dpc_sched) {
1422 bus->activity = false;
1423 brcmf_sdbrcm_clkctl(bus, CLK_NONE, true);
1426 brcmf_os_sdunlock(bus->dhd);
1432 static uint brcmf_sdbrcm_sendfromq(dhd_bus_t *bus, uint maxframes)
1434 struct sk_buff *pkt;
1437 int ret = 0, prec_out;
1442 dhd_pub_t *dhd = bus->dhd;
1443 struct sdpcmd_regs *regs = bus->regs;
1445 DHD_TRACE(("%s: Enter\n", __func__));
1447 tx_prec_map = ~bus->flowcontrol;
1449 /* Send frames until the limit or some other event */
1450 for (cnt = 0; (cnt < maxframes) && DATAOK(bus); cnt++) {
1451 spin_lock_bh(&bus->txqlock);
1452 pkt = brcmu_pktq_mdeq(&bus->txq, tx_prec_map, &prec_out);
1454 spin_unlock_bh(&bus->txqlock);
1457 spin_unlock_bh(&bus->txqlock);
1458 datalen = pkt->len - SDPCM_HDRLEN;
1461 ret = brcmf_sdbrcm_txpkt(bus, pkt, SDPCM_DATA_CHANNEL, true);
1463 ret = brcmf_sdbrcm_txpkt(bus, pkt,
1464 (bus->ext_loop ? SDPCM_TEST_CHANNEL :
1465 SDPCM_DATA_CHANNEL), true);
1468 bus->dhd->tx_errors++;
1470 bus->dhd->dstats.tx_bytes += datalen;
1472 /* In poll mode, need to check for other events */
1473 if (!bus->intr && cnt) {
1474 /* Check device status, signal pending interrupt */
1475 R_SDREG(intstatus, ®s->intstatus, retries);
1477 if (brcmf_sdcard_regfail(bus->sdh))
1479 if (intstatus & bus->hostintmask)
1484 /* Deflow-control stack if needed */
1485 if (dhd->up && (dhd->busstate == DHD_BUS_DATA) &&
1486 dhd->txoff && (pktq_len(&bus->txq) < TXLOW))
1487 brcmf_txflowcontrol(dhd, 0, OFF);
1493 brcmf_sdbrcm_bus_txctl(struct dhd_bus *bus, unsigned char *msg, uint msglen)
1499 struct brcmf_sdio *sdh = bus->sdh;
1504 DHD_TRACE(("%s: Enter\n", __func__));
1506 if (bus->dhd->dongle_reset)
1509 /* Back the pointer to make a room for bus header */
1510 frame = msg - SDPCM_HDRLEN;
1511 len = (msglen += SDPCM_HDRLEN);
1513 /* Add alignment padding (optional for ctl frames) */
1515 doff = ((unsigned long)frame % DHD_SDALIGN);
1520 memset(frame, 0, doff + SDPCM_HDRLEN);
1522 ASSERT(doff < DHD_SDALIGN);
1524 doff += SDPCM_HDRLEN;
1526 /* Round send length to next SDIO block */
1527 if (bus->roundup && bus->blocksize && (len > bus->blocksize)) {
1528 u16 pad = bus->blocksize - (len % bus->blocksize);
1529 if ((pad <= bus->roundup) && (pad < bus->blocksize))
1531 } else if (len % DHD_SDALIGN) {
1532 len += DHD_SDALIGN - (len % DHD_SDALIGN);
1535 /* Satisfy length-alignment requirements */
1536 if (forcealign && (len & (ALIGNMENT - 1)))
1537 len = roundup(len, ALIGNMENT);
1539 ASSERT(IS_ALIGNED((unsigned long)frame, 2));
1541 /* Need to lock here to protect txseq and SDIO tx calls */
1542 brcmf_os_sdlock(bus->dhd);
1546 /* Make sure backplane clock is on */
1547 brcmf_sdbrcm_clkctl(bus, CLK_AVAIL, false);
1549 /* Hardware tag: 2 byte len followed by 2 byte ~len check (all LE) */
1550 *(u16 *) frame = cpu_to_le16((u16) msglen);
1551 *(((u16 *) frame) + 1) = cpu_to_le16(~msglen);
1553 /* Software tag: channel, sequence number, data offset */
1555 ((SDPCM_CONTROL_CHANNEL << SDPCM_CHANNEL_SHIFT) &
1557 | bus->tx_seq | ((doff << SDPCM_DOFFSET_SHIFT) &
1558 SDPCM_DOFFSET_MASK);
1559 put_unaligned_le32(swheader, frame + SDPCM_FRAMETAG_LEN);
1560 put_unaligned_le32(0, frame + SDPCM_FRAMETAG_LEN + sizeof(swheader));
1563 DHD_INFO(("%s: No bus credit bus->tx_max %d, bus->tx_seq %d\n",
1564 __func__, bus->tx_max, bus->tx_seq));
1565 bus->ctrl_frame_stat = true;
1567 bus->ctrl_frame_buf = frame;
1568 bus->ctrl_frame_len = len;
1570 brcmf_wait_for_event(bus->dhd, &bus->ctrl_frame_stat);
1572 if (bus->ctrl_frame_stat == false) {
1573 DHD_INFO(("%s: ctrl_frame_stat == false\n", __func__));
1576 DHD_INFO(("%s: ctrl_frame_stat == true\n", __func__));
1583 if (DHD_BYTES_ON() && DHD_CTL_ON()) {
1584 printk(KERN_DEBUG "Tx Frame:\n");
1585 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
1587 } else if (DHD_HDRS_ON()) {
1588 printk(KERN_DEBUG "TxHdr:\n");
1589 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
1590 frame, min_t(u16, len, 16));
1595 bus->ctrl_frame_stat = false;
1596 ret = brcmf_sdbrcm_send_buf(bus,
1597 brcmf_sdcard_cur_sbwad(sdh), SDIO_FUNC_2,
1598 F2SYNC, frame, len, NULL, NULL, NULL);
1600 ASSERT(ret != -BCME_PENDING);
1603 /* On failure, abort the command and
1604 terminate the frame */
1605 DHD_INFO(("%s: sdio error %d, abort command and terminate frame.\n",
1609 brcmf_sdcard_abort(sdh, SDIO_FUNC_2);
1611 brcmf_sdcard_cfg_write(sdh, SDIO_FUNC_1,
1612 SBSDIO_FUNC1_FRAMECTRL,
1616 for (i = 0; i < 3; i++) {
1618 hi = brcmf_sdcard_cfg_read(sdh,
1620 SBSDIO_FUNC1_WFRAMEBCHI,
1622 lo = brcmf_sdcard_cfg_read(sdh,
1624 SBSDIO_FUNC1_WFRAMEBCLO,
1626 bus->f1regdata += 2;
1627 if ((hi == 0) && (lo == 0))
1634 (bus->tx_seq + 1) % SDPCM_SEQUENCE_WRAP;
1636 } while ((ret < 0) && retries++ < TXRETRIES);
1639 if ((bus->idletime == DHD_IDLE_IMMEDIATE) && !bus->dpc_sched) {
1640 bus->activity = false;
1641 brcmf_sdbrcm_clkctl(bus, CLK_NONE, true);
1644 brcmf_os_sdunlock(bus->dhd);
1647 bus->dhd->tx_ctlerrs++;
1649 bus->dhd->tx_ctlpkts++;
1651 return ret ? -EIO : 0;
1654 int brcmf_sdbrcm_bus_rxctl(struct dhd_bus *bus, unsigned char *msg, uint msglen)
1660 DHD_TRACE(("%s: Enter\n", __func__));
1662 if (bus->dhd->dongle_reset)
1665 /* Wait until control frame is available */
1666 timeleft = brcmf_os_ioctl_resp_wait(bus->dhd, &bus->rxlen, &pending);
1668 brcmf_os_sdlock(bus->dhd);
1670 memcpy(msg, bus->rxctl, min(msglen, rxlen));
1672 brcmf_os_sdunlock(bus->dhd);
1675 DHD_CTL(("%s: resumed on rxctl frame, got %d expected %d\n",
1676 __func__, rxlen, msglen));
1677 } else if (timeleft == 0) {
1678 DHD_ERROR(("%s: resumed on timeout\n", __func__));
1680 brcmf_os_sdlock(bus->dhd);
1681 brcmf_sdbrcm_checkdied(bus, NULL, 0);
1682 brcmf_os_sdunlock(bus->dhd);
1683 #endif /* DHD_DEBUG */
1684 } else if (pending == true) {
1685 DHD_CTL(("%s: cancelled\n", __func__));
1686 return -ERESTARTSYS;
1688 DHD_CTL(("%s: resumed for unknown reason?\n", __func__));
1690 brcmf_os_sdlock(bus->dhd);
1691 brcmf_sdbrcm_checkdied(bus, NULL, 0);
1692 brcmf_os_sdunlock(bus->dhd);
1693 #endif /* DHD_DEBUG */
1697 bus->dhd->rx_ctlpkts++;
1699 bus->dhd->rx_ctlerrs++;
1701 return rxlen ? (int)rxlen : -ETIMEDOUT;
1740 const struct brcmu_iovar dhdsdio_iovars[] = {
1741 {"intr", IOV_INTR, 0, IOVT_BOOL, 0},
1742 {"sleep", IOV_SLEEP, 0, IOVT_BOOL, 0},
1743 {"pollrate", IOV_POLLRATE, 0, IOVT_UINT32, 0},
1744 {"idletime", IOV_IDLETIME, 0, IOVT_INT32, 0},
1745 {"idleclock", IOV_IDLECLOCK, 0, IOVT_INT32, 0},
1746 {"sd1idle", IOV_SD1IDLE, 0, IOVT_BOOL, 0},
1747 {"membytes", IOV_MEMBYTES, 0, IOVT_BUFFER, 2 * sizeof(int)},
1748 {"memsize", IOV_MEMSIZE, 0, IOVT_UINT32, 0},
1749 {"download", IOV_DOWNLOAD, 0, IOVT_BOOL, 0},
1750 {"vars", IOV_VARS, 0, IOVT_BUFFER, 0},
1751 {"sdiod_drive", IOV_SDIOD_DRIVE, 0, IOVT_UINT32, 0},
1752 {"readahead", IOV_READAHEAD, 0, IOVT_BOOL, 0},
1753 {"sdrxchain", IOV_SDRXCHAIN, 0, IOVT_BOOL, 0},
1754 {"alignctl", IOV_ALIGNCTL, 0, IOVT_BOOL, 0},
1755 {"sdalign", IOV_SDALIGN, 0, IOVT_BOOL, 0},
1756 {"devreset", IOV_DEVRESET, 0, IOVT_BOOL, 0},
1758 {"sdreg", IOV_SDREG, 0, IOVT_BUFFER, sizeof(sdreg_t)}
1760 {"sbreg", IOV_SBREG, 0, IOVT_BUFFER, sizeof(sdreg_t)}
1762 {"sd_cis", IOV_SDCIS, 0, IOVT_BUFFER, DHD_IOCTL_MAXLEN}
1764 {"forcealign", IOV_FORCEEVEN, 0, IOVT_BOOL, 0}
1766 {"txbound", IOV_TXBOUND, 0, IOVT_UINT32, 0}
1768 {"rxbound", IOV_RXBOUND, 0, IOVT_UINT32, 0}
1770 {"txminmax", IOV_TXMINMAX, 0, IOVT_UINT32, 0}
1772 {"cpu", IOV_CPU, 0, IOVT_BOOL, 0}
1775 {"checkdied", IOV_CHECKDIED, 0, IOVT_BUFFER, 0}
1777 #endif /* DHD_DEBUG */
1778 #endif /* DHD_DEBUG */
1780 {"extloop", IOV_EXTLOOP, 0, IOVT_BOOL, 0}
1782 {"pktgen", IOV_PKTGEN, 0, IOVT_BUFFER, sizeof(brcmf_pktgen_t)}
1790 dhd_dump_pct(struct brcmu_strbuf *strbuf, char *desc, uint num, uint div)
1795 brcmu_bprintf(strbuf, "%s N/A", desc);
1798 q2 = (100 * (num - (q1 * div))) / div;
1799 brcmu_bprintf(strbuf, "%s %d.%02d", desc, q1, q2);
1803 void brcmf_sdbrcm_bus_dump(dhd_pub_t *dhdp, struct brcmu_strbuf *strbuf)
1805 dhd_bus_t *bus = dhdp->bus;
1807 brcmu_bprintf(strbuf, "Bus SDIO structure:\n");
1808 brcmu_bprintf(strbuf,
1809 "hostintmask 0x%08x intstatus 0x%08x sdpcm_ver %d\n",
1810 bus->hostintmask, bus->intstatus, bus->sdpcm_ver);
1811 brcmu_bprintf(strbuf,
1812 "fcstate %d qlen %d tx_seq %d, max %d, rxskip %d rxlen %d rx_seq %d\n",
1813 bus->fcstate, pktq_len(&bus->txq), bus->tx_seq, bus->tx_max,
1814 bus->rxskip, bus->rxlen, bus->rx_seq);
1815 brcmu_bprintf(strbuf, "intr %d intrcount %d lastintrs %d spurious %d\n",
1816 bus->intr, bus->intrcount, bus->lastintrs, bus->spurious);
1817 brcmu_bprintf(strbuf, "pollrate %d pollcnt %d regfails %d\n",
1818 bus->pollrate, bus->pollcnt, bus->regfails);
1820 brcmu_bprintf(strbuf, "\nAdditional counters:\n");
1821 brcmu_bprintf(strbuf,
1822 "tx_sderrs %d fcqueued %d rxrtx %d rx_toolong %d rxc_errors %d\n",
1823 bus->tx_sderrs, bus->fcqueued, bus->rxrtx, bus->rx_toolong,
1825 brcmu_bprintf(strbuf, "rx_hdrfail %d badhdr %d badseq %d\n",
1826 bus->rx_hdrfail, bus->rx_badhdr, bus->rx_badseq);
1827 brcmu_bprintf(strbuf, "fc_rcvd %d, fc_xoff %d, fc_xon %d\n",
1828 bus->fc_rcvd, bus->fc_xoff, bus->fc_xon);
1829 brcmu_bprintf(strbuf, "rxglomfail %d, rxglomframes %d, rxglompkts %d\n",
1830 bus->rxglomfail, bus->rxglomframes, bus->rxglompkts);
1831 brcmu_bprintf(strbuf, "f2rx (hdrs/data) %d (%d/%d), f2tx %d f1regs"
1833 (bus->f2rxhdrs + bus->f2rxdata), bus->f2rxhdrs,
1834 bus->f2rxdata, bus->f2txdata, bus->f1regdata);
1836 dhd_dump_pct(strbuf, "\nRx: pkts/f2rd", bus->dhd->rx_packets,
1837 (bus->f2rxhdrs + bus->f2rxdata));
1838 dhd_dump_pct(strbuf, ", pkts/f1sd", bus->dhd->rx_packets,
1840 dhd_dump_pct(strbuf, ", pkts/sd", bus->dhd->rx_packets,
1841 (bus->f2rxhdrs + bus->f2rxdata + bus->f1regdata));
1842 dhd_dump_pct(strbuf, ", pkts/int", bus->dhd->rx_packets,
1844 brcmu_bprintf(strbuf, "\n");
1846 dhd_dump_pct(strbuf, "Rx: glom pct", (100 * bus->rxglompkts),
1847 bus->dhd->rx_packets);
1848 dhd_dump_pct(strbuf, ", pkts/glom", bus->rxglompkts,
1850 brcmu_bprintf(strbuf, "\n");
1852 dhd_dump_pct(strbuf, "Tx: pkts/f2wr", bus->dhd->tx_packets,
1854 dhd_dump_pct(strbuf, ", pkts/f1sd", bus->dhd->tx_packets,
1856 dhd_dump_pct(strbuf, ", pkts/sd", bus->dhd->tx_packets,
1857 (bus->f2txdata + bus->f1regdata));
1858 dhd_dump_pct(strbuf, ", pkts/int", bus->dhd->tx_packets,
1860 brcmu_bprintf(strbuf, "\n");
1862 dhd_dump_pct(strbuf, "Total: pkts/f2rw",
1863 (bus->dhd->tx_packets + bus->dhd->rx_packets),
1864 (bus->f2txdata + bus->f2rxhdrs + bus->f2rxdata));
1865 dhd_dump_pct(strbuf, ", pkts/f1sd",
1866 (bus->dhd->tx_packets + bus->dhd->rx_packets),
1868 dhd_dump_pct(strbuf, ", pkts/sd",
1869 (bus->dhd->tx_packets + bus->dhd->rx_packets),
1870 (bus->f2txdata + bus->f2rxhdrs + bus->f2rxdata +
1872 dhd_dump_pct(strbuf, ", pkts/int",
1873 (bus->dhd->tx_packets + bus->dhd->rx_packets),
1875 brcmu_bprintf(strbuf, "\n\n");
1879 if (bus->pktgen_count) {
1880 brcmu_bprintf(strbuf, "pktgen config and count:\n");
1881 brcmu_bprintf(strbuf,
1882 "freq %d count %d print %d total %d min %d len %d\n",
1883 bus->pktgen_freq, bus->pktgen_count,
1884 bus->pktgen_print, bus->pktgen_total,
1885 bus->pktgen_minlen, bus->pktgen_maxlen);
1886 brcmu_bprintf(strbuf, "send attempts %d rcvd %d fail %d\n",
1887 bus->pktgen_sent, bus->pktgen_rcvd,
1892 brcmu_bprintf(strbuf, "dpc_sched %d host interrupt%spending\n",
1894 (brcmf_sdcard_intr_pending(bus->sdh) ? " " : " not "));
1895 brcmu_bprintf(strbuf, "blocksize %d roundup %d\n", bus->blocksize,
1897 #endif /* DHD_DEBUG */
1898 brcmu_bprintf(strbuf,
1899 "clkstate %d activity %d idletime %d idlecount %d sleeping %d\n",
1900 bus->clkstate, bus->activity, bus->idletime, bus->idlecount,
1904 void dhd_bus_clearcounts(dhd_pub_t *dhdp)
1906 dhd_bus_t *bus = (dhd_bus_t *) dhdp->bus;
1908 bus->intrcount = bus->lastintrs = bus->spurious = bus->regfails = 0;
1909 bus->rxrtx = bus->rx_toolong = bus->rxc_errors = 0;
1910 bus->rx_hdrfail = bus->rx_badhdr = bus->rx_badseq = 0;
1911 bus->tx_sderrs = bus->fc_rcvd = bus->fc_xoff = bus->fc_xon = 0;
1912 bus->rxglomfail = bus->rxglomframes = bus->rxglompkts = 0;
1913 bus->f2rxhdrs = bus->f2rxdata = bus->f2txdata = bus->f1regdata = 0;
1917 static int brcmf_sdbrcm_pktgen_get(dhd_bus_t *bus, u8 *arg)
1919 brcmf_pktgen_t pktgen;
1921 pktgen.version = DHD_PKTGEN_VERSION;
1922 pktgen.freq = bus->pktgen_freq;
1923 pktgen.count = bus->pktgen_count;
1924 pktgen.print = bus->pktgen_print;
1925 pktgen.total = bus->pktgen_total;
1926 pktgen.minlen = bus->pktgen_minlen;
1927 pktgen.maxlen = bus->pktgen_maxlen;
1928 pktgen.numsent = bus->pktgen_sent;
1929 pktgen.numrcvd = bus->pktgen_rcvd;
1930 pktgen.numfail = bus->pktgen_fail;
1931 pktgen.mode = bus->pktgen_mode;
1932 pktgen.stop = bus->pktgen_stop;
1934 memcpy(arg, &pktgen, sizeof(pktgen));
1939 static int brcmf_sdbrcm_pktgen_set(dhd_bus_t *bus, u8 *arg)
1941 brcmf_pktgen_t pktgen;
1942 uint oldcnt, oldmode;
1944 memcpy(&pktgen, arg, sizeof(pktgen));
1945 if (pktgen.version != DHD_PKTGEN_VERSION)
1948 oldcnt = bus->pktgen_count;
1949 oldmode = bus->pktgen_mode;
1951 bus->pktgen_freq = pktgen.freq;
1952 bus->pktgen_count = pktgen.count;
1953 bus->pktgen_print = pktgen.print;
1954 bus->pktgen_total = pktgen.total;
1955 bus->pktgen_minlen = pktgen.minlen;
1956 bus->pktgen_maxlen = pktgen.maxlen;
1957 bus->pktgen_mode = pktgen.mode;
1958 bus->pktgen_stop = pktgen.stop;
1960 bus->pktgen_tick = bus->pktgen_ptick = 0;
1961 bus->pktgen_len = max(bus->pktgen_len, bus->pktgen_minlen);
1962 bus->pktgen_len = min(bus->pktgen_len, bus->pktgen_maxlen);
1964 /* Clear counts for a new pktgen (mode change, or was stopped) */
1965 if (bus->pktgen_count && (!oldcnt || oldmode != bus->pktgen_mode))
1966 bus->pktgen_sent = bus->pktgen_rcvd = bus->pktgen_fail = 0;
1973 brcmf_sdbrcm_membytes(dhd_bus_t *bus, bool write, u32 address, u8 *data,
1980 /* Determine initial transfer parameters */
1981 sdaddr = address & SBSDIO_SB_OFT_ADDR_MASK;
1982 if ((sdaddr + size) & SBSDIO_SBWINDOW_MASK)
1983 dsize = (SBSDIO_SB_OFT_ADDR_LIMIT - sdaddr);
1987 /* Set the backplane window to include the start address */
1988 bcmerror = brcmf_sdbrcm_set_siaddr_window(bus, address);
1990 DHD_ERROR(("%s: window change failed\n", __func__));
1994 /* Do the transfer(s) */
1996 DHD_INFO(("%s: %s %d bytes at offset 0x%08x in window 0x%08x\n",
1997 __func__, (write ? "write" : "read"), dsize,
1998 sdaddr, (address & SBSDIO_SBWINDOW_MASK)));
2000 brcmf_sdcard_rwdata(bus->sdh, write, sdaddr, data, dsize);
2002 DHD_ERROR(("%s: membytes transfer failed\n", __func__));
2006 /* Adjust for next transfer (if any) */
2011 bcmerror = brcmf_sdbrcm_set_siaddr_window(bus, address);
2013 DHD_ERROR(("%s: window change failed\n",
2018 dsize = min_t(uint, SBSDIO_SB_OFT_ADDR_LIMIT, size);
2023 /* Return the window to backplane enumeration space for core access */
2024 if (brcmf_sdbrcm_set_siaddr_window(bus,
2025 brcmf_sdcard_cur_sbwad(bus->sdh))) {
2026 DHD_ERROR(("%s: FAILED to set window back to 0x%x\n",
2027 __func__, brcmf_sdcard_cur_sbwad(bus->sdh)));
2034 static int brcmf_sdbrcm_readshared(dhd_bus_t *bus, struct sdpcm_shared *sh)
2039 /* Read last word in memory to determine address of
2040 sdpcm_shared structure */
2041 rv = brcmf_sdbrcm_membytes(bus, false, bus->ramsize - 4, (u8 *)&addr,
2046 addr = le32_to_cpu(addr);
2048 DHD_INFO(("sdpcm_shared address 0x%08X\n", addr));
2051 * Check if addr is valid.
2052 * NVRAM length at the end of memory should have been overwritten.
2054 if (addr == 0 || ((~addr >> 16) & 0xffff) == (addr & 0xffff)) {
2055 DHD_ERROR(("%s: address (0x%08x) of sdpcm_shared invalid\n",
2060 /* Read rte_shared structure */
2061 rv = brcmf_sdbrcm_membytes(bus, false, addr, (u8 *) sh,
2062 sizeof(struct sdpcm_shared));
2067 sh->flags = le32_to_cpu(sh->flags);
2068 sh->trap_addr = le32_to_cpu(sh->trap_addr);
2069 sh->assert_exp_addr = le32_to_cpu(sh->assert_exp_addr);
2070 sh->assert_file_addr = le32_to_cpu(sh->assert_file_addr);
2071 sh->assert_line = le32_to_cpu(sh->assert_line);
2072 sh->console_addr = le32_to_cpu(sh->console_addr);
2073 sh->msgtrace_addr = le32_to_cpu(sh->msgtrace_addr);
2075 if ((sh->flags & SDPCM_SHARED_VERSION_MASK) != SDPCM_SHARED_VERSION) {
2076 DHD_ERROR(("%s: sdpcm_shared version %d in dhd "
2077 "is different than sdpcm_shared version %d in dongle\n",
2078 __func__, SDPCM_SHARED_VERSION,
2079 sh->flags & SDPCM_SHARED_VERSION_MASK));
2086 static int brcmf_sdbrcm_checkdied(dhd_bus_t *bus, u8 *data, uint size)
2090 char *mbuffer = NULL;
2091 uint maxstrlen = 256;
2094 struct sdpcm_shared sdpcm_shared;
2095 struct brcmu_strbuf strbuf;
2097 DHD_TRACE(("%s: Enter\n", __func__));
2101 * Called after a rx ctrl timeout. "data" is NULL.
2102 * allocate memory to trace the trap or assert.
2105 mbuffer = data = kmalloc(msize, GFP_ATOMIC);
2106 if (mbuffer == NULL) {
2107 DHD_ERROR(("%s: kmalloc(%d) failed\n", __func__,
2114 str = kmalloc(maxstrlen, GFP_ATOMIC);
2116 DHD_ERROR(("%s: kmalloc(%d) failed\n", __func__, maxstrlen));
2121 bcmerror = brcmf_sdbrcm_readshared(bus, &sdpcm_shared);
2125 brcmu_binit(&strbuf, data, size);
2127 brcmu_bprintf(&strbuf,
2128 "msgtrace address : 0x%08X\nconsole address : 0x%08X\n",
2129 sdpcm_shared.msgtrace_addr, sdpcm_shared.console_addr);
2131 if ((sdpcm_shared.flags & SDPCM_SHARED_ASSERT_BUILT) == 0) {
2132 /* NOTE: Misspelled assert is intentional - DO NOT FIX.
2133 * (Avoids conflict with real asserts for programmatic
2134 * parsing of output.)
2136 brcmu_bprintf(&strbuf, "Assrt not built in dongle\n");
2139 if ((sdpcm_shared.flags & (SDPCM_SHARED_ASSERT | SDPCM_SHARED_TRAP)) ==
2141 /* NOTE: Misspelled assert is intentional - DO NOT FIX.
2142 * (Avoids conflict with real asserts for programmatic
2143 * parsing of output.)
2145 brcmu_bprintf(&strbuf, "No trap%s in dongle",
2146 (sdpcm_shared.flags & SDPCM_SHARED_ASSERT_BUILT)
2149 if (sdpcm_shared.flags & SDPCM_SHARED_ASSERT) {
2150 /* Download assert */
2151 brcmu_bprintf(&strbuf, "Dongle assert");
2152 if (sdpcm_shared.assert_exp_addr != 0) {
2154 bcmerror = brcmf_sdbrcm_membytes(bus, false,
2155 sdpcm_shared.assert_exp_addr,
2156 (u8 *) str, maxstrlen);
2160 str[maxstrlen - 1] = '\0';
2161 brcmu_bprintf(&strbuf, " expr \"%s\"", str);
2164 if (sdpcm_shared.assert_file_addr != 0) {
2166 bcmerror = brcmf_sdbrcm_membytes(bus, false,
2167 sdpcm_shared.assert_file_addr,
2168 (u8 *) str, maxstrlen);
2172 str[maxstrlen - 1] = '\0';
2173 brcmu_bprintf(&strbuf, " file \"%s\"", str);
2176 brcmu_bprintf(&strbuf, " line %d ",
2177 sdpcm_shared.assert_line);
2180 if (sdpcm_shared.flags & SDPCM_SHARED_TRAP) {
2181 bcmerror = brcmf_sdbrcm_membytes(bus, false,
2182 sdpcm_shared.trap_addr, (u8 *)&tr,
2187 brcmu_bprintf(&strbuf,
2188 "Dongle trap type 0x%x @ epc 0x%x, cpsr 0x%x, spsr 0x%x, sp 0x%x,"
2189 "lp 0x%x, rpc 0x%x Trap offset 0x%x, "
2190 "r0 0x%x, r1 0x%x, r2 0x%x, r3 0x%x, r4 0x%x, r5 0x%x, r6 0x%x, r7 0x%x\n",
2191 tr.type, tr.epc, tr.cpsr, tr.spsr, tr.r13,
2192 tr.r14, tr.pc, sdpcm_shared.trap_addr,
2193 tr.r0, tr.r1, tr.r2, tr.r3, tr.r4, tr.r5,
2198 if (sdpcm_shared.flags & (SDPCM_SHARED_ASSERT | SDPCM_SHARED_TRAP))
2199 DHD_ERROR(("%s: %s\n", __func__, strbuf.origbuf));
2202 if (sdpcm_shared.flags & SDPCM_SHARED_TRAP) {
2203 /* Mem dump to a file on device */
2204 brcmf_sdbrcm_mem_dump(bus);
2206 #endif /* DHD_DEBUG */
2215 static int brcmf_sdbrcm_mem_dump(dhd_bus_t *bus)
2218 int size; /* Full mem size */
2219 int start = 0; /* Start address */
2220 int read_size = 0; /* Read size of each iteration */
2221 u8 *buf = NULL, *databuf = NULL;
2223 /* Get full mem size */
2224 size = bus->ramsize;
2225 buf = kmalloc(size, GFP_ATOMIC);
2227 DHD_ERROR(("%s: Out of memory (%d bytes)\n", __func__, size));
2231 /* Read mem content */
2232 printk(KERN_DEBUG "Dump dongle memory");
2235 read_size = min(MEMBLOCK, size);
2236 ret = brcmf_sdbrcm_membytes(bus, false, start, databuf,
2239 DHD_ERROR(("%s: Error membytes %d\n", __func__, ret));
2245 /* Decrement size and increment start address */
2248 databuf += read_size;
2250 printk(KERN_DEBUG "Done\n");
2252 /* free buf before return !!! */
2253 if (brcmf_write_to_file(bus->dhd, buf, bus->ramsize)) {
2254 DHD_ERROR(("%s: Error writing to files\n", __func__));
2258 /* buf free handled in brcmf_write_to_file, not here */
2262 #define CONSOLE_LINE_MAX 192
2264 static int brcmf_sdbrcm_readconsole(dhd_bus_t *bus)
2266 dhd_console_t *c = &bus->console;
2267 u8 line[CONSOLE_LINE_MAX], ch;
2271 /* Don't do anything until FWREADY updates console address */
2272 if (bus->console_addr == 0)
2275 /* Read console log struct */
2276 addr = bus->console_addr + offsetof(rte_cons_t, log);
2277 rv = brcmf_sdbrcm_membytes(bus, false, addr, (u8 *)&c->log,
2282 /* Allocate console buffer (one time only) */
2283 if (c->buf == NULL) {
2284 c->bufsize = le32_to_cpu(c->log.buf_size);
2285 c->buf = kmalloc(c->bufsize, GFP_ATOMIC);
2290 idx = le32_to_cpu(c->log.idx);
2292 /* Protect against corrupt value */
2293 if (idx > c->bufsize)
2296 /* Skip reading the console buffer if the index pointer
2301 /* Read the console buffer */
2302 addr = le32_to_cpu(c->log.buf);
2303 rv = brcmf_sdbrcm_membytes(bus, false, addr, c->buf, c->bufsize);
2307 while (c->last != idx) {
2308 for (n = 0; n < CONSOLE_LINE_MAX - 2; n++) {
2309 if (c->last == idx) {
2310 /* This would output a partial line.
2312 * the buffer pointer and output this
2313 * line next time around.
2318 c->last = c->bufsize - n;
2321 ch = c->buf[c->last];
2322 c->last = (c->last + 1) % c->bufsize;
2329 if (line[n - 1] == '\r')
2332 printk(KERN_DEBUG "CONSOLE: %s\n", line);
2339 #endif /* DHD_DEBUG */
2341 int brcmf_sdbrcm_downloadvars(dhd_bus_t *bus, void *arg, int len)
2345 DHD_TRACE(("%s: Enter\n", __func__));
2347 /* Basic sanity checks */
2349 bcmerror = -EISCONN;
2353 bcmerror = -EOVERFLOW;
2357 /* Free the old ones and replace with passed variables */
2360 bus->vars = kmalloc(len, GFP_ATOMIC);
2361 bus->varsz = bus->vars ? len : 0;
2362 if (bus->vars == NULL) {
2367 /* Copy the passed variables, which should include the
2368 terminating double-null */
2369 memcpy(bus->vars, arg, bus->varsz);
2375 brcmf_sdbrcm_doiovar(dhd_bus_t *bus, const struct brcmu_iovar *vi, u32 actionid,
2376 const char *name, void *params, int plen, void *arg, int len,
2383 DHD_TRACE(("%s: Enter, action %d name %s params %p plen %d arg %p "
2384 "len %d val_size %d\n",
2385 __func__, actionid, name, params, plen, arg, len, val_size));
2387 bcmerror = brcmu_iovar_lencheck(vi, arg, len, IOV_ISSET(actionid));
2391 if (plen >= (int)sizeof(int_val))
2392 memcpy(&int_val, params, sizeof(int_val));
2394 bool_val = (int_val != 0) ? true : false;
2396 /* Some ioctls use the bus */
2397 brcmf_os_sdlock(bus->dhd);
2399 /* Check if dongle is in reset. If so, only allow DEVRESET iovars */
2400 if (bus->dhd->dongle_reset && !(actionid == IOV_SVAL(IOV_DEVRESET) ||
2401 actionid == IOV_GVAL(IOV_DEVRESET))) {
2406 /* Handle sleep stuff before any clock mucking */
2407 if (vi->varid == IOV_SLEEP) {
2408 if (IOV_ISSET(actionid)) {
2409 bcmerror = brcmf_sdbrcm_bussleep(bus, bool_val);
2411 int_val = (s32) bus->sleeping;
2412 memcpy(arg, &int_val, val_size);
2417 /* Request clock to allow SDIO accesses */
2418 if (!bus->dhd->dongle_reset) {
2420 brcmf_sdbrcm_clkctl(bus, CLK_AVAIL, false);
2424 case IOV_GVAL(IOV_INTR):
2425 int_val = (s32) bus->intr;
2426 memcpy(arg, &int_val, val_size);
2429 case IOV_SVAL(IOV_INTR):
2430 bus->intr = bool_val;
2431 bus->intdis = false;
2434 DHD_INTR(("%s: enable SDIO device interrupts\n",
2436 brcmf_sdcard_intr_enable(bus->sdh);
2438 DHD_INTR(("%s: disable SDIO interrupts\n",
2440 brcmf_sdcard_intr_disable(bus->sdh);
2445 case IOV_GVAL(IOV_POLLRATE):
2446 int_val = (s32) bus->pollrate;
2447 memcpy(arg, &int_val, val_size);
2450 case IOV_SVAL(IOV_POLLRATE):
2451 bus->pollrate = (uint) int_val;
2452 bus->poll = (bus->pollrate != 0);
2455 case IOV_GVAL(IOV_IDLETIME):
2456 int_val = bus->idletime;
2457 memcpy(arg, &int_val, val_size);
2460 case IOV_SVAL(IOV_IDLETIME):
2461 if ((int_val < 0) && (int_val != DHD_IDLE_IMMEDIATE))
2464 bus->idletime = int_val;
2467 case IOV_GVAL(IOV_IDLECLOCK):
2468 int_val = (s32) bus->idleclock;
2469 memcpy(arg, &int_val, val_size);
2472 case IOV_SVAL(IOV_IDLECLOCK):
2473 bus->idleclock = int_val;
2476 case IOV_GVAL(IOV_SD1IDLE):
2477 int_val = (s32) sd1idle;
2478 memcpy(arg, &int_val, val_size);
2481 case IOV_SVAL(IOV_SD1IDLE):
2485 case IOV_SVAL(IOV_MEMBYTES):
2486 case IOV_GVAL(IOV_MEMBYTES):
2492 bool set = (actionid == IOV_SVAL(IOV_MEMBYTES));
2494 ASSERT(plen >= 2 * sizeof(int));
2496 address = (u32) int_val;
2497 memcpy(&int_val, (char *)params + sizeof(int_val),
2499 size = (uint) int_val;
2501 /* Do some validation */
2502 dsize = set ? plen - (2 * sizeof(int)) : len;
2504 DHD_ERROR(("%s: error on %s membytes, addr "
2505 "0x%08x size %d dsize %d\n",
2506 __func__, (set ? "set" : "get"),
2507 address, size, dsize));
2512 DHD_INFO(("%s: Request to %s %d bytes at address "
2514 __func__, (set ? "write" : "read"), size, address));
2516 /* If we know about SOCRAM, check for a fit */
2517 if ((bus->orig_ramsize) &&
2518 ((address > bus->orig_ramsize)
2519 || (address + size > bus->orig_ramsize))) {
2520 DHD_ERROR(("%s: ramsize 0x%08x doesn't have %d "
2521 "bytes at 0x%08x\n",
2522 __func__, bus->orig_ramsize, size, address));
2527 /* Generate the actual data pointer */
2529 set ? (u8 *) params +
2530 2 * sizeof(int) : (u8 *) arg;
2532 /* Call to do the transfer */
2533 bcmerror = brcmf_sdbrcm_membytes(bus, set, address,
2539 case IOV_GVAL(IOV_MEMSIZE):
2540 int_val = (s32) bus->ramsize;
2541 memcpy(arg, &int_val, val_size);
2544 case IOV_GVAL(IOV_SDIOD_DRIVE):
2545 int_val = (s32) brcmf_sdiod_drive_strength;
2546 memcpy(arg, &int_val, val_size);
2549 case IOV_SVAL(IOV_SDIOD_DRIVE):
2550 brcmf_sdiod_drive_strength = int_val;
2551 brcmf_sdbrcm_sdiod_drive_strength_init(bus,
2552 brcmf_sdiod_drive_strength);
2555 case IOV_SVAL(IOV_DOWNLOAD):
2556 bcmerror = brcmf_sdbrcm_download_state(bus, bool_val);
2559 case IOV_SVAL(IOV_VARS):
2560 bcmerror = brcmf_sdbrcm_downloadvars(bus, arg, len);
2563 case IOV_GVAL(IOV_READAHEAD):
2564 int_val = (s32) dhd_readahead;
2565 memcpy(arg, &int_val, val_size);
2568 case IOV_SVAL(IOV_READAHEAD):
2569 if (bool_val && !dhd_readahead)
2571 dhd_readahead = bool_val;
2574 case IOV_GVAL(IOV_SDRXCHAIN):
2575 int_val = (s32) bus->use_rxchain;
2576 memcpy(arg, &int_val, val_size);
2579 case IOV_SVAL(IOV_SDRXCHAIN):
2580 if (bool_val && !bus->sd_rxchain)
2581 bcmerror = -ENOTSUPP;
2583 bus->use_rxchain = bool_val;
2585 case IOV_GVAL(IOV_ALIGNCTL):
2586 int_val = (s32) dhd_alignctl;
2587 memcpy(arg, &int_val, val_size);
2590 case IOV_SVAL(IOV_ALIGNCTL):
2591 dhd_alignctl = bool_val;
2594 case IOV_GVAL(IOV_SDALIGN):
2595 int_val = DHD_SDALIGN;
2596 memcpy(arg, &int_val, val_size);
2600 case IOV_GVAL(IOV_VARS):
2601 if (bus->varsz < (uint) len)
2602 memcpy(arg, bus->vars, bus->varsz);
2604 bcmerror = -EOVERFLOW;
2606 #endif /* DHD_DEBUG */
2609 case IOV_GVAL(IOV_SDREG):
2614 sd_ptr = (sdreg_t *) params;
2616 addr = (unsigned long)bus->regs + sd_ptr->offset;
2617 size = sd_ptr->func;
2618 int_val = (s32) brcmf_sdcard_reg_read(bus->sdh, addr,
2620 if (brcmf_sdcard_regfail(bus->sdh))
2622 memcpy(arg, &int_val, sizeof(s32));
2626 case IOV_SVAL(IOV_SDREG):
2631 sd_ptr = (sdreg_t *) params;
2633 addr = (unsigned long)bus->regs + sd_ptr->offset;
2634 size = sd_ptr->func;
2635 brcmf_sdcard_reg_write(bus->sdh, addr, size,
2637 if (brcmf_sdcard_regfail(bus->sdh))
2642 /* Same as above, but offset is not backplane
2644 case IOV_GVAL(IOV_SBREG):
2649 memcpy(&sdreg, params, sizeof(sdreg));
2651 addr = SI_ENUM_BASE + sdreg.offset;
2653 int_val = (s32) brcmf_sdcard_reg_read(bus->sdh, addr,
2655 if (brcmf_sdcard_regfail(bus->sdh))
2657 memcpy(arg, &int_val, sizeof(s32));
2661 case IOV_SVAL(IOV_SBREG):
2666 memcpy(&sdreg, params, sizeof(sdreg));
2668 addr = SI_ENUM_BASE + sdreg.offset;
2670 brcmf_sdcard_reg_write(bus->sdh, addr, size,
2672 if (brcmf_sdcard_regfail(bus->sdh))
2677 case IOV_GVAL(IOV_SDCIS):
2681 strcat(arg, "\nFunc 0\n");
2682 brcmf_sdcard_cis_read(bus->sdh, 0x10,
2683 (u8 *) arg + strlen(arg),
2684 SBSDIO_CIS_SIZE_LIMIT);
2685 strcat(arg, "\nFunc 1\n");
2686 brcmf_sdcard_cis_read(bus->sdh, 0x11,
2687 (u8 *) arg + strlen(arg),
2688 SBSDIO_CIS_SIZE_LIMIT);
2689 strcat(arg, "\nFunc 2\n");
2690 brcmf_sdcard_cis_read(bus->sdh, 0x12,
2691 (u8 *) arg + strlen(arg),
2692 SBSDIO_CIS_SIZE_LIMIT);
2696 case IOV_GVAL(IOV_FORCEEVEN):
2697 int_val = (s32) forcealign;
2698 memcpy(arg, &int_val, val_size);
2701 case IOV_SVAL(IOV_FORCEEVEN):
2702 forcealign = bool_val;
2705 case IOV_GVAL(IOV_TXBOUND):
2706 int_val = (s32) brcmf_txbound;
2707 memcpy(arg, &int_val, val_size);
2710 case IOV_SVAL(IOV_TXBOUND):
2711 brcmf_txbound = (uint) int_val;
2714 case IOV_GVAL(IOV_RXBOUND):
2715 int_val = (s32) brcmf_rxbound;
2716 memcpy(arg, &int_val, val_size);
2719 case IOV_SVAL(IOV_RXBOUND):
2720 brcmf_rxbound = (uint) int_val;
2723 case IOV_GVAL(IOV_TXMINMAX):
2724 int_val = (s32) dhd_txminmax;
2725 memcpy(arg, &int_val, val_size);
2728 case IOV_SVAL(IOV_TXMINMAX):
2729 dhd_txminmax = (uint) int_val;
2731 #endif /* DHD_DEBUG */
2734 case IOV_GVAL(IOV_EXTLOOP):
2735 int_val = (s32) bus->ext_loop;
2736 memcpy(arg, &int_val, val_size);
2739 case IOV_SVAL(IOV_EXTLOOP):
2740 bus->ext_loop = bool_val;
2743 case IOV_GVAL(IOV_PKTGEN):
2744 bcmerror = brcmf_sdbrcm_pktgen_get(bus, arg);
2747 case IOV_SVAL(IOV_PKTGEN):
2748 bcmerror = brcmf_sdbrcm_pktgen_set(bus, arg);
2752 case IOV_SVAL(IOV_DEVRESET):
2753 DHD_TRACE(("%s: Called set IOV_DEVRESET=%d dongle_reset=%d "
2755 __func__, bool_val, bus->dhd->dongle_reset,
2756 bus->dhd->busstate));
2758 brcmf_bus_devreset(bus->dhd, (u8) bool_val);
2762 case IOV_GVAL(IOV_DEVRESET):
2763 DHD_TRACE(("%s: Called get IOV_DEVRESET\n", __func__));
2765 /* Get its status */
2766 int_val = (bool) bus->dhd->dongle_reset;
2767 memcpy(arg, &int_val, val_size);
2772 bcmerror = -ENOTSUPP;
2777 if ((bus->idletime == DHD_IDLE_IMMEDIATE) && !bus->dpc_sched) {
2778 bus->activity = false;
2779 brcmf_sdbrcm_clkctl(bus, CLK_NONE, true);
2782 brcmf_os_sdunlock(bus->dhd);
2784 if (actionid == IOV_SVAL(IOV_DEVRESET) && bool_val == false)
2785 brcmf_c_preinit_ioctls((dhd_pub_t *) bus->dhd);
2790 static int brcmf_sdbrcm_write_vars(dhd_bus_t *bus)
2798 char *nvram_ularray;
2799 #endif /* DHD_DEBUG */
2801 /* Even if there are no vars are to be written, we still
2802 need to set the ramsize. */
2803 varsize = bus->varsz ? roundup(bus->varsz, 4) : 0;
2804 varaddr = (bus->ramsize - 4) - varsize;
2807 vbuffer = kzalloc(varsize, GFP_ATOMIC);
2811 memcpy(vbuffer, bus->vars, bus->varsz);
2813 /* Write the vars list */
2815 brcmf_sdbrcm_membytes(bus, true, varaddr, vbuffer, varsize);
2817 /* Verify NVRAM bytes */
2818 DHD_INFO(("Compare NVRAM dl & ul; varsize=%d\n", varsize));
2819 nvram_ularray = kmalloc(varsize, GFP_ATOMIC);
2823 /* Upload image to verify downloaded contents. */
2824 memset(nvram_ularray, 0xaa, varsize);
2826 /* Read the vars list to temp buffer for comparison */
2828 brcmf_sdbrcm_membytes(bus, false, varaddr, nvram_ularray,
2831 DHD_ERROR(("%s: error %d on reading %d nvram bytes at "
2832 "0x%08x\n", __func__, bcmerror, varsize, varaddr));
2834 /* Compare the org NVRAM with the one read from RAM */
2835 if (memcmp(vbuffer, nvram_ularray, varsize)) {
2836 DHD_ERROR(("%s: Downloaded NVRAM image is corrupted.\n",
2839 DHD_ERROR(("%s: Download/Upload/Compare of NVRAM ok.\n",
2842 kfree(nvram_ularray);
2843 #endif /* DHD_DEBUG */
2848 /* adjust to the user specified RAM */
2849 DHD_INFO(("Physical memory size: %d, usable memory size: %d\n",
2850 bus->orig_ramsize, bus->ramsize));
2851 DHD_INFO(("Vars are at %d, orig varsize is %d\n", varaddr, varsize));
2852 varsize = ((bus->orig_ramsize - 4) - varaddr);
2855 * Determine the length token:
2856 * Varsize, converted to words, in lower 16-bits, checksum
2862 varsizew = varsize / 4;
2863 varsizew = (~varsizew << 16) | (varsizew & 0x0000FFFF);
2864 varsizew = cpu_to_le32(varsizew);
2867 DHD_INFO(("New varsize is %d, length token=0x%08x\n", varsize,
2870 /* Write the length token to the last word */
2871 bcmerror = brcmf_sdbrcm_membytes(bus, true, (bus->orig_ramsize - 4),
2872 (u8 *)&varsizew, 4);
2877 static int brcmf_sdbrcm_download_state(dhd_bus_t *bus, bool enter)
2883 /* To enter download state, disable ARM and reset SOCRAM.
2884 * To exit download state, simply reset ARM (default is RAM boot).
2887 bus->alp_only = true;
2889 brcmf_sdbrcm_chip_disablecore(bus->sdh, bus->ci->armcorebase);
2891 brcmf_sdbrcm_chip_resetcore(bus->sdh, bus->ci->ramcorebase);
2893 /* Clear the top bit of memory */
2896 brcmf_sdbrcm_membytes(bus, true, bus->ramsize - 4,
2900 regdata = brcmf_sdcard_reg_read(bus->sdh,
2901 CORE_SB(bus->ci->ramcorebase, sbtmstatelow), 4);
2902 regdata &= (SBTML_RESET | SBTML_REJ_MASK |
2903 (SICF_CLOCK_EN << SBTML_SICF_SHIFT));
2904 if ((SICF_CLOCK_EN << SBTML_SICF_SHIFT) != regdata) {
2905 DHD_ERROR(("%s: SOCRAM core is down after reset?\n",
2911 bcmerror = brcmf_sdbrcm_write_vars(bus);
2913 DHD_ERROR(("%s: no vars written to RAM\n", __func__));
2917 W_SDREG(0xFFFFFFFF, &bus->regs->intstatus, retries);
2919 brcmf_sdbrcm_chip_resetcore(bus->sdh, bus->ci->armcorebase);
2921 /* Allow HT Clock now that the ARM is running. */
2922 bus->alp_only = false;
2924 bus->dhd->busstate = DHD_BUS_LOAD;
2931 brcmf_sdbrcm_bus_iovar_op(dhd_pub_t *dhdp, const char *name,
2932 void *params, int plen, void *arg, int len, bool set)
2934 dhd_bus_t *bus = dhdp->bus;
2935 const struct brcmu_iovar *vi = NULL;
2940 DHD_TRACE(("%s: Enter\n", __func__));
2945 /* Get MUST have return space */
2946 ASSERT(set || (arg && len));
2948 /* Set does NOT take qualifiers */
2949 ASSERT(!set || (!params && !plen));
2951 /* Look up var locally; if not found pass to host driver */
2952 vi = brcmu_iovar_lookup(dhdsdio_iovars, name);
2954 brcmf_os_sdlock(bus->dhd);
2958 /* Turn on clock in case SD command needs backplane */
2959 brcmf_sdbrcm_clkctl(bus, CLK_AVAIL, false);
2961 bcmerror = brcmf_sdcard_iovar_op(bus->sdh, name, params, plen,
2964 /* Similar check for blocksize change */
2965 if (set && strcmp(name, "sd_blocksize") == 0) {
2967 if (brcmf_sdcard_iovar_op
2968 (bus->sdh, "sd_blocksize", &fnum, sizeof(s32),
2969 &bus->blocksize, sizeof(s32),
2972 DHD_ERROR(("%s: fail on %s get\n", __func__,
2975 DHD_INFO(("%s: noted %s update, value now %d\n",
2976 __func__, "sd_blocksize",
2980 bus->roundup = min(max_roundup, bus->blocksize);
2982 if ((bus->idletime == DHD_IDLE_IMMEDIATE) && !bus->dpc_sched) {
2983 bus->activity = false;
2984 brcmf_sdbrcm_clkctl(bus, CLK_NONE, true);
2987 brcmf_os_sdunlock(bus->dhd);
2991 DHD_CTL(("%s: %s %s, len %d plen %d\n", __func__,
2992 name, (set ? "set" : "get"), len, plen));
2994 /* set up 'params' pointer in case this is a set command so that
2995 * the convenience int and bool code can be common to set and get
2997 if (params == NULL) {
3002 if (vi->type == IOVT_VOID)
3004 else if (vi->type == IOVT_BUFFER)
3007 /* all other types are integer sized */
3008 val_size = sizeof(int);
3010 actionid = set ? IOV_SVAL(vi->varid) : IOV_GVAL(vi->varid);
3011 bcmerror = brcmf_sdbrcm_doiovar(bus, vi, actionid, name, params, plen,
3012 arg, len, val_size);
3018 void brcmf_sdbrcm_bus_stop(struct dhd_bus *bus, bool enforce_mutex)
3020 u32 local_hostintmask;
3025 DHD_TRACE(("%s: Enter\n", __func__));
3028 brcmf_os_sdlock(bus->dhd);
3032 /* Enable clock for device interrupts */
3033 brcmf_sdbrcm_clkctl(bus, CLK_AVAIL, false);
3035 /* Disable and clear interrupts at the chip level also */
3036 W_SDREG(0, &bus->regs->hostintmask, retries);
3037 local_hostintmask = bus->hostintmask;
3038 bus->hostintmask = 0;
3040 /* Change our idea of bus state */
3041 bus->dhd->busstate = DHD_BUS_DOWN;
3043 /* Force clocks on backplane to be sure F2 interrupt propagates */
3044 saveclk = brcmf_sdcard_cfg_read(bus->sdh, SDIO_FUNC_1,
3045 SBSDIO_FUNC1_CHIPCLKCSR, &err);
3047 brcmf_sdcard_cfg_write(bus->sdh, SDIO_FUNC_1,
3048 SBSDIO_FUNC1_CHIPCLKCSR,
3049 (saveclk | SBSDIO_FORCE_HT), &err);
3052 DHD_ERROR(("%s: Failed to force clock for F2: err %d\n",
3056 /* Turn off the bus (F2), free any pending packets */
3057 DHD_INTR(("%s: disable SDIO interrupts\n", __func__));
3058 brcmf_sdcard_intr_disable(bus->sdh);
3059 brcmf_sdcard_cfg_write(bus->sdh, SDIO_FUNC_0, SDIO_CCCR_IOEx,
3060 SDIO_FUNC_ENABLE_1, NULL);
3062 /* Clear any pending interrupts now that F2 is disabled */
3063 W_SDREG(local_hostintmask, &bus->regs->intstatus, retries);
3065 /* Turn off the backplane clock (only) */
3066 brcmf_sdbrcm_clkctl(bus, CLK_SDONLY, false);
3068 /* Clear the data packet queues */
3069 brcmu_pktq_flush(&bus->txq, true, NULL, NULL);
3071 /* Clear any held glomming stuff */
3073 brcmu_pkt_buf_free_skb(bus->glomd);
3076 brcmu_pkt_buf_free_skb(bus->glom);
3078 bus->glom = bus->glomd = NULL;
3080 /* Clear rx control and wake any waiters */
3082 brcmf_os_ioctl_resp_wake(bus->dhd);
3084 /* Reset some F2 state stuff */
3085 bus->rxskip = false;
3086 bus->tx_seq = bus->rx_seq = 0;
3089 brcmf_os_sdunlock(bus->dhd);
3092 int brcmf_sdbrcm_bus_init(dhd_pub_t *dhdp, bool enforce_mutex)
3094 dhd_bus_t *bus = dhdp->bus;
3101 DHD_TRACE(("%s: Enter\n", __func__));
3108 brcmf_os_sdlock(bus->dhd);
3110 /* Make sure backplane clock is on, needed to generate F2 interrupt */
3111 brcmf_sdbrcm_clkctl(bus, CLK_AVAIL, false);
3112 if (bus->clkstate != CLK_AVAIL)
3115 /* Force clocks on backplane to be sure F2 interrupt propagates */
3117 brcmf_sdcard_cfg_read(bus->sdh, SDIO_FUNC_1,
3118 SBSDIO_FUNC1_CHIPCLKCSR, &err);
3120 brcmf_sdcard_cfg_write(bus->sdh, SDIO_FUNC_1,
3121 SBSDIO_FUNC1_CHIPCLKCSR,
3122 (saveclk | SBSDIO_FORCE_HT), &err);
3125 DHD_ERROR(("%s: Failed to force clock for F2: err %d\n",
3130 /* Enable function 2 (frame transfers) */
3131 W_SDREG((SDPCM_PROT_VERSION << SMB_DATA_VERSION_SHIFT),
3132 &bus->regs->tosbmailboxdata, retries);
3133 enable = (SDIO_FUNC_ENABLE_1 | SDIO_FUNC_ENABLE_2);
3135 brcmf_sdcard_cfg_write(bus->sdh, SDIO_FUNC_0, SDIO_CCCR_IOEx, enable,
3138 /* Give the dongle some time to do its thing and set IOR2 */
3139 brcmf_timeout_start(&tmo, DHD_WAIT_F2RDY * 1000);
3142 while (ready != enable && !brcmf_timeout_expired(&tmo))
3144 brcmf_sdcard_cfg_read(bus->sdh, SDIO_FUNC_0, SDIO_CCCR_IORx,
3147 DHD_INFO(("%s: enable 0x%02x, ready 0x%02x (waited %uus)\n",
3148 __func__, enable, ready, tmo.elapsed));
3150 /* If F2 successfully enabled, set core and enable interrupts */
3151 if (ready == enable) {
3152 /* Set up the interrupt mask and enable interrupts */
3153 bus->hostintmask = HOSTINTMASK;
3154 W_SDREG(bus->hostintmask,
3155 (unsigned int *)CORE_BUS_REG(bus->ci->buscorebase,
3156 hostintmask), retries);
3158 brcmf_sdcard_cfg_write(bus->sdh, SDIO_FUNC_1, SBSDIO_WATERMARK,
3159 (u8) watermark, &err);
3161 /* Set bus state according to enable result */
3162 dhdp->busstate = DHD_BUS_DATA;
3164 /* bcmsdh_intr_unmask(bus->sdh); */
3166 bus->intdis = false;
3168 DHD_INTR(("%s: enable SDIO device interrupts\n",
3170 brcmf_sdcard_intr_enable(bus->sdh);
3172 DHD_INTR(("%s: disable SDIO interrupts\n", __func__));
3173 brcmf_sdcard_intr_disable(bus->sdh);
3179 /* Disable F2 again */
3180 enable = SDIO_FUNC_ENABLE_1;
3181 brcmf_sdcard_cfg_write(bus->sdh, SDIO_FUNC_0, SDIO_CCCR_IOEx,
3185 /* Restore previous clock setting */
3186 brcmf_sdcard_cfg_write(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
3189 /* If we didn't come up, turn off backplane clock */
3190 if (dhdp->busstate != DHD_BUS_DATA)
3191 brcmf_sdbrcm_clkctl(bus, CLK_NONE, false);
3195 brcmf_os_sdunlock(bus->dhd);
3200 static void brcmf_sdbrcm_rxfail(dhd_bus_t *bus, bool abort, bool rtx)
3202 struct brcmf_sdio *sdh = bus->sdh;
3203 struct sdpcmd_regs *regs = bus->regs;
3209 DHD_ERROR(("%s: %sterminate frame%s\n", __func__,
3210 (abort ? "abort command, " : ""),
3211 (rtx ? ", send NAK" : "")));
3214 brcmf_sdcard_abort(sdh, SDIO_FUNC_2);
3216 brcmf_sdcard_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_FRAMECTRL,
3220 /* Wait until the packet has been flushed (device/FIFO stable) */
3221 for (lastrbc = retries = 0xffff; retries > 0; retries--) {
3222 hi = brcmf_sdcard_cfg_read(sdh, SDIO_FUNC_1,
3223 SBSDIO_FUNC1_RFRAMEBCHI, NULL);
3224 lo = brcmf_sdcard_cfg_read(sdh, SDIO_FUNC_1,
3225 SBSDIO_FUNC1_RFRAMEBCLO, NULL);
3226 bus->f1regdata += 2;
3228 if ((hi == 0) && (lo == 0))
3231 if ((hi > (lastrbc >> 8)) && (lo > (lastrbc & 0x00ff))) {
3232 DHD_ERROR(("%s: count growing: last 0x%04x now "
3234 __func__, lastrbc, ((hi << 8) + lo)));
3236 lastrbc = (hi << 8) + lo;
3240 DHD_ERROR(("%s: count never zeroed: last 0x%04x\n",
3241 __func__, lastrbc));
3243 DHD_INFO(("%s: flush took %d iterations\n", __func__,
3244 (0xffff - retries)));
3249 W_SDREG(SMB_NAK, ®s->tosbmailbox, retries);
3251 if (retries <= retry_limit)
3255 /* Clear partial in any case */
3258 /* If we can't reach the device, signal failure */
3259 if (err || brcmf_sdcard_regfail(sdh))
3260 bus->dhd->busstate = DHD_BUS_DOWN;
3264 brcmf_sdbrcm_read_control(dhd_bus_t *bus, u8 *hdr, uint len, uint doff)
3266 struct brcmf_sdio *sdh = bus->sdh;
3271 DHD_TRACE(("%s: Enter\n", __func__));
3273 /* Control data already received in aligned rxctl */
3274 if ((bus->bus == SPI_BUS) && (!bus->usebufpool))
3278 /* Set rxctl for frame (w/optional alignment) */
3279 bus->rxctl = bus->rxbuf;
3281 bus->rxctl += firstread;
3282 pad = ((unsigned long)bus->rxctl % DHD_SDALIGN);
3284 bus->rxctl += (DHD_SDALIGN - pad);
3285 bus->rxctl -= firstread;
3287 ASSERT(bus->rxctl >= bus->rxbuf);
3289 /* Copy the already-read portion over */
3290 memcpy(bus->rxctl, hdr, firstread);
3291 if (len <= firstread)
3294 /* Copy the full data pkt in gSPI case and process ioctl. */
3295 if (bus->bus == SPI_BUS) {
3296 memcpy(bus->rxctl, hdr, len);
3300 /* Raise rdlen to next SDIO block to avoid tail command */
3301 rdlen = len - firstread;
3302 if (bus->roundup && bus->blocksize && (rdlen > bus->blocksize)) {
3303 pad = bus->blocksize - (rdlen % bus->blocksize);
3304 if ((pad <= bus->roundup) && (pad < bus->blocksize) &&
3305 ((len + pad) < bus->dhd->maxctl))
3307 } else if (rdlen % DHD_SDALIGN) {
3308 rdlen += DHD_SDALIGN - (rdlen % DHD_SDALIGN);
3311 /* Satisfy length-alignment requirements */
3312 if (forcealign && (rdlen & (ALIGNMENT - 1)))
3313 rdlen = roundup(rdlen, ALIGNMENT);
3315 /* Drop if the read is too big or it exceeds our maximum */
3316 if ((rdlen + firstread) > bus->dhd->maxctl) {
3317 DHD_ERROR(("%s: %d-byte control read exceeds %d-byte buffer\n",
3318 __func__, rdlen, bus->dhd->maxctl));
3319 bus->dhd->rx_errors++;
3320 brcmf_sdbrcm_rxfail(bus, false, false);
3324 if ((len - doff) > bus->dhd->maxctl) {
3325 DHD_ERROR(("%s: %d-byte ctl frame (%d-byte ctl data) exceeds "
3327 __func__, len, (len - doff), bus->dhd->maxctl));
3328 bus->dhd->rx_errors++;
3330 brcmf_sdbrcm_rxfail(bus, false, false);
3334 /* Read remainder of frame body into the rxctl buffer */
3335 sdret = brcmf_sdcard_recv_buf(sdh, brcmf_sdcard_cur_sbwad(sdh),
3337 F2SYNC, (bus->rxctl + firstread), rdlen,
3340 ASSERT(sdret != -BCME_PENDING);
3342 /* Control frame failures need retransmission */
3344 DHD_ERROR(("%s: read %d control bytes failed: %d\n",
3345 __func__, rdlen, sdret));
3346 bus->rxc_errors++; /* dhd.rx_ctlerrs is higher level */
3347 brcmf_sdbrcm_rxfail(bus, true, true);
3354 if (DHD_BYTES_ON() && DHD_CTL_ON()) {
3355 printk(KERN_DEBUG "RxCtrl:\n");
3356 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, bus->rxctl, len);
3360 /* Point to valid data and indicate its length */
3362 bus->rxlen = len - doff;
3365 /* Awake any waiters */
3366 brcmf_os_ioctl_resp_wake(bus->dhd);
3369 static u8 brcmf_sdbrcm_rxglom(dhd_bus_t *bus, u8 rxseq)
3375 struct sk_buff *pfirst, *plast, *pnext, *save_pfirst;
3378 u8 chan, seq, doff, sfdoff;
3382 bool usechain = bus->use_rxchain;
3384 /* If packets, issue read(s) and send up packet chain */
3385 /* Return sequence numbers consumed? */
3387 DHD_TRACE(("brcmf_sdbrcm_rxglom: start: glomd %p glom %p\n", bus->glomd,
3390 /* If there's a descriptor, generate the packet chain */
3392 pfirst = plast = pnext = NULL;
3393 dlen = (u16) (bus->glomd->len);
3394 dptr = bus->glomd->data;
3395 if (!dlen || (dlen & 1)) {
3396 DHD_ERROR(("%s: bad glomd len(%d), ignore descriptor\n",
3401 for (totlen = num = 0; dlen; num++) {
3402 /* Get (and move past) next length */
3403 sublen = get_unaligned_le16(dptr);
3404 dlen -= sizeof(u16);
3405 dptr += sizeof(u16);
3406 if ((sublen < SDPCM_HDRLEN) ||
3407 ((num == 0) && (sublen < (2 * SDPCM_HDRLEN)))) {
3408 DHD_ERROR(("%s: descriptor len %d bad: %d\n",
3409 __func__, num, sublen));
3413 if (sublen % DHD_SDALIGN) {
3414 DHD_ERROR(("%s: sublen %d not multiple of %d\n",
3415 __func__, sublen, DHD_SDALIGN));
3420 /* For last frame, adjust read len so total
3421 is a block multiple */
3424 (roundup(totlen, bus->blocksize) - totlen);
3425 totlen = roundup(totlen, bus->blocksize);
3428 /* Allocate/chain packet for next subframe */
3429 pnext = brcmu_pkt_buf_get_skb(sublen + DHD_SDALIGN);
3430 if (pnext == NULL) {
3431 DHD_ERROR(("%s: bcm_pkt_buf_get_skb failed, "
3432 "num %d len %d\n", __func__,
3436 ASSERT(!(pnext->prev));
3439 pfirst = plast = pnext;
3442 plast->next = pnext;
3446 /* Adhere to start alignment requirements */
3447 PKTALIGN(pnext, sublen, DHD_SDALIGN);
3450 /* If all allocations succeeded, save packet chain
3453 DHD_GLOM(("%s: allocated %d-byte packet chain for %d "
3454 "subframes\n", __func__, totlen, num));
3455 if (DHD_GLOM_ON() && bus->nextlen) {
3456 if (totlen != bus->nextlen) {
3457 DHD_GLOM(("%s: glomdesc mismatch: nextlen %d glomdesc %d " "rxseq %d\n",
3458 __func__, bus->nextlen,
3463 pfirst = pnext = NULL;
3466 brcmu_pkt_buf_free_skb(pfirst);
3471 /* Done with descriptor packet */
3472 brcmu_pkt_buf_free_skb(bus->glomd);
3477 /* Ok -- either we just generated a packet chain,
3478 or had one from before */
3480 if (DHD_GLOM_ON()) {
3481 DHD_GLOM(("%s: try superframe read, packet chain:\n",
3483 for (pnext = bus->glom; pnext; pnext = pnext->next) {
3484 DHD_GLOM((" %p: %p len 0x%04x (%d)\n",
3485 pnext, (u8 *) (pnext->data),
3486 pnext->len, pnext->len));
3491 dlen = (u16) brcmu_pkttotlen(pfirst);
3493 /* Do an SDIO read for the superframe. Configurable iovar to
3494 * read directly into the chained packet, or allocate a large
3495 * packet and and copy into the chain.
3498 errcode = brcmf_sdcard_recv_buf(bus->sdh,
3499 brcmf_sdcard_cur_sbwad(bus->sdh),
3501 F2SYNC, (u8 *) pfirst->data, dlen,
3502 pfirst, NULL, NULL);
3503 } else if (bus->dataptr) {
3504 errcode = brcmf_sdcard_recv_buf(bus->sdh,
3505 brcmf_sdcard_cur_sbwad(bus->sdh),
3507 F2SYNC, bus->dataptr, dlen,
3509 sublen = (u16) brcmu_pktfrombuf(pfirst, 0, dlen,
3511 if (sublen != dlen) {
3512 DHD_ERROR(("%s: FAILED TO COPY, dlen %d sublen %d\n",
3513 __func__, dlen, sublen));
3518 DHD_ERROR(("COULDN'T ALLOC %d-BYTE GLOM, FORCE FAILURE\n",
3523 ASSERT(errcode != -BCME_PENDING);
3525 /* On failure, kill the superframe, allow a couple retries */
3527 DHD_ERROR(("%s: glom read of %d bytes failed: %d\n",
3528 __func__, dlen, errcode));
3529 bus->dhd->rx_errors++;
3531 if (bus->glomerr++ < 3) {
3532 brcmf_sdbrcm_rxfail(bus, true, true);
3535 brcmf_sdbrcm_rxfail(bus, true, false);
3536 brcmu_pkt_buf_free_skb(bus->glom);
3543 if (DHD_GLOM_ON()) {
3544 printk(KERN_DEBUG "SUPERFRAME:\n");
3545 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
3546 pfirst->data, min_t(int, pfirst->len, 48));
3550 /* Validate the superframe header */
3551 dptr = (u8 *) (pfirst->data);
3552 sublen = get_unaligned_le16(dptr);
3553 check = get_unaligned_le16(dptr + sizeof(u16));
3555 chan = SDPCM_PACKET_CHANNEL(&dptr[SDPCM_FRAMETAG_LEN]);
3556 seq = SDPCM_PACKET_SEQUENCE(&dptr[SDPCM_FRAMETAG_LEN]);
3557 bus->nextlen = dptr[SDPCM_FRAMETAG_LEN + SDPCM_NEXTLEN_OFFSET];
3558 if ((bus->nextlen << 4) > MAX_RX_DATASZ) {
3559 DHD_INFO(("%s: nextlen too large (%d) seq %d\n",
3560 __func__, bus->nextlen, seq));
3563 doff = SDPCM_DOFFSET_VALUE(&dptr[SDPCM_FRAMETAG_LEN]);
3564 txmax = SDPCM_WINDOW_VALUE(&dptr[SDPCM_FRAMETAG_LEN]);
3567 if ((u16)~(sublen ^ check)) {
3568 DHD_ERROR(("%s (superframe): HW hdr error: len/check "
3569 "0x%04x/0x%04x\n", __func__, sublen, check));
3571 } else if (roundup(sublen, bus->blocksize) != dlen) {
3572 DHD_ERROR(("%s (superframe): len 0x%04x, rounded "
3573 "0x%04x, expect 0x%04x\n",
3575 roundup(sublen, bus->blocksize), dlen));
3577 } else if (SDPCM_PACKET_CHANNEL(&dptr[SDPCM_FRAMETAG_LEN]) !=
3578 SDPCM_GLOM_CHANNEL) {
3579 DHD_ERROR(("%s (superframe): bad channel %d\n",
3581 SDPCM_PACKET_CHANNEL(&dptr
3582 [SDPCM_FRAMETAG_LEN])));
3584 } else if (SDPCM_GLOMDESC(&dptr[SDPCM_FRAMETAG_LEN])) {
3585 DHD_ERROR(("%s (superframe): got second descriptor?\n",
3588 } else if ((doff < SDPCM_HDRLEN) ||
3589 (doff > (pfirst->len - SDPCM_HDRLEN))) {
3590 DHD_ERROR(("%s (superframe): Bad data offset %d: HW %d "
3592 __func__, doff, sublen,
3593 pfirst->len, SDPCM_HDRLEN));
3597 /* Check sequence number of superframe SW header */
3599 DHD_INFO(("%s: (superframe) rx_seq %d, expected %d\n",
3600 __func__, seq, rxseq));
3605 /* Check window for sanity */
3606 if ((u8) (txmax - bus->tx_seq) > 0x40) {
3607 DHD_ERROR(("%s: unlikely tx max %d with tx_seq %d\n",
3608 __func__, txmax, bus->tx_seq));
3609 txmax = bus->tx_seq + 2;
3611 bus->tx_max = txmax;
3613 /* Remove superframe header, remember offset */
3614 skb_pull(pfirst, doff);
3617 /* Validate all the subframe headers */
3618 for (num = 0, pnext = pfirst; pnext && !errcode;
3619 num++, pnext = pnext->next) {
3620 dptr = (u8 *) (pnext->data);
3621 dlen = (u16) (pnext->len);
3622 sublen = get_unaligned_le16(dptr);
3623 check = get_unaligned_le16(dptr + sizeof(u16));
3624 chan = SDPCM_PACKET_CHANNEL(&dptr[SDPCM_FRAMETAG_LEN]);
3625 doff = SDPCM_DOFFSET_VALUE(&dptr[SDPCM_FRAMETAG_LEN]);
3627 if (DHD_GLOM_ON()) {
3628 printk(KERN_DEBUG "subframe:\n");
3629 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
3634 if ((u16)~(sublen ^ check)) {
3635 DHD_ERROR(("%s (subframe %d): HW hdr error: "
3636 "len/check 0x%04x/0x%04x\n",
3637 __func__, num, sublen, check));
3639 } else if ((sublen > dlen) || (sublen < SDPCM_HDRLEN)) {
3640 DHD_ERROR(("%s (subframe %d): length mismatch: "
3641 "len 0x%04x, expect 0x%04x\n",
3642 __func__, num, sublen, dlen));
3644 } else if ((chan != SDPCM_DATA_CHANNEL) &&
3645 (chan != SDPCM_EVENT_CHANNEL)) {
3646 DHD_ERROR(("%s (subframe %d): bad channel %d\n",
3647 __func__, num, chan));
3649 } else if ((doff < SDPCM_HDRLEN) || (doff > sublen)) {
3650 DHD_ERROR(("%s (subframe %d): Bad data offset %d: HW %d min %d\n",
3651 __func__, num, doff, sublen,
3658 /* Terminate frame on error, request
3660 if (bus->glomerr++ < 3) {
3661 /* Restore superframe header space */
3662 skb_push(pfirst, sfdoff);
3663 brcmf_sdbrcm_rxfail(bus, true, true);
3666 brcmf_sdbrcm_rxfail(bus, true, false);
3667 brcmu_pkt_buf_free_skb(bus->glom);
3675 /* Basic SD framing looks ok - process each packet (header) */
3676 save_pfirst = pfirst;
3680 for (num = 0; pfirst; rxseq++, pfirst = pnext) {
3681 pnext = pfirst->next;
3682 pfirst->next = NULL;
3684 dptr = (u8 *) (pfirst->data);
3685 sublen = get_unaligned_le16(dptr);
3686 chan = SDPCM_PACKET_CHANNEL(&dptr[SDPCM_FRAMETAG_LEN]);
3687 seq = SDPCM_PACKET_SEQUENCE(&dptr[SDPCM_FRAMETAG_LEN]);
3688 doff = SDPCM_DOFFSET_VALUE(&dptr[SDPCM_FRAMETAG_LEN]);
3690 DHD_GLOM(("%s: Get subframe %d, %p(%p/%d), sublen %d "
3692 __func__, num, pfirst, pfirst->data,
3693 pfirst->len, sublen, chan, seq));
3695 ASSERT((chan == SDPCM_DATA_CHANNEL)
3696 || (chan == SDPCM_EVENT_CHANNEL));
3699 DHD_GLOM(("%s: rx_seq %d, expected %d\n",
3700 __func__, seq, rxseq));
3705 if (DHD_BYTES_ON() && DHD_DATA_ON()) {
3706 printk(KERN_DEBUG "Rx Subframe Data:\n");
3707 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
3712 __skb_trim(pfirst, sublen);
3713 skb_pull(pfirst, doff);
3715 if (pfirst->len == 0) {
3716 brcmu_pkt_buf_free_skb(pfirst);
3718 plast->next = pnext;
3720 ASSERT(save_pfirst == pfirst);
3721 save_pfirst = pnext;
3724 } else if (brcmf_proto_hdrpull(bus->dhd, &ifidx, pfirst)
3726 DHD_ERROR(("%s: rx protocol error\n",
3728 bus->dhd->rx_errors++;
3729 brcmu_pkt_buf_free_skb(pfirst);
3731 plast->next = pnext;
3733 ASSERT(save_pfirst == pfirst);
3734 save_pfirst = pnext;
3739 /* this packet will go up, link back into
3740 chain and count it */
3741 pfirst->next = pnext;
3746 if (DHD_GLOM_ON()) {
3747 DHD_GLOM(("%s subframe %d to stack, %p(%p/%d) "
3749 __func__, num, pfirst, pfirst->data,
3750 pfirst->len, pfirst->next,
3752 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
3754 min_t(int, pfirst->len, 32));
3756 #endif /* DHD_DEBUG */
3759 brcmf_os_sdunlock(bus->dhd);
3760 brcmf_rx_frame(bus->dhd, ifidx, save_pfirst, num);
3761 brcmf_os_sdlock(bus->dhd);
3764 bus->rxglomframes++;
3765 bus->rxglompkts += num;
3770 /* Return true if there may be more frames to read */
3772 brcmf_sdbrcm_readframes(dhd_bus_t *bus, uint maxframes, bool *finished)
3774 struct brcmf_sdio *sdh = bus->sdh;
3776 u16 len, check; /* Extracted hardware header fields */
3777 u8 chan, seq, doff; /* Extracted software header fields */
3778 u8 fcbits; /* Extracted fcbits from software header */
3780 struct sk_buff *pkt; /* Packet for event or data frames */
3781 u16 pad; /* Number of pad bytes to read */
3782 u16 rdlen; /* Total number of bytes to read */
3783 u8 rxseq; /* Next sequence number to expect */
3784 uint rxleft = 0; /* Remaining number of frames allowed */
3785 int sdret; /* Return code from bcmsdh calls */
3786 u8 txmax; /* Maximum tx sequence offered */
3787 bool len_consistent; /* Result of comparing readahead len and
3791 uint rxcount = 0; /* Total frames read */
3793 #if defined(DHD_DEBUG) || defined(SDTEST)
3794 bool sdtest = false; /* To limit message spew from test mode */
3797 DHD_TRACE(("%s: Enter\n", __func__));
3802 /* Allow pktgen to override maxframes */
3803 if (bus->pktgen_count && (bus->pktgen_mode == DHD_PKTGEN_RECV)) {
3804 maxframes = bus->pktgen_count;
3809 /* Not finished unless we encounter no more frames indication */
3812 for (rxseq = bus->rx_seq, rxleft = maxframes;
3813 !bus->rxskip && rxleft && bus->dhd->busstate != DHD_BUS_DOWN;
3814 rxseq++, rxleft--) {
3816 /* Handle glomming separately */
3817 if (bus->glom || bus->glomd) {
3819 DHD_GLOM(("%s: calling rxglom: glomd %p, glom %p\n",
3820 __func__, bus->glomd, bus->glom));
3821 cnt = brcmf_sdbrcm_rxglom(bus, rxseq);
3822 DHD_GLOM(("%s: rxglom returned %d\n", __func__, cnt));
3824 rxleft = (rxleft > cnt) ? (rxleft - cnt) : 1;
3828 /* Try doing single read if we can */
3829 if (dhd_readahead && bus->nextlen) {
3830 u16 nextlen = bus->nextlen;
3833 if (bus->bus == SPI_BUS) {
3834 rdlen = len = nextlen;
3836 rdlen = len = nextlen << 4;
3838 /* Pad read to blocksize for efficiency */
3839 if (bus->roundup && bus->blocksize
3840 && (rdlen > bus->blocksize)) {
3843 (rdlen % bus->blocksize);
3844 if ((pad <= bus->roundup)
3845 && (pad < bus->blocksize)
3846 && ((rdlen + pad + firstread) <
3849 } else if (rdlen % DHD_SDALIGN) {
3851 DHD_SDALIGN - (rdlen % DHD_SDALIGN);
3855 /* We use bus->rxctl buffer in WinXP for initial
3856 * control pkt receives.
3857 * Later we use buffer-poll for data as well
3858 * as control packets.
3859 * This is required because dhd receives full
3860 * frame in gSPI unlike SDIO.
3861 * After the frame is received we have to
3862 * distinguish whether it is data
3863 * or non-data frame.
3865 /* Allocate a packet buffer */
3866 pkt = brcmu_pkt_buf_get_skb(rdlen + DHD_SDALIGN);
3868 if (bus->bus == SPI_BUS) {
3869 bus->usebufpool = false;
3870 bus->rxctl = bus->rxbuf;
3872 bus->rxctl += firstread;
3873 pad = ((unsigned long)bus->rxctl %
3877 (DHD_SDALIGN - pad);
3878 bus->rxctl -= firstread;
3880 ASSERT(bus->rxctl >= bus->rxbuf);
3882 /* Read the entire frame */
3883 sdret = brcmf_sdcard_recv_buf(sdh,
3884 brcmf_sdcard_cur_sbwad(sdh),
3885 SDIO_FUNC_2, F2SYNC,
3889 ASSERT(sdret != -BCME_PENDING);
3891 /* Control frame failures need
3894 DHD_ERROR(("%s: read %d control bytes failed: %d\n",
3897 /* dhd.rx_ctlerrs is higher */
3899 brcmf_sdbrcm_rxfail(bus, true,
3907 request rtx of events */
3908 DHD_ERROR(("%s (nextlen): "
3909 "brcmu_pkt_buf_get_skb "
3911 " len %d rdlen %d expected"
3912 " rxseq %d\n", __func__,
3913 len, rdlen, rxseq));
3917 if (bus->bus == SPI_BUS)
3918 bus->usebufpool = true;
3920 ASSERT(!(pkt->prev));
3921 PKTALIGN(pkt, rdlen, DHD_SDALIGN);
3922 rxbuf = (u8 *) (pkt->data);
3923 /* Read the entire frame */
3924 sdret = brcmf_sdcard_recv_buf(sdh,
3925 brcmf_sdcard_cur_sbwad(sdh),
3926 SDIO_FUNC_2, F2SYNC,
3930 ASSERT(sdret != -BCME_PENDING);
3933 DHD_ERROR(("%s (nextlen): read %d bytes failed: %d\n",
3934 __func__, rdlen, sdret));
3935 brcmu_pkt_buf_free_skb(pkt);
3936 bus->dhd->rx_errors++;
3937 /* Force retry w/normal header read.
3938 * Don't attempt NAK for
3941 brcmf_sdbrcm_rxfail(bus, true,
3949 /* Now check the header */
3950 memcpy(bus->rxhdr, rxbuf, SDPCM_HDRLEN);
3952 /* Extract hardware header fields */
3953 len = get_unaligned_le16(bus->rxhdr);
3954 check = get_unaligned_le16(bus->rxhdr + sizeof(u16));
3956 /* All zeros means readahead info was bad */
3957 if (!(len | check)) {
3958 DHD_INFO(("%s (nextlen): read zeros in HW "
3959 "header???\n", __func__));
3960 brcmf_sdbrcm_pktfree2(bus, pkt);
3964 /* Validate check bytes */
3965 if ((u16)~(len ^ check)) {
3966 DHD_ERROR(("%s (nextlen): HW hdr error:"
3967 " nextlen/len/check"
3968 " 0x%04x/0x%04x/0x%04x\n",
3969 __func__, nextlen, len, check));
3971 brcmf_sdbrcm_rxfail(bus, false, false);
3972 brcmf_sdbrcm_pktfree2(bus, pkt);
3976 /* Validate frame length */
3977 if (len < SDPCM_HDRLEN) {
3978 DHD_ERROR(("%s (nextlen): HW hdr length "
3979 "invalid: %d\n", __func__, len));
3980 brcmf_sdbrcm_pktfree2(bus, pkt);
3984 /* Check for consistency withreadahead info */
3985 len_consistent = (nextlen != (roundup(len, 16) >> 4));
3986 if (len_consistent) {
3987 /* Mismatch, force retry w/normal
3988 header (may be >4K) */
3989 DHD_ERROR(("%s (nextlen): mismatch, "
3990 "nextlen %d len %d rnd %d; "
3991 "expected rxseq %d\n",
3993 len, roundup(len, 16), rxseq));
3994 brcmf_sdbrcm_rxfail(bus, true,
3995 bus->bus != SPI_BUS);
3996 brcmf_sdbrcm_pktfree2(bus, pkt);
4000 /* Extract software header fields */
4001 chan = SDPCM_PACKET_CHANNEL(
4002 &bus->rxhdr[SDPCM_FRAMETAG_LEN]);
4003 seq = SDPCM_PACKET_SEQUENCE(
4004 &bus->rxhdr[SDPCM_FRAMETAG_LEN]);
4005 doff = SDPCM_DOFFSET_VALUE(
4006 &bus->rxhdr[SDPCM_FRAMETAG_LEN]);
4007 txmax = SDPCM_WINDOW_VALUE(
4008 &bus->rxhdr[SDPCM_FRAMETAG_LEN]);
4011 bus->rxhdr[SDPCM_FRAMETAG_LEN +
4012 SDPCM_NEXTLEN_OFFSET];
4013 if ((bus->nextlen << 4) > MAX_RX_DATASZ) {
4014 DHD_INFO(("%s (nextlen): got frame w/nextlen too large" " (%d), seq %d\n",
4015 __func__, bus->nextlen, seq));
4019 bus->dhd->rx_readahead_cnt++;
4021 /* Handle Flow Control */
4022 fcbits = SDPCM_FCMASK_VALUE(
4023 &bus->rxhdr[SDPCM_FRAMETAG_LEN]);
4025 if (bus->flowcontrol != fcbits) {
4026 if (~bus->flowcontrol & fcbits)
4029 if (bus->flowcontrol & ~fcbits)
4033 bus->flowcontrol = fcbits;
4036 /* Check and update sequence number */
4038 DHD_INFO(("%s (nextlen): rx_seq %d, expected "
4039 "%d\n", __func__, seq, rxseq));
4044 /* Check window for sanity */
4045 if ((u8) (txmax - bus->tx_seq) > 0x40) {
4046 DHD_ERROR(("%s: got unlikely tx max %d with "
4048 __func__, txmax, bus->tx_seq));
4049 txmax = bus->tx_seq + 2;
4051 bus->tx_max = txmax;
4054 if (DHD_BYTES_ON() && DHD_DATA_ON()) {
4055 printk(KERN_DEBUG "Rx Data:\n");
4056 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
4058 } else if (DHD_HDRS_ON()) {
4059 printk(KERN_DEBUG "RxHdr:\n");
4060 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
4061 bus->rxhdr, SDPCM_HDRLEN);
4065 if (chan == SDPCM_CONTROL_CHANNEL) {
4066 if (bus->bus == SPI_BUS) {
4067 brcmf_sdbrcm_read_control(bus, rxbuf,
4070 DHD_ERROR(("%s (nextlen): readahead on control" " packet %d?\n",
4072 /* Force retry w/normal header read */
4074 brcmf_sdbrcm_rxfail(bus, false, true);
4076 brcmf_sdbrcm_pktfree2(bus, pkt);
4080 if ((bus->bus == SPI_BUS) && !bus->usebufpool) {
4081 DHD_ERROR(("Received %d bytes on %d channel. Running out of " "rx pktbuf's or not yet malloced.\n",
4086 /* Validate data offset */
4087 if ((doff < SDPCM_HDRLEN) || (doff > len)) {
4088 DHD_ERROR(("%s (nextlen): bad data offset %d: HW len %d min %d\n",
4089 __func__, doff, len, SDPCM_HDRLEN));
4090 brcmf_sdbrcm_rxfail(bus, false, false);
4091 brcmf_sdbrcm_pktfree2(bus, pkt);
4095 /* All done with this one -- now deliver the packet */
4098 /* gSPI frames should not be handled in fractions */
4099 if (bus->bus == SPI_BUS)
4102 /* Read frame header (hardware and software) */
4103 sdret = brcmf_sdcard_recv_buf(sdh, brcmf_sdcard_cur_sbwad(sdh),
4104 SDIO_FUNC_2, F2SYNC, bus->rxhdr, firstread,
4107 ASSERT(sdret != -BCME_PENDING);
4110 DHD_ERROR(("%s: RXHEADER FAILED: %d\n", __func__,
4113 brcmf_sdbrcm_rxfail(bus, true, true);
4117 if (DHD_BYTES_ON() || DHD_HDRS_ON()) {
4118 printk(KERN_DEBUG "RxHdr:\n");
4119 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
4120 bus->rxhdr, SDPCM_HDRLEN);
4124 /* Extract hardware header fields */
4125 len = get_unaligned_le16(bus->rxhdr);
4126 check = get_unaligned_le16(bus->rxhdr + sizeof(u16));
4128 /* All zeros means no more frames */
4129 if (!(len | check)) {
4134 /* Validate check bytes */
4135 if ((u16) ~(len ^ check)) {
4136 DHD_ERROR(("%s: HW hdr err: len/check 0x%04x/0x%04x\n",
4137 __func__, len, check));
4139 brcmf_sdbrcm_rxfail(bus, false, false);
4143 /* Validate frame length */
4144 if (len < SDPCM_HDRLEN) {
4145 DHD_ERROR(("%s: HW hdr length invalid: %d\n",
4150 /* Extract software header fields */
4151 chan = SDPCM_PACKET_CHANNEL(&bus->rxhdr[SDPCM_FRAMETAG_LEN]);
4152 seq = SDPCM_PACKET_SEQUENCE(&bus->rxhdr[SDPCM_FRAMETAG_LEN]);
4153 doff = SDPCM_DOFFSET_VALUE(&bus->rxhdr[SDPCM_FRAMETAG_LEN]);
4154 txmax = SDPCM_WINDOW_VALUE(&bus->rxhdr[SDPCM_FRAMETAG_LEN]);
4156 /* Validate data offset */
4157 if ((doff < SDPCM_HDRLEN) || (doff > len)) {
4158 DHD_ERROR(("%s: Bad data offset %d: HW len %d, min %d "
4160 __func__, doff, len, SDPCM_HDRLEN, seq));
4163 brcmf_sdbrcm_rxfail(bus, false, false);
4167 /* Save the readahead length if there is one */
4169 bus->rxhdr[SDPCM_FRAMETAG_LEN + SDPCM_NEXTLEN_OFFSET];
4170 if ((bus->nextlen << 4) > MAX_RX_DATASZ) {
4171 DHD_INFO(("%s (nextlen): got frame w/nextlen too large "
4173 __func__, bus->nextlen, seq));
4177 /* Handle Flow Control */
4178 fcbits = SDPCM_FCMASK_VALUE(&bus->rxhdr[SDPCM_FRAMETAG_LEN]);
4180 if (bus->flowcontrol != fcbits) {
4181 if (~bus->flowcontrol & fcbits)
4184 if (bus->flowcontrol & ~fcbits)
4188 bus->flowcontrol = fcbits;
4191 /* Check and update sequence number */
4193 DHD_INFO(("%s: rx_seq %d, expected %d\n", __func__,
4199 /* Check window for sanity */
4200 if ((u8) (txmax - bus->tx_seq) > 0x40) {
4201 DHD_ERROR(("%s: unlikely tx max %d with tx_seq %d\n",
4202 __func__, txmax, bus->tx_seq));
4203 txmax = bus->tx_seq + 2;
4205 bus->tx_max = txmax;
4207 /* Call a separate function for control frames */
4208 if (chan == SDPCM_CONTROL_CHANNEL) {
4209 brcmf_sdbrcm_read_control(bus, bus->rxhdr, len, doff);
4213 ASSERT((chan == SDPCM_DATA_CHANNEL)
4214 || (chan == SDPCM_EVENT_CHANNEL)
4215 || (chan == SDPCM_TEST_CHANNEL)
4216 || (chan == SDPCM_GLOM_CHANNEL));
4218 /* Length to read */
4219 rdlen = (len > firstread) ? (len - firstread) : 0;
4221 /* May pad read to blocksize for efficiency */
4222 if (bus->roundup && bus->blocksize &&
4223 (rdlen > bus->blocksize)) {
4224 pad = bus->blocksize - (rdlen % bus->blocksize);
4225 if ((pad <= bus->roundup) && (pad < bus->blocksize) &&
4226 ((rdlen + pad + firstread) < MAX_RX_DATASZ))
4228 } else if (rdlen % DHD_SDALIGN) {
4229 rdlen += DHD_SDALIGN - (rdlen % DHD_SDALIGN);
4232 /* Satisfy length-alignment requirements */
4233 if (forcealign && (rdlen & (ALIGNMENT - 1)))
4234 rdlen = roundup(rdlen, ALIGNMENT);
4236 if ((rdlen + firstread) > MAX_RX_DATASZ) {
4237 /* Too long -- skip this frame */
4238 DHD_ERROR(("%s: too long: len %d rdlen %d\n",
4239 __func__, len, rdlen));
4240 bus->dhd->rx_errors++;
4242 brcmf_sdbrcm_rxfail(bus, false, false);
4246 pkt = brcmu_pkt_buf_get_skb(rdlen + firstread + DHD_SDALIGN);
4248 /* Give up on data, request rtx of events */
4249 DHD_ERROR(("%s: brcmu_pkt_buf_get_skb failed: rdlen %d"
4250 " chan %d\n", __func__, rdlen, chan));
4251 bus->dhd->rx_dropped++;
4252 brcmf_sdbrcm_rxfail(bus, false, RETRYCHAN(chan));
4256 ASSERT(!(pkt->prev));
4258 /* Leave room for what we already read, and align remainder */
4259 ASSERT(firstread < pkt->len);
4260 skb_pull(pkt, firstread);
4261 PKTALIGN(pkt, rdlen, DHD_SDALIGN);
4263 /* Read the remaining frame data */
4264 sdret = brcmf_sdcard_recv_buf(sdh, brcmf_sdcard_cur_sbwad(sdh),
4265 SDIO_FUNC_2, F2SYNC, ((u8 *) (pkt->data)),
4266 rdlen, pkt, NULL, NULL);
4268 ASSERT(sdret != -BCME_PENDING);
4271 DHD_ERROR(("%s: read %d %s bytes failed: %d\n",
4274 SDPCM_EVENT_CHANNEL) ? "event" : ((chan ==
4276 ? "data" : "test")),
4278 brcmu_pkt_buf_free_skb(pkt);
4279 bus->dhd->rx_errors++;
4280 brcmf_sdbrcm_rxfail(bus, true, RETRYCHAN(chan));
4284 /* Copy the already-read portion */
4285 skb_push(pkt, firstread);
4286 memcpy(pkt->data, bus->rxhdr, firstread);
4289 if (DHD_BYTES_ON() && DHD_DATA_ON()) {
4290 printk(KERN_DEBUG "Rx Data:\n");
4291 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
4297 /* Save superframe descriptor and allocate packet frame */
4298 if (chan == SDPCM_GLOM_CHANNEL) {
4299 if (SDPCM_GLOMDESC(&bus->rxhdr[SDPCM_FRAMETAG_LEN])) {
4300 DHD_GLOM(("%s: glom descriptor, %d bytes:\n",
4303 if (DHD_GLOM_ON()) {
4304 printk(KERN_DEBUG "Glom Data:\n");
4305 print_hex_dump_bytes("",
4310 __skb_trim(pkt, len);
4311 ASSERT(doff == SDPCM_HDRLEN);
4312 skb_pull(pkt, SDPCM_HDRLEN);
4315 DHD_ERROR(("%s: glom superframe w/o "
4316 "descriptor!\n", __func__));
4317 brcmf_sdbrcm_rxfail(bus, false, false);
4322 /* Fill in packet len and prio, deliver upward */
4323 __skb_trim(pkt, len);
4324 skb_pull(pkt, doff);
4327 /* Test channel packets are processed separately */
4328 if (chan == SDPCM_TEST_CHANNEL) {
4329 brcmf_sdbrcm_checkdied(bus, pkt, seq);
4334 if (pkt->len == 0) {
4335 brcmu_pkt_buf_free_skb(pkt);
4337 } else if (brcmf_proto_hdrpull(bus->dhd, &ifidx, pkt) != 0) {
4338 DHD_ERROR(("%s: rx protocol error\n", __func__));
4339 brcmu_pkt_buf_free_skb(pkt);
4340 bus->dhd->rx_errors++;
4344 /* Unlock during rx call */
4345 brcmf_os_sdunlock(bus->dhd);
4346 brcmf_rx_frame(bus->dhd, ifidx, pkt, 1);
4347 brcmf_os_sdlock(bus->dhd);
4349 rxcount = maxframes - rxleft;
4351 /* Message if we hit the limit */
4352 if (!rxleft && !sdtest)
4353 DHD_DATA(("%s: hit rx limit of %d frames\n", __func__,
4356 #endif /* DHD_DEBUG */
4357 DHD_DATA(("%s: processed %d frames\n", __func__, rxcount));
4358 /* Back off rxseq if awaiting rtx, update rx_seq */
4361 bus->rx_seq = rxseq;
4366 static u32 brcmf_sdbrcm_hostmail(dhd_bus_t *bus)
4368 struct sdpcmd_regs *regs = bus->regs;
4374 DHD_TRACE(("%s: Enter\n", __func__));
4376 /* Read mailbox data and ack that we did so */
4377 R_SDREG(hmb_data, ®s->tohostmailboxdata, retries);
4378 if (retries <= retry_limit)
4379 W_SDREG(SMB_INT_ACK, ®s->tosbmailbox, retries);
4380 bus->f1regdata += 2;
4382 /* Dongle recomposed rx frames, accept them again */
4383 if (hmb_data & HMB_DATA_NAKHANDLED) {
4384 DHD_INFO(("Dongle reports NAK handled, expect rtx of %d\n",
4387 DHD_ERROR(("%s: unexpected NAKHANDLED!\n", __func__));
4389 bus->rxskip = false;
4390 intstatus |= I_HMB_FRAME_IND;
4394 * DEVREADY does not occur with gSPI.
4396 if (hmb_data & (HMB_DATA_DEVREADY | HMB_DATA_FWREADY)) {
4398 (hmb_data & HMB_DATA_VERSION_MASK) >>
4399 HMB_DATA_VERSION_SHIFT;
4400 if (bus->sdpcm_ver != SDPCM_PROT_VERSION)
4401 DHD_ERROR(("Version mismatch, dongle reports %d, "
4403 bus->sdpcm_ver, SDPCM_PROT_VERSION));
4405 DHD_INFO(("Dongle ready, protocol version %d\n",
4410 * Flow Control has been moved into the RX headers and this out of band
4411 * method isn't used any more.
4412 * remaining backward compatible with older dongles.
4414 if (hmb_data & HMB_DATA_FC) {
4415 fcbits = (hmb_data & HMB_DATA_FCDATA_MASK) >>
4416 HMB_DATA_FCDATA_SHIFT;
4418 if (fcbits & ~bus->flowcontrol)
4421 if (bus->flowcontrol & ~fcbits)
4425 bus->flowcontrol = fcbits;
4428 /* Shouldn't be any others */
4429 if (hmb_data & ~(HMB_DATA_DEVREADY |
4430 HMB_DATA_NAKHANDLED |
4433 HMB_DATA_FCDATA_MASK | HMB_DATA_VERSION_MASK)) {
4434 DHD_ERROR(("Unknown mailbox data content: 0x%02x\n", hmb_data));
4440 bool brcmf_sdbrcm_dpc(dhd_bus_t *bus)
4442 struct brcmf_sdio *sdh = bus->sdh;
4443 struct sdpcmd_regs *regs = bus->regs;
4444 u32 intstatus, newstatus = 0;
4446 uint rxlimit = brcmf_rxbound; /* Rx frames to read before resched */
4447 uint txlimit = brcmf_txbound; /* Tx frames to send before resched */
4448 uint framecnt = 0; /* Temporary counter of tx/rx frames */
4449 bool rxdone = true; /* Flag for no more read data */
4450 bool resched = false; /* Flag indicating resched wanted */
4452 DHD_TRACE(("%s: Enter\n", __func__));
4454 /* Start with leftover status bits */
4455 intstatus = bus->intstatus;
4457 brcmf_os_sdlock(bus->dhd);
4459 /* If waiting for HTAVAIL, check status */
4460 if (bus->clkstate == CLK_PENDING) {
4462 u8 clkctl, devctl = 0;
4465 /* Check for inconsistent device control */
4466 devctl = brcmf_sdcard_cfg_read(sdh, SDIO_FUNC_1,
4467 SBSDIO_DEVICE_CTL, &err);
4469 DHD_ERROR(("%s: error reading DEVCTL: %d\n",
4471 bus->dhd->busstate = DHD_BUS_DOWN;
4473 ASSERT(devctl & SBSDIO_DEVCTL_CA_INT_ONLY);
4475 #endif /* DHD_DEBUG */
4477 /* Read CSR, if clock on switch to AVAIL, else ignore */
4478 clkctl = brcmf_sdcard_cfg_read(sdh, SDIO_FUNC_1,
4479 SBSDIO_FUNC1_CHIPCLKCSR, &err);
4481 DHD_ERROR(("%s: error reading CSR: %d\n", __func__,
4483 bus->dhd->busstate = DHD_BUS_DOWN;
4486 DHD_INFO(("DPC: PENDING, devctl 0x%02x clkctl 0x%02x\n", devctl,
4489 if (SBSDIO_HTAV(clkctl)) {
4490 devctl = brcmf_sdcard_cfg_read(sdh, SDIO_FUNC_1,
4491 SBSDIO_DEVICE_CTL, &err);
4493 DHD_ERROR(("%s: error reading DEVCTL: %d\n",
4495 bus->dhd->busstate = DHD_BUS_DOWN;
4497 devctl &= ~SBSDIO_DEVCTL_CA_INT_ONLY;
4498 brcmf_sdcard_cfg_write(sdh, SDIO_FUNC_1,
4499 SBSDIO_DEVICE_CTL, devctl, &err);
4501 DHD_ERROR(("%s: error writing DEVCTL: %d\n",
4503 bus->dhd->busstate = DHD_BUS_DOWN;
4505 bus->clkstate = CLK_AVAIL;
4513 /* Make sure backplane clock is on */
4514 brcmf_sdbrcm_clkctl(bus, CLK_AVAIL, true);
4515 if (bus->clkstate == CLK_PENDING)
4518 /* Pending interrupt indicates new device status */
4521 R_SDREG(newstatus, ®s->intstatus, retries);
4523 if (brcmf_sdcard_regfail(bus->sdh))
4525 newstatus &= bus->hostintmask;
4526 bus->fcstate = !!(newstatus & I_HMB_FC_STATE);
4528 W_SDREG(newstatus, ®s->intstatus, retries);
4533 /* Merge new bits with previous */
4534 intstatus |= newstatus;
4537 /* Handle flow-control change: read new state in case our ack
4538 * crossed another change interrupt. If change still set, assume
4539 * FC ON for safety, let next loop through do the debounce.
4541 if (intstatus & I_HMB_FC_CHANGE) {
4542 intstatus &= ~I_HMB_FC_CHANGE;
4543 W_SDREG(I_HMB_FC_CHANGE, ®s->intstatus, retries);
4544 R_SDREG(newstatus, ®s->intstatus, retries);
4545 bus->f1regdata += 2;
4547 !!(newstatus & (I_HMB_FC_STATE | I_HMB_FC_CHANGE));
4548 intstatus |= (newstatus & bus->hostintmask);
4551 /* Handle host mailbox indication */
4552 if (intstatus & I_HMB_HOST_INT) {
4553 intstatus &= ~I_HMB_HOST_INT;
4554 intstatus |= brcmf_sdbrcm_hostmail(bus);
4557 /* Generally don't ask for these, can get CRC errors... */
4558 if (intstatus & I_WR_OOSYNC) {
4559 DHD_ERROR(("Dongle reports WR_OOSYNC\n"));
4560 intstatus &= ~I_WR_OOSYNC;
4563 if (intstatus & I_RD_OOSYNC) {
4564 DHD_ERROR(("Dongle reports RD_OOSYNC\n"));
4565 intstatus &= ~I_RD_OOSYNC;
4568 if (intstatus & I_SBINT) {
4569 DHD_ERROR(("Dongle reports SBINT\n"));
4570 intstatus &= ~I_SBINT;
4573 /* Would be active due to wake-wlan in gSPI */
4574 if (intstatus & I_CHIPACTIVE) {
4575 DHD_INFO(("Dongle reports CHIPACTIVE\n"));
4576 intstatus &= ~I_CHIPACTIVE;
4579 /* Ignore frame indications if rxskip is set */
4581 intstatus &= ~I_HMB_FRAME_IND;
4583 /* On frame indication, read available frames */
4584 if (PKT_AVAILABLE()) {
4585 framecnt = brcmf_sdbrcm_readframes(bus, rxlimit, &rxdone);
4586 if (rxdone || bus->rxskip)
4587 intstatus &= ~I_HMB_FRAME_IND;
4588 rxlimit -= min(framecnt, rxlimit);
4591 /* Keep still-pending events for next scheduling */
4592 bus->intstatus = intstatus;
4595 #if defined(OOB_INTR_ONLY)
4596 brcmf_sdio_oob_intr_set(1);
4597 #endif /* (OOB_INTR_ONLY) */
4598 /* Re-enable interrupts to detect new device events (mailbox, rx frame)
4599 * or clock availability. (Allows tx loop to check ipend if desired.)
4600 * (Unless register access seems hosed, as we may not be able to ACK...)
4602 if (bus->intr && bus->intdis && !brcmf_sdcard_regfail(sdh)) {
4603 DHD_INTR(("%s: enable SDIO interrupts, rxdone %d framecnt %d\n",
4604 __func__, rxdone, framecnt));
4605 bus->intdis = false;
4606 brcmf_sdcard_intr_enable(sdh);
4609 if (DATAOK(bus) && bus->ctrl_frame_stat &&
4610 (bus->clkstate == CLK_AVAIL)) {
4613 ret = brcmf_sdbrcm_send_buf(bus, brcmf_sdcard_cur_sbwad(sdh),
4614 SDIO_FUNC_2, F2SYNC, (u8 *) bus->ctrl_frame_buf,
4615 (u32) bus->ctrl_frame_len, NULL, NULL, NULL);
4616 ASSERT(ret != -BCME_PENDING);
4619 /* On failure, abort the command and
4620 terminate the frame */
4621 DHD_INFO(("%s: sdio error %d, abort command and "
4622 "terminate frame.\n", __func__, ret));
4625 brcmf_sdcard_abort(sdh, SDIO_FUNC_2);
4627 brcmf_sdcard_cfg_write(sdh, SDIO_FUNC_1,
4628 SBSDIO_FUNC1_FRAMECTRL, SFC_WF_TERM,
4632 for (i = 0; i < 3; i++) {
4634 hi = brcmf_sdcard_cfg_read(sdh, SDIO_FUNC_1,
4635 SBSDIO_FUNC1_WFRAMEBCHI,
4637 lo = brcmf_sdcard_cfg_read(sdh, SDIO_FUNC_1,
4638 SBSDIO_FUNC1_WFRAMEBCLO,
4640 bus->f1regdata += 2;
4641 if ((hi == 0) && (lo == 0))
4647 bus->tx_seq = (bus->tx_seq + 1) % SDPCM_SEQUENCE_WRAP;
4649 DHD_INFO(("Return_dpc value is : %d\n", ret));
4650 bus->ctrl_frame_stat = false;
4651 brcmf_wait_event_wakeup(bus->dhd);
4653 /* Send queued frames (limit 1 if rx may still be pending) */
4654 else if ((bus->clkstate == CLK_AVAIL) && !bus->fcstate &&
4655 brcmu_pktq_mlen(&bus->txq, ~bus->flowcontrol) && txlimit
4657 framecnt = rxdone ? txlimit : min(txlimit, dhd_txminmax);
4658 framecnt = brcmf_sdbrcm_sendfromq(bus, framecnt);
4659 txlimit -= framecnt;
4662 /* Resched if events or tx frames are pending,
4663 else await next interrupt */
4664 /* On failed register access, all bets are off:
4665 no resched or interrupts */
4666 if ((bus->dhd->busstate == DHD_BUS_DOWN) || brcmf_sdcard_regfail(sdh)) {
4667 DHD_ERROR(("%s: failed backplane access over SDIO, halting "
4668 "operation %d\n", __func__, brcmf_sdcard_regfail(sdh)));
4669 bus->dhd->busstate = DHD_BUS_DOWN;
4671 } else if (bus->clkstate == CLK_PENDING) {
4672 DHD_INFO(("%s: rescheduled due to CLK_PENDING awaiting "
4673 "I_CHIPACTIVE interrupt\n", __func__));
4675 } else if (bus->intstatus || bus->ipend ||
4676 (!bus->fcstate && brcmu_pktq_mlen(&bus->txq, ~bus->flowcontrol)
4677 && DATAOK(bus)) || PKT_AVAILABLE()) {
4681 bus->dpc_sched = resched;
4683 /* If we're done for now, turn off clock request. */
4684 if ((bus->clkstate != CLK_PENDING)
4685 && bus->idletime == DHD_IDLE_IMMEDIATE) {
4686 bus->activity = false;
4687 brcmf_sdbrcm_clkctl(bus, CLK_NONE, false);
4690 brcmf_os_sdunlock(bus->dhd);
4695 bool dhd_bus_dpc(struct dhd_bus *bus)
4699 /* Call the DPC directly. */
4700 DHD_TRACE(("Calling brcmf_sdbrcm_dpc() from %s\n", __func__));
4701 resched = brcmf_sdbrcm_dpc(bus);
4706 void brcmf_sdbrcm_isr(void *arg)
4708 dhd_bus_t *bus = (dhd_bus_t *) arg;
4709 struct brcmf_sdio *sdh;
4711 DHD_TRACE(("%s: Enter\n", __func__));
4714 DHD_ERROR(("%s : bus is null pointer , exit\n", __func__));
4719 if (bus->dhd->busstate == DHD_BUS_DOWN) {
4720 DHD_ERROR(("%s : bus is down. we have nothing to do\n",
4724 /* Count the interrupt call */
4728 /* Shouldn't get this interrupt if we're sleeping? */
4729 if (bus->sleeping) {
4730 DHD_ERROR(("INTERRUPT WHILE SLEEPING??\n"));
4734 /* Disable additional interrupts (is this needed now)? */
4736 DHD_INTR(("%s: disable SDIO interrupts\n", __func__));
4738 DHD_ERROR(("brcmf_sdbrcm_isr() w/o interrupt configured!\n"));
4740 brcmf_sdcard_intr_disable(sdh);
4743 #if defined(SDIO_ISR_THREAD)
4744 DHD_TRACE(("Calling brcmf_sdbrcm_dpc() from %s\n", __func__));
4745 while (brcmf_sdbrcm_dpc(bus))
4748 bus->dpc_sched = true;
4749 brcmf_sched_dpc(bus->dhd);
4755 static void brcmf_sdbrcm_pktgen_init(dhd_bus_t *bus)
4757 /* Default to specified length, or full range */
4758 if (brcmf_pktgen_len) {
4759 bus->pktgen_maxlen = min(brcmf_pktgen_len,
4760 BRCMF_MAX_PKTGEN_LEN);
4761 bus->pktgen_minlen = bus->pktgen_maxlen;
4763 bus->pktgen_maxlen = BRCMF_MAX_PKTGEN_LEN;
4764 bus->pktgen_minlen = 0;
4766 bus->pktgen_len = (u16) bus->pktgen_minlen;
4768 /* Default to per-watchdog burst with 10s print time */
4769 bus->pktgen_freq = 1;
4770 bus->pktgen_print = 10000 / brcmf_watchdog_ms;
4771 bus->pktgen_count = (brcmf_pktgen * brcmf_watchdog_ms + 999) / 1000;
4773 /* Default to echo mode */
4774 bus->pktgen_mode = DHD_PKTGEN_ECHO;
4775 bus->pktgen_stop = 1;
4778 static void brcmf_sdbrcm_pktgen(dhd_bus_t *bus)
4780 struct sk_buff *pkt;
4786 /* Display current count if appropriate */
4787 if (bus->pktgen_print && (++bus->pktgen_ptick >= bus->pktgen_print)) {
4788 bus->pktgen_ptick = 0;
4789 printk(KERN_DEBUG "%s: send attempts %d rcvd %d\n",
4790 __func__, bus->pktgen_sent, bus->pktgen_rcvd);
4793 /* For recv mode, just make sure dongle has started sending */
4794 if (bus->pktgen_mode == DHD_PKTGEN_RECV) {
4795 if (!bus->pktgen_rcvd)
4796 brcmf_sdbrcm_sdtest_set(bus, true);
4800 /* Otherwise, generate or request the specified number of packets */
4801 for (pktcount = 0; pktcount < bus->pktgen_count; pktcount++) {
4802 /* Stop if total has been reached */
4803 if (bus->pktgen_total
4804 && (bus->pktgen_sent >= bus->pktgen_total)) {
4805 bus->pktgen_count = 0;
4809 /* Allocate an appropriate-sized packet */
4810 len = bus->pktgen_len;
4811 pkt = brcmu_pkt_buf_get_skb(
4812 (len + SDPCM_HDRLEN + SDPCM_TEST_HDRLEN + DHD_SDALIGN),
4815 DHD_ERROR(("%s: brcmu_pkt_buf_get_skb failed!\n",
4819 PKTALIGN(pkt, (len + SDPCM_HDRLEN + SDPCM_TEST_HDRLEN),
4821 data = (u8 *) (pkt->data) + SDPCM_HDRLEN;
4823 /* Write test header cmd and extra based on mode */
4824 switch (bus->pktgen_mode) {
4825 case DHD_PKTGEN_ECHO:
4826 *data++ = SDPCM_TEST_ECHOREQ;
4827 *data++ = (u8) bus->pktgen_sent;
4830 case DHD_PKTGEN_SEND:
4831 *data++ = SDPCM_TEST_DISCARD;
4832 *data++ = (u8) bus->pktgen_sent;
4835 case DHD_PKTGEN_RXBURST:
4836 *data++ = SDPCM_TEST_BURST;
4837 *data++ = (u8) bus->pktgen_count;
4841 DHD_ERROR(("Unrecognized pktgen mode %d\n",
4843 brcmu_pkt_buf_free_skb(pkt, true);
4844 bus->pktgen_count = 0;
4848 /* Write test header length field */
4849 *data++ = (len >> 0);
4850 *data++ = (len >> 8);
4852 /* Then fill in the remainder -- N/A for burst,
4854 for (fillbyte = 0; fillbyte < len; fillbyte++)
4856 SDPCM_TEST_FILL(fillbyte, (u8) bus->pktgen_sent);
4859 if (DHD_BYTES_ON() && DHD_DATA_ON()) {
4860 data = (u8 *) (pkt->data) + SDPCM_HDRLEN;
4861 printk(KERN_DEBUG "brcmf_sdbrcm_pktgen: Tx Data:\n");
4862 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, data,
4863 pkt->len - SDPCM_HDRLEN);
4868 if (brcmf_sdbrcm_txpkt(bus, pkt, SDPCM_TEST_CHANNEL, true)) {
4870 if (bus->pktgen_stop
4871 && bus->pktgen_stop == bus->pktgen_fail)
4872 bus->pktgen_count = 0;
4876 /* Bump length if not fixed, wrap at max */
4877 if (++bus->pktgen_len > bus->pktgen_maxlen)
4878 bus->pktgen_len = (u16) bus->pktgen_minlen;
4880 /* Special case for burst mode: just send one request! */
4881 if (bus->pktgen_mode == DHD_PKTGEN_RXBURST)
4886 static void brcmf_sdbrcm_sdtest_set(dhd_bus_t *bus, bool start)
4888 struct sk_buff *pkt;
4891 /* Allocate the packet */
4892 pkt = brcmu_pkt_buf_get_skb(SDPCM_HDRLEN + SDPCM_TEST_HDRLEN +
4895 DHD_ERROR(("%s: brcmu_pkt_buf_get_skb failed!\n", __func__));
4898 PKTALIGN(pkt, (SDPCM_HDRLEN + SDPCM_TEST_HDRLEN), DHD_SDALIGN);
4899 data = (u8 *) (pkt->data) + SDPCM_HDRLEN;
4901 /* Fill in the test header */
4902 *data++ = SDPCM_TEST_SEND;
4904 *data++ = (bus->pktgen_maxlen >> 0);
4905 *data++ = (bus->pktgen_maxlen >> 8);
4908 if (brcmf_sdbrcm_txpkt(bus, pkt, SDPCM_TEST_CHANNEL, true))
4913 brcmf_sdbrcm_checkdied(dhd_bus_t *bus, struct sk_buff *pkt, uint seq)
4923 /* Check for min length */
4925 if (pktlen < SDPCM_TEST_HDRLEN) {
4926 DHD_ERROR(("brcmf_sdbrcm_checkdied: toss runt frame, pktlen "
4928 brcmu_pkt_buf_free_skb(pkt, false);
4932 /* Extract header fields */
4937 len += *data++ << 8;
4939 /* Check length for relevant commands */
4940 if (cmd == SDPCM_TEST_DISCARD || cmd == SDPCM_TEST_ECHOREQ
4941 || cmd == SDPCM_TEST_ECHORSP) {
4942 if (pktlen != len + SDPCM_TEST_HDRLEN) {
4943 DHD_ERROR(("brcmf_sdbrcm_checkdied: frame length "
4944 "mismatch, pktlen %d seq %d" " cmd %d extra %d "
4946 pktlen, seq, cmd, extra, len));
4947 brcmu_pkt_buf_free_skb(pkt, false);
4952 /* Process as per command */
4954 case SDPCM_TEST_ECHOREQ:
4955 /* Rx->Tx turnaround ok (even on NDIS w/current
4957 *(u8 *) (pkt->data) = SDPCM_TEST_ECHORSP;
4958 if (brcmf_sdbrcm_txpkt(bus, pkt, SDPCM_TEST_CHANNEL, true) == 0)
4962 brcmu_pkt_buf_free_skb(pkt, false);
4967 case SDPCM_TEST_ECHORSP:
4968 if (bus->ext_loop) {
4969 brcmu_pkt_buf_free_skb(pkt, false);
4974 for (offset = 0; offset < len; offset++, data++) {
4975 if (*data != SDPCM_TEST_FILL(offset, extra)) {
4976 DHD_ERROR(("brcmf_sdbrcm_checkdied: echo data "
4977 "mismatch: " "offset %d (len %d) "
4978 "expect 0x%02x rcvd 0x%02x\n",
4980 SDPCM_TEST_FILL(offset, extra),
4985 brcmu_pkt_buf_free_skb(pkt, false);
4989 case SDPCM_TEST_DISCARD:
4990 brcmu_pkt_buf_free_skb(pkt, false);
4994 case SDPCM_TEST_BURST:
4995 case SDPCM_TEST_SEND:
4997 DHD_INFO(("brcmf_sdbrcm_checkdied: unsupported or unknown "
4998 "command, pktlen %d seq %d" " cmd %d extra %d len %d\n",
4999 pktlen, seq, cmd, extra, len));
5000 brcmu_pkt_buf_free_skb(pkt, false);
5004 /* For recv mode, stop at limie (and tell dongle to stop sending) */
5005 if (bus->pktgen_mode == DHD_PKTGEN_RECV) {
5006 if (bus->pktgen_total
5007 && (bus->pktgen_rcvd >= bus->pktgen_total)) {
5008 bus->pktgen_count = 0;
5009 brcmf_sdbrcm_sdtest_set(bus, false);
5015 extern bool brcmf_sdbrcm_bus_watchdog(dhd_pub_t *dhdp)
5019 DHD_TIMER(("%s: Enter\n", __func__));
5023 if (bus->dhd->dongle_reset)
5026 /* Ignore the timer if simulating bus down */
5030 brcmf_os_sdlock(bus->dhd);
5032 /* Poll period: check device if appropriate. */
5033 if (bus->poll && (++bus->polltick >= bus->pollrate)) {
5036 /* Reset poll tick */
5039 /* Check device if no interrupts */
5040 if (!bus->intr || (bus->intrcount == bus->lastintrs)) {
5042 if (!bus->dpc_sched) {
5044 devpend = brcmf_sdcard_cfg_read(bus->sdh,
5045 SDIO_FUNC_0, SDIO_CCCR_INTx,
5048 devpend & (INTR_STATUS_FUNC1 |
5052 /* If there is something, make like the ISR and
5058 brcmf_sdcard_intr_disable(bus->sdh);
5060 bus->dpc_sched = true;
5061 brcmf_sched_dpc(bus->dhd);
5066 /* Update interrupt tracking */
5067 bus->lastintrs = bus->intrcount;
5070 /* Poll for console output periodically */
5071 if (dhdp->busstate == DHD_BUS_DATA && brcmf_console_ms != 0) {
5072 bus->console.count += brcmf_watchdog_ms;
5073 if (bus->console.count >= brcmf_console_ms) {
5074 bus->console.count -= brcmf_console_ms;
5075 /* Make sure backplane clock is on */
5076 brcmf_sdbrcm_clkctl(bus, CLK_AVAIL, false);
5077 if (brcmf_sdbrcm_readconsole(bus) < 0)
5078 brcmf_console_ms = 0; /* On error,
5082 #endif /* DHD_DEBUG */
5085 /* Generate packets if configured */
5086 if (bus->pktgen_count && (++bus->pktgen_tick >= bus->pktgen_freq)) {
5087 /* Make sure backplane clock is on */
5088 brcmf_sdbrcm_clkctl(bus, CLK_AVAIL, false);
5089 bus->pktgen_tick = 0;
5090 brcmf_sdbrcm_pktgen(bus);
5094 /* On idle timeout clear activity flag and/or turn off clock */
5095 if ((bus->idletime > 0) && (bus->clkstate == CLK_AVAIL)) {
5096 if (++bus->idlecount >= bus->idletime) {
5098 if (bus->activity) {
5099 bus->activity = false;
5100 brcmf_os_wd_timer(bus->dhd, brcmf_watchdog_ms);
5102 brcmf_sdbrcm_clkctl(bus, CLK_NONE, false);
5107 brcmf_os_sdunlock(bus->dhd);
5113 extern int brcmf_sdbrcm_bus_console_in(dhd_pub_t *dhdp, unsigned char *msg,
5116 dhd_bus_t *bus = dhdp->bus;
5119 struct sk_buff *pkt;
5121 /* Address could be zero if CONSOLE := 0 in dongle Makefile */
5122 if (bus->console_addr == 0)
5125 /* Exclusive bus access */
5126 brcmf_os_sdlock(bus->dhd);
5128 /* Don't allow input if dongle is in reset */
5129 if (bus->dhd->dongle_reset) {
5130 brcmf_os_sdunlock(bus->dhd);
5134 /* Request clock to allow SDIO accesses */
5136 /* No pend allowed since txpkt is called later, ht clk has to be on */
5137 brcmf_sdbrcm_clkctl(bus, CLK_AVAIL, false);
5139 /* Zero cbuf_index */
5140 addr = bus->console_addr + offsetof(rte_cons_t, cbuf_idx);
5141 val = cpu_to_le32(0);
5142 rv = brcmf_sdbrcm_membytes(bus, true, addr, (u8 *)&val, sizeof(val));
5146 /* Write message into cbuf */
5147 addr = bus->console_addr + offsetof(rte_cons_t, cbuf);
5148 rv = brcmf_sdbrcm_membytes(bus, true, addr, (u8 *)msg, msglen);
5152 /* Write length into vcons_in */
5153 addr = bus->console_addr + offsetof(rte_cons_t, vcons_in);
5154 val = cpu_to_le32(msglen);
5155 rv = brcmf_sdbrcm_membytes(bus, true, addr, (u8 *)&val, sizeof(val));
5159 /* Bump dongle by sending an empty event pkt.
5160 * sdpcm_sendup (RX) checks for virtual console input.
5162 pkt = brcmu_pkt_buf_get_skb(4 + SDPCM_RESERVE);
5163 if ((pkt != NULL) && bus->clkstate == CLK_AVAIL)
5164 brcmf_sdbrcm_txpkt(bus, pkt, SDPCM_EVENT_CHANNEL, true);
5167 if ((bus->idletime == DHD_IDLE_IMMEDIATE) && !bus->dpc_sched) {
5168 bus->activity = false;
5169 brcmf_sdbrcm_clkctl(bus, CLK_NONE, true);
5172 brcmf_os_sdunlock(bus->dhd);
5176 #endif /* DHD_DEBUG */
5178 static bool brcmf_sdbrcm_chipmatch(u16 chipid)
5180 if (chipid == BCM4325_CHIP_ID)
5182 if (chipid == BCM4329_CHIP_ID)
5184 if (chipid == BCM4319_CHIP_ID)
5189 static void *brcmf_sdbrcm_probe(u16 venid, u16 devid, u16 bus_no,
5190 u16 slot, u16 func, uint bustype, void *regsva,
5196 /* Init global variables at run-time, not as part of the declaration.
5197 * This is required to support init/de-init of the driver.
5199 * of globals as part of the declaration results in non-deterministic
5200 * behavior since the value of the globals may be different on the
5201 * first time that the driver is initialized vs subsequent
5204 brcmf_txbound = DHD_TXBOUND;
5205 brcmf_rxbound = DHD_RXBOUND;
5206 dhd_alignctl = true;
5208 dhd_readahead = true;
5210 brcmf_dongle_memsize = 0;
5211 dhd_txminmax = DHD_TXMINMAX;
5217 DHD_TRACE(("%s: Enter\n", __func__));
5218 DHD_INFO(("%s: venid 0x%04x devid 0x%04x\n", __func__, venid, devid));
5220 /* We make assumptions about address window mappings */
5221 ASSERT((unsigned long)regsva == SI_ENUM_BASE);
5223 /* BCMSDH passes venid and devid based on CIS parsing -- but
5225 * means early parse could fail, so here we should get either an ID
5226 * we recognize OR (-1) indicating we must request power first.
5228 /* Check the Vendor ID */
5231 case PCI_VENDOR_ID_BROADCOM:
5234 DHD_ERROR(("%s: unknown vendor: 0x%04x\n", __func__, venid));
5238 /* Check the Device ID and make sure it's one that we support */
5240 case BCM4325_D11DUAL_ID: /* 4325 802.11a/g id */
5241 case BCM4325_D11G_ID: /* 4325 802.11g 2.4Ghz band id */
5242 case BCM4325_D11A_ID: /* 4325 802.11a 5Ghz band id */
5243 DHD_INFO(("%s: found 4325 Dongle\n", __func__));
5245 case BCM4329_D11NDUAL_ID: /* 4329 802.11n dualband device */
5246 case BCM4329_D11N2G_ID: /* 4329 802.11n 2.4G device */
5247 case BCM4329_D11N5G_ID: /* 4329 802.11n 5G device */
5249 DHD_INFO(("%s: found 4329 Dongle\n", __func__));
5251 case BCM4319_D11N_ID: /* 4319 802.11n id */
5252 case BCM4319_D11N2G_ID: /* 4319 802.11n2g id */
5253 case BCM4319_D11N5G_ID: /* 4319 802.11n5g id */
5254 DHD_INFO(("%s: found 4319 Dongle\n", __func__));
5257 DHD_INFO(("%s: allow device id 0, will check chip internals\n",
5262 DHD_ERROR(("%s: skipping 0x%04x/0x%04x, not a dongle\n",
5263 __func__, venid, devid));
5267 /* Allocate private bus interface state */
5268 bus = kzalloc(sizeof(dhd_bus_t), GFP_ATOMIC);
5270 DHD_ERROR(("%s: kmalloc of dhd_bus_t failed\n", __func__));
5274 bus->cl_devid = (u16) devid;
5276 bus->tx_seq = SDPCM_SEQUENCE_WRAP - 1;
5277 bus->usebufpool = false; /* Use bufpool if allocated,
5278 else use locally malloced rxbuf */
5280 /* attempt to attach to the dongle */
5281 if (!(brcmf_sdbrcm_probe_attach(bus, sdh, regsva, devid))) {
5282 DHD_ERROR(("%s: brcmf_sdbrcm_probe_attach failed\n", __func__));
5286 spin_lock_init(&bus->txqlock);
5288 /* Attach to the dhd/OS/network interface */
5289 bus->dhd = brcmf_attach(bus, SDPCM_RESERVE);
5291 DHD_ERROR(("%s: dhd_attach failed\n", __func__));
5295 /* Allocate buffers */
5296 if (!(brcmf_sdbrcm_probe_malloc(bus, sdh))) {
5297 DHD_ERROR(("%s: brcmf_sdbrcm_probe_malloc failed\n", __func__));
5301 if (!(brcmf_sdbrcm_probe_init(bus, sdh))) {
5302 DHD_ERROR(("%s: brcmf_sdbrcm_probe_init failed\n", __func__));
5306 /* Register interrupt callback, but mask it (not operational yet). */
5307 DHD_INTR(("%s: disable SDIO interrupts (not interested yet)\n",
5309 brcmf_sdcard_intr_disable(sdh);
5310 ret = brcmf_sdcard_intr_reg(sdh, brcmf_sdbrcm_isr, bus);
5312 DHD_ERROR(("%s: FAILED: bcmsdh_intr_reg returned %d\n",
5316 DHD_INTR(("%s: registered SDIO interrupt function ok\n", __func__));
5318 DHD_INFO(("%s: completed!!\n", __func__));
5320 /* if firmware path present try to download and bring up bus */
5321 ret = brcmf_bus_start(bus->dhd);
5323 if (ret == -ENOLINK) {
5324 DHD_ERROR(("%s: dongle is not responding\n", __func__));
5328 /* Ok, have the per-port tell the stack we're open for business */
5329 if (brcmf_net_attach(bus->dhd, 0) != 0) {
5330 DHD_ERROR(("%s: Net attach failed!!\n", __func__));
5337 brcmf_sdbrcm_release(bus);
5342 brcmf_sdbrcm_probe_attach(struct dhd_bus *bus, void *sdh, void *regsva,
5348 bus->alp_only = true;
5350 /* Return the window to backplane enumeration space for core access */
5351 if (brcmf_sdbrcm_set_siaddr_window(bus, SI_ENUM_BASE))
5352 DHD_ERROR(("%s: FAILED to return to SI_ENUM_BASE\n", __func__));
5355 printk(KERN_DEBUG "F1 signature read @0x18000000=0x%4x\n",
5356 brcmf_sdcard_reg_read(bus->sdh, SI_ENUM_BASE, 4));
5358 #endif /* DHD_DEBUG */
5361 * Force PLL off until brcmf_sdbrcm_chip_attach()
5362 * programs PLL control regs
5365 brcmf_sdcard_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
5366 DHD_INIT_CLKCTL1, &err);
5369 brcmf_sdcard_cfg_read(sdh, SDIO_FUNC_1,
5370 SBSDIO_FUNC1_CHIPCLKCSR, &err);
5372 if (err || ((clkctl & ~SBSDIO_AVBITS) != DHD_INIT_CLKCTL1)) {
5373 DHD_ERROR(("brcmf_sdbrcm_probe: ChipClkCSR access: err %d wrote"
5374 " 0x%02x read 0x%02x\n",
5375 err, DHD_INIT_CLKCTL1, clkctl));
5379 if (brcmf_sdbrcm_chip_attach(bus, regsva)) {
5380 DHD_ERROR(("%s: brcmf_sdbrcm_chip_attach failed!\n", __func__));
5384 brcmf_sdcard_chipinfo(sdh, bus->ci->chip, bus->ci->chiprev);
5386 if (!brcmf_sdbrcm_chipmatch((u16) bus->ci->chip)) {
5387 DHD_ERROR(("%s: unsupported chip: 0x%04x\n",
5388 __func__, bus->ci->chip));
5392 brcmf_sdbrcm_sdiod_drive_strength_init(bus, brcmf_sdiod_drive_strength);
5394 /* Get info on the ARM and SOCRAM cores... */
5395 if (!DHD_NOPMU(bus)) {
5396 bus->armrev = SBCOREREV(brcmf_sdcard_reg_read(bus->sdh,
5397 CORE_SB(bus->ci->armcorebase, sbidhigh), 4));
5398 bus->orig_ramsize = bus->ci->ramsize;
5399 if (!(bus->orig_ramsize)) {
5400 DHD_ERROR(("%s: failed to find SOCRAM memory!\n",
5404 bus->ramsize = bus->orig_ramsize;
5405 if (brcmf_dongle_memsize)
5406 brcmf_sdbrcm_setmemsize(bus, brcmf_dongle_memsize);
5408 DHD_ERROR(("DHD: dongle ram size is set to %d(orig %d)\n",
5409 bus->ramsize, bus->orig_ramsize));
5412 bus->regs = (void *)bus->ci->buscorebase;
5414 /* Set core control so an SDIO reset does a backplane reset */
5415 OR_REG(&bus->regs->corecontrol, CC_BPRESEN);
5417 brcmu_pktq_init(&bus->txq, (PRIOMASK + 1), TXQLEN);
5419 /* Locate an appropriately-aligned portion of hdrbuf */
5420 bus->rxhdr = (u8 *) roundup((unsigned long)&bus->hdrbuf[0], DHD_SDALIGN);
5422 /* Set the poll and/or interrupt flags */
5423 bus->intr = (bool) brcmf_intr;
5424 bus->poll = (bool) brcmf_poll;
5434 static bool brcmf_sdbrcm_probe_malloc(dhd_bus_t *bus, void *sdh)
5436 DHD_TRACE(("%s: Enter\n", __func__));
5438 if (bus->dhd->maxctl) {
5440 roundup((bus->dhd->maxctl + SDPCM_HDRLEN),
5441 ALIGNMENT) + DHD_SDALIGN;
5442 bus->rxbuf = kmalloc(bus->rxblen, GFP_ATOMIC);
5443 if (!(bus->rxbuf)) {
5444 DHD_ERROR(("%s: kmalloc of %d-byte rxbuf failed\n",
5445 __func__, bus->rxblen));
5450 /* Allocate buffer to receive glomed packet */
5451 bus->databuf = kmalloc(MAX_DATA_BUF, GFP_ATOMIC);
5452 if (!(bus->databuf)) {
5453 DHD_ERROR(("%s: kmalloc of %d-byte databuf failed\n",
5454 __func__, MAX_DATA_BUF));
5455 /* release rxbuf which was already located as above */
5461 /* Align the buffer */
5462 if ((unsigned long)bus->databuf % DHD_SDALIGN)
5464 bus->databuf + (DHD_SDALIGN -
5465 ((unsigned long)bus->databuf % DHD_SDALIGN));
5467 bus->dataptr = bus->databuf;
5475 static bool brcmf_sdbrcm_probe_init(dhd_bus_t *bus, void *sdh)
5479 DHD_TRACE(("%s: Enter\n", __func__));
5482 brcmf_sdbrcm_pktgen_init(bus);
5485 /* Disable F2 to clear any intermediate frame state on the dongle */
5486 brcmf_sdcard_cfg_write(sdh, SDIO_FUNC_0, SDIO_CCCR_IOEx,
5487 SDIO_FUNC_ENABLE_1, NULL);
5489 bus->dhd->busstate = DHD_BUS_DOWN;
5490 bus->sleeping = false;
5491 bus->rxflow = false;
5492 bus->prev_rxlim_hit = 0;
5494 /* Done with backplane-dependent accesses, can drop clock... */
5495 brcmf_sdcard_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR, 0,
5498 /* ...and initialize clock/power states */
5499 bus->clkstate = CLK_SDONLY;
5500 bus->idletime = (s32) brcmf_idletime;
5501 bus->idleclock = DHD_IDLE_ACTIVE;
5503 /* Query the F2 block size, set roundup accordingly */
5505 if (brcmf_sdcard_iovar_op(sdh, "sd_blocksize", &fnum, sizeof(s32),
5506 &bus->blocksize, sizeof(s32), false) != 0) {
5508 DHD_ERROR(("%s: fail on %s get\n", __func__, "sd_blocksize"));
5510 DHD_INFO(("%s: Initial value for %s is %d\n",
5511 __func__, "sd_blocksize", bus->blocksize));
5513 bus->roundup = min(max_roundup, bus->blocksize);
5515 /* Query if bus module supports packet chaining,
5516 default to use if supported */
5517 if (brcmf_sdcard_iovar_op(sdh, "sd_rxchain", NULL, 0,
5518 &bus->sd_rxchain, sizeof(s32),
5520 bus->sd_rxchain = false;
5522 DHD_INFO(("%s: bus module (through bcmsdh API) %s chaining\n",
5524 (bus->sd_rxchain ? "supports" : "does not support")));
5526 bus->use_rxchain = (bool) bus->sd_rxchain;
5532 dhd_bus_download_firmware(struct dhd_bus *bus, char *fw_path, char *nv_path)
5535 bus->fw_path = fw_path;
5536 bus->nv_path = nv_path;
5538 ret = brcmf_sdbrcm_download_firmware(bus, bus->sdh);
5544 brcmf_sdbrcm_download_firmware(struct dhd_bus *bus, void *sdh)
5548 /* Download the firmware */
5549 brcmf_sdbrcm_clkctl(bus, CLK_AVAIL, false);
5551 ret = _brcmf_sdbrcm_download_firmware(bus) == 0;
5553 brcmf_sdbrcm_clkctl(bus, CLK_SDONLY, false);
5558 /* Detach and free everything */
5559 static void brcmf_sdbrcm_release(dhd_bus_t *bus)
5561 DHD_TRACE(("%s: Enter\n", __func__));
5564 /* De-register interrupt handler */
5565 brcmf_sdcard_intr_disable(bus->sdh);
5566 brcmf_sdcard_intr_dereg(bus->sdh);
5569 brcmf_detach(bus->dhd);
5570 brcmf_sdbrcm_release_dongle(bus);
5574 brcmf_sdbrcm_release_malloc(bus);
5579 DHD_TRACE(("%s: Disconnected\n", __func__));
5582 static void brcmf_sdbrcm_release_malloc(dhd_bus_t *bus)
5584 DHD_TRACE(("%s: Enter\n", __func__));
5586 if (bus->dhd && bus->dhd->dongle_reset)
5590 bus->rxctl = bus->rxbuf = NULL;
5593 kfree(bus->databuf);
5594 bus->databuf = NULL;
5597 static void brcmf_sdbrcm_release_dongle(dhd_bus_t *bus)
5599 DHD_TRACE(("%s: Enter\n", __func__));
5601 if (bus->dhd && bus->dhd->dongle_reset)
5605 brcmf_sdbrcm_clkctl(bus, CLK_AVAIL, false);
5606 brcmf_sdbrcm_clkctl(bus, CLK_NONE, false);
5607 brcmf_sdbrcm_chip_detach(bus);
5608 if (bus->vars && bus->varsz)
5613 DHD_TRACE(("%s: Disconnected\n", __func__));
5616 static void brcmf_sdbrcm_disconnect(void *ptr)
5618 dhd_bus_t *bus = (dhd_bus_t *)ptr;
5620 DHD_TRACE(("%s: Enter\n", __func__));
5624 brcmf_sdbrcm_release(bus);
5627 DHD_TRACE(("%s: Disconnected\n", __func__));
5630 /* Register/Unregister functions are called by the main DHD entry
5631 * point (e.g. module insertion) to link with the bus driver, in
5632 * order to look for or await the device.
5635 static bcmsdh_driver_t dhd_sdio = {
5637 brcmf_sdbrcm_disconnect
5640 int dhd_bus_register(void)
5642 DHD_TRACE(("%s: Enter\n", __func__));
5644 return brcmf_sdio_register(&dhd_sdio);
5647 void dhd_bus_unregister(void)
5649 DHD_TRACE(("%s: Enter\n", __func__));
5651 brcmf_sdio_unregister();
5654 static int brcmf_sdbrcm_download_code_file(struct dhd_bus *bus, char *fw_path)
5660 u8 *memblock = NULL, *memptr;
5662 DHD_INFO(("%s: download firmware %s\n", __func__, brcmf_fw_path));
5664 image = brcmf_os_open_image(fw_path);
5668 memptr = memblock = kmalloc(MEMBLOCK + DHD_SDALIGN, GFP_ATOMIC);
5669 if (memblock == NULL) {
5670 DHD_ERROR(("%s: Failed to allocate memory %d bytes\n",
5671 __func__, MEMBLOCK));
5674 if ((u32)(unsigned long)memblock % DHD_SDALIGN)
5676 (DHD_SDALIGN - ((u32)(unsigned long)memblock % DHD_SDALIGN));
5678 /* Download image */
5680 brcmf_os_get_image_block((char *)memptr, MEMBLOCK, image))) {
5681 bcmerror = brcmf_sdbrcm_membytes(bus, true, offset, memptr,
5684 DHD_ERROR(("%s: error %d on writing %d membytes at "
5685 "0x%08x\n", __func__, bcmerror, MEMBLOCK, offset));
5696 brcmf_os_close_image(image);
5702 * ProcessVars:Takes a buffer of "<var>=<value>\n" lines read from a file
5703 * and ending in a NUL.
5704 * Removes carriage returns, empty lines, comment lines, and converts
5706 * Shortens buffer as needed and pads with NULs. End of buffer is marked
5710 static uint brcmf_process_nvram_vars(char *varbuf, uint len)
5719 findNewline = false;
5722 for (n = 0; n < len; n++) {
5725 if (varbuf[n] == '\r')
5727 if (findNewline && varbuf[n] != '\n')
5729 findNewline = false;
5730 if (varbuf[n] == '#') {
5734 if (varbuf[n] == '\n') {
5744 buf_len = dp - varbuf;
5746 while (dp < varbuf + n)
5753 EXAMPLE: nvram_array
5756 Use carriage return at the end of each assignment,
5757 and an empty string with
5758 carriage return at the end of array.
5761 unsigned char nvram_array[] = {"name1=value1\n",
5762 "name2=value2\n", "\n"};
5763 Hex values start with 0x, and mac addr format: xx:xx:xx:xx:xx:xx.
5765 Search "EXAMPLE: nvram_array" to see how the array is activated.
5768 void dhd_bus_set_nvram_params(struct dhd_bus *bus, const char *nvram_params)
5770 bus->nvram_params = nvram_params;
5773 static int brcmf_sdbrcm_download_nvram(struct dhd_bus *bus)
5778 char *memblock = NULL;
5781 bool nvram_file_exists;
5783 nv_path = bus->nv_path;
5785 nvram_file_exists = ((nv_path != NULL) && (nv_path[0] != '\0'));
5786 if (!nvram_file_exists && (bus->nvram_params == NULL))
5789 if (nvram_file_exists) {
5790 image = brcmf_os_open_image(nv_path);
5795 memblock = kmalloc(MEMBLOCK, GFP_ATOMIC);
5796 if (memblock == NULL) {
5797 DHD_ERROR(("%s: Failed to allocate memory %d bytes\n",
5798 __func__, MEMBLOCK));
5802 /* Download variables */
5803 if (nvram_file_exists) {
5804 len = brcmf_os_get_image_block(memblock, MEMBLOCK, image);
5806 len = strlen(bus->nvram_params);
5807 ASSERT(len <= MEMBLOCK);
5810 memcpy(memblock, bus->nvram_params, len);
5813 if (len > 0 && len < MEMBLOCK) {
5814 bufp = (char *)memblock;
5816 len = brcmf_process_nvram_vars(bufp, len);
5820 bcmerror = brcmf_sdbrcm_downloadvars(bus, memblock,
5823 DHD_ERROR(("%s: error downloading vars: %d\n",
5824 __func__, bcmerror));
5827 DHD_ERROR(("%s: error reading nvram file: %d\n",
5836 brcmf_os_close_image(image);
5841 static int _brcmf_sdbrcm_download_firmware(struct dhd_bus *bus)
5845 bool embed = false; /* download embedded firmware */
5846 bool dlok = false; /* download firmware succeeded */
5848 /* Out immediately if no image to download */
5849 if ((bus->fw_path == NULL) || (bus->fw_path[0] == '\0'))
5852 /* Keep arm in reset */
5853 if (brcmf_sdbrcm_download_state(bus, true)) {
5854 DHD_ERROR(("%s: error placing ARM core in reset\n", __func__));
5858 /* External image takes precedence if specified */
5859 if ((bus->fw_path != NULL) && (bus->fw_path[0] != '\0')) {
5860 if (brcmf_sdbrcm_download_code_file(bus, bus->fw_path)) {
5861 DHD_ERROR(("%s: dongle image file download failed\n",
5870 DHD_ERROR(("%s: dongle image download failed\n", __func__));
5874 /* EXAMPLE: nvram_array */
5875 /* If a valid nvram_arry is specified as above, it can be passed
5877 /* dhd_bus_set_nvram_params(bus, (char *)&nvram_array); */
5879 /* External nvram takes precedence if specified */
5880 if (brcmf_sdbrcm_download_nvram(bus)) {
5881 DHD_ERROR(("%s: dongle nvram file download failed\n",
5885 /* Take arm out of reset */
5886 if (brcmf_sdbrcm_download_state(bus, false)) {
5887 DHD_ERROR(("%s: error getting out of ARM core reset\n",
5900 brcmf_sdbrcm_send_buf(dhd_bus_t *bus, u32 addr, uint fn, uint flags,
5901 u8 *buf, uint nbytes, struct sk_buff *pkt,
5902 bcmsdh_cmplt_fn_t complete, void *handle)
5904 return brcmf_sdcard_send_buf
5905 (bus->sdh, addr, fn, flags, buf, nbytes, pkt, complete,
5909 uint dhd_bus_chip(struct dhd_bus *bus)
5911 ASSERT(bus->ci != NULL);
5912 return bus->ci->chip;
5915 void *dhd_bus_pub(struct dhd_bus *bus)
5920 void *dhd_bus_txq(struct dhd_bus *bus)
5925 uint dhd_bus_hdrlen(struct dhd_bus *bus)
5927 return SDPCM_HDRLEN;
5930 int brcmf_bus_devreset(dhd_pub_t *dhdp, u8 flag)
5938 if (!bus->dhd->dongle_reset) {
5939 /* Expect app to have torn down any
5940 connection before calling */
5941 /* Stop the bus, disable F2 */
5942 brcmf_sdbrcm_bus_stop(bus, false);
5944 /* Clean tx/rx buffer pointers,
5945 detach from the dongle */
5946 brcmf_sdbrcm_release_dongle(bus);
5948 bus->dhd->dongle_reset = true;
5949 bus->dhd->up = false;
5951 DHD_TRACE(("%s: WLAN OFF DONE\n", __func__));
5952 /* App can now remove power from device */
5956 /* App must have restored power to device before calling */
5958 DHD_TRACE(("\n\n%s: == WLAN ON ==\n", __func__));
5960 if (bus->dhd->dongle_reset) {
5962 /* Reset SD client */
5963 brcmf_sdcard_reset(bus->sdh);
5965 /* Attempt to re-attach & download */
5966 if (brcmf_sdbrcm_probe_attach(bus, bus->sdh,
5967 (u32 *) SI_ENUM_BASE,
5969 /* Attempt to download binary to the dongle */
5970 if (brcmf_sdbrcm_probe_init
5972 && brcmf_sdbrcm_download_firmware(bus,
5975 /* Re-init bus, enable F2 transfer */
5976 brcmf_sdbrcm_bus_init(
5977 (dhd_pub_t *) bus->dhd, false);
5979 #if defined(OOB_INTR_ONLY)
5980 brcmf_sdbrcm_enable_oob_intr(bus, true);
5981 #endif /* defined(OOB_INTR_ONLY) */
5983 bus->dhd->dongle_reset = false;
5984 bus->dhd->up = true;
5986 DHD_TRACE(("%s: WLAN ON DONE\n",
5993 bcmerror = -EISCONN;
5994 DHD_ERROR(("%s: Set DEVRESET=false invoked when device "
5995 "is on\n", __func__));
6003 brcmf_sdbrcm_chip_recognition(struct brcmf_sdio *sdh, struct chip_info *ci,
6010 * Chipid is assume to be at offset 0 from regs arg
6011 * For different chiptypes or old sdio hosts w/o chipcommon,
6012 * other ways of recognition should be added here.
6014 ci->cccorebase = (u32)regs;
6015 regdata = brcmf_sdcard_reg_read(sdh,
6016 CORE_CC_REG(ci->cccorebase, chipid), 4);
6017 ci->chip = regdata & CID_ID_MASK;
6018 ci->chiprev = (regdata & CID_REV_MASK) >> CID_REV_SHIFT;
6020 DHD_INFO(("%s: chipid=0x%x chiprev=%d\n",
6021 __func__, ci->chip, ci->chiprev));
6023 /* Address of cores for new chips should be added here */
6025 case BCM4329_CHIP_ID:
6026 ci->buscorebase = BCM4329_CORE_BUS_BASE;
6027 ci->ramcorebase = BCM4329_CORE_SOCRAM_BASE;
6028 ci->armcorebase = BCM4329_CORE_ARM_BASE;
6029 ci->ramsize = BCM4329_RAMSIZE;
6032 DHD_ERROR(("%s: chipid 0x%x is not supported\n",
6033 __func__, ci->chip));
6037 regdata = brcmf_sdcard_reg_read(sdh,
6038 CORE_SB(ci->cccorebase, sbidhigh), 4);
6039 ci->ccrev = SBCOREREV(regdata);
6041 regdata = brcmf_sdcard_reg_read(sdh,
6042 CORE_CC_REG(ci->cccorebase, pmucapabilities), 4);
6043 ci->pmurev = regdata & PCAP_REV_MASK;
6045 regdata = brcmf_sdcard_reg_read(sdh,
6046 CORE_SB(ci->buscorebase, sbidhigh), 4);
6047 ci->buscorerev = SBCOREREV(regdata);
6048 ci->buscoretype = (regdata & SBIDH_CC_MASK) >> SBIDH_CC_SHIFT;
6050 DHD_INFO(("%s: ccrev=%d, pmurev=%d, buscore rev/type=%d/0x%x\n",
6051 __func__, ci->ccrev, ci->pmurev,
6052 ci->buscorerev, ci->buscoretype));
6054 /* get chipcommon capabilites */
6055 ci->cccaps = brcmf_sdcard_reg_read(sdh,
6056 CORE_CC_REG(ci->cccorebase, capabilities), 4);
6062 brcmf_sdbrcm_chip_disablecore(struct brcmf_sdio *sdh, u32 corebase)
6066 regdata = brcmf_sdcard_reg_read(sdh,
6067 CORE_SB(corebase, sbtmstatelow), 4);
6068 if (regdata & SBTML_RESET)
6071 regdata = brcmf_sdcard_reg_read(sdh,
6072 CORE_SB(corebase, sbtmstatelow), 4);
6073 if ((regdata & (SICF_CLOCK_EN << SBTML_SICF_SHIFT)) != 0) {
6075 * set target reject and spin until busy is clear
6076 * (preserve core-specific bits)
6078 regdata = brcmf_sdcard_reg_read(sdh,
6079 CORE_SB(corebase, sbtmstatelow), 4);
6080 brcmf_sdcard_reg_write(sdh, CORE_SB(corebase, sbtmstatelow), 4,
6081 regdata | SBTML_REJ);
6083 regdata = brcmf_sdcard_reg_read(sdh,
6084 CORE_SB(corebase, sbtmstatelow), 4);
6086 SPINWAIT((brcmf_sdcard_reg_read(sdh,
6087 CORE_SB(corebase, sbtmstatehigh), 4) &
6088 SBTMH_BUSY), 100000);
6090 regdata = brcmf_sdcard_reg_read(sdh,
6091 CORE_SB(corebase, sbtmstatehigh), 4);
6092 if (regdata & SBTMH_BUSY)
6093 DHD_ERROR(("%s: ARM core still busy\n", __func__));
6095 regdata = brcmf_sdcard_reg_read(sdh,
6096 CORE_SB(corebase, sbidlow), 4);
6097 if (regdata & SBIDL_INIT) {
6098 regdata = brcmf_sdcard_reg_read(sdh,
6099 CORE_SB(corebase, sbimstate), 4) |
6101 brcmf_sdcard_reg_write(sdh,
6102 CORE_SB(corebase, sbimstate), 4,
6104 regdata = brcmf_sdcard_reg_read(sdh,
6105 CORE_SB(corebase, sbimstate), 4);
6107 SPINWAIT((brcmf_sdcard_reg_read(sdh,
6108 CORE_SB(corebase, sbimstate), 4) &
6112 /* set reset and reject while enabling the clocks */
6113 brcmf_sdcard_reg_write(sdh,
6114 CORE_SB(corebase, sbtmstatelow), 4,
6115 (((SICF_FGC | SICF_CLOCK_EN) << SBTML_SICF_SHIFT) |
6116 SBTML_REJ | SBTML_RESET));
6117 regdata = brcmf_sdcard_reg_read(sdh,
6118 CORE_SB(corebase, sbtmstatelow), 4);
6121 /* clear the initiator reject bit */
6122 regdata = brcmf_sdcard_reg_read(sdh,
6123 CORE_SB(corebase, sbidlow), 4);
6124 if (regdata & SBIDL_INIT) {
6125 regdata = brcmf_sdcard_reg_read(sdh,
6126 CORE_SB(corebase, sbimstate), 4) &
6128 brcmf_sdcard_reg_write(sdh,
6129 CORE_SB(corebase, sbimstate), 4,
6134 /* leave reset and reject asserted */
6135 brcmf_sdcard_reg_write(sdh, CORE_SB(corebase, sbtmstatelow), 4,
6136 (SBTML_REJ | SBTML_RESET));
6141 brcmf_sdbrcm_chip_attach(struct dhd_bus *bus, void *regs)
6143 struct chip_info *ci;
6147 DHD_TRACE(("%s: Enter\n", __func__));
6149 /* alloc chip_info_t */
6150 ci = kmalloc(sizeof(struct chip_info), GFP_ATOMIC);
6152 DHD_ERROR(("%s: malloc failed!\n", __func__));
6156 memset((unsigned char *)ci, 0, sizeof(struct chip_info));
6158 /* bus/core/clk setup for register access */
6159 /* Try forcing SDIO core to do ALPAvail request only */
6160 clkset = SBSDIO_FORCE_HW_CLKREQ_OFF | SBSDIO_ALP_AVAIL_REQ;
6161 brcmf_sdcard_cfg_write(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
6164 DHD_ERROR(("%s: error writing for HT off\n", __func__));
6168 /* If register supported, wait for ALPAvail and then force ALP */
6169 /* This may take up to 15 milliseconds */
6170 clkval = brcmf_sdcard_cfg_read(bus->sdh, SDIO_FUNC_1,
6171 SBSDIO_FUNC1_CHIPCLKCSR, NULL);
6172 if ((clkval & ~SBSDIO_AVBITS) == clkset) {
6174 brcmf_sdcard_cfg_read(bus->sdh, SDIO_FUNC_1,
6175 SBSDIO_FUNC1_CHIPCLKCSR,
6177 !SBSDIO_ALPAV(clkval)),
6178 PMU_MAX_TRANSITION_DLY);
6179 if (!SBSDIO_ALPAV(clkval)) {
6180 DHD_ERROR(("%s: timeout on ALPAV wait, clkval 0x%02x\n",
6185 clkset = SBSDIO_FORCE_HW_CLKREQ_OFF |
6187 brcmf_sdcard_cfg_write(bus->sdh, SDIO_FUNC_1,
6188 SBSDIO_FUNC1_CHIPCLKCSR,
6192 DHD_ERROR(("%s: ChipClkCSR access: wrote 0x%02x read 0x%02x\n",
6193 __func__, clkset, clkval));
6198 /* Also, disable the extra SDIO pull-ups */
6199 brcmf_sdcard_cfg_write(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_SDIOPULLUP,
6202 err = brcmf_sdbrcm_chip_recognition(bus->sdh, ci, regs);
6207 * Make sure any on-chip ARM is off (in case strapping is wrong),
6208 * or downloaded code was already running.
6210 brcmf_sdbrcm_chip_disablecore(bus->sdh, ci->armcorebase);
6212 brcmf_sdcard_reg_write(bus->sdh,
6213 CORE_CC_REG(ci->cccorebase, gpiopullup), 4, 0);
6214 brcmf_sdcard_reg_write(bus->sdh,
6215 CORE_CC_REG(ci->cccorebase, gpiopulldown), 4, 0);
6217 /* Disable F2 to clear any intermediate frame state on the dongle */
6218 brcmf_sdcard_cfg_write(bus->sdh, SDIO_FUNC_0, SDIO_CCCR_IOEx,
6219 SDIO_FUNC_ENABLE_1, NULL);
6221 /* WAR: cmd52 backplane read so core HW will drop ALPReq */
6222 clkval = brcmf_sdcard_cfg_read(bus->sdh, SDIO_FUNC_1,
6225 /* Done with backplane-dependent accesses, can drop clock... */
6226 brcmf_sdcard_cfg_write(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
6238 brcmf_sdbrcm_chip_resetcore(struct brcmf_sdio *sdh, u32 corebase)
6243 * Must do the disable sequence first to work for
6244 * arbitrary current core state.
6246 brcmf_sdbrcm_chip_disablecore(sdh, corebase);
6249 * Now do the initialization sequence.
6250 * set reset while enabling the clock and
6251 * forcing them on throughout the core
6253 brcmf_sdcard_reg_write(sdh, CORE_SB(corebase, sbtmstatelow), 4,
6254 ((SICF_FGC | SICF_CLOCK_EN) << SBTML_SICF_SHIFT) |
6258 regdata = brcmf_sdcard_reg_read(sdh, CORE_SB(corebase, sbtmstatehigh),
6260 if (regdata & SBTMH_SERR)
6261 brcmf_sdcard_reg_write(sdh, CORE_SB(corebase, sbtmstatehigh),
6264 regdata = brcmf_sdcard_reg_read(sdh, CORE_SB(corebase, sbimstate), 4);
6265 if (regdata & (SBIM_IBE | SBIM_TO))
6266 brcmf_sdcard_reg_write(sdh, CORE_SB(corebase, sbimstate), 4,
6267 regdata & ~(SBIM_IBE | SBIM_TO));
6269 /* clear reset and allow it to propagate throughout the core */
6270 brcmf_sdcard_reg_write(sdh, CORE_SB(corebase, sbtmstatelow), 4,
6271 (SICF_FGC << SBTML_SICF_SHIFT) |
6272 (SICF_CLOCK_EN << SBTML_SICF_SHIFT));
6275 /* leave clock enabled */
6276 brcmf_sdcard_reg_write(sdh, CORE_SB(corebase, sbtmstatelow), 4,
6277 (SICF_CLOCK_EN << SBTML_SICF_SHIFT));
6281 /* SDIO Pad drive strength to select value mappings */
6282 struct sdiod_drive_str {
6283 u8 strength; /* Pad Drive Strength in mA */
6284 u8 sel; /* Chip-specific select value */
6287 /* SDIO Drive Strength to sel value table for PMU Rev 1 */
6288 static const struct sdiod_drive_str sdiod_drive_strength_tab1[] = {
6296 /* SDIO Drive Strength to sel value table for PMU Rev 2, 3 */
6297 static const struct sdiod_drive_str sdiod_drive_strength_tab2[] = {
6308 /* SDIO Drive Strength to sel value table for PMU Rev 8 (1.8V) */
6309 static const struct sdiod_drive_str sdiod_drive_strength_tab3[] = {
6321 #define SDIOD_DRVSTR_KEY(chip, pmu) (((chip) << 16) | (pmu))
6324 brcmf_sdbrcm_sdiod_drive_strength_init(struct dhd_bus *bus, u32 drivestrength) {
6325 struct sdiod_drive_str *str_tab = NULL;
6330 if (!(bus->ci->cccaps & CC_CAP_PMU))
6333 switch (SDIOD_DRVSTR_KEY(bus->ci->chip, bus->ci->pmurev)) {
6334 case SDIOD_DRVSTR_KEY(BCM4325_CHIP_ID, 1):
6335 str_tab = (struct sdiod_drive_str *)&sdiod_drive_strength_tab1;
6336 str_mask = 0x30000000;
6339 case SDIOD_DRVSTR_KEY(BCM4325_CHIP_ID, 2):
6340 case SDIOD_DRVSTR_KEY(BCM4325_CHIP_ID, 3):
6341 str_tab = (struct sdiod_drive_str *)&sdiod_drive_strength_tab2;
6342 str_mask = 0x00003800;
6345 case SDIOD_DRVSTR_KEY(BCM4336_CHIP_ID, 8):
6346 str_tab = (struct sdiod_drive_str *)&sdiod_drive_strength_tab3;
6347 str_mask = 0x00003800;
6351 DHD_ERROR(("No SDIO Drive strength init"
6352 "done for chip %s rev %d pmurev %d\n",
6353 brcmu_chipname(bus->ci->chip, chn, 8),
6354 bus->ci->chiprev, bus->ci->pmurev));
6358 if (str_tab != NULL) {
6359 u32 drivestrength_sel = 0;
6363 for (i = 0; str_tab[i].strength != 0; i++) {
6364 if (drivestrength >= str_tab[i].strength) {
6365 drivestrength_sel = str_tab[i].sel;
6370 brcmf_sdcard_reg_write(bus->sdh,
6371 CORE_CC_REG(bus->ci->cccorebase, chipcontrol_addr),
6373 cc_data_temp = brcmf_sdcard_reg_read(bus->sdh,
6374 CORE_CC_REG(bus->ci->cccorebase, chipcontrol_addr), 4);
6375 cc_data_temp &= ~str_mask;
6376 drivestrength_sel <<= str_shift;
6377 cc_data_temp |= drivestrength_sel;
6378 brcmf_sdcard_reg_write(bus->sdh,
6379 CORE_CC_REG(bus->ci->cccorebase, chipcontrol_addr),
6382 DHD_INFO(("SDIO: %dmA drive strength selected, set to 0x%08x\n",
6383 drivestrength, cc_data_temp));
6388 brcmf_sdbrcm_chip_detach(struct dhd_bus *bus)
6390 DHD_TRACE(("%s: Enter\n", __func__));
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