2 * Copyright (c) 2010 Broadcom Corporation
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
16 #include <linux/delay.h>
17 #include <linux/pci.h>
20 #include <chipcommon.h>
21 #include <brcmu_utils.h>
22 #include <brcm_hw_ids.h>
31 #define SCC_SS_MASK 0x00000007 /* slow clock source mask */
32 #define SCC_SS_LPO 0x00000000 /* source of slow clock is LPO */
33 #define SCC_SS_XTAL 0x00000001 /* source of slow clock is crystal */
34 #define SCC_SS_PCI 0x00000002 /* source of slow clock is PCI */
35 #define SCC_LF 0x00000200 /* LPOFreqSel, 1: 160Khz, 0: 32KHz */
36 #define SCC_LP 0x00000400 /* LPOPowerDown, 1: LPO is disabled,
39 #define SCC_FS 0x00000800 /* ForceSlowClk, 1: sb/cores running on slow clock,
40 * 0: power logic control
42 #define SCC_IP 0x00001000 /* IgnorePllOffReq, 1/0: power logic ignores/honors
43 * PLL clock disable requests from core
45 #define SCC_XC 0x00002000 /* XtalControlEn, 1/0: power logic does/doesn't
46 * disable crystal when appropriate
48 #define SCC_XP 0x00004000 /* XtalPU (RO), 1/0: crystal running/disabled */
49 #define SCC_CD_MASK 0xffff0000 /* ClockDivider (SlowClk = 1/(4+divisor)) */
50 #define SCC_CD_SHIFT 16
53 #define SYCC_IE 0x00000001 /* ILPen: Enable Idle Low Power */
54 #define SYCC_AE 0x00000002 /* ALPen: Enable Active Low Power */
55 #define SYCC_FP 0x00000004 /* ForcePLLOn */
56 #define SYCC_AR 0x00000008 /* Force ALP (or HT if ALPen is not set */
57 #define SYCC_HR 0x00000010 /* Force HT */
58 #define SYCC_CD_MASK 0xffff0000 /* ClkDiv (ILP = 1/(4 * (divisor + 1)) */
59 #define SYCC_CD_SHIFT 16
61 #define CST4329_SPROM_OTP_SEL_MASK 0x00000003
62 #define CST4329_DEFCIS_SEL 0 /* OTP is powered up, use def. CIS, no SPROM */
63 #define CST4329_SPROM_SEL 1 /* OTP is powered up, SPROM is present */
64 #define CST4329_OTP_SEL 2 /* OTP is powered up, no SPROM */
65 #define CST4329_OTP_PWRDN 3 /* OTP is powered down, SPROM is present */
66 #define CST4329_SPI_SDIO_MODE_MASK 0x00000004
67 #define CST4329_SPI_SDIO_MODE_SHIFT 2
69 /* 43224 chip-specific ChipControl register bits */
70 #define CCTRL43224_GPIO_TOGGLE 0x8000
71 #define CCTRL_43224A0_12MA_LED_DRIVE 0x00F000F0 /* 12 mA drive strength */
72 #define CCTRL_43224B0_12MA_LED_DRIVE 0xF0 /* 12 mA drive strength for later 43224s */
74 /* 43236 Chip specific ChipStatus register bits */
75 #define CST43236_SFLASH_MASK 0x00000040
76 #define CST43236_OTP_MASK 0x00000080
77 #define CST43236_HSIC_MASK 0x00000100 /* USB/HSIC */
78 #define CST43236_BP_CLK 0x00000200 /* 120/96Mbps */
79 #define CST43236_BOOT_MASK 0x00001800
80 #define CST43236_BOOT_SHIFT 11
81 #define CST43236_BOOT_FROM_SRAM 0 /* boot from SRAM, ARM in reset */
82 #define CST43236_BOOT_FROM_ROM 1 /* boot from ROM */
83 #define CST43236_BOOT_FROM_FLASH 2 /* boot from FLASH */
84 #define CST43236_BOOT_FROM_INVALID 3
86 /* 4331 chip-specific ChipControl register bits */
87 #define CCTRL4331_BT_COEXIST (1<<0) /* 0 disable */
88 #define CCTRL4331_SECI (1<<1) /* 0 SECI is disabled (JATG functional) */
89 #define CCTRL4331_EXT_LNA (1<<2) /* 0 disable */
90 #define CCTRL4331_SPROM_GPIO13_15 (1<<3) /* sprom/gpio13-15 mux */
91 #define CCTRL4331_EXTPA_EN (1<<4) /* 0 ext pa disable, 1 ext pa enabled */
92 #define CCTRL4331_GPIOCLK_ON_SPROMCS (1<<5) /* set drive out GPIO_CLK on sprom_cs pin */
93 #define CCTRL4331_PCIE_MDIO_ON_SPROMCS (1<<6) /* use sprom_cs pin as PCIE mdio interface */
94 #define CCTRL4331_EXTPA_ON_GPIO2_5 (1<<7) /* aband extpa will be at gpio2/5 and sprom_dout */
95 #define CCTRL4331_OVR_PIPEAUXCLKEN (1<<8) /* override core control on pipe_AuxClkEnable */
96 #define CCTRL4331_OVR_PIPEAUXPWRDOWN (1<<9) /* override core control on pipe_AuxPowerDown */
97 #define CCTRL4331_PCIE_AUXCLKEN (1<<10) /* pcie_auxclkenable */
98 #define CCTRL4331_PCIE_PIPE_PLLDOWN (1<<11) /* pcie_pipe_pllpowerdown */
99 #define CCTRL4331_BT_SHD0_ON_GPIO4 (1<<16) /* enable bt_shd0 at gpio4 */
100 #define CCTRL4331_BT_SHD1_ON_GPIO5 (1<<17) /* enable bt_shd1 at gpio5 */
102 /* 4331 Chip specific ChipStatus register bits */
103 #define CST4331_XTAL_FREQ 0x00000001 /* crystal frequency 20/40Mhz */
104 #define CST4331_SPROM_PRESENT 0x00000002
105 #define CST4331_OTP_PRESENT 0x00000004
106 #define CST4331_LDO_RF 0x00000008
107 #define CST4331_LDO_PAR 0x00000010
109 /* 4319 chip-specific ChipStatus register bits */
110 #define CST4319_SPI_CPULESSUSB 0x00000001
111 #define CST4319_SPI_CLK_POL 0x00000002
112 #define CST4319_SPI_CLK_PH 0x00000008
113 #define CST4319_SPROM_OTP_SEL_MASK 0x000000c0 /* gpio [7:6], SDIO CIS selection */
114 #define CST4319_SPROM_OTP_SEL_SHIFT 6
115 #define CST4319_DEFCIS_SEL 0x00000000 /* use default CIS, OTP is powered up */
116 #define CST4319_SPROM_SEL 0x00000040 /* use SPROM, OTP is powered up */
117 #define CST4319_OTP_SEL 0x00000080 /* use OTP, OTP is powered up */
118 #define CST4319_OTP_PWRDN 0x000000c0 /* use SPROM, OTP is powered down */
119 #define CST4319_SDIO_USB_MODE 0x00000100 /* gpio [8], sdio/usb mode */
120 #define CST4319_REMAP_SEL_MASK 0x00000600
121 #define CST4319_ILPDIV_EN 0x00000800
122 #define CST4319_XTAL_PD_POL 0x00001000
123 #define CST4319_LPO_SEL 0x00002000
124 #define CST4319_RES_INIT_MODE 0x0000c000
125 #define CST4319_PALDO_EXTPNP 0x00010000 /* PALDO is configured with external PNP */
126 #define CST4319_CBUCK_MODE_MASK 0x00060000
127 #define CST4319_CBUCK_MODE_BURST 0x00020000
128 #define CST4319_CBUCK_MODE_LPBURST 0x00060000
129 #define CST4319_RCAL_VALID 0x01000000
130 #define CST4319_RCAL_VALUE_MASK 0x3e000000
131 #define CST4319_RCAL_VALUE_SHIFT 25
133 /* 4336 chip-specific ChipStatus register bits */
134 #define CST4336_SPI_MODE_MASK 0x00000001
135 #define CST4336_SPROM_PRESENT 0x00000002
136 #define CST4336_OTP_PRESENT 0x00000004
137 #define CST4336_ARMREMAP_0 0x00000008
138 #define CST4336_ILPDIV_EN_MASK 0x00000010
139 #define CST4336_ILPDIV_EN_SHIFT 4
140 #define CST4336_XTAL_PD_POL_MASK 0x00000020
141 #define CST4336_XTAL_PD_POL_SHIFT 5
142 #define CST4336_LPO_SEL_MASK 0x00000040
143 #define CST4336_LPO_SEL_SHIFT 6
144 #define CST4336_RES_INIT_MODE_MASK 0x00000180
145 #define CST4336_RES_INIT_MODE_SHIFT 7
146 #define CST4336_CBUCK_MODE_MASK 0x00000600
147 #define CST4336_CBUCK_MODE_SHIFT 9
149 /* 4313 chip-specific ChipStatus register bits */
150 #define CST4313_SPROM_PRESENT 1
151 #define CST4313_OTP_PRESENT 2
152 #define CST4313_SPROM_OTP_SEL_MASK 0x00000002
153 #define CST4313_SPROM_OTP_SEL_SHIFT 0
155 /* 4313 Chip specific ChipControl register bits */
156 #define CCTRL_4313_12MA_LED_DRIVE 0x00000007 /* 12 mA drive strengh for later 4313 */
158 #define BCM47162_DMP() ((sih->chip == BCM47162_CHIP_ID) && \
159 (sih->chiprev == 0) && \
160 (sii->coreid[sii->curidx] == MIPS74K_CORE_ID))
162 /* Manufacturer Ids */
163 #define MFGID_ARM 0x43b
164 #define MFGID_BRCM 0x4bf
165 #define MFGID_MIPS 0x4a7
167 /* Enumeration ROM registers */
168 #define ER_EROMENTRY 0x000
169 #define ER_REMAPCONTROL 0xe00
170 #define ER_REMAPSELECT 0xe04
171 #define ER_MASTERSELECT 0xe10
172 #define ER_ITCR 0xf00
173 #define ER_ITIP 0xf04
183 #define ER_BAD 0xffffffff
185 /* EROM CompIdentA */
186 #define CIA_MFG_MASK 0xfff00000
187 #define CIA_MFG_SHIFT 20
188 #define CIA_CID_MASK 0x000fff00
189 #define CIA_CID_SHIFT 8
190 #define CIA_CCL_MASK 0x000000f0
191 #define CIA_CCL_SHIFT 4
193 /* EROM CompIdentB */
194 #define CIB_REV_MASK 0xff000000
195 #define CIB_REV_SHIFT 24
196 #define CIB_NSW_MASK 0x00f80000
197 #define CIB_NSW_SHIFT 19
198 #define CIB_NMW_MASK 0x0007c000
199 #define CIB_NMW_SHIFT 14
200 #define CIB_NSP_MASK 0x00003e00
201 #define CIB_NSP_SHIFT 9
202 #define CIB_NMP_MASK 0x000001f0
203 #define CIB_NMP_SHIFT 4
206 #define AD_ADDR_MASK 0xfffff000
207 #define AD_SP_MASK 0x00000f00
208 #define AD_SP_SHIFT 8
209 #define AD_ST_MASK 0x000000c0
210 #define AD_ST_SHIFT 6
211 #define AD_ST_SLAVE 0x00000000
212 #define AD_ST_BRIDGE 0x00000040
213 #define AD_ST_SWRAP 0x00000080
214 #define AD_ST_MWRAP 0x000000c0
215 #define AD_SZ_MASK 0x00000030
216 #define AD_SZ_SHIFT 4
217 #define AD_SZ_4K 0x00000000
218 #define AD_SZ_8K 0x00000010
219 #define AD_SZ_16K 0x00000020
220 #define AD_SZ_SZD 0x00000030
221 #define AD_AG32 0x00000008
222 #define AD_ADDR_ALIGN 0x00000fff
223 #define AD_SZ_BASE 0x00001000 /* 4KB */
226 #define SD_SZ_MASK 0xfffff000
227 #define SD_SG32 0x00000008
228 #define SD_SZ_ALIGN 0x00000fff
230 #define PCI_CFG_GPIO_SCS 0x10 /* PCI config space bit 4 for 4306c0 slow clock source */
231 #define PCI_CFG_GPIO_XTAL 0x40 /* PCI config space GPIO 14 for Xtal power-up */
232 #define PCI_CFG_GPIO_PLL 0x80 /* PCI config space GPIO 15 for PLL power-down */
234 /* power control defines */
235 #define PLL_DELAY 150 /* us pll on delay */
236 #define FREF_DELAY 200 /* us fref change delay */
237 #define XTAL_ON_DELAY 1000 /* us crystal power-on delay */
243 u32 oobselina30; /* 0x000 */
244 u32 oobselina74; /* 0x004 */
246 u32 oobselinb30; /* 0x020 */
247 u32 oobselinb74; /* 0x024 */
249 u32 oobselinc30; /* 0x040 */
250 u32 oobselinc74; /* 0x044 */
252 u32 oobselind30; /* 0x060 */
253 u32 oobselind74; /* 0x064 */
255 u32 oobselouta30; /* 0x100 */
256 u32 oobselouta74; /* 0x104 */
258 u32 oobseloutb30; /* 0x120 */
259 u32 oobseloutb74; /* 0x124 */
261 u32 oobseloutc30; /* 0x140 */
262 u32 oobseloutc74; /* 0x144 */
264 u32 oobseloutd30; /* 0x160 */
265 u32 oobseloutd74; /* 0x164 */
267 u32 oobsynca; /* 0x200 */
268 u32 oobseloutaen; /* 0x204 */
270 u32 oobsyncb; /* 0x220 */
271 u32 oobseloutben; /* 0x224 */
273 u32 oobsyncc; /* 0x240 */
274 u32 oobseloutcen; /* 0x244 */
276 u32 oobsyncd; /* 0x260 */
277 u32 oobseloutden; /* 0x264 */
279 u32 oobaextwidth; /* 0x300 */
280 u32 oobainwidth; /* 0x304 */
281 u32 oobaoutwidth; /* 0x308 */
283 u32 oobbextwidth; /* 0x320 */
284 u32 oobbinwidth; /* 0x324 */
285 u32 oobboutwidth; /* 0x328 */
287 u32 oobcextwidth; /* 0x340 */
288 u32 oobcinwidth; /* 0x344 */
289 u32 oobcoutwidth; /* 0x348 */
291 u32 oobdextwidth; /* 0x360 */
292 u32 oobdinwidth; /* 0x364 */
293 u32 oobdoutwidth; /* 0x368 */
295 u32 ioctrlset; /* 0x400 */
296 u32 ioctrlclear; /* 0x404 */
297 u32 ioctrl; /* 0x408 */
299 u32 iostatus; /* 0x500 */
301 u32 ioctrlwidth; /* 0x700 */
302 u32 iostatuswidth; /* 0x704 */
304 u32 resetctrl; /* 0x800 */
305 u32 resetstatus; /* 0x804 */
306 u32 resetreadid; /* 0x808 */
307 u32 resetwriteid; /* 0x80c */
309 u32 errlogctrl; /* 0x900 */
310 u32 errlogdone; /* 0x904 */
311 u32 errlogstatus; /* 0x908 */
312 u32 errlogaddrlo; /* 0x90c */
313 u32 errlogaddrhi; /* 0x910 */
314 u32 errlogid; /* 0x914 */
315 u32 errloguser; /* 0x918 */
316 u32 errlogflags; /* 0x91c */
318 u32 intstatus; /* 0xa00 */
320 u32 config; /* 0xe00 */
322 u32 itcr; /* 0xf00 */
324 u32 itipooba; /* 0xf10 */
325 u32 itipoobb; /* 0xf14 */
326 u32 itipoobc; /* 0xf18 */
327 u32 itipoobd; /* 0xf1c */
329 u32 itipoobaout; /* 0xf30 */
330 u32 itipoobbout; /* 0xf34 */
331 u32 itipoobcout; /* 0xf38 */
332 u32 itipoobdout; /* 0xf3c */
334 u32 itopooba; /* 0xf50 */
335 u32 itopoobb; /* 0xf54 */
336 u32 itopoobc; /* 0xf58 */
337 u32 itopoobd; /* 0xf5c */
339 u32 itopoobain; /* 0xf70 */
340 u32 itopoobbin; /* 0xf74 */
341 u32 itopoobcin; /* 0xf78 */
342 u32 itopoobdin; /* 0xf7c */
344 u32 itopreset; /* 0xf90 */
346 u32 peripherialid4; /* 0xfd0 */
347 u32 peripherialid5; /* 0xfd4 */
348 u32 peripherialid6; /* 0xfd8 */
349 u32 peripherialid7; /* 0xfdc */
350 u32 peripherialid0; /* 0xfe0 */
351 u32 peripherialid1; /* 0xfe4 */
352 u32 peripherialid2; /* 0xfe8 */
353 u32 peripherialid3; /* 0xfec */
354 u32 componentid0; /* 0xff0 */
355 u32 componentid1; /* 0xff4 */
356 u32 componentid2; /* 0xff8 */
357 u32 componentid3; /* 0xffc */
363 get_erom_ent(struct si_pub *sih, u32 **eromptr, u32 mask, u32 match)
366 uint inv = 0, nom = 0;
369 ent = R_REG(*eromptr);
375 if ((ent & ER_VALID) == 0) {
380 if (ent == (ER_END | ER_VALID))
383 if ((ent & mask) == match)
389 SI_VMSG(("%s: Returning ent 0x%08x\n", __func__, ent));
391 SI_VMSG((" after %d invalid and %d non-matching entries\n",
398 get_asd(struct si_pub *sih, u32 **eromptr, uint sp, uint ad, uint st,
399 u32 *addrl, u32 *addrh, u32 *sizel, u32 *sizeh)
403 asd = get_erom_ent(sih, eromptr, ER_VALID, ER_VALID);
404 if (((asd & ER_TAG1) != ER_ADD) ||
405 (((asd & AD_SP_MASK) >> AD_SP_SHIFT) != sp) ||
406 ((asd & AD_ST_MASK) != st)) {
407 /* This is not what we want, "push" it back */
411 *addrl = asd & AD_ADDR_MASK;
413 *addrh = get_erom_ent(sih, eromptr, 0, 0);
417 sz = asd & AD_SZ_MASK;
418 if (sz == AD_SZ_SZD) {
419 szd = get_erom_ent(sih, eromptr, 0, 0);
420 *sizel = szd & SD_SZ_MASK;
422 *sizeh = get_erom_ent(sih, eromptr, 0, 0);
424 *sizel = AD_SZ_BASE << (sz >> AD_SZ_SHIFT);
426 SI_VMSG((" SP %d, ad %d: st = %d, 0x%08x_0x%08x @ 0x%08x_0x%08x\n",
427 sp, ad, st, *sizeh, *sizel, *addrh, *addrl));
432 static void ai_hwfixup(struct si_info *sii)
436 /* parse the enumeration rom to identify all cores */
437 void ai_scan(struct si_pub *sih, void *regs)
439 struct si_info *sii = SI_INFO(sih);
440 chipcregs_t *cc = (chipcregs_t *) regs;
441 u32 erombase, *eromptr, *eromlim;
443 erombase = R_REG(&cc->eromptr);
445 switch (sih->bustype) {
447 eromptr = (u32 *) REG_MAP(erombase, SI_CORE_SIZE);
451 /* Set wrappers address */
452 sii->curwrap = (void *)((unsigned long)regs + SI_CORE_SIZE);
454 /* Now point the window at the erom */
455 pci_write_config_dword(sii->pbus, PCI_BAR0_WIN, erombase);
461 eromptr = (u32 *)(unsigned long)erombase;
465 SI_ERROR(("Don't know how to do AXI enumertion on bus %d\n",
469 eromlim = eromptr + (ER_REMAPCONTROL / sizeof(u32));
471 SI_VMSG(("ai_scan: regs = 0x%p, erombase = 0x%08x, eromptr = 0x%p, eromlim = 0x%p\n", regs, erombase, eromptr, eromlim));
472 while (eromptr < eromlim) {
473 u32 cia, cib, cid, mfg, crev, nmw, nsw, nmp, nsp;
474 u32 mpd, asd, addrl, addrh, sizel, sizeh;
481 /* Grok a component */
482 cia = get_erom_ent(sih, &eromptr, ER_TAG, ER_CI);
483 if (cia == (ER_END | ER_VALID)) {
484 SI_VMSG(("Found END of erom after %d cores\n",
490 cib = get_erom_ent(sih, &eromptr, 0, 0);
492 if ((cib & ER_TAG) != ER_CI) {
493 SI_ERROR(("CIA not followed by CIB\n"));
497 cid = (cia & CIA_CID_MASK) >> CIA_CID_SHIFT;
498 mfg = (cia & CIA_MFG_MASK) >> CIA_MFG_SHIFT;
499 crev = (cib & CIB_REV_MASK) >> CIB_REV_SHIFT;
500 nmw = (cib & CIB_NMW_MASK) >> CIB_NMW_SHIFT;
501 nsw = (cib & CIB_NSW_MASK) >> CIB_NSW_SHIFT;
502 nmp = (cib & CIB_NMP_MASK) >> CIB_NMP_SHIFT;
503 nsp = (cib & CIB_NSP_MASK) >> CIB_NSP_SHIFT;
505 SI_VMSG(("Found component 0x%04x/0x%04x rev %d at erom addr 0x%p, with nmw = %d, " "nsw = %d, nmp = %d & nsp = %d\n", mfg, cid, crev, base, nmw, nsw, nmp, nsp));
507 if (((mfg == MFGID_ARM) && (cid == DEF_AI_COMP)) || (nsp == 0))
509 if ((nmw + nsw == 0)) {
510 /* A component which is not a core */
511 if (cid == OOB_ROUTER_CORE_ID) {
512 asd = get_asd(sih, &eromptr, 0, 0, AD_ST_SLAVE,
513 &addrl, &addrh, &sizel, &sizeh);
515 sii->oob_router = addrl;
522 /* sii->eromptr[idx] = base; */
525 sii->coreid[idx] = cid;
527 for (i = 0; i < nmp; i++) {
528 mpd = get_erom_ent(sih, &eromptr, ER_VALID, ER_VALID);
529 if ((mpd & ER_TAG) != ER_MP) {
530 SI_ERROR(("Not enough MP entries for component 0x%x\n", cid));
533 SI_VMSG((" Master port %d, mp: %d id: %d\n", i,
534 (mpd & MPD_MP_MASK) >> MPD_MP_SHIFT,
535 (mpd & MPD_MUI_MASK) >> MPD_MUI_SHIFT));
538 /* First Slave Address Descriptor should be port 0:
539 * the main register space for the core
542 get_asd(sih, &eromptr, 0, 0, AD_ST_SLAVE, &addrl, &addrh,
545 /* Try again to see if it is a bridge */
547 get_asd(sih, &eromptr, 0, 0, AD_ST_BRIDGE, &addrl,
548 &addrh, &sizel, &sizeh);
551 else if ((addrh != 0) || (sizeh != 0)
552 || (sizel != SI_CORE_SIZE)) {
553 SI_ERROR(("First Slave ASD for core 0x%04x malformed " "(0x%08x)\n", cid, asd));
557 sii->coresba[idx] = addrl;
558 sii->coresba_size[idx] = sizel;
559 /* Get any more ASDs in port 0 */
563 get_asd(sih, &eromptr, 0, j, AD_ST_SLAVE, &addrl,
564 &addrh, &sizel, &sizeh);
565 if ((asd != 0) && (j == 1) && (sizel == SI_CORE_SIZE)) {
566 sii->coresba2[idx] = addrl;
567 sii->coresba2_size[idx] = sizel;
572 /* Go through the ASDs for other slave ports */
573 for (i = 1; i < nsp; i++) {
577 get_asd(sih, &eromptr, i, j++, AD_ST_SLAVE,
578 &addrl, &addrh, &sizel, &sizeh);
581 SI_ERROR((" SP %d has no address descriptors\n",
587 /* Now get master wrappers */
588 for (i = 0; i < nmw; i++) {
590 get_asd(sih, &eromptr, i, 0, AD_ST_MWRAP, &addrl,
591 &addrh, &sizel, &sizeh);
593 SI_ERROR(("Missing descriptor for MW %d\n", i));
596 if ((sizeh != 0) || (sizel != SI_CORE_SIZE)) {
597 SI_ERROR(("Master wrapper %d is not 4KB\n", i));
601 sii->wrapba[idx] = addrl;
604 /* And finally slave wrappers */
605 for (i = 0; i < nsw; i++) {
606 uint fwp = (nsp == 1) ? 0 : 1;
608 get_asd(sih, &eromptr, fwp + i, 0, AD_ST_SWRAP,
609 &addrl, &addrh, &sizel, &sizeh);
611 SI_ERROR(("Missing descriptor for SW %d\n", i));
614 if ((sizeh != 0) || (sizel != SI_CORE_SIZE)) {
615 SI_ERROR(("Slave wrapper %d is not 4KB\n", i));
618 if ((nmw == 0) && (i == 0))
619 sii->wrapba[idx] = addrl;
622 /* Don't record bridges */
630 SI_ERROR(("Reached end of erom without finding END"));
637 /* This function changes the logical "focus" to the indicated core.
638 * Return the current core's virtual address.
640 void *ai_setcoreidx(struct si_pub *sih, uint coreidx)
642 struct si_info *sii = SI_INFO(sih);
643 u32 addr = sii->coresba[coreidx];
644 u32 wrap = sii->wrapba[coreidx];
647 if (coreidx >= sii->numcores)
650 switch (sih->bustype) {
653 if (!sii->regs[coreidx]) {
654 sii->regs[coreidx] = REG_MAP(addr, SI_CORE_SIZE);
656 sii->curmap = regs = sii->regs[coreidx];
657 if (!sii->wrappers[coreidx]) {
658 sii->wrappers[coreidx] = REG_MAP(wrap, SI_CORE_SIZE);
660 sii->curwrap = sii->wrappers[coreidx];
664 /* point bar0 window */
665 pci_write_config_dword(sii->pbus, PCI_BAR0_WIN, addr);
667 /* point bar0 2nd 4KB window */
668 pci_write_config_dword(sii->pbus, PCI_BAR0_WIN2, wrap);
673 sii->curmap = regs = (void *)(unsigned long)addr;
674 sii->curwrap = (void *)(unsigned long)wrap;
683 sii->curidx = coreidx;
688 /* Return the number of address spaces in current core */
689 int ai_numaddrspaces(struct si_pub *sih)
694 /* Return the address of the nth address space in the current core */
695 u32 ai_addrspace(struct si_pub *sih, uint asidx)
704 return sii->coresba[cidx];
706 return sii->coresba2[cidx];
708 SI_ERROR(("%s: Need to parse the erom again to find addr space %d\n", __func__, asidx));
713 /* Return the size of the nth address space in the current core */
714 u32 ai_addrspacesize(struct si_pub *sih, uint asidx)
723 return sii->coresba_size[cidx];
725 return sii->coresba2_size[cidx];
727 SI_ERROR(("%s: Need to parse the erom again to find addr space %d\n", __func__, asidx));
732 uint ai_flag(struct si_pub *sih)
738 if (BCM47162_DMP()) {
739 SI_ERROR(("%s: Attempting to read MIPS DMP registers on 47162a0", __func__));
744 return R_REG(&ai->oobselouta30) & 0x1f;
747 void ai_setint(struct si_pub *sih, int siflag)
751 uint ai_corevendor(struct si_pub *sih)
757 cia = sii->cia[sii->curidx];
758 return (cia & CIA_MFG_MASK) >> CIA_MFG_SHIFT;
761 uint ai_corerev(struct si_pub *sih)
767 cib = sii->cib[sii->curidx];
768 return (cib & CIB_REV_MASK) >> CIB_REV_SHIFT;
771 bool ai_iscoreup(struct si_pub *sih)
779 return (((R_REG(&ai->ioctrl) & (SICF_FGC | SICF_CLOCK_EN)) ==
781 && ((R_REG(&ai->resetctrl) & AIRC_RESET) == 0));
784 void ai_core_cflags_wo(struct si_pub *sih, u32 mask, u32 val)
792 if (BCM47162_DMP()) {
793 SI_ERROR(("%s: Accessing MIPS DMP register (ioctrl) on 47162a0",
801 w = ((R_REG(&ai->ioctrl) & ~mask) | val);
802 W_REG(&ai->ioctrl, w);
806 u32 ai_core_cflags(struct si_pub *sih, u32 mask, u32 val)
813 if (BCM47162_DMP()) {
814 SI_ERROR(("%s: Accessing MIPS DMP register (ioctrl) on 47162a0",
822 w = ((R_REG(&ai->ioctrl) & ~mask) | val);
823 W_REG(&ai->ioctrl, w);
826 return R_REG(&ai->ioctrl);
829 u32 ai_core_sflags(struct si_pub *sih, u32 mask, u32 val)
836 if (BCM47162_DMP()) {
837 SI_ERROR(("%s: Accessing MIPS DMP register (iostatus) on 47162a0", __func__));
844 w = ((R_REG(&ai->iostatus) & ~mask) | val);
845 W_REG(&ai->iostatus, w);
848 return R_REG(&ai->iostatus);
851 /* *************** from siutils.c ************** */
852 /* local prototypes */
853 static struct si_info *ai_doattach(struct si_info *sii, void *regs,
854 uint bustype, void *sdh, char **vars,
856 static bool ai_buscore_prep(struct si_info *sii, uint bustype);
857 static bool ai_buscore_setup(struct si_info *sii, chipcregs_t *cc, uint bustype,
858 u32 savewin, uint *origidx, void *regs);
859 static void ai_nvram_process(struct si_info *sii, char *pvars);
861 /* dev path concatenation util */
862 static char *ai_devpathvar(struct si_pub *sih, char *var, int len,
864 static bool _ai_clkctl_cc(struct si_info *sii, uint mode);
865 static bool ai_ispcie(struct si_info *sii);
867 /* global variable to indicate reservation/release of gpio's */
868 static u32 ai_gpioreservation;
871 * Allocate a si handle.
872 * devid - pci device id (used to determine chip#)
873 * osh - opaque OS handle
874 * regs - virtual address of initial core registers
875 * bustype - pci/sb/sdio/etc
876 * vars - pointer to a pointer area for "environment" variables
877 * varsz - pointer to int to return the size of the vars
879 struct si_pub *ai_attach(void *regs, uint bustype,
880 void *sdh, char **vars, uint *varsz)
884 /* alloc struct si_info */
885 sii = kmalloc(sizeof(struct si_info), GFP_ATOMIC);
887 SI_ERROR(("si_attach: malloc failed!\n"));
891 if (ai_doattach(sii, regs, bustype, sdh, vars, varsz) ==
896 sii->vars = vars ? *vars : NULL;
897 sii->varsz = varsz ? *varsz : 0;
899 return (struct si_pub *) sii;
902 /* global kernel resource */
903 static struct si_info ksii;
905 static bool ai_buscore_prep(struct si_info *sii, uint bustype)
907 /* kludge to enable the clock on the 4306 which lacks a slowclock */
908 if (bustype == PCI_BUS && !ai_ispcie(sii))
909 ai_clkctl_xtal(&sii->pub, XTAL | PLL, ON);
913 static bool ai_buscore_setup(struct si_info *sii, chipcregs_t *cc, uint bustype,
914 u32 savewin, uint *origidx, void *regs)
918 uint pciidx, pcieidx, pcirev, pcierev;
920 cc = ai_setcoreidx(&sii->pub, SI_CC_IDX);
922 /* get chipcommon rev */
923 sii->pub.ccrev = (int)ai_corerev(&sii->pub);
925 /* get chipcommon chipstatus */
926 if (sii->pub.ccrev >= 11)
927 sii->pub.chipst = R_REG(&cc->chipstatus);
929 /* get chipcommon capabilites */
930 sii->pub.cccaps = R_REG(&cc->capabilities);
931 /* get chipcommon extended capabilities */
933 if (sii->pub.ccrev >= 35)
934 sii->pub.cccaps_ext = R_REG(&cc->capabilities_ext);
936 /* get pmu rev and caps */
937 if (sii->pub.cccaps & CC_CAP_PMU) {
938 sii->pub.pmucaps = R_REG(&cc->pmucapabilities);
939 sii->pub.pmurev = sii->pub.pmucaps & PCAP_REV_MASK;
942 /* figure out bus/orignal core idx */
943 sii->pub.buscoretype = NODEV_CORE_ID;
944 sii->pub.buscorerev = NOREV;
945 sii->pub.buscoreidx = BADIDX;
948 pcirev = pcierev = NOREV;
949 pciidx = pcieidx = BADIDX;
951 for (i = 0; i < sii->numcores; i++) {
954 ai_setcoreidx(&sii->pub, i);
955 cid = ai_coreid(&sii->pub);
956 crev = ai_corerev(&sii->pub);
958 /* Display cores found */
959 SI_VMSG(("CORE[%d]: id 0x%x rev %d base 0x%x regs 0x%p\n",
960 i, cid, crev, sii->coresba[i], sii->regs[i]));
962 if (bustype == PCI_BUS) {
963 if (cid == PCI_CORE_ID) {
967 } else if (cid == PCIE_CORE_ID) {
974 /* find the core idx before entering this func. */
975 if ((savewin && (savewin == sii->coresba[i])) ||
976 (regs == sii->regs[i]))
987 sii->pub.buscoretype = PCI_CORE_ID;
988 sii->pub.buscorerev = pcirev;
989 sii->pub.buscoreidx = pciidx;
991 sii->pub.buscoretype = PCIE_CORE_ID;
992 sii->pub.buscorerev = pcierev;
993 sii->pub.buscoreidx = pcieidx;
996 SI_VMSG(("Buscore id/type/rev %d/0x%x/%d\n", sii->pub.buscoreidx,
997 sii->pub.buscoretype, sii->pub.buscorerev));
999 /* fixup necessary chip/core configurations */
1000 if (sii->pub.bustype == PCI_BUS) {
1003 sii->pch = (void *)pcicore_init(
1004 &sii->pub, sii->pbus,
1005 (void *)PCIEREGS(sii));
1006 if (sii->pch == NULL)
1010 if (ai_pci_fixcfg(&sii->pub)) {
1011 SI_ERROR(("si_doattach: si_pci_fixcfg failed\n"));
1016 /* return to the original core */
1017 ai_setcoreidx(&sii->pub, *origidx);
1022 static __used void ai_nvram_process(struct si_info *sii, char *pvars)
1026 /* get boardtype and boardrev */
1027 switch (sii->pub.bustype) {
1029 /* do a pci config read to get subsystem id and subvendor id */
1030 pci_read_config_dword(sii->pbus, PCI_SUBSYSTEM_VENDOR_ID, &w);
1031 /* Let nvram variables override subsystem Vend/ID */
1032 sii->pub.boardvendor = (u16)ai_getdevpathintvar(&sii->pub,
1034 if (sii->pub.boardvendor == 0)
1035 sii->pub.boardvendor = w & 0xffff;
1037 SI_ERROR(("Overriding boardvendor: 0x%x instead of "
1038 "0x%x\n", sii->pub.boardvendor, w & 0xffff));
1039 sii->pub.boardtype = (u16)ai_getdevpathintvar(&sii->pub,
1041 if (sii->pub.boardtype == 0)
1042 sii->pub.boardtype = (w >> 16) & 0xffff;
1044 SI_ERROR(("Overriding boardtype: 0x%x instead of 0x%x\n"
1045 , sii->pub.boardtype, (w >> 16) & 0xffff));
1048 sii->pub.boardvendor = getintvar(pvars, "manfid");
1049 sii->pub.boardtype = getintvar(pvars, "prodid");
1054 sii->pub.boardvendor = PCI_VENDOR_ID_BROADCOM;
1055 sii->pub.boardtype = getintvar(pvars, "prodid");
1056 if (pvars == NULL || (sii->pub.boardtype == 0)) {
1057 sii->pub.boardtype = getintvar(NULL, "boardtype");
1058 if (sii->pub.boardtype == 0)
1059 sii->pub.boardtype = 0xffff;
1064 if (sii->pub.boardtype == 0) {
1065 SI_ERROR(("si_doattach: unknown board type\n"));
1068 sii->pub.boardflags = getintvar(pvars, "boardflags");
1071 static struct si_info *ai_doattach(struct si_info *sii,
1072 void *regs, uint bustype, void *pbus,
1073 char **vars, uint *varsz)
1075 struct si_pub *sih = &sii->pub;
1082 memset((unsigned char *) sii, 0, sizeof(struct si_info));
1086 sih->buscoreidx = BADIDX;
1091 /* check to see if we are a si core mimic'ing a pci core */
1092 if (bustype == PCI_BUS) {
1093 pci_read_config_dword(sii->pbus, PCI_SPROM_CONTROL, &w);
1094 if (w == 0xffffffff) {
1095 SI_ERROR(("%s: incoming bus is PCI but it's a lie, "
1096 " switching to SI devid:0x%x\n",
1102 /* find Chipcommon address */
1103 if (bustype == PCI_BUS) {
1104 pci_read_config_dword(sii->pbus, PCI_BAR0_WIN, &savewin);
1105 if (!GOODCOREADDR(savewin, SI_ENUM_BASE))
1106 savewin = SI_ENUM_BASE;
1107 pci_write_config_dword(sii->pbus, PCI_BAR0_WIN,
1109 cc = (chipcregs_t *) regs;
1111 cc = (chipcregs_t *) REG_MAP(SI_ENUM_BASE, SI_CORE_SIZE);
1114 sih->bustype = bustype;
1116 /* bus/core/clk setup for register access */
1117 if (!ai_buscore_prep(sii, bustype)) {
1118 SI_ERROR(("si_doattach: si_core_clk_prep failed %d\n",
1124 * ChipID recognition.
1125 * We assume we can read chipid at offset 0 from the regs arg.
1126 * If we add other chiptypes (or if we need to support old sdio
1127 * hosts w/o chipcommon), some way of recognizing them needs to
1130 w = R_REG(&cc->chipid);
1131 socitype = (w & CID_TYPE_MASK) >> CID_TYPE_SHIFT;
1132 /* Might as wll fill in chip id rev & pkg */
1133 sih->chip = w & CID_ID_MASK;
1134 sih->chiprev = (w & CID_REV_MASK) >> CID_REV_SHIFT;
1135 sih->chippkg = (w & CID_PKG_MASK) >> CID_PKG_SHIFT;
1137 sih->issim = IS_SIM(sih->chippkg);
1139 /* scan for cores */
1140 if (socitype == SOCI_AI) {
1141 SI_MSG(("Found chip type AI (0x%08x)\n", w));
1142 /* pass chipc address instead of original core base */
1143 ai_scan(&sii->pub, (void *)cc);
1145 SI_ERROR(("Found chip of unknown type (0x%08x)\n", w));
1148 /* no cores found, bail out */
1149 if (sii->numcores == 0) {
1150 SI_ERROR(("si_doattach: could not find any cores\n"));
1153 /* bus/core/clk setup */
1154 origidx = SI_CC_IDX;
1155 if (!ai_buscore_setup(sii, cc, bustype, savewin, &origidx, regs)) {
1156 SI_ERROR(("si_doattach: si_buscore_setup failed\n"));
1160 /* Init nvram from sprom/otp if they exist */
1162 (&sii->pub, bustype, regs, vars, varsz)) {
1163 SI_ERROR(("si_doattach: srom_var_init failed: bad srom\n"));
1166 pvars = vars ? *vars : NULL;
1167 ai_nvram_process(sii, pvars);
1169 /* === NVRAM, clock is ready === */
1170 cc = (chipcregs_t *) ai_setcore(sih, CC_CORE_ID, 0);
1171 W_REG(&cc->gpiopullup, 0);
1172 W_REG(&cc->gpiopulldown, 0);
1173 ai_setcoreidx(sih, origidx);
1175 /* PMU specific initializations */
1176 if (PMUCTL_ENAB(sih)) {
1179 si_pmu_chip_init(sih);
1180 xtalfreq = getintvar(pvars, "xtalfreq");
1181 /* If xtalfreq var not available, try to measure it */
1183 xtalfreq = si_pmu_measure_alpclk(sih);
1184 si_pmu_pll_init(sih, xtalfreq);
1185 si_pmu_res_init(sih);
1186 si_pmu_swreg_init(sih);
1189 /* setup the GPIO based LED powersave register */
1190 w = getintvar(pvars, "leddc");
1192 w = DEFAULT_GPIOTIMERVAL;
1193 ai_corereg(sih, SI_CC_IDX, offsetof(chipcregs_t, gpiotimerval), ~0, w);
1196 pcicore_attach(sii->pch, pvars, SI_DOATTACH);
1199 if (sih->chip == BCM43224_CHIP_ID) {
1201 * enable 12 mA drive strenth for 43224 and
1202 * set chipControl register bit 15
1204 if (sih->chiprev == 0) {
1205 SI_MSG(("Applying 43224A0 WARs\n"));
1206 ai_corereg(sih, SI_CC_IDX,
1207 offsetof(chipcregs_t, chipcontrol),
1208 CCTRL43224_GPIO_TOGGLE,
1209 CCTRL43224_GPIO_TOGGLE);
1210 si_pmu_chipcontrol(sih, 0, CCTRL_43224A0_12MA_LED_DRIVE,
1211 CCTRL_43224A0_12MA_LED_DRIVE);
1213 if (sih->chiprev >= 1) {
1214 SI_MSG(("Applying 43224B0+ WARs\n"));
1215 si_pmu_chipcontrol(sih, 0, CCTRL_43224B0_12MA_LED_DRIVE,
1216 CCTRL_43224B0_12MA_LED_DRIVE);
1220 if (sih->chip == BCM4313_CHIP_ID) {
1222 * enable 12 mA drive strenth for 4313 and
1223 * set chipControl register bit 1
1225 SI_MSG(("Applying 4313 WARs\n"));
1226 si_pmu_chipcontrol(sih, 0, CCTRL_4313_12MA_LED_DRIVE,
1227 CCTRL_4313_12MA_LED_DRIVE);
1232 if (sih->bustype == PCI_BUS) {
1234 pcicore_deinit(sii->pch);
1241 /* may be called with core in reset */
1242 void ai_detach(struct si_pub *sih)
1244 struct si_info *sii;
1247 struct si_pub *si_local = NULL;
1248 memcpy(&si_local, &sih, sizeof(struct si_pub **));
1255 if (sih->bustype == SI_BUS)
1256 for (idx = 0; idx < SI_MAXCORES; idx++)
1257 if (sii->regs[idx]) {
1258 iounmap(sii->regs[idx]);
1259 sii->regs[idx] = NULL;
1262 if (sih->bustype == PCI_BUS) {
1264 pcicore_deinit(sii->pch);
1272 /* register driver interrupt disabling and restoring callback functions */
1274 ai_register_intr_callback(struct si_pub *sih, void *intrsoff_fn,
1275 void *intrsrestore_fn,
1276 void *intrsenabled_fn, void *intr_arg)
1278 struct si_info *sii;
1281 sii->intr_arg = intr_arg;
1282 sii->intrsoff_fn = (si_intrsoff_t) intrsoff_fn;
1283 sii->intrsrestore_fn = (si_intrsrestore_t) intrsrestore_fn;
1284 sii->intrsenabled_fn = (si_intrsenabled_t) intrsenabled_fn;
1285 /* save current core id. when this function called, the current core
1286 * must be the core which provides driver functions(il, et, wl, etc.)
1288 sii->dev_coreid = sii->coreid[sii->curidx];
1291 void ai_deregister_intr_callback(struct si_pub *sih)
1293 struct si_info *sii;
1296 sii->intrsoff_fn = NULL;
1299 uint ai_coreid(struct si_pub *sih)
1301 struct si_info *sii;
1304 return sii->coreid[sii->curidx];
1307 uint ai_coreidx(struct si_pub *sih)
1309 struct si_info *sii;
1315 bool ai_backplane64(struct si_pub *sih)
1317 return (sih->cccaps & CC_CAP_BKPLN64) != 0;
1320 /* return index of coreid or BADIDX if not found */
1321 uint ai_findcoreidx(struct si_pub *sih, uint coreid, uint coreunit)
1323 struct si_info *sii;
1331 for (i = 0; i < sii->numcores; i++)
1332 if (sii->coreid[i] == coreid) {
1333 if (found == coreunit)
1342 * This function changes logical "focus" to the indicated core;
1343 * must be called with interrupts off.
1344 * Moreover, callers should keep interrupts off during switching
1345 * out of and back to d11 core.
1347 void *ai_setcore(struct si_pub *sih, uint coreid, uint coreunit)
1351 idx = ai_findcoreidx(sih, coreid, coreunit);
1355 return ai_setcoreidx(sih, idx);
1358 /* Turn off interrupt as required by ai_setcore, before switch core */
1359 void *ai_switch_core(struct si_pub *sih, uint coreid, uint *origidx,
1363 struct si_info *sii;
1368 /* Overloading the origidx variable to remember the coreid,
1369 * this works because the core ids cannot be confused with
1373 if (coreid == CC_CORE_ID)
1374 return (void *)CCREGS_FAST(sii);
1375 else if (coreid == sih->buscoretype)
1376 return (void *)PCIEREGS(sii);
1378 INTR_OFF(sii, *intr_val);
1379 *origidx = sii->curidx;
1380 cc = ai_setcore(sih, coreid, 0);
1384 /* restore coreidx and restore interrupt */
1385 void ai_restore_core(struct si_pub *sih, uint coreid, uint intr_val)
1387 struct si_info *sii;
1391 && ((coreid == CC_CORE_ID) || (coreid == sih->buscoretype)))
1394 ai_setcoreidx(sih, coreid);
1395 INTR_RESTORE(sii, intr_val);
1398 void ai_write_wrapperreg(struct si_pub *sih, u32 offset, u32 val)
1400 struct si_info *sii = SI_INFO(sih);
1401 u32 *w = (u32 *) sii->curwrap;
1402 W_REG(w + (offset / 4), val);
1407 * Switch to 'coreidx', issue a single arbitrary 32bit register mask&set
1408 * operation, switch back to the original core, and return the new value.
1410 * When using the silicon backplane, no fiddling with interrupts or core
1411 * switches is needed.
1413 * Also, when using pci/pcie, we can optimize away the core switching for pci
1414 * registers and (on newer pci cores) chipcommon registers.
1416 uint ai_corereg(struct si_pub *sih, uint coreidx, uint regoff, uint mask,
1424 struct si_info *sii;
1428 if (coreidx >= SI_MAXCORES)
1431 if (sih->bustype == SI_BUS) {
1432 /* If internal bus, we can always get at everything */
1434 /* map if does not exist */
1435 if (!sii->regs[coreidx]) {
1436 sii->regs[coreidx] = REG_MAP(sii->coresba[coreidx],
1439 r = (u32 *) ((unsigned char *) sii->regs[coreidx] + regoff);
1440 } else if (sih->bustype == PCI_BUS) {
1442 * If pci/pcie, we can get at pci/pcie regs
1443 * and on newer cores to chipc
1445 if ((sii->coreid[coreidx] == CC_CORE_ID) && SI_FAST(sii)) {
1446 /* Chipc registers are mapped at 12KB */
1449 r = (u32 *) ((char *)sii->curmap +
1450 PCI_16KB0_CCREGS_OFFSET + regoff);
1451 } else if (sii->pub.buscoreidx == coreidx) {
1453 * pci registers are at either in the last 2KB of
1454 * an 8KB window or, in pcie and pci rev 13 at 8KB
1458 r = (u32 *) ((char *)sii->curmap +
1459 PCI_16KB0_PCIREGS_OFFSET +
1462 r = (u32 *) ((char *)sii->curmap +
1463 ((regoff >= SBCONFIGOFF) ?
1464 PCI_BAR0_PCISBR_OFFSET :
1465 PCI_BAR0_PCIREGS_OFFSET) +
1471 INTR_OFF(sii, intr_val);
1473 /* save current core index */
1474 origidx = ai_coreidx(&sii->pub);
1477 r = (u32 *) ((unsigned char *) ai_setcoreidx(&sii->pub, coreidx)
1483 w = (R_REG(r) & ~mask) | val;
1491 /* restore core index */
1492 if (origidx != coreidx)
1493 ai_setcoreidx(&sii->pub, origidx);
1495 INTR_RESTORE(sii, intr_val);
1501 void ai_core_disable(struct si_pub *sih, u32 bits)
1503 struct si_info *sii;
1511 /* if core is already in reset, just return */
1512 if (R_REG(&ai->resetctrl) & AIRC_RESET)
1515 W_REG(&ai->ioctrl, bits);
1516 dummy = R_REG(&ai->ioctrl);
1519 W_REG(&ai->resetctrl, AIRC_RESET);
1523 /* reset and re-enable a core
1525 * bits - core specific bits that are set during and after reset sequence
1526 * resetbits - core specific bits that are set only during reset sequence
1528 void ai_core_reset(struct si_pub *sih, u32 bits, u32 resetbits)
1530 struct si_info *sii;
1538 * Must do the disable sequence first to work
1539 * for arbitrary current core state.
1541 ai_core_disable(sih, (bits | resetbits));
1544 * Now do the initialization sequence.
1546 W_REG(&ai->ioctrl, (bits | SICF_FGC | SICF_CLOCK_EN));
1547 dummy = R_REG(&ai->ioctrl);
1548 W_REG(&ai->resetctrl, 0);
1551 W_REG(&ai->ioctrl, (bits | SICF_CLOCK_EN));
1552 dummy = R_REG(&ai->ioctrl);
1556 /* return the slow clock source - LPO, XTAL, or PCI */
1557 static uint ai_slowclk_src(struct si_info *sii)
1562 if (sii->pub.ccrev < 6) {
1563 if (sii->pub.bustype == PCI_BUS) {
1564 pci_read_config_dword(sii->pbus, PCI_GPIO_OUT,
1566 if (val & PCI_CFG_GPIO_SCS)
1570 } else if (sii->pub.ccrev < 10) {
1571 cc = (chipcregs_t *) ai_setcoreidx(&sii->pub, sii->curidx);
1572 return R_REG(&cc->slow_clk_ctl) & SCC_SS_MASK;
1573 } else /* Insta-clock */
1578 * return the ILP (slowclock) min or max frequency
1579 * precondition: we've established the chip has dynamic clk control
1581 static uint ai_slowclk_freq(struct si_info *sii, bool max_freq, chipcregs_t *cc)
1586 slowclk = ai_slowclk_src(sii);
1587 if (sii->pub.ccrev < 6) {
1588 if (slowclk == SCC_SS_PCI)
1589 return max_freq ? (PCIMAXFREQ / 64)
1590 : (PCIMINFREQ / 64);
1592 return max_freq ? (XTALMAXFREQ / 32)
1593 : (XTALMINFREQ / 32);
1594 } else if (sii->pub.ccrev < 10) {
1596 (((R_REG(&cc->slow_clk_ctl) & SCC_CD_MASK) >>
1598 if (slowclk == SCC_SS_LPO)
1599 return max_freq ? LPOMAXFREQ : LPOMINFREQ;
1600 else if (slowclk == SCC_SS_XTAL)
1601 return max_freq ? (XTALMAXFREQ / div)
1602 : (XTALMINFREQ / div);
1603 else if (slowclk == SCC_SS_PCI)
1604 return max_freq ? (PCIMAXFREQ / div)
1605 : (PCIMINFREQ / div);
1607 /* Chipc rev 10 is InstaClock */
1608 div = R_REG(&cc->system_clk_ctl) >> SYCC_CD_SHIFT;
1609 div = 4 * (div + 1);
1610 return max_freq ? XTALMAXFREQ : (XTALMINFREQ / div);
1615 static void ai_clkctl_setdelay(struct si_info *sii, void *chipcregs)
1617 chipcregs_t *cc = (chipcregs_t *) chipcregs;
1618 uint slowmaxfreq, pll_delay, slowclk;
1619 uint pll_on_delay, fref_sel_delay;
1621 pll_delay = PLL_DELAY;
1624 * If the slow clock is not sourced by the xtal then
1625 * add the xtal_on_delay since the xtal will also be
1626 * powered down by dynamic clk control logic.
1629 slowclk = ai_slowclk_src(sii);
1630 if (slowclk != SCC_SS_XTAL)
1631 pll_delay += XTAL_ON_DELAY;
1633 /* Starting with 4318 it is ILP that is used for the delays */
1635 ai_slowclk_freq(sii, (sii->pub.ccrev >= 10) ? false : true, cc);
1637 pll_on_delay = ((slowmaxfreq * pll_delay) + 999999) / 1000000;
1638 fref_sel_delay = ((slowmaxfreq * FREF_DELAY) + 999999) / 1000000;
1640 W_REG(&cc->pll_on_delay, pll_on_delay);
1641 W_REG(&cc->fref_sel_delay, fref_sel_delay);
1644 /* initialize power control delay registers */
1645 void ai_clkctl_init(struct si_pub *sih)
1647 struct si_info *sii;
1652 if (!CCCTL_ENAB(sih))
1656 fast = SI_FAST(sii);
1658 origidx = sii->curidx;
1659 cc = (chipcregs_t *) ai_setcore(sih, CC_CORE_ID, 0);
1663 cc = (chipcregs_t *) CCREGS_FAST(sii);
1668 /* set all Instaclk chip ILP to 1 MHz */
1669 if (sih->ccrev >= 10)
1670 SET_REG(&cc->system_clk_ctl, SYCC_CD_MASK,
1671 (ILP_DIV_1MHZ << SYCC_CD_SHIFT));
1673 ai_clkctl_setdelay(sii, (void *)cc);
1676 ai_setcoreidx(sih, origidx);
1680 * return the value suitable for writing to the
1681 * dot11 core FAST_PWRUP_DELAY register
1683 u16 ai_clkctl_fast_pwrup_delay(struct si_pub *sih)
1685 struct si_info *sii;
1694 if (PMUCTL_ENAB(sih)) {
1695 INTR_OFF(sii, intr_val);
1696 fpdelay = si_pmu_fast_pwrup_delay(sih);
1697 INTR_RESTORE(sii, intr_val);
1701 if (!CCCTL_ENAB(sih))
1704 fast = SI_FAST(sii);
1707 origidx = sii->curidx;
1708 INTR_OFF(sii, intr_val);
1709 cc = (chipcregs_t *) ai_setcore(sih, CC_CORE_ID, 0);
1713 cc = (chipcregs_t *) CCREGS_FAST(sii);
1718 slowminfreq = ai_slowclk_freq(sii, false, cc);
1719 fpdelay = (((R_REG(&cc->pll_on_delay) + 2) * 1000000) +
1720 (slowminfreq - 1)) / slowminfreq;
1724 ai_setcoreidx(sih, origidx);
1725 INTR_RESTORE(sii, intr_val);
1730 /* turn primary xtal and/or pll off/on */
1731 int ai_clkctl_xtal(struct si_pub *sih, uint what, bool on)
1733 struct si_info *sii;
1738 switch (sih->bustype) {
1741 /* pcie core doesn't have any mapping to control the xtal pu */
1745 pci_read_config_dword(sii->pbus, PCI_GPIO_IN, &in);
1746 pci_read_config_dword(sii->pbus, PCI_GPIO_OUT, &out);
1747 pci_read_config_dword(sii->pbus, PCI_GPIO_OUTEN, &outen);
1750 * Avoid glitching the clock if GPRS is already using it.
1751 * We can't actually read the state of the PLLPD so we infer it
1752 * by the value of XTAL_PU which *is* readable via gpioin.
1754 if (on && (in & PCI_CFG_GPIO_XTAL))
1758 outen |= PCI_CFG_GPIO_XTAL;
1760 outen |= PCI_CFG_GPIO_PLL;
1763 /* turn primary xtal on */
1765 out |= PCI_CFG_GPIO_XTAL;
1767 out |= PCI_CFG_GPIO_PLL;
1768 pci_write_config_dword(sii->pbus,
1770 pci_write_config_dword(sii->pbus,
1771 PCI_GPIO_OUTEN, outen);
1772 udelay(XTAL_ON_DELAY);
1777 out &= ~PCI_CFG_GPIO_PLL;
1778 pci_write_config_dword(sii->pbus,
1784 out &= ~PCI_CFG_GPIO_XTAL;
1786 out |= PCI_CFG_GPIO_PLL;
1787 pci_write_config_dword(sii->pbus,
1789 pci_write_config_dword(sii->pbus,
1790 PCI_GPIO_OUTEN, outen);
1801 * clock control policy function throught chipcommon
1803 * set dynamic clk control mode (forceslow, forcefast, dynamic)
1804 * returns true if we are forcing fast clock
1805 * this is a wrapper over the next internal function
1806 * to allow flexible policy settings for outside caller
1808 bool ai_clkctl_cc(struct si_pub *sih, uint mode)
1810 struct si_info *sii;
1814 /* chipcommon cores prior to rev6 don't support dynamic clock control */
1818 if (PCI_FORCEHT(sii))
1819 return mode == CLK_FAST;
1821 return _ai_clkctl_cc(sii, mode);
1824 /* clk control mechanism through chipcommon, no policy checking */
1825 static bool _ai_clkctl_cc(struct si_info *sii, uint mode)
1831 bool fast = SI_FAST(sii);
1833 /* chipcommon cores prior to rev6 don't support dynamic clock control */
1834 if (sii->pub.ccrev < 6)
1838 INTR_OFF(sii, intr_val);
1839 origidx = sii->curidx;
1841 if ((sii->pub.bustype == SI_BUS) &&
1842 ai_setcore(&sii->pub, MIPS33_CORE_ID, 0) &&
1843 (ai_corerev(&sii->pub) <= 7) && (sii->pub.ccrev >= 10))
1846 cc = (chipcregs_t *) ai_setcore(&sii->pub, CC_CORE_ID, 0);
1848 cc = (chipcregs_t *) CCREGS_FAST(sii);
1853 if (!CCCTL_ENAB(&sii->pub) && (sii->pub.ccrev < 20))
1857 case CLK_FAST: /* FORCEHT, fast (pll) clock */
1858 if (sii->pub.ccrev < 10) {
1860 * don't forget to force xtal back
1861 * on before we clear SCC_DYN_XTAL..
1863 ai_clkctl_xtal(&sii->pub, XTAL, ON);
1864 SET_REG(&cc->slow_clk_ctl,
1865 (SCC_XC | SCC_FS | SCC_IP), SCC_IP);
1866 } else if (sii->pub.ccrev < 20) {
1867 OR_REG(&cc->system_clk_ctl, SYCC_HR);
1869 OR_REG(&cc->clk_ctl_st, CCS_FORCEHT);
1872 /* wait for the PLL */
1873 if (PMUCTL_ENAB(&sii->pub)) {
1874 u32 htavail = CCS_HTAVAIL;
1875 SPINWAIT(((R_REG(&cc->clk_ctl_st) & htavail)
1876 == 0), PMU_MAX_TRANSITION_DLY);
1882 case CLK_DYNAMIC: /* enable dynamic clock control */
1883 if (sii->pub.ccrev < 10) {
1884 scc = R_REG(&cc->slow_clk_ctl);
1885 scc &= ~(SCC_FS | SCC_IP | SCC_XC);
1886 if ((scc & SCC_SS_MASK) != SCC_SS_XTAL)
1888 W_REG(&cc->slow_clk_ctl, scc);
1891 * for dynamic control, we have to
1892 * release our xtal_pu "force on"
1895 ai_clkctl_xtal(&sii->pub, XTAL, OFF);
1896 } else if (sii->pub.ccrev < 20) {
1898 AND_REG(&cc->system_clk_ctl, ~SYCC_HR);
1900 AND_REG(&cc->clk_ctl_st, ~CCS_FORCEHT);
1910 ai_setcoreidx(&sii->pub, origidx);
1911 INTR_RESTORE(sii, intr_val);
1913 return mode == CLK_FAST;
1916 /* Build device path. Support SI, PCI, and JTAG for now. */
1917 int ai_devpath(struct si_pub *sih, char *path, int size)
1921 if (!path || size <= 0)
1924 switch (sih->bustype) {
1927 slen = snprintf(path, (size_t) size, "sb/%u/", ai_coreidx(sih));
1930 slen = snprintf(path, (size_t) size, "pci/%u/%u/",
1931 ((struct pci_dev *)((SI_INFO(sih))->pbus))->bus->number,
1933 ((struct pci_dev *)((SI_INFO(sih))->pbus))->devfn));
1941 if (slen < 0 || slen >= size) {
1949 /* Get a variable, but only if it has a devpath prefix */
1950 char *ai_getdevpathvar(struct si_pub *sih, const char *name)
1952 char varname[SI_DEVPATH_BUFSZ + 32];
1954 ai_devpathvar(sih, varname, sizeof(varname), name);
1956 return getvar(NULL, varname);
1959 /* Get a variable, but only if it has a devpath prefix */
1960 int ai_getdevpathintvar(struct si_pub *sih, const char *name)
1962 #if defined(BCMBUSTYPE) && (BCMBUSTYPE == SI_BUS)
1963 return getintvar(NULL, name);
1965 char varname[SI_DEVPATH_BUFSZ + 32];
1967 ai_devpathvar(sih, varname, sizeof(varname), name);
1969 return getintvar(NULL, varname);
1973 char *ai_getnvramflvar(struct si_pub *sih, const char *name)
1975 return getvar(NULL, name);
1978 /* Concatenate the dev path with a varname into the given 'var' buffer
1979 * and return the 'var' pointer. Nothing is done to the arguments if
1980 * len == 0 or var is NULL, var is still returned. On overflow, the
1981 * first char will be set to '\0'.
1983 static char *ai_devpathvar(struct si_pub *sih, char *var, int len,
1988 if (!var || len <= 0)
1991 if (ai_devpath(sih, var, len) == 0) {
1992 path_len = strlen(var);
1994 if (strlen(name) + 1 > (uint) (len - path_len))
1997 strncpy(var + path_len, name, len - path_len - 1);
2003 /* return true if PCIE capability exists in the pci config space */
2004 static bool ai_ispcie(struct si_info *sii)
2008 if (sii->pub.bustype != PCI_BUS)
2012 pcicore_find_pci_capability(sii->pbus, PCI_CAP_ID_EXP, NULL,
2020 bool ai_pci_war16165(struct si_pub *sih)
2022 struct si_info *sii;
2026 return PCI(sii) && (sih->buscorerev <= 10);
2029 void ai_pci_up(struct si_pub *sih)
2031 struct si_info *sii;
2035 /* if not pci bus, we're done */
2036 if (sih->bustype != PCI_BUS)
2039 if (PCI_FORCEHT(sii))
2040 _ai_clkctl_cc(sii, CLK_FAST);
2043 pcicore_up(sii->pch, SI_PCIUP);
2047 /* Unconfigure and/or apply various WARs when system is going to sleep mode */
2048 void ai_pci_sleep(struct si_pub *sih)
2050 struct si_info *sii;
2054 pcicore_sleep(sii->pch);
2057 /* Unconfigure and/or apply various WARs when going down */
2058 void ai_pci_down(struct si_pub *sih)
2060 struct si_info *sii;
2064 /* if not pci bus, we're done */
2065 if (sih->bustype != PCI_BUS)
2068 /* release FORCEHT since chip is going to "down" state */
2069 if (PCI_FORCEHT(sii))
2070 _ai_clkctl_cc(sii, CLK_DYNAMIC);
2072 pcicore_down(sii->pch, SI_PCIDOWN);
2076 * Configure the pci core for pci client (NIC) action
2077 * coremask is the bitvec of cores by index to be enabled.
2079 void ai_pci_setup(struct si_pub *sih, uint coremask)
2081 struct si_info *sii;
2088 if (sii->pub.bustype != PCI_BUS)
2092 /* get current core index */
2095 /* we interrupt on this backplane flag number */
2096 siflag = ai_flag(sih);
2098 /* switch over to pci core */
2099 regs = ai_setcoreidx(sih, sii->pub.buscoreidx);
2103 * Enable sb->pci interrupts. Assume
2104 * PCI rev 2.3 support was added in pci core rev 6 and things changed..
2106 if (PCIE(sii) || (PCI(sii) && ((sii->pub.buscorerev) >= 6))) {
2107 /* pci config write to set this core bit in PCIIntMask */
2108 pci_read_config_dword(sii->pbus, PCI_INT_MASK, &w);
2109 w |= (coremask << PCI_SBIM_SHIFT);
2110 pci_write_config_dword(sii->pbus, PCI_INT_MASK, w);
2112 /* set sbintvec bit for our flag number */
2113 ai_setint(sih, siflag);
2117 pcicore_pci_setup(sii->pch, regs);
2119 /* switch back to previous core */
2120 ai_setcoreidx(sih, idx);
2125 * Fixup SROMless PCI device's configuration.
2126 * The current core may be changed upon return.
2128 int ai_pci_fixcfg(struct si_pub *sih)
2133 struct si_info *sii = SI_INFO(sih);
2135 /* Fixup PI in SROM shadow area to enable the correct PCI core access */
2136 /* save the current index */
2137 origidx = ai_coreidx(&sii->pub);
2139 /* check 'pi' is correct and fix it if not */
2140 regs = ai_setcore(&sii->pub, sii->pub.buscoretype, 0);
2141 pcicore_fixcfg(sii->pch, regs);
2143 /* restore the original index */
2144 ai_setcoreidx(&sii->pub, origidx);
2146 pcicore_hwup(sii->pch);
2150 /* mask&set gpiocontrol bits */
2151 u32 ai_gpiocontrol(struct si_pub *sih, u32 mask, u32 val, u8 priority)
2157 /* gpios could be shared on router platforms
2158 * ignore reservation if it's high priority (e.g., test apps)
2160 if ((priority != GPIO_HI_PRIORITY) &&
2161 (sih->bustype == SI_BUS) && (val || mask)) {
2162 mask = priority ? (ai_gpioreservation & mask) :
2163 ((ai_gpioreservation | mask) & ~(ai_gpioreservation));
2167 regoff = offsetof(chipcregs_t, gpiocontrol);
2168 return ai_corereg(sih, SI_CC_IDX, regoff, mask, val);
2171 void ai_chipcontrl_epa4331(struct si_pub *sih, bool on)
2173 struct si_info *sii;
2179 origidx = ai_coreidx(sih);
2181 cc = (chipcregs_t *) ai_setcore(sih, CC_CORE_ID, 0);
2183 val = R_REG(&cc->chipcontrol);
2186 if (sih->chippkg == 9 || sih->chippkg == 0xb) {
2187 /* Ext PA Controls for 4331 12x9 Package */
2188 W_REG(&cc->chipcontrol, val |
2189 (CCTRL4331_EXTPA_EN |
2190 CCTRL4331_EXTPA_ON_GPIO2_5));
2192 /* Ext PA Controls for 4331 12x12 Package */
2193 W_REG(&cc->chipcontrol,
2194 val | (CCTRL4331_EXTPA_EN));
2197 val &= ~(CCTRL4331_EXTPA_EN | CCTRL4331_EXTPA_ON_GPIO2_5);
2198 W_REG(&cc->chipcontrol, val);
2201 ai_setcoreidx(sih, origidx);
2204 /* Enable BT-COEX & Ex-PA for 4313 */
2205 void ai_epa_4313war(struct si_pub *sih)
2207 struct si_info *sii;
2212 origidx = ai_coreidx(sih);
2214 cc = (chipcregs_t *) ai_setcore(sih, CC_CORE_ID, 0);
2217 W_REG(&cc->gpiocontrol,
2218 R_REG(&cc->gpiocontrol) | GPIO_CTRL_EPA_EN_MASK);
2220 ai_setcoreidx(sih, origidx);
2223 /* check if the device is removed */
2224 bool ai_deviceremoved(struct si_pub *sih)
2227 struct si_info *sii;
2231 switch (sih->bustype) {
2233 pci_read_config_dword(sii->pbus, PCI_VENDOR_ID, &w);
2234 if ((w & 0xFFFF) != PCI_VENDOR_ID_BROADCOM)
2241 bool ai_is_sprom_available(struct si_pub *sih)
2243 if (sih->ccrev >= 31) {
2244 struct si_info *sii;
2249 if ((sih->cccaps & CC_CAP_SROM) == 0)
2253 origidx = sii->curidx;
2254 cc = ai_setcoreidx(sih, SI_CC_IDX);
2255 sromctrl = R_REG(&cc->sromcontrol);
2256 ai_setcoreidx(sih, origidx);
2257 return sromctrl & SRC_PRESENT;
2260 switch (sih->chip) {
2261 case BCM4313_CHIP_ID:
2262 return (sih->chipst & CST4313_SPROM_PRESENT) != 0;
2268 bool ai_is_otp_disabled(struct si_pub *sih)
2270 switch (sih->chip) {
2271 case BCM4313_CHIP_ID:
2272 return (sih->chipst & CST4313_OTP_PRESENT) == 0;
2273 /* These chips always have their OTP on */
2274 case BCM43224_CHIP_ID:
2275 case BCM43225_CHIP_ID: