drivers/staging/brcm80211/brcmsmac/bmac.c

   1 /*
   2  * Copyright (c) 2010 Broadcom Corporation
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
  11  * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
  13  * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
  14  * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16 #include <linux/pci.h>
  17 #include <net/mac80211.h>
  18
  19 #include <brcm_hw_ids.h>
  20 #include <aiutils.h>
  21 #include <chipcommon.h>
  22 #include "types.h"
  23 #include "rate.h"
  24 #include "phy/phy_hal.h"
  25 #include "channel.h"
  26 #include "main.h"
  27 #include "ucode_loader.h"
  28 #include "mac80211_if.h"
  29 #include "bmac.h"
  30
  31 #define TIMER_INTERVAL_WATCHDOG_BMAC    1000    /* watchdog timer, in unit of ms */
  32
  33 #define SYNTHPU_DLY_APHY_US     3700    /* a phy synthpu_dly time in us */
  34 #define SYNTHPU_DLY_BPHY_US     1050    /* b/g phy synthpu_dly time in us, default */
  35 #define SYNTHPU_DLY_NPHY_US     2048    /* n phy REV3 synthpu_dly time in us, default */
  36 #define SYNTHPU_DLY_LPPHY_US    300     /* lpphy synthpu_dly time in us */
  37
  38 #define SYNTHPU_DLY_PHY_US_QT   100     /* QT synthpu_dly time in us */
  39
  40 #ifndef BMAC_DUP_TO_REMOVE
  41 #define WLC_RM_WAIT_TX_SUSPEND          4       /* Wait Tx Suspend */
  42
  43 #define ANTCNT                  10      /* vanilla M_MAX_ANTCNT value */
  44
  45 #endif                          /* BMAC_DUP_TO_REMOVE */
  46
  47 #define DMAREG(wlc_hw, direction, fifonum) \
  48         ((direction == DMA_TX) ? \
  49                 (void *)&(wlc_hw->regs->fifo64regs[fifonum].dmaxmt) : \
  50                 (void *)&(wlc_hw->regs->fifo64regs[fifonum].dmarcv))
  51
  52 #define APHY_SLOT_TIME          9
  53 #define BPHY_SLOT_TIME          20
  54
  55 /*
  56  * The following table lists the buffer memory allocated to xmt fifos in HW.
  57  * the size is in units of 256bytes(one block), total size is HW dependent
  58  * ucode has default fifo partition, sw can overwrite if necessary
  59  *
  60  * This is documented in twiki under the topic UcodeTxFifo. Please ensure
  61  * the twiki is updated before making changes.
  62  */
  63
  64 #define XMTFIFOTBL_STARTREV     20      /* Starting corerev for the fifo size table */
  65
  66 static u16 xmtfifo_sz[][NFIFO] = {
  67         {20, 192, 192, 21, 17, 5},      /* corerev 20: 5120, 49152, 49152, 5376, 4352, 1280 */
  68         {9, 58, 22, 14, 14, 5}, /* corerev 21: 2304, 14848, 5632, 3584, 3584, 1280 */
  69         {20, 192, 192, 21, 17, 5},      /* corerev 22: 5120, 49152, 49152, 5376, 4352, 1280 */
  70         {20, 192, 192, 21, 17, 5},      /* corerev 23: 5120, 49152, 49152, 5376, 4352, 1280 */
  71         {9, 58, 22, 14, 14, 5}, /* corerev 24: 2304, 14848, 5632, 3584, 3584, 1280 */
  72 };
  73
  74 static void brcms_b_clkctl_clk(struct wlc_hw_info *wlc, uint mode);
  75 static void brcms_b_coreinit(struct wlc_info *wlc);
  76
  77 /* used by wlc_wakeucode_init() */
  78 static void wlc_write_inits(struct wlc_hw_info *wlc_hw,
  79                             const struct d11init *inits);
  80 static void wlc_ucode_write(struct wlc_hw_info *wlc_hw, const u32 ucode[],
  81                             const uint nbytes);
  82 static void wlc_ucode_download(struct wlc_hw_info *wlc);
  83 static void wlc_ucode_txant_set(struct wlc_hw_info *wlc_hw);
  84
  85 /* used by wlc_dpc() */
  86 static bool brcms_b_dotxstatus(struct wlc_hw_info *wlc, tx_status_t *txs,
  87                                 u32 s2);
  88 static bool brcms_b_txstatus(struct wlc_hw_info *wlc, bool bound, bool *fatal);
  89 static bool brcms_b_recv(struct wlc_hw_info *wlc_hw, uint fifo, bool bound);
  90
  91 /* used by wlc_down() */
  92 static void wlc_flushqueues(struct wlc_info *wlc);
  93
  94 static void wlc_write_mhf(struct wlc_hw_info *wlc_hw, u16 *mhfs);
  95 static void wlc_mctrl_reset(struct wlc_hw_info *wlc_hw);
  96 static void brcms_b_corerev_fifofixup(struct wlc_hw_info *wlc_hw);
  97 static bool brcms_b_tx_fifo_suspended(struct wlc_hw_info *wlc_hw,
  98                                        uint tx_fifo);
  99 static void brcms_b_tx_fifo_suspend(struct wlc_hw_info *wlc_hw, uint tx_fifo);
 100 static void brcms_b_tx_fifo_resume(struct wlc_hw_info *wlc_hw, uint tx_fifo);
 101
 102 /* Low Level Prototypes */
 103 static int brcms_b_bandtype(struct wlc_hw_info *wlc_hw);
 104 static void brcms_b_info_init(struct wlc_hw_info *wlc_hw);
 105 static void brcms_b_xtal(struct wlc_hw_info *wlc_hw, bool want);
 106 static u16 brcms_b_read_objmem(struct wlc_hw_info *wlc_hw, uint offset,
 107                                    u32 sel);
 108 static void brcms_b_write_objmem(struct wlc_hw_info *wlc_hw, uint offset,
 109                                   u16 v, u32 sel);
 110 static void brcms_b_core_phy_clk(struct wlc_hw_info *wlc_hw, bool clk);
 111 static bool brcms_b_attach_dmapio(struct wlc_info *wlc, uint j, bool wme);
 112 static void brcms_b_detach_dmapio(struct wlc_hw_info *wlc_hw);
 113 static void wlc_ucode_bsinit(struct wlc_hw_info *wlc_hw);
 114 static bool wlc_validboardtype(struct wlc_hw_info *wlc);
 115 static bool wlc_isgoodchip(struct wlc_hw_info *wlc_hw);
 116 static bool brcms_b_validate_chip_access(struct wlc_hw_info *wlc_hw);
 117 static char *wlc_get_macaddr(struct wlc_hw_info *wlc_hw);
 118 static void wlc_mhfdef(struct wlc_info *wlc, u16 *mhfs, u16 mhf2_init);
 119 static void wlc_mctrl_write(struct wlc_hw_info *wlc_hw);
 120 static void brcms_b_mute(struct wlc_hw_info *wlc_hw, bool want, mbool flags);
 121 static void wlc_ucode_mute_override_set(struct wlc_hw_info *wlc_hw);
 122 static void wlc_ucode_mute_override_clear(struct wlc_hw_info *wlc_hw);
 123 static u32 wlc_wlintrsoff(struct wlc_info *wlc);
 124 static void wlc_wlintrsrestore(struct wlc_info *wlc, u32 macintmask);
 125 static void wlc_gpio_init(struct wlc_info *wlc);
 126 static void wlc_write_hw_bcntemplate0(struct wlc_hw_info *wlc_hw, void *bcn,
 127                                       int len);
 128 static void wlc_write_hw_bcntemplate1(struct wlc_hw_info *wlc_hw, void *bcn,
 129                                       int len);
 130 static void brcms_b_bsinit(struct wlc_info *wlc, chanspec_t chanspec);
 131 static u32 wlc_setband_inact(struct wlc_info *wlc, uint bandunit);
 132 static void brcms_b_setband(struct wlc_hw_info *wlc_hw, uint bandunit,
 133                              chanspec_t chanspec);
 134 static void brcms_b_update_slot_timing(struct wlc_hw_info *wlc_hw,
 135                                         bool shortslot);
 136 static void wlc_upd_ofdm_pctl1_table(struct wlc_hw_info *wlc_hw);
 137 static u16 brcms_b_ofdm_ratetable_offset(struct wlc_hw_info *wlc_hw,
 138                                              u8 rate);
 139
 140 /* === Low Level functions === */
 141
 142 void brcms_b_set_shortslot(struct wlc_hw_info *wlc_hw, bool shortslot)
 143 {
 144         wlc_hw->shortslot = shortslot;
 145
 146         if (BAND_2G(brcms_b_bandtype(wlc_hw)) && wlc_hw->up) {
 147                 wlc_suspend_mac_and_wait(wlc_hw->wlc);
 148                 brcms_b_update_slot_timing(wlc_hw, shortslot);
 149                 wlc_enable_mac(wlc_hw->wlc);
 150         }
 151 }
 152
 153 /*
 154  * Update the slot timing for standard 11b/g (20us slots)
 155  * or shortslot 11g (9us slots)
 156  * The PSM needs to be suspended for this call.
 157  */
 158 static void brcms_b_update_slot_timing(struct wlc_hw_info *wlc_hw,
 159                                         bool shortslot)
 160 {
 161         d11regs_t *regs;
 162
 163         regs = wlc_hw->regs;
 164
 165         if (shortslot) {
 166                 /* 11g short slot: 11a timing */
 167                 W_REG(&regs->ifs_slot, 0x0207); /* APHY_SLOT_TIME */
 168                 brcms_b_write_shm(wlc_hw, M_DOT11_SLOT, APHY_SLOT_TIME);
 169         } else {
 170                 /* 11g long slot: 11b timing */
 171                 W_REG(&regs->ifs_slot, 0x0212); /* BPHY_SLOT_TIME */
 172                 brcms_b_write_shm(wlc_hw, M_DOT11_SLOT, BPHY_SLOT_TIME);
 173         }
 174 }
 175
 176 static void WLBANDINITFN(wlc_ucode_bsinit) (struct wlc_hw_info *wlc_hw)
 177 {
 178         struct wiphy *wiphy = wlc_hw->wlc->wiphy;
 179
 180         /* init microcode host flags */
 181         wlc_write_mhf(wlc_hw, wlc_hw->band->mhfs);
 182
 183         /* do band-specific ucode IHR, SHM, and SCR inits */
 184         if (D11REV_IS(wlc_hw->corerev, 23)) {
 185                 if (WLCISNPHY(wlc_hw->band)) {
 186                         wlc_write_inits(wlc_hw, d11n0bsinitvals16);
 187                 } else {
 188                         wiphy_err(wiphy, "%s: wl%d: unsupported phy in corerev"
 189                                   " %d\n", __func__, wlc_hw->unit,
 190                                   wlc_hw->corerev);
 191                 }
 192         } else {
 193                 if (D11REV_IS(wlc_hw->corerev, 24)) {
 194                         if (WLCISLCNPHY(wlc_hw->band)) {
 195                                 wlc_write_inits(wlc_hw, d11lcn0bsinitvals24);
 196                         } else
 197                                 wiphy_err(wiphy, "%s: wl%d: unsupported phy in"
 198                                           " core rev %d\n", __func__,
 199                                           wlc_hw->unit, wlc_hw->corerev);
 200                 } else {
 201                         wiphy_err(wiphy, "%s: wl%d: unsupported corerev %d\n",
 202                                 __func__, wlc_hw->unit, wlc_hw->corerev);
 203                 }
 204         }
 205 }
 206
 207 /* switch to new band but leave it inactive */
 208 static u32 WLBANDINITFN(wlc_setband_inact) (struct wlc_info *wlc, uint bandunit)
 209 {
 210         struct wlc_hw_info *wlc_hw = wlc->hw;
 211         u32 macintmask;
 212
 213         BCMMSG(wlc->wiphy, "wl%d\n", wlc_hw->unit);
 214
 215         WARN_ON((R_REG(&wlc_hw->regs->maccontrol) & MCTL_EN_MAC) != 0);
 216
 217         /* disable interrupts */
 218         macintmask = brcms_intrsoff(wlc->wl);
 219
 220         /* radio off */
 221         wlc_phy_switch_radio(wlc_hw->band->pi, OFF);
 222
 223         brcms_b_core_phy_clk(wlc_hw, OFF);
 224
 225         wlc_setxband(wlc_hw, bandunit);
 226
 227         return macintmask;
 228 }
 229
 230 /* Process received frames */
 231 /*
 232  * Return true if more frames need to be processed. false otherwise.
 233  * Param 'bound' indicates max. # frames to process before break out.
 234  */
 235 static bool
 236 brcms_b_recv(struct wlc_hw_info *wlc_hw, uint fifo, bool bound)
 237 {
 238         struct sk_buff *p;
 239         struct sk_buff *head = NULL;
 240         struct sk_buff *tail = NULL;
 241         uint n = 0;
 242         uint bound_limit = bound ? wlc_hw->wlc->pub->tunables->rxbnd : -1;
 243         wlc_d11rxhdr_t *wlc_rxhdr = NULL;
 244
 245         BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
 246         /* gather received frames */
 247         while ((p = dma_rx(wlc_hw->di[fifo]))) {
 248
 249                 if (!tail)
 250                         head = tail = p;
 251                 else {
 252                         tail->prev = p;
 253                         tail = p;
 254                 }
 255
 256                 /* !give others some time to run! */
 257                 if (++n >= bound_limit)
 258                         break;
 259         }
 260
 261         /* post more rbufs */
 262         dma_rxfill(wlc_hw->di[fifo]);
 263
 264         /* process each frame */
 265         while ((p = head) != NULL) {
 266                 head = head->prev;
 267                 p->prev = NULL;
 268
 269                 wlc_rxhdr = (wlc_d11rxhdr_t *) p->data;
 270
 271                 /* compute the RSSI from d11rxhdr and record it in wlc_rxd11hr */
 272                 wlc_phy_rssi_compute(wlc_hw->band->pi, wlc_rxhdr);
 273
 274                 wlc_recv(wlc_hw->wlc, p);
 275         }
 276
 277         return n >= bound_limit;
 278 }
 279
 280 /* second-level interrupt processing
 281  *   Return true if another dpc needs to be re-scheduled. false otherwise.
 282  *   Param 'bounded' indicates if applicable loops should be bounded.
 283  */
 284 bool wlc_dpc(struct wlc_info *wlc, bool bounded)
 285 {
 286         u32 macintstatus;
 287         struct wlc_hw_info *wlc_hw = wlc->hw;
 288         d11regs_t *regs = wlc_hw->regs;
 289         bool fatal = false;
 290         struct wiphy *wiphy = wlc->wiphy;
 291
 292         if (DEVICEREMOVED(wlc)) {
 293                 wiphy_err(wiphy, "wl%d: %s: dead chip\n", wlc_hw->unit,
 294                           __func__);
 295                 brcms_down(wlc->wl);
 296                 return false;
 297         }
 298
 299         /* grab and clear the saved software intstatus bits */
 300         macintstatus = wlc->macintstatus;
 301         wlc->macintstatus = 0;
 302
 303         BCMMSG(wlc->wiphy, "wl%d: macintstatus 0x%x\n",
 304                wlc_hw->unit, macintstatus);
 305
 306         WARN_ON(macintstatus & MI_PRQ); /* PRQ Interrupt in non-MBSS */
 307
 308         /* BCN template is available */
 309         /* ZZZ: Use AP_ACTIVE ? */
 310         if (AP_ENAB(wlc->pub) && (!APSTA_ENAB(wlc->pub))
 311             && (macintstatus & MI_BCNTPL)) {
 312                 wlc_update_beacon(wlc);
 313         }
 314
 315         /* PMQ entry addition */
 316         if (macintstatus & MI_PMQ) {
 317         }
 318
 319         /* tx status */
 320         if (macintstatus & MI_TFS) {
 321                 if (brcms_b_txstatus(wlc->hw, bounded, &fatal))
 322                         wlc->macintstatus |= MI_TFS;
 323                 if (fatal) {
 324                         wiphy_err(wiphy, "MI_TFS: fatal\n");
 325                         goto fatal;
 326                 }
 327         }
 328
 329         if (macintstatus & (MI_TBTT | MI_DTIM_TBTT))
 330                 wlc_tbtt(wlc);
 331
 332         /* ATIM window end */
 333         if (macintstatus & MI_ATIMWINEND) {
 334                 BCMMSG(wlc->wiphy, "end of ATIM window\n");
 335                 OR_REG(&regs->maccommand, wlc->qvalid);
 336                 wlc->qvalid = 0;
 337         }
 338
 339         /* received data or control frame, MI_DMAINT is indication of RX_FIFO interrupt */
 340         if (macintstatus & MI_DMAINT)
 341                 if (brcms_b_recv(wlc_hw, RX_FIFO, bounded))
 342                         wlc->macintstatus |= MI_DMAINT;
 343
 344         /* TX FIFO suspend/flush completion */
 345         if (macintstatus & MI_TXSTOP)
 346                 if (brcms_b_tx_fifo_suspended(wlc_hw, TX_DATA_FIFO));
 347
 348         /* noise sample collected */
 349         if (macintstatus & MI_BG_NOISE) {
 350                 wlc_phy_noise_sample_intr(wlc_hw->band->pi);
 351         }
 352
 353         if (macintstatus & MI_GP0) {
 354                 wiphy_err(wiphy, "wl%d: PSM microcode watchdog fired at %d "
 355                         "(seconds). Resetting.\n", wlc_hw->unit, wlc_hw->now);
 356
 357                 printk_once("%s : PSM Watchdog, chipid 0x%x, chiprev 0x%x\n",
 358                                         __func__, wlc_hw->sih->chip,
 359                                         wlc_hw->sih->chiprev);
 360                 /* big hammer */
 361                 brcms_init(wlc->wl);
 362         }
 363
 364         /* gptimer timeout */
 365         if (macintstatus & MI_TO) {
 366                 W_REG(&regs->gptimer, 0);
 367         }
 368
 369         if (macintstatus & MI_RFDISABLE) {
 370                 BCMMSG(wlc->wiphy, "wl%d: BMAC Detected a change on the"
 371                        " RF Disable Input\n", wlc_hw->unit);
 372                 brcms_rfkill_set_hw_state(wlc->wl);
 373         }
 374
 375         /* send any enq'd tx packets. Just makes sure to jump start tx */
 376         if (!pktq_empty(&wlc->pkt_queue->q))
 377                 wlc_send_q(wlc);
 378
 379         /* it isn't done and needs to be resched if macintstatus is non-zero */
 380         return wlc->macintstatus != 0;
 381
 382  fatal:
 383         brcms_init(wlc->wl);
 384         return wlc->macintstatus != 0;
 385 }
 386
 387 /* common low-level watchdog code */
 388 void brcms_b_watchdog(void *arg)
 389 {
 390         struct wlc_info *wlc = (struct wlc_info *) arg;
 391         struct wlc_hw_info *wlc_hw = wlc->hw;
 392
 393         BCMMSG(wlc->wiphy, "wl%d\n", wlc_hw->unit);
 394
 395         if (!wlc_hw->up)
 396                 return;
 397
 398         /* increment second count */
 399         wlc_hw->now++;
 400
 401         /* Check for FIFO error interrupts */
 402         brcms_b_fifoerrors(wlc_hw);
 403
 404         /* make sure RX dma has buffers */
 405         dma_rxfill(wlc->hw->di[RX_FIFO]);
 406
 407         wlc_phy_watchdog(wlc_hw->band->pi);
 408 }
 409
 410 void
 411 brcms_b_set_chanspec(struct wlc_hw_info *wlc_hw, chanspec_t chanspec,
 412                       bool mute, struct txpwr_limits *txpwr)
 413 {
 414         uint bandunit;
 415
 416         BCMMSG(wlc_hw->wlc->wiphy, "wl%d: 0x%x\n", wlc_hw->unit, chanspec);
 417
 418         wlc_hw->chanspec = chanspec;
 419
 420         /* Switch bands if necessary */
 421         if (NBANDS_HW(wlc_hw) > 1) {
 422                 bandunit = CHSPEC_WLCBANDUNIT(chanspec);
 423                 if (wlc_hw->band->bandunit != bandunit) {
 424                         /* brcms_b_setband disables other bandunit,
 425                          *  use light band switch if not up yet
 426                          */
 427                         if (wlc_hw->up) {
 428                                 wlc_phy_chanspec_radio_set(wlc_hw->
 429                                                            bandstate[bandunit]->
 430                                                            pi, chanspec);
 431                                 brcms_b_setband(wlc_hw, bandunit, chanspec);
 432                         } else {
 433                                 wlc_setxband(wlc_hw, bandunit);
 434                         }
 435                 }
 436         }
 437
 438         wlc_phy_initcal_enable(wlc_hw->band->pi, !mute);
 439
 440         if (!wlc_hw->up) {
 441                 if (wlc_hw->clk)
 442                         wlc_phy_txpower_limit_set(wlc_hw->band->pi, txpwr,
 443                                                   chanspec);
 444                 wlc_phy_chanspec_radio_set(wlc_hw->band->pi, chanspec);
 445         } else {
 446                 wlc_phy_chanspec_set(wlc_hw->band->pi, chanspec);
 447                 wlc_phy_txpower_limit_set(wlc_hw->band->pi, txpwr, chanspec);
 448
 449                 /* Update muting of the channel */
 450                 brcms_b_mute(wlc_hw, mute, 0);
 451         }
 452 }
 453
 454 int brcms_b_state_get(struct wlc_hw_info *wlc_hw, brcms_b_state_t *state)
 455 {
 456         state->machwcap = wlc_hw->machwcap;
 457
 458         return 0;
 459 }
 460
 461 static bool brcms_b_attach_dmapio(struct wlc_info *wlc, uint j, bool wme)
 462 {
 463         uint i;
 464         char name[8];
 465         /* ucode host flag 2 needed for pio mode, independent of band and fifo */
 466         u16 pio_mhf2 = 0;
 467         struct wlc_hw_info *wlc_hw = wlc->hw;
 468         uint unit = wlc_hw->unit;
 469         wlc_tunables_t *tune = wlc->pub->tunables;
 470         struct wiphy *wiphy = wlc->wiphy;
 471
 472         /* name and offsets for dma_attach */
 473         snprintf(name, sizeof(name), "wl%d", unit);
 474
 475         if (wlc_hw->di[0] == 0) {       /* Init FIFOs */
 476                 uint addrwidth;
 477                 int dma_attach_err = 0;
 478                 /* Find out the DMA addressing capability and let OS know
 479                  * All the channels within one DMA core have 'common-minimum' same
 480                  * capability
 481                  */
 482                 addrwidth =
 483                     dma_addrwidth(wlc_hw->sih, DMAREG(wlc_hw, DMA_TX, 0));
 484
 485                 if (!wl_alloc_dma_resources(wlc_hw->wlc->wl, addrwidth)) {
 486                         wiphy_err(wiphy, "wl%d: wlc_attach: alloc_dma_"
 487                                   "resources failed\n", unit);
 488                         return false;
 489                 }
 490
 491                 /*
 492                  * FIFO 0
 493                  * TX: TX_AC_BK_FIFO (TX AC Background data packets)
 494                  * RX: RX_FIFO (RX data packets)
 495                  */
 496                 wlc_hw->di[0] = dma_attach(name, wlc_hw->sih,
 497                                            (wme ? DMAREG(wlc_hw, DMA_TX, 0) :
 498                                             NULL), DMAREG(wlc_hw, DMA_RX, 0),
 499                                            (wme ? tune->ntxd : 0), tune->nrxd,
 500                                            tune->rxbufsz, -1, tune->nrxbufpost,
 501                                            WL_HWRXOFF, &brcm_msg_level);
 502                 dma_attach_err |= (NULL == wlc_hw->di[0]);
 503
 504                 /*
 505                  * FIFO 1
 506                  * TX: TX_AC_BE_FIFO (TX AC Best-Effort data packets)
 507                  *   (legacy) TX_DATA_FIFO (TX data packets)
 508                  * RX: UNUSED
 509                  */
 510                 wlc_hw->di[1] = dma_attach(name, wlc_hw->sih,
 511                                            DMAREG(wlc_hw, DMA_TX, 1), NULL,
 512                                            tune->ntxd, 0, 0, -1, 0, 0,
 513                                            &brcm_msg_level);
 514                 dma_attach_err |= (NULL == wlc_hw->di[1]);
 515
 516                 /*
 517                  * FIFO 2
 518                  * TX: TX_AC_VI_FIFO (TX AC Video data packets)
 519                  * RX: UNUSED
 520                  */
 521                 wlc_hw->di[2] = dma_attach(name, wlc_hw->sih,
 522                                            DMAREG(wlc_hw, DMA_TX, 2), NULL,
 523                                            tune->ntxd, 0, 0, -1, 0, 0,
 524                                            &brcm_msg_level);
 525                 dma_attach_err |= (NULL == wlc_hw->di[2]);
 526                 /*
 527                  * FIFO 3
 528                  * TX: TX_AC_VO_FIFO (TX AC Voice data packets)
 529                  *   (legacy) TX_CTL_FIFO (TX control & mgmt packets)
 530                  */
 531                 wlc_hw->di[3] = dma_attach(name, wlc_hw->sih,
 532                                            DMAREG(wlc_hw, DMA_TX, 3),
 533                                            NULL, tune->ntxd, 0, 0, -1,
 534                                            0, 0, &brcm_msg_level);
 535                 dma_attach_err |= (NULL == wlc_hw->di[3]);
 536 /* Cleaner to leave this as if with AP defined */
 537
 538                 if (dma_attach_err) {
 539                         wiphy_err(wiphy, "wl%d: wlc_attach: dma_attach failed"
 540                                   "\n", unit);
 541                         return false;
 542                 }
 543
 544                 /* get pointer to dma engine tx flow control variable */
 545                 for (i = 0; i < NFIFO; i++)
 546                         if (wlc_hw->di[i])
 547                                 wlc_hw->txavail[i] =
 548                                     (uint *) dma_getvar(wlc_hw->di[i],
 549                                                         "&txavail");
 550         }
 551
 552         /* initial ucode host flags */
 553         wlc_mhfdef(wlc, wlc_hw->band->mhfs, pio_mhf2);
 554
 555         return true;
 556 }
 557
 558 static void brcms_b_detach_dmapio(struct wlc_hw_info *wlc_hw)
 559 {
 560         uint j;
 561
 562         for (j = 0; j < NFIFO; j++) {
 563                 if (wlc_hw->di[j]) {
 564                         dma_detach(wlc_hw->di[j]);
 565                         wlc_hw->di[j] = NULL;
 566                 }
 567         }
 568 }
 569
 570 /* low level attach
 571  *    run backplane attach, init nvram
 572  *    run phy attach
 573  *    initialize software state for each core and band
 574  *    put the whole chip in reset(driver down state), no clock
 575  */
 576 int brcms_b_attach(struct wlc_info *wlc, u16 vendor, u16 device, uint unit,
 577                     bool piomode, void *regsva, uint bustype, void *btparam)
 578 {
 579         struct wlc_hw_info *wlc_hw;
 580         d11regs_t *regs;
 581         char *macaddr = NULL;
 582         char *vars;
 583         uint err = 0;
 584         uint j;
 585         bool wme = false;
 586         shared_phy_params_t sha_params;
 587         struct wiphy *wiphy = wlc->wiphy;
 588
 589         BCMMSG(wlc->wiphy, "wl%d: vendor 0x%x device 0x%x\n", unit, vendor,
 590                 device);
 591
 592         wme = true;
 593
 594         wlc_hw = wlc->hw;
 595         wlc_hw->wlc = wlc;
 596         wlc_hw->unit = unit;
 597         wlc_hw->band = wlc_hw->bandstate[0];
 598         wlc_hw->_piomode = piomode;
 599
 600         /* populate struct wlc_hw_info with default values  */
 601         brcms_b_info_init(wlc_hw);
 602
 603         /*
 604          * Do the hardware portion of the attach.
 605          * Also initialize software state that depends on the particular hardware
 606          * we are running.
 607          */
 608         wlc_hw->sih = ai_attach(regsva, bustype, btparam,
 609                                 &wlc_hw->vars, &wlc_hw->vars_size);
 610         if (wlc_hw->sih == NULL) {
 611                 wiphy_err(wiphy, "wl%d: brcms_b_attach: si_attach failed\n",
 612                           unit);
 613                 err = 11;
 614                 goto fail;
 615         }
 616         vars = wlc_hw->vars;
 617
 618         /*
 619          * Get vendid/devid nvram overwrites, which could be different
 620          * than those the BIOS recognizes for devices on PCMCIA_BUS,
 621          * SDIO_BUS, and SROMless devices on PCI_BUS.
 622          */
 623 #ifdef BCMBUSTYPE
 624         bustype = BCMBUSTYPE;
 625 #endif
 626         if (bustype != SI_BUS) {
 627                 char *var;
 628
 629                 var = getvar(vars, "vendid");
 630                 if (var) {
 631                         vendor = (u16) simple_strtoul(var, NULL, 0);
 632                         wiphy_err(wiphy, "Overriding vendor id = 0x%x\n",
 633                                   vendor);
 634                 }
 635                 var = getvar(vars, "devid");
 636                 if (var) {
 637                         u16 devid = (u16) simple_strtoul(var, NULL, 0);
 638                         if (devid != 0xffff) {
 639                                 device = devid;
 640                                 wiphy_err(wiphy, "Overriding device id = 0x%x"
 641                                           "\n", device);
 642                         }
 643                 }
 644
 645                 /* verify again the device is supported */
 646                 if (!wlc_chipmatch(vendor, device)) {
 647                         wiphy_err(wiphy, "wl%d: brcms_b_attach: Unsupported "
 648                                 "vendor/device (0x%x/0x%x)\n",
 649                                  unit, vendor, device);
 650                         err = 12;
 651                         goto fail;
 652                 }
 653         }
 654
 655         wlc_hw->vendorid = vendor;
 656         wlc_hw->deviceid = device;
 657
 658         /* set bar0 window to point at D11 core */
 659         wlc_hw->regs = (d11regs_t *) ai_setcore(wlc_hw->sih, D11_CORE_ID, 0);
 660         wlc_hw->corerev = ai_corerev(wlc_hw->sih);
 661
 662         regs = wlc_hw->regs;
 663
 664         wlc->regs = wlc_hw->regs;
 665
 666         /* validate chip, chiprev and corerev */
 667         if (!wlc_isgoodchip(wlc_hw)) {
 668                 err = 13;
 669                 goto fail;
 670         }
 671
 672         /* initialize power control registers */
 673         ai_clkctl_init(wlc_hw->sih);
 674
 675         /* request fastclock and force fastclock for the rest of attach
 676          * bring the d11 core out of reset.
 677          *   For PMU chips, the first wlc_clkctl_clk is no-op since core-clk is still false;
 678          *   But it will be called again inside wlc_corereset, after d11 is out of reset.
 679          */
 680         brcms_b_clkctl_clk(wlc_hw, CLK_FAST);
 681         brcms_b_corereset(wlc_hw, WLC_USE_COREFLAGS);
 682
 683         if (!brcms_b_validate_chip_access(wlc_hw)) {
 684                 wiphy_err(wiphy, "wl%d: brcms_b_attach: validate_chip_access "
 685                         "failed\n", unit);
 686                 err = 14;
 687                 goto fail;
 688         }
 689
 690         /* get the board rev, used just below */
 691         j = getintvar(vars, "boardrev");
 692         /* promote srom boardrev of 0xFF to 1 */
 693         if (j == BOARDREV_PROMOTABLE)
 694                 j = BOARDREV_PROMOTED;
 695         wlc_hw->boardrev = (u16) j;
 696         if (!wlc_validboardtype(wlc_hw)) {
 697                 wiphy_err(wiphy, "wl%d: brcms_b_attach: Unsupported Broadcom "
 698                         "board type (0x%x)" " or revision level (0x%x)\n",
 699                          unit, wlc_hw->sih->boardtype, wlc_hw->boardrev);
 700                 err = 15;
 701                 goto fail;
 702         }
 703         wlc_hw->sromrev = (u8) getintvar(vars, "sromrev");
 704         wlc_hw->boardflags = (u32) getintvar(vars, "boardflags");
 705         wlc_hw->boardflags2 = (u32) getintvar(vars, "boardflags2");
 706
 707         if (wlc_hw->boardflags & BFL_NOPLLDOWN)
 708                 brcms_b_pllreq(wlc_hw, true, WLC_PLLREQ_SHARED);
 709
 710         if ((wlc_hw->sih->bustype == PCI_BUS)
 711             && (ai_pci_war16165(wlc_hw->sih)))
 712                 wlc->war16165 = true;
 713
 714         /* check device id(srom, nvram etc.) to set bands */
 715         if (wlc_hw->deviceid == BCM43224_D11N_ID ||
 716             wlc_hw->deviceid == BCM43224_D11N_ID_VEN1) {
 717                 /* Dualband boards */
 718                 wlc_hw->_nbands = 2;
 719         } else
 720                 wlc_hw->_nbands = 1;
 721
 722         if ((wlc_hw->sih->chip == BCM43225_CHIP_ID))
 723                 wlc_hw->_nbands = 1;
 724
 725         /* BMAC_NOTE: remove init of pub values when wlc_attach() unconditionally does the
 726          * init of these values
 727          */
 728         wlc->vendorid = wlc_hw->vendorid;
 729         wlc->deviceid = wlc_hw->deviceid;
 730         wlc->pub->sih = wlc_hw->sih;
 731         wlc->pub->corerev = wlc_hw->corerev;
 732         wlc->pub->sromrev = wlc_hw->sromrev;
 733         wlc->pub->boardrev = wlc_hw->boardrev;
 734         wlc->pub->boardflags = wlc_hw->boardflags;
 735         wlc->pub->boardflags2 = wlc_hw->boardflags2;
 736         wlc->pub->_nbands = wlc_hw->_nbands;
 737
 738         wlc_hw->physhim = wlc_phy_shim_attach(wlc_hw, wlc->wl, wlc);
 739
 740         if (wlc_hw->physhim == NULL) {
 741                 wiphy_err(wiphy, "wl%d: brcms_b_attach: wlc_phy_shim_attach "
 742                         "failed\n", unit);
 743                 err = 25;
 744                 goto fail;
 745         }
 746
 747         /* pass all the parameters to wlc_phy_shared_attach in one struct */
 748         sha_params.sih = wlc_hw->sih;
 749         sha_params.physhim = wlc_hw->physhim;
 750         sha_params.unit = unit;
 751         sha_params.corerev = wlc_hw->corerev;
 752         sha_params.vars = vars;
 753         sha_params.vid = wlc_hw->vendorid;
 754         sha_params.did = wlc_hw->deviceid;
 755         sha_params.chip = wlc_hw->sih->chip;
 756         sha_params.chiprev = wlc_hw->sih->chiprev;
 757         sha_params.chippkg = wlc_hw->sih->chippkg;
 758         sha_params.sromrev = wlc_hw->sromrev;
 759         sha_params.boardtype = wlc_hw->sih->boardtype;
 760         sha_params.boardrev = wlc_hw->boardrev;
 761         sha_params.boardvendor = wlc_hw->sih->boardvendor;
 762         sha_params.boardflags = wlc_hw->boardflags;
 763         sha_params.boardflags2 = wlc_hw->boardflags2;
 764         sha_params.bustype = wlc_hw->sih->bustype;
 765         sha_params.buscorerev = wlc_hw->sih->buscorerev;
 766
 767         /* alloc and save pointer to shared phy state area */
 768         wlc_hw->phy_sh = wlc_phy_shared_attach(&sha_params);
 769         if (!wlc_hw->phy_sh) {
 770                 err = 16;
 771                 goto fail;
 772         }
 773
 774         /* initialize software state for each core and band */
 775         for (j = 0; j < NBANDS_HW(wlc_hw); j++) {
 776                 /*
 777                  * band0 is always 2.4Ghz
 778                  * band1, if present, is 5Ghz
 779                  */
 780
 781                 /* So if this is a single band 11a card, use band 1 */
 782                 if (IS_SINGLEBAND_5G(wlc_hw->deviceid))
 783                         j = BAND_5G_INDEX;
 784
 785                 wlc_setxband(wlc_hw, j);
 786
 787                 wlc_hw->band->bandunit = j;
 788                 wlc_hw->band->bandtype = j ? WLC_BAND_5G : WLC_BAND_2G;
 789                 wlc->band->bandunit = j;
 790                 wlc->band->bandtype = j ? WLC_BAND_5G : WLC_BAND_2G;
 791                 wlc->core->coreidx = ai_coreidx(wlc_hw->sih);
 792
 793                 wlc_hw->machwcap = R_REG(&regs->machwcap);
 794                 wlc_hw->machwcap_backup = wlc_hw->machwcap;
 795
 796                 /* init tx fifo size */
 797                 wlc_hw->xmtfifo_sz =
 798                     xmtfifo_sz[(wlc_hw->corerev - XMTFIFOTBL_STARTREV)];
 799
 800                 /* Get a phy for this band */
 801                 wlc_hw->band->pi = wlc_phy_attach(wlc_hw->phy_sh,
 802                         (void *)regs, brcms_b_bandtype(wlc_hw), vars,
 803                         wlc->wiphy);
 804                 if (wlc_hw->band->pi == NULL) {
 805                         wiphy_err(wiphy, "wl%d: brcms_b_attach: wlc_phy_"
 806                                   "attach failed\n", unit);
 807                         err = 17;
 808                         goto fail;
 809                 }
 810
 811                 wlc_phy_machwcap_set(wlc_hw->band->pi, wlc_hw->machwcap);
 812
 813                 wlc_phy_get_phyversion(wlc_hw->band->pi, &wlc_hw->band->phytype,
 814                                        &wlc_hw->band->phyrev,
 815                                        &wlc_hw->band->radioid,
 816                                        &wlc_hw->band->radiorev);
 817                 wlc_hw->band->abgphy_encore =
 818                     wlc_phy_get_encore(wlc_hw->band->pi);
 819                 wlc->band->abgphy_encore = wlc_phy_get_encore(wlc_hw->band->pi);
 820                 wlc_hw->band->core_flags =
 821                     wlc_phy_get_coreflags(wlc_hw->band->pi);
 822
 823                 /* verify good phy_type & supported phy revision */
 824                 if (WLCISNPHY(wlc_hw->band)) {
 825                         if (NCONF_HAS(wlc_hw->band->phyrev))
 826                                 goto good_phy;
 827                         else
 828                                 goto bad_phy;
 829                 } else if (WLCISLCNPHY(wlc_hw->band)) {
 830                         if (LCNCONF_HAS(wlc_hw->band->phyrev))
 831                                 goto good_phy;
 832                         else
 833                                 goto bad_phy;
 834                 } else {
 835  bad_phy:
 836                         wiphy_err(wiphy, "wl%d: brcms_b_attach: unsupported "
 837                                   "phy type/rev (%d/%d)\n", unit,
 838                                   wlc_hw->band->phytype, wlc_hw->band->phyrev);
 839                         err = 18;
 840                         goto fail;
 841                 }
 842
 843  good_phy:
 844                 /* BMAC_NOTE: wlc->band->pi should not be set below and should be done in the
 845                  * high level attach. However we can not make that change until all low level access
 846                  * is changed to wlc_hw->band->pi. Instead do the wlc->band->pi init below, keeping
 847                  * wlc_hw->band->pi as well for incremental update of low level fns, and cut over
 848                  * low only init when all fns updated.
 849                  */
 850                 wlc->band->pi = wlc_hw->band->pi;
 851                 wlc->band->phytype = wlc_hw->band->phytype;
 852                 wlc->band->phyrev = wlc_hw->band->phyrev;
 853                 wlc->band->radioid = wlc_hw->band->radioid;
 854                 wlc->band->radiorev = wlc_hw->band->radiorev;
 855
 856                 /* default contention windows size limits */
 857                 wlc_hw->band->CWmin = APHY_CWMIN;
 858                 wlc_hw->band->CWmax = PHY_CWMAX;
 859
 860                 if (!brcms_b_attach_dmapio(wlc, j, wme)) {
 861                         err = 19;
 862                         goto fail;
 863                 }
 864         }
 865
 866         /* disable core to match driver "down" state */
 867         wlc_coredisable(wlc_hw);
 868
 869         /* Match driver "down" state */
 870         if (wlc_hw->sih->bustype == PCI_BUS)
 871                 ai_pci_down(wlc_hw->sih);
 872
 873         /* register sb interrupt callback functions */
 874         ai_register_intr_callback(wlc_hw->sih, (void *)wlc_wlintrsoff,
 875                                   (void *)wlc_wlintrsrestore, NULL, wlc);
 876
 877         /* turn off pll and xtal to match driver "down" state */
 878         brcms_b_xtal(wlc_hw, OFF);
 879
 880         /* *********************************************************************
 881          * The hardware is in the DOWN state at this point. D11 core
 882          * or cores are in reset with clocks off, and the board PLLs
 883          * are off if possible.
 884          *
 885          * Beyond this point, wlc->sbclk == false and chip registers
 886          * should not be touched.
 887          *********************************************************************
 888          */
 889
 890         /* init etheraddr state variables */
 891         macaddr = wlc_get_macaddr(wlc_hw);
 892         if (macaddr == NULL) {
 893                 wiphy_err(wiphy, "wl%d: brcms_b_attach: macaddr not found\n",
 894                           unit);
 895                 err = 21;
 896                 goto fail;
 897         }
 898         brcmu_ether_atoe(macaddr, wlc_hw->etheraddr);
 899         if (is_broadcast_ether_addr(wlc_hw->etheraddr) ||
 900             is_zero_ether_addr(wlc_hw->etheraddr)) {
 901                 wiphy_err(wiphy, "wl%d: brcms_b_attach: bad macaddr %s\n",
 902                           unit, macaddr);
 903                 err = 22;
 904                 goto fail;
 905         }
 906
 907         BCMMSG(wlc->wiphy,
 908                  "deviceid 0x%x nbands %d board 0x%x macaddr: %s\n",
 909                  wlc_hw->deviceid, wlc_hw->_nbands,
 910                  wlc_hw->sih->boardtype, macaddr);
 911
 912         return err;
 913
 914  fail:
 915         wiphy_err(wiphy, "wl%d: brcms_b_attach: failed with err %d\n", unit,
 916                   err);
 917         return err;
 918 }
 919
 920 /*
 921  * Initialize wlc_info default values ...
 922  * may get overrides later in this function
 923  *  BMAC_NOTES, move low out and resolve the dangling ones
 924  */
 925 static void brcms_b_info_init(struct wlc_hw_info *wlc_hw)
 926 {
 927         struct wlc_info *wlc = wlc_hw->wlc;
 928
 929         /* set default sw macintmask value */
 930         wlc->defmacintmask = DEF_MACINTMASK;
 931
 932         /* various 802.11g modes */
 933         wlc_hw->shortslot = false;
 934
 935         wlc_hw->SFBL = RETRY_SHORT_FB;
 936         wlc_hw->LFBL = RETRY_LONG_FB;
 937
 938         /* default mac retry limits */
 939         wlc_hw->SRL = RETRY_SHORT_DEF;
 940         wlc_hw->LRL = RETRY_LONG_DEF;
 941         wlc_hw->chanspec = CH20MHZ_CHSPEC(1);
 942 }
 943
 944 /*
 945  * low level detach
 946  */
 947 int brcms_b_detach(struct wlc_info *wlc)
 948 {
 949         uint i;
 950         struct wlc_hwband *band;
 951         struct wlc_hw_info *wlc_hw = wlc->hw;
 952         int callbacks;
 953
 954         callbacks = 0;
 955
 956         if (wlc_hw->sih) {
 957                 /* detach interrupt sync mechanism since interrupt is disabled and per-port
 958                  * interrupt object may has been freed. this must be done before sb core switch
 959                  */
 960                 ai_deregister_intr_callback(wlc_hw->sih);
 961
 962                 if (wlc_hw->sih->bustype == PCI_BUS)
 963                         ai_pci_sleep(wlc_hw->sih);
 964         }
 965
 966         brcms_b_detach_dmapio(wlc_hw);
 967
 968         band = wlc_hw->band;
 969         for (i = 0; i < NBANDS_HW(wlc_hw); i++) {
 970                 if (band->pi) {
 971                         /* Detach this band's phy */
 972                         wlc_phy_detach(band->pi);
 973                         band->pi = NULL;
 974                 }
 975                 band = wlc_hw->bandstate[OTHERBANDUNIT(wlc)];
 976         }
 977
 978         /* Free shared phy state */
 979         wlc_phy_shared_detach(wlc_hw->phy_sh);
 980
 981         wlc_phy_shim_detach(wlc_hw->physhim);
 982
 983         /* free vars */
 984         kfree(wlc_hw->vars);
 985         wlc_hw->vars = NULL;
 986
 987         if (wlc_hw->sih) {
 988                 ai_detach(wlc_hw->sih);
 989                 wlc_hw->sih = NULL;
 990         }
 991
 992         return callbacks;
 993
 994 }
 995
 996 void brcms_b_reset(struct wlc_hw_info *wlc_hw)
 997 {
 998         BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
 999
1000         /* reset the core */
1001         if (!DEVICEREMOVED(wlc_hw->wlc))
1002                 brcms_b_corereset(wlc_hw, WLC_USE_COREFLAGS);
1003
1004         /* purge the dma rings */
1005         wlc_flushqueues(wlc_hw->wlc);
1006
1007         wlc_reset_bmac_done(wlc_hw->wlc);
1008 }
1009
1010 void
1011 brcms_b_init(struct wlc_hw_info *wlc_hw, chanspec_t chanspec,
1012                           bool mute) {
1013         u32 macintmask;
1014         bool fastclk;
1015         struct wlc_info *wlc = wlc_hw->wlc;
1016
1017         BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
1018
1019         /* request FAST clock if not on */
1020         fastclk = wlc_hw->forcefastclk;
1021         if (!fastclk)
1022                 brcms_b_clkctl_clk(wlc_hw, CLK_FAST);
1023
1024         /* disable interrupts */
1025         macintmask = brcms_intrsoff(wlc->wl);
1026
1027         /* set up the specified band and chanspec */
1028         wlc_setxband(wlc_hw, CHSPEC_WLCBANDUNIT(chanspec));
1029         wlc_phy_chanspec_radio_set(wlc_hw->band->pi, chanspec);
1030
1031         /* do one-time phy inits and calibration */
1032         wlc_phy_cal_init(wlc_hw->band->pi);
1033
1034         /* core-specific initialization */
1035         brcms_b_coreinit(wlc);
1036
1037         /* suspend the tx fifos and mute the phy for preism cac time */
1038         if (mute)
1039                 brcms_b_mute(wlc_hw, ON, PHY_MUTE_FOR_PREISM);
1040
1041         /* band-specific inits */
1042         brcms_b_bsinit(wlc, chanspec);
1043
1044         /* restore macintmask */
1045         brcms_intrsrestore(wlc->wl, macintmask);
1046
1047         /* seed wake_override with WLC_WAKE_OVERRIDE_MACSUSPEND since the mac is suspended
1048          * and wlc_enable_mac() will clear this override bit.
1049          */
1050         mboolset(wlc_hw->wake_override, WLC_WAKE_OVERRIDE_MACSUSPEND);
1051
1052         /*
1053          * initialize mac_suspend_depth to 1 to match ucode initial suspended state
1054          */
1055         wlc_hw->mac_suspend_depth = 1;
1056
1057         /* restore the clk */
1058         if (!fastclk)
1059                 brcms_b_clkctl_clk(wlc_hw, CLK_DYNAMIC);
1060 }
1061
1062 int brcms_b_up_prep(struct wlc_hw_info *wlc_hw)
1063 {
1064         uint coremask;
1065
1066         BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
1067
1068         /*
1069          * Enable pll and xtal, initialize the power control registers,
1070          * and force fastclock for the remainder of wlc_up().
1071          */
1072         brcms_b_xtal(wlc_hw, ON);
1073         ai_clkctl_init(wlc_hw->sih);
1074         brcms_b_clkctl_clk(wlc_hw, CLK_FAST);
1075
1076         /*
1077          * Configure pci/pcmcia here instead of in wlc_attach()
1078          * to allow mfg hotswap:  down, hotswap (chip power cycle), up.
1079          */
1080         coremask = (1 << wlc_hw->wlc->core->coreidx);
1081
1082         if (wlc_hw->sih->bustype == PCI_BUS)
1083                 ai_pci_setup(wlc_hw->sih, coremask);
1084
1085         /*
1086          * Need to read the hwradio status here to cover the case where the system
1087          * is loaded with the hw radio disabled. We do not want to bring the driver up in this case.
1088          */
1089         if (brcms_b_radio_read_hwdisabled(wlc_hw)) {
1090                 /* put SB PCI in down state again */
1091                 if (wlc_hw->sih->bustype == PCI_BUS)
1092                         ai_pci_down(wlc_hw->sih);
1093                 brcms_b_xtal(wlc_hw, OFF);
1094                 return -ENOMEDIUM;
1095         }
1096
1097         if (wlc_hw->sih->bustype == PCI_BUS)
1098                 ai_pci_up(wlc_hw->sih);
1099
1100         /* reset the d11 core */
1101         brcms_b_corereset(wlc_hw, WLC_USE_COREFLAGS);
1102
1103         return 0;
1104 }
1105
1106 int brcms_b_up_finish(struct wlc_hw_info *wlc_hw)
1107 {
1108         BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
1109
1110         wlc_hw->up = true;
1111         wlc_phy_hw_state_upd(wlc_hw->band->pi, true);
1112
1113         /* FULLY enable dynamic power control and d11 core interrupt */
1114         brcms_b_clkctl_clk(wlc_hw, CLK_DYNAMIC);
1115         brcms_intrson(wlc_hw->wlc->wl);
1116         return 0;
1117 }
1118
1119 int brcms_b_bmac_down_prep(struct wlc_hw_info *wlc_hw)
1120 {
1121         bool dev_gone;
1122         uint callbacks = 0;
1123
1124         BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
1125
1126         if (!wlc_hw->up)
1127                 return callbacks;
1128
1129         dev_gone = DEVICEREMOVED(wlc_hw->wlc);
1130
1131         /* disable interrupts */
1132         if (dev_gone)
1133                 wlc_hw->wlc->macintmask = 0;
1134         else {
1135                 /* now disable interrupts */
1136                 brcms_intrsoff(wlc_hw->wlc->wl);
1137
1138                 /* ensure we're running on the pll clock again */
1139                 brcms_b_clkctl_clk(wlc_hw, CLK_FAST);
1140         }
1141         /* down phy at the last of this stage */
1142         callbacks += wlc_phy_down(wlc_hw->band->pi);
1143
1144         return callbacks;
1145 }
1146
1147 int brcms_b_down_finish(struct wlc_hw_info *wlc_hw)
1148 {
1149         uint callbacks = 0;
1150         bool dev_gone;
1151
1152         BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
1153
1154         if (!wlc_hw->up)
1155                 return callbacks;
1156
1157         wlc_hw->up = false;
1158         wlc_phy_hw_state_upd(wlc_hw->band->pi, false);
1159
1160         dev_gone = DEVICEREMOVED(wlc_hw->wlc);
1161
1162         if (dev_gone) {
1163                 wlc_hw->sbclk = false;
1164                 wlc_hw->clk = false;
1165                 wlc_phy_hw_clk_state_upd(wlc_hw->band->pi, false);
1166
1167                 /* reclaim any posted packets */
1168                 wlc_flushqueues(wlc_hw->wlc);
1169         } else {
1170
1171                 /* Reset and disable the core */
1172                 if (ai_iscoreup(wlc_hw->sih)) {
1173                         if (R_REG(&wlc_hw->regs->maccontrol) &
1174                             MCTL_EN_MAC)
1175                                 wlc_suspend_mac_and_wait(wlc_hw->wlc);
1176                         callbacks += brcms_reset(wlc_hw->wlc->wl);
1177                         wlc_coredisable(wlc_hw);
1178                 }
1179
1180                 /* turn off primary xtal and pll */
1181                 if (!wlc_hw->noreset) {
1182                         if (wlc_hw->sih->bustype == PCI_BUS)
1183                                 ai_pci_down(wlc_hw->sih);
1184                         brcms_b_xtal(wlc_hw, OFF);
1185                 }
1186         }
1187
1188         return callbacks;
1189 }
1190
1191 void brcms_b_wait_for_wake(struct wlc_hw_info *wlc_hw)
1192 {
1193         /* delay before first read of ucode state */
1194         udelay(40);
1195
1196         /* wait until ucode is no longer asleep */
1197         SPINWAIT((brcms_b_read_shm(wlc_hw, M_UCODE_DBGST) ==
1198                   DBGST_ASLEEP), wlc_hw->wlc->fastpwrup_dly);
1199 }
1200
1201 void brcms_b_hw_etheraddr(struct wlc_hw_info *wlc_hw, u8 *ea)
1202 {
1203         memcpy(ea, wlc_hw->etheraddr, ETH_ALEN);
1204 }
1205
1206 static int brcms_b_bandtype(struct wlc_hw_info *wlc_hw)
1207 {
1208         return wlc_hw->band->bandtype;
1209 }
1210
1211 /* control chip clock to save power, enable dynamic clock or force fast clock */
1212 static void brcms_b_clkctl_clk(struct wlc_hw_info *wlc_hw, uint mode)
1213 {
1214         if (PMUCTL_ENAB(wlc_hw->sih)) {
1215                 /* new chips with PMU, CCS_FORCEHT will distribute the HT clock on backplane,
1216                  *  but mac core will still run on ALP(not HT) when it enters powersave mode,
1217                  *      which means the FCA bit may not be set.
1218                  *      should wakeup mac if driver wants it to run on HT.
1219                  */
1220
1221                 if (wlc_hw->clk) {
1222                         if (mode == CLK_FAST) {
1223                                 OR_REG(&wlc_hw->regs->clk_ctl_st,
1224                                        CCS_FORCEHT);
1225
1226                                 udelay(64);
1227
1228                                 SPINWAIT(((R_REG
1229                                            (&wlc_hw->regs->
1230                                             clk_ctl_st) & CCS_HTAVAIL) == 0),
1231                                          PMU_MAX_TRANSITION_DLY);
1232                                 WARN_ON(!(R_REG
1233                                           (&wlc_hw->regs->
1234                                            clk_ctl_st) & CCS_HTAVAIL));
1235                         } else {
1236                                 if ((wlc_hw->sih->pmurev == 0) &&
1237                                     (R_REG
1238                                      (&wlc_hw->regs->
1239                                       clk_ctl_st) & (CCS_FORCEHT | CCS_HTAREQ)))
1240                                         SPINWAIT(((R_REG
1241                                                    (&wlc_hw->regs->
1242                                                     clk_ctl_st) & CCS_HTAVAIL)
1243                                                   == 0),
1244                                                  PMU_MAX_TRANSITION_DLY);
1245                                 AND_REG(&wlc_hw->regs->clk_ctl_st,
1246                                         ~CCS_FORCEHT);
1247                         }
1248                 }
1249                 wlc_hw->forcefastclk = (mode == CLK_FAST);
1250         } else {
1251
1252                 /* old chips w/o PMU, force HT through cc,
1253                  * then use FCA to verify mac is running fast clock
1254                  */
1255
1256                 wlc_hw->forcefastclk = ai_clkctl_cc(wlc_hw->sih, mode);
1257
1258                 /* check fast clock is available (if core is not in reset) */
1259                 if (wlc_hw->forcefastclk && wlc_hw->clk)
1260                         WARN_ON(!(ai_core_sflags(wlc_hw->sih, 0, 0) &
1261                                   SISF_FCLKA));
1262
1263                 /* keep the ucode wake bit on if forcefastclk is on
1264                  * since we do not want ucode to put us back to slow clock
1265                  * when it dozes for PM mode.
1266                  * Code below matches the wake override bit with current forcefastclk state
1267                  * Only setting bit in wake_override instead of waking ucode immediately
1268                  * since old code (wlc.c 1.4499) had this behavior. Older code set
1269                  * wlc->forcefastclk but only had the wake happen if the wakup_ucode work
1270                  * (protected by an up check) was executed just below.
1271                  */
1272                 if (wlc_hw->forcefastclk)
1273                         mboolset(wlc_hw->wake_override,
1274                                  WLC_WAKE_OVERRIDE_FORCEFAST);
1275                 else
1276                         mboolclr(wlc_hw->wake_override,
1277                                  WLC_WAKE_OVERRIDE_FORCEFAST);
1278         }
1279 }
1280
1281 /* set initial host flags value */
1282 static void
1283 wlc_mhfdef(struct wlc_info *wlc, u16 *mhfs, u16 mhf2_init)
1284 {
1285         struct wlc_hw_info *wlc_hw = wlc->hw;
1286
1287         memset(mhfs, 0, MHFMAX * sizeof(u16));
1288
1289         mhfs[MHF2] |= mhf2_init;
1290
1291         /* prohibit use of slowclock on multifunction boards */
1292         if (wlc_hw->boardflags & BFL_NOPLLDOWN)
1293                 mhfs[MHF1] |= MHF1_FORCEFASTCLK;
1294
1295         if (WLCISNPHY(wlc_hw->band) && NREV_LT(wlc_hw->band->phyrev, 2)) {
1296                 mhfs[MHF2] |= MHF2_NPHY40MHZ_WAR;
1297                 mhfs[MHF1] |= MHF1_IQSWAP_WAR;
1298         }
1299 }
1300
1301 /* set or clear ucode host flag bits
1302  * it has an optimization for no-change write
1303  * it only writes through shared memory when the core has clock;
1304  * pre-CLK changes should use wlc_write_mhf to get around the optimization
1305  *
1306  *
1307  * bands values are: WLC_BAND_AUTO <--- Current band only
1308  *                   WLC_BAND_5G   <--- 5G band only
1309  *                   WLC_BAND_2G   <--- 2G band only
1310  *                   WLC_BAND_ALL  <--- All bands
1311  */
1312 void
1313 brcms_b_mhf(struct wlc_hw_info *wlc_hw, u8 idx, u16 mask, u16 val,
1314              int bands)
1315 {
1316         u16 save;
1317         u16 addr[MHFMAX] = {
1318                 M_HOST_FLAGS1, M_HOST_FLAGS2, M_HOST_FLAGS3, M_HOST_FLAGS4,
1319                 M_HOST_FLAGS5
1320         };
1321         struct wlc_hwband *band;
1322
1323         if ((val & ~mask) || idx >= MHFMAX)
1324                 return; /* error condition */
1325
1326         switch (bands) {
1327                 /* Current band only or all bands,
1328                  * then set the band to current band
1329                  */
1330         case WLC_BAND_AUTO:
1331         case WLC_BAND_ALL:
1332                 band = wlc_hw->band;
1333                 break;
1334         case WLC_BAND_5G:
1335                 band = wlc_hw->bandstate[BAND_5G_INDEX];
1336                 break;
1337         case WLC_BAND_2G:
1338                 band = wlc_hw->bandstate[BAND_2G_INDEX];
1339                 break;
1340         default:
1341                 band = NULL;    /* error condition */
1342         }
1343
1344         if (band) {
1345                 save = band->mhfs[idx];
1346                 band->mhfs[idx] = (band->mhfs[idx] & ~mask) | val;
1347
1348                 /* optimization: only write through if changed, and
1349                  * changed band is the current band
1350                  */
1351                 if (wlc_hw->clk && (band->mhfs[idx] != save)
1352                     && (band == wlc_hw->band))
1353                         brcms_b_write_shm(wlc_hw, addr[idx],
1354                                            (u16) band->mhfs[idx]);
1355         }
1356
1357         if (bands == WLC_BAND_ALL) {
1358                 wlc_hw->bandstate[0]->mhfs[idx] =
1359                     (wlc_hw->bandstate[0]->mhfs[idx] & ~mask) | val;
1360                 wlc_hw->bandstate[1]->mhfs[idx] =
1361                     (wlc_hw->bandstate[1]->mhfs[idx] & ~mask) | val;
1362         }
1363 }
1364
1365 u16 brcms_b_mhf_get(struct wlc_hw_info *wlc_hw, u8 idx, int bands)
1366 {
1367         struct wlc_hwband *band;
1368
1369         if (idx >= MHFMAX)
1370                 return 0; /* error condition */
1371         switch (bands) {
1372         case WLC_BAND_AUTO:
1373                 band = wlc_hw->band;
1374                 break;
1375         case WLC_BAND_5G:
1376                 band = wlc_hw->bandstate[BAND_5G_INDEX];
1377                 break;
1378         case WLC_BAND_2G:
1379                 band = wlc_hw->bandstate[BAND_2G_INDEX];
1380                 break;
1381         default:
1382                 band = NULL;            /* error condition */
1383         }
1384
1385         if (!band)
1386                 return 0;
1387
1388         return band->mhfs[idx];
1389 }
1390
1391 static void wlc_write_mhf(struct wlc_hw_info *wlc_hw, u16 *mhfs)
1392 {
1393         u8 idx;
1394         u16 addr[] = {
1395                 M_HOST_FLAGS1, M_HOST_FLAGS2, M_HOST_FLAGS3, M_HOST_FLAGS4,
1396                 M_HOST_FLAGS5
1397         };
1398
1399         for (idx = 0; idx < MHFMAX; idx++) {
1400                 brcms_b_write_shm(wlc_hw, addr[idx], mhfs[idx]);
1401         }
1402 }
1403
1404 /* set the maccontrol register to desired reset state and
1405  * initialize the sw cache of the register
1406  */
1407 static void wlc_mctrl_reset(struct wlc_hw_info *wlc_hw)
1408 {
1409         /* IHR accesses are always enabled, PSM disabled, HPS off and WAKE on */
1410         wlc_hw->maccontrol = 0;
1411         wlc_hw->suspended_fifos = 0;
1412         wlc_hw->wake_override = 0;
1413         wlc_hw->mute_override = 0;
1414         brcms_b_mctrl(wlc_hw, ~0, MCTL_IHR_EN | MCTL_WAKE);
1415 }
1416
1417 /* set or clear maccontrol bits */
1418 void brcms_b_mctrl(struct wlc_hw_info *wlc_hw, u32 mask, u32 val)
1419 {
1420         u32 maccontrol;
1421         u32 new_maccontrol;
1422
1423         if (val & ~mask)
1424                 return; /* error condition */
1425         maccontrol = wlc_hw->maccontrol;
1426         new_maccontrol = (maccontrol & ~mask) | val;
1427
1428         /* if the new maccontrol value is the same as the old, nothing to do */
1429         if (new_maccontrol == maccontrol)
1430                 return;
1431
1432         /* something changed, cache the new value */
1433         wlc_hw->maccontrol = new_maccontrol;
1434
1435         /* write the new values with overrides applied */
1436         wlc_mctrl_write(wlc_hw);
1437 }
1438
1439 /* write the software state of maccontrol and overrides to the maccontrol register */
1440 static void wlc_mctrl_write(struct wlc_hw_info *wlc_hw)
1441 {
1442         u32 maccontrol = wlc_hw->maccontrol;
1443
1444         /* OR in the wake bit if overridden */
1445         if (wlc_hw->wake_override)
1446                 maccontrol |= MCTL_WAKE;
1447
1448         /* set AP and INFRA bits for mute if needed */
1449         if (wlc_hw->mute_override) {
1450                 maccontrol &= ~(MCTL_AP);
1451                 maccontrol |= MCTL_INFRA;
1452         }
1453
1454         W_REG(&wlc_hw->regs->maccontrol, maccontrol);
1455 }
1456
1457 void wlc_ucode_wake_override_set(struct wlc_hw_info *wlc_hw, u32 override_bit)
1458 {
1459         if (wlc_hw->wake_override || (wlc_hw->maccontrol & MCTL_WAKE)) {
1460                 mboolset(wlc_hw->wake_override, override_bit);
1461                 return;
1462         }
1463
1464         mboolset(wlc_hw->wake_override, override_bit);
1465
1466         wlc_mctrl_write(wlc_hw);
1467         brcms_b_wait_for_wake(wlc_hw);
1468
1469         return;
1470 }
1471
1472 void wlc_ucode_wake_override_clear(struct wlc_hw_info *wlc_hw, u32 override_bit)
1473 {
1474         mboolclr(wlc_hw->wake_override, override_bit);
1475
1476         if (wlc_hw->wake_override || (wlc_hw->maccontrol & MCTL_WAKE))
1477                 return;
1478
1479         wlc_mctrl_write(wlc_hw);
1480
1481         return;
1482 }
1483
1484 /* When driver needs ucode to stop beaconing, it has to make sure that
1485  * MCTL_AP is clear and MCTL_INFRA is set
1486  * Mode           MCTL_AP        MCTL_INFRA
1487  * AP                1              1
1488  * STA               0              1 <--- This will ensure no beacons
1489  * IBSS              0              0
1490  */
1491 static void wlc_ucode_mute_override_set(struct wlc_hw_info *wlc_hw)
1492 {
1493         wlc_hw->mute_override = 1;
1494
1495         /* if maccontrol already has AP == 0 and INFRA == 1 without this
1496          * override, then there is no change to write
1497          */
1498         if ((wlc_hw->maccontrol & (MCTL_AP | MCTL_INFRA)) == MCTL_INFRA)
1499                 return;
1500
1501         wlc_mctrl_write(wlc_hw);
1502
1503         return;
1504 }
1505
1506 /* Clear the override on AP and INFRA bits */
1507 static void wlc_ucode_mute_override_clear(struct wlc_hw_info *wlc_hw)
1508 {
1509         if (wlc_hw->mute_override == 0)
1510                 return;
1511
1512         wlc_hw->mute_override = 0;
1513
1514         /* if maccontrol already has AP == 0 and INFRA == 1 without this
1515          * override, then there is no change to write
1516          */
1517         if ((wlc_hw->maccontrol & (MCTL_AP | MCTL_INFRA)) == MCTL_INFRA)
1518                 return;
1519
1520         wlc_mctrl_write(wlc_hw);
1521 }
1522
1523 /*
1524  * Write a MAC address to the given match reg offset in the RXE match engine.
1525  */
1526 void
1527 brcms_b_set_addrmatch(struct wlc_hw_info *wlc_hw, int match_reg_offset,
1528                        const u8 *addr)
1529 {
1530         d11regs_t *regs;
1531         u16 mac_l;
1532         u16 mac_m;
1533         u16 mac_h;
1534
1535         BCMMSG(wlc_hw->wlc->wiphy, "wl%d: brcms_b_set_addrmatch\n",
1536                  wlc_hw->unit);
1537
1538         regs = wlc_hw->regs;
1539         mac_l = addr[0] | (addr[1] << 8);
1540         mac_m = addr[2] | (addr[3] << 8);
1541         mac_h = addr[4] | (addr[5] << 8);
1542
1543         /* enter the MAC addr into the RXE match registers */
1544         W_REG(&regs->rcm_ctl, RCM_INC_DATA | match_reg_offset);
1545         W_REG(&regs->rcm_mat_data, mac_l);
1546         W_REG(&regs->rcm_mat_data, mac_m);
1547         W_REG(&regs->rcm_mat_data, mac_h);
1548
1549 }
1550
1551 void
1552 brcms_b_write_template_ram(struct wlc_hw_info *wlc_hw, int offset, int len,
1553                             void *buf)
1554 {
1555         d11regs_t *regs;
1556         u32 word;
1557         bool be_bit;
1558         BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
1559
1560         regs = wlc_hw->regs;
1561         W_REG(&regs->tplatewrptr, offset);
1562
1563         /* if MCTL_BIGEND bit set in mac control register,
1564          * the chip swaps data in fifo, as well as data in
1565          * template ram
1566          */
1567         be_bit = (R_REG(&regs->maccontrol) & MCTL_BIGEND) != 0;
1568
1569         while (len > 0) {
1570                 memcpy(&word, buf, sizeof(u32));
1571
1572                 if (be_bit)
1573                         word = cpu_to_be32(word);
1574                 else
1575                         word = cpu_to_le32(word);
1576
1577                 W_REG(&regs->tplatewrdata, word);
1578
1579                 buf = (u8 *) buf + sizeof(u32);
1580                 len -= sizeof(u32);
1581         }
1582 }
1583
1584 void brcms_b_set_cwmin(struct wlc_hw_info *wlc_hw, u16 newmin)
1585 {
1586         wlc_hw->band->CWmin = newmin;
1587
1588         W_REG(&wlc_hw->regs->objaddr, OBJADDR_SCR_SEL | S_DOT11_CWMIN);
1589         (void)R_REG(&wlc_hw->regs->objaddr);
1590         W_REG(&wlc_hw->regs->objdata, newmin);
1591 }
1592
1593 void brcms_b_set_cwmax(struct wlc_hw_info *wlc_hw, u16 newmax)
1594 {
1595         wlc_hw->band->CWmax = newmax;
1596
1597         W_REG(&wlc_hw->regs->objaddr, OBJADDR_SCR_SEL | S_DOT11_CWMAX);
1598         (void)R_REG(&wlc_hw->regs->objaddr);
1599         W_REG(&wlc_hw->regs->objdata, newmax);
1600 }
1601
1602 void brcms_b_bw_set(struct wlc_hw_info *wlc_hw, u16 bw)
1603 {
1604         bool fastclk;
1605
1606         /* request FAST clock if not on */
1607         fastclk = wlc_hw->forcefastclk;
1608         if (!fastclk)
1609                 brcms_b_clkctl_clk(wlc_hw, CLK_FAST);
1610
1611         wlc_phy_bw_state_set(wlc_hw->band->pi, bw);
1612
1613         brcms_b_phy_reset(wlc_hw);
1614         wlc_phy_init(wlc_hw->band->pi, wlc_phy_chanspec_get(wlc_hw->band->pi));
1615
1616         /* restore the clk */
1617         if (!fastclk)
1618                 brcms_b_clkctl_clk(wlc_hw, CLK_DYNAMIC);
1619 }
1620
1621 static void
1622 wlc_write_hw_bcntemplate0(struct wlc_hw_info *wlc_hw, void *bcn, int len)
1623 {
1624         d11regs_t *regs = wlc_hw->regs;
1625
1626         brcms_b_write_template_ram(wlc_hw, T_BCN0_TPL_BASE, (len + 3) & ~3,
1627                                     bcn);
1628         /* write beacon length to SCR */
1629         brcms_b_write_shm(wlc_hw, M_BCN0_FRM_BYTESZ, (u16) len);
1630         /* mark beacon0 valid */
1631         OR_REG(&regs->maccommand, MCMD_BCN0VLD);
1632 }
1633
1634 static void
1635 wlc_write_hw_bcntemplate1(struct wlc_hw_info *wlc_hw, void *bcn, int len)
1636 {
1637         d11regs_t *regs = wlc_hw->regs;
1638
1639         brcms_b_write_template_ram(wlc_hw, T_BCN1_TPL_BASE, (len + 3) & ~3,
1640                                     bcn);
1641         /* write beacon length to SCR */
1642         brcms_b_write_shm(wlc_hw, M_BCN1_FRM_BYTESZ, (u16) len);
1643         /* mark beacon1 valid */
1644         OR_REG(&regs->maccommand, MCMD_BCN1VLD);
1645 }
1646
1647 /* mac is assumed to be suspended at this point */
1648 void
1649 brcms_b_write_hw_bcntemplates(struct wlc_hw_info *wlc_hw, void *bcn, int len,
1650                                bool both)
1651 {
1652         d11regs_t *regs = wlc_hw->regs;
1653
1654         if (both) {
1655                 wlc_write_hw_bcntemplate0(wlc_hw, bcn, len);
1656                 wlc_write_hw_bcntemplate1(wlc_hw, bcn, len);
1657         } else {
1658                 /* bcn 0 */
1659                 if (!(R_REG(&regs->maccommand) & MCMD_BCN0VLD))
1660                         wlc_write_hw_bcntemplate0(wlc_hw, bcn, len);
1661                 /* bcn 1 */
1662                 else if (!
1663                          (R_REG(&regs->maccommand) & MCMD_BCN1VLD))
1664                         wlc_write_hw_bcntemplate1(wlc_hw, bcn, len);
1665         }
1666 }
1667
1668 static void WLBANDINITFN(brcms_b_upd_synthpu) (struct wlc_hw_info *wlc_hw)
1669 {
1670         u16 v;
1671         struct wlc_info *wlc = wlc_hw->wlc;
1672         /* update SYNTHPU_DLY */
1673
1674         if (WLCISLCNPHY(wlc->band)) {
1675                 v = SYNTHPU_DLY_LPPHY_US;
1676         } else if (WLCISNPHY(wlc->band) && (NREV_GE(wlc->band->phyrev, 3))) {
1677                 v = SYNTHPU_DLY_NPHY_US;
1678         } else {
1679                 v = SYNTHPU_DLY_BPHY_US;
1680         }
1681
1682         brcms_b_write_shm(wlc_hw, M_SYNTHPU_DLY, v);
1683 }
1684
1685 /* band-specific init */
1686 static void
1687 WLBANDINITFN(brcms_b_bsinit) (struct wlc_info *wlc, chanspec_t chanspec)
1688 {
1689         struct wlc_hw_info *wlc_hw = wlc->hw;
1690
1691         BCMMSG(wlc->wiphy, "wl%d: bandunit %d\n", wlc_hw->unit,
1692                 wlc_hw->band->bandunit);
1693
1694         wlc_ucode_bsinit(wlc_hw);
1695
1696         wlc_phy_init(wlc_hw->band->pi, chanspec);
1697
1698         wlc_ucode_txant_set(wlc_hw);
1699
1700         /* cwmin is band-specific, update hardware with value for current band */
1701         brcms_b_set_cwmin(wlc_hw, wlc_hw->band->CWmin);
1702         brcms_b_set_cwmax(wlc_hw, wlc_hw->band->CWmax);
1703
1704         brcms_b_update_slot_timing(wlc_hw,
1705                                     BAND_5G(wlc_hw->band->
1706                                             bandtype) ? true : wlc_hw->
1707                                     shortslot);
1708
1709         /* write phytype and phyvers */
1710         brcms_b_write_shm(wlc_hw, M_PHYTYPE, (u16) wlc_hw->band->phytype);
1711         brcms_b_write_shm(wlc_hw, M_PHYVER, (u16) wlc_hw->band->phyrev);
1712
1713         /* initialize the txphyctl1 rate table since shmem is shared between bands */
1714         wlc_upd_ofdm_pctl1_table(wlc_hw);
1715
1716         brcms_b_upd_synthpu(wlc_hw);
1717 }
1718
1719 static void brcms_b_core_phy_clk(struct wlc_hw_info *wlc_hw, bool clk)
1720 {
1721         BCMMSG(wlc_hw->wlc->wiphy, "wl%d: clk %d\n", wlc_hw->unit, clk);
1722
1723         wlc_hw->phyclk = clk;
1724
1725         if (OFF == clk) {       /* clear gmode bit, put phy into reset */
1726
1727                 ai_core_cflags(wlc_hw->sih, (SICF_PRST | SICF_FGC | SICF_GMODE),
1728                                (SICF_PRST | SICF_FGC));
1729                 udelay(1);
1730                 ai_core_cflags(wlc_hw->sih, (SICF_PRST | SICF_FGC), SICF_PRST);
1731                 udelay(1);
1732
1733         } else {                /* take phy out of reset */
1734
1735                 ai_core_cflags(wlc_hw->sih, (SICF_PRST | SICF_FGC), SICF_FGC);
1736                 udelay(1);
1737                 ai_core_cflags(wlc_hw->sih, (SICF_FGC), 0);
1738                 udelay(1);
1739
1740         }
1741 }
1742
1743 /* Perform a soft reset of the PHY PLL */
1744 void brcms_b_core_phypll_reset(struct wlc_hw_info *wlc_hw)
1745 {
1746         BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
1747
1748         ai_corereg(wlc_hw->sih, SI_CC_IDX,
1749                    offsetof(chipcregs_t, chipcontrol_addr), ~0, 0);
1750         udelay(1);
1751         ai_corereg(wlc_hw->sih, SI_CC_IDX,
1752                    offsetof(chipcregs_t, chipcontrol_data), 0x4, 0);
1753         udelay(1);
1754         ai_corereg(wlc_hw->sih, SI_CC_IDX,
1755                    offsetof(chipcregs_t, chipcontrol_data), 0x4, 4);
1756         udelay(1);
1757         ai_corereg(wlc_hw->sih, SI_CC_IDX,
1758                    offsetof(chipcregs_t, chipcontrol_data), 0x4, 0);
1759         udelay(1);
1760 }
1761
1762 /* light way to turn on phy clock without reset for NPHY only
1763  *  refer to brcms_b_core_phy_clk for full version
1764  */
1765 void brcms_b_phyclk_fgc(struct wlc_hw_info *wlc_hw, bool clk)
1766 {
1767         /* support(necessary for NPHY and HYPHY) only */
1768         if (!WLCISNPHY(wlc_hw->band))
1769                 return;
1770
1771         if (ON == clk)
1772                 ai_core_cflags(wlc_hw->sih, SICF_FGC, SICF_FGC);
1773         else
1774                 ai_core_cflags(wlc_hw->sih, SICF_FGC, 0);
1775
1776 }
1777
1778 void brcms_b_macphyclk_set(struct wlc_hw_info *wlc_hw, bool clk)
1779 {
1780         if (ON == clk)
1781                 ai_core_cflags(wlc_hw->sih, SICF_MPCLKE, SICF_MPCLKE);
1782         else
1783                 ai_core_cflags(wlc_hw->sih, SICF_MPCLKE, 0);
1784 }
1785
1786 void brcms_b_phy_reset(struct wlc_hw_info *wlc_hw)
1787 {
1788         wlc_phy_t *pih = wlc_hw->band->pi;
1789         u32 phy_bw_clkbits;
1790         bool phy_in_reset = false;
1791
1792         BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
1793
1794         if (pih == NULL)
1795                 return;
1796
1797         phy_bw_clkbits = wlc_phy_clk_bwbits(wlc_hw->band->pi);
1798
1799         /* Specific reset sequence required for NPHY rev 3 and 4 */
1800         if (WLCISNPHY(wlc_hw->band) && NREV_GE(wlc_hw->band->phyrev, 3) &&
1801             NREV_LE(wlc_hw->band->phyrev, 4)) {
1802                 /* Set the PHY bandwidth */
1803                 ai_core_cflags(wlc_hw->sih, SICF_BWMASK, phy_bw_clkbits);
1804
1805                 udelay(1);
1806
1807                 /* Perform a soft reset of the PHY PLL */
1808                 brcms_b_core_phypll_reset(wlc_hw);
1809
1810                 /* reset the PHY */
1811                 ai_core_cflags(wlc_hw->sih, (SICF_PRST | SICF_PCLKE),
1812                                (SICF_PRST | SICF_PCLKE));
1813                 phy_in_reset = true;
1814         } else {
1815
1816                 ai_core_cflags(wlc_hw->sih,
1817                                (SICF_PRST | SICF_PCLKE | SICF_BWMASK),
1818                                (SICF_PRST | SICF_PCLKE | phy_bw_clkbits));
1819         }
1820
1821         udelay(2);
1822         brcms_b_core_phy_clk(wlc_hw, ON);
1823
1824         if (pih)
1825                 wlc_phy_anacore(pih, ON);
1826 }
1827
1828 /* switch to and initialize new band */
1829 static void
1830 WLBANDINITFN(brcms_b_setband) (struct wlc_hw_info *wlc_hw, uint bandunit,
1831                                 chanspec_t chanspec) {
1832         struct wlc_info *wlc = wlc_hw->wlc;
1833         u32 macintmask;
1834
1835         /* Enable the d11 core before accessing it */
1836         if (!ai_iscoreup(wlc_hw->sih)) {
1837                 ai_core_reset(wlc_hw->sih, 0, 0);
1838                 wlc_mctrl_reset(wlc_hw);
1839         }
1840
1841         macintmask = wlc_setband_inact(wlc, bandunit);
1842
1843         if (!wlc_hw->up)
1844                 return;
1845
1846         brcms_b_core_phy_clk(wlc_hw, ON);
1847
1848         /* band-specific initializations */
1849         brcms_b_bsinit(wlc, chanspec);
1850
1851         /*
1852          * If there are any pending software interrupt bits,
1853          * then replace these with a harmless nonzero value
1854          * so wlc_dpc() will re-enable interrupts when done.
1855          */
1856         if (wlc->macintstatus)
1857                 wlc->macintstatus = MI_DMAINT;
1858
1859         /* restore macintmask */
1860         brcms_intrsrestore(wlc->wl, macintmask);
1861
1862         /* ucode should still be suspended.. */
1863         WARN_ON((R_REG(&wlc_hw->regs->maccontrol) & MCTL_EN_MAC) != 0);
1864 }
1865
1866 /* low-level band switch utility routine */
1867 void WLBANDINITFN(wlc_setxband) (struct wlc_hw_info *wlc_hw, uint bandunit)
1868 {
1869         BCMMSG(wlc_hw->wlc->wiphy, "wl%d: bandunit %d\n", wlc_hw->unit,
1870                 bandunit);
1871
1872         wlc_hw->band = wlc_hw->bandstate[bandunit];
1873
1874         /* BMAC_NOTE: until we eliminate need for wlc->band refs in low level code */
1875         wlc_hw->wlc->band = wlc_hw->wlc->bandstate[bandunit];
1876
1877         /* set gmode core flag */
1878         if (wlc_hw->sbclk && !wlc_hw->noreset) {
1879                 ai_core_cflags(wlc_hw->sih, SICF_GMODE,
1880                                ((bandunit == 0) ? SICF_GMODE : 0));
1881         }
1882 }
1883
1884 static bool wlc_isgoodchip(struct wlc_hw_info *wlc_hw)
1885 {
1886
1887         /* reject unsupported corerev */
1888         if (!VALID_COREREV(wlc_hw->corerev)) {
1889                 wiphy_err(wlc_hw->wlc->wiphy, "unsupported core rev %d\n",
1890                           wlc_hw->corerev);
1891                 return false;
1892         }
1893
1894         return true;
1895 }
1896
1897 static bool wlc_validboardtype(struct wlc_hw_info *wlc_hw)
1898 {
1899         bool goodboard = true;
1900         uint boardrev = wlc_hw->boardrev;
1901
1902         if (boardrev == 0)
1903                 goodboard = false;
1904         else if (boardrev > 0xff) {
1905                 uint brt = (boardrev & 0xf000) >> 12;
1906                 uint b0 = (boardrev & 0xf00) >> 8;
1907                 uint b1 = (boardrev & 0xf0) >> 4;
1908                 uint b2 = boardrev & 0xf;
1909
1910                 if ((brt > 2) || (brt == 0) || (b0 > 9) || (b0 == 0) || (b1 > 9)
1911                     || (b2 > 9))
1912                         goodboard = false;
1913         }
1914
1915         if (wlc_hw->sih->boardvendor != PCI_VENDOR_ID_BROADCOM)
1916                 return goodboard;
1917
1918         return goodboard;
1919 }
1920
1921 static char *wlc_get_macaddr(struct wlc_hw_info *wlc_hw)
1922 {
1923         const char *varname = "macaddr";
1924         char *macaddr;
1925
1926         /* If macaddr exists, use it (Sromrev4, CIS, ...). */
1927         macaddr = getvar(wlc_hw->vars, varname);
1928         if (macaddr != NULL)
1929                 return macaddr;
1930
1931         if (NBANDS_HW(wlc_hw) > 1)
1932                 varname = "et1macaddr";
1933         else
1934                 varname = "il0macaddr";
1935
1936         macaddr = getvar(wlc_hw->vars, varname);
1937         if (macaddr == NULL) {
1938                 wiphy_err(wlc_hw->wlc->wiphy, "wl%d: wlc_get_macaddr: macaddr "
1939                           "getvar(%s) not found\n", wlc_hw->unit, varname);
1940         }
1941
1942         return macaddr;
1943 }
1944
1945 /*
1946  * Return true if radio is disabled, otherwise false.
1947  * hw radio disable signal is an external pin, users activate it asynchronously
1948  * this function could be called when driver is down and w/o clock
1949  * it operates on different registers depending on corerev and boardflag.
1950  */
1951 bool brcms_b_radio_read_hwdisabled(struct wlc_hw_info *wlc_hw)
1952 {
1953         bool v, clk, xtal;
1954         u32 resetbits = 0, flags = 0;
1955
1956         xtal = wlc_hw->sbclk;
1957         if (!xtal)
1958                 brcms_b_xtal(wlc_hw, ON);
1959
1960         /* may need to take core out of reset first */
1961         clk = wlc_hw->clk;
1962         if (!clk) {
1963                 /*
1964                  * mac no longer enables phyclk automatically when driver
1965                  * accesses phyreg throughput mac. This can be skipped since
1966                  * only mac reg is accessed below
1967                  */
1968                 flags |= SICF_PCLKE;
1969
1970                 /* AI chip doesn't restore bar0win2 on hibernation/resume, need sw fixup */
1971                 if ((wlc_hw->sih->chip == BCM43224_CHIP_ID) ||
1972                     (wlc_hw->sih->chip == BCM43225_CHIP_ID) ||
1973                     (wlc_hw->sih->chip == BCM43421_CHIP_ID))
1974                         wlc_hw->regs =
1975                             (d11regs_t *) ai_setcore(wlc_hw->sih, D11_CORE_ID,
1976                                                      0);
1977                 ai_core_reset(wlc_hw->sih, flags, resetbits);
1978                 wlc_mctrl_reset(wlc_hw);
1979         }
1980
1981         v = ((R_REG(&wlc_hw->regs->phydebug) & PDBG_RFD) != 0);
1982
1983         /* put core back into reset */
1984         if (!clk)
1985                 ai_core_disable(wlc_hw->sih, 0);
1986
1987         if (!xtal)
1988                 brcms_b_xtal(wlc_hw, OFF);
1989
1990         return v;
1991 }
1992
1993 /* Initialize just the hardware when coming out of POR or S3/S5 system states */
1994 void brcms_b_hw_up(struct wlc_hw_info *wlc_hw)
1995 {
1996         if (wlc_hw->wlc->pub->hw_up)
1997                 return;
1998
1999         BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
2000
2001         /*
2002          * Enable pll and xtal, initialize the power control registers,
2003          * and force fastclock for the remainder of wlc_up().
2004          */
2005         brcms_b_xtal(wlc_hw, ON);
2006         ai_clkctl_init(wlc_hw->sih);
2007         brcms_b_clkctl_clk(wlc_hw, CLK_FAST);
2008
2009         if (wlc_hw->sih->bustype == PCI_BUS) {
2010                 ai_pci_fixcfg(wlc_hw->sih);
2011
2012                 /* AI chip doesn't restore bar0win2 on hibernation/resume, need sw fixup */
2013                 if ((wlc_hw->sih->chip == BCM43224_CHIP_ID) ||
2014                     (wlc_hw->sih->chip == BCM43225_CHIP_ID) ||
2015                     (wlc_hw->sih->chip == BCM43421_CHIP_ID))
2016                         wlc_hw->regs =
2017                             (d11regs_t *) ai_setcore(wlc_hw->sih, D11_CORE_ID,
2018                                                      0);
2019         }
2020
2021         /* Inform phy that a POR reset has occurred so it does a complete phy init */
2022         wlc_phy_por_inform(wlc_hw->band->pi);
2023
2024         wlc_hw->ucode_loaded = false;
2025         wlc_hw->wlc->pub->hw_up = true;
2026
2027         if ((wlc_hw->boardflags & BFL_FEM)
2028             && (wlc_hw->sih->chip == BCM4313_CHIP_ID)) {
2029                 if (!
2030                     (wlc_hw->boardrev >= 0x1250
2031                      && (wlc_hw->boardflags & BFL_FEM_BT)))
2032                         ai_epa_4313war(wlc_hw->sih);
2033         }
2034 }
2035
2036 static bool wlc_dma_rxreset(struct wlc_hw_info *wlc_hw, uint fifo)
2037 {
2038         struct dma_pub *di = wlc_hw->di[fifo];
2039         return dma_rxreset(di);
2040 }
2041
2042 /* d11 core reset
2043  *   ensure fask clock during reset
2044  *   reset dma
2045  *   reset d11(out of reset)
2046  *   reset phy(out of reset)
2047  *   clear software macintstatus for fresh new start
2048  * one testing hack wlc_hw->noreset will bypass the d11/phy reset
2049  */
2050 void brcms_b_corereset(struct wlc_hw_info *wlc_hw, u32 flags)
2051 {
2052         d11regs_t *regs;
2053         uint i;
2054         bool fastclk;
2055         u32 resetbits = 0;
2056
2057         if (flags == WLC_USE_COREFLAGS)
2058                 flags = (wlc_hw->band->pi ? wlc_hw->band->core_flags : 0);
2059
2060         BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
2061
2062         regs = wlc_hw->regs;
2063
2064         /* request FAST clock if not on  */
2065         fastclk = wlc_hw->forcefastclk;
2066         if (!fastclk)
2067                 brcms_b_clkctl_clk(wlc_hw, CLK_FAST);
2068
2069         /* reset the dma engines except first time thru */
2070         if (ai_iscoreup(wlc_hw->sih)) {
2071                 for (i = 0; i < NFIFO; i++)
2072                         if ((wlc_hw->di[i]) && (!dma_txreset(wlc_hw->di[i]))) {
2073                                 wiphy_err(wlc_hw->wlc->wiphy, "wl%d: %s: "
2074                                           "dma_txreset[%d]: cannot stop dma\n",
2075                                            wlc_hw->unit, __func__, i);
2076                         }
2077
2078                 if ((wlc_hw->di[RX_FIFO])
2079                     && (!wlc_dma_rxreset(wlc_hw, RX_FIFO))) {
2080                         wiphy_err(wlc_hw->wlc->wiphy, "wl%d: %s: dma_rxreset"
2081                                   "[%d]: cannot stop dma\n",
2082                                   wlc_hw->unit, __func__, RX_FIFO);
2083                 }
2084         }
2085         /* if noreset, just stop the psm and return */
2086         if (wlc_hw->noreset) {
2087                 wlc_hw->wlc->macintstatus = 0;  /* skip wl_dpc after down */
2088                 brcms_b_mctrl(wlc_hw, MCTL_PSM_RUN | MCTL_EN_MAC, 0);
2089                 return;
2090         }
2091
2092         /*
2093          * mac no longer enables phyclk automatically when driver accesses
2094          * phyreg throughput mac, AND phy_reset is skipped at early stage when
2095          * band->pi is invalid. need to enable PHY CLK
2096          */
2097         flags |= SICF_PCLKE;
2098
2099         /* reset the core
2100          * In chips with PMU, the fastclk request goes through d11 core reg 0x1e0, which
2101          *  is cleared by the core_reset. have to re-request it.
2102          *  This adds some delay and we can optimize it by also requesting fastclk through
2103          *  chipcommon during this period if necessary. But that has to work coordinate
2104          *  with other driver like mips/arm since they may touch chipcommon as well.
2105          */
2106         wlc_hw->clk = false;
2107         ai_core_reset(wlc_hw->sih, flags, resetbits);
2108         wlc_hw->clk = true;
2109         if (wlc_hw->band && wlc_hw->band->pi)
2110                 wlc_phy_hw_clk_state_upd(wlc_hw->band->pi, true);
2111
2112         wlc_mctrl_reset(wlc_hw);
2113
2114         if (PMUCTL_ENAB(wlc_hw->sih))
2115                 brcms_b_clkctl_clk(wlc_hw, CLK_FAST);
2116
2117         brcms_b_phy_reset(wlc_hw);
2118
2119         /* turn on PHY_PLL */
2120         brcms_b_core_phypll_ctl(wlc_hw, true);
2121
2122         /* clear sw intstatus */
2123         wlc_hw->wlc->macintstatus = 0;
2124
2125         /* restore the clk setting */
2126         if (!fastclk)
2127                 brcms_b_clkctl_clk(wlc_hw, CLK_DYNAMIC);
2128 }
2129
2130 /* txfifo sizes needs to be modified(increased) since the newer cores
2131  * have more memory.
2132  */
2133 static void brcms_b_corerev_fifofixup(struct wlc_hw_info *wlc_hw)
2134 {
2135         d11regs_t *regs = wlc_hw->regs;
2136         u16 fifo_nu;
2137         u16 txfifo_startblk = TXFIFO_START_BLK, txfifo_endblk;
2138         u16 txfifo_def, txfifo_def1;
2139         u16 txfifo_cmd;
2140
2141         /* tx fifos start at TXFIFO_START_BLK from the Base address */
2142         txfifo_startblk = TXFIFO_START_BLK;
2143
2144         /* sequence of operations:  reset fifo, set fifo size, reset fifo */
2145         for (fifo_nu = 0; fifo_nu < NFIFO; fifo_nu++) {
2146
2147                 txfifo_endblk = txfifo_startblk + wlc_hw->xmtfifo_sz[fifo_nu];
2148                 txfifo_def = (txfifo_startblk & 0xff) |
2149                     (((txfifo_endblk - 1) & 0xff) << TXFIFO_FIFOTOP_SHIFT);
2150                 txfifo_def1 = ((txfifo_startblk >> 8) & 0x1) |
2151                     ((((txfifo_endblk -
2152                         1) >> 8) & 0x1) << TXFIFO_FIFOTOP_SHIFT);
2153                 txfifo_cmd =
2154                     TXFIFOCMD_RESET_MASK | (fifo_nu << TXFIFOCMD_FIFOSEL_SHIFT);
2155
2156                 W_REG(&regs->xmtfifocmd, txfifo_cmd);
2157                 W_REG(&regs->xmtfifodef, txfifo_def);
2158                 W_REG(&regs->xmtfifodef1, txfifo_def1);
2159
2160                 W_REG(&regs->xmtfifocmd, txfifo_cmd);
2161
2162                 txfifo_startblk += wlc_hw->xmtfifo_sz[fifo_nu];
2163         }
2164         /*
2165          * need to propagate to shm location to be in sync since ucode/hw won't
2166          * do this
2167          */
2168         brcms_b_write_shm(wlc_hw, M_FIFOSIZE0,
2169                            wlc_hw->xmtfifo_sz[TX_AC_BE_FIFO]);
2170         brcms_b_write_shm(wlc_hw, M_FIFOSIZE1,
2171                            wlc_hw->xmtfifo_sz[TX_AC_VI_FIFO]);
2172         brcms_b_write_shm(wlc_hw, M_FIFOSIZE2,
2173                            ((wlc_hw->xmtfifo_sz[TX_AC_VO_FIFO] << 8) | wlc_hw->
2174                             xmtfifo_sz[TX_AC_BK_FIFO]));
2175         brcms_b_write_shm(wlc_hw, M_FIFOSIZE3,
2176                            ((wlc_hw->xmtfifo_sz[TX_ATIM_FIFO] << 8) | wlc_hw->
2177                             xmtfifo_sz[TX_BCMC_FIFO]));
2178 }
2179
2180 /* d11 core init
2181  *   reset PSM
2182  *   download ucode/PCM
2183  *   let ucode run to suspended
2184  *   download ucode inits
2185  *   config other core registers
2186  *   init dma
2187  */
2188 static void brcms_b_coreinit(struct wlc_info *wlc)
2189 {
2190         struct wlc_hw_info *wlc_hw = wlc->hw;
2191         d11regs_t *regs;
2192         u32 sflags;
2193         uint bcnint_us;
2194         uint i = 0;
2195         bool fifosz_fixup = false;
2196         int err = 0;
2197         u16 buf[NFIFO];
2198         struct wiphy *wiphy = wlc->wiphy;
2199
2200         regs = wlc_hw->regs;
2201
2202         BCMMSG(wlc->wiphy, "wl%d\n", wlc_hw->unit);
2203
2204         /* reset PSM */
2205         brcms_b_mctrl(wlc_hw, ~0, (MCTL_IHR_EN | MCTL_PSM_JMP_0 | MCTL_WAKE));
2206
2207         wlc_ucode_download(wlc_hw);
2208         /*
2209          * FIFOSZ fixup. driver wants to controls the fifo allocation.
2210          */
2211         fifosz_fixup = true;
2212
2213         /* let the PSM run to the suspended state, set mode to BSS STA */
2214         W_REG(&regs->macintstatus, -1);
2215         brcms_b_mctrl(wlc_hw, ~0,
2216                        (MCTL_IHR_EN | MCTL_INFRA | MCTL_PSM_RUN | MCTL_WAKE));
2217
2218         /* wait for ucode to self-suspend after auto-init */
2219         SPINWAIT(((R_REG(&regs->macintstatus) & MI_MACSSPNDD) == 0),
2220                  1000 * 1000);
2221         if ((R_REG(&regs->macintstatus) & MI_MACSSPNDD) == 0)
2222                 wiphy_err(wiphy, "wl%d: wlc_coreinit: ucode did not self-"
2223                           "suspend!\n", wlc_hw->unit);
2224
2225         wlc_gpio_init(wlc);
2226
2227         sflags = ai_core_sflags(wlc_hw->sih, 0, 0);
2228
2229         if (D11REV_IS(wlc_hw->corerev, 23)) {
2230                 if (WLCISNPHY(wlc_hw->band))
2231                         wlc_write_inits(wlc_hw, d11n0initvals16);
2232                 else
2233                         wiphy_err(wiphy, "%s: wl%d: unsupported phy in corerev"
2234                                   " %d\n", __func__, wlc_hw->unit,
2235                                   wlc_hw->corerev);
2236         } else if (D11REV_IS(wlc_hw->corerev, 24)) {
2237                 if (WLCISLCNPHY(wlc_hw->band)) {
2238                         wlc_write_inits(wlc_hw, d11lcn0initvals24);
2239                 } else {
2240                         wiphy_err(wiphy, "%s: wl%d: unsupported phy in corerev"
2241                                   " %d\n", __func__, wlc_hw->unit,
2242                                   wlc_hw->corerev);
2243                 }
2244         } else {
2245                 wiphy_err(wiphy, "%s: wl%d: unsupported corerev %d\n",
2246                           __func__, wlc_hw->unit, wlc_hw->corerev);
2247         }
2248
2249         /* For old ucode, txfifo sizes needs to be modified(increased) */
2250         if (fifosz_fixup == true) {
2251                 brcms_b_corerev_fifofixup(wlc_hw);
2252         }
2253
2254         /* check txfifo allocations match between ucode and driver */
2255         buf[TX_AC_BE_FIFO] = brcms_b_read_shm(wlc_hw, M_FIFOSIZE0);
2256         if (buf[TX_AC_BE_FIFO] != wlc_hw->xmtfifo_sz[TX_AC_BE_FIFO]) {
2257                 i = TX_AC_BE_FIFO;
2258                 err = -1;
2259         }
2260         buf[TX_AC_VI_FIFO] = brcms_b_read_shm(wlc_hw, M_FIFOSIZE1);
2261         if (buf[TX_AC_VI_FIFO] != wlc_hw->xmtfifo_sz[TX_AC_VI_FIFO]) {
2262                 i = TX_AC_VI_FIFO;
2263                 err = -1;
2264         }
2265         buf[TX_AC_BK_FIFO] = brcms_b_read_shm(wlc_hw, M_FIFOSIZE2);
2266         buf[TX_AC_VO_FIFO] = (buf[TX_AC_BK_FIFO] >> 8) & 0xff;
2267         buf[TX_AC_BK_FIFO] &= 0xff;
2268         if (buf[TX_AC_BK_FIFO] != wlc_hw->xmtfifo_sz[TX_AC_BK_FIFO]) {
2269                 i = TX_AC_BK_FIFO;
2270                 err = -1;
2271         }
2272         if (buf[TX_AC_VO_FIFO] != wlc_hw->xmtfifo_sz[TX_AC_VO_FIFO]) {
2273                 i = TX_AC_VO_FIFO;
2274                 err = -1;
2275         }
2276         buf[TX_BCMC_FIFO] = brcms_b_read_shm(wlc_hw, M_FIFOSIZE3);
2277         buf[TX_ATIM_FIFO] = (buf[TX_BCMC_FIFO] >> 8) & 0xff;
2278         buf[TX_BCMC_FIFO] &= 0xff;
2279         if (buf[TX_BCMC_FIFO] != wlc_hw->xmtfifo_sz[TX_BCMC_FIFO]) {
2280                 i = TX_BCMC_FIFO;
2281                 err = -1;
2282         }
2283         if (buf[TX_ATIM_FIFO] != wlc_hw->xmtfifo_sz[TX_ATIM_FIFO]) {
2284                 i = TX_ATIM_FIFO;
2285                 err = -1;
2286         }
2287         if (err != 0) {
2288                 wiphy_err(wiphy, "wlc_coreinit: txfifo mismatch: ucode size %d"
2289                           " driver size %d index %d\n", buf[i],
2290                           wlc_hw->xmtfifo_sz[i], i);
2291         }
2292
2293         /* make sure we can still talk to the mac */
2294         WARN_ON(R_REG(&regs->maccontrol) == 0xffffffff);
2295
2296         /* band-specific inits done by wlc_bsinit() */
2297
2298         /* Set up frame burst size and antenna swap threshold init values */
2299         brcms_b_write_shm(wlc_hw, M_MBURST_SIZE, MAXTXFRAMEBURST);
2300         brcms_b_write_shm(wlc_hw, M_MAX_ANTCNT, ANTCNT);
2301
2302         /* enable one rx interrupt per received frame */
2303         W_REG(&regs->intrcvlazy[0], (1 << IRL_FC_SHIFT));
2304
2305         /* set the station mode (BSS STA) */
2306         brcms_b_mctrl(wlc_hw,
2307                        (MCTL_INFRA | MCTL_DISCARD_PMQ | MCTL_AP),
2308                        (MCTL_INFRA | MCTL_DISCARD_PMQ));
2309
2310         /* set up Beacon interval */
2311         bcnint_us = 0x8000 << 10;
2312         W_REG(&regs->tsf_cfprep, (bcnint_us << CFPREP_CBI_SHIFT));
2313         W_REG(&regs->tsf_cfpstart, bcnint_us);
2314         W_REG(&regs->macintstatus, MI_GP1);
2315
2316         /* write interrupt mask */
2317         W_REG(&regs->intctrlregs[RX_FIFO].intmask, DEF_RXINTMASK);
2318
2319         /* allow the MAC to control the PHY clock (dynamic on/off) */
2320         brcms_b_macphyclk_set(wlc_hw, ON);
2321
2322         /* program dynamic clock control fast powerup delay register */
2323         wlc->fastpwrup_dly = ai_clkctl_fast_pwrup_delay(wlc_hw->sih);
2324         W_REG(&regs->scc_fastpwrup_dly, wlc->fastpwrup_dly);
2325
2326         /* tell the ucode the corerev */
2327         brcms_b_write_shm(wlc_hw, M_MACHW_VER, (u16) wlc_hw->corerev);
2328
2329         /* tell the ucode MAC capabilities */
2330         brcms_b_write_shm(wlc_hw, M_MACHW_CAP_L,
2331                            (u16) (wlc_hw->machwcap & 0xffff));
2332         brcms_b_write_shm(wlc_hw, M_MACHW_CAP_H,
2333                            (u16) ((wlc_hw->
2334                                       machwcap >> 16) & 0xffff));
2335
2336         /* write retry limits to SCR, this done after PSM init */
2337         W_REG(&regs->objaddr, OBJADDR_SCR_SEL | S_DOT11_SRC_LMT);
2338         (void)R_REG(&regs->objaddr);
2339         W_REG(&regs->objdata, wlc_hw->SRL);
2340         W_REG(&regs->objaddr, OBJADDR_SCR_SEL | S_DOT11_LRC_LMT);
2341         (void)R_REG(&regs->objaddr);
2342         W_REG(&regs->objdata, wlc_hw->LRL);
2343
2344         /* write rate fallback retry limits */
2345         brcms_b_write_shm(wlc_hw, M_SFRMTXCNTFBRTHSD, wlc_hw->SFBL);
2346         brcms_b_write_shm(wlc_hw, M_LFRMTXCNTFBRTHSD, wlc_hw->LFBL);
2347
2348         AND_REG(&regs->ifs_ctl, 0x0FFF);
2349         W_REG(&regs->ifs_aifsn, EDCF_AIFSN_MIN);
2350
2351         /* dma initializations */
2352         wlc->txpend16165war = 0;
2353
2354         /* init the tx dma engines */
2355         for (i = 0; i < NFIFO; i++) {
2356                 if (wlc_hw->di[i])
2357                         dma_txinit(wlc_hw->di[i]);
2358         }
2359
2360         /* init the rx dma engine(s) and post receive buffers */
2361         dma_rxinit(wlc_hw->di[RX_FIFO]);
2362         dma_rxfill(wlc_hw->di[RX_FIFO]);
2363 }
2364
2365 /* This function is used for changing the tsf frac register
2366  * If spur avoidance mode is off, the mac freq will be 80/120/160Mhz
2367  * If spur avoidance mode is on1, the mac freq will be 82/123/164Mhz
2368  * If spur avoidance mode is on2, the mac freq will be 84/126/168Mhz
2369  * HTPHY Formula is 2^26/freq(MHz) e.g.
2370  * For spuron2 - 126MHz -> 2^26/126 = 532610.0
2371  *  - 532610 = 0x82082 => tsf_clk_frac_h = 0x8, tsf_clk_frac_l = 0x2082
2372  * For spuron: 123MHz -> 2^26/123    = 545600.5
2373  *  - 545601 = 0x85341 => tsf_clk_frac_h = 0x8, tsf_clk_frac_l = 0x5341
2374  * For spur off: 120MHz -> 2^26/120    = 559240.5
2375  *  - 559241 = 0x88889 => tsf_clk_frac_h = 0x8, tsf_clk_frac_l = 0x8889
2376  */
2377
2378 void brcms_b_switch_macfreq(struct wlc_hw_info *wlc_hw, u8 spurmode)
2379 {
2380         d11regs_t *regs;
2381         regs = wlc_hw->regs;
2382
2383         if ((wlc_hw->sih->chip == BCM43224_CHIP_ID) ||
2384             (wlc_hw->sih->chip == BCM43225_CHIP_ID)) {
2385                 if (spurmode == WL_SPURAVOID_ON2) {     /* 126Mhz */
2386                         W_REG(&regs->tsf_clk_frac_l, 0x2082);
2387                         W_REG(&regs->tsf_clk_frac_h, 0x8);
2388                 } else if (spurmode == WL_SPURAVOID_ON1) {      /* 123Mhz */
2389                         W_REG(&regs->tsf_clk_frac_l, 0x5341);
2390                         W_REG(&regs->tsf_clk_frac_h, 0x8);
2391                 } else {        /* 120Mhz */
2392                         W_REG(&regs->tsf_clk_frac_l, 0x8889);
2393                         W_REG(&regs->tsf_clk_frac_h, 0x8);
2394                 }
2395         } else if (WLCISLCNPHY(wlc_hw->band)) {
2396                 if (spurmode == WL_SPURAVOID_ON1) {     /* 82Mhz */
2397                         W_REG(&regs->tsf_clk_frac_l, 0x7CE0);
2398                         W_REG(&regs->tsf_clk_frac_h, 0xC);
2399                 } else {        /* 80Mhz */
2400                         W_REG(&regs->tsf_clk_frac_l, 0xCCCD);
2401                         W_REG(&regs->tsf_clk_frac_h, 0xC);
2402                 }
2403         }
2404 }
2405
2406 /* Initialize GPIOs that are controlled by D11 core */
2407 static void wlc_gpio_init(struct wlc_info *wlc)
2408 {
2409         struct wlc_hw_info *wlc_hw = wlc->hw;
2410         d11regs_t *regs;
2411         u32 gc, gm;
2412
2413         regs = wlc_hw->regs;
2414
2415         /* use GPIO select 0 to get all gpio signals from the gpio out reg */
2416         brcms_b_mctrl(wlc_hw, MCTL_GPOUT_SEL_MASK, 0);
2417
2418         /*
2419          * Common GPIO setup:
2420          *      G0 = LED 0 = WLAN Activity
2421          *      G1 = LED 1 = WLAN 2.4 GHz Radio State
2422          *      G2 = LED 2 = WLAN 5 GHz Radio State
2423          *      G4 = radio disable input (HI enabled, LO disabled)
2424          */
2425
2426         gc = gm = 0;
2427
2428         /* Allocate GPIOs for mimo antenna diversity feature */
2429         if (wlc_hw->antsel_type == ANTSEL_2x3) {
2430                 /* Enable antenna diversity, use 2x3 mode */
2431                 brcms_b_mhf(wlc_hw, MHF3, MHF3_ANTSEL_EN,
2432                              MHF3_ANTSEL_EN, WLC_BAND_ALL);
2433                 brcms_b_mhf(wlc_hw, MHF3, MHF3_ANTSEL_MODE,
2434                              MHF3_ANTSEL_MODE, WLC_BAND_ALL);
2435
2436                 /* init superswitch control */
2437                 wlc_phy_antsel_init(wlc_hw->band->pi, false);
2438
2439         } else if (wlc_hw->antsel_type == ANTSEL_2x4) {
2440                 gm |= gc |= (BOARD_GPIO_12 | BOARD_GPIO_13);
2441                 /*
2442                  * The board itself is powered by these GPIOs
2443                  * (when not sending pattern) so set them high
2444                  */
2445                 OR_REG(&regs->psm_gpio_oe,
2446                        (BOARD_GPIO_12 | BOARD_GPIO_13));
2447                 OR_REG(&regs->psm_gpio_out,
2448                        (BOARD_GPIO_12 | BOARD_GPIO_13));
2449
2450                 /* Enable antenna diversity, use 2x4 mode */
2451                 brcms_b_mhf(wlc_hw, MHF3, MHF3_ANTSEL_EN,
2452                              MHF3_ANTSEL_EN, WLC_BAND_ALL);
2453                 brcms_b_mhf(wlc_hw, MHF3, MHF3_ANTSEL_MODE, 0,
2454                              WLC_BAND_ALL);
2455
2456                 /* Configure the desired clock to be 4Mhz */
2457                 brcms_b_write_shm(wlc_hw, M_ANTSEL_CLKDIV,
2458                                    ANTSEL_CLKDIV_4MHZ);
2459         }
2460
2461         /* gpio 9 controls the PA.  ucode is responsible for wiggling out and oe */
2462         if (wlc_hw->boardflags & BFL_PACTRL)
2463                 gm |= gc |= BOARD_GPIO_PACTRL;
2464
2465         /* apply to gpiocontrol register */
2466         ai_gpiocontrol(wlc_hw->sih, gm, gc, GPIO_DRV_PRIORITY);
2467 }
2468
2469 static void wlc_ucode_download(struct wlc_hw_info *wlc_hw)
2470 {
2471         struct wlc_info *wlc;
2472         wlc = wlc_hw->wlc;
2473
2474         if (wlc_hw->ucode_loaded)
2475                 return;
2476
2477         if (D11REV_IS(wlc_hw->corerev, 23)) {
2478                 if (WLCISNPHY(wlc_hw->band)) {
2479                         wlc_ucode_write(wlc_hw, bcm43xx_16_mimo,
2480                                         bcm43xx_16_mimosz);
2481                         wlc_hw->ucode_loaded = true;
2482                 } else
2483                         wiphy_err(wlc->wiphy, "%s: wl%d: unsupported phy in "
2484                                   "corerev %d\n",
2485                                   __func__, wlc_hw->unit, wlc_hw->corerev);
2486         } else if (D11REV_IS(wlc_hw->corerev, 24)) {
2487                 if (WLCISLCNPHY(wlc_hw->band)) {
2488                         wlc_ucode_write(wlc_hw, bcm43xx_24_lcn,
2489                                         bcm43xx_24_lcnsz);
2490                         wlc_hw->ucode_loaded = true;
2491                 } else {
2492                         wiphy_err(wlc->wiphy, "%s: wl%d: unsupported phy in "
2493                                   "corerev %d\n",
2494                                   __func__, wlc_hw->unit, wlc_hw->corerev);
2495                 }
2496         }
2497 }
2498
2499 static void wlc_ucode_write(struct wlc_hw_info *wlc_hw, const u32 ucode[],
2500                               const uint nbytes) {
2501         d11regs_t *regs = wlc_hw->regs;
2502         uint i;
2503         uint count;
2504
2505         BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
2506
2507         count = (nbytes / sizeof(u32));
2508
2509         W_REG(&regs->objaddr, (OBJADDR_AUTO_INC | OBJADDR_UCM_SEL));
2510         (void)R_REG(&regs->objaddr);
2511         for (i = 0; i < count; i++)
2512                 W_REG(&regs->objdata, ucode[i]);
2513 }
2514
2515 static void wlc_write_inits(struct wlc_hw_info *wlc_hw,
2516                             const struct d11init *inits)
2517 {
2518         int i;
2519         volatile u8 *base;
2520
2521         BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
2522
2523         base = (volatile u8 *)wlc_hw->regs;
2524
2525         for (i = 0; inits[i].addr != 0xffff; i++) {
2526                 if (inits[i].size == 2)
2527                         W_REG((u16 *)(base + inits[i].addr),
2528                               inits[i].value);
2529                 else if (inits[i].size == 4)
2530                         W_REG((u32 *)(base + inits[i].addr),
2531                               inits[i].value);
2532         }
2533 }
2534
2535 static void wlc_ucode_txant_set(struct wlc_hw_info *wlc_hw)
2536 {
2537         u16 phyctl;
2538         u16 phytxant = wlc_hw->bmac_phytxant;
2539         u16 mask = PHY_TXC_ANT_MASK;
2540
2541         /* set the Probe Response frame phy control word */
2542         phyctl = brcms_b_read_shm(wlc_hw, M_CTXPRS_BLK + C_CTX_PCTLWD_POS);
2543         phyctl = (phyctl & ~mask) | phytxant;
2544         brcms_b_write_shm(wlc_hw, M_CTXPRS_BLK + C_CTX_PCTLWD_POS, phyctl);
2545
2546         /* set the Response (ACK/CTS) frame phy control word */
2547         phyctl = brcms_b_read_shm(wlc_hw, M_RSP_PCTLWD);
2548         phyctl = (phyctl & ~mask) | phytxant;
2549         brcms_b_write_shm(wlc_hw, M_RSP_PCTLWD, phyctl);
2550 }
2551
2552 void brcms_b_txant_set(struct wlc_hw_info *wlc_hw, u16 phytxant)
2553 {
2554         /* update sw state */
2555         wlc_hw->bmac_phytxant = phytxant;
2556
2557         /* push to ucode if up */
2558         if (!wlc_hw->up)
2559                 return;
2560         wlc_ucode_txant_set(wlc_hw);
2561
2562 }
2563
2564 u16 brcms_b_get_txant(struct wlc_hw_info *wlc_hw)
2565 {
2566         return (u16) wlc_hw->wlc->stf->txant;
2567 }
2568
2569 void brcms_b_antsel_type_set(struct wlc_hw_info *wlc_hw, u8 antsel_type)
2570 {
2571         wlc_hw->antsel_type = antsel_type;
2572
2573         /* Update the antsel type for phy module to use */
2574         wlc_phy_antsel_type_set(wlc_hw->band->pi, antsel_type);
2575 }
2576
2577 void brcms_b_fifoerrors(struct wlc_hw_info *wlc_hw)
2578 {
2579         bool fatal = false;
2580         uint unit;
2581         uint intstatus, idx;
2582         d11regs_t *regs = wlc_hw->regs;
2583         struct wiphy *wiphy = wlc_hw->wlc->wiphy;
2584
2585         unit = wlc_hw->unit;
2586
2587         for (idx = 0; idx < NFIFO; idx++) {
2588                 /* read intstatus register and ignore any non-error bits */
2589                 intstatus =
2590                     R_REG(&regs->intctrlregs[idx].intstatus) & I_ERRORS;
2591                 if (!intstatus)
2592                         continue;
2593
2594                 BCMMSG(wlc_hw->wlc->wiphy, "wl%d: intstatus%d 0x%x\n",
2595                         unit, idx, intstatus);
2596
2597                 if (intstatus & I_RO) {
2598                         wiphy_err(wiphy, "wl%d: fifo %d: receive fifo "
2599                                   "overflow\n", unit, idx);
2600                         fatal = true;
2601                 }
2602
2603                 if (intstatus & I_PC) {
2604                         wiphy_err(wiphy, "wl%d: fifo %d: descriptor error\n",
2605                                  unit, idx);
2606                         fatal = true;
2607                 }
2608
2609                 if (intstatus & I_PD) {
2610                         wiphy_err(wiphy, "wl%d: fifo %d: data error\n", unit,
2611                                   idx);
2612                         fatal = true;
2613                 }
2614
2615                 if (intstatus & I_DE) {
2616                         wiphy_err(wiphy, "wl%d: fifo %d: descriptor protocol "
2617                                   "error\n", unit, idx);
2618                         fatal = true;
2619                 }
2620
2621                 if (intstatus & I_RU) {
2622                         wiphy_err(wiphy, "wl%d: fifo %d: receive descriptor "
2623                                   "underflow\n", idx, unit);
2624                 }
2625
2626                 if (intstatus & I_XU) {
2627                         wiphy_err(wiphy, "wl%d: fifo %d: transmit fifo "
2628                                   "underflow\n", idx, unit);
2629                         fatal = true;
2630                 }
2631
2632                 if (fatal) {
2633                         wlc_fatal_error(wlc_hw->wlc);   /* big hammer */
2634                         break;
2635                 } else
2636                         W_REG(&regs->intctrlregs[idx].intstatus,
2637                               intstatus);
2638         }
2639 }
2640
2641 void wlc_intrson(struct wlc_info *wlc)
2642 {
2643         struct wlc_hw_info *wlc_hw = wlc->hw;
2644         wlc->macintmask = wlc->defmacintmask;
2645         W_REG(&wlc_hw->regs->macintmask, wlc->macintmask);
2646 }
2647
2648 /* callback for siutils.c, which has only wlc handler, no wl
2649  * they both check up, not only because there is no need to off/restore d11 interrupt
2650  *  but also because per-port code may require sync with valid interrupt.
2651  */
2652
2653 static u32 wlc_wlintrsoff(struct wlc_info *wlc)
2654 {
2655         if (!wlc->hw->up)
2656                 return 0;
2657
2658         return brcms_intrsoff(wlc->wl);
2659 }
2660
2661 static void wlc_wlintrsrestore(struct wlc_info *wlc, u32 macintmask)
2662 {
2663         if (!wlc->hw->up)
2664                 return;
2665
2666         brcms_intrsrestore(wlc->wl, macintmask);
2667 }
2668
2669 u32 wlc_intrsoff(struct wlc_info *wlc)
2670 {
2671         struct wlc_hw_info *wlc_hw = wlc->hw;
2672         u32 macintmask;
2673
2674         if (!wlc_hw->clk)
2675                 return 0;
2676
2677         macintmask = wlc->macintmask;   /* isr can still happen */
2678
2679         W_REG(&wlc_hw->regs->macintmask, 0);
2680         (void)R_REG(&wlc_hw->regs->macintmask); /* sync readback */
2681         udelay(1);              /* ensure int line is no longer driven */
2682         wlc->macintmask = 0;
2683
2684         /* return previous macintmask; resolve race between us and our isr */
2685         return wlc->macintstatus ? 0 : macintmask;
2686 }
2687
2688 void wlc_intrsrestore(struct wlc_info *wlc, u32 macintmask)
2689 {
2690         struct wlc_hw_info *wlc_hw = wlc->hw;
2691         if (!wlc_hw->clk)
2692                 return;
2693
2694         wlc->macintmask = macintmask;
2695         W_REG(&wlc_hw->regs->macintmask, wlc->macintmask);
2696 }
2697
2698 static void brcms_b_mute(struct wlc_hw_info *wlc_hw, bool on, mbool flags)
2699 {
2700         u8 null_ether_addr[ETH_ALEN] = {0, 0, 0, 0, 0, 0};
2701
2702         if (on) {
2703                 /* suspend tx fifos */
2704                 brcms_b_tx_fifo_suspend(wlc_hw, TX_DATA_FIFO);
2705                 brcms_b_tx_fifo_suspend(wlc_hw, TX_CTL_FIFO);
2706                 brcms_b_tx_fifo_suspend(wlc_hw, TX_AC_BK_FIFO);
2707                 brcms_b_tx_fifo_suspend(wlc_hw, TX_AC_VI_FIFO);
2708
2709                 /* zero the address match register so we do not send ACKs */
2710                 brcms_b_set_addrmatch(wlc_hw, RCM_MAC_OFFSET,
2711                                        null_ether_addr);
2712         } else {
2713                 /* resume tx fifos */
2714                 if (!wlc_hw->wlc->tx_suspended) {
2715                         brcms_b_tx_fifo_resume(wlc_hw, TX_DATA_FIFO);
2716                 }
2717                 brcms_b_tx_fifo_resume(wlc_hw, TX_CTL_FIFO);
2718                 brcms_b_tx_fifo_resume(wlc_hw, TX_AC_BK_FIFO);
2719                 brcms_b_tx_fifo_resume(wlc_hw, TX_AC_VI_FIFO);
2720
2721                 /* Restore address */
2722                 brcms_b_set_addrmatch(wlc_hw, RCM_MAC_OFFSET,
2723                                        wlc_hw->etheraddr);
2724         }
2725
2726         wlc_phy_mute_upd(wlc_hw->band->pi, on, flags);
2727
2728         if (on)
2729                 wlc_ucode_mute_override_set(wlc_hw);
2730         else
2731                 wlc_ucode_mute_override_clear(wlc_hw);
2732 }
2733
2734 int brcms_b_xmtfifo_sz_get(struct wlc_hw_info *wlc_hw, uint fifo, uint *blocks)
2735 {
2736         if (fifo >= NFIFO)
2737                 return -EINVAL;
2738
2739         *blocks = wlc_hw->xmtfifo_sz[fifo];
2740
2741         return 0;
2742 }
2743
2744 /* brcms_b_tx_fifo_suspended:
2745  * Check the MAC's tx suspend status for a tx fifo.
2746  *
2747  * When the MAC acknowledges a tx suspend, it indicates that no more
2748  * packets will be transmitted out the radio. This is independent of
2749  * DMA channel suspension---the DMA may have finished suspending, or may still
2750  * be pulling data into a tx fifo, by the time the MAC acks the suspend
2751  * request.
2752  */
2753 static bool brcms_b_tx_fifo_suspended(struct wlc_hw_info *wlc_hw, uint tx_fifo)
2754 {
2755         /* check that a suspend has been requested and is no longer pending */
2756
2757         /*
2758          * for DMA mode, the suspend request is set in xmtcontrol of the DMA engine,
2759          * and the tx fifo suspend at the lower end of the MAC is acknowledged in the
2760          * chnstatus register.
2761          * The tx fifo suspend completion is independent of the DMA suspend completion and
2762          *   may be acked before or after the DMA is suspended.
2763          */
2764         if (dma_txsuspended(wlc_hw->di[tx_fifo]) &&
2765             (R_REG(&wlc_hw->regs->chnstatus) &
2766              (1 << tx_fifo)) == 0)
2767                 return true;
2768
2769         return false;
2770 }
2771
2772 static void brcms_b_tx_fifo_suspend(struct wlc_hw_info *wlc_hw, uint tx_fifo)
2773 {
2774         u8 fifo = 1 << tx_fifo;
2775
2776         /* Two clients of this code, 11h Quiet period and scanning. */
2777
2778         /* only suspend if not already suspended */
2779         if ((wlc_hw->suspended_fifos & fifo) == fifo)
2780                 return;
2781
2782         /* force the core awake only if not already */
2783         if (wlc_hw->suspended_fifos == 0)
2784                 wlc_ucode_wake_override_set(wlc_hw, WLC_WAKE_OVERRIDE_TXFIFO);
2785
2786         wlc_hw->suspended_fifos |= fifo;
2787
2788         if (wlc_hw->di[tx_fifo]) {
2789                 /* Suspending AMPDU transmissions in the middle can cause underflow
2790                  * which may result in mismatch between ucode and driver
2791                  * so suspend the mac before suspending the FIFO
2792                  */
2793                 if (WLC_PHY_11N_CAP(wlc_hw->band))
2794                         wlc_suspend_mac_and_wait(wlc_hw->wlc);
2795
2796                 dma_txsuspend(wlc_hw->di[tx_fifo]);
2797
2798                 if (WLC_PHY_11N_CAP(wlc_hw->band))
2799                         wlc_enable_mac(wlc_hw->wlc);
2800         }
2801 }
2802
2803 static void brcms_b_tx_fifo_resume(struct wlc_hw_info *wlc_hw, uint tx_fifo)
2804 {
2805         /* BMAC_NOTE: WLC_TX_FIFO_ENAB is done in wlc_dpc() for DMA case but need to be done
2806          * here for PIO otherwise the watchdog will catch the inconsistency and fire
2807          */
2808         /* Two clients of this code, 11h Quiet period and scanning. */
2809         if (wlc_hw->di[tx_fifo])
2810                 dma_txresume(wlc_hw->di[tx_fifo]);
2811
2812         /* allow core to sleep again */
2813         if (wlc_hw->suspended_fifos == 0)
2814                 return;
2815         else {
2816                 wlc_hw->suspended_fifos &= ~(1 << tx_fifo);
2817                 if (wlc_hw->suspended_fifos == 0)
2818                         wlc_ucode_wake_override_clear(wlc_hw,
2819                                                       WLC_WAKE_OVERRIDE_TXFIFO);
2820         }
2821 }
2822
2823 /*
2824  * Read and clear macintmask and macintstatus and intstatus registers.
2825  * This routine should be called with interrupts off
2826  * Return:
2827  *   -1 if DEVICEREMOVED(wlc) evaluates to true;
2828  *   0 if the interrupt is not for us, or we are in some special cases;
2829  *   device interrupt status bits otherwise.
2830  */
2831 static inline u32 wlc_intstatus(struct wlc_info *wlc, bool in_isr)
2832 {
2833         struct wlc_hw_info *wlc_hw = wlc->hw;
2834         d11regs_t *regs = wlc_hw->regs;
2835         u32 macintstatus;
2836
2837         /* macintstatus includes a DMA interrupt summary bit */
2838         macintstatus = R_REG(&regs->macintstatus);
2839
2840         BCMMSG(wlc->wiphy, "wl%d: macintstatus: 0x%x\n", wlc_hw->unit,
2841                  macintstatus);
2842
2843         /* detect cardbus removed, in power down(suspend) and in reset */
2844         if (DEVICEREMOVED(wlc))
2845                 return -1;
2846
2847         /* DEVICEREMOVED succeeds even when the core is still resetting,
2848          * handle that case here.
2849          */
2850         if (macintstatus == 0xffffffff)
2851                 return 0;
2852
2853         /* defer unsolicited interrupts */
2854         macintstatus &= (in_isr ? wlc->macintmask : wlc->defmacintmask);
2855
2856         /* if not for us */
2857         if (macintstatus == 0)
2858                 return 0;
2859
2860         /* interrupts are already turned off for CFE build
2861          * Caution: For CFE Turning off the interrupts again has some undesired
2862          * consequences
2863          */
2864         /* turn off the interrupts */
2865         W_REG(&regs->macintmask, 0);
2866         (void)R_REG(&regs->macintmask); /* sync readback */
2867         wlc->macintmask = 0;
2868
2869         /* clear device interrupts */
2870         W_REG(&regs->macintstatus, macintstatus);
2871
2872         /* MI_DMAINT is indication of non-zero intstatus */
2873         if (macintstatus & MI_DMAINT) {
2874                 /*
2875                  * only fifo interrupt enabled is I_RI in
2876                  * RX_FIFO. If MI_DMAINT is set, assume it
2877                  * is set and clear the interrupt.
2878                  */
2879                 W_REG(&regs->intctrlregs[RX_FIFO].intstatus,
2880                       DEF_RXINTMASK);
2881         }
2882
2883         return macintstatus;
2884 }
2885
2886 /* Update wlc->macintstatus and wlc->intstatus[]. */
2887 /* Return true if they are updated successfully. false otherwise */
2888 bool wlc_intrsupd(struct wlc_info *wlc)
2889 {
2890         u32 macintstatus;
2891
2892         /* read and clear macintstatus and intstatus registers */
2893         macintstatus = wlc_intstatus(wlc, false);
2894
2895         /* device is removed */
2896         if (macintstatus == 0xffffffff)
2897                 return false;
2898
2899         /* update interrupt status in software */
2900         wlc->macintstatus |= macintstatus;
2901
2902         return true;
2903 }
2904
2905 /*
2906  * First-level interrupt processing.
2907  * Return true if this was our interrupt, false otherwise.
2908  * *wantdpc will be set to true if further wlc_dpc() processing is required,
2909  * false otherwise.
2910  */
2911 bool wlc_isr(struct wlc_info *wlc, bool *wantdpc)
2912 {
2913         struct wlc_hw_info *wlc_hw = wlc->hw;
2914         u32 macintstatus;
2915
2916         *wantdpc = false;
2917
2918         if (!wlc_hw->up || !wlc->macintmask)
2919                 return false;
2920
2921         /* read and clear macintstatus and intstatus registers */
2922         macintstatus = wlc_intstatus(wlc, true);
2923
2924         if (macintstatus == 0xffffffff)
2925                 wiphy_err(wlc->wiphy, "DEVICEREMOVED detected in the ISR code"
2926                           " path\n");
2927
2928         /* it is not for us */
2929         if (macintstatus == 0)
2930                 return false;
2931
2932         *wantdpc = true;
2933
2934         /* save interrupt status bits */
2935         wlc->macintstatus = macintstatus;
2936
2937         return true;
2938
2939 }
2940
2941 static bool
2942 brcms_b_dotxstatus(struct wlc_hw_info *wlc_hw, tx_status_t *txs, u32 s2)
2943 {
2944         /* discard intermediate indications for ucode with one legitimate case:
2945          *   e.g. if "useRTS" is set. ucode did a successful rts/cts exchange, but the subsequent
2946          *   tx of DATA failed. so it will start rts/cts from the beginning (resetting the rts
2947          *   transmission count)
2948          */
2949         if (!(txs->status & TX_STATUS_AMPDU)
2950             && (txs->status & TX_STATUS_INTERMEDIATE)) {
2951                 return false;
2952         }
2953
2954         return wlc_dotxstatus(wlc_hw->wlc, txs, s2);
2955 }
2956
2957 /* process tx completion events in BMAC
2958  * Return true if more tx status need to be processed. false otherwise.
2959  */
2960 static bool
2961 brcms_b_txstatus(struct wlc_hw_info *wlc_hw, bool bound, bool *fatal)
2962 {
2963         bool morepending = false;
2964         struct wlc_info *wlc = wlc_hw->wlc;
2965         d11regs_t *regs;
2966         tx_status_t txstatus, *txs;
2967         u32 s1, s2;
2968         uint n = 0;
2969         /*
2970          * Param 'max_tx_num' indicates max. # tx status to process before
2971          * break out.
2972          */
2973         uint max_tx_num = bound ? wlc->pub->tunables->txsbnd : -1;
2974
2975         BCMMSG(wlc->wiphy, "wl%d\n", wlc_hw->unit);
2976
2977         txs = &txstatus;
2978         regs = wlc_hw->regs;
2979         while (!(*fatal)
2980                && (s1 = R_REG(&regs->frmtxstatus)) & TXS_V) {
2981
2982                 if (s1 == 0xffffffff) {
2983                         wiphy_err(wlc->wiphy, "wl%d: %s: dead chip\n",
2984                                 wlc_hw->unit, __func__);
2985                         return morepending;
2986                 }
2987
2988                         s2 = R_REG(&regs->frmtxstatus2);
2989
2990                 txs->status = s1 & TXS_STATUS_MASK;
2991                 txs->frameid = (s1 & TXS_FID_MASK) >> TXS_FID_SHIFT;
2992                 txs->sequence = s2 & TXS_SEQ_MASK;
2993                 txs->phyerr = (s2 & TXS_PTX_MASK) >> TXS_PTX_SHIFT;
2994                 txs->lasttxtime = 0;
2995
2996                 *fatal = brcms_b_dotxstatus(wlc_hw, txs, s2);
2997
2998                 /* !give others some time to run! */
2999                 if (++n >= max_tx_num)
3000                         break;
3001         }
3002
3003         if (*fatal)
3004                 return 0;
3005
3006         if (n >= max_tx_num)
3007                 morepending = true;
3008
3009         if (!pktq_empty(&wlc->pkt_queue->q))
3010                 wlc_send_q(wlc);
3011
3012         return morepending;
3013 }
3014
3015 void wlc_suspend_mac_and_wait(struct wlc_info *wlc)
3016 {
3017         struct wlc_hw_info *wlc_hw = wlc->hw;
3018         d11regs_t *regs = wlc_hw->regs;
3019         u32 mc, mi;
3020         struct wiphy *wiphy = wlc->wiphy;
3021
3022         BCMMSG(wlc->wiphy, "wl%d: bandunit %d\n", wlc_hw->unit,
3023                 wlc_hw->band->bandunit);
3024
3025         /*
3026          * Track overlapping suspend requests
3027          */
3028         wlc_hw->mac_suspend_depth++;
3029         if (wlc_hw->mac_suspend_depth > 1)
3030                 return;
3031
3032         /* force the core awake */
3033         wlc_ucode_wake_override_set(wlc_hw, WLC_WAKE_OVERRIDE_MACSUSPEND);
3034
3035         mc = R_REG(&regs->maccontrol);
3036
3037         if (mc == 0xffffffff) {
3038                 wiphy_err(wiphy, "wl%d: %s: dead chip\n", wlc_hw->unit,
3039                           __func__);
3040                 brcms_down(wlc->wl);
3041                 return;
3042         }
3043         WARN_ON(mc & MCTL_PSM_JMP_0);
3044         WARN_ON(!(mc & MCTL_PSM_RUN));
3045         WARN_ON(!(mc & MCTL_EN_MAC));
3046
3047         mi = R_REG(&regs->macintstatus);
3048         if (mi == 0xffffffff) {
3049                 wiphy_err(wiphy, "wl%d: %s: dead chip\n", wlc_hw->unit,
3050                           __func__);
3051                 brcms_down(wlc->wl);
3052                 return;
3053         }
3054         WARN_ON(mi & MI_MACSSPNDD);
3055
3056         brcms_b_mctrl(wlc_hw, MCTL_EN_MAC, 0);
3057
3058         SPINWAIT(!(R_REG(&regs->macintstatus) & MI_MACSSPNDD),
3059                  WLC_MAX_MAC_SUSPEND);
3060
3061         if (!(R_REG(&regs->macintstatus) & MI_MACSSPNDD)) {
3062                 wiphy_err(wiphy, "wl%d: wlc_suspend_mac_and_wait: waited %d uS"
3063                           " and MI_MACSSPNDD is still not on.\n",
3064                           wlc_hw->unit, WLC_MAX_MAC_SUSPEND);
3065                 wiphy_err(wiphy, "wl%d: psmdebug 0x%08x, phydebug 0x%08x, "
3066                           "psm_brc 0x%04x\n", wlc_hw->unit,
3067                           R_REG(&regs->psmdebug),
3068                           R_REG(&regs->phydebug),
3069                           R_REG(&regs->psm_brc));
3070         }
3071
3072         mc = R_REG(&regs->maccontrol);
3073         if (mc == 0xffffffff) {
3074                 wiphy_err(wiphy, "wl%d: %s: dead chip\n", wlc_hw->unit,
3075                           __func__);
3076                 brcms_down(wlc->wl);
3077                 return;
3078         }
3079         WARN_ON(mc & MCTL_PSM_JMP_0);
3080         WARN_ON(!(mc & MCTL_PSM_RUN));
3081         WARN_ON(mc & MCTL_EN_MAC);
3082 }
3083
3084 void wlc_enable_mac(struct wlc_info *wlc)
3085 {
3086         struct wlc_hw_info *wlc_hw = wlc->hw;
3087         d11regs_t *regs = wlc_hw->regs;
3088         u32 mc, mi;
3089
3090         BCMMSG(wlc->wiphy, "wl%d: bandunit %d\n", wlc_hw->unit,
3091                 wlc->band->bandunit);
3092
3093         /*
3094          * Track overlapping suspend requests
3095          */
3096         wlc_hw->mac_suspend_depth--;
3097         if (wlc_hw->mac_suspend_depth > 0)
3098                 return;
3099
3100         mc = R_REG(&regs->maccontrol);
3101         WARN_ON(mc & MCTL_PSM_JMP_0);
3102         WARN_ON(mc & MCTL_EN_MAC);
3103         WARN_ON(!(mc & MCTL_PSM_RUN));
3104
3105         brcms_b_mctrl(wlc_hw, MCTL_EN_MAC, MCTL_EN_MAC);
3106         W_REG(&regs->macintstatus, MI_MACSSPNDD);
3107
3108         mc = R_REG(&regs->maccontrol);
3109         WARN_ON(mc & MCTL_PSM_JMP_0);
3110         WARN_ON(!(mc & MCTL_EN_MAC));
3111         WARN_ON(!(mc & MCTL_PSM_RUN));
3112
3113         mi = R_REG(&regs->macintstatus);
3114         WARN_ON(mi & MI_MACSSPNDD);
3115
3116         wlc_ucode_wake_override_clear(wlc_hw, WLC_WAKE_OVERRIDE_MACSUSPEND);
3117 }
3118
3119 static void wlc_upd_ofdm_pctl1_table(struct wlc_hw_info *wlc_hw)
3120 {
3121         u8 rate;
3122         u8 rates[8] = {
3123                 WLC_RATE_6M, WLC_RATE_9M, WLC_RATE_12M, WLC_RATE_18M,
3124                 WLC_RATE_24M, WLC_RATE_36M, WLC_RATE_48M, WLC_RATE_54M
3125         };
3126         u16 entry_ptr;
3127         u16 pctl1;
3128         uint i;
3129
3130         if (!WLC_PHY_11N_CAP(wlc_hw->band))
3131                 return;
3132
3133         /* walk the phy rate table and update the entries */
3134         for (i = 0; i < ARRAY_SIZE(rates); i++) {
3135                 rate = rates[i];
3136
3137                 entry_ptr = brcms_b_ofdm_ratetable_offset(wlc_hw, rate);
3138
3139                 /* read the SHM Rate Table entry OFDM PCTL1 values */
3140                 pctl1 =
3141                     brcms_b_read_shm(wlc_hw, entry_ptr + M_RT_OFDM_PCTL1_POS);
3142
3143                 /* modify the value */
3144                 pctl1 &= ~PHY_TXC1_MODE_MASK;
3145                 pctl1 |= (wlc_hw->hw_stf_ss_opmode << PHY_TXC1_MODE_SHIFT);
3146
3147                 /* Update the SHM Rate Table entry OFDM PCTL1 values */
3148                 brcms_b_write_shm(wlc_hw, entry_ptr + M_RT_OFDM_PCTL1_POS,
3149                                    pctl1);
3150         }
3151 }
3152
3153 static u16 brcms_b_ofdm_ratetable_offset(struct wlc_hw_info *wlc_hw, u8 rate)
3154 {
3155         uint i;
3156         u8 plcp_rate = 0;
3157         struct plcp_signal_rate_lookup {
3158                 u8 rate;
3159                 u8 signal_rate;
3160         };
3161         /* OFDM RATE sub-field of PLCP SIGNAL field, per 802.11 sec 17.3.4.1 */
3162         const struct plcp_signal_rate_lookup rate_lookup[] = {
3163                 {WLC_RATE_6M, 0xB},
3164                 {WLC_RATE_9M, 0xF},
3165                 {WLC_RATE_12M, 0xA},
3166                 {WLC_RATE_18M, 0xE},
3167                 {WLC_RATE_24M, 0x9},
3168                 {WLC_RATE_36M, 0xD},
3169                 {WLC_RATE_48M, 0x8},
3170                 {WLC_RATE_54M, 0xC}
3171         };
3172
3173         for (i = 0; i < ARRAY_SIZE(rate_lookup); i++) {
3174                 if (rate == rate_lookup[i].rate) {
3175                         plcp_rate = rate_lookup[i].signal_rate;
3176                         break;
3177                 }
3178         }
3179
3180         /* Find the SHM pointer to the rate table entry by looking in the
3181          * Direct-map Table
3182          */
3183         return 2 * brcms_b_read_shm(wlc_hw, M_RT_DIRMAP_A + (plcp_rate * 2));
3184 }
3185
3186 void brcms_b_band_stf_ss_set(struct wlc_hw_info *wlc_hw, u8 stf_mode)
3187 {
3188         wlc_hw->hw_stf_ss_opmode = stf_mode;
3189
3190         if (wlc_hw->clk)
3191                 wlc_upd_ofdm_pctl1_table(wlc_hw);
3192 }
3193
3194 void
3195 brcms_b_read_tsf(struct wlc_hw_info *wlc_hw, u32 *tsf_l_ptr,
3196                   u32 *tsf_h_ptr)
3197 {
3198         d11regs_t *regs = wlc_hw->regs;
3199
3200         /* read the tsf timer low, then high to get an atomic read */
3201         *tsf_l_ptr = R_REG(&regs->tsf_timerlow);
3202         *tsf_h_ptr = R_REG(&regs->tsf_timerhigh);
3203
3204         return;
3205 }
3206
3207 static bool brcms_b_validate_chip_access(struct wlc_hw_info *wlc_hw)
3208 {
3209         d11regs_t *regs;
3210         u32 w, val;
3211         struct wiphy *wiphy = wlc_hw->wlc->wiphy;
3212
3213         BCMMSG(wiphy, "wl%d\n", wlc_hw->unit);
3214
3215         regs = wlc_hw->regs;
3216
3217         /* Validate dchip register access */
3218
3219         W_REG(&regs->objaddr, OBJADDR_SHM_SEL | 0);
3220         (void)R_REG(&regs->objaddr);
3221         w = R_REG(&regs->objdata);
3222
3223         /* Can we write and read back a 32bit register? */
3224         W_REG(&regs->objaddr, OBJADDR_SHM_SEL | 0);
3225         (void)R_REG(&regs->objaddr);
3226         W_REG(&regs->objdata, (u32) 0xaa5555aa);
3227
3228         W_REG(&regs->objaddr, OBJADDR_SHM_SEL | 0);
3229         (void)R_REG(&regs->objaddr);
3230         val = R_REG(&regs->objdata);
3231         if (val != (u32) 0xaa5555aa) {
3232                 wiphy_err(wiphy, "wl%d: validate_chip_access: SHM = 0x%x, "
3233                           "expected 0xaa5555aa\n", wlc_hw->unit, val);
3234                 return false;
3235         }
3236
3237         W_REG(&regs->objaddr, OBJADDR_SHM_SEL | 0);
3238         (void)R_REG(&regs->objaddr);
3239         W_REG(&regs->objdata, (u32) 0x55aaaa55);
3240
3241         W_REG(&regs->objaddr, OBJADDR_SHM_SEL | 0);
3242         (void)R_REG(&regs->objaddr);
3243         val = R_REG(&regs->objdata);
3244         if (val != (u32) 0x55aaaa55) {
3245                 wiphy_err(wiphy, "wl%d: validate_chip_access: SHM = 0x%x, "
3246                           "expected 0x55aaaa55\n", wlc_hw->unit, val);
3247                 return false;
3248         }
3249
3250         W_REG(&regs->objaddr, OBJADDR_SHM_SEL | 0);
3251         (void)R_REG(&regs->objaddr);
3252         W_REG(&regs->objdata, w);
3253
3254         /* clear CFPStart */
3255         W_REG(&regs->tsf_cfpstart, 0);
3256
3257         w = R_REG(&regs->maccontrol);
3258         if ((w != (MCTL_IHR_EN | MCTL_WAKE)) &&
3259             (w != (MCTL_IHR_EN | MCTL_GMODE | MCTL_WAKE))) {
3260                 wiphy_err(wiphy, "wl%d: validate_chip_access: maccontrol = "
3261                           "0x%x, expected 0x%x or 0x%x\n", wlc_hw->unit, w,
3262                           (MCTL_IHR_EN | MCTL_WAKE),
3263                           (MCTL_IHR_EN | MCTL_GMODE | MCTL_WAKE));
3264                 return false;
3265         }
3266
3267         return true;
3268 }
3269
3270 #define PHYPLL_WAIT_US  100000
3271
3272 void brcms_b_core_phypll_ctl(struct wlc_hw_info *wlc_hw, bool on)
3273 {
3274         d11regs_t *regs;
3275         u32 tmp;
3276
3277         BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
3278
3279         tmp = 0;
3280         regs = wlc_hw->regs;
3281
3282         if (on) {
3283                 if ((wlc_hw->sih->chip == BCM4313_CHIP_ID)) {
3284                         OR_REG(&regs->clk_ctl_st,
3285                                (CCS_ERSRC_REQ_HT | CCS_ERSRC_REQ_D11PLL |
3286                                 CCS_ERSRC_REQ_PHYPLL));
3287                         SPINWAIT((R_REG(&regs->clk_ctl_st) &
3288                                   (CCS_ERSRC_AVAIL_HT)) != (CCS_ERSRC_AVAIL_HT),
3289                                  PHYPLL_WAIT_US);
3290
3291                         tmp = R_REG(&regs->clk_ctl_st);
3292                         if ((tmp & (CCS_ERSRC_AVAIL_HT)) !=
3293                             (CCS_ERSRC_AVAIL_HT)) {
3294                                 wiphy_err(wlc_hw->wlc->wiphy, "%s: turn on PHY"
3295                                           " PLL failed\n", __func__);
3296                         }
3297                 } else {
3298                         OR_REG(&regs->clk_ctl_st,
3299                                (CCS_ERSRC_REQ_D11PLL | CCS_ERSRC_REQ_PHYPLL));
3300                         SPINWAIT((R_REG(&regs->clk_ctl_st) &
3301                                   (CCS_ERSRC_AVAIL_D11PLL |
3302                                    CCS_ERSRC_AVAIL_PHYPLL)) !=
3303                                  (CCS_ERSRC_AVAIL_D11PLL |
3304                                   CCS_ERSRC_AVAIL_PHYPLL), PHYPLL_WAIT_US);
3305
3306                         tmp = R_REG(&regs->clk_ctl_st);
3307                         if ((tmp &
3308                              (CCS_ERSRC_AVAIL_D11PLL | CCS_ERSRC_AVAIL_PHYPLL))
3309                             !=
3310                             (CCS_ERSRC_AVAIL_D11PLL | CCS_ERSRC_AVAIL_PHYPLL)) {
3311                                 wiphy_err(wlc_hw->wlc->wiphy, "%s: turn on "
3312                                           "PHY PLL failed\n", __func__);
3313                         }
3314                 }
3315         } else {
3316                 /* Since the PLL may be shared, other cores can still be requesting it;
3317                  * so we'll deassert the request but not wait for status to comply.
3318                  */
3319                 AND_REG(&regs->clk_ctl_st, ~CCS_ERSRC_REQ_PHYPLL);
3320                 tmp = R_REG(&regs->clk_ctl_st);
3321         }
3322 }
3323
3324 void wlc_coredisable(struct wlc_hw_info *wlc_hw)
3325 {
3326         bool dev_gone;
3327
3328         BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
3329
3330         dev_gone = DEVICEREMOVED(wlc_hw->wlc);
3331
3332         if (dev_gone)
3333                 return;
3334
3335         if (wlc_hw->noreset)
3336                 return;
3337
3338         /* radio off */
3339         wlc_phy_switch_radio(wlc_hw->band->pi, OFF);
3340
3341         /* turn off analog core */
3342         wlc_phy_anacore(wlc_hw->band->pi, OFF);
3343
3344         /* turn off PHYPLL to save power */
3345         brcms_b_core_phypll_ctl(wlc_hw, false);
3346
3347         /* No need to set wlc->pub->radio_active = OFF
3348          * because this function needs down capability and
3349          * radio_active is designed for BCMNODOWN.
3350          */
3351
3352         /* remove gpio controls */
3353         if (wlc_hw->ucode_dbgsel)
3354                 ai_gpiocontrol(wlc_hw->sih, ~0, 0, GPIO_DRV_PRIORITY);
3355
3356         wlc_hw->clk = false;
3357         ai_core_disable(wlc_hw->sih, 0);
3358         wlc_phy_hw_clk_state_upd(wlc_hw->band->pi, false);
3359 }
3360
3361 /* power both the pll and external oscillator on/off */
3362 static void brcms_b_xtal(struct wlc_hw_info *wlc_hw, bool want)
3363 {
3364         BCMMSG(wlc_hw->wlc->wiphy, "wl%d: want %d\n", wlc_hw->unit, want);
3365
3366         /* dont power down if plldown is false or we must poll hw radio disable */
3367         if (!want && wlc_hw->pllreq)
3368                 return;
3369
3370         if (wlc_hw->sih)
3371                 ai_clkctl_xtal(wlc_hw->sih, XTAL | PLL, want);
3372
3373         wlc_hw->sbclk = want;
3374         if (!wlc_hw->sbclk) {
3375                 wlc_hw->clk = false;
3376                 if (wlc_hw->band && wlc_hw->band->pi)
3377                         wlc_phy_hw_clk_state_upd(wlc_hw->band->pi, false);
3378         }
3379 }
3380
3381 static void wlc_flushqueues(struct wlc_info *wlc)
3382 {
3383         struct wlc_hw_info *wlc_hw = wlc->hw;
3384         uint i;
3385
3386         wlc->txpend16165war = 0;
3387
3388         /* free any posted tx packets */
3389         for (i = 0; i < NFIFO; i++)
3390                 if (wlc_hw->di[i]) {
3391                         dma_txreclaim(wlc_hw->di[i], DMA_RANGE_ALL);
3392                         TXPKTPENDCLR(wlc, i);
3393                         BCMMSG(wlc->wiphy, "pktpend fifo %d clrd\n", i);
3394                 }
3395
3396         /* free any posted rx packets */
3397         dma_rxreclaim(wlc_hw->di[RX_FIFO]);
3398 }
3399
3400 u16 brcms_b_read_shm(struct wlc_hw_info *wlc_hw, uint offset)
3401 {
3402         return brcms_b_read_objmem(wlc_hw, offset, OBJADDR_SHM_SEL);
3403 }
3404
3405 void brcms_b_write_shm(struct wlc_hw_info *wlc_hw, uint offset, u16 v)
3406 {
3407         brcms_b_write_objmem(wlc_hw, offset, v, OBJADDR_SHM_SEL);
3408 }
3409
3410 static u16
3411 brcms_b_read_objmem(struct wlc_hw_info *wlc_hw, uint offset, u32 sel)
3412 {
3413         d11regs_t *regs = wlc_hw->regs;
3414         volatile u16 *objdata_lo = (volatile u16 *)&regs->objdata;
3415         volatile u16 *objdata_hi = objdata_lo + 1;
3416         u16 v;
3417
3418         W_REG(&regs->objaddr, sel | (offset >> 2));
3419         (void)R_REG(&regs->objaddr);
3420         if (offset & 2) {
3421                 v = R_REG(objdata_hi);
3422         } else {
3423                 v = R_REG(objdata_lo);
3424         }
3425
3426         return v;
3427 }
3428
3429 static void
3430 brcms_b_write_objmem(struct wlc_hw_info *wlc_hw, uint offset, u16 v, u32 sel)
3431 {
3432         d11regs_t *regs = wlc_hw->regs;
3433         volatile u16 *objdata_lo = (volatile u16 *)&regs->objdata;
3434         volatile u16 *objdata_hi = objdata_lo + 1;
3435
3436         W_REG(&regs->objaddr, sel | (offset >> 2));
3437         (void)R_REG(&regs->objaddr);
3438         if (offset & 2) {
3439                 W_REG(objdata_hi, v);
3440         } else {
3441                 W_REG(objdata_lo, v);
3442         }
3443 }
3444
3445 /* Copy a buffer to shared memory of specified type .
3446  * SHM 'offset' needs to be an even address and
3447  * Buffer length 'len' must be an even number of bytes
3448  * 'sel' selects the type of memory
3449  */
3450 void
3451 brcms_b_copyto_objmem(struct wlc_hw_info *wlc_hw, uint offset, const void *buf,
3452                        int len, u32 sel)
3453 {
3454         u16 v;
3455         const u8 *p = (const u8 *)buf;
3456         int i;
3457
3458         if (len <= 0 || (offset & 1) || (len & 1))
3459                 return;
3460
3461         for (i = 0; i < len; i += 2) {
3462                 v = p[i] | (p[i + 1] << 8);
3463                 brcms_b_write_objmem(wlc_hw, offset + i, v, sel);
3464         }
3465 }
3466
3467 /* Copy a piece of shared memory of specified type to a buffer .
3468  * SHM 'offset' needs to be an even address and
3469  * Buffer length 'len' must be an even number of bytes
3470  * 'sel' selects the type of memory
3471  */
3472 void
3473 brcms_b_copyfrom_objmem(struct wlc_hw_info *wlc_hw, uint offset, void *buf,
3474                          int len, u32 sel)
3475 {
3476         u16 v;
3477         u8 *p = (u8 *) buf;
3478         int i;
3479
3480         if (len <= 0 || (offset & 1) || (len & 1))
3481                 return;
3482
3483         for (i = 0; i < len; i += 2) {
3484                 v = brcms_b_read_objmem(wlc_hw, offset + i, sel);
3485                 p[i] = v & 0xFF;
3486                 p[i + 1] = (v >> 8) & 0xFF;
3487         }
3488 }
3489
3490 void brcms_b_copyfrom_vars(struct wlc_hw_info *wlc_hw, char **buf, uint *len)
3491 {
3492         BCMMSG(wlc_hw->wlc->wiphy, "nvram vars totlen=%d\n",
3493                 wlc_hw->vars_size);
3494
3495         *buf = wlc_hw->vars;
3496         *len = wlc_hw->vars_size;
3497 }
3498
3499 void brcms_b_retrylimit_upd(struct wlc_hw_info *wlc_hw, u16 SRL, u16 LRL)
3500 {
3501         wlc_hw->SRL = SRL;
3502         wlc_hw->LRL = LRL;
3503
3504         /* write retry limit to SCR, shouldn't need to suspend */
3505         if (wlc_hw->up) {
3506                 W_REG(&wlc_hw->regs->objaddr,
3507                       OBJADDR_SCR_SEL | S_DOT11_SRC_LMT);
3508                 (void)R_REG(&wlc_hw->regs->objaddr);
3509                 W_REG(&wlc_hw->regs->objdata, wlc_hw->SRL);
3510                 W_REG(&wlc_hw->regs->objaddr,
3511                       OBJADDR_SCR_SEL | S_DOT11_LRC_LMT);
3512                 (void)R_REG(&wlc_hw->regs->objaddr);
3513                 W_REG(&wlc_hw->regs->objdata, wlc_hw->LRL);
3514         }
3515 }
3516
3517 void brcms_b_pllreq(struct wlc_hw_info *wlc_hw, bool set, mbool req_bit)
3518 {
3519         if (set) {
3520                 if (mboolisset(wlc_hw->pllreq, req_bit))
3521                         return;
3522
3523                 mboolset(wlc_hw->pllreq, req_bit);
3524
3525                 if (mboolisset(wlc_hw->pllreq, WLC_PLLREQ_FLIP)) {
3526                         if (!wlc_hw->sbclk) {
3527                                 brcms_b_xtal(wlc_hw, ON);
3528                         }
3529                 }
3530         } else {
3531                 if (!mboolisset(wlc_hw->pllreq, req_bit))
3532                         return;
3533
3534                 mboolclr(wlc_hw->pllreq, req_bit);
3535
3536                 if (mboolisset(wlc_hw->pllreq, WLC_PLLREQ_FLIP)) {
3537                         if (wlc_hw->sbclk) {
3538                                 brcms_b_xtal(wlc_hw, OFF);
3539                         }
3540                 }
3541         }
3542
3543         return;
3544 }
3545
3546 u16 brcms_b_rate_shm_offset(struct wlc_hw_info *wlc_hw, u8 rate)
3547 {
3548         u16 table_ptr;
3549         u8 phy_rate, index;
3550
3551         /* get the phy specific rate encoding for the PLCP SIGNAL field */
3552         /* XXX4321 fixup needed ? */
3553         if (IS_OFDM(rate))
3554                 table_ptr = M_RT_DIRMAP_A;
3555         else
3556                 table_ptr = M_RT_DIRMAP_B;
3557
3558         /* for a given rate, the LS-nibble of the PLCP SIGNAL field is
3559          * the index into the rate table.
3560          */
3561         phy_rate = rate_info[rate] & WLC_RATE_MASK;
3562         index = phy_rate & 0xf;
3563
3564         /* Find the SHM pointer to the rate table entry by looking in the
3565          * Direct-map Table
3566          */
3567         return 2 * brcms_b_read_shm(wlc_hw, table_ptr + (index * 2));
3568 }
3569
3570 void brcms_b_antsel_set(struct wlc_hw_info *wlc_hw, u32 antsel_avail)
3571 {
3572         wlc_hw->antsel_avail = antsel_avail;
3573 }