drivers/staging/brcm80211/brcmsmac/srom.c

   1 /*
   2  * Copyright (c) 2010 Broadcom Corporation
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
  11  * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
  13  * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
  14  * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #include <linux/kernel.h>
  18 #include <linux/string.h>
  19 #include <linux/io.h>
  20 #include <linux/etherdevice.h>
  21 #include <linux/crc8.h>
  22 #include <stdarg.h>
  23
  24 #include <chipcommon.h>
  25 #include <brcmu_utils.h>
  26 #include "nicpci.h"
  27 #include "aiutils.h"
  28 #include "otp.h"
  29 #include "srom.h"
  30
  31 #define SROM_OFFSET(sih) ((sih->ccrev > 31) ? \
  32         (((sih->cccaps & CC_CAP_SROM) == 0) ? NULL : \
  33          ((u8 *)curmap + PCI_16KB0_CCREGS_OFFSET + CC_SROM_OTP)) : \
  34         ((u8 *)curmap + PCI_BAR0_SPROM_OFFSET))
  35
  36 #if defined(BCMDBG)
  37 /* 500 ms after write enable/disable toggle */
  38 #define WRITE_ENABLE_DELAY      500
  39 /* 20 ms between each word write */
  40 #define WRITE_WORD_DELAY        20
  41 #endif
  42
  43 /*
  44  * SROM CRC8 polynomial value:
  45  *
  46  * x^8 + x^7 +x^6 + x^4 + x^2 + 1
  47  */
  48 #define SROM_CRC8_POLY          0xAB
  49
  50 /* Maximum srom: 6 Kilobits == 768 bytes */
  51 #define SROM_MAX                768
  52
  53 /* PCI fields */
  54 #define PCI_F0DEVID             48
  55
  56 #define SROM_WORDS              64
  57
  58 #define SROM_SSID               2
  59
  60 #define SROM_WL1LHMAXP          29
  61
  62 #define SROM_WL1LPAB0           30
  63 #define SROM_WL1LPAB1           31
  64 #define SROM_WL1LPAB2           32
  65
  66 #define SROM_WL1HPAB0           33
  67 #define SROM_WL1HPAB1           34
  68 #define SROM_WL1HPAB2           35
  69
  70 #define SROM_MACHI_IL0          36
  71 #define SROM_MACMID_IL0         37
  72 #define SROM_MACLO_IL0          38
  73 #define SROM_MACHI_ET1          42
  74 #define SROM_MACMID_ET1         43
  75 #define SROM_MACLO_ET1          44
  76 #define SROM3_MACHI             37
  77 #define SROM3_MACMID            38
  78 #define SROM3_MACLO             39
  79
  80 #define SROM_BXARSSI2G          40
  81 #define SROM_BXARSSI5G          41
  82
  83 #define SROM_TRI52G             42
  84 #define SROM_TRI5GHL            43
  85
  86 #define SROM_RXPO52G            45
  87
  88 #define SROM_AABREV             46
  89 /* Fields in AABREV */
  90 #define SROM_BR_MASK            0x00ff
  91 #define SROM_CC_MASK            0x0f00
  92 #define SROM_CC_SHIFT           8
  93 #define SROM_AA0_MASK           0x3000
  94 #define SROM_AA0_SHIFT          12
  95 #define SROM_AA1_MASK           0xc000
  96 #define SROM_AA1_SHIFT          14
  97
  98 #define SROM_WL0PAB0            47
  99 #define SROM_WL0PAB1            48
 100 #define SROM_WL0PAB2            49
 101
 102 #define SROM_LEDBH10            50
 103 #define SROM_LEDBH32            51
 104
 105 #define SROM_WL10MAXP           52
 106
 107 #define SROM_WL1PAB0            53
 108 #define SROM_WL1PAB1            54
 109 #define SROM_WL1PAB2            55
 110
 111 #define SROM_ITT                56
 112
 113 #define SROM_BFL                57
 114 #define SROM_BFL2               28
 115 #define SROM3_BFL2              61
 116
 117 #define SROM_AG10               58
 118
 119 #define SROM_CCODE              59
 120
 121 #define SROM_OPO                60
 122
 123 #define SROM3_LEDDC             62
 124
 125 #define SROM_CRCREV             63
 126
 127 /* SROM Rev 4: Reallocate the software part of the srom to accommodate
 128  * MIMO features. It assumes up to two PCIE functions and 440 bytes
 129  * of usable srom i.e. the usable storage in chips with OTP that
 130  * implements hardware redundancy.
 131  */
 132
 133 #define SROM4_WORDS             220
 134
 135 #define SROM4_SIGN              32
 136 #define SROM4_SIGNATURE         0x5372
 137
 138 #define SROM4_BREV              33
 139
 140 #define SROM4_BFL0              34
 141 #define SROM4_BFL1              35
 142 #define SROM4_BFL2              36
 143 #define SROM4_BFL3              37
 144 #define SROM5_BFL0              37
 145 #define SROM5_BFL1              38
 146 #define SROM5_BFL2              39
 147 #define SROM5_BFL3              40
 148
 149 #define SROM4_MACHI             38
 150 #define SROM4_MACMID            39
 151 #define SROM4_MACLO             40
 152 #define SROM5_MACHI             41
 153 #define SROM5_MACMID            42
 154 #define SROM5_MACLO             43
 155
 156 #define SROM4_CCODE             41
 157 #define SROM4_REGREV            42
 158 #define SROM5_CCODE             34
 159 #define SROM5_REGREV            35
 160
 161 #define SROM4_LEDBH10           43
 162 #define SROM4_LEDBH32           44
 163 #define SROM5_LEDBH10           59
 164 #define SROM5_LEDBH32           60
 165
 166 #define SROM4_LEDDC             45
 167 #define SROM5_LEDDC             45
 168
 169 #define SROM4_AA                46
 170
 171 #define SROM4_AG10              47
 172 #define SROM4_AG32              48
 173
 174 #define SROM4_TXPID2G           49
 175 #define SROM4_TXPID5G           51
 176 #define SROM4_TXPID5GL          53
 177 #define SROM4_TXPID5GH          55
 178
 179 #define SROM4_TXRXC             61
 180 #define SROM4_TXCHAIN_MASK      0x000f
 181 #define SROM4_TXCHAIN_SHIFT     0
 182 #define SROM4_RXCHAIN_MASK      0x00f0
 183 #define SROM4_RXCHAIN_SHIFT     4
 184 #define SROM4_SWITCH_MASK       0xff00
 185 #define SROM4_SWITCH_SHIFT      8
 186
 187 /* Per-path fields */
 188 #define MAX_PATH_SROM           4
 189 #define SROM4_PATH0             64
 190 #define SROM4_PATH1             87
 191 #define SROM4_PATH2             110
 192 #define SROM4_PATH3             133
 193
 194 #define SROM4_2G_ITT_MAXP       0
 195 #define SROM4_2G_PA             1
 196 #define SROM4_5G_ITT_MAXP       5
 197 #define SROM4_5GLH_MAXP         6
 198 #define SROM4_5G_PA             7
 199 #define SROM4_5GL_PA            11
 200 #define SROM4_5GH_PA            15
 201
 202 /* All the miriad power offsets */
 203 #define SROM4_2G_CCKPO          156
 204 #define SROM4_2G_OFDMPO         157
 205 #define SROM4_5G_OFDMPO         159
 206 #define SROM4_5GL_OFDMPO        161
 207 #define SROM4_5GH_OFDMPO        163
 208 #define SROM4_2G_MCSPO          165
 209 #define SROM4_5G_MCSPO          173
 210 #define SROM4_5GL_MCSPO         181
 211 #define SROM4_5GH_MCSPO         189
 212 #define SROM4_CDDPO             197
 213 #define SROM4_STBCPO            198
 214 #define SROM4_BW40PO            199
 215 #define SROM4_BWDUPPO           200
 216
 217 #define SROM4_CRCREV            219
 218
 219 /* SROM Rev 8: Make space for a 48word hardware header for PCIe rev >= 6.
 220  * This is acombined srom for both MIMO and SISO boards, usable in
 221  * the .130 4Kilobit OTP with hardware redundancy.
 222  */
 223 #define SROM8_BREV              65
 224
 225 #define SROM8_BFL0              66
 226 #define SROM8_BFL1              67
 227 #define SROM8_BFL2              68
 228 #define SROM8_BFL3              69
 229
 230 #define SROM8_MACHI             70
 231 #define SROM8_MACMID            71
 232 #define SROM8_MACLO             72
 233
 234 #define SROM8_CCODE             73
 235 #define SROM8_REGREV            74
 236
 237 #define SROM8_LEDBH10           75
 238 #define SROM8_LEDBH32           76
 239
 240 #define SROM8_LEDDC             77
 241
 242 #define SROM8_AA                78
 243
 244 #define SROM8_AG10              79
 245 #define SROM8_AG32              80
 246
 247 #define SROM8_TXRXC             81
 248
 249 #define SROM8_BXARSSI2G         82
 250 #define SROM8_BXARSSI5G         83
 251 #define SROM8_TRI52G            84
 252 #define SROM8_TRI5GHL           85
 253 #define SROM8_RXPO52G           86
 254
 255 #define SROM8_FEM2G             87
 256 #define SROM8_FEM5G             88
 257 #define SROM8_FEM_ANTSWLUT_MASK         0xf800
 258 #define SROM8_FEM_ANTSWLUT_SHIFT        11
 259 #define SROM8_FEM_TR_ISO_MASK           0x0700
 260 #define SROM8_FEM_TR_ISO_SHIFT          8
 261 #define SROM8_FEM_PDET_RANGE_MASK       0x00f8
 262 #define SROM8_FEM_PDET_RANGE_SHIFT      3
 263 #define SROM8_FEM_EXTPA_GAIN_MASK       0x0006
 264 #define SROM8_FEM_EXTPA_GAIN_SHIFT      1
 265 #define SROM8_FEM_TSSIPOS_MASK          0x0001
 266 #define SROM8_FEM_TSSIPOS_SHIFT         0
 267
 268 #define SROM8_THERMAL           89
 269
 270 /* Temp sense related entries */
 271 #define SROM8_MPWR_RAWTS                90
 272 #define SROM8_TS_SLP_OPT_CORRX  91
 273 /* FOC: freiquency offset correction, HWIQ: H/W IOCAL enable,
 274  * IQSWP: IQ CAL swap disable */
 275 #define SROM8_FOC_HWIQ_IQSWP    92
 276
 277 /* Temperature delta for PHY calibration */
 278 #define SROM8_PHYCAL_TEMPDELTA  93
 279
 280 /* Per-path offsets & fields */
 281 #define SROM8_PATH0             96
 282 #define SROM8_PATH1             112
 283 #define SROM8_PATH2             128
 284 #define SROM8_PATH3             144
 285
 286 #define SROM8_2G_ITT_MAXP       0
 287 #define SROM8_2G_PA             1
 288 #define SROM8_5G_ITT_MAXP       4
 289 #define SROM8_5GLH_MAXP         5
 290 #define SROM8_5G_PA             6
 291 #define SROM8_5GL_PA            9
 292 #define SROM8_5GH_PA            12
 293
 294 /* All the miriad power offsets */
 295 #define SROM8_2G_CCKPO          160
 296
 297 #define SROM8_2G_OFDMPO         161
 298 #define SROM8_5G_OFDMPO         163
 299 #define SROM8_5GL_OFDMPO        165
 300 #define SROM8_5GH_OFDMPO        167
 301
 302 #define SROM8_2G_MCSPO          169
 303 #define SROM8_5G_MCSPO          177
 304 #define SROM8_5GL_MCSPO         185
 305 #define SROM8_5GH_MCSPO         193
 306
 307 #define SROM8_CDDPO             201
 308 #define SROM8_STBCPO            202
 309 #define SROM8_BW40PO            203
 310 #define SROM8_BWDUPPO           204
 311
 312 /* SISO PA parameters are in the path0 spaces */
 313 #define SROM8_SISO              96
 314
 315 /* Legacy names for SISO PA paramters */
 316 #define SROM8_W0_ITTMAXP        (SROM8_SISO + SROM8_2G_ITT_MAXP)
 317 #define SROM8_W0_PAB0           (SROM8_SISO + SROM8_2G_PA)
 318 #define SROM8_W0_PAB1           (SROM8_SISO + SROM8_2G_PA + 1)
 319 #define SROM8_W0_PAB2           (SROM8_SISO + SROM8_2G_PA + 2)
 320 #define SROM8_W1_ITTMAXP        (SROM8_SISO + SROM8_5G_ITT_MAXP)
 321 #define SROM8_W1_MAXP_LCHC      (SROM8_SISO + SROM8_5GLH_MAXP)
 322 #define SROM8_W1_PAB0           (SROM8_SISO + SROM8_5G_PA)
 323 #define SROM8_W1_PAB1           (SROM8_SISO + SROM8_5G_PA + 1)
 324 #define SROM8_W1_PAB2           (SROM8_SISO + SROM8_5G_PA + 2)
 325 #define SROM8_W1_PAB0_LC        (SROM8_SISO + SROM8_5GL_PA)
 326 #define SROM8_W1_PAB1_LC        (SROM8_SISO + SROM8_5GL_PA + 1)
 327 #define SROM8_W1_PAB2_LC        (SROM8_SISO + SROM8_5GL_PA + 2)
 328 #define SROM8_W1_PAB0_HC        (SROM8_SISO + SROM8_5GH_PA)
 329 #define SROM8_W1_PAB1_HC        (SROM8_SISO + SROM8_5GH_PA + 1)
 330 #define SROM8_W1_PAB2_HC        (SROM8_SISO + SROM8_5GH_PA + 2)
 331
 332 /* SROM REV 9 */
 333 #define SROM9_2GPO_CCKBW20      160
 334 #define SROM9_2GPO_CCKBW20UL    161
 335 #define SROM9_2GPO_LOFDMBW20    162
 336 #define SROM9_2GPO_LOFDMBW20UL  164
 337
 338 #define SROM9_5GLPO_LOFDMBW20   166
 339 #define SROM9_5GLPO_LOFDMBW20UL 168
 340 #define SROM9_5GMPO_LOFDMBW20   170
 341 #define SROM9_5GMPO_LOFDMBW20UL 172
 342 #define SROM9_5GHPO_LOFDMBW20   174
 343 #define SROM9_5GHPO_LOFDMBW20UL 176
 344
 345 #define SROM9_2GPO_MCSBW20      178
 346 #define SROM9_2GPO_MCSBW20UL    180
 347 #define SROM9_2GPO_MCSBW40      182
 348
 349 #define SROM9_5GLPO_MCSBW20     184
 350 #define SROM9_5GLPO_MCSBW20UL   186
 351 #define SROM9_5GLPO_MCSBW40     188
 352 #define SROM9_5GMPO_MCSBW20     190
 353 #define SROM9_5GMPO_MCSBW20UL   192
 354 #define SROM9_5GMPO_MCSBW40     194
 355 #define SROM9_5GHPO_MCSBW20     196
 356 #define SROM9_5GHPO_MCSBW20UL   198
 357 #define SROM9_5GHPO_MCSBW40     200
 358
 359 #define SROM9_PO_MCS32          202
 360 #define SROM9_PO_LOFDM40DUP     203
 361
 362 /* SROM flags (see sromvar_t) */
 363
 364 /* value continues as described by the next entry */
 365 #define SRFL_MORE       1
 366 #define SRFL_NOFFS      2       /* value bits can't be all one's */
 367 #define SRFL_PRHEX      4       /* value is in hexdecimal format */
 368 #define SRFL_PRSIGN     8       /* value is in signed decimal format */
 369 #define SRFL_CCODE      0x10    /* value is in country code format */
 370 #define SRFL_ETHADDR    0x20    /* value is an Ethernet address */
 371 #define SRFL_LEDDC      0x40    /* value is an LED duty cycle */
 372 /* do not generate a nvram param, entry is for mfgc */
 373 #define SRFL_NOVAR      0x80
 374
 375 /* Max. nvram variable table size */
 376 #define MAXSZ_NVRAM_VARS        4096
 377
 378 struct brcms_sromvar {
 379         const char *name;
 380         u32 revmask;
 381         u32 flags;
 382         u16 off;
 383         u16 mask;
 384 };
 385
 386 struct brcms_varbuf {
 387         char *base;             /* pointer to buffer base */
 388         char *buf;              /* pointer to current position */
 389         unsigned int size;      /* current (residual) size in bytes */
 390 };
 391
 392 /*
 393  * Assumptions:
 394  * - Ethernet address spans across 3 consecutive words
 395  *
 396  * Table rules:
 397  * - Add multiple entries next to each other if a value spans across multiple
 398  *   words (even multiple fields in the same word) with each entry except the
 399  *   last having it's SRFL_MORE bit set.
 400  * - Ethernet address entry does not follow above rule and must not have
 401  *   SRFL_MORE bit set. Its SRFL_ETHADDR bit implies it takes multiple words.
 402  * - The last entry's name field must be NULL to indicate the end of the table.
 403  *   Other entries must have non-NULL name.
 404  */
 405 static const struct brcms_sromvar pci_sromvars[] = {
 406         {"devid", 0xffffff00, SRFL_PRHEX | SRFL_NOVAR, PCI_F0DEVID, 0xffff},
 407         {"boardrev", 0x0000000e, SRFL_PRHEX, SROM_AABREV, SROM_BR_MASK},
 408         {"boardrev", 0x000000f0, SRFL_PRHEX, SROM4_BREV, 0xffff},
 409         {"boardrev", 0xffffff00, SRFL_PRHEX, SROM8_BREV, 0xffff},
 410         {"boardflags", 0x00000002, SRFL_PRHEX, SROM_BFL, 0xffff},
 411         {"boardflags", 0x00000004, SRFL_PRHEX | SRFL_MORE, SROM_BFL, 0xffff},
 412         {"", 0, 0, SROM_BFL2, 0xffff},
 413         {"boardflags", 0x00000008, SRFL_PRHEX | SRFL_MORE, SROM_BFL, 0xffff},
 414         {"", 0, 0, SROM3_BFL2, 0xffff},
 415         {"boardflags", 0x00000010, SRFL_PRHEX | SRFL_MORE, SROM4_BFL0, 0xffff},
 416         {"", 0, 0, SROM4_BFL1, 0xffff},
 417         {"boardflags", 0x000000e0, SRFL_PRHEX | SRFL_MORE, SROM5_BFL0, 0xffff},
 418         {"", 0, 0, SROM5_BFL1, 0xffff},
 419         {"boardflags", 0xffffff00, SRFL_PRHEX | SRFL_MORE, SROM8_BFL0, 0xffff},
 420         {"", 0, 0, SROM8_BFL1, 0xffff},
 421         {"boardflags2", 0x00000010, SRFL_PRHEX | SRFL_MORE, SROM4_BFL2, 0xffff},
 422         {"", 0, 0, SROM4_BFL3, 0xffff},
 423         {"boardflags2", 0x000000e0, SRFL_PRHEX | SRFL_MORE, SROM5_BFL2, 0xffff},
 424         {"", 0, 0, SROM5_BFL3, 0xffff},
 425         {"boardflags2", 0xffffff00, SRFL_PRHEX | SRFL_MORE, SROM8_BFL2, 0xffff},
 426         {"", 0, 0, SROM8_BFL3, 0xffff},
 427         {"boardtype", 0xfffffffc, SRFL_PRHEX, SROM_SSID, 0xffff},
 428         {"boardnum", 0x00000006, 0, SROM_MACLO_IL0, 0xffff},
 429         {"boardnum", 0x00000008, 0, SROM3_MACLO, 0xffff},
 430         {"boardnum", 0x00000010, 0, SROM4_MACLO, 0xffff},
 431         {"boardnum", 0x000000e0, 0, SROM5_MACLO, 0xffff},
 432         {"boardnum", 0xffffff00, 0, SROM8_MACLO, 0xffff},
 433         {"cc", 0x00000002, 0, SROM_AABREV, SROM_CC_MASK},
 434         {"regrev", 0x00000008, 0, SROM_OPO, 0xff00},
 435         {"regrev", 0x00000010, 0, SROM4_REGREV, 0x00ff},
 436         {"regrev", 0x000000e0, 0, SROM5_REGREV, 0x00ff},
 437         {"regrev", 0xffffff00, 0, SROM8_REGREV, 0x00ff},
 438         {"ledbh0", 0x0000000e, SRFL_NOFFS, SROM_LEDBH10, 0x00ff},
 439         {"ledbh1", 0x0000000e, SRFL_NOFFS, SROM_LEDBH10, 0xff00},
 440         {"ledbh2", 0x0000000e, SRFL_NOFFS, SROM_LEDBH32, 0x00ff},
 441         {"ledbh3", 0x0000000e, SRFL_NOFFS, SROM_LEDBH32, 0xff00},
 442         {"ledbh0", 0x00000010, SRFL_NOFFS, SROM4_LEDBH10, 0x00ff},
 443         {"ledbh1", 0x00000010, SRFL_NOFFS, SROM4_LEDBH10, 0xff00},
 444         {"ledbh2", 0x00000010, SRFL_NOFFS, SROM4_LEDBH32, 0x00ff},
 445         {"ledbh3", 0x00000010, SRFL_NOFFS, SROM4_LEDBH32, 0xff00},
 446         {"ledbh0", 0x000000e0, SRFL_NOFFS, SROM5_LEDBH10, 0x00ff},
 447         {"ledbh1", 0x000000e0, SRFL_NOFFS, SROM5_LEDBH10, 0xff00},
 448         {"ledbh2", 0x000000e0, SRFL_NOFFS, SROM5_LEDBH32, 0x00ff},
 449         {"ledbh3", 0x000000e0, SRFL_NOFFS, SROM5_LEDBH32, 0xff00},
 450         {"ledbh0", 0xffffff00, SRFL_NOFFS, SROM8_LEDBH10, 0x00ff},
 451         {"ledbh1", 0xffffff00, SRFL_NOFFS, SROM8_LEDBH10, 0xff00},
 452         {"ledbh2", 0xffffff00, SRFL_NOFFS, SROM8_LEDBH32, 0x00ff},
 453         {"ledbh3", 0xffffff00, SRFL_NOFFS, SROM8_LEDBH32, 0xff00},
 454         {"pa0b0", 0x0000000e, SRFL_PRHEX, SROM_WL0PAB0, 0xffff},
 455         {"pa0b1", 0x0000000e, SRFL_PRHEX, SROM_WL0PAB1, 0xffff},
 456         {"pa0b2", 0x0000000e, SRFL_PRHEX, SROM_WL0PAB2, 0xffff},
 457         {"pa0itssit", 0x0000000e, 0, SROM_ITT, 0x00ff},
 458         {"pa0maxpwr", 0x0000000e, 0, SROM_WL10MAXP, 0x00ff},
 459         {"pa0b0", 0xffffff00, SRFL_PRHEX, SROM8_W0_PAB0, 0xffff},
 460         {"pa0b1", 0xffffff00, SRFL_PRHEX, SROM8_W0_PAB1, 0xffff},
 461         {"pa0b2", 0xffffff00, SRFL_PRHEX, SROM8_W0_PAB2, 0xffff},
 462         {"pa0itssit", 0xffffff00, 0, SROM8_W0_ITTMAXP, 0xff00},
 463         {"pa0maxpwr", 0xffffff00, 0, SROM8_W0_ITTMAXP, 0x00ff},
 464         {"opo", 0x0000000c, 0, SROM_OPO, 0x00ff},
 465         {"opo", 0xffffff00, 0, SROM8_2G_OFDMPO, 0x00ff},
 466         {"aa2g", 0x0000000e, 0, SROM_AABREV, SROM_AA0_MASK},
 467         {"aa2g", 0x000000f0, 0, SROM4_AA, 0x00ff},
 468         {"aa2g", 0xffffff00, 0, SROM8_AA, 0x00ff},
 469         {"aa5g", 0x0000000e, 0, SROM_AABREV, SROM_AA1_MASK},
 470         {"aa5g", 0x000000f0, 0, SROM4_AA, 0xff00},
 471         {"aa5g", 0xffffff00, 0, SROM8_AA, 0xff00},
 472         {"ag0", 0x0000000e, 0, SROM_AG10, 0x00ff},
 473         {"ag1", 0x0000000e, 0, SROM_AG10, 0xff00},
 474         {"ag0", 0x000000f0, 0, SROM4_AG10, 0x00ff},
 475         {"ag1", 0x000000f0, 0, SROM4_AG10, 0xff00},
 476         {"ag2", 0x000000f0, 0, SROM4_AG32, 0x00ff},
 477         {"ag3", 0x000000f0, 0, SROM4_AG32, 0xff00},
 478         {"ag0", 0xffffff00, 0, SROM8_AG10, 0x00ff},
 479         {"ag1", 0xffffff00, 0, SROM8_AG10, 0xff00},
 480         {"ag2", 0xffffff00, 0, SROM8_AG32, 0x00ff},
 481         {"ag3", 0xffffff00, 0, SROM8_AG32, 0xff00},
 482         {"pa1b0", 0x0000000e, SRFL_PRHEX, SROM_WL1PAB0, 0xffff},
 483         {"pa1b1", 0x0000000e, SRFL_PRHEX, SROM_WL1PAB1, 0xffff},
 484         {"pa1b2", 0x0000000e, SRFL_PRHEX, SROM_WL1PAB2, 0xffff},
 485         {"pa1lob0", 0x0000000c, SRFL_PRHEX, SROM_WL1LPAB0, 0xffff},
 486         {"pa1lob1", 0x0000000c, SRFL_PRHEX, SROM_WL1LPAB1, 0xffff},
 487         {"pa1lob2", 0x0000000c, SRFL_PRHEX, SROM_WL1LPAB2, 0xffff},
 488         {"pa1hib0", 0x0000000c, SRFL_PRHEX, SROM_WL1HPAB0, 0xffff},
 489         {"pa1hib1", 0x0000000c, SRFL_PRHEX, SROM_WL1HPAB1, 0xffff},
 490         {"pa1hib2", 0x0000000c, SRFL_PRHEX, SROM_WL1HPAB2, 0xffff},
 491         {"pa1itssit", 0x0000000e, 0, SROM_ITT, 0xff00},
 492         {"pa1maxpwr", 0x0000000e, 0, SROM_WL10MAXP, 0xff00},
 493         {"pa1lomaxpwr", 0x0000000c, 0, SROM_WL1LHMAXP, 0xff00},
 494         {"pa1himaxpwr", 0x0000000c, 0, SROM_WL1LHMAXP, 0x00ff},
 495         {"pa1b0", 0xffffff00, SRFL_PRHEX, SROM8_W1_PAB0, 0xffff},
 496         {"pa1b1", 0xffffff00, SRFL_PRHEX, SROM8_W1_PAB1, 0xffff},
 497         {"pa1b2", 0xffffff00, SRFL_PRHEX, SROM8_W1_PAB2, 0xffff},
 498         {"pa1lob0", 0xffffff00, SRFL_PRHEX, SROM8_W1_PAB0_LC, 0xffff},
 499         {"pa1lob1", 0xffffff00, SRFL_PRHEX, SROM8_W1_PAB1_LC, 0xffff},
 500         {"pa1lob2", 0xffffff00, SRFL_PRHEX, SROM8_W1_PAB2_LC, 0xffff},
 501         {"pa1hib0", 0xffffff00, SRFL_PRHEX, SROM8_W1_PAB0_HC, 0xffff},
 502         {"pa1hib1", 0xffffff00, SRFL_PRHEX, SROM8_W1_PAB1_HC, 0xffff},
 503         {"pa1hib2", 0xffffff00, SRFL_PRHEX, SROM8_W1_PAB2_HC, 0xffff},
 504         {"pa1itssit", 0xffffff00, 0, SROM8_W1_ITTMAXP, 0xff00},
 505         {"pa1maxpwr", 0xffffff00, 0, SROM8_W1_ITTMAXP, 0x00ff},
 506         {"pa1lomaxpwr", 0xffffff00, 0, SROM8_W1_MAXP_LCHC, 0xff00},
 507         {"pa1himaxpwr", 0xffffff00, 0, SROM8_W1_MAXP_LCHC, 0x00ff},
 508         {"bxa2g", 0x00000008, 0, SROM_BXARSSI2G, 0x1800},
 509         {"rssisav2g", 0x00000008, 0, SROM_BXARSSI2G, 0x0700},
 510         {"rssismc2g", 0x00000008, 0, SROM_BXARSSI2G, 0x00f0},
 511         {"rssismf2g", 0x00000008, 0, SROM_BXARSSI2G, 0x000f},
 512         {"bxa2g", 0xffffff00, 0, SROM8_BXARSSI2G, 0x1800},
 513         {"rssisav2g", 0xffffff00, 0, SROM8_BXARSSI2G, 0x0700},
 514         {"rssismc2g", 0xffffff00, 0, SROM8_BXARSSI2G, 0x00f0},
 515         {"rssismf2g", 0xffffff00, 0, SROM8_BXARSSI2G, 0x000f},
 516         {"bxa5g", 0x00000008, 0, SROM_BXARSSI5G, 0x1800},
 517         {"rssisav5g", 0x00000008, 0, SROM_BXARSSI5G, 0x0700},
 518         {"rssismc5g", 0x00000008, 0, SROM_BXARSSI5G, 0x00f0},
 519         {"rssismf5g", 0x00000008, 0, SROM_BXARSSI5G, 0x000f},
 520         {"bxa5g", 0xffffff00, 0, SROM8_BXARSSI5G, 0x1800},
 521         {"rssisav5g", 0xffffff00, 0, SROM8_BXARSSI5G, 0x0700},
 522         {"rssismc5g", 0xffffff00, 0, SROM8_BXARSSI5G, 0x00f0},
 523         {"rssismf5g", 0xffffff00, 0, SROM8_BXARSSI5G, 0x000f},
 524         {"tri2g", 0x00000008, 0, SROM_TRI52G, 0x00ff},
 525         {"tri5g", 0x00000008, 0, SROM_TRI52G, 0xff00},
 526         {"tri5gl", 0x00000008, 0, SROM_TRI5GHL, 0x00ff},
 527         {"tri5gh", 0x00000008, 0, SROM_TRI5GHL, 0xff00},
 528         {"tri2g", 0xffffff00, 0, SROM8_TRI52G, 0x00ff},
 529         {"tri5g", 0xffffff00, 0, SROM8_TRI52G, 0xff00},
 530         {"tri5gl", 0xffffff00, 0, SROM8_TRI5GHL, 0x00ff},
 531         {"tri5gh", 0xffffff00, 0, SROM8_TRI5GHL, 0xff00},
 532         {"rxpo2g", 0x00000008, SRFL_PRSIGN, SROM_RXPO52G, 0x00ff},
 533         {"rxpo5g", 0x00000008, SRFL_PRSIGN, SROM_RXPO52G, 0xff00},
 534         {"rxpo2g", 0xffffff00, SRFL_PRSIGN, SROM8_RXPO52G, 0x00ff},
 535         {"rxpo5g", 0xffffff00, SRFL_PRSIGN, SROM8_RXPO52G, 0xff00},
 536         {"txchain", 0x000000f0, SRFL_NOFFS, SROM4_TXRXC, SROM4_TXCHAIN_MASK},
 537         {"rxchain", 0x000000f0, SRFL_NOFFS, SROM4_TXRXC, SROM4_RXCHAIN_MASK},
 538         {"antswitch", 0x000000f0, SRFL_NOFFS, SROM4_TXRXC, SROM4_SWITCH_MASK},
 539         {"txchain", 0xffffff00, SRFL_NOFFS, SROM8_TXRXC, SROM4_TXCHAIN_MASK},
 540         {"rxchain", 0xffffff00, SRFL_NOFFS, SROM8_TXRXC, SROM4_RXCHAIN_MASK},
 541         {"antswitch", 0xffffff00, SRFL_NOFFS, SROM8_TXRXC, SROM4_SWITCH_MASK},
 542         {"tssipos2g", 0xffffff00, 0, SROM8_FEM2G, SROM8_FEM_TSSIPOS_MASK},
 543         {"extpagain2g", 0xffffff00, 0, SROM8_FEM2G, SROM8_FEM_EXTPA_GAIN_MASK},
 544         {"pdetrange2g", 0xffffff00, 0, SROM8_FEM2G, SROM8_FEM_PDET_RANGE_MASK},
 545         {"triso2g", 0xffffff00, 0, SROM8_FEM2G, SROM8_FEM_TR_ISO_MASK},
 546         {"antswctl2g", 0xffffff00, 0, SROM8_FEM2G, SROM8_FEM_ANTSWLUT_MASK},
 547         {"tssipos5g", 0xffffff00, 0, SROM8_FEM5G, SROM8_FEM_TSSIPOS_MASK},
 548         {"extpagain5g", 0xffffff00, 0, SROM8_FEM5G, SROM8_FEM_EXTPA_GAIN_MASK},
 549         {"pdetrange5g", 0xffffff00, 0, SROM8_FEM5G, SROM8_FEM_PDET_RANGE_MASK},
 550         {"triso5g", 0xffffff00, 0, SROM8_FEM5G, SROM8_FEM_TR_ISO_MASK},
 551         {"antswctl5g", 0xffffff00, 0, SROM8_FEM5G, SROM8_FEM_ANTSWLUT_MASK},
 552         {"tempthresh", 0xffffff00, 0, SROM8_THERMAL, 0xff00},
 553         {"tempoffset", 0xffffff00, 0, SROM8_THERMAL, 0x00ff},
 554         {"txpid2ga0", 0x000000f0, 0, SROM4_TXPID2G, 0x00ff},
 555         {"txpid2ga1", 0x000000f0, 0, SROM4_TXPID2G, 0xff00},
 556         {"txpid2ga2", 0x000000f0, 0, SROM4_TXPID2G + 1, 0x00ff},
 557         {"txpid2ga3", 0x000000f0, 0, SROM4_TXPID2G + 1, 0xff00},
 558         {"txpid5ga0", 0x000000f0, 0, SROM4_TXPID5G, 0x00ff},
 559         {"txpid5ga1", 0x000000f0, 0, SROM4_TXPID5G, 0xff00},
 560         {"txpid5ga2", 0x000000f0, 0, SROM4_TXPID5G + 1, 0x00ff},
 561         {"txpid5ga3", 0x000000f0, 0, SROM4_TXPID5G + 1, 0xff00},
 562         {"txpid5gla0", 0x000000f0, 0, SROM4_TXPID5GL, 0x00ff},
 563         {"txpid5gla1", 0x000000f0, 0, SROM4_TXPID5GL, 0xff00},
 564         {"txpid5gla2", 0x000000f0, 0, SROM4_TXPID5GL + 1, 0x00ff},
 565         {"txpid5gla3", 0x000000f0, 0, SROM4_TXPID5GL + 1, 0xff00},
 566         {"txpid5gha0", 0x000000f0, 0, SROM4_TXPID5GH, 0x00ff},
 567         {"txpid5gha1", 0x000000f0, 0, SROM4_TXPID5GH, 0xff00},
 568         {"txpid5gha2", 0x000000f0, 0, SROM4_TXPID5GH + 1, 0x00ff},
 569         {"txpid5gha3", 0x000000f0, 0, SROM4_TXPID5GH + 1, 0xff00},
 570
 571         {"ccode", 0x0000000f, SRFL_CCODE, SROM_CCODE, 0xffff},
 572         {"ccode", 0x00000010, SRFL_CCODE, SROM4_CCODE, 0xffff},
 573         {"ccode", 0x000000e0, SRFL_CCODE, SROM5_CCODE, 0xffff},
 574         {"ccode", 0xffffff00, SRFL_CCODE, SROM8_CCODE, 0xffff},
 575         {"macaddr", 0xffffff00, SRFL_ETHADDR, SROM8_MACHI, 0xffff},
 576         {"macaddr", 0x000000e0, SRFL_ETHADDR, SROM5_MACHI, 0xffff},
 577         {"macaddr", 0x00000010, SRFL_ETHADDR, SROM4_MACHI, 0xffff},
 578         {"macaddr", 0x00000008, SRFL_ETHADDR, SROM3_MACHI, 0xffff},
 579         {"il0macaddr", 0x00000007, SRFL_ETHADDR, SROM_MACHI_IL0, 0xffff},
 580         {"et1macaddr", 0x00000007, SRFL_ETHADDR, SROM_MACHI_ET1, 0xffff},
 581         {"leddc", 0xffffff00, SRFL_NOFFS | SRFL_LEDDC, SROM8_LEDDC, 0xffff},
 582         {"leddc", 0x000000e0, SRFL_NOFFS | SRFL_LEDDC, SROM5_LEDDC, 0xffff},
 583         {"leddc", 0x00000010, SRFL_NOFFS | SRFL_LEDDC, SROM4_LEDDC, 0xffff},
 584         {"leddc", 0x00000008, SRFL_NOFFS | SRFL_LEDDC, SROM3_LEDDC, 0xffff},
 585         {"rawtempsense", 0xffffff00, SRFL_PRHEX, SROM8_MPWR_RAWTS, 0x01ff},
 586         {"measpower", 0xffffff00, SRFL_PRHEX, SROM8_MPWR_RAWTS, 0xfe00},
 587         {"tempsense_slope", 0xffffff00, SRFL_PRHEX, SROM8_TS_SLP_OPT_CORRX,
 588          0x00ff},
 589         {"tempcorrx", 0xffffff00, SRFL_PRHEX, SROM8_TS_SLP_OPT_CORRX, 0xfc00},
 590         {"tempsense_option", 0xffffff00, SRFL_PRHEX, SROM8_TS_SLP_OPT_CORRX,
 591          0x0300},
 592         {"freqoffset_corr", 0xffffff00, SRFL_PRHEX, SROM8_FOC_HWIQ_IQSWP,
 593          0x000f},
 594         {"iqcal_swp_dis", 0xffffff00, SRFL_PRHEX, SROM8_FOC_HWIQ_IQSWP, 0x0010},
 595         {"hw_iqcal_en", 0xffffff00, SRFL_PRHEX, SROM8_FOC_HWIQ_IQSWP, 0x0020},
 596         {"phycal_tempdelta", 0xffffff00, 0, SROM8_PHYCAL_TEMPDELTA, 0x00ff},
 597
 598         {"cck2gpo", 0x000000f0, 0, SROM4_2G_CCKPO, 0xffff},
 599         {"cck2gpo", 0x00000100, 0, SROM8_2G_CCKPO, 0xffff},
 600         {"ofdm2gpo", 0x000000f0, SRFL_MORE, SROM4_2G_OFDMPO, 0xffff},
 601         {"", 0, 0, SROM4_2G_OFDMPO + 1, 0xffff},
 602         {"ofdm5gpo", 0x000000f0, SRFL_MORE, SROM4_5G_OFDMPO, 0xffff},
 603         {"", 0, 0, SROM4_5G_OFDMPO + 1, 0xffff},
 604         {"ofdm5glpo", 0x000000f0, SRFL_MORE, SROM4_5GL_OFDMPO, 0xffff},
 605         {"", 0, 0, SROM4_5GL_OFDMPO + 1, 0xffff},
 606         {"ofdm5ghpo", 0x000000f0, SRFL_MORE, SROM4_5GH_OFDMPO, 0xffff},
 607         {"", 0, 0, SROM4_5GH_OFDMPO + 1, 0xffff},
 608         {"ofdm2gpo", 0x00000100, SRFL_MORE, SROM8_2G_OFDMPO, 0xffff},
 609         {"", 0, 0, SROM8_2G_OFDMPO + 1, 0xffff},
 610         {"ofdm5gpo", 0x00000100, SRFL_MORE, SROM8_5G_OFDMPO, 0xffff},
 611         {"", 0, 0, SROM8_5G_OFDMPO + 1, 0xffff},
 612         {"ofdm5glpo", 0x00000100, SRFL_MORE, SROM8_5GL_OFDMPO, 0xffff},
 613         {"", 0, 0, SROM8_5GL_OFDMPO + 1, 0xffff},
 614         {"ofdm5ghpo", 0x00000100, SRFL_MORE, SROM8_5GH_OFDMPO, 0xffff},
 615         {"", 0, 0, SROM8_5GH_OFDMPO + 1, 0xffff},
 616         {"mcs2gpo0", 0x000000f0, 0, SROM4_2G_MCSPO, 0xffff},
 617         {"mcs2gpo1", 0x000000f0, 0, SROM4_2G_MCSPO + 1, 0xffff},
 618         {"mcs2gpo2", 0x000000f0, 0, SROM4_2G_MCSPO + 2, 0xffff},
 619         {"mcs2gpo3", 0x000000f0, 0, SROM4_2G_MCSPO + 3, 0xffff},
 620         {"mcs2gpo4", 0x000000f0, 0, SROM4_2G_MCSPO + 4, 0xffff},
 621         {"mcs2gpo5", 0x000000f0, 0, SROM4_2G_MCSPO + 5, 0xffff},
 622         {"mcs2gpo6", 0x000000f0, 0, SROM4_2G_MCSPO + 6, 0xffff},
 623         {"mcs2gpo7", 0x000000f0, 0, SROM4_2G_MCSPO + 7, 0xffff},
 624         {"mcs5gpo0", 0x000000f0, 0, SROM4_5G_MCSPO, 0xffff},
 625         {"mcs5gpo1", 0x000000f0, 0, SROM4_5G_MCSPO + 1, 0xffff},
 626         {"mcs5gpo2", 0x000000f0, 0, SROM4_5G_MCSPO + 2, 0xffff},
 627         {"mcs5gpo3", 0x000000f0, 0, SROM4_5G_MCSPO + 3, 0xffff},
 628         {"mcs5gpo4", 0x000000f0, 0, SROM4_5G_MCSPO + 4, 0xffff},
 629         {"mcs5gpo5", 0x000000f0, 0, SROM4_5G_MCSPO + 5, 0xffff},
 630         {"mcs5gpo6", 0x000000f0, 0, SROM4_5G_MCSPO + 6, 0xffff},
 631         {"mcs5gpo7", 0x000000f0, 0, SROM4_5G_MCSPO + 7, 0xffff},
 632         {"mcs5glpo0", 0x000000f0, 0, SROM4_5GL_MCSPO, 0xffff},
 633         {"mcs5glpo1", 0x000000f0, 0, SROM4_5GL_MCSPO + 1, 0xffff},
 634         {"mcs5glpo2", 0x000000f0, 0, SROM4_5GL_MCSPO + 2, 0xffff},
 635         {"mcs5glpo3", 0x000000f0, 0, SROM4_5GL_MCSPO + 3, 0xffff},
 636         {"mcs5glpo4", 0x000000f0, 0, SROM4_5GL_MCSPO + 4, 0xffff},
 637         {"mcs5glpo5", 0x000000f0, 0, SROM4_5GL_MCSPO + 5, 0xffff},
 638         {"mcs5glpo6", 0x000000f0, 0, SROM4_5GL_MCSPO + 6, 0xffff},
 639         {"mcs5glpo7", 0x000000f0, 0, SROM4_5GL_MCSPO + 7, 0xffff},
 640         {"mcs5ghpo0", 0x000000f0, 0, SROM4_5GH_MCSPO, 0xffff},
 641         {"mcs5ghpo1", 0x000000f0, 0, SROM4_5GH_MCSPO + 1, 0xffff},
 642         {"mcs5ghpo2", 0x000000f0, 0, SROM4_5GH_MCSPO + 2, 0xffff},
 643         {"mcs5ghpo3", 0x000000f0, 0, SROM4_5GH_MCSPO + 3, 0xffff},
 644         {"mcs5ghpo4", 0x000000f0, 0, SROM4_5GH_MCSPO + 4, 0xffff},
 645         {"mcs5ghpo5", 0x000000f0, 0, SROM4_5GH_MCSPO + 5, 0xffff},
 646         {"mcs5ghpo6", 0x000000f0, 0, SROM4_5GH_MCSPO + 6, 0xffff},
 647         {"mcs5ghpo7", 0x000000f0, 0, SROM4_5GH_MCSPO + 7, 0xffff},
 648         {"mcs2gpo0", 0x00000100, 0, SROM8_2G_MCSPO, 0xffff},
 649         {"mcs2gpo1", 0x00000100, 0, SROM8_2G_MCSPO + 1, 0xffff},
 650         {"mcs2gpo2", 0x00000100, 0, SROM8_2G_MCSPO + 2, 0xffff},
 651         {"mcs2gpo3", 0x00000100, 0, SROM8_2G_MCSPO + 3, 0xffff},
 652         {"mcs2gpo4", 0x00000100, 0, SROM8_2G_MCSPO + 4, 0xffff},
 653         {"mcs2gpo5", 0x00000100, 0, SROM8_2G_MCSPO + 5, 0xffff},
 654         {"mcs2gpo6", 0x00000100, 0, SROM8_2G_MCSPO + 6, 0xffff},
 655         {"mcs2gpo7", 0x00000100, 0, SROM8_2G_MCSPO + 7, 0xffff},
 656         {"mcs5gpo0", 0x00000100, 0, SROM8_5G_MCSPO, 0xffff},
 657         {"mcs5gpo1", 0x00000100, 0, SROM8_5G_MCSPO + 1, 0xffff},
 658         {"mcs5gpo2", 0x00000100, 0, SROM8_5G_MCSPO + 2, 0xffff},
 659         {"mcs5gpo3", 0x00000100, 0, SROM8_5G_MCSPO + 3, 0xffff},
 660         {"mcs5gpo4", 0x00000100, 0, SROM8_5G_MCSPO + 4, 0xffff},
 661         {"mcs5gpo5", 0x00000100, 0, SROM8_5G_MCSPO + 5, 0xffff},
 662         {"mcs5gpo6", 0x00000100, 0, SROM8_5G_MCSPO + 6, 0xffff},
 663         {"mcs5gpo7", 0x00000100, 0, SROM8_5G_MCSPO + 7, 0xffff},
 664         {"mcs5glpo0", 0x00000100, 0, SROM8_5GL_MCSPO, 0xffff},
 665         {"mcs5glpo1", 0x00000100, 0, SROM8_5GL_MCSPO + 1, 0xffff},
 666         {"mcs5glpo2", 0x00000100, 0, SROM8_5GL_MCSPO + 2, 0xffff},
 667         {"mcs5glpo3", 0x00000100, 0, SROM8_5GL_MCSPO + 3, 0xffff},
 668         {"mcs5glpo4", 0x00000100, 0, SROM8_5GL_MCSPO + 4, 0xffff},
 669         {"mcs5glpo5", 0x00000100, 0, SROM8_5GL_MCSPO + 5, 0xffff},
 670         {"mcs5glpo6", 0x00000100, 0, SROM8_5GL_MCSPO + 6, 0xffff},
 671         {"mcs5glpo7", 0x00000100, 0, SROM8_5GL_MCSPO + 7, 0xffff},
 672         {"mcs5ghpo0", 0x00000100, 0, SROM8_5GH_MCSPO, 0xffff},
 673         {"mcs5ghpo1", 0x00000100, 0, SROM8_5GH_MCSPO + 1, 0xffff},
 674         {"mcs5ghpo2", 0x00000100, 0, SROM8_5GH_MCSPO + 2, 0xffff},
 675         {"mcs5ghpo3", 0x00000100, 0, SROM8_5GH_MCSPO + 3, 0xffff},
 676         {"mcs5ghpo4", 0x00000100, 0, SROM8_5GH_MCSPO + 4, 0xffff},
 677         {"mcs5ghpo5", 0x00000100, 0, SROM8_5GH_MCSPO + 5, 0xffff},
 678         {"mcs5ghpo6", 0x00000100, 0, SROM8_5GH_MCSPO + 6, 0xffff},
 679         {"mcs5ghpo7", 0x00000100, 0, SROM8_5GH_MCSPO + 7, 0xffff},
 680         {"cddpo", 0x000000f0, 0, SROM4_CDDPO, 0xffff},
 681         {"stbcpo", 0x000000f0, 0, SROM4_STBCPO, 0xffff},
 682         {"bw40po", 0x000000f0, 0, SROM4_BW40PO, 0xffff},
 683         {"bwduppo", 0x000000f0, 0, SROM4_BWDUPPO, 0xffff},
 684         {"cddpo", 0x00000100, 0, SROM8_CDDPO, 0xffff},
 685         {"stbcpo", 0x00000100, 0, SROM8_STBCPO, 0xffff},
 686         {"bw40po", 0x00000100, 0, SROM8_BW40PO, 0xffff},
 687         {"bwduppo", 0x00000100, 0, SROM8_BWDUPPO, 0xffff},
 688
 689         /* power per rate from sromrev 9 */
 690         {"cckbw202gpo", 0xfffffe00, 0, SROM9_2GPO_CCKBW20, 0xffff},
 691         {"cckbw20ul2gpo", 0xfffffe00, 0, SROM9_2GPO_CCKBW20UL, 0xffff},
 692         {"legofdmbw202gpo", 0xfffffe00, SRFL_MORE, SROM9_2GPO_LOFDMBW20,
 693          0xffff},
 694         {"", 0, 0, SROM9_2GPO_LOFDMBW20 + 1, 0xffff},
 695         {"legofdmbw20ul2gpo", 0xfffffe00, SRFL_MORE, SROM9_2GPO_LOFDMBW20UL,
 696          0xffff},
 697         {"", 0, 0, SROM9_2GPO_LOFDMBW20UL + 1, 0xffff},
 698         {"legofdmbw205glpo", 0xfffffe00, SRFL_MORE, SROM9_5GLPO_LOFDMBW20,
 699          0xffff},
 700         {"", 0, 0, SROM9_5GLPO_LOFDMBW20 + 1, 0xffff},
 701         {"legofdmbw20ul5glpo", 0xfffffe00, SRFL_MORE, SROM9_5GLPO_LOFDMBW20UL,
 702          0xffff},
 703         {"", 0, 0, SROM9_5GLPO_LOFDMBW20UL + 1, 0xffff},
 704         {"legofdmbw205gmpo", 0xfffffe00, SRFL_MORE, SROM9_5GMPO_LOFDMBW20,
 705          0xffff},
 706         {"", 0, 0, SROM9_5GMPO_LOFDMBW20 + 1, 0xffff},
 707         {"legofdmbw20ul5gmpo", 0xfffffe00, SRFL_MORE, SROM9_5GMPO_LOFDMBW20UL,
 708          0xffff},
 709         {"", 0, 0, SROM9_5GMPO_LOFDMBW20UL + 1, 0xffff},
 710         {"legofdmbw205ghpo", 0xfffffe00, SRFL_MORE, SROM9_5GHPO_LOFDMBW20,
 711          0xffff},
 712         {"", 0, 0, SROM9_5GHPO_LOFDMBW20 + 1, 0xffff},
 713         {"legofdmbw20ul5ghpo", 0xfffffe00, SRFL_MORE, SROM9_5GHPO_LOFDMBW20UL,
 714          0xffff},
 715         {"", 0, 0, SROM9_5GHPO_LOFDMBW20UL + 1, 0xffff},
 716         {"mcsbw202gpo", 0xfffffe00, SRFL_MORE, SROM9_2GPO_MCSBW20, 0xffff},
 717         {"", 0, 0, SROM9_2GPO_MCSBW20 + 1, 0xffff},
 718         {"mcsbw20ul2gpo", 0xfffffe00, SRFL_MORE, SROM9_2GPO_MCSBW20UL, 0xffff},
 719         {"", 0, 0, SROM9_2GPO_MCSBW20UL + 1, 0xffff},
 720         {"mcsbw402gpo", 0xfffffe00, SRFL_MORE, SROM9_2GPO_MCSBW40, 0xffff},
 721         {"", 0, 0, SROM9_2GPO_MCSBW40 + 1, 0xffff},
 722         {"mcsbw205glpo", 0xfffffe00, SRFL_MORE, SROM9_5GLPO_MCSBW20, 0xffff},
 723         {"", 0, 0, SROM9_5GLPO_MCSBW20 + 1, 0xffff},
 724         {"mcsbw20ul5glpo", 0xfffffe00, SRFL_MORE, SROM9_5GLPO_MCSBW20UL,
 725          0xffff},
 726         {"", 0, 0, SROM9_5GLPO_MCSBW20UL + 1, 0xffff},
 727         {"mcsbw405glpo", 0xfffffe00, SRFL_MORE, SROM9_5GLPO_MCSBW40, 0xffff},
 728         {"", 0, 0, SROM9_5GLPO_MCSBW40 + 1, 0xffff},
 729         {"mcsbw205gmpo", 0xfffffe00, SRFL_MORE, SROM9_5GMPO_MCSBW20, 0xffff},
 730         {"", 0, 0, SROM9_5GMPO_MCSBW20 + 1, 0xffff},
 731         {"mcsbw20ul5gmpo", 0xfffffe00, SRFL_MORE, SROM9_5GMPO_MCSBW20UL,
 732          0xffff},
 733         {"", 0, 0, SROM9_5GMPO_MCSBW20UL + 1, 0xffff},
 734         {"mcsbw405gmpo", 0xfffffe00, SRFL_MORE, SROM9_5GMPO_MCSBW40, 0xffff},
 735         {"", 0, 0, SROM9_5GMPO_MCSBW40 + 1, 0xffff},
 736         {"mcsbw205ghpo", 0xfffffe00, SRFL_MORE, SROM9_5GHPO_MCSBW20, 0xffff},
 737         {"", 0, 0, SROM9_5GHPO_MCSBW20 + 1, 0xffff},
 738         {"mcsbw20ul5ghpo", 0xfffffe00, SRFL_MORE, SROM9_5GHPO_MCSBW20UL,
 739          0xffff},
 740         {"", 0, 0, SROM9_5GHPO_MCSBW20UL + 1, 0xffff},
 741         {"mcsbw405ghpo", 0xfffffe00, SRFL_MORE, SROM9_5GHPO_MCSBW40, 0xffff},
 742         {"", 0, 0, SROM9_5GHPO_MCSBW40 + 1, 0xffff},
 743         {"mcs32po", 0xfffffe00, 0, SROM9_PO_MCS32, 0xffff},
 744         {"legofdm40duppo", 0xfffffe00, 0, SROM9_PO_LOFDM40DUP, 0xffff},
 745
 746         {NULL, 0, 0, 0, 0}
 747 };
 748
 749 static const struct brcms_sromvar perpath_pci_sromvars[] = {
 750         {"maxp2ga", 0x000000f0, 0, SROM4_2G_ITT_MAXP, 0x00ff},
 751         {"itt2ga", 0x000000f0, 0, SROM4_2G_ITT_MAXP, 0xff00},
 752         {"itt5ga", 0x000000f0, 0, SROM4_5G_ITT_MAXP, 0xff00},
 753         {"pa2gw0a", 0x000000f0, SRFL_PRHEX, SROM4_2G_PA, 0xffff},
 754         {"pa2gw1a", 0x000000f0, SRFL_PRHEX, SROM4_2G_PA + 1, 0xffff},
 755         {"pa2gw2a", 0x000000f0, SRFL_PRHEX, SROM4_2G_PA + 2, 0xffff},
 756         {"pa2gw3a", 0x000000f0, SRFL_PRHEX, SROM4_2G_PA + 3, 0xffff},
 757         {"maxp5ga", 0x000000f0, 0, SROM4_5G_ITT_MAXP, 0x00ff},
 758         {"maxp5gha", 0x000000f0, 0, SROM4_5GLH_MAXP, 0x00ff},
 759         {"maxp5gla", 0x000000f0, 0, SROM4_5GLH_MAXP, 0xff00},
 760         {"pa5gw0a", 0x000000f0, SRFL_PRHEX, SROM4_5G_PA, 0xffff},
 761         {"pa5gw1a", 0x000000f0, SRFL_PRHEX, SROM4_5G_PA + 1, 0xffff},
 762         {"pa5gw2a", 0x000000f0, SRFL_PRHEX, SROM4_5G_PA + 2, 0xffff},
 763         {"pa5gw3a", 0x000000f0, SRFL_PRHEX, SROM4_5G_PA + 3, 0xffff},
 764         {"pa5glw0a", 0x000000f0, SRFL_PRHEX, SROM4_5GL_PA, 0xffff},
 765         {"pa5glw1a", 0x000000f0, SRFL_PRHEX, SROM4_5GL_PA + 1, 0xffff},
 766         {"pa5glw2a", 0x000000f0, SRFL_PRHEX, SROM4_5GL_PA + 2, 0xffff},
 767         {"pa5glw3a", 0x000000f0, SRFL_PRHEX, SROM4_5GL_PA + 3, 0xffff},
 768         {"pa5ghw0a", 0x000000f0, SRFL_PRHEX, SROM4_5GH_PA, 0xffff},
 769         {"pa5ghw1a", 0x000000f0, SRFL_PRHEX, SROM4_5GH_PA + 1, 0xffff},
 770         {"pa5ghw2a", 0x000000f0, SRFL_PRHEX, SROM4_5GH_PA + 2, 0xffff},
 771         {"pa5ghw3a", 0x000000f0, SRFL_PRHEX, SROM4_5GH_PA + 3, 0xffff},
 772         {"maxp2ga", 0xffffff00, 0, SROM8_2G_ITT_MAXP, 0x00ff},
 773         {"itt2ga", 0xffffff00, 0, SROM8_2G_ITT_MAXP, 0xff00},
 774         {"itt5ga", 0xffffff00, 0, SROM8_5G_ITT_MAXP, 0xff00},
 775         {"pa2gw0a", 0xffffff00, SRFL_PRHEX, SROM8_2G_PA, 0xffff},
 776         {"pa2gw1a", 0xffffff00, SRFL_PRHEX, SROM8_2G_PA + 1, 0xffff},
 777         {"pa2gw2a", 0xffffff00, SRFL_PRHEX, SROM8_2G_PA + 2, 0xffff},
 778         {"maxp5ga", 0xffffff00, 0, SROM8_5G_ITT_MAXP, 0x00ff},
 779         {"maxp5gha", 0xffffff00, 0, SROM8_5GLH_MAXP, 0x00ff},
 780         {"maxp5gla", 0xffffff00, 0, SROM8_5GLH_MAXP, 0xff00},
 781         {"pa5gw0a", 0xffffff00, SRFL_PRHEX, SROM8_5G_PA, 0xffff},
 782         {"pa5gw1a", 0xffffff00, SRFL_PRHEX, SROM8_5G_PA + 1, 0xffff},
 783         {"pa5gw2a", 0xffffff00, SRFL_PRHEX, SROM8_5G_PA + 2, 0xffff},
 784         {"pa5glw0a", 0xffffff00, SRFL_PRHEX, SROM8_5GL_PA, 0xffff},
 785         {"pa5glw1a", 0xffffff00, SRFL_PRHEX, SROM8_5GL_PA + 1, 0xffff},
 786         {"pa5glw2a", 0xffffff00, SRFL_PRHEX, SROM8_5GL_PA + 2, 0xffff},
 787         {"pa5ghw0a", 0xffffff00, SRFL_PRHEX, SROM8_5GH_PA, 0xffff},
 788         {"pa5ghw1a", 0xffffff00, SRFL_PRHEX, SROM8_5GH_PA + 1, 0xffff},
 789         {"pa5ghw2a", 0xffffff00, SRFL_PRHEX, SROM8_5GH_PA + 2, 0xffff},
 790         {NULL, 0, 0, 0, 0}
 791 };
 792
 793 static u8 srom_crc8_table[CRC8_TABLE_SIZE];
 794
 795 static void _initvars_srom_pci(u8 sromrev, u16 *srom, uint off,
 796                                struct brcms_varbuf *b);
 797 static int initvars_srom_pci(struct si_pub *sih, void *curmap, char **vars,
 798                              uint *count);
 799 static int sprom_read_pci(struct si_pub *sih, u16 *sprom,
 800                           uint wordoff, u16 *buf, uint nwords, bool check_crc);
 801 #if defined(BCMNVRAMR)
 802 static int otp_read_pci(struct si_pub *sih, u16 *buf, uint bufsz);
 803 #endif
 804
 805 static int initvars_table(char *start, char *end,
 806                           char **vars, uint *count);
 807
 808 /* Initialization of varbuf structure */
 809 static void varbuf_init(struct brcms_varbuf *b, char *buf, uint size)
 810 {
 811         b->size = size;
 812         b->base = b->buf = buf;
 813 }
 814
 815 /* append a null terminated var=value string */
 816 static int varbuf_append(struct brcms_varbuf *b, const char *fmt, ...)
 817 {
 818         va_list ap;
 819         int r;
 820         size_t len;
 821         char *s;
 822
 823         if (b->size < 2)
 824                 return 0;
 825
 826         va_start(ap, fmt);
 827         r = vsnprintf(b->buf, b->size, fmt, ap);
 828         va_end(ap);
 829
 830         /*
 831          * C99 snprintf behavior returns r >= size on overflow,
 832          * others return -1 on overflow. All return -1 on format error.
 833          * We need to leave room for 2 null terminations, one for the current
 834          * var string, and one for final null of the var table. So check that
 835          * the strlen written, r, leaves room for 2 chars.
 836          */
 837         if ((r == -1) || (r > (int)(b->size - 2))) {
 838                 b->size = 0;
 839                 return 0;
 840         }
 841
 842         /* Remove any earlier occurrence of the same variable */
 843         s = strchr(b->buf, '=');
 844         if (s != NULL) {
 845                 len = (size_t) (s - b->buf);
 846                 for (s = b->base; s < b->buf;) {
 847                         if ((memcmp(s, b->buf, len) == 0) && s[len] == '=') {
 848                                 len = strlen(s) + 1;
 849                                 memmove(s, (s + len),
 850                                         ((b->buf + r + 1) - (s + len)));
 851                                 b->buf -= len;
 852                                 b->size += (unsigned int)len;
 853                                 break;
 854                         }
 855
 856                         while (*s++)
 857                                 ;
 858                 }
 859         }
 860
 861         /* skip over this string's null termination */
 862         r++;
 863         b->size -= r;
 864         b->buf += r;
 865
 866         return r;
 867 }
 868
 869 /*
 870  * Initialize local vars from the right source for this platform.
 871  * Return 0 on success, nonzero on error.
 872  */
 873 int srom_var_init(struct si_pub *sih, void *curmap, char **vars, uint *count)
 874 {
 875         uint len;
 876
 877         len = 0;
 878
 879         if (vars == NULL || count == NULL)
 880                 return 0;
 881
 882         *vars = NULL;
 883         *count = 0;
 884
 885         if (curmap != NULL)
 886                 return initvars_srom_pci(sih, curmap, vars, count);
 887
 888         return -EINVAL;
 889 }
 890
 891 static inline void ltoh16_buf(u16 *buf, unsigned int size)
 892 {
 893         size /= 2;
 894         while (size--)
 895                 *(buf + size) = le16_to_cpu(*(buf + size));
 896 }
 897
 898 static inline void htol16_buf(u16 *buf, unsigned int size)
 899 {
 900         size /= 2;
 901         while (size--)
 902                 *(buf + size) = cpu_to_le16(*(buf + size));
 903 }
 904
 905 /*
 906  * Read in and validate sprom.
 907  * Return 0 on success, nonzero on error.
 908  */
 909 static int
 910 sprom_read_pci(struct si_pub *sih, u16 *sprom, uint wordoff,
 911                u16 *buf, uint nwords, bool check_crc)
 912 {
 913         int err = 0;
 914         uint i;
 915
 916         /* read the sprom */
 917         for (i = 0; i < nwords; i++)
 918                 buf[i] = R_REG(&sprom[wordoff + i]);
 919
 920         if (check_crc) {
 921
 922                 if (buf[0] == 0xffff)
 923                         /*
 924                          * The hardware thinks that an srom that starts with
 925                          * 0xffff is blank, regardless of the rest of the
 926                          * content, so declare it bad.
 927                          */
 928                         return -ENODATA;
 929
 930                 /* fixup the endianness so crc8 will pass */
 931                 htol16_buf(buf, nwords * 2);
 932                 if (crc8(srom_crc8_table, (u8 *) buf, nwords * 2,
 933                          CRC8_INIT_VALUE) != CRC8_GOOD_VALUE(srom_crc8_table))
 934                         /* DBG only pci always read srom4 first, then srom8/9 */
 935                         err = -EIO;
 936
 937                 /* now correct the endianness of the byte array */
 938                 ltoh16_buf(buf, nwords * 2);
 939         }
 940         return err;
 941 }
 942
 943 #if defined(BCMNVRAMR)
 944 static int otp_read_pci(struct si_pub *sih, u16 *buf, uint bufsz)
 945 {
 946         u8 *otp;
 947         uint sz = OTP_SZ_MAX / 2;       /* size in words */
 948         int err = 0;
 949
 950         otp = kzalloc(OTP_SZ_MAX, GFP_ATOMIC);
 951         if (otp == NULL)
 952                 return -ENOMEM;
 953
 954         err = otp_read_region(sih, OTP_HW_RGN, (u16 *) otp, &sz);
 955
 956         memcpy(buf, otp, bufsz);
 957
 958         kfree(otp);
 959
 960         /* Check CRC */
 961         if (buf[0] == 0xffff)
 962                 /* The hardware thinks that an srom that starts with 0xffff
 963                  * is blank, regardless of the rest of the content, so declare
 964                  * it bad.
 965                  */
 966                 return -ENODATA;
 967
 968         /* fixup the endianness so crc8 will pass */
 969         htol16_buf(buf, bufsz);
 970         if (crc8(srom_crc8_table, (u8 *) buf, SROM4_WORDS * 2,
 971                  CRC8_INIT_VALUE) != CRC8_GOOD_VALUE(srom_crc8_table))
 972                 err = -EIO;
 973
 974         /* now correct the endianness of the byte array */
 975         ltoh16_buf(buf, bufsz);
 976
 977         return err;
 978 }
 979 #endif                          /* defined(BCMNVRAMR) */
 980 /*
 981 * Create variable table from memory.
 982 * Return 0 on success, nonzero on error.
 983 */
 984 static int initvars_table(char *start, char *end,
 985                           char **vars, uint *count)
 986 {
 987         int c = (int)(end - start);
 988
 989         /* do it only when there is more than just the null string */
 990         if (c > 1) {
 991                 char *vp = kmalloc(c, GFP_ATOMIC);
 992                 if (!vp)
 993                         return -ENOMEM;
 994                 memcpy(vp, start, c);
 995                 *vars = vp;
 996                 *count = c;
 997         } else {
 998                 *vars = NULL;
 999                 *count = 0;
1000         }
1001
1002         return 0;
1003 }
1004
1005 /* Parse SROM and create name=value pairs. 'srom' points to
1006  * the SROM word array. 'off' specifies the offset of the
1007  * first word 'srom' points to, which should be either 0 or
1008  * SROM3_SWRG_OFF (full SROM or software region).
1009  */
1010
1011 static uint mask_shift(u16 mask)
1012 {
1013         uint i;
1014         for (i = 0; i < (sizeof(mask) << 3); i++) {
1015                 if (mask & (1 << i))
1016                         return i;
1017         }
1018         return 0;
1019 }
1020
1021 static uint mask_width(u16 mask)
1022 {
1023         int i;
1024         for (i = (sizeof(mask) << 3) - 1; i >= 0; i--) {
1025                 if (mask & (1 << i))
1026                         return (uint) (i - mask_shift(mask) + 1);
1027         }
1028         return 0;
1029 }
1030
1031 static void
1032 _initvars_srom_pci(u8 sromrev, u16 *srom, uint off, struct brcms_varbuf *b)
1033 {
1034         u16 w;
1035         u32 val;
1036         const struct brcms_sromvar *srv;
1037         uint width;
1038         uint flags;
1039         u32 sr = (1 << sromrev);
1040
1041         varbuf_append(b, "sromrev=%d", sromrev);
1042
1043         for (srv = pci_sromvars; srv->name != NULL; srv++) {
1044                 const char *name;
1045
1046                 if ((srv->revmask & sr) == 0)
1047                         continue;
1048
1049                 if (srv->off < off)
1050                         continue;
1051
1052                 flags = srv->flags;
1053                 name = srv->name;
1054
1055                 /* This entry is for mfgc only. Don't generate param for it, */
1056                 if (flags & SRFL_NOVAR)
1057                         continue;
1058
1059                 if (flags & SRFL_ETHADDR) {
1060                         u8 ea[ETH_ALEN];
1061
1062                         ea[0] = (srom[srv->off - off] >> 8) & 0xff;
1063                         ea[1] = srom[srv->off - off] & 0xff;
1064                         ea[2] = (srom[srv->off + 1 - off] >> 8) & 0xff;
1065                         ea[3] = srom[srv->off + 1 - off] & 0xff;
1066                         ea[4] = (srom[srv->off + 2 - off] >> 8) & 0xff;
1067                         ea[5] = srom[srv->off + 2 - off] & 0xff;
1068
1069                         varbuf_append(b, "%s=%pM", name, ea);
1070                 } else {
1071                         w = srom[srv->off - off];
1072                         val = (w & srv->mask) >> mask_shift(srv->mask);
1073                         width = mask_width(srv->mask);
1074
1075                         while (srv->flags & SRFL_MORE) {
1076                                 srv++;
1077                                 if (srv->off == 0 || srv->off < off)
1078                                         continue;
1079
1080                                 w = srom[srv->off - off];
1081                                 val +=
1082                                     ((w & srv->mask) >> mask_shift(srv->
1083                                                                    mask)) <<
1084                                     width;
1085                                 width += mask_width(srv->mask);
1086                         }
1087
1088                         if ((flags & SRFL_NOFFS)
1089                             && ((int)val == (1 << width) - 1))
1090                                 continue;
1091
1092                         if (flags & SRFL_CCODE) {
1093                                 if (val == 0)
1094                                         varbuf_append(b, "ccode=");
1095                                 else
1096                                         varbuf_append(b, "ccode=%c%c",
1097                                                       (val >> 8), (val & 0xff));
1098                         }
1099                         /* LED Powersave duty cycle has to be scaled:
1100                          *(oncount >> 24) (offcount >> 8)
1101                          */
1102                         else if (flags & SRFL_LEDDC) {
1103                                 u32 w32 = /* oncount */
1104                                           (((val >> 8) & 0xff) << 24) |
1105                                           /* offcount */
1106                                           (((val & 0xff)) << 8);
1107                                 varbuf_append(b, "leddc=%d", w32);
1108                         } else if (flags & SRFL_PRHEX)
1109                                 varbuf_append(b, "%s=0x%x", name, val);
1110                         else if ((flags & SRFL_PRSIGN)
1111                                  && (val & (1 << (width - 1))))
1112                                 varbuf_append(b, "%s=%d", name,
1113                                               (int)(val | (~0 << width)));
1114                         else
1115                                 varbuf_append(b, "%s=%u", name, val);
1116                 }
1117         }
1118
1119         if (sromrev >= 4) {
1120                 /* Do per-path variables */
1121                 uint p, pb, psz;
1122
1123                 if (sromrev >= 8) {
1124                         pb = SROM8_PATH0;
1125                         psz = SROM8_PATH1 - SROM8_PATH0;
1126                 } else {
1127                         pb = SROM4_PATH0;
1128                         psz = SROM4_PATH1 - SROM4_PATH0;
1129                 }
1130
1131                 for (p = 0; p < MAX_PATH_SROM; p++) {
1132                         for (srv = perpath_pci_sromvars; srv->name != NULL;
1133                              srv++) {
1134                                 if ((srv->revmask & sr) == 0)
1135                                         continue;
1136
1137                                 if (pb + srv->off < off)
1138                                         continue;
1139
1140                                 if (srv->flags & SRFL_NOVAR)
1141                                         continue;
1142
1143                                 w = srom[pb + srv->off - off];
1144                                 val = (w & srv->mask) >> mask_shift(srv->mask);
1145                                 width = mask_width(srv->mask);
1146
1147                                 /* Cheating: no per-path var is more than
1148                                  * 1 word */
1149                                 if ((srv->flags & SRFL_NOFFS)
1150                                     && ((int)val == (1 << width) - 1))
1151                                         continue;
1152
1153                                 if (srv->flags & SRFL_PRHEX)
1154                                         varbuf_append(b, "%s%d=0x%x", srv->name,
1155                                                       p, val);
1156                                 else
1157                                         varbuf_append(b, "%s%d=%d", srv->name,
1158                                                       p, val);
1159                         }
1160                         pb += psz;
1161                 }
1162         }
1163 }
1164
1165 /*
1166  * Initialize nonvolatile variable table from sprom.
1167  * Return 0 on success, nonzero on error.
1168  */
1169 static int initvars_srom_pci(struct si_pub *sih, void *curmap, char **vars,
1170                              uint *count)
1171 {
1172         u16 *srom, *sromwindow;
1173         u8 sromrev = 0;
1174         u32 sr;
1175         struct brcms_varbuf b;
1176         char *vp, *base = NULL;
1177         int err = 0;
1178
1179         /*
1180          * Apply CRC over SROM content regardless SROM is present or not.
1181          */
1182         srom = kmalloc(SROM_MAX, GFP_ATOMIC);
1183         if (!srom)
1184                 return -ENOMEM;
1185
1186         sromwindow = (u16 *) SROM_OFFSET(sih);
1187
1188         crc8_populate_lsb(srom_crc8_table, SROM_CRC8_POLY);
1189         if (ai_is_sprom_available(sih)) {
1190                 err = sprom_read_pci(sih, sromwindow, 0, srom, SROM_WORDS,
1191                                      true);
1192
1193                 if ((srom[SROM4_SIGN] == SROM4_SIGNATURE) ||
1194                     (((sih->buscoretype == PCIE_CORE_ID)
1195                       && (sih->buscorerev >= 6))
1196                      || ((sih->buscoretype == PCI_CORE_ID)
1197                          && (sih->buscorerev >= 0xe)))) {
1198                         /* sromrev >= 4, read more */
1199                         err = sprom_read_pci(sih, sromwindow, 0, srom,
1200                                              SROM4_WORDS, true);
1201                         sromrev = srom[SROM4_CRCREV] & 0xff;
1202                 } else if (err == 0) {
1203                         /* srom is good and is rev < 4 */
1204                         /* top word of sprom contains version and crc8 */
1205                         sromrev = srom[SROM_CRCREV] & 0xff;
1206                         /* bcm4401 sroms misprogrammed */
1207                         if (sromrev == 0x10)
1208                                 sromrev = 1;
1209                 }
1210         }
1211 #if defined(BCMNVRAMR)
1212         /* Use OTP if SPROM not available */
1213         else {
1214                 err = otp_read_pci(sih, srom, SROM_MAX);
1215                 if (err == 0)
1216                         /* OTP only contain SROM rev8/rev9 for now */
1217                         sromrev = srom[SROM4_CRCREV] & 0xff;
1218         }
1219 #else
1220         else
1221                 err = -ENODEV;
1222 #endif
1223
1224         if (!err) {
1225                 /* Bitmask for the sromrev */
1226                 sr = 1 << sromrev;
1227
1228                 /*
1229                  * srom version check: Current valid versions: 1, 2, 3, 4, 5, 8,
1230                  * 9
1231                  */
1232                 if ((sr & 0x33e) == 0) {
1233                         err = -EINVAL;
1234                         goto errout;
1235                 }
1236
1237                 base = kmalloc(MAXSZ_NVRAM_VARS, GFP_ATOMIC);
1238                 if (!base) {
1239                         err = -ENOMEM;
1240                         goto errout;
1241                 }
1242
1243                 varbuf_init(&b, base, MAXSZ_NVRAM_VARS);
1244
1245                 /* parse SROM into name=value pairs. */
1246                 _initvars_srom_pci(sromrev, srom, 0, &b);
1247
1248                 /* final nullbyte terminator */
1249                 vp = b.buf;
1250                 *vp++ = '\0';
1251
1252                 err = initvars_table(base, vp, vars, count);
1253                 kfree(base);
1254         }
1255
1256 errout:
1257         kfree(srom);
1258         return err;
1259 }