drivers/staging/comedi/drivers/addi-data/hwdrv_apci1500.c

   1 /*
   2  * Copyright (C) 2004,2005  ADDI-DATA GmbH for the source code of this module.
   3  *
   4  *      ADDI-DATA GmbH
   5  *      Dieselstrasse 3
   6  *      D-77833 Ottersweier
   7  *      Tel: +19(0)7223/9493-0
   8  *      Fax: +49(0)7223/9493-92
   9  *      http://www.addi-data.com
  10  *      info@addi-data.com
  11  *
  12  * This program is free software; you can redistribute it and/or modify it under
  13  * the terms of the GNU General Public License as published by the Free Software
  14  * Foundation; either version 2 of the License, or (at your option) any later
  15  * version.
  16  *
  17  * This program is distributed in the hope that it will be useful, but WITHOUT
  18  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
  19  * FOR A PARTICULAR PURPOSE. See the GNU General Public License for more
  20  * details.
  21  *
  22  */
  23
  24 /* Card Specific information */
  25 #define APCI1500_ADDRESS_RANGE          4
  26
  27 /* DIGITAL INPUT-OUTPUT DEFINE */
  28
  29 #define APCI1500_DIGITAL_OP             2
  30 #define APCI1500_DIGITAL_IP             0
  31 #define APCI1500_AND                    2
  32 #define APCI1500_OR                     4
  33 #define APCI1500_OR_PRIORITY            6
  34 #define APCI1500_CLK_SELECT             0
  35 #define COUNTER1                        0
  36 #define COUNTER2                        1
  37 #define COUNTER3                        2
  38 #define APCI1500_COUNTER                0x20
  39 #define APCI1500_TIMER                  0
  40 #define APCI1500_WATCHDOG               0
  41 #define APCI1500_SINGLE                 0
  42 #define APCI1500_CONTINUOUS             0x80
  43 #define APCI1500_DISABLE                0
  44 #define APCI1500_ENABLE                 1
  45 #define APCI1500_SOFTWARE_TRIGGER       0x4
  46 #define APCI1500_HARDWARE_TRIGGER       0x10
  47 #define APCI1500_SOFTWARE_GATE          0
  48 #define APCI1500_HARDWARE_GATE          0x8
  49 #define START                           0
  50 #define STOP                            1
  51 #define TRIGGER                         2
  52
  53 /*
  54  * Z8536 CIO Internal Address
  55  */
  56 enum {
  57         APCI1500_RW_MASTER_INTERRUPT_CONTROL,
  58         APCI1500_RW_MASTER_CONFIGURATION_CONTROL,
  59         APCI1500_RW_PORT_A_INTERRUPT_CONTROL,
  60         APCI1500_RW_PORT_B_INTERRUPT_CONTROL,
  61         APCI1500_RW_TIMER_COUNTER_INTERRUPT_VECTOR,
  62         APCI1500_RW_PORT_C_DATA_PCITCH_POLARITY,
  63         APCI1500_RW_PORT_C_DATA_DIRECTION,
  64         APCI1500_RW_PORT_C_SPECIAL_IO_CONTROL,
  65
  66         APCI1500_RW_PORT_A_COMMAND_AND_STATUS,
  67         APCI1500_RW_PORT_B_COMMAND_AND_STATUS,
  68         APCI1500_RW_CPT_TMR1_CMD_STATUS,
  69         APCI1500_RW_CPT_TMR2_CMD_STATUS,
  70         APCI1500_RW_CPT_TMR3_CMD_STATUS,
  71         APCI1500_RW_PORT_A_DATA,
  72         APCI1500_RW_PORT_B_DATA,
  73         APCI1500_RW_PORT_C_DATA,
  74
  75         APCI1500_R_CPT_TMR1_VALUE_HIGH,
  76         APCI1500_R_CPT_TMR1_VALUE_LOW,
  77         APCI1500_R_CPT_TMR2_VALUE_HIGH,
  78         APCI1500_R_CPT_TMR2_VALUE_LOW,
  79         APCI1500_R_CPT_TMR3_VALUE_HIGH,
  80         APCI1500_R_CPT_TMR3_VALUE_LOW,
  81         APCI1500_RW_CPT_TMR1_TIME_CST_HIGH,
  82         APCI1500_RW_CPT_TMR1_TIME_CST_LOW,
  83         APCI1500_RW_CPT_TMR2_TIME_CST_HIGH,
  84         APCI1500_RW_CPT_TMR2_TIME_CST_LOW,
  85         APCI1500_RW_CPT_TMR3_TIME_CST_HIGH,
  86         APCI1500_RW_CPT_TMR3_TIME_CST_LOW,
  87         APCI1500_RW_CPT_TMR1_MODE_SPECIFICATION,
  88         APCI1500_RW_CPT_TMR2_MODE_SPECIFICATION,
  89         APCI1500_RW_CPT_TMR3_MODE_SPECIFICATION,
  90         APCI1500_R_CURRENT_VECTOR,
  91
  92         APCI1500_RW_PORT_A_SPECIFICATION,
  93         APCI1500_RW_PORT_A_HANDSHAKE_SPECIFICATION,
  94         APCI1500_RW_PORT_A_DATA_PCITCH_POLARITY,
  95         APCI1500_RW_PORT_A_DATA_DIRECTION,
  96         APCI1500_RW_PORT_A_SPECIAL_IO_CONTROL,
  97         APCI1500_RW_PORT_A_PATTERN_POLARITY,
  98         APCI1500_RW_PORT_A_PATTERN_TRANSITION,
  99         APCI1500_RW_PORT_A_PATTERN_MASK,
 100
 101         APCI1500_RW_PORT_B_SPECIFICATION,
 102         APCI1500_RW_PORT_B_HANDSHAKE_SPECIFICATION,
 103         APCI1500_RW_PORT_B_DATA_PCITCH_POLARITY,
 104         APCI1500_RW_PORT_B_DATA_DIRECTION,
 105         APCI1500_RW_PORT_B_SPECIAL_IO_CONTROL,
 106         APCI1500_RW_PORT_B_PATTERN_POLARITY,
 107         APCI1500_RW_PORT_B_PATTERN_TRANSITION,
 108         APCI1500_RW_PORT_B_PATTERN_MASK
 109 };
 110
 111 static int i_TimerCounter1Init;
 112 static int i_TimerCounter2Init;
 113 static int i_WatchdogCounter3Init;
 114 static int i_Event1Status, i_Event2Status;
 115 static int i_TimerCounterWatchdogInterrupt;
 116 static int i_Logic, i_CounterLogic;
 117 static int i_InterruptMask;
 118 static int i_InputChannel;
 119 static int i_TimerCounter1Enabled, i_TimerCounter2Enabled,
 120            i_WatchdogCounter3Enabled;
 121
 122 static unsigned int z8536_read(struct comedi_device *dev, unsigned int reg)
 123 {
 124         struct apci1500_private *devpriv = dev->private;
 125         unsigned long flags;
 126         unsigned int val;
 127
 128         spin_lock_irqsave(&dev->spinlock, flags);
 129         outb(reg, devpriv->iobase + APCI1500_Z8536_CTRL_REG);
 130         val = inb(devpriv->iobase + APCI1500_Z8536_CTRL_REG);
 131         spin_unlock_irqrestore(&dev->spinlock, flags);
 132
 133         return val;
 134 }
 135
 136 static void z8536_write(struct comedi_device *dev,
 137                         unsigned int val, unsigned int reg)
 138 {
 139         struct apci1500_private *devpriv = dev->private;
 140         unsigned long flags;
 141
 142         spin_lock_irqsave(&dev->spinlock, flags);
 143         outb(reg, devpriv->iobase + APCI1500_Z8536_CTRL_REG);
 144         outb(val, devpriv->iobase + APCI1500_Z8536_CTRL_REG);
 145         spin_unlock_irqrestore(&dev->spinlock, flags);
 146 }
 147
 148 static void z8536_reset(struct comedi_device *dev)
 149 {
 150         struct apci1500_private *devpriv = dev->private;
 151         unsigned long flags;
 152
 153         /*
 154          * Even if the state of the Z8536 is not known, the following
 155          * sequence will reset it and put it in State 0.
 156          */
 157         spin_lock_irqsave(&dev->spinlock, flags);
 158         inb(devpriv->iobase + APCI1500_Z8536_CTRL_REG);
 159         outb(0, devpriv->iobase + APCI1500_Z8536_CTRL_REG);
 160         inb(devpriv->iobase + APCI1500_Z8536_CTRL_REG);
 161         outb(0, devpriv->iobase + APCI1500_Z8536_CTRL_REG);
 162         outb(1, devpriv->iobase + APCI1500_Z8536_CTRL_REG);
 163         outb(0, devpriv->iobase + APCI1500_Z8536_CTRL_REG);
 164         spin_unlock_irqrestore(&dev->spinlock, flags);
 165
 166         z8536_write(dev, 0xf4, APCI1500_RW_MASTER_CONFIGURATION_CONTROL);
 167
 168         z8536_write(dev, 0x10, APCI1500_RW_PORT_A_SPECIFICATION);
 169         /* High level of port A means 1 */
 170         z8536_write(dev, 0xff, APCI1500_RW_PORT_A_DATA_PCITCH_POLARITY);
 171         /* All bits used as inputs */
 172         z8536_write(dev, 0xff, APCI1500_RW_PORT_A_DATA_DIRECTION);
 173         /* Deletes IP and IUS */
 174         z8536_write(dev, 0x20, APCI1500_RW_PORT_A_COMMAND_AND_STATUS);
 175         /* Deactivates the interrupt management of port A */
 176         z8536_write(dev, 0xe0, APCI1500_RW_PORT_A_COMMAND_AND_STATUS);
 177         /* Deletes the register */
 178         z8536_write(dev, 0x00, APCI1500_RW_PORT_A_HANDSHAKE_SPECIFICATION);
 179
 180         z8536_write(dev, 0x10, APCI1500_RW_PORT_B_SPECIFICATION);
 181         /* A high level of port B means 1 */
 182         z8536_write(dev, 0x7f, APCI1500_RW_PORT_B_DATA_PCITCH_POLARITY);
 183         /* All bits used as inputs */
 184         z8536_write(dev, 0xff, APCI1500_RW_PORT_B_DATA_DIRECTION);
 185         /* Deletes IP and IUS */
 186         z8536_write(dev, 0x20, APCI1500_RW_PORT_B_COMMAND_AND_STATUS);
 187         /* Deactivates the interrupt management of port B */
 188         z8536_write(dev, 0xe0, APCI1500_RW_PORT_B_COMMAND_AND_STATUS);
 189         /* Deletes the register */
 190         z8536_write(dev, 0x00, APCI1500_RW_PORT_B_HANDSHAKE_SPECIFICATION);
 191
 192         /* High level of port C means 1 */
 193         z8536_write(dev, 0x09, APCI1500_RW_PORT_C_DATA_PCITCH_POLARITY);
 194         /* All bits used as inputs except channel 1 */
 195         z8536_write(dev, 0x0e, APCI1500_RW_PORT_C_DATA_DIRECTION);
 196         /* Deletes it */
 197         z8536_write(dev, 0x00, APCI1500_RW_PORT_C_SPECIAL_IO_CONTROL);
 198
 199         /* Deletes IP and IUS */
 200         z8536_write(dev, 0x20, APCI1500_RW_CPT_TMR1_CMD_STATUS);
 201         /* Deactivates the interrupt management of timer 1 */
 202         z8536_write(dev, 0xe0, APCI1500_RW_CPT_TMR1_CMD_STATUS);
 203
 204         /* Deletes IP and IUS */
 205         z8536_write(dev, 0x20, APCI1500_RW_CPT_TMR2_CMD_STATUS);
 206         /* Deactivates Timer 2 interrupt management */
 207         z8536_write(dev, 0xe0, APCI1500_RW_CPT_TMR2_CMD_STATUS);
 208
 209         /* Deletes IP and IUS */
 210         z8536_write(dev, 0x20, APCI1500_RW_CPT_TMR3_CMD_STATUS);
 211         /* Deactivates interrupt management of timer 3 */
 212         z8536_write(dev, 0xe0, APCI1500_RW_CPT_TMR3_CMD_STATUS);
 213
 214         /* Deletes all interrupts */
 215         z8536_write(dev, 0x00, APCI1500_RW_MASTER_INTERRUPT_CONTROL);
 216 }
 217
 218 /*
 219  * An event can be generated for each port. The first event is related to the
 220  * first 8 channels (port 1) and the second to the following 6 channels (port 2)
 221  * An interrupt is generated when one or both events have occurred.
 222  *
 223  * data[0] Number of the input port on which the event will take place (1 or 2)
 224  * data[1] The event logic for port 1 has three possibilities:
 225  *      APCI1500_AND            This logic links the inputs with an AND logic.
 226  *      APCI1500_OR             This logic links the inputs with a OR logic.
 227  *      APCI1500_OR_PRIORITY    This logic links the inputs with a priority OR
 228  *                              logic. Input 1 has the highest priority level
 229  *                              and input 8 the smallest.
 230  *      For the second port the user has 1 possibility:
 231  *      APCI1500_OR     This logic links the inputs with a polarity OR logic
 232  * data[2] These 8-character word for port1 and 6-character word for port 2
 233  *         give the mask of the event. Each place gives the state of the input
 234  *         channels and can have one of these six characters
 235  *      0 This input must be on 0
 236  *      1 This input must be on 1
 237  *      2 This input reacts to a falling edge
 238  *      3 This input reacts to a rising edge
 239  *      4 This input reacts to both edges
 240  *      5 This input is not used for event
 241  */
 242 static int apci1500_di_config(struct comedi_device *dev,
 243                               struct comedi_subdevice *s,
 244                               struct comedi_insn *insn,
 245                               unsigned int *data)
 246 {
 247         int i_PatternPolarity = 0, i_PatternTransition = 0, i_PatternMask = 0;
 248         int i_MaxChannel = 0, i_Count = 0, i_EventMask = 0;
 249         int i_PatternTransitionCount = 0, i_RegValue;
 250         int i;
 251
 252         /* Disables the main interrupt on the board */
 253         z8536_write(dev, 0x00, APCI1500_RW_MASTER_INTERRUPT_CONTROL);
 254
 255         if (data[0] == 1) {
 256                 i_MaxChannel = 8;
 257         } else {
 258                 if (data[0] == 2) {
 259                         i_MaxChannel = 6;
 260                 } else {
 261                         dev_warn(dev->class_dev,
 262                                 "The specified port event does not exist\n");
 263                         return -EINVAL;
 264                 }
 265         }
 266         switch (data[1]) {
 267         case 0:
 268                 data[1] = APCI1500_AND;
 269                 break;
 270         case 1:
 271                 data[1] = APCI1500_OR;
 272                 break;
 273         case 2:
 274                 data[1] = APCI1500_OR_PRIORITY;
 275                 break;
 276         default:
 277                 dev_warn(dev->class_dev,
 278                         "The specified interrupt logic does not exist\n");
 279                 return -EINVAL;
 280         }
 281
 282         i_Logic = data[1];
 283         for (i_Count = i_MaxChannel, i = 0; i_Count > 0; i_Count--, i++) {
 284                 i_EventMask = data[2 + i];
 285                 switch (i_EventMask) {
 286                 case 0:
 287                         i_PatternMask =
 288                                 i_PatternMask | (1 << (i_MaxChannel - i_Count));
 289                         break;
 290                 case 1:
 291                         i_PatternMask =
 292                                 i_PatternMask | (1 << (i_MaxChannel - i_Count));
 293                         i_PatternPolarity =
 294                                 i_PatternPolarity | (1 << (i_MaxChannel -
 295                                         i_Count));
 296                         break;
 297                 case 2:
 298                         i_PatternMask =
 299                                 i_PatternMask | (1 << (i_MaxChannel - i_Count));
 300                         i_PatternTransition =
 301                                 i_PatternTransition | (1 << (i_MaxChannel -
 302                                         i_Count));
 303                         break;
 304                 case 3:
 305                         i_PatternMask =
 306                                 i_PatternMask | (1 << (i_MaxChannel - i_Count));
 307                         i_PatternPolarity =
 308                                 i_PatternPolarity | (1 << (i_MaxChannel -
 309                                         i_Count));
 310                         i_PatternTransition =
 311                                 i_PatternTransition | (1 << (i_MaxChannel -
 312                                         i_Count));
 313                         break;
 314                 case 4:
 315                         i_PatternTransition =
 316                                 i_PatternTransition | (1 << (i_MaxChannel -
 317                                         i_Count));
 318                         break;
 319                 case 5:
 320                         break;
 321                 default:
 322                         dev_warn(dev->class_dev,
 323                                 "The option indicated in the event mask does not exist\n");
 324                         return -EINVAL;
 325                 }
 326         }
 327
 328         if (data[0] == 1) {
 329                 /* Test the interrupt logic */
 330
 331                 if (data[1] == APCI1500_AND ||
 332                         data[1] == APCI1500_OR ||
 333                         data[1] == APCI1500_OR_PRIORITY) {
 334                         /* Tests if a transition was declared */
 335                         /* for a OR PRIORITY logic            */
 336
 337                         if (data[1] == APCI1500_OR_PRIORITY
 338                                 && i_PatternTransition != 0) {
 339                                 dev_warn(dev->class_dev,
 340                                         "Transition error on an OR PRIORITY logic\n");
 341                                 return -EINVAL;
 342                         }
 343
 344                         /* Tests if more than one transition */
 345                         /* was declared for an AND logic     */
 346
 347                         if (data[1] == APCI1500_AND) {
 348                                 for (i_Count = 0; i_Count < 8; i_Count++) {
 349                                         i_PatternTransitionCount =
 350                                                 i_PatternTransitionCount +
 351                                                 ((i_PatternTransition >>
 352                                                         i_Count) & 0x1);
 353
 354                                 }
 355
 356                                 if (i_PatternTransitionCount > 1) {
 357                                         dev_warn(dev->class_dev,
 358                                                 "Transition error on an AND logic\n");
 359                                         return -EINVAL;
 360                                 }
 361                         }
 362
 363                         /* Disable Port A */
 364                         z8536_write(dev, 0xf0,
 365                                     APCI1500_RW_MASTER_CONFIGURATION_CONTROL);
 366
 367                         z8536_write(dev, i_PatternPolarity,
 368                                     APCI1500_RW_PORT_A_PATTERN_POLARITY);
 369                         z8536_write(dev, i_PatternMask,
 370                                     APCI1500_RW_PORT_A_PATTERN_MASK);
 371                         z8536_write(dev, i_PatternTransition,
 372                                     APCI1500_RW_PORT_A_PATTERN_TRANSITION);
 373
 374                         /* Port A new mode    */
 375                         i_RegValue = z8536_read(dev,
 376                                         APCI1500_RW_PORT_A_SPECIFICATION);
 377                         i_RegValue = (i_RegValue & 0xF9) | data[1] | 0x9;
 378                         z8536_write(dev, i_RegValue,
 379                                     APCI1500_RW_PORT_A_SPECIFICATION);
 380
 381                         i_Event1Status = 1;
 382
 383                         /* Enable Port A */
 384                         z8536_write(dev, 0xf4,
 385                                     APCI1500_RW_MASTER_CONFIGURATION_CONTROL);
 386                 } else {
 387                         dev_warn(dev->class_dev,
 388                                 "The choice for interrupt logic does not exist\n");
 389                         return -EINVAL;
 390                 }
 391         }
 392
 393         /* Test if event setting for port 2 */
 394
 395         if (data[0] == 2) {
 396                 /* Test the event logic */
 397
 398                 if (data[1] == APCI1500_OR) {
 399                         /* Disable Port B */
 400                         z8536_write(dev, 0x74,
 401                                     APCI1500_RW_MASTER_CONFIGURATION_CONTROL);
 402
 403                         i_RegValue = z8536_read(dev,
 404                                         APCI1500_RW_PORT_B_SPECIFICATION);
 405                         i_RegValue = i_RegValue & 0xF9;
 406                         z8536_write(dev, i_RegValue,
 407                                     APCI1500_RW_PORT_B_SPECIFICATION);
 408
 409                         /* Selects error channels 1 and 2 */
 410                         i_PatternMask = (i_PatternMask | 0xC0);
 411                         i_PatternPolarity = (i_PatternPolarity | 0xC0);
 412                         i_PatternTransition = (i_PatternTransition | 0xC0);
 413
 414                         z8536_write(dev, i_PatternPolarity,
 415                                     APCI1500_RW_PORT_B_PATTERN_POLARITY);
 416                         z8536_write(dev, i_PatternTransition,
 417                                     APCI1500_RW_PORT_B_PATTERN_TRANSITION);
 418                         z8536_write(dev, i_PatternMask,
 419                                     APCI1500_RW_PORT_B_PATTERN_MASK);
 420
 421                         i_RegValue = z8536_read(dev,
 422                                         APCI1500_RW_PORT_B_SPECIFICATION);
 423                         i_RegValue = (i_RegValue & 0xF9) | 4;
 424                         z8536_write(dev, i_RegValue,
 425                                     APCI1500_RW_PORT_B_SPECIFICATION);
 426
 427                         i_Event2Status = 1;
 428
 429                         /* Enable Port B */
 430                         z8536_write(dev, 0xf4,
 431                                     APCI1500_RW_MASTER_CONFIGURATION_CONTROL);
 432                 } else {
 433                         dev_warn(dev->class_dev,
 434                                 "The choice for interrupt logic does not exist\n");
 435                         return -EINVAL;
 436                 }
 437         }
 438
 439         return insn->n;
 440 }
 441
 442 /*
 443  * Allows or disallows a port event
 444  *
 445  * data[0] 0 = Start input event, 1 = Stop input event
 446  * data[1] Number of port (1 or 2)
 447  */
 448 static int apci1500_di_write(struct comedi_device *dev,
 449                              struct comedi_subdevice *s,
 450                              struct comedi_insn *insn,
 451                              unsigned int *data)
 452 {
 453         int i_Event1InterruptStatus = 0, i_Event2InterruptStatus =
 454                 0, i_RegValue;
 455
 456         switch (data[0]) {
 457         case START:
 458                 /* Tests the port number */
 459
 460                 if (data[1] == 1 || data[1] == 2) {
 461                         /* Test if port 1 selected */
 462
 463                         if (data[1] == 1) {
 464                                 /* Test if event initialised */
 465                                 if (i_Event1Status == 1) {
 466                                         /* Disable Port A */
 467                                         z8536_write(dev, 0xf0,
 468                                             APCI1500_RW_MASTER_CONFIGURATION_CONTROL);
 469                                         /* Allows the pattern interrupt      */
 470                                         z8536_write(dev, 0xc0,
 471                                             APCI1500_RW_PORT_A_COMMAND_AND_STATUS);
 472                                         /* Enable Port A */
 473                                         z8536_write(dev, 0xf4,
 474                                             APCI1500_RW_MASTER_CONFIGURATION_CONTROL);
 475
 476                                         i_Event1InterruptStatus = 1;
 477
 478                                         i_RegValue = z8536_read(dev,
 479                                             APCI1500_RW_PORT_A_SPECIFICATION);
 480
 481                                         /* Authorizes the main interrupt on the board */
 482                                         z8536_write(dev, 0xd0,
 483                                             APCI1500_RW_MASTER_INTERRUPT_CONTROL);
 484                                 } else {
 485                                         dev_warn(dev->class_dev,
 486                                                 "Event 1 not initialised\n");
 487                                         return -EINVAL;
 488                                 }
 489                         }
 490                         if (data[1] == 2) {
 491
 492                                 if (i_Event2Status == 1) {
 493                                         /* Disable Port B */
 494                                         z8536_write(dev, 0x74,
 495                                             APCI1500_RW_MASTER_CONFIGURATION_CONTROL);
 496                                         /* Allows the pattern interrupt      */
 497                                         z8536_write(dev, 0xc0,
 498                                             APCI1500_RW_PORT_B_COMMAND_AND_STATUS);
 499                                         /* Enable Port B */
 500                                         z8536_write(dev, 0xf4,
 501                                             APCI1500_RW_MASTER_CONFIGURATION_CONTROL);
 502
 503                                         /* Authorizes the main interrupt on the board */
 504                                         z8536_write(dev, 0xd0,
 505                                             APCI1500_RW_MASTER_INTERRUPT_CONTROL);
 506
 507                                         i_Event2InterruptStatus = 1;
 508                                 } else {
 509                                         dev_warn(dev->class_dev,
 510                                                 "Event 2 not initialised\n");
 511                                         return -EINVAL;
 512                                 }
 513                         }
 514                 } else {
 515                         dev_warn(dev->class_dev,
 516                                 "The port parameter is in error\n");
 517                         return -EINVAL;
 518                 }
 519
 520                 break;
 521
 522         case STOP:
 523                 /* Tests the port number */
 524
 525                 if (data[1] == 1 || data[1] == 2) {
 526                         /* Test if port 1 selected */
 527
 528                         if (data[1] == 1) {
 529                                 /* Test if event initialised */
 530                                 if (i_Event1Status == 1) {
 531                                         /* Disable Port A */
 532                                         z8536_write(dev, 0xf0,
 533                                             APCI1500_RW_MASTER_CONFIGURATION_CONTROL);
 534                                         /* Inhibits the pattern interrupt */
 535                                         z8536_write(dev, 0xe0,
 536                                             APCI1500_RW_PORT_A_COMMAND_AND_STATUS);
 537                                         /* Enable Port A */
 538                                         z8536_write(dev, 0xf4,
 539                                             APCI1500_RW_MASTER_CONFIGURATION_CONTROL);
 540
 541                                         i_Event1InterruptStatus = 0;
 542                                 } else {
 543                                         dev_warn(dev->class_dev,
 544                                                 "Event 1 not initialised\n");
 545                                         return -EINVAL;
 546                                 }
 547                         }
 548                         if (data[1] == 2) {
 549                                 /* Test if event initialised */
 550                                 if (i_Event2Status == 1) {
 551                                         /* Disable Port B */
 552                                         z8536_write(dev, 0x74,
 553                                             APCI1500_RW_MASTER_CONFIGURATION_CONTROL);
 554                                         /* Inhibits the pattern interrupt      */
 555                                         z8536_write(dev, 0xe0,
 556                                             APCI1500_RW_PORT_B_COMMAND_AND_STATUS);
 557                                         /* Enable Port B */
 558                                         z8536_write(dev, 0xf4,
 559                                             APCI1500_RW_MASTER_CONFIGURATION_CONTROL);
 560
 561                                         i_Event2InterruptStatus = 0;
 562                                 } else {
 563
 564                                         dev_warn(dev->class_dev,
 565                                                 "Event 2 not initialised\n");
 566                                         return -EINVAL;
 567                                 }
 568                         }
 569
 570                 } else {
 571                         dev_warn(dev->class_dev,
 572                                 "The port parameter is in error\n");
 573                         return -EINVAL;
 574                 }
 575                 break;
 576         default:
 577                 dev_warn(dev->class_dev,
 578                         "The option of START/STOP logic does not exist\n");
 579                 return -EINVAL;
 580         }
 581
 582         return insn->n;
 583 }
 584
 585 /*
 586  * Return the status of the digital input
 587  */
 588 static int apci1500_di_read(struct comedi_device *dev,
 589                             struct comedi_subdevice *s,
 590                             struct comedi_insn *insn,
 591                             unsigned int *data)
 592 {
 593         /* Software reset */
 594         z8536_reset(dev);
 595
 596         return insn->n;
 597 }
 598
 599 static int apci1500_di_insn_bits(struct comedi_device *dev,
 600                                  struct comedi_subdevice *s,
 601                                  struct comedi_insn *insn,
 602                                  unsigned int *data)
 603 {
 604         struct apci1500_private *devpriv = dev->private;
 605
 606         data[1] = inw(devpriv->i_IobaseAddon + APCI1500_DIGITAL_IP);
 607
 608         return insn->n;
 609 }
 610
 611 /*
 612  * Configures the digital output memory and the digital output error interrupt
 613  *
 614  * data[1] 1 = Enable the voltage error interrupt
 615  *         2 = Disable the voltage error interrupt
 616  */
 617 static int apci1500_do_config(struct comedi_device *dev,
 618                               struct comedi_subdevice *s,
 619                               struct comedi_insn *insn,
 620                               unsigned int *data)
 621 {
 622         struct apci1500_private *devpriv = dev->private;
 623
 624         devpriv->b_OutputMemoryStatus = data[0];
 625         return insn->n;
 626 }
 627
 628 /*
 629  * Writes port value to the selected port
 630  */
 631 static int apci1500_do_write(struct comedi_device *dev,
 632                              struct comedi_subdevice *s,
 633                              struct comedi_insn *insn,
 634                              unsigned int *data)
 635 {
 636         struct apci1500_private *devpriv = dev->private;
 637         static unsigned int ui_Temp;
 638         unsigned int ui_Temp1;
 639         unsigned int ui_NoOfChannel = CR_CHAN(insn->chanspec);  /*  get the channel */
 640
 641         if (!devpriv->b_OutputMemoryStatus)
 642                 ui_Temp = 0;
 643
 644         if (data[3] == 0) {
 645                 if (data[1] == 0) {
 646                         data[0] = (data[0] << ui_NoOfChannel) | ui_Temp;
 647                         outw(data[0],
 648                                 devpriv->i_IobaseAddon + APCI1500_DIGITAL_OP);
 649                 } else {
 650                         if (data[1] == 1) {
 651                                 switch (ui_NoOfChannel) {
 652
 653                                 case 2:
 654                                         data[0] =
 655                                                 (data[0] << (2 *
 656                                                         data[2])) | ui_Temp;
 657                                         break;
 658
 659                                 case 4:
 660                                         data[0] =
 661                                                 (data[0] << (4 *
 662                                                         data[2])) | ui_Temp;
 663                                         break;
 664
 665                                 case 8:
 666                                         data[0] =
 667                                                 (data[0] << (8 *
 668                                                         data[2])) | ui_Temp;
 669                                         break;
 670
 671                                 case 15:
 672                                         data[0] = data[0] | ui_Temp;
 673                                         break;
 674
 675                                 default:
 676                                         dev_err(dev->class_dev,
 677                                                 "chan spec wrong\n");
 678                                         return -EINVAL; /*  "sorry channel spec wrong " */
 679
 680                                 }
 681
 682                                 outw(data[0],
 683                                         devpriv->i_IobaseAddon +
 684                                         APCI1500_DIGITAL_OP);
 685                         } else {
 686                                 dev_warn(dev->class_dev,
 687                                         "Specified channel not supported\n");
 688                                 return -EINVAL;
 689                         }
 690                 }
 691         } else {
 692                 if (data[3] == 1) {
 693                         if (data[1] == 0) {
 694                                 data[0] = ~data[0] & 0x1;
 695                                 ui_Temp1 = 1;
 696                                 ui_Temp1 = ui_Temp1 << ui_NoOfChannel;
 697                                 ui_Temp = ui_Temp | ui_Temp1;
 698                                 data[0] =
 699                                         (data[0] << ui_NoOfChannel) ^
 700                                         0xffffffff;
 701                                 data[0] = data[0] & ui_Temp;
 702                                 outw(data[0],
 703                                         devpriv->i_IobaseAddon +
 704                                         APCI1500_DIGITAL_OP);
 705                         } else {
 706                                 if (data[1] == 1) {
 707                                         switch (ui_NoOfChannel) {
 708
 709                                         case 2:
 710                                                 data[0] = ~data[0] & 0x3;
 711                                                 ui_Temp1 = 3;
 712                                                 ui_Temp1 =
 713                                                         ui_Temp1 << 2 * data[2];
 714                                                 ui_Temp = ui_Temp | ui_Temp1;
 715                                                 data[0] =
 716                                                         ((data[0] << (2 *
 717                                                                         data
 718                                                                         [2])) ^
 719                                                         0xffffffff) & ui_Temp;
 720                                                 break;
 721
 722                                         case 4:
 723                                                 data[0] = ~data[0] & 0xf;
 724                                                 ui_Temp1 = 15;
 725                                                 ui_Temp1 =
 726                                                         ui_Temp1 << 4 * data[2];
 727                                                 ui_Temp = ui_Temp | ui_Temp1;
 728                                                 data[0] =
 729                                                         ((data[0] << (4 *
 730                                                                         data
 731                                                                         [2])) ^
 732                                                         0xffffffff) & ui_Temp;
 733                                                 break;
 734
 735                                         case 8:
 736                                                 data[0] = ~data[0] & 0xff;
 737                                                 ui_Temp1 = 255;
 738                                                 ui_Temp1 =
 739                                                         ui_Temp1 << 8 * data[2];
 740                                                 ui_Temp = ui_Temp | ui_Temp1;
 741                                                 data[0] =
 742                                                         ((data[0] << (8 *
 743                                                                         data
 744                                                                         [2])) ^
 745                                                         0xffffffff) & ui_Temp;
 746                                                 break;
 747
 748                                         case 15:
 749                                                 break;
 750
 751                                         default:
 752                                                 dev_err(dev->class_dev,
 753                                                         "chan spec wrong\n");
 754                                                 return -EINVAL; /*  "sorry channel spec wrong " */
 755
 756                                         }
 757
 758                                         outw(data[0],
 759                                                 devpriv->i_IobaseAddon +
 760                                                 APCI1500_DIGITAL_OP);
 761                                 } else {
 762                                         dev_warn(dev->class_dev,
 763                                                 "Specified channel not supported\n");
 764                                         return -EINVAL;
 765                                 }
 766                         }
 767                 } else {
 768                         dev_warn(dev->class_dev,
 769                                 "Specified functionality does not exist\n");
 770                         return -EINVAL;
 771                 }
 772         }
 773         ui_Temp = data[0];
 774         return insn->n;
 775 }
 776
 777 /*
 778  * Configures The Watchdog
 779  *
 780  * data[0] 0 = APCI1500_115_KHZ, 1 = APCI1500_3_6_KHZ, 2 = APCI1500_1_8_KHZ
 781  * data[1] 0 = Counter1/Timer1, 1 =  Counter2/Timer2, 2 = Counter3/Watchdog
 782  * data[2] 0 = Counter, 1 = Timer/Watchdog
 783  * data[3] This parameter has two meanings. If the counter/timer is used as
 784  *      a counter the limit value of the counter is given. If the counter/timer
 785  *      is used as a timer, the divider factor for the output is given.
 786  * data[4] 0 = APCI1500_CONTINUOUS, 1 = APCI1500_SINGLE
 787  * data[5] 0 = Software Trigger, 1 = Hardware Trigger
 788  * data[6] 0 = Software gate, 1 = Hardware gate
 789  * data[7] 0 = Interrupt Disable, 1 = Interrupt Enable
 790  */
 791 static int apci1500_timer_config(struct comedi_device *dev,
 792                                  struct comedi_subdevice *s,
 793                                  struct comedi_insn *insn,
 794                                  unsigned int *data)
 795 {
 796         struct apci1500_private *devpriv = dev->private;
 797         int i_TimerCounterMode, i_MasterConfiguration;
 798
 799         devpriv->tsk_Current = current;
 800
 801         /* Selection of the input clock */
 802         if (data[0] == 0 || data[0] == 1 || data[0] == 2) {
 803                 outw(data[0], devpriv->i_IobaseAddon + APCI1500_CLK_SELECT);
 804         } else {
 805                 if (data[0] != 3) {
 806                         dev_warn(dev->class_dev,
 807                                 "The option for input clock selection does not exist\n");
 808                         return -EINVAL;
 809                 }
 810         }
 811         /* Select the counter/timer */
 812         switch (data[1]) {
 813         case COUNTER1:
 814                 /* selecting counter or timer */
 815                 switch (data[2]) {
 816                 case 0:
 817                         data[2] = APCI1500_COUNTER;
 818                         break;
 819                 case 1:
 820                         data[2] = APCI1500_TIMER;
 821                         break;
 822                 default:
 823                         dev_warn(dev->class_dev,
 824                                 "This choice is not a timer nor a counter\n");
 825                         return -EINVAL;
 826                 }
 827
 828                 /* Selecting  single or continuous mode */
 829                 switch (data[4]) {
 830                 case 0:
 831                         data[4] = APCI1500_CONTINUOUS;
 832                         break;
 833                 case 1:
 834                         data[4] = APCI1500_SINGLE;
 835                         break;
 836                 default:
 837                         dev_warn(dev->class_dev,
 838                                 "This option for single/continuous mode does not exist\n");
 839                         return -EINVAL;
 840                 }
 841
 842                 i_TimerCounterMode = data[2] | data[4] | 7;
 843                 /* Test the reload value */
 844
 845                 if ((data[3] >= 0) && (data[3] <= 65535)) {
 846                         if (data[7] == APCI1500_ENABLE ||
 847                             data[7] == APCI1500_DISABLE) {
 848                                 /* Writes the new mode */
 849                                 z8536_write(dev, i_TimerCounterMode,
 850                                     APCI1500_RW_CPT_TMR1_MODE_SPECIFICATION);
 851
 852                                 /* Writes the low value */
 853                                 z8536_write(dev, data[3],
 854                                             APCI1500_RW_CPT_TMR1_TIME_CST_LOW);
 855                                 /* Writes the high value  */
 856                                 data[3] = data[3] >> 8;
 857                                 z8536_write(dev, data[3],
 858                                             APCI1500_RW_CPT_TMR1_TIME_CST_HIGH);
 859
 860                                 /* Enables timer/counter 1 and triggers timer/counter 1 */
 861                                 i_MasterConfiguration = z8536_read(dev,
 862                                     APCI1500_RW_MASTER_CONFIGURATION_CONTROL);
 863                                 i_MasterConfiguration =
 864                                         i_MasterConfiguration | 0x40;
 865                                 z8536_write(dev, i_MasterConfiguration,
 866                                     APCI1500_RW_MASTER_CONFIGURATION_CONTROL);
 867
 868                                 /* Disable timer/counter 1 */
 869                                 z8536_write(dev, 0x00,
 870                                             APCI1500_RW_CPT_TMR1_CMD_STATUS);
 871                                 /* Trigger timer/counter 1 */
 872                                 z8536_write(dev, 0x02,
 873                                             APCI1500_RW_CPT_TMR1_CMD_STATUS);
 874                         } else {
 875                                 dev_warn(dev->class_dev,
 876                                         "Error in selection of interrupt enable or disable\n");
 877                                 return -EINVAL;
 878                         }
 879                 } else {
 880                         dev_warn(dev->class_dev,
 881                                 "Error in selection of reload value\n");
 882                         return -EINVAL;
 883                 }
 884                 i_TimerCounterWatchdogInterrupt = data[7];
 885                 i_TimerCounter1Init = 1;
 886                 break;
 887
 888         case COUNTER2:          /* selecting counter or timer */
 889                 switch (data[2]) {
 890                 case 0:
 891                         data[2] = APCI1500_COUNTER;
 892                         break;
 893                 case 1:
 894                         data[2] = APCI1500_TIMER;
 895                         break;
 896                 default:
 897                         dev_warn(dev->class_dev,
 898                                 "This choice is not a timer nor a counter\n");
 899                         return -EINVAL;
 900                 }
 901
 902                 /* Selecting  single or continuous mode */
 903                 switch (data[4]) {
 904                 case 0:
 905                         data[4] = APCI1500_CONTINUOUS;
 906                         break;
 907                 case 1:
 908                         data[4] = APCI1500_SINGLE;
 909                         break;
 910                 default:
 911                         dev_warn(dev->class_dev,
 912                                 "This option for single/continuous mode does not exist\n");
 913                         return -EINVAL;
 914                 }
 915
 916                 /* Selecting  software or hardware trigger */
 917                 switch (data[5]) {
 918                 case 0:
 919                         data[5] = APCI1500_SOFTWARE_TRIGGER;
 920                         break;
 921                 case 1:
 922                         data[5] = APCI1500_HARDWARE_TRIGGER;
 923                         break;
 924                 default:
 925                         dev_warn(dev->class_dev,
 926                                 "This choice for software or hardware trigger does not exist\n");
 927                         return -EINVAL;
 928                 }
 929
 930                 /* Selecting  software or hardware gate */
 931                 switch (data[6]) {
 932                 case 0:
 933                         data[6] = APCI1500_SOFTWARE_GATE;
 934                         break;
 935                 case 1:
 936                         data[6] = APCI1500_HARDWARE_GATE;
 937                         break;
 938                 default:
 939                         dev_warn(dev->class_dev,
 940                                 "This choice for software or hardware gate does not exist\n");
 941                         return -EINVAL;
 942                 }
 943
 944                 i_TimerCounterMode = data[2] | data[4] | data[5] | data[6] | 7;
 945
 946                 /* Test the reload value */
 947
 948                 if ((data[3] >= 0) && (data[3] <= 65535)) {
 949                         if (data[7] == APCI1500_ENABLE ||
 950                             data[7] == APCI1500_DISABLE) {
 951                                 /* Writes the new mode */
 952                                 z8536_write(dev, i_TimerCounterMode,
 953                                     APCI1500_RW_CPT_TMR2_MODE_SPECIFICATION);
 954
 955                                 /* Writes the low value */
 956                                 z8536_write(dev, data[3],
 957                                             APCI1500_RW_CPT_TMR2_TIME_CST_LOW);
 958                                 /* Writes the high value */
 959                                 data[3] = data[3] >> 8;
 960                                 z8536_write(dev, data[3],
 961                                             APCI1500_RW_CPT_TMR2_TIME_CST_HIGH);
 962
 963                                 /* Enables timer/counter 2 and triggers timer/counter 2 */
 964                                 i_MasterConfiguration = z8536_read(dev,
 965                                     APCI1500_RW_MASTER_CONFIGURATION_CONTROL);
 966                                 i_MasterConfiguration =
 967                                         i_MasterConfiguration | 0x20;
 968                                 z8536_write(dev, i_MasterConfiguration,
 969                                     APCI1500_RW_MASTER_CONFIGURATION_CONTROL);
 970
 971                                 /* Disable timer/counter 2 */
 972                                 z8536_write(dev, 0x00,
 973                                             APCI1500_RW_CPT_TMR2_CMD_STATUS);
 974                                 /* Trigger timer/counter 1 */
 975                                 z8536_write(dev, 0x02,
 976                                             APCI1500_RW_CPT_TMR2_CMD_STATUS);
 977                         } else {
 978                                 dev_warn(dev->class_dev,
 979                                         "Error in selection of interrupt enable or disable\n");
 980                                 return -EINVAL;
 981                         }
 982                 } else {
 983                         dev_warn(dev->class_dev,
 984                                 "Error in selection of reload value\n");
 985                         return -EINVAL;
 986                 }
 987                 i_TimerCounterWatchdogInterrupt = data[7];
 988                 i_TimerCounter2Init = 1;
 989                 break;
 990
 991         case COUNTER3:          /* selecting counter or watchdog */
 992                 switch (data[2]) {
 993                 case 0:
 994                         data[2] = APCI1500_COUNTER;
 995                         break;
 996                 case 1:
 997                         data[2] = APCI1500_WATCHDOG;
 998                         break;
 999                 default:
1000                         dev_warn(dev->class_dev,
1001                                 "This choice is not a watchdog nor a counter\n");
1002                         return -EINVAL;
1003                 }
1004
1005                 /* Selecting  single or continuous mode */
1006                 switch (data[4]) {
1007                 case 0:
1008                         data[4] = APCI1500_CONTINUOUS;
1009                         break;
1010                 case 1:
1011                         data[4] = APCI1500_SINGLE;
1012                         break;
1013                 default:
1014                         dev_warn(dev->class_dev,
1015                                 "This option for single/continuous mode does not exist\n");
1016                         return -EINVAL;
1017                 }
1018
1019                 /* Selecting  software or hardware gate */
1020                 switch (data[6]) {
1021                 case 0:
1022                         data[6] = APCI1500_SOFTWARE_GATE;
1023                         break;
1024                 case 1:
1025                         data[6] = APCI1500_HARDWARE_GATE;
1026                         break;
1027                 default:
1028                         dev_warn(dev->class_dev,
1029                                 "This choice for software or hardware gate does not exist\n");
1030                         return -EINVAL;
1031                 }
1032
1033                 /* Test if used for watchdog */
1034
1035                 if (data[2] == APCI1500_WATCHDOG) {
1036                         /* - Enables the output line */
1037                         /* - Enables retrigger       */
1038                         /* - Pulses output           */
1039                         i_TimerCounterMode = data[2] | data[4] | 0x54;
1040                 } else {
1041                         i_TimerCounterMode = data[2] | data[4] | data[6] | 7;
1042                 }
1043                 /* Test the reload value */
1044
1045                 if ((data[3] >= 0) && (data[3] <= 65535)) {
1046                         if (data[7] == APCI1500_ENABLE ||
1047                             data[7] == APCI1500_DISABLE) {
1048                                 /* Writes the new mode */
1049                                 z8536_write(dev, i_TimerCounterMode,
1050                                     APCI1500_RW_CPT_TMR3_MODE_SPECIFICATION);
1051
1052                                 /* Writes the low value  */
1053                                 z8536_write(dev, data[3],
1054                                             APCI1500_RW_CPT_TMR3_TIME_CST_LOW);
1055                                 /* Writes the high value  */
1056                                 data[3] = data[3] >> 8;
1057                                 z8536_write(dev, data[3],
1058                                             APCI1500_RW_CPT_TMR3_TIME_CST_HIGH);
1059
1060                                 /* Enables watchdog/counter 3 and triggers watchdog/counter 3 */
1061                                 i_MasterConfiguration = z8536_read(dev,
1062                                     APCI1500_RW_MASTER_CONFIGURATION_CONTROL);
1063                                 i_MasterConfiguration =
1064                                         i_MasterConfiguration | 0x10;
1065                                 z8536_write(dev, i_MasterConfiguration,
1066                                     APCI1500_RW_MASTER_CONFIGURATION_CONTROL);
1067
1068                                 /* Test if COUNTER */
1069                                 if (data[2] == APCI1500_COUNTER) {
1070                                         /* Disable the  watchdog/counter 3 and starts it */
1071                                         z8536_write(dev, 0x00,
1072                                             APCI1500_RW_CPT_TMR3_CMD_STATUS);
1073                                         /* Trigger the  watchdog/counter 3 and starts it */
1074                                         z8536_write(dev, 0x02,
1075                                             APCI1500_RW_CPT_TMR3_CMD_STATUS);
1076                                 }
1077
1078                         } else {
1079
1080                                 dev_warn(dev->class_dev,
1081                                         "Error in selection of interrupt enable or disable\n");
1082                                 return -EINVAL;
1083                         }
1084                 } else {
1085                         dev_warn(dev->class_dev,
1086                                 "Error in selection of reload value\n");
1087                         return -EINVAL;
1088                 }
1089                 i_TimerCounterWatchdogInterrupt = data[7];
1090                 i_WatchdogCounter3Init = 1;
1091                 break;
1092
1093         default:
1094                 dev_warn(dev->class_dev,
1095                         "The specified counter/timer option does not exist\n");
1096                 return -EINVAL;
1097         }
1098         i_CounterLogic = data[2];
1099         return insn->n;
1100 }
1101
1102 /*
1103  * Start / Stop or trigger the timer counter or Watchdog
1104  *
1105  * data[0] 0 = Counter1/Timer1, 1 =  Counter2/Timer2, 2 = Counter3/Watchdog
1106  * data[1] 0 = Start, 1 = Stop, 2 = Trigger
1107  * data[2] 0 = Counter, 1 = Timer/Watchdog
1108  */
1109 static int apci1500_timer_write(struct comedi_device *dev,
1110                                 struct comedi_subdevice *s,
1111                                 struct comedi_insn *insn,
1112                                 unsigned int *data)
1113 {
1114         int i_CommandAndStatusValue;
1115
1116         switch (data[0]) {
1117         case COUNTER1:
1118                 switch (data[1]) {
1119                 case START:
1120                         if (i_TimerCounter1Init == 1) {
1121                                 if (i_TimerCounterWatchdogInterrupt == 1)
1122                                         i_CommandAndStatusValue = 0xC4; /* Enable the interrupt */
1123                                 else
1124                                         i_CommandAndStatusValue = 0xE4; /* disable the interrupt */
1125
1126                                 /* Starts timer/counter 1 */
1127                                 i_TimerCounter1Enabled = 1;
1128                                 z8536_write(dev, i_CommandAndStatusValue,
1129                                             APCI1500_RW_CPT_TMR1_CMD_STATUS);
1130                         } else {
1131                                 dev_warn(dev->class_dev,
1132                                         "Counter/Timer1 not configured\n");
1133                                 return -EINVAL;
1134                         }
1135                         break;
1136
1137                 case STOP:
1138                         /* Stop timer/counter 1 */
1139                         z8536_write(dev, 0x00, APCI1500_RW_CPT_TMR1_CMD_STATUS);
1140                         i_TimerCounter1Enabled = 0;
1141                         break;
1142
1143                 case TRIGGER:
1144                         if (i_TimerCounter1Init == 1) {
1145                                 if (i_TimerCounter1Enabled == 1) {
1146                                         /* Set Trigger and gate */
1147
1148                                         i_CommandAndStatusValue = 0x6;
1149                                 } else {
1150                                         /* Set Trigger */
1151
1152                                         i_CommandAndStatusValue = 0x2;
1153                                 }
1154                                 z8536_write(dev, i_CommandAndStatusValue,
1155                                             APCI1500_RW_CPT_TMR1_CMD_STATUS);
1156                         } else {
1157                                 dev_warn(dev->class_dev,
1158                                         "Counter/Timer1 not configured\n");
1159                                 return -EINVAL;
1160                         }
1161                         break;
1162
1163                 default:
1164                         dev_warn(dev->class_dev,
1165                                 "The specified option for start/stop/trigger does not exist\n");
1166                         return -EINVAL;
1167                 }
1168                 break;
1169
1170         case COUNTER2:
1171                 switch (data[1]) {
1172                 case START:
1173                         if (i_TimerCounter2Init == 1) {
1174                                 if (i_TimerCounterWatchdogInterrupt == 1)
1175                                         i_CommandAndStatusValue = 0xC4; /* Enable the interrupt */
1176                                 else
1177                                         i_CommandAndStatusValue = 0xE4; /* disable the interrupt */
1178
1179                                 /* Starts timer/counter 2 */
1180                                 i_TimerCounter2Enabled = 1;
1181                                 z8536_write(dev, i_CommandAndStatusValue,
1182                                             APCI1500_RW_CPT_TMR2_CMD_STATUS);
1183                         } else {
1184                                 dev_warn(dev->class_dev,
1185                                         "Counter/Timer2 not configured\n");
1186                                 return -EINVAL;
1187                         }
1188                         break;
1189
1190                 case STOP:
1191                         /* Stop timer/counter 2 */
1192                         z8536_write(dev, 0x00, APCI1500_RW_CPT_TMR2_CMD_STATUS);
1193                         i_TimerCounter2Enabled = 0;
1194                         break;
1195                 case TRIGGER:
1196                         if (i_TimerCounter2Init == 1) {
1197                                 if (i_TimerCounter2Enabled == 1) {
1198                                         /* Set Trigger and gate */
1199
1200                                         i_CommandAndStatusValue = 0x6;
1201                                 } else {
1202                                         /* Set Trigger */
1203
1204                                         i_CommandAndStatusValue = 0x2;
1205                                 }
1206                                 z8536_write(dev, i_CommandAndStatusValue,
1207                                             APCI1500_RW_CPT_TMR2_CMD_STATUS);
1208                         } else {
1209                                 dev_warn(dev->class_dev,
1210                                         "Counter/Timer2 not configured\n");
1211                                 return -EINVAL;
1212                         }
1213                         break;
1214                 default:
1215                         dev_warn(dev->class_dev,
1216                                 "The specified option for start/stop/trigger does not exist\n");
1217                         return -EINVAL;
1218                 }
1219                 break;
1220         case COUNTER3:
1221                 switch (data[1]) {
1222                 case START:
1223                         if (i_WatchdogCounter3Init == 1) {
1224
1225                                 if (i_TimerCounterWatchdogInterrupt == 1)
1226                                         i_CommandAndStatusValue = 0xC4; /* Enable the interrupt */
1227                                 else
1228                                         i_CommandAndStatusValue = 0xE4; /* disable the interrupt */
1229
1230                                 /* Starts Watchdog/counter 3 */
1231                                 i_WatchdogCounter3Enabled = 1;
1232                                 z8536_write(dev, i_CommandAndStatusValue,
1233                                             APCI1500_RW_CPT_TMR3_CMD_STATUS);
1234                         } else {
1235                                 dev_warn(dev->class_dev,
1236                                         "Watchdog/Counter3 not configured\n");
1237                                 return -EINVAL;
1238                         }
1239                         break;
1240
1241                 case STOP:
1242                         /* Stop Watchdog/counter 3 */
1243                         z8536_write(dev, 0x00, APCI1500_RW_CPT_TMR3_CMD_STATUS);
1244                         i_WatchdogCounter3Enabled = 0;
1245                         break;
1246
1247                 case TRIGGER:
1248                         switch (data[2]) {
1249                         case 0: /* triggering counter 3 */
1250                                 if (i_WatchdogCounter3Init == 1) {
1251                                         if (i_WatchdogCounter3Enabled == 1) {
1252                                                 /* Set Trigger and gate */
1253
1254                                                 i_CommandAndStatusValue = 0x6;
1255                                         } else {
1256                                                 /* Set Trigger */
1257
1258                                                 i_CommandAndStatusValue = 0x2;
1259                                         }
1260                                         z8536_write(dev, i_CommandAndStatusValue,
1261                                             APCI1500_RW_CPT_TMR3_CMD_STATUS);
1262                                 } else {
1263                                         dev_warn(dev->class_dev,
1264                                                 "Counter3 not configured\n");
1265                                         return -EINVAL;
1266                                 }
1267                                 break;
1268                         case 1:
1269                                 /* triggering Watchdog 3 */
1270                                 if (i_WatchdogCounter3Init == 1) {
1271                                         z8536_write(dev, 0x06,
1272                                             APCI1500_RW_CPT_TMR3_CMD_STATUS);
1273                                 } else {
1274                                         dev_warn(dev->class_dev,
1275                                                 "Watchdog 3 not configured\n");
1276                                         return -EINVAL;
1277                                 }
1278                                 break;
1279                         default:
1280                                 dev_warn(dev->class_dev,
1281                                         "Wrong choice of watchdog/counter3\n");
1282                                 return -EINVAL;
1283                         }
1284                         break;
1285                 default:
1286                         dev_warn(dev->class_dev,
1287                                 "The specified option for start/stop/trigger does not exist\n");
1288                         return -EINVAL;
1289                 }
1290                 break;
1291         default:
1292                 dev_warn(dev->class_dev,
1293                         "The specified choice for counter/watchdog/timer does not exist\n");
1294                 return -EINVAL;
1295         }
1296         return insn->n;
1297 }
1298
1299 /*
1300  * Read The Watchdog
1301  *
1302  * data[0] 0 = Counter1/Timer1, 1 =  Counter2/Timer2, 2 = Counter3/Watchdog
1303  */
1304 static int apci1500_timer_bits(struct comedi_device *dev,
1305                                struct comedi_subdevice *s,
1306                                struct comedi_insn *insn,
1307                                unsigned int *data)
1308 {
1309         int i_CommandAndStatusValue;
1310
1311         switch (data[0]) {
1312         case COUNTER1:
1313                 /* Read counter/timer1 */
1314                 if (i_TimerCounter1Init == 1) {
1315                         if (i_TimerCounter1Enabled == 1) {
1316                                 /* Set RCC and gate */
1317
1318                                 i_CommandAndStatusValue = 0xC;
1319                         } else {
1320                                 /* Set RCC */
1321
1322                                 i_CommandAndStatusValue = 0x8;
1323                         }
1324                         z8536_write(dev, i_CommandAndStatusValue,
1325                                     APCI1500_RW_CPT_TMR1_CMD_STATUS);
1326
1327                         data[0] = z8536_read(dev,
1328                                              APCI1500_R_CPT_TMR1_VALUE_HIGH);
1329                         data[0] = data[0] << 8;
1330                         data[0] = data[0] & 0xff00;
1331                         data[0] |= z8536_read(dev,
1332                                               APCI1500_R_CPT_TMR1_VALUE_LOW);
1333                 } else {
1334                         dev_warn(dev->class_dev,
1335                                 "Timer/Counter1 not configured\n");
1336                         return -EINVAL;
1337                 }
1338                 break;
1339         case COUNTER2:
1340                 /* Read counter/timer2 */
1341                 if (i_TimerCounter2Init == 1) {
1342                         if (i_TimerCounter2Enabled == 1) {
1343                                 /* Set RCC and gate */
1344
1345                                 i_CommandAndStatusValue = 0xC;
1346                         } else {
1347                                 /* Set RCC */
1348
1349                                 i_CommandAndStatusValue = 0x8;
1350                         }
1351                         z8536_write(dev, i_CommandAndStatusValue,
1352                                     APCI1500_RW_CPT_TMR2_CMD_STATUS);
1353
1354                         data[0] = z8536_read(dev,
1355                                              APCI1500_R_CPT_TMR2_VALUE_HIGH);
1356                         data[0] = data[0] << 8;
1357                         data[0] = data[0] & 0xff00;
1358                         data[0] |= z8536_read(dev,
1359                                               APCI1500_R_CPT_TMR2_VALUE_LOW);
1360                 } else {
1361                         dev_warn(dev->class_dev,
1362                                 "Timer/Counter2 not configured\n");
1363                         return -EINVAL;
1364                 }
1365                 break;
1366         case COUNTER3:
1367                 /* Read counter/watchdog2 */
1368                 if (i_WatchdogCounter3Init == 1) {
1369                         if (i_WatchdogCounter3Enabled == 1) {
1370                                 /* Set RCC and gate */
1371
1372                                 i_CommandAndStatusValue = 0xC;
1373                         } else {
1374                                 /* Set RCC */
1375
1376                                 i_CommandAndStatusValue = 0x8;
1377                         }
1378                         z8536_write(dev, i_CommandAndStatusValue,
1379                                     APCI1500_RW_CPT_TMR3_CMD_STATUS);
1380
1381                         data[0] = z8536_read(dev,
1382                                              APCI1500_R_CPT_TMR3_VALUE_HIGH);
1383                         data[0] = data[0] << 8;
1384                         data[0] = data[0] & 0xff00;
1385                         data[0] |= z8536_read(dev,
1386                                               APCI1500_R_CPT_TMR3_VALUE_LOW);
1387                 } else {
1388                         dev_warn(dev->class_dev,
1389                                 "WatchdogCounter3 not configured\n");
1390                         return -EINVAL;
1391                 }
1392                 break;
1393         default:
1394                 dev_warn(dev->class_dev,
1395                         "The choice of timer/counter/watchdog does not exist\n");
1396                 return -EINVAL;
1397         }
1398
1399         return insn->n;
1400 }
1401
1402 /*
1403  * Read the interrupt mask
1404  *
1405  * data[0] The interrupt mask value
1406  * data[1] Channel Number
1407  */
1408 static int apci1500_timer_read(struct comedi_device *dev,
1409                                struct comedi_subdevice *s,
1410                                struct comedi_insn *insn,
1411                                unsigned int *data)
1412 {
1413         data[0] = i_InterruptMask;
1414         data[1] = i_InputChannel;
1415         i_InterruptMask = 0;
1416         return insn->n;
1417 }
1418
1419 /*
1420  * Configures the interrupt registers
1421  */
1422 static int apci1500_do_bits(struct comedi_device *dev,
1423                             struct comedi_subdevice *s,
1424                             struct comedi_insn *insn,
1425                             unsigned int *data)
1426 {
1427         struct apci1500_private *devpriv = dev->private;
1428         unsigned int ui_Status;
1429         int i_RegValue;
1430         int i_Constant;
1431
1432         devpriv->tsk_Current = current;
1433         outl(0x0, devpriv->i_IobaseAmcc + 0x38);
1434         if (data[0] == 1) {
1435                 i_Constant = 0xC0;
1436         } else {
1437                 if (data[0] == 0) {
1438                         i_Constant = 0x00;
1439                 } else {
1440                         dev_warn(dev->class_dev,
1441                                 "The parameter passed to driver is in error for enabling the voltage interrupt\n");
1442                         return -EINVAL;
1443                 }
1444         }
1445
1446         /* Writes the new configuration (APCI1500_OR) */
1447         i_RegValue = z8536_read(dev, APCI1500_RW_PORT_B_SPECIFICATION);
1448         i_RegValue = (i_RegValue & 0xF9) | APCI1500_OR;
1449         z8536_write(dev, i_RegValue, APCI1500_RW_PORT_B_SPECIFICATION);
1450
1451         /* Authorises the interrupt on the board */
1452         z8536_write(dev, 0xc0, APCI1500_RW_PORT_B_COMMAND_AND_STATUS);
1453
1454         z8536_write(dev, i_Constant, APCI1500_RW_PORT_B_PATTERN_POLARITY);
1455         z8536_write(dev, i_Constant, APCI1500_RW_PORT_B_PATTERN_TRANSITION);
1456         z8536_write(dev, i_Constant, APCI1500_RW_PORT_B_PATTERN_MASK);
1457
1458         /* Deletes the interrupt of port A */
1459         i_RegValue = z8536_read(dev, APCI1500_RW_PORT_A_COMMAND_AND_STATUS);
1460         i_RegValue = (i_RegValue & 0x0F) | 0x20;
1461         z8536_write(dev, i_RegValue, APCI1500_RW_PORT_A_COMMAND_AND_STATUS);
1462
1463         /* Deletes the interrupt of port B */
1464         i_RegValue = z8536_read(dev, APCI1500_RW_PORT_B_COMMAND_AND_STATUS);
1465         i_RegValue = (i_RegValue & 0x0F) | 0x20;
1466         z8536_write(dev, i_RegValue, APCI1500_RW_PORT_B_COMMAND_AND_STATUS);
1467
1468         /* Deletes the interrupt of timer 1 */
1469         i_RegValue = z8536_read(dev, APCI1500_RW_CPT_TMR1_CMD_STATUS);
1470         i_RegValue = (i_RegValue & 0x0F) | 0x20;
1471         z8536_write(dev, i_RegValue, APCI1500_RW_CPT_TMR1_CMD_STATUS);
1472
1473         /* Deletes the interrupt of timer 2 */
1474         i_RegValue = z8536_read(dev, APCI1500_RW_CPT_TMR2_CMD_STATUS);
1475         i_RegValue = (i_RegValue & 0x0F) | 0x20;
1476         z8536_write(dev, i_RegValue, APCI1500_RW_CPT_TMR2_CMD_STATUS);
1477
1478         /* Deletes the interrupt of timer 3 */
1479         i_RegValue = z8536_read(dev, APCI1500_RW_CPT_TMR3_CMD_STATUS);
1480         i_RegValue = (i_RegValue & 0x0F) | 0x20;
1481         z8536_write(dev, i_RegValue, APCI1500_RW_CPT_TMR3_CMD_STATUS);
1482
1483         /* Authorizes the main interrupt on the board */
1484         z8536_write(dev, 0xd0, APCI1500_RW_MASTER_INTERRUPT_CONTROL);
1485
1486         /* Enables the PCI interrupt */
1487         outl(0x3000, devpriv->i_IobaseAmcc + 0x38);
1488         ui_Status = inl(devpriv->i_IobaseAmcc + 0x10);
1489         ui_Status = inl(devpriv->i_IobaseAmcc + 0x38);
1490         outl(0x23000, devpriv->i_IobaseAmcc + 0x38);
1491
1492         return insn->n;
1493 }
1494
1495 static irqreturn_t apci1500_interrupt(int irq, void *d)
1496 {
1497
1498         struct comedi_device *dev = d;
1499         struct apci1500_private *devpriv = dev->private;
1500         unsigned int ui_InterruptStatus = 0;
1501         int i_RegValue = 0;
1502
1503         /* Clear the interrupt mask */
1504         i_InterruptMask = 0;
1505
1506         /* Read the board interrupt status */
1507         ui_InterruptStatus = inl(devpriv->i_IobaseAmcc + 0x38);
1508
1509         /* Test if board generated a interrupt */
1510         if ((ui_InterruptStatus & 0x800000) == 0x800000) {
1511                 /* Disable all Interrupt */
1512                 /* Selects the master interrupt control register */
1513                 /* Disables  the main interrupt on the board */
1514                 i_RegValue = z8536_read(dev,
1515                                         APCI1500_RW_PORT_A_COMMAND_AND_STATUS);
1516                 if ((i_RegValue & 0x60) == 0x60) {
1517                         /* Deletes the interrupt of port A */
1518                         i_RegValue = (i_RegValue & 0x0F) | 0x20;
1519                         z8536_write(dev, i_RegValue,
1520                                     APCI1500_RW_PORT_A_COMMAND_AND_STATUS);
1521                         i_InterruptMask = i_InterruptMask | 1;
1522                         if (i_Logic == APCI1500_OR_PRIORITY) {
1523                                 i_RegValue = z8536_read(dev,
1524                                         APCI1500_RW_PORT_A_SPECIFICATION);
1525
1526                                 i_RegValue = z8536_read(dev,
1527                                         APCI1500_RW_PORT_A_INTERRUPT_CONTROL);
1528
1529                                 i_InputChannel = 1 + (i_RegValue >> 1);
1530
1531                         } else {
1532                                 i_InputChannel = 0;
1533                         }
1534                 }
1535
1536                 i_RegValue = z8536_read(dev,
1537                                         APCI1500_RW_PORT_B_COMMAND_AND_STATUS);
1538                 if ((i_RegValue & 0x60) == 0x60) {
1539                         /* Deletes the interrupt of port B */
1540                         i_RegValue = (i_RegValue & 0x0F) | 0x20;
1541                         z8536_write(dev, i_RegValue,
1542                                     APCI1500_RW_PORT_B_COMMAND_AND_STATUS);
1543                         /* Reads port B */
1544                         i_RegValue = inb(devpriv->iobase +
1545                                          APCI1500_Z8536_PORTB_REG);
1546
1547                         i_RegValue = i_RegValue & 0xC0;
1548                         /* Tests if this is an external error */
1549
1550                         if (i_RegValue) {
1551                                 /* Disable the interrupt */
1552                                 /* Selects the command and status register of port B */
1553                                 outl(0x0, devpriv->i_IobaseAmcc + 0x38);
1554
1555                                 if (i_RegValue & 0x80) {
1556                                         i_InterruptMask =
1557                                                 i_InterruptMask | 0x40;
1558                                 }
1559
1560                                 if (i_RegValue & 0x40) {
1561                                         i_InterruptMask =
1562                                                 i_InterruptMask | 0x80;
1563                                 }
1564                         } else {
1565                                 i_InterruptMask = i_InterruptMask | 2;
1566                         }
1567                 }
1568
1569                 i_RegValue = z8536_read(dev, APCI1500_RW_CPT_TMR1_CMD_STATUS);
1570                 if ((i_RegValue & 0x60) == 0x60) {
1571                         /* Deletes the interrupt of timer 1 */
1572                         i_RegValue = (i_RegValue & 0x0F) | 0x20;
1573                         z8536_write(dev, i_RegValue,
1574                                     APCI1500_RW_CPT_TMR1_CMD_STATUS);
1575                         i_InterruptMask = i_InterruptMask | 4;
1576                 }
1577
1578                 i_RegValue = z8536_read(dev, APCI1500_RW_CPT_TMR2_CMD_STATUS);
1579                 if ((i_RegValue & 0x60) == 0x60) {
1580                         /* Deletes the interrupt of timer 2 */
1581                         i_RegValue = (i_RegValue & 0x0F) | 0x20;
1582                         z8536_write(dev, i_RegValue,
1583                                     APCI1500_RW_CPT_TMR2_CMD_STATUS);
1584                         i_InterruptMask = i_InterruptMask | 8;
1585                 }
1586
1587                 i_RegValue = z8536_read(dev, APCI1500_RW_CPT_TMR3_CMD_STATUS);
1588                 if ((i_RegValue & 0x60) == 0x60) {
1589                         /* Deletes the interrupt of timer 3 */
1590                         i_RegValue = (i_RegValue & 0x0F) | 0x20;
1591                         z8536_write(dev, i_RegValue,
1592                                     APCI1500_RW_CPT_TMR3_CMD_STATUS);
1593                         if (i_CounterLogic == APCI1500_COUNTER)
1594                                 i_InterruptMask = i_InterruptMask | 0x10;
1595                         else
1596                                 i_InterruptMask = i_InterruptMask | 0x20;
1597                 }
1598
1599                 send_sig(SIGIO, devpriv->tsk_Current, 0);       /*  send signal to the sample */
1600
1601                 /* Authorizes the main interrupt on the board */
1602                 z8536_write(dev, 0xd0, APCI1500_RW_MASTER_INTERRUPT_CONTROL);
1603         } else {
1604                 dev_warn(dev->class_dev,
1605                         "Interrupt from unknown source\n");
1606
1607         }
1608
1609         return IRQ_HANDLED;
1610 }
1611
1612 static int apci1500_reset(struct comedi_device *dev)
1613 {
1614         struct apci1500_private *devpriv = dev->private;
1615
1616         i_TimerCounter1Init = 0;
1617         i_TimerCounter2Init = 0;
1618         i_WatchdogCounter3Init = 0;
1619         i_Event1Status = 0;
1620         i_Event2Status = 0;
1621         i_TimerCounterWatchdogInterrupt = 0;
1622         i_Logic = 0;
1623         i_CounterLogic = 0;
1624         i_InterruptMask = 0;
1625         i_InputChannel = 0;
1626         i_TimerCounter1Enabled = 0;
1627         i_TimerCounter2Enabled = 0;
1628         i_WatchdogCounter3Enabled = 0;
1629
1630         /* Software reset */
1631         z8536_reset(dev);
1632
1633         /* reset all the digital outputs */
1634         outw(0x0, devpriv->i_IobaseAddon + APCI1500_DIGITAL_OP);
1635
1636         /* Deactivates all interrupts */
1637         z8536_write(dev, 0x00, APCI1500_RW_MASTER_INTERRUPT_CONTROL);
1638         z8536_write(dev, 0x00, APCI1500_RW_PORT_A_COMMAND_AND_STATUS);
1639         z8536_write(dev, 0x00, APCI1500_RW_PORT_B_COMMAND_AND_STATUS);
1640         z8536_write(dev, 0x00, APCI1500_RW_CPT_TMR1_CMD_STATUS);
1641         z8536_write(dev, 0x00, APCI1500_RW_CPT_TMR2_CMD_STATUS);
1642         z8536_write(dev, 0x00, APCI1500_RW_CPT_TMR3_CMD_STATUS);
1643
1644         return 0;
1645 }