3 comedi/drivers/adl_pci9111.c
5 Hardware driver for PCI9111 ADLink cards:
9 Copyright (C) 2002-2005 Emmanuel Pacaud <emmanuel.pacaud@univ-poitiers.fr>
11 This program is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2 of the License, or
14 (at your option) any later version.
16 This program is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
24 Description: Adlink PCI-9111HR
25 Author: Emmanuel Pacaud <emmanuel.pacaud@univ-poitiers.fr>
26 Devices: [ADLink] PCI-9111HR (adl_pci9111)
35 - ai_do_cmd mode with the following sources:
38 - scan_begin_src TRIG_FOLLOW TRIG_TIMER TRIG_EXT
39 - convert_src TRIG_TIMER TRIG_EXT
40 - scan_end_src TRIG_COUNT
41 - stop_src TRIG_COUNT TRIG_NONE
43 The scanned channels must be consecutive and start from 0. They must
44 all have the same range and aref.
46 Configuration options: not applicable, uses PCI auto config
52 2005/02/17 Extend AI streaming capabilities. Now, scan_begin_arg can be
53 a multiple of chanlist_len*convert_arg.
54 2002/02/19 Fixed the two's complement conversion in pci9111_(hr_)ai_get_data.
55 2002/02/18 Added external trigger support for analog input.
59 - Really test implemented functionality.
60 - Add support for the PCI-9111DG with a probe routine to identify
61 the card type (perhaps with the help of the channel number readback
62 of the A/D Data register).
63 - Add external multiplexer support.
67 #include <linux/module.h>
68 #include <linux/pci.h>
69 #include <linux/delay.h>
70 #include <linux/interrupt.h>
72 #include "../comedidev.h"
76 #include "comedi_fc.h"
78 #define PCI9111_DRIVER_NAME "adl_pci9111"
79 #define PCI9111_HR_DEVICE_ID 0x9111
81 #define PCI9111_FIFO_HALF_SIZE 512
83 #define PCI9111_AI_ACQUISITION_PERIOD_MIN_NS 10000
85 #define PCI9111_RANGE_SETTING_DELAY 10
86 #define PCI9111_AI_INSTANT_READ_UDELAY_US 2
89 * IO address map and bit defines
91 #define PCI9111_AI_FIFO_REG 0x00
92 #define PCI9111_AO_REG 0x00
93 #define PCI9111_DIO_REG 0x02
94 #define PCI9111_EDIO_REG 0x04
95 #define PCI9111_AI_CHANNEL_REG 0x06
96 #define PCI9111_AI_RANGE_STAT_REG 0x08
97 #define PCI9111_AI_STAT_AD_BUSY (1 << 7)
98 #define PCI9111_AI_STAT_FF_FF (1 << 6)
99 #define PCI9111_AI_STAT_FF_HF (1 << 5)
100 #define PCI9111_AI_STAT_FF_EF (1 << 4)
101 #define PCI9111_AI_RANGE_MASK (7 << 0)
102 #define PCI9111_AI_TRIG_CTRL_REG 0x0a
103 #define PCI9111_AI_TRIG_CTRL_TRGEVENT (1 << 5)
104 #define PCI9111_AI_TRIG_CTRL_POTRG (1 << 4)
105 #define PCI9111_AI_TRIG_CTRL_PTRG (1 << 3)
106 #define PCI9111_AI_TRIG_CTRL_ETIS (1 << 2)
107 #define PCI9111_AI_TRIG_CTRL_TPST (1 << 1)
108 #define PCI9111_AI_TRIG_CTRL_ASCAN (1 << 0)
109 #define PCI9111_INT_CTRL_REG 0x0c
110 #define PCI9111_INT_CTRL_ISC2 (1 << 3)
111 #define PCI9111_INT_CTRL_FFEN (1 << 2)
112 #define PCI9111_INT_CTRL_ISC1 (1 << 1)
113 #define PCI9111_INT_CTRL_ISC0 (1 << 0)
114 #define PCI9111_SOFT_TRIG_REG 0x0e
115 #define PCI9111_8254_BASE_REG 0x40
116 #define PCI9111_INT_CLR_REG 0x48
118 /* PLX 9052 Local Interrupt 1 enabled and active */
119 #define PCI9111_LI1_ACTIVE (PLX9052_INTCSR_LI1ENAB | \
120 PLX9052_INTCSR_LI1STAT)
122 /* PLX 9052 Local Interrupt 2 enabled and active */
123 #define PCI9111_LI2_ACTIVE (PLX9052_INTCSR_LI2ENAB | \
124 PLX9052_INTCSR_LI2STAT)
126 static const struct comedi_lrange pci9111_ai_range = {
136 struct pci9111_private_data {
137 unsigned long lcr_io_base;
141 unsigned int scan_delay;
142 unsigned int chunk_counter;
143 unsigned int chunk_num_samples;
150 unsigned short ai_bounce_buffer[2 * PCI9111_FIFO_HALF_SIZE];
153 static void plx9050_interrupt_control(unsigned long io_base,
155 bool LINTi1_active_high,
157 bool LINTi2_active_high,
158 bool interrupt_enable)
163 flags |= PLX9052_INTCSR_LI1ENAB;
164 if (LINTi1_active_high)
165 flags |= PLX9052_INTCSR_LI1POL;
167 flags |= PLX9052_INTCSR_LI2ENAB;
168 if (LINTi2_active_high)
169 flags |= PLX9052_INTCSR_LI2POL;
171 if (interrupt_enable)
172 flags |= PLX9052_INTCSR_PCIENAB;
174 outb(flags, io_base + PLX9052_INTCSR);
177 static void pci9111_timer_set(struct comedi_device *dev)
179 struct pci9111_private_data *dev_private = dev->private;
180 unsigned long timer_base = dev->iobase + PCI9111_8254_BASE_REG;
182 i8254_set_mode(timer_base, 1, 0, I8254_MODE0 | I8254_BINARY);
183 i8254_set_mode(timer_base, 1, 1, I8254_MODE2 | I8254_BINARY);
184 i8254_set_mode(timer_base, 1, 2, I8254_MODE2 | I8254_BINARY);
188 i8254_write(timer_base, 1, 2, dev_private->div2);
189 i8254_write(timer_base, 1, 1, dev_private->div1);
192 enum pci9111_trigger_sources {
198 static void pci9111_trigger_source_set(struct comedi_device *dev,
199 enum pci9111_trigger_sources source)
203 /* Read the current trigger mode control bits */
204 flags = inb(dev->iobase + PCI9111_AI_TRIG_CTRL_REG);
205 /* Mask off the EITS and TPST bits */
213 flags |= PCI9111_AI_TRIG_CTRL_TPST;
217 flags |= PCI9111_AI_TRIG_CTRL_ETIS;
221 outb(flags, dev->iobase + PCI9111_AI_TRIG_CTRL_REG);
224 static void pci9111_pretrigger_set(struct comedi_device *dev, bool pretrigger)
228 /* Read the current trigger mode control bits */
229 flags = inb(dev->iobase + PCI9111_AI_TRIG_CTRL_REG);
230 /* Mask off the PTRG bit */
234 flags |= PCI9111_AI_TRIG_CTRL_PTRG;
236 outb(flags, dev->iobase + PCI9111_AI_TRIG_CTRL_REG);
239 static void pci9111_autoscan_set(struct comedi_device *dev, bool autoscan)
243 /* Read the current trigger mode control bits */
244 flags = inb(dev->iobase + PCI9111_AI_TRIG_CTRL_REG);
245 /* Mask off the ASCAN bit */
249 flags |= PCI9111_AI_TRIG_CTRL_ASCAN;
251 outb(flags, dev->iobase + PCI9111_AI_TRIG_CTRL_REG);
254 enum pci9111_ISC0_sources {
256 irq_on_fifo_half_full
259 enum pci9111_ISC1_sources {
261 irq_on_external_trigger
264 static void pci9111_interrupt_source_set(struct comedi_device *dev,
265 enum pci9111_ISC0_sources irq_0_source,
266 enum pci9111_ISC1_sources irq_1_source)
270 /* Read the current interrupt control bits */
271 flags = inb(dev->iobase + PCI9111_AI_TRIG_CTRL_REG);
272 /* Shift the bits so they are compatible with the write register */
274 /* Mask off the ISCx bits */
277 /* Now set the new ISCx bits */
278 if (irq_0_source == irq_on_fifo_half_full)
279 flags |= PCI9111_INT_CTRL_ISC0;
281 if (irq_1_source == irq_on_external_trigger)
282 flags |= PCI9111_INT_CTRL_ISC1;
284 outb(flags, dev->iobase + PCI9111_INT_CTRL_REG);
287 static void pci9111_fifo_reset(struct comedi_device *dev)
289 unsigned long int_ctrl_reg = dev->iobase + PCI9111_INT_CTRL_REG;
291 /* To reset the FIFO, set FFEN sequence as 0 -> 1 -> 0 */
292 outb(0, int_ctrl_reg);
293 outb(PCI9111_INT_CTRL_FFEN, int_ctrl_reg);
294 outb(0, int_ctrl_reg);
297 static int pci9111_ai_cancel(struct comedi_device *dev,
298 struct comedi_subdevice *s)
300 struct pci9111_private_data *dev_private = dev->private;
302 /* Disable interrupts */
303 plx9050_interrupt_control(dev_private->lcr_io_base, true, true, true,
306 pci9111_trigger_source_set(dev, software);
308 pci9111_autoscan_set(dev, false);
310 pci9111_fifo_reset(dev);
315 static int pci9111_ai_check_chanlist(struct comedi_device *dev,
316 struct comedi_subdevice *s,
317 struct comedi_cmd *cmd)
319 unsigned int range0 = CR_RANGE(cmd->chanlist[0]);
320 unsigned int aref0 = CR_AREF(cmd->chanlist[0]);
323 for (i = 1; i < cmd->chanlist_len; i++) {
324 unsigned int chan = CR_CHAN(cmd->chanlist[i]);
325 unsigned int range = CR_RANGE(cmd->chanlist[i]);
326 unsigned int aref = CR_AREF(cmd->chanlist[i]);
329 dev_dbg(dev->class_dev,
330 "entries in chanlist must be consecutive channels,counting upwards from 0\n");
334 if (range != range0) {
335 dev_dbg(dev->class_dev,
336 "entries in chanlist must all have the same gain\n");
341 dev_dbg(dev->class_dev,
342 "entries in chanlist must all have the same reference\n");
350 static int pci9111_ai_do_cmd_test(struct comedi_device *dev,
351 struct comedi_subdevice *s,
352 struct comedi_cmd *cmd)
354 struct pci9111_private_data *dev_private = dev->private;
358 /* Step 1 : check if triggers are trivially valid */
360 err |= cfc_check_trigger_src(&cmd->start_src, TRIG_NOW);
361 err |= cfc_check_trigger_src(&cmd->scan_begin_src,
362 TRIG_TIMER | TRIG_FOLLOW | TRIG_EXT);
363 err |= cfc_check_trigger_src(&cmd->convert_src,
364 TRIG_TIMER | TRIG_EXT);
365 err |= cfc_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
366 err |= cfc_check_trigger_src(&cmd->stop_src,
367 TRIG_COUNT | TRIG_NONE);
372 /* Step 2a : make sure trigger sources are unique */
374 err |= cfc_check_trigger_is_unique(cmd->scan_begin_src);
375 err |= cfc_check_trigger_is_unique(cmd->convert_src);
376 err |= cfc_check_trigger_is_unique(cmd->stop_src);
378 /* Step 2b : and mutually compatible */
380 if (cmd->scan_begin_src != TRIG_FOLLOW) {
381 if (cmd->scan_begin_src != cmd->convert_src)
388 /* Step 3: check if arguments are trivially valid */
390 err |= cfc_check_trigger_arg_is(&cmd->start_arg, 0);
392 if (cmd->convert_src == TRIG_TIMER)
393 err |= cfc_check_trigger_arg_min(&cmd->convert_arg,
394 PCI9111_AI_ACQUISITION_PERIOD_MIN_NS);
396 err |= cfc_check_trigger_arg_is(&cmd->convert_arg, 0);
398 if (cmd->scan_begin_src == TRIG_TIMER)
399 err |= cfc_check_trigger_arg_min(&cmd->scan_begin_arg,
400 PCI9111_AI_ACQUISITION_PERIOD_MIN_NS);
401 else /* TRIG_FOLLOW || TRIG_EXT */
402 err |= cfc_check_trigger_arg_is(&cmd->scan_begin_arg, 0);
404 err |= cfc_check_trigger_arg_is(&cmd->scan_end_arg, cmd->chanlist_len);
406 if (cmd->stop_src == TRIG_COUNT)
407 err |= cfc_check_trigger_arg_min(&cmd->stop_arg, 1);
409 err |= cfc_check_trigger_arg_is(&cmd->stop_arg, 0);
414 /* Step 4: fix up any arguments */
416 if (cmd->convert_src == TRIG_TIMER) {
417 arg = cmd->convert_arg;
418 i8253_cascade_ns_to_timer(I8254_OSC_BASE_2MHZ,
422 err |= cfc_check_trigger_arg_is(&cmd->convert_arg, arg);
426 * There's only one timer on this card, so the scan_begin timer
427 * must be a multiple of chanlist_len*convert_arg
429 if (cmd->scan_begin_src == TRIG_TIMER) {
430 arg = cmd->chanlist_len * cmd->convert_arg;
432 if (arg < cmd->scan_begin_arg)
433 arg *= (cmd->scan_begin_arg / arg);
435 err |= cfc_check_trigger_arg_is(&cmd->scan_begin_arg, arg);
441 /* Step 5: check channel list if it exists */
442 if (cmd->chanlist && cmd->chanlist_len > 0)
443 err |= pci9111_ai_check_chanlist(dev, s, cmd);
452 static int pci9111_ai_do_cmd(struct comedi_device *dev,
453 struct comedi_subdevice *s)
455 struct pci9111_private_data *dev_private = dev->private;
456 struct comedi_cmd *cmd = &s->async->cmd;
458 /* Set channel scan limit */
459 /* PCI9111 allows only scanning from channel 0 to channel n */
460 /* TODO: handle the case of an external multiplexer */
462 if (cmd->chanlist_len > 1) {
463 outb(cmd->chanlist_len - 1,
464 dev->iobase + PCI9111_AI_CHANNEL_REG);
465 pci9111_autoscan_set(dev, true);
467 outb(CR_CHAN(cmd->chanlist[0]),
468 dev->iobase + PCI9111_AI_CHANNEL_REG);
469 pci9111_autoscan_set(dev, false);
473 /* This is the same gain on every channel */
475 outb(CR_RANGE(cmd->chanlist[0]) & PCI9111_AI_RANGE_MASK,
476 dev->iobase + PCI9111_AI_RANGE_STAT_REG);
479 if (cmd->stop_src == TRIG_COUNT)
480 dev_private->stop_counter = cmd->stop_arg * cmd->chanlist_len;
482 dev_private->stop_counter = 0;
484 /* Set timer pacer */
485 dev_private->scan_delay = 0;
486 if (cmd->convert_src == TRIG_TIMER) {
487 pci9111_trigger_source_set(dev, software);
488 pci9111_timer_set(dev);
489 pci9111_fifo_reset(dev);
490 pci9111_interrupt_source_set(dev, irq_on_fifo_half_full,
492 pci9111_trigger_source_set(dev, timer_pacer);
493 plx9050_interrupt_control(dev_private->lcr_io_base, true, true,
496 if (cmd->scan_begin_src == TRIG_TIMER) {
497 dev_private->scan_delay = (cmd->scan_begin_arg /
498 (cmd->convert_arg * cmd->chanlist_len)) - 1;
500 } else { /* TRIG_EXT */
501 pci9111_trigger_source_set(dev, external);
502 pci9111_fifo_reset(dev);
503 pci9111_interrupt_source_set(dev, irq_on_fifo_half_full,
505 plx9050_interrupt_control(dev_private->lcr_io_base, true, true,
510 dev_private->stop_counter *= (1 + dev_private->scan_delay);
511 dev_private->chunk_counter = 0;
512 dev_private->chunk_num_samples = cmd->chanlist_len *
513 (1 + dev_private->scan_delay);
518 static void pci9111_ai_munge(struct comedi_device *dev,
519 struct comedi_subdevice *s, void *data,
520 unsigned int num_bytes,
521 unsigned int start_chan_index)
523 unsigned short *array = data;
524 unsigned int maxdata = s->maxdata;
525 unsigned int invert = (maxdata + 1) >> 1;
526 unsigned int shift = (maxdata == 0xffff) ? 0 : 4;
527 unsigned int num_samples = num_bytes / sizeof(short);
530 for (i = 0; i < num_samples; i++)
531 array[i] = ((array[i] >> shift) & maxdata) ^ invert;
534 static void pci9111_handle_fifo_half_full(struct comedi_device *dev,
535 struct comedi_subdevice *s)
537 struct pci9111_private_data *devpriv = dev->private;
538 struct comedi_cmd *cmd = &s->async->cmd;
539 unsigned int total = 0;
540 unsigned int samples;
542 if (cmd->stop_src == TRIG_COUNT &&
543 PCI9111_FIFO_HALF_SIZE > devpriv->stop_counter)
544 samples = devpriv->stop_counter;
546 samples = PCI9111_FIFO_HALF_SIZE;
548 insw(dev->iobase + PCI9111_AI_FIFO_REG,
549 devpriv->ai_bounce_buffer, samples);
551 if (devpriv->scan_delay < 1) {
552 total = cfc_write_array_to_buffer(s,
553 devpriv->ai_bounce_buffer,
554 samples * sizeof(short));
556 unsigned int pos = 0;
557 unsigned int to_read;
559 while (pos < samples) {
560 if (devpriv->chunk_counter < cmd->chanlist_len) {
561 to_read = cmd->chanlist_len -
562 devpriv->chunk_counter;
564 if (to_read > samples - pos)
565 to_read = samples - pos;
567 total += cfc_write_array_to_buffer(s,
568 devpriv->ai_bounce_buffer + pos,
569 to_read * sizeof(short));
571 to_read = devpriv->chunk_num_samples -
572 devpriv->chunk_counter;
574 if (to_read > samples - pos)
575 to_read = samples - pos;
577 total += to_read * sizeof(short);
581 devpriv->chunk_counter += to_read;
583 if (devpriv->chunk_counter >=
584 devpriv->chunk_num_samples)
585 devpriv->chunk_counter = 0;
589 devpriv->stop_counter -= total / sizeof(short);
592 static irqreturn_t pci9111_interrupt(int irq, void *p_device)
594 struct comedi_device *dev = p_device;
595 struct pci9111_private_data *dev_private = dev->private;
596 struct comedi_subdevice *s = dev->read_subdev;
597 struct comedi_async *async;
598 struct comedi_cmd *cmd;
600 unsigned long irq_flags;
601 unsigned char intcsr;
603 if (!dev->attached) {
604 /* Ignore interrupt before device fully attached. */
605 /* Might not even have allocated subdevices yet! */
612 spin_lock_irqsave(&dev->spinlock, irq_flags);
614 /* Check if we are source of interrupt */
615 intcsr = inb(dev_private->lcr_io_base + PLX9052_INTCSR);
616 if (!(((intcsr & PLX9052_INTCSR_PCIENAB) != 0) &&
617 (((intcsr & PCI9111_LI1_ACTIVE) == PCI9111_LI1_ACTIVE) ||
618 ((intcsr & PCI9111_LI2_ACTIVE) == PCI9111_LI2_ACTIVE)))) {
619 /* Not the source of the interrupt. */
620 /* (N.B. not using PLX9052_INTCSR_SOFTINT) */
621 spin_unlock_irqrestore(&dev->spinlock, irq_flags);
625 if ((intcsr & PCI9111_LI1_ACTIVE) == PCI9111_LI1_ACTIVE) {
626 /* Interrupt comes from fifo_half-full signal */
628 status = inb(dev->iobase + PCI9111_AI_RANGE_STAT_REG);
630 /* '0' means FIFO is full, data may have been lost */
631 if (!(status & PCI9111_AI_STAT_FF_FF)) {
632 spin_unlock_irqrestore(&dev->spinlock, irq_flags);
633 comedi_error(dev, PCI9111_DRIVER_NAME " fifo overflow");
634 outb(0, dev->iobase + PCI9111_INT_CLR_REG);
635 async->events |= COMEDI_CB_ERROR | COMEDI_CB_EOA;
636 cfc_handle_events(dev, s);
641 /* '0' means FIFO is half-full */
642 if (!(status & PCI9111_AI_STAT_FF_HF))
643 pci9111_handle_fifo_half_full(dev, s);
646 if (cmd->stop_src == TRIG_COUNT && dev_private->stop_counter == 0)
647 async->events |= COMEDI_CB_EOA;
649 outb(0, dev->iobase + PCI9111_INT_CLR_REG);
651 spin_unlock_irqrestore(&dev->spinlock, irq_flags);
653 cfc_handle_events(dev, s);
658 static int pci9111_ai_eoc(struct comedi_device *dev,
659 struct comedi_subdevice *s,
660 struct comedi_insn *insn,
661 unsigned long context)
665 status = inb(dev->iobase + PCI9111_AI_RANGE_STAT_REG);
666 if (status & PCI9111_AI_STAT_FF_EF)
671 static int pci9111_ai_insn_read(struct comedi_device *dev,
672 struct comedi_subdevice *s,
673 struct comedi_insn *insn, unsigned int *data)
675 unsigned int chan = CR_CHAN(insn->chanspec);
676 unsigned int range = CR_RANGE(insn->chanspec);
677 unsigned int maxdata = s->maxdata;
678 unsigned int invert = (maxdata + 1) >> 1;
679 unsigned int shift = (maxdata == 0xffff) ? 0 : 4;
684 outb(chan, dev->iobase + PCI9111_AI_CHANNEL_REG);
686 status = inb(dev->iobase + PCI9111_AI_RANGE_STAT_REG);
687 if ((status & PCI9111_AI_RANGE_MASK) != range) {
688 outb(range & PCI9111_AI_RANGE_MASK,
689 dev->iobase + PCI9111_AI_RANGE_STAT_REG);
692 pci9111_fifo_reset(dev);
694 for (i = 0; i < insn->n; i++) {
695 /* Generate a software trigger */
696 outb(0, dev->iobase + PCI9111_SOFT_TRIG_REG);
698 ret = comedi_timeout(dev, s, insn, pci9111_ai_eoc, 0);
700 pci9111_fifo_reset(dev);
704 data[i] = inw(dev->iobase + PCI9111_AI_FIFO_REG);
705 data[i] = ((data[i] >> shift) & maxdata) ^ invert;
711 static int pci9111_ao_insn_write(struct comedi_device *dev,
712 struct comedi_subdevice *s,
713 struct comedi_insn *insn,
716 struct pci9111_private_data *dev_private = dev->private;
717 unsigned int val = 0;
720 for (i = 0; i < insn->n; i++) {
722 outw(val, dev->iobase + PCI9111_AO_REG);
724 dev_private->ao_readback = val;
729 static int pci9111_ao_insn_read(struct comedi_device *dev,
730 struct comedi_subdevice *s,
731 struct comedi_insn *insn,
734 struct pci9111_private_data *dev_private = dev->private;
737 for (i = 0; i < insn->n; i++)
738 data[i] = dev_private->ao_readback;
743 static int pci9111_di_insn_bits(struct comedi_device *dev,
744 struct comedi_subdevice *s,
745 struct comedi_insn *insn,
748 data[1] = inw(dev->iobase + PCI9111_DIO_REG);
753 static int pci9111_do_insn_bits(struct comedi_device *dev,
754 struct comedi_subdevice *s,
755 struct comedi_insn *insn,
758 if (comedi_dio_update_state(s, data))
759 outw(s->state, dev->iobase + PCI9111_DIO_REG);
766 static int pci9111_reset(struct comedi_device *dev)
768 struct pci9111_private_data *dev_private = dev->private;
770 /* Set trigger source to software */
771 plx9050_interrupt_control(dev_private->lcr_io_base, true, true, true,
774 pci9111_trigger_source_set(dev, software);
775 pci9111_pretrigger_set(dev, false);
776 pci9111_autoscan_set(dev, false);
778 /* Reset 8254 chip */
779 dev_private->div1 = 0;
780 dev_private->div2 = 0;
781 pci9111_timer_set(dev);
786 static int pci9111_auto_attach(struct comedi_device *dev,
787 unsigned long context_unused)
789 struct pci_dev *pcidev = comedi_to_pci_dev(dev);
790 struct pci9111_private_data *dev_private;
791 struct comedi_subdevice *s;
794 dev_private = comedi_alloc_devpriv(dev, sizeof(*dev_private));
798 ret = comedi_pci_enable(dev);
801 dev_private->lcr_io_base = pci_resource_start(pcidev, 1);
802 dev->iobase = pci_resource_start(pcidev, 2);
807 ret = request_irq(pcidev->irq, pci9111_interrupt,
808 IRQF_SHARED, dev->board_name, dev);
810 dev->irq = pcidev->irq;
813 ret = comedi_alloc_subdevices(dev, 4);
817 s = &dev->subdevices[0];
818 s->type = COMEDI_SUBD_AI;
819 s->subdev_flags = SDF_READABLE | SDF_COMMON;
822 s->range_table = &pci9111_ai_range;
823 s->insn_read = pci9111_ai_insn_read;
825 dev->read_subdev = s;
826 s->subdev_flags |= SDF_CMD_READ;
827 s->len_chanlist = s->n_chan;
828 s->do_cmdtest = pci9111_ai_do_cmd_test;
829 s->do_cmd = pci9111_ai_do_cmd;
830 s->cancel = pci9111_ai_cancel;
831 s->munge = pci9111_ai_munge;
834 s = &dev->subdevices[1];
835 s->type = COMEDI_SUBD_AO;
836 s->subdev_flags = SDF_WRITABLE | SDF_COMMON;
840 s->range_table = &range_bipolar10;
841 s->insn_write = pci9111_ao_insn_write;
842 s->insn_read = pci9111_ao_insn_read;
844 s = &dev->subdevices[2];
845 s->type = COMEDI_SUBD_DI;
846 s->subdev_flags = SDF_READABLE;
849 s->range_table = &range_digital;
850 s->insn_bits = pci9111_di_insn_bits;
852 s = &dev->subdevices[3];
853 s->type = COMEDI_SUBD_DO;
854 s->subdev_flags = SDF_READABLE | SDF_WRITABLE;
857 s->range_table = &range_digital;
858 s->insn_bits = pci9111_do_insn_bits;
863 static void pci9111_detach(struct comedi_device *dev)
868 free_irq(dev->irq, dev);
869 comedi_pci_disable(dev);
872 static struct comedi_driver adl_pci9111_driver = {
873 .driver_name = "adl_pci9111",
874 .module = THIS_MODULE,
875 .auto_attach = pci9111_auto_attach,
876 .detach = pci9111_detach,
879 static int pci9111_pci_probe(struct pci_dev *dev,
880 const struct pci_device_id *id)
882 return comedi_pci_auto_config(dev, &adl_pci9111_driver,
886 static const struct pci_device_id pci9111_pci_table[] = {
887 { PCI_DEVICE(PCI_VENDOR_ID_ADLINK, PCI9111_HR_DEVICE_ID) },
888 /* { PCI_DEVICE(PCI_VENDOR_ID_ADLINK, PCI9111_HG_DEVICE_ID) }, */
891 MODULE_DEVICE_TABLE(pci, pci9111_pci_table);
893 static struct pci_driver adl_pci9111_pci_driver = {
894 .name = "adl_pci9111",
895 .id_table = pci9111_pci_table,
896 .probe = pci9111_pci_probe,
897 .remove = comedi_pci_auto_unconfig,
899 module_comedi_pci_driver(adl_pci9111_driver, adl_pci9111_pci_driver);
901 MODULE_AUTHOR("Comedi http://www.comedi.org");
902 MODULE_DESCRIPTION("Comedi low-level driver");
903 MODULE_LICENSE("GPL");